mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32_hal_legacy.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:: <>
Date:: Fri Sep 02 15:07:44 2016 +0100
Revision:: 144:ef7eb2e8f9f7
Parent:: 0:9b334a45a8ff

This updates the lib to the mbed lib v125

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32_hal_legacy.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.4.0
<>	144:ef7eb2e8f9f7	6	* @date 27-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief This file contains aliases definition for the STM32Cube HAL constants
<>	144:ef7eb2e8f9f7	8	* macros and functions maintained for legacy purpose.
<>	144:ef7eb2e8f9f7	9	******************************************************************************
<>	144:ef7eb2e8f9f7	10	* @attention
<>	144:ef7eb2e8f9f7	11	*
<>	144:ef7eb2e8f9f7	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	15	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	16	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	17	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	19	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	20	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	22	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	23	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	24	*
<>	144:ef7eb2e8f9f7	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	35	*
<>	144:ef7eb2e8f9f7	36	******************************************************************************
<>	144:ef7eb2e8f9f7	37	*/
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	40	#ifndef __STM32_HAL_LEGACY
<>	144:ef7eb2e8f9f7	41	#define __STM32_HAL_LEGACY
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	44	extern "C" {
<>	144:ef7eb2e8f9f7	45	#endif
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	48	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	49	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54	#define AES_FLAG_RDERR CRYP_FLAG_RDERR
<>	144:ef7eb2e8f9f7	55	#define AES_FLAG_WRERR CRYP_FLAG_WRERR
<>	144:ef7eb2e8f9f7	56	#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
<>	144:ef7eb2e8f9f7	57	#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
<>	144:ef7eb2e8f9f7	58	#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
<>	144:ef7eb2e8f9f7	59
<>	144:ef7eb2e8f9f7	60	/**
<>	144:ef7eb2e8f9f7	61	* @}
<>	144:ef7eb2e8f9f7	62	*/
<>	144:ef7eb2e8f9f7	63
<>	144:ef7eb2e8f9f7	64	/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	65	* @{
<>	144:ef7eb2e8f9f7	66	*/
<>	144:ef7eb2e8f9f7	67	#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
<>	144:ef7eb2e8f9f7	68	#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
<>	144:ef7eb2e8f9f7	69	#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
<>	144:ef7eb2e8f9f7	70	#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
<>	144:ef7eb2e8f9f7	71	#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
<>	144:ef7eb2e8f9f7	72	#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
<>	144:ef7eb2e8f9f7	73	#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
<>	144:ef7eb2e8f9f7	74	#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
<>	144:ef7eb2e8f9f7	75	#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
<>	144:ef7eb2e8f9f7	76	#define REGULAR_GROUP ADC_REGULAR_GROUP
<>	144:ef7eb2e8f9f7	77	#define INJECTED_GROUP ADC_INJECTED_GROUP
<>	144:ef7eb2e8f9f7	78	#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
<>	144:ef7eb2e8f9f7	79	#define AWD_EVENT ADC_AWD_EVENT
<>	144:ef7eb2e8f9f7	80	#define AWD1_EVENT ADC_AWD1_EVENT
<>	144:ef7eb2e8f9f7	81	#define AWD2_EVENT ADC_AWD2_EVENT
<>	144:ef7eb2e8f9f7	82	#define AWD3_EVENT ADC_AWD3_EVENT
<>	144:ef7eb2e8f9f7	83	#define OVR_EVENT ADC_OVR_EVENT
<>	144:ef7eb2e8f9f7	84	#define JQOVF_EVENT ADC_JQOVF_EVENT
<>	144:ef7eb2e8f9f7	85	#define ALL_CHANNELS ADC_ALL_CHANNELS
<>	144:ef7eb2e8f9f7	86	#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
<>	144:ef7eb2e8f9f7	87	#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
<>	144:ef7eb2e8f9f7	88	#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
<>	144:ef7eb2e8f9f7	89	#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
<>	144:ef7eb2e8f9f7	90	#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
<>	144:ef7eb2e8f9f7	91	#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
<>	144:ef7eb2e8f9f7	92	#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
<>	144:ef7eb2e8f9f7	93	#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
<>	144:ef7eb2e8f9f7	94	#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
<>	144:ef7eb2e8f9f7	95	#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
<>	144:ef7eb2e8f9f7	96	#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
<>	144:ef7eb2e8f9f7	97	#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
<>	144:ef7eb2e8f9f7	98	#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
<>	144:ef7eb2e8f9f7	99	#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
<>	144:ef7eb2e8f9f7	100	#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
<>	144:ef7eb2e8f9f7	101	#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
<>	144:ef7eb2e8f9f7	102	#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
<>	144:ef7eb2e8f9f7	103	#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
<>	144:ef7eb2e8f9f7	104	#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
<>	144:ef7eb2e8f9f7	105	#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
<>	144:ef7eb2e8f9f7	106	#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
<>	144:ef7eb2e8f9f7	109	#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
<>	144:ef7eb2e8f9f7	110	#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
<>	144:ef7eb2e8f9f7	111	#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
<>	144:ef7eb2e8f9f7	112	#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
<>	144:ef7eb2e8f9f7	113	#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
<>	144:ef7eb2e8f9f7	114	#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
<>	144:ef7eb2e8f9f7	115	/**
<>	144:ef7eb2e8f9f7	116	* @}
<>	144:ef7eb2e8f9f7	117	*/
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	120	* @{
<>	144:ef7eb2e8f9f7	121	*/
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	/**
<>	144:ef7eb2e8f9f7	126	* @}
<>	144:ef7eb2e8f9f7	127	*/
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	130	* @{
<>	144:ef7eb2e8f9f7	131	*/
<>	144:ef7eb2e8f9f7	132	#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
<>	144:ef7eb2e8f9f7	133	#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
<>	144:ef7eb2e8f9f7	134	#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
<>	144:ef7eb2e8f9f7	135	#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
<>	144:ef7eb2e8f9f7	136	#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
<>	144:ef7eb2e8f9f7	137	#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
<>	144:ef7eb2e8f9f7	138	#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
<>	144:ef7eb2e8f9f7	139	#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
<>	144:ef7eb2e8f9f7	140	#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
<>	144:ef7eb2e8f9f7	141	#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
<>	144:ef7eb2e8f9f7	142	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	143	#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
<>	144:ef7eb2e8f9f7	144	#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
<>	144:ef7eb2e8f9f7	145	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	146
<>	144:ef7eb2e8f9f7	147	#if defined(STM32L0) \|\| defined(STM32L4)
<>	144:ef7eb2e8f9f7	148	#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
<>	144:ef7eb2e8f9f7	151	#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
<>	144:ef7eb2e8f9f7	152	#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
<>	144:ef7eb2e8f9f7	153	#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
<>	144:ef7eb2e8f9f7	154	#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
<>	144:ef7eb2e8f9f7	155	#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
<>	144:ef7eb2e8f9f7	158	#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
<>	144:ef7eb2e8f9f7	159	#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
<>	144:ef7eb2e8f9f7	160	#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
<>	144:ef7eb2e8f9f7	161	#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
<>	144:ef7eb2e8f9f7	162	#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
<>	144:ef7eb2e8f9f7	163	#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
<>	144:ef7eb2e8f9f7	164	#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
<>	144:ef7eb2e8f9f7	165	#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
<>	144:ef7eb2e8f9f7	166	#if defined(STM32L0)
<>	144:ef7eb2e8f9f7	167	/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
<>	144:ef7eb2e8f9f7	168	/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
<>	144:ef7eb2e8f9f7	169	/* to the second dedicated IO (only for COMP2). */
<>	144:ef7eb2e8f9f7	170	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
<>	144:ef7eb2e8f9f7	171	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
<>	144:ef7eb2e8f9f7	172	#else
<>	144:ef7eb2e8f9f7	173	#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
<>	144:ef7eb2e8f9f7	174	#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
<>	144:ef7eb2e8f9f7	175	#endif
<>	144:ef7eb2e8f9f7	176	#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
<>	144:ef7eb2e8f9f7	177	#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
<>	144:ef7eb2e8f9f7	180	#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
<>	144:ef7eb2e8f9f7	183	/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
<>	144:ef7eb2e8f9f7	184	#if defined(COMP_CSR_LOCK)
<>	144:ef7eb2e8f9f7	185	#define COMP_FLAG_LOCK COMP_CSR_LOCK
<>	144:ef7eb2e8f9f7	186	#elif defined(COMP_CSR_COMP1LOCK)
<>	144:ef7eb2e8f9f7	187	#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
<>	144:ef7eb2e8f9f7	188	#elif defined(COMP_CSR_COMPxLOCK)
<>	144:ef7eb2e8f9f7	189	#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
<>	144:ef7eb2e8f9f7	190	#endif
<>	144:ef7eb2e8f9f7	191
<>	144:ef7eb2e8f9f7	192	#if defined(STM32L4)
<>	144:ef7eb2e8f9f7	193	#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
<>	144:ef7eb2e8f9f7	194	#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
<>	144:ef7eb2e8f9f7	195	#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
<>	144:ef7eb2e8f9f7	196	#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
<>	144:ef7eb2e8f9f7	197	#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
<>	144:ef7eb2e8f9f7	198	#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
<>	144:ef7eb2e8f9f7	199	#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
<>	144:ef7eb2e8f9f7	200	#endif
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	#if defined(STM32L0)
<>	144:ef7eb2e8f9f7	203	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
<>	144:ef7eb2e8f9f7	204	#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
<>	144:ef7eb2e8f9f7	205	#else
<>	144:ef7eb2e8f9f7	206	#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
<>	144:ef7eb2e8f9f7	207	#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
<>	144:ef7eb2e8f9f7	208	#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
<>	144:ef7eb2e8f9f7	209	#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
<>	144:ef7eb2e8f9f7	210	#endif
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	#endif
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @}
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	218	* @{
<>	144:ef7eb2e8f9f7	219	*/
<>	144:ef7eb2e8f9f7	220	#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
<>	144:ef7eb2e8f9f7	221	/**
<>	144:ef7eb2e8f9f7	222	* @}
<>	144:ef7eb2e8f9f7	223	*/
<>	144:ef7eb2e8f9f7	224
<>	144:ef7eb2e8f9f7	225	/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	226	* @{
<>	144:ef7eb2e8f9f7	227	*/
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
<>	144:ef7eb2e8f9f7	230	#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/**
<>	144:ef7eb2e8f9f7	233	* @}
<>	144:ef7eb2e8f9f7	234	*/
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	237	* @{
<>	144:ef7eb2e8f9f7	238	*/
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	#define DAC1_CHANNEL_1 DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	241	#define DAC1_CHANNEL_2 DAC_CHANNEL_2
<>	144:ef7eb2e8f9f7	242	#define DAC2_CHANNEL_1 DAC_CHANNEL_1
<>	144:ef7eb2e8f9f7	243	#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
<>	144:ef7eb2e8f9f7	244	#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
<>	144:ef7eb2e8f9f7	245	#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
<>	144:ef7eb2e8f9f7	246	#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
<>	144:ef7eb2e8f9f7	247	#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
<>	144:ef7eb2e8f9f7	248	#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
<>	144:ef7eb2e8f9f7	249
<>	144:ef7eb2e8f9f7	250	/**
<>	144:ef7eb2e8f9f7	251	* @}
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	255	* @{
<>	144:ef7eb2e8f9f7	256	*/
<>	144:ef7eb2e8f9f7	257	#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
<>	144:ef7eb2e8f9f7	258	#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
<>	144:ef7eb2e8f9f7	259	#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
<>	144:ef7eb2e8f9f7	260	#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
<>	144:ef7eb2e8f9f7	261	#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
<>	144:ef7eb2e8f9f7	262	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<>	144:ef7eb2e8f9f7	263	#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
<>	144:ef7eb2e8f9f7	264	#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
<>	144:ef7eb2e8f9f7	265	#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
<>	144:ef7eb2e8f9f7	266	#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
<>	144:ef7eb2e8f9f7	267	#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
<>	144:ef7eb2e8f9f7	268	#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
<>	144:ef7eb2e8f9f7	269	#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
<>	144:ef7eb2e8f9f7	270	#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
<>	144:ef7eb2e8f9f7	271	#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	#define IS_HAL_REMAPDMA IS_DMA_REMAP
<>	144:ef7eb2e8f9f7	274	#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
<>	144:ef7eb2e8f9f7	275	#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277
<>	144:ef7eb2e8f9f7	278
<>	144:ef7eb2e8f9f7	279	/**
<>	144:ef7eb2e8f9f7	280	* @}
<>	144:ef7eb2e8f9f7	281	*/
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	284	* @{
<>	144:ef7eb2e8f9f7	285	*/
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287	#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
<>	144:ef7eb2e8f9f7	288	#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
<>	144:ef7eb2e8f9f7	289	#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
<>	144:ef7eb2e8f9f7	290	#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
<>	144:ef7eb2e8f9f7	291	#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
<>	144:ef7eb2e8f9f7	292	#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
<>	144:ef7eb2e8f9f7	293	#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
<>	144:ef7eb2e8f9f7	294	#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
<>	144:ef7eb2e8f9f7	295	#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
<>	144:ef7eb2e8f9f7	296	#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
<>	144:ef7eb2e8f9f7	297	#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
<>	144:ef7eb2e8f9f7	298	#define OBEX_PCROP OPTIONBYTE_PCROP
<>	144:ef7eb2e8f9f7	299	#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
<>	144:ef7eb2e8f9f7	300	#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
<>	144:ef7eb2e8f9f7	301	#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
<>	144:ef7eb2e8f9f7	302	#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
<>	144:ef7eb2e8f9f7	303	#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
<>	144:ef7eb2e8f9f7	304	#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
<>	144:ef7eb2e8f9f7	305	#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
<>	144:ef7eb2e8f9f7	306	#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
<>	144:ef7eb2e8f9f7	307	#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
<>	144:ef7eb2e8f9f7	308	#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
<>	144:ef7eb2e8f9f7	309	#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
<>	144:ef7eb2e8f9f7	310	#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
<>	144:ef7eb2e8f9f7	311	#define PAGESIZE FLASH_PAGE_SIZE
<>	144:ef7eb2e8f9f7	312	#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
<>	144:ef7eb2e8f9f7	313	#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
<>	144:ef7eb2e8f9f7	314	#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
<>	144:ef7eb2e8f9f7	315	#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
<>	144:ef7eb2e8f9f7	316	#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
<>	144:ef7eb2e8f9f7	317	#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
<>	144:ef7eb2e8f9f7	318	#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
<>	144:ef7eb2e8f9f7	319	#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
<>	144:ef7eb2e8f9f7	320	#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
<>	144:ef7eb2e8f9f7	321	#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
<>	144:ef7eb2e8f9f7	322	#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
<>	144:ef7eb2e8f9f7	323	#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
<>	144:ef7eb2e8f9f7	324	#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
<>	144:ef7eb2e8f9f7	325	#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
<>	144:ef7eb2e8f9f7	326	#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
<>	144:ef7eb2e8f9f7	327	#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
<>	144:ef7eb2e8f9f7	328	#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
<>	144:ef7eb2e8f9f7	329	#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
<>	144:ef7eb2e8f9f7	330	#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
<>	144:ef7eb2e8f9f7	331	#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
<>	144:ef7eb2e8f9f7	332	#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
<>	144:ef7eb2e8f9f7	333	#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
<>	144:ef7eb2e8f9f7	334	#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
<>	144:ef7eb2e8f9f7	335	#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
<>	144:ef7eb2e8f9f7	336	#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
<>	144:ef7eb2e8f9f7	337	#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
<>	144:ef7eb2e8f9f7	338	#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
<>	144:ef7eb2e8f9f7	339	#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
<>	144:ef7eb2e8f9f7	340	#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
<>	144:ef7eb2e8f9f7	341	#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
<>	144:ef7eb2e8f9f7	342	#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
<>	144:ef7eb2e8f9f7	343	#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
<>	144:ef7eb2e8f9f7	344	#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
<>	144:ef7eb2e8f9f7	345	#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
<>	144:ef7eb2e8f9f7	346	#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
<>	144:ef7eb2e8f9f7	347	#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
<>	144:ef7eb2e8f9f7	348	#define OB_WDG_SW OB_IWDG_SW
<>	144:ef7eb2e8f9f7	349	#define OB_WDG_HW OB_IWDG_HW
<>	144:ef7eb2e8f9f7	350	#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
<>	144:ef7eb2e8f9f7	351	#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
<>	144:ef7eb2e8f9f7	352	#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
<>	144:ef7eb2e8f9f7	353	#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
<>	144:ef7eb2e8f9f7	354	#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
<>	144:ef7eb2e8f9f7	355	#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
<>	144:ef7eb2e8f9f7	356	#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
<>	144:ef7eb2e8f9f7	357	#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
<>	144:ef7eb2e8f9f7	358	/**
<>	144:ef7eb2e8f9f7	359	* @}
<>	144:ef7eb2e8f9f7	360	*/
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	363	* @{
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
<>	144:ef7eb2e8f9f7	367	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
<>	144:ef7eb2e8f9f7	368	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
<>	144:ef7eb2e8f9f7	369	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
<>	144:ef7eb2e8f9f7	370	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
<>	144:ef7eb2e8f9f7	371	#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
<>	144:ef7eb2e8f9f7	372	#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
<>	144:ef7eb2e8f9f7	373	#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
<>	144:ef7eb2e8f9f7	374	#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
<>	144:ef7eb2e8f9f7	375	/**
<>	144:ef7eb2e8f9f7	376	* @}
<>	144:ef7eb2e8f9f7	377	*/
<>	144:ef7eb2e8f9f7	378
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
<>	144:ef7eb2e8f9f7	381	* @{
<>	144:ef7eb2e8f9f7	382	*/
<>	144:ef7eb2e8f9f7	383	#if defined(STM32L4) \|\| defined(STM32F7)
<>	144:ef7eb2e8f9f7	384	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
<>	144:ef7eb2e8f9f7	385	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
<>	144:ef7eb2e8f9f7	386	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
<>	144:ef7eb2e8f9f7	387	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
<>	144:ef7eb2e8f9f7	388	#else
<>	144:ef7eb2e8f9f7	389	#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
<>	144:ef7eb2e8f9f7	390	#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
<>	144:ef7eb2e8f9f7	391	#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
<>	144:ef7eb2e8f9f7	392	#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
<>	144:ef7eb2e8f9f7	393	#endif
<>	144:ef7eb2e8f9f7	394	/**
<>	144:ef7eb2e8f9f7	395	* @}
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
<>	144:ef7eb2e8f9f7	403	#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
<>	144:ef7eb2e8f9f7	404	/**
<>	144:ef7eb2e8f9f7	405	* @}
<>	144:ef7eb2e8f9f7	406	*/
<>	144:ef7eb2e8f9f7	407
<>	144:ef7eb2e8f9f7	408	/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	409	* @{
<>	144:ef7eb2e8f9f7	410	*/
<>	144:ef7eb2e8f9f7	411	#define GET_GPIO_SOURCE GPIO_GET_INDEX
<>	144:ef7eb2e8f9f7	412	#define GET_GPIO_INDEX GPIO_GET_INDEX
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	#if defined(STM32F4)
<>	144:ef7eb2e8f9f7	415	#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
<>	144:ef7eb2e8f9f7	416	#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
<>	144:ef7eb2e8f9f7	417	#endif
<>	144:ef7eb2e8f9f7	418
<>	144:ef7eb2e8f9f7	419	#if defined(STM32F7)
<>	144:ef7eb2e8f9f7	420	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<>	144:ef7eb2e8f9f7	421	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<>	144:ef7eb2e8f9f7	422	#endif
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	#if defined(STM32L4)
<>	144:ef7eb2e8f9f7	425	#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
<>	144:ef7eb2e8f9f7	426	#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
<>	144:ef7eb2e8f9f7	427	#endif
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
<>	144:ef7eb2e8f9f7	430	#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
<>	144:ef7eb2e8f9f7	431	#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
<>	144:ef7eb2e8f9f7	432
<>	144:ef7eb2e8f9f7	433	#if defined(STM32L0) \|\| defined(STM32L4) \|\| defined(STM32F4) \|\| defined(STM32F2) \|\| defined(STM32F7)
<>	144:ef7eb2e8f9f7	434	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<>	144:ef7eb2e8f9f7	435	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<>	144:ef7eb2e8f9f7	436	#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
<>	144:ef7eb2e8f9f7	437	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<>	144:ef7eb2e8f9f7	438	#endif /* STM32L0 \|\| STM32L4 \|\| STM32F4 \|\| STM32F2 \|\| STM32F7 */
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	#if defined(STM32L1)
<>	144:ef7eb2e8f9f7	441	#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
<>	144:ef7eb2e8f9f7	442	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
<>	144:ef7eb2e8f9f7	443	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
<>	144:ef7eb2e8f9f7	444	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
<>	144:ef7eb2e8f9f7	445	#endif /* STM32L1 */
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	#if defined(STM32F0) \|\| defined(STM32F3) \|\| defined(STM32F1)
<>	144:ef7eb2e8f9f7	448	#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
<>	144:ef7eb2e8f9f7	449	#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
<>	144:ef7eb2e8f9f7	450	#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
<>	144:ef7eb2e8f9f7	451	#endif /* STM32F0 \|\| STM32F3 \|\| STM32F1 */
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
<>	144:ef7eb2e8f9f7	454	/**
<>	144:ef7eb2e8f9f7	455	* @}
<>	144:ef7eb2e8f9f7	456	*/
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	459	* @{
<>	144:ef7eb2e8f9f7	460	*/
<>	144:ef7eb2e8f9f7	461	#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
<>	144:ef7eb2e8f9f7	462	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
<>	144:ef7eb2e8f9f7	463	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
<>	144:ef7eb2e8f9f7	464	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
<>	144:ef7eb2e8f9f7	465	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
<>	144:ef7eb2e8f9f7	466	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
<>	144:ef7eb2e8f9f7	467	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
<>	144:ef7eb2e8f9f7	468	#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
<>	144:ef7eb2e8f9f7	469	#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
<>	144:ef7eb2e8f9f7	472	#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
<>	144:ef7eb2e8f9f7	473	#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
<>	144:ef7eb2e8f9f7	474	#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
<>	144:ef7eb2e8f9f7	475	#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
<>	144:ef7eb2e8f9f7	476	#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
<>	144:ef7eb2e8f9f7	477	#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
<>	144:ef7eb2e8f9f7	478	#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
<>	144:ef7eb2e8f9f7	479	/**
<>	144:ef7eb2e8f9f7	480	* @}
<>	144:ef7eb2e8f9f7	481	*/
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	484	* @{
<>	144:ef7eb2e8f9f7	485	*/
<>	144:ef7eb2e8f9f7	486	#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
<>	144:ef7eb2e8f9f7	487	#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
<>	144:ef7eb2e8f9f7	488	#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
<>	144:ef7eb2e8f9f7	489	#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
<>	144:ef7eb2e8f9f7	490	#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
<>	144:ef7eb2e8f9f7	491	#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
<>	144:ef7eb2e8f9f7	492	#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
<>	144:ef7eb2e8f9f7	493	#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
<>	144:ef7eb2e8f9f7	494	#if defined(STM32F0) \|\| defined(STM32F1) \|\| defined(STM32F3) \|\| defined(STM32G0) \|\| defined(STM32L4) \|\| defined(STM32L1) \|\| defined(STM32F7)
<>	144:ef7eb2e8f9f7	495	#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
<>	144:ef7eb2e8f9f7	496	#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
<>	144:ef7eb2e8f9f7	497	#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
<>	144:ef7eb2e8f9f7	498	#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
<>	144:ef7eb2e8f9f7	499	#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
<>	144:ef7eb2e8f9f7	500	#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
<>	144:ef7eb2e8f9f7	501	#endif
<>	144:ef7eb2e8f9f7	502	/**
<>	144:ef7eb2e8f9f7	503	* @}
<>	144:ef7eb2e8f9f7	504	*/
<>	144:ef7eb2e8f9f7	505
<>	144:ef7eb2e8f9f7	506	/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	507	* @{
<>	144:ef7eb2e8f9f7	508	*/
<>	144:ef7eb2e8f9f7	509	#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	510	#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512	/**
<>	144:ef7eb2e8f9f7	513	* @}
<>	144:ef7eb2e8f9f7	514	*/
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	517	* @{
<>	144:ef7eb2e8f9f7	518	*/
<>	144:ef7eb2e8f9f7	519	#define KR_KEY_RELOAD IWDG_KEY_RELOAD
<>	144:ef7eb2e8f9f7	520	#define KR_KEY_ENABLE IWDG_KEY_ENABLE
<>	144:ef7eb2e8f9f7	521	#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
<>	144:ef7eb2e8f9f7	522	#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
<>	144:ef7eb2e8f9f7	523	/**
<>	144:ef7eb2e8f9f7	524	* @}
<>	144:ef7eb2e8f9f7	525	*/
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	528	* @{
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530
<>	144:ef7eb2e8f9f7	531	#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
<>	144:ef7eb2e8f9f7	532	#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
<>	144:ef7eb2e8f9f7	533	#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
<>	144:ef7eb2e8f9f7	534	#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
<>	144:ef7eb2e8f9f7	537	#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	538	#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
<>	144:ef7eb2e8f9f7	539
<>	144:ef7eb2e8f9f7	540	#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
<>	144:ef7eb2e8f9f7	541	#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<>	144:ef7eb2e8f9f7	542	#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<>	144:ef7eb2e8f9f7	543	#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<>	144:ef7eb2e8f9f7	544
<>	144:ef7eb2e8f9f7	545	/* The following 3 definition have also been present in a temporary version of lptim.h */
<>	144:ef7eb2e8f9f7	546	/* They need to be renamed also to the right name, just in case */
<>	144:ef7eb2e8f9f7	547	#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
<>	144:ef7eb2e8f9f7	548	#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
<>	144:ef7eb2e8f9f7	549	#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/**
<>	144:ef7eb2e8f9f7	552	* @}
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
<>	144:ef7eb2e8f9f7	559	#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
<>	144:ef7eb2e8f9f7	560	#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
<>	144:ef7eb2e8f9f7	561	#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	#define NAND_AddressTypedef NAND_AddressTypeDef
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	#define __ARRAY_ADDRESS ARRAY_ADDRESS
<>	144:ef7eb2e8f9f7	566	#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
<>	144:ef7eb2e8f9f7	567	#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
<>	144:ef7eb2e8f9f7	568	#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
<>	144:ef7eb2e8f9f7	569	#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
<>	144:ef7eb2e8f9f7	570	/**
<>	144:ef7eb2e8f9f7	571	* @}
<>	144:ef7eb2e8f9f7	572	*/
<>	144:ef7eb2e8f9f7	573
<>	144:ef7eb2e8f9f7	574	/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	575	* @{
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577	#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
<>	144:ef7eb2e8f9f7	578	#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
<>	144:ef7eb2e8f9f7	579	#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
<>	144:ef7eb2e8f9f7	580	#define NOR_ERROR HAL_NOR_STATUS_ERROR
<>	144:ef7eb2e8f9f7	581	#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	#define __NOR_WRITE NOR_WRITE
<>	144:ef7eb2e8f9f7	584	#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
<>	144:ef7eb2e8f9f7	585	/**
<>	144:ef7eb2e8f9f7	586	* @}
<>	144:ef7eb2e8f9f7	587	*/
<>	144:ef7eb2e8f9f7	588
<>	144:ef7eb2e8f9f7	589	/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	590	* @{
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	594	#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	595	#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
<>	144:ef7eb2e8f9f7	596	#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	599	#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	600	#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
<>	144:ef7eb2e8f9f7	601	#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
<>	144:ef7eb2e8f9f7	602
<>	144:ef7eb2e8f9f7	603	#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	604	#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	607	#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	608
<>	144:ef7eb2e8f9f7	609	#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	610	#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
<>	144:ef7eb2e8f9f7	615	#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
<>	144:ef7eb2e8f9f7	616	#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/**
<>	144:ef7eb2e8f9f7	619	* @}
<>	144:ef7eb2e8f9f7	620	*/
<>	144:ef7eb2e8f9f7	621
<>	144:ef7eb2e8f9f7	622	/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	623	* @{
<>	144:ef7eb2e8f9f7	624	*/
<>	144:ef7eb2e8f9f7	625	#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
<>	144:ef7eb2e8f9f7	626	#if defined(STM32F7)
<>	144:ef7eb2e8f9f7	627	#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
<>	144:ef7eb2e8f9f7	628	#endif
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @}
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	634	* @{
<>	144:ef7eb2e8f9f7	635	*/
<>	144:ef7eb2e8f9f7	636
<>	144:ef7eb2e8f9f7	637	/* Compact Flash-ATA registers description */
<>	144:ef7eb2e8f9f7	638	#define CF_DATA ATA_DATA
<>	144:ef7eb2e8f9f7	639	#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
<>	144:ef7eb2e8f9f7	640	#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
<>	144:ef7eb2e8f9f7	641	#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
<>	144:ef7eb2e8f9f7	642	#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
<>	144:ef7eb2e8f9f7	643	#define CF_CARD_HEAD ATA_CARD_HEAD
<>	144:ef7eb2e8f9f7	644	#define CF_STATUS_CMD ATA_STATUS_CMD
<>	144:ef7eb2e8f9f7	645	#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
<>	144:ef7eb2e8f9f7	646	#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
<>	144:ef7eb2e8f9f7	647
<>	144:ef7eb2e8f9f7	648	/* Compact Flash-ATA commands */
<>	144:ef7eb2e8f9f7	649	#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
<>	144:ef7eb2e8f9f7	650	#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
<>	144:ef7eb2e8f9f7	651	#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
<>	144:ef7eb2e8f9f7	652	#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
<>	144:ef7eb2e8f9f7	653
<>	144:ef7eb2e8f9f7	654	#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
<>	144:ef7eb2e8f9f7	655	#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
<>	144:ef7eb2e8f9f7	656	#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
<>	144:ef7eb2e8f9f7	657	#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
<>	144:ef7eb2e8f9f7	658	#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
<>	144:ef7eb2e8f9f7	659	/**
<>	144:ef7eb2e8f9f7	660	* @}
<>	144:ef7eb2e8f9f7	661	*/
<>	144:ef7eb2e8f9f7	662
<>	144:ef7eb2e8f9f7	663	/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	664	* @{
<>	144:ef7eb2e8f9f7	665	*/
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	#define FORMAT_BIN RTC_FORMAT_BIN
<>	144:ef7eb2e8f9f7	668	#define FORMAT_BCD RTC_FORMAT_BCD
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
<>	144:ef7eb2e8f9f7	671	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
<>	144:ef7eb2e8f9f7	672	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
<>	144:ef7eb2e8f9f7	673	#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<>	144:ef7eb2e8f9f7	674	#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<>	144:ef7eb2e8f9f7	677	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<>	144:ef7eb2e8f9f7	678	#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
<>	144:ef7eb2e8f9f7	679	#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
<>	144:ef7eb2e8f9f7	680	#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
<>	144:ef7eb2e8f9f7	681	#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
<>	144:ef7eb2e8f9f7	682	#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<>	144:ef7eb2e8f9f7	683	#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
<>	144:ef7eb2e8f9f7	686	#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
<>	144:ef7eb2e8f9f7	687	#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
<>	144:ef7eb2e8f9f7	688	#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
<>	144:ef7eb2e8f9f7	691	#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
<>	144:ef7eb2e8f9f7	692	#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
<>	144:ef7eb2e8f9f7	695	#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
<>	144:ef7eb2e8f9f7	696	#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
<>	144:ef7eb2e8f9f7	697
<>	144:ef7eb2e8f9f7	698	/**
<>	144:ef7eb2e8f9f7	699	* @}
<>	144:ef7eb2e8f9f7	700	*/
<>	144:ef7eb2e8f9f7	701
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	704	* @{
<>	144:ef7eb2e8f9f7	705	*/
<>	144:ef7eb2e8f9f7	706	#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
<>	144:ef7eb2e8f9f7	707	#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
<>	144:ef7eb2e8f9f7	708
<>	144:ef7eb2e8f9f7	709	#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	710	#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	711	#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	712	#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	713
<>	144:ef7eb2e8f9f7	714	#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
<>	144:ef7eb2e8f9f7	715	#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
<>	144:ef7eb2e8f9f7	718	#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
<>	144:ef7eb2e8f9f7	719	/**
<>	144:ef7eb2e8f9f7	720	* @}
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723
<>	144:ef7eb2e8f9f7	724	/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	725	* @{
<>	144:ef7eb2e8f9f7	726	*/
<>	144:ef7eb2e8f9f7	727	#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
<>	144:ef7eb2e8f9f7	728	#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
<>	144:ef7eb2e8f9f7	729	#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
<>	144:ef7eb2e8f9f7	730	#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
<>	144:ef7eb2e8f9f7	731	#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
<>	144:ef7eb2e8f9f7	732	#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
<>	144:ef7eb2e8f9f7	733	#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
<>	144:ef7eb2e8f9f7	734	#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
<>	144:ef7eb2e8f9f7	735	#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
<>	144:ef7eb2e8f9f7	736	#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
<>	144:ef7eb2e8f9f7	737	#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
<>	144:ef7eb2e8f9f7	738	/**
<>	144:ef7eb2e8f9f7	739	* @}
<>	144:ef7eb2e8f9f7	740	*/
<>	144:ef7eb2e8f9f7	741
<>	144:ef7eb2e8f9f7	742	/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	743	* @{
<>	144:ef7eb2e8f9f7	744	*/
<>	144:ef7eb2e8f9f7	745	#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
<>	144:ef7eb2e8f9f7	746	#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
<>	144:ef7eb2e8f9f7	749	#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
<>	144:ef7eb2e8f9f7	752	#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/**
<>	144:ef7eb2e8f9f7	755	* @}
<>	144:ef7eb2e8f9f7	756	*/
<>	144:ef7eb2e8f9f7	757
<>	144:ef7eb2e8f9f7	758	/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	759	* @{
<>	144:ef7eb2e8f9f7	760	*/
<>	144:ef7eb2e8f9f7	761	#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
<>	144:ef7eb2e8f9f7	762	#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	#define TIM_DMABase_CR1 TIM_DMABASE_CR1
<>	144:ef7eb2e8f9f7	765	#define TIM_DMABase_CR2 TIM_DMABASE_CR2
<>	144:ef7eb2e8f9f7	766	#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
<>	144:ef7eb2e8f9f7	767	#define TIM_DMABase_DIER TIM_DMABASE_DIER
<>	144:ef7eb2e8f9f7	768	#define TIM_DMABase_SR TIM_DMABASE_SR
<>	144:ef7eb2e8f9f7	769	#define TIM_DMABase_EGR TIM_DMABASE_EGR
<>	144:ef7eb2e8f9f7	770	#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
<>	144:ef7eb2e8f9f7	771	#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
<>	144:ef7eb2e8f9f7	772	#define TIM_DMABase_CCER TIM_DMABASE_CCER
<>	144:ef7eb2e8f9f7	773	#define TIM_DMABase_CNT TIM_DMABASE_CNT
<>	144:ef7eb2e8f9f7	774	#define TIM_DMABase_PSC TIM_DMABASE_PSC
<>	144:ef7eb2e8f9f7	775	#define TIM_DMABase_ARR TIM_DMABASE_ARR
<>	144:ef7eb2e8f9f7	776	#define TIM_DMABase_RCR TIM_DMABASE_RCR
<>	144:ef7eb2e8f9f7	777	#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
<>	144:ef7eb2e8f9f7	778	#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
<>	144:ef7eb2e8f9f7	779	#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
<>	144:ef7eb2e8f9f7	780	#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
<>	144:ef7eb2e8f9f7	781	#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
<>	144:ef7eb2e8f9f7	782	#define TIM_DMABase_DCR TIM_DMABASE_DCR
<>	144:ef7eb2e8f9f7	783	#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
<>	144:ef7eb2e8f9f7	784	#define TIM_DMABase_OR1 TIM_DMABASE_OR1
<>	144:ef7eb2e8f9f7	785	#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
<>	144:ef7eb2e8f9f7	786	#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
<>	144:ef7eb2e8f9f7	787	#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
<>	144:ef7eb2e8f9f7	788	#define TIM_DMABase_OR2 TIM_DMABASE_OR2
<>	144:ef7eb2e8f9f7	789	#define TIM_DMABase_OR3 TIM_DMABASE_OR3
<>	144:ef7eb2e8f9f7	790	#define TIM_DMABase_OR TIM_DMABASE_OR
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
<>	144:ef7eb2e8f9f7	793	#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
<>	144:ef7eb2e8f9f7	794	#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
<>	144:ef7eb2e8f9f7	795	#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
<>	144:ef7eb2e8f9f7	796	#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
<>	144:ef7eb2e8f9f7	797	#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
<>	144:ef7eb2e8f9f7	798	#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
<>	144:ef7eb2e8f9f7	799	#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
<>	144:ef7eb2e8f9f7	800	#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
<>	144:ef7eb2e8f9f7	803	#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
<>	144:ef7eb2e8f9f7	804	#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
<>	144:ef7eb2e8f9f7	805	#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
<>	144:ef7eb2e8f9f7	806	#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
<>	144:ef7eb2e8f9f7	807	#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
<>	144:ef7eb2e8f9f7	808	#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
<>	144:ef7eb2e8f9f7	809	#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
<>	144:ef7eb2e8f9f7	810	#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
<>	144:ef7eb2e8f9f7	811	#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
<>	144:ef7eb2e8f9f7	812	#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
<>	144:ef7eb2e8f9f7	813	#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
<>	144:ef7eb2e8f9f7	814	#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
<>	144:ef7eb2e8f9f7	815	#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
<>	144:ef7eb2e8f9f7	816	#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
<>	144:ef7eb2e8f9f7	817	#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
<>	144:ef7eb2e8f9f7	818	#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
<>	144:ef7eb2e8f9f7	819	#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	/**
<>	144:ef7eb2e8f9f7	822	* @}
<>	144:ef7eb2e8f9f7	823	*/
<>	144:ef7eb2e8f9f7	824
<>	144:ef7eb2e8f9f7	825	/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	826	* @{
<>	144:ef7eb2e8f9f7	827	*/
<>	144:ef7eb2e8f9f7	828	#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
<>	144:ef7eb2e8f9f7	829	#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
<>	144:ef7eb2e8f9f7	830	/**
<>	144:ef7eb2e8f9f7	831	* @}
<>	144:ef7eb2e8f9f7	832	*/
<>	144:ef7eb2e8f9f7	833
<>	144:ef7eb2e8f9f7	834	/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	835	* @{
<>	144:ef7eb2e8f9f7	836	*/
<>	144:ef7eb2e8f9f7	837	#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	838	#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	839	#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	840	#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842	#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
<>	144:ef7eb2e8f9f7	843	#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
<>	144:ef7eb2e8f9f7	844
<>	144:ef7eb2e8f9f7	845	#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
<>	144:ef7eb2e8f9f7	846	#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
<>	144:ef7eb2e8f9f7	847	#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
<>	144:ef7eb2e8f9f7	848	#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
<>	144:ef7eb2e8f9f7	851	#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
<>	144:ef7eb2e8f9f7	852	#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
<>	144:ef7eb2e8f9f7	853	#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
<>	144:ef7eb2e8f9f7	854
<>	144:ef7eb2e8f9f7	855	#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
<>	144:ef7eb2e8f9f7	856	#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	/**
<>	144:ef7eb2e8f9f7	859	* @}
<>	144:ef7eb2e8f9f7	860	*/
<>	144:ef7eb2e8f9f7	861
<>	144:ef7eb2e8f9f7	862
<>	144:ef7eb2e8f9f7	863	/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	864	* @{
<>	144:ef7eb2e8f9f7	865	*/
<>	144:ef7eb2e8f9f7	866
<>	144:ef7eb2e8f9f7	867	#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
<>	144:ef7eb2e8f9f7	868	#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	#define USARTNACK_ENABLED USART_NACK_ENABLE
<>	144:ef7eb2e8f9f7	871	#define USARTNACK_DISABLED USART_NACK_DISABLE
<>	144:ef7eb2e8f9f7	872	/**
<>	144:ef7eb2e8f9f7	873	* @}
<>	144:ef7eb2e8f9f7	874	*/
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	877	* @{
<>	144:ef7eb2e8f9f7	878	*/
<>	144:ef7eb2e8f9f7	879	#define CFR_BASE WWDG_CFR_BASE
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/**
<>	144:ef7eb2e8f9f7	882	* @}
<>	144:ef7eb2e8f9f7	883	*/
<>	144:ef7eb2e8f9f7	884
<>	144:ef7eb2e8f9f7	885	/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	886	* @{
<>	144:ef7eb2e8f9f7	887	*/
<>	144:ef7eb2e8f9f7	888	#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
<>	144:ef7eb2e8f9f7	889	#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
<>	144:ef7eb2e8f9f7	890	#define CAN_IT_RQCP0 CAN_IT_TME
<>	144:ef7eb2e8f9f7	891	#define CAN_IT_RQCP1 CAN_IT_TME
<>	144:ef7eb2e8f9f7	892	#define CAN_IT_RQCP2 CAN_IT_TME
<>	144:ef7eb2e8f9f7	893	#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
<>	144:ef7eb2e8f9f7	894	#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
<>	144:ef7eb2e8f9f7	895	#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
<>	144:ef7eb2e8f9f7	896	#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
<>	144:ef7eb2e8f9f7	897	#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	/**
<>	144:ef7eb2e8f9f7	900	* @}
<>	144:ef7eb2e8f9f7	901	*/
<>	144:ef7eb2e8f9f7	902
<>	144:ef7eb2e8f9f7	903	/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	904	* @{
<>	144:ef7eb2e8f9f7	905	*/
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	#define VLAN_TAG ETH_VLAN_TAG
<>	144:ef7eb2e8f9f7	908	#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
<>	144:ef7eb2e8f9f7	909	#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
<>	144:ef7eb2e8f9f7	910	#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
<>	144:ef7eb2e8f9f7	911	#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
<>	144:ef7eb2e8f9f7	912	#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
<>	144:ef7eb2e8f9f7	913	#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
<>	144:ef7eb2e8f9f7	914	#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	#define ETH_MMCCR ((uint32_t)0x00000100U)
<>	144:ef7eb2e8f9f7	917	#define ETH_MMCRIR ((uint32_t)0x00000104U)
<>	144:ef7eb2e8f9f7	918	#define ETH_MMCTIR ((uint32_t)0x00000108U)
<>	144:ef7eb2e8f9f7	919	#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
<>	144:ef7eb2e8f9f7	920	#define ETH_MMCTIMR ((uint32_t)0x00000110U)
<>	144:ef7eb2e8f9f7	921	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
<>	144:ef7eb2e8f9f7	922	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
<>	144:ef7eb2e8f9f7	923	#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
<>	144:ef7eb2e8f9f7	924	#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
<>	144:ef7eb2e8f9f7	925	#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
<>	144:ef7eb2e8f9f7	926	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
<>	144:ef7eb2e8f9f7	927
<>	144:ef7eb2e8f9f7	928	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
<>	144:ef7eb2e8f9f7	929	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
<>	144:ef7eb2e8f9f7	930	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
<>	144:ef7eb2e8f9f7	931	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
<>	144:ef7eb2e8f9f7	932	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
<>	144:ef7eb2e8f9f7	933	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
<>	144:ef7eb2e8f9f7	934	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
<>	144:ef7eb2e8f9f7	935	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
<>	144:ef7eb2e8f9f7	936	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
<>	144:ef7eb2e8f9f7	937	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
<>	144:ef7eb2e8f9f7	938	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
<>	144:ef7eb2e8f9f7	939	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
<>	144:ef7eb2e8f9f7	940	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
<>	144:ef7eb2e8f9f7	941	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
<>	144:ef7eb2e8f9f7	942	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
<>	144:ef7eb2e8f9f7	943	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
<>	144:ef7eb2e8f9f7	944	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
<>	144:ef7eb2e8f9f7	945	#if defined(STM32F1)
<>	144:ef7eb2e8f9f7	946	#else
<>	144:ef7eb2e8f9f7	947	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
<>	144:ef7eb2e8f9f7	948	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
<>	144:ef7eb2e8f9f7	949	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
<>	144:ef7eb2e8f9f7	950	#endif
<>	144:ef7eb2e8f9f7	951	#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
<>	144:ef7eb2e8f9f7	952	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
<>	144:ef7eb2e8f9f7	953	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
<>	144:ef7eb2e8f9f7	954	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
<>	144:ef7eb2e8f9f7	955	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
<>	144:ef7eb2e8f9f7	956	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
<>	144:ef7eb2e8f9f7	957	#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	/**
<>	144:ef7eb2e8f9f7	960	* @}
<>	144:ef7eb2e8f9f7	961	*/
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	964	* @{
<>	144:ef7eb2e8f9f7	965	*/
<>	144:ef7eb2e8f9f7	966	#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
<>	144:ef7eb2e8f9f7	967	#define DCMI_IT_OVF DCMI_IT_OVR
<>	144:ef7eb2e8f9f7	968	#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
<>	144:ef7eb2e8f9f7	969	#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
<>	144:ef7eb2e8f9f7	972	#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
<>	144:ef7eb2e8f9f7	973	#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
<>	144:ef7eb2e8f9f7	974
<>	144:ef7eb2e8f9f7	975	/**
<>	144:ef7eb2e8f9f7	976	* @}
<>	144:ef7eb2e8f9f7	977	*/
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	#if defined(STM32L4xx) \|\| defined(STM32F7) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\|\
<>	144:ef7eb2e8f9f7	980	defined(STM32F429xx) \|\| defined(STM32F439xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
<>	144:ef7eb2e8f9f7	981	/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	982	* @{
<>	144:ef7eb2e8f9f7	983	*/
<>	144:ef7eb2e8f9f7	984	#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
<>	144:ef7eb2e8f9f7	985	#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
<>	144:ef7eb2e8f9f7	986	#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
<>	144:ef7eb2e8f9f7	987	#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
<>	144:ef7eb2e8f9f7	988	#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
<>	144:ef7eb2e8f9f7	991	#define CM_RGB888 DMA2D_INPUT_RGB888
<>	144:ef7eb2e8f9f7	992	#define CM_RGB565 DMA2D_INPUT_RGB565
<>	144:ef7eb2e8f9f7	993	#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
<>	144:ef7eb2e8f9f7	994	#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
<>	144:ef7eb2e8f9f7	995	#define CM_L8 DMA2D_INPUT_L8
<>	144:ef7eb2e8f9f7	996	#define CM_AL44 DMA2D_INPUT_AL44
<>	144:ef7eb2e8f9f7	997	#define CM_AL88 DMA2D_INPUT_AL88
<>	144:ef7eb2e8f9f7	998	#define CM_L4 DMA2D_INPUT_L4
<>	144:ef7eb2e8f9f7	999	#define CM_A8 DMA2D_INPUT_A8
<>	144:ef7eb2e8f9f7	1000	#define CM_A4 DMA2D_INPUT_A4
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @}
<>	144:ef7eb2e8f9f7	1003	*/
<>	144:ef7eb2e8f9f7	1004	#endif /* STM32L4xx \|\| STM32F7*/
<>	144:ef7eb2e8f9f7	1005
<>	144:ef7eb2e8f9f7	1006	/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1007	* @{
<>	144:ef7eb2e8f9f7	1008	*/
<>	144:ef7eb2e8f9f7	1009
<>	144:ef7eb2e8f9f7	1010	/**
<>	144:ef7eb2e8f9f7	1011	* @}
<>	144:ef7eb2e8f9f7	1012	*/
<>	144:ef7eb2e8f9f7	1013
<>	144:ef7eb2e8f9f7	1014	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1017	* @{
<>	144:ef7eb2e8f9f7	1018	*/
<>	144:ef7eb2e8f9f7	1019	#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
<>	144:ef7eb2e8f9f7	1020	/**
<>	144:ef7eb2e8f9f7	1021	* @}
<>	144:ef7eb2e8f9f7	1022	*/
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1025	* @{
<>	144:ef7eb2e8f9f7	1026	*/
<>	144:ef7eb2e8f9f7	1027	#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
<>	144:ef7eb2e8f9f7	1028	#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
<>	144:ef7eb2e8f9f7	1029	#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
<>	144:ef7eb2e8f9f7	1030	#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
<>	144:ef7eb2e8f9f7	1031	#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
<>	144:ef7eb2e8f9f7	1032	#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/HASH Algorithm Selection/
<>	144:ef7eb2e8f9f7	1035
<>	144:ef7eb2e8f9f7	1036	#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
<>	144:ef7eb2e8f9f7	1037	#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
<>	144:ef7eb2e8f9f7	1038	#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
<>	144:ef7eb2e8f9f7	1039	#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
<>	144:ef7eb2e8f9f7	1042	#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
<>	144:ef7eb2e8f9f7	1045	#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
<>	144:ef7eb2e8f9f7	1046	/**
<>	144:ef7eb2e8f9f7	1047	* @}
<>	144:ef7eb2e8f9f7	1048	*/
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1051	* @{
<>	144:ef7eb2e8f9f7	1052	*/
<>	144:ef7eb2e8f9f7	1053	#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
<>	144:ef7eb2e8f9f7	1054	#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
<>	144:ef7eb2e8f9f7	1055	#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
<>	144:ef7eb2e8f9f7	1056	#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
<>	144:ef7eb2e8f9f7	1057	#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
<>	144:ef7eb2e8f9f7	1058	#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
<>	144:ef7eb2e8f9f7	1059	#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
<>	144:ef7eb2e8f9f7	1060	#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
<>	144:ef7eb2e8f9f7	1061	#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
<>	144:ef7eb2e8f9f7	1062	#if defined(STM32L0)
<>	144:ef7eb2e8f9f7	1063	#else
<>	144:ef7eb2e8f9f7	1064	#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
<>	144:ef7eb2e8f9f7	1065	#endif
<>	144:ef7eb2e8f9f7	1066	#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
<>	144:ef7eb2e8f9f7	1067	#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
<>	144:ef7eb2e8f9f7	1068	/**
<>	144:ef7eb2e8f9f7	1069	* @}
<>	144:ef7eb2e8f9f7	1070	*/
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1073	* @{
<>	144:ef7eb2e8f9f7	1074	*/
<>	144:ef7eb2e8f9f7	1075	#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
<>	144:ef7eb2e8f9f7	1076	#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
<>	144:ef7eb2e8f9f7	1077	#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
<>	144:ef7eb2e8f9f7	1078	#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
<>	144:ef7eb2e8f9f7	1079	#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
<>	144:ef7eb2e8f9f7	1080	#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
<>	144:ef7eb2e8f9f7	1081	#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/**
<>	144:ef7eb2e8f9f7	1084	* @}
<>	144:ef7eb2e8f9f7	1085	*/
<>	144:ef7eb2e8f9f7	1086
<>	144:ef7eb2e8f9f7	1087	/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1088	* @{
<>	144:ef7eb2e8f9f7	1089	*/
<>	144:ef7eb2e8f9f7	1090	#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
<>	144:ef7eb2e8f9f7	1091	#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
<>	144:ef7eb2e8f9f7	1092	#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
<>	144:ef7eb2e8f9f7	1093	#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
<>	144:ef7eb2e8f9f7	1096	/**
<>	144:ef7eb2e8f9f7	1097	* @}
<>	144:ef7eb2e8f9f7	1098	*/
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1101	* @{
<>	144:ef7eb2e8f9f7	1102	*/
<>	144:ef7eb2e8f9f7	1103	#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
<>	144:ef7eb2e8f9f7	1104	#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
<>	144:ef7eb2e8f9f7	1105	#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
<>	144:ef7eb2e8f9f7	1106	#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
<>	144:ef7eb2e8f9f7	1107	#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
<>	144:ef7eb2e8f9f7	1108	#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
<>	144:ef7eb2e8f9f7	1109	#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
<>	144:ef7eb2e8f9f7	1110	#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
<>	144:ef7eb2e8f9f7	1111	#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
<>	144:ef7eb2e8f9f7	1112	#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
<>	144:ef7eb2e8f9f7	1113	#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
<>	144:ef7eb2e8f9f7	1114	#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
<>	144:ef7eb2e8f9f7	1115	#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
<>	144:ef7eb2e8f9f7	1116	#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
<>	144:ef7eb2e8f9f7	1117	#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
<>	144:ef7eb2e8f9f7	1118	#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120	#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
<>	144:ef7eb2e8f9f7	1121	#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
<>	144:ef7eb2e8f9f7	1122	#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
<>	144:ef7eb2e8f9f7	1123	#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
<>	144:ef7eb2e8f9f7	1124	#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
<>	144:ef7eb2e8f9f7	1125	#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
<>	144:ef7eb2e8f9f7	1126	#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
<>	144:ef7eb2e8f9f7	1127
<>	144:ef7eb2e8f9f7	1128	#define CR_OFFSET_BB PWR_CR_OFFSET_BB
<>	144:ef7eb2e8f9f7	1129	#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
<>	144:ef7eb2e8f9f7	1130
<>	144:ef7eb2e8f9f7	1131	#define DBP_BitNumber DBP_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1132	#define PVDE_BitNumber PVDE_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1133	#define PMODE_BitNumber PMODE_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1134	#define EWUP_BitNumber EWUP_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1135	#define FPDS_BitNumber FPDS_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1136	#define ODEN_BitNumber ODEN_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1137	#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1138	#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1139	#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1140	#define BRE_BitNumber BRE_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
<>	144:ef7eb2e8f9f7	1143
<>	144:ef7eb2e8f9f7	1144	/**
<>	144:ef7eb2e8f9f7	1145	* @}
<>	144:ef7eb2e8f9f7	1146	*/
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1149	* @{
<>	144:ef7eb2e8f9f7	1150	*/
<>	144:ef7eb2e8f9f7	1151	#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
<>	144:ef7eb2e8f9f7	1152	#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
<>	144:ef7eb2e8f9f7	1153	#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
<>	144:ef7eb2e8f9f7	1154	/**
<>	144:ef7eb2e8f9f7	1155	* @}
<>	144:ef7eb2e8f9f7	1156	*/
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1159	* @{
<>	144:ef7eb2e8f9f7	1160	*/
<>	144:ef7eb2e8f9f7	1161	#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
<>	144:ef7eb2e8f9f7	1162	/**
<>	144:ef7eb2e8f9f7	1163	* @}
<>	144:ef7eb2e8f9f7	1164	*/
<>	144:ef7eb2e8f9f7	1165
<>	144:ef7eb2e8f9f7	1166	/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1167	* @{
<>	144:ef7eb2e8f9f7	1168	*/
<>	144:ef7eb2e8f9f7	1169	#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
<>	144:ef7eb2e8f9f7	1170	#define HAL_TIM_DMAError TIM_DMAError
<>	144:ef7eb2e8f9f7	1171	#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
<>	144:ef7eb2e8f9f7	1172	#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
<>	144:ef7eb2e8f9f7	1173	/**
<>	144:ef7eb2e8f9f7	1174	* @}
<>	144:ef7eb2e8f9f7	1175	*/
<>	144:ef7eb2e8f9f7	1176
<>	144:ef7eb2e8f9f7	1177	/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1178	* @{
<>	144:ef7eb2e8f9f7	1179	*/
<>	144:ef7eb2e8f9f7	1180	#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
<>	144:ef7eb2e8f9f7	1181	/**
<>	144:ef7eb2e8f9f7	1182	* @}
<>	144:ef7eb2e8f9f7	1183	*/
<>	144:ef7eb2e8f9f7	1184
<>	144:ef7eb2e8f9f7	1185	/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1186	* @{
<>	144:ef7eb2e8f9f7	1187	*/
<>	144:ef7eb2e8f9f7	1188	#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
<>	144:ef7eb2e8f9f7	1189	/**
<>	144:ef7eb2e8f9f7	1190	* @}
<>	144:ef7eb2e8f9f7	1191	*/
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1195	* @{
<>	144:ef7eb2e8f9f7	1196	*/
<>	144:ef7eb2e8f9f7	1197
<>	144:ef7eb2e8f9f7	1198	/**
<>	144:ef7eb2e8f9f7	1199	* @}
<>	144:ef7eb2e8f9f7	1200	*/
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/* Exported macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1203
<>	144:ef7eb2e8f9f7	1204	/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1205	* @{
<>	144:ef7eb2e8f9f7	1206	*/
<>	144:ef7eb2e8f9f7	1207	#define AES_IT_CC CRYP_IT_CC
<>	144:ef7eb2e8f9f7	1208	#define AES_IT_ERR CRYP_IT_ERR
<>	144:ef7eb2e8f9f7	1209	#define AES_FLAG_CCF CRYP_FLAG_CCF
<>	144:ef7eb2e8f9f7	1210	/**
<>	144:ef7eb2e8f9f7	1211	* @}
<>	144:ef7eb2e8f9f7	1212	*/
<>	144:ef7eb2e8f9f7	1213
<>	144:ef7eb2e8f9f7	1214	/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1215	* @{
<>	144:ef7eb2e8f9f7	1216	*/
<>	144:ef7eb2e8f9f7	1217	#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
<>	144:ef7eb2e8f9f7	1218	#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
<>	144:ef7eb2e8f9f7	1219	#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
<>	144:ef7eb2e8f9f7	1220	#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
<>	144:ef7eb2e8f9f7	1221	#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
<>	144:ef7eb2e8f9f7	1222	#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
<>	144:ef7eb2e8f9f7	1223	#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
<>	144:ef7eb2e8f9f7	1224	#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
<>	144:ef7eb2e8f9f7	1225	#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
<>	144:ef7eb2e8f9f7	1226	#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
<>	144:ef7eb2e8f9f7	1227	#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	1228	#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
<>	144:ef7eb2e8f9f7	1229	#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
<>	144:ef7eb2e8f9f7	1230
<>	144:ef7eb2e8f9f7	1231	#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
<>	144:ef7eb2e8f9f7	1232	#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
<>	144:ef7eb2e8f9f7	1233	#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
<>	144:ef7eb2e8f9f7	1234	#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1235	#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
<>	144:ef7eb2e8f9f7	1236
<>	144:ef7eb2e8f9f7	1237	/**
<>	144:ef7eb2e8f9f7	1238	* @}
<>	144:ef7eb2e8f9f7	1239	*/
<>	144:ef7eb2e8f9f7	1240
<>	144:ef7eb2e8f9f7	1241
<>	144:ef7eb2e8f9f7	1242	/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1243	* @{
<>	144:ef7eb2e8f9f7	1244	*/
<>	144:ef7eb2e8f9f7	1245	#define __ADC_ENABLE __HAL_ADC_ENABLE
<>	144:ef7eb2e8f9f7	1246	#define __ADC_DISABLE __HAL_ADC_DISABLE
<>	144:ef7eb2e8f9f7	1247	#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
<>	144:ef7eb2e8f9f7	1248	#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
<>	144:ef7eb2e8f9f7	1249	#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
<>	144:ef7eb2e8f9f7	1250	#define __ADC_IS_ENABLED ADC_IS_ENABLE
<>	144:ef7eb2e8f9f7	1251	#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
<>	144:ef7eb2e8f9f7	1252	#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
<>	144:ef7eb2e8f9f7	1253	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
<>	144:ef7eb2e8f9f7	1254	#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
<>	144:ef7eb2e8f9f7	1255	#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
<>	144:ef7eb2e8f9f7	1256	#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
<>	144:ef7eb2e8f9f7	1257	#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
<>	144:ef7eb2e8f9f7	1258
<>	144:ef7eb2e8f9f7	1259	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
<>	144:ef7eb2e8f9f7	1260	#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
<>	144:ef7eb2e8f9f7	1261	#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
<>	144:ef7eb2e8f9f7	1262	#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
<>	144:ef7eb2e8f9f7	1263	#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
<>	144:ef7eb2e8f9f7	1264	#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
<>	144:ef7eb2e8f9f7	1265	#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
<>	144:ef7eb2e8f9f7	1266	#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
<>	144:ef7eb2e8f9f7	1267	#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
<>	144:ef7eb2e8f9f7	1268	#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
<>	144:ef7eb2e8f9f7	1269	#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
<>	144:ef7eb2e8f9f7	1270	#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
<>	144:ef7eb2e8f9f7	1271	#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
<>	144:ef7eb2e8f9f7	1272	#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
<>	144:ef7eb2e8f9f7	1273	#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
<>	144:ef7eb2e8f9f7	1274	#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
<>	144:ef7eb2e8f9f7	1275	#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
<>	144:ef7eb2e8f9f7	1276	#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
<>	144:ef7eb2e8f9f7	1277	#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
<>	144:ef7eb2e8f9f7	1278	#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
<>	144:ef7eb2e8f9f7	1281	#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
<>	144:ef7eb2e8f9f7	1282	#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
<>	144:ef7eb2e8f9f7	1283	#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
<>	144:ef7eb2e8f9f7	1284	#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
<>	144:ef7eb2e8f9f7	1285	#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<>	144:ef7eb2e8f9f7	1286	#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
<>	144:ef7eb2e8f9f7	1287	#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
<>	144:ef7eb2e8f9f7	1288	#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
<>	144:ef7eb2e8f9f7	1289	#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
<>	144:ef7eb2e8f9f7	1292	#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
<>	144:ef7eb2e8f9f7	1293	#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
<>	144:ef7eb2e8f9f7	1294	#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
<>	144:ef7eb2e8f9f7	1295	#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
<>	144:ef7eb2e8f9f7	1296	#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
<>	144:ef7eb2e8f9f7	1297	#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
<>	144:ef7eb2e8f9f7	1298	#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	#define __HAL_ADC_SQR1 ADC_SQR1
<>	144:ef7eb2e8f9f7	1301	#define __HAL_ADC_SMPR1 ADC_SMPR1
<>	144:ef7eb2e8f9f7	1302	#define __HAL_ADC_SMPR2 ADC_SMPR2
<>	144:ef7eb2e8f9f7	1303	#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
<>	144:ef7eb2e8f9f7	1304	#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
<>	144:ef7eb2e8f9f7	1305	#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
<>	144:ef7eb2e8f9f7	1306	#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
<>	144:ef7eb2e8f9f7	1307	#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
<>	144:ef7eb2e8f9f7	1308	#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
<>	144:ef7eb2e8f9f7	1309	#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
<>	144:ef7eb2e8f9f7	1310	#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
<>	144:ef7eb2e8f9f7	1311	#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
<>	144:ef7eb2e8f9f7	1312	#define __HAL_ADC_JSQR ADC_JSQR
<>	144:ef7eb2e8f9f7	1313
<>	144:ef7eb2e8f9f7	1314	#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
<>	144:ef7eb2e8f9f7	1315	#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
<>	144:ef7eb2e8f9f7	1316	#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
<>	144:ef7eb2e8f9f7	1317	#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
<>	144:ef7eb2e8f9f7	1318	#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
<>	144:ef7eb2e8f9f7	1319	#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
<>	144:ef7eb2e8f9f7	1320	#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
<>	144:ef7eb2e8f9f7	1321	#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323	/**
<>	144:ef7eb2e8f9f7	1324	* @}
<>	144:ef7eb2e8f9f7	1325	*/
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1328	* @{
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330	#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
<>	144:ef7eb2e8f9f7	1331	#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
<>	144:ef7eb2e8f9f7	1332	#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
<>	144:ef7eb2e8f9f7	1333	#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
<>	144:ef7eb2e8f9f7	1334
<>	144:ef7eb2e8f9f7	1335	/**
<>	144:ef7eb2e8f9f7	1336	* @}
<>	144:ef7eb2e8f9f7	1337	*/
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1340	* @{
<>	144:ef7eb2e8f9f7	1341	*/
<>	144:ef7eb2e8f9f7	1342	#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
<>	144:ef7eb2e8f9f7	1343	#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
<>	144:ef7eb2e8f9f7	1344	#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
<>	144:ef7eb2e8f9f7	1345	#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
<>	144:ef7eb2e8f9f7	1346	#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
<>	144:ef7eb2e8f9f7	1347	#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
<>	144:ef7eb2e8f9f7	1348	#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
<>	144:ef7eb2e8f9f7	1349	#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
<>	144:ef7eb2e8f9f7	1350	#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
<>	144:ef7eb2e8f9f7	1351	#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
<>	144:ef7eb2e8f9f7	1352	#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
<>	144:ef7eb2e8f9f7	1353	#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
<>	144:ef7eb2e8f9f7	1354	#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
<>	144:ef7eb2e8f9f7	1355	#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
<>	144:ef7eb2e8f9f7	1356	#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
<>	144:ef7eb2e8f9f7	1357	#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
<>	144:ef7eb2e8f9f7	1358
<>	144:ef7eb2e8f9f7	1359	#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
<>	144:ef7eb2e8f9f7	1360	#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
<>	144:ef7eb2e8f9f7	1361	#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
<>	144:ef7eb2e8f9f7	1362	#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
<>	144:ef7eb2e8f9f7	1363	#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
<>	144:ef7eb2e8f9f7	1364	#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
<>	144:ef7eb2e8f9f7	1365	#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
<>	144:ef7eb2e8f9f7	1366	#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
<>	144:ef7eb2e8f9f7	1367	#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
<>	144:ef7eb2e8f9f7	1368	#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
<>	144:ef7eb2e8f9f7	1369	#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
<>	144:ef7eb2e8f9f7	1370	#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
<>	144:ef7eb2e8f9f7	1371	#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
<>	144:ef7eb2e8f9f7	1372	#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
<>	144:ef7eb2e8f9f7	1373
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
<>	144:ef7eb2e8f9f7	1376	#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
<>	144:ef7eb2e8f9f7	1377	#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
<>	144:ef7eb2e8f9f7	1378	#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
<>	144:ef7eb2e8f9f7	1379	#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
<>	144:ef7eb2e8f9f7	1380	#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
<>	144:ef7eb2e8f9f7	1381	#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
<>	144:ef7eb2e8f9f7	1382	#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
<>	144:ef7eb2e8f9f7	1383	#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
<>	144:ef7eb2e8f9f7	1384	#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
<>	144:ef7eb2e8f9f7	1385	#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
<>	144:ef7eb2e8f9f7	1386	#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
<>	144:ef7eb2e8f9f7	1387	#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
<>	144:ef7eb2e8f9f7	1388	#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
<>	144:ef7eb2e8f9f7	1389	#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
<>	144:ef7eb2e8f9f7	1390	#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
<>	144:ef7eb2e8f9f7	1391	#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
<>	144:ef7eb2e8f9f7	1392	#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
<>	144:ef7eb2e8f9f7	1393	#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
<>	144:ef7eb2e8f9f7	1394	#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
<>	144:ef7eb2e8f9f7	1395	#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
<>	144:ef7eb2e8f9f7	1396	#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
<>	144:ef7eb2e8f9f7	1397	#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
<>	144:ef7eb2e8f9f7	1398	#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
<>	144:ef7eb2e8f9f7	1399
<>	144:ef7eb2e8f9f7	1400	/**
<>	144:ef7eb2e8f9f7	1401	* @}
<>	144:ef7eb2e8f9f7	1402	*/
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1405	* @{
<>	144:ef7eb2e8f9f7	1406	*/
<>	144:ef7eb2e8f9f7	1407	#if defined(STM32F3)
<>	144:ef7eb2e8f9f7	1408	#define COMP_START __HAL_COMP_ENABLE
<>	144:ef7eb2e8f9f7	1409	#define COMP_STOP __HAL_COMP_DISABLE
<>	144:ef7eb2e8f9f7	1410	#define COMP_LOCK __HAL_COMP_LOCK
<>	144:ef7eb2e8f9f7	1411
<>	144:ef7eb2e8f9f7	1412	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
<>	144:ef7eb2e8f9f7	1413	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1414	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1415	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1416	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1417	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1418	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1419	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1420	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1421	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1422	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1423	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1424	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1425	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1426	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1427	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
<>	144:ef7eb2e8f9f7	1428	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1429	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1430	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
<>	144:ef7eb2e8f9f7	1431	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1432	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1433	__HAL_COMP_COMP6_EXTI_GET_FLAG())
<>	144:ef7eb2e8f9f7	1434	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1435	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1436	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<>	144:ef7eb2e8f9f7	1437	# endif
<>	144:ef7eb2e8f9f7	1438	# if defined(STM32F302xE) \|\| defined(STM32F302xC)
<>	144:ef7eb2e8f9f7	1439	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1440	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1441	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1442	__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1443	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1444	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1445	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1446	__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1447	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1448	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1449	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1450	__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1451	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1452	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1453	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1454	__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1455	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1456	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1457	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1458	__HAL_COMP_COMP6_EXTI_ENABLE_IT())
<>	144:ef7eb2e8f9f7	1459	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1460	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1461	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1462	__HAL_COMP_COMP6_EXTI_DISABLE_IT())
<>	144:ef7eb2e8f9f7	1463	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1464	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1465	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1466	__HAL_COMP_COMP6_EXTI_GET_FLAG())
<>	144:ef7eb2e8f9f7	1467	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1468	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1469	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1470	__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
<>	144:ef7eb2e8f9f7	1471	# endif
<>	144:ef7eb2e8f9f7	1472	# if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	1473	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1474	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1475	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1476	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1477	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1478	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1479	__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1480	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1481	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1482	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1483	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1484	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1485	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1486	__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1487	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1488	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1489	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1490	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1491	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1492	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1493	__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1494	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1495	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1496	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1497	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1498	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1499	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1500	__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1501	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1502	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1503	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1504	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1505	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1506	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1507	__HAL_COMP_COMP7_EXTI_ENABLE_IT())
<>	144:ef7eb2e8f9f7	1508	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1509	((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1510	((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1511	((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1512	((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1513	((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1514	__HAL_COMP_COMP7_EXTI_DISABLE_IT())
<>	144:ef7eb2e8f9f7	1515	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1516	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1517	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1518	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1519	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1520	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1521	__HAL_COMP_COMP7_EXTI_GET_FLAG())
<>	144:ef7eb2e8f9f7	1522	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1523	((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1524	((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1525	((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1526	((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1527	((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1528	__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
<>	144:ef7eb2e8f9f7	1529	# endif
<>	144:ef7eb2e8f9f7	1530	# if defined(STM32F373xC) \|\|defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	1531	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1532	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1533	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1534	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1535	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1536	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1537	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1538	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1539	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1540	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
<>	144:ef7eb2e8f9f7	1541	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1542	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
<>	144:ef7eb2e8f9f7	1543	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1544	__HAL_COMP_COMP2_EXTI_GET_FLAG())
<>	144:ef7eb2e8f9f7	1545	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1546	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<>	144:ef7eb2e8f9f7	1547	# endif
<>	144:ef7eb2e8f9f7	1548	#else
<>	144:ef7eb2e8f9f7	1549	#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1550	__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1551	#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
<>	144:ef7eb2e8f9f7	1552	__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
<>	144:ef7eb2e8f9f7	1553	#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1554	__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1555	#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
<>	144:ef7eb2e8f9f7	1556	__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
<>	144:ef7eb2e8f9f7	1557	#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	1558	__HAL_COMP_COMP2_EXTI_ENABLE_IT())
<>	144:ef7eb2e8f9f7	1559	#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	1560	__HAL_COMP_COMP2_EXTI_DISABLE_IT())
<>	144:ef7eb2e8f9f7	1561	#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	1562	__HAL_COMP_COMP2_EXTI_GET_FLAG())
<>	144:ef7eb2e8f9f7	1563	#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	1564	__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
<>	144:ef7eb2e8f9f7	1565	#endif
<>	144:ef7eb2e8f9f7	1566
<>	144:ef7eb2e8f9f7	1567	#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
<>	144:ef7eb2e8f9f7	1568
<>	144:ef7eb2e8f9f7	1569	#if defined(STM32L0) \|\| defined(STM32L4)
<>	144:ef7eb2e8f9f7	1570	/* Note: On these STM32 families, the only argument of this macro */
<>	144:ef7eb2e8f9f7	1571	/* is COMP_FLAG_LOCK. */
<>	144:ef7eb2e8f9f7	1572	/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
<>	144:ef7eb2e8f9f7	1573	/* argument. */
<>	144:ef7eb2e8f9f7	1574	#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
<>	144:ef7eb2e8f9f7	1575	#endif
<>	144:ef7eb2e8f9f7	1576	/**
<>	144:ef7eb2e8f9f7	1577	* @}
<>	144:ef7eb2e8f9f7	1578	*/
<>	144:ef7eb2e8f9f7	1579
<>	144:ef7eb2e8f9f7	1580	#if defined(STM32L0) \|\| defined(STM32L4)
<>	144:ef7eb2e8f9f7	1581	/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1582	* @{
<>	144:ef7eb2e8f9f7	1583	*/
<>	144:ef7eb2e8f9f7	1584	#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<>	144:ef7eb2e8f9f7	1585	#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
<>	144:ef7eb2e8f9f7	1586	/**
<>	144:ef7eb2e8f9f7	1587	* @}
<>	144:ef7eb2e8f9f7	1588	*/
<>	144:ef7eb2e8f9f7	1589	#endif
<>	144:ef7eb2e8f9f7	1590
<>	144:ef7eb2e8f9f7	1591	/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1592	* @{
<>	144:ef7eb2e8f9f7	1593	*/
<>	144:ef7eb2e8f9f7	1594
<>	144:ef7eb2e8f9f7	1595	#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1596	((WAVE) == DAC_WAVE_NOISE)\|\| \
<>	144:ef7eb2e8f9f7	1597	((WAVE) == DAC_WAVE_TRIANGLE))
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/**
<>	144:ef7eb2e8f9f7	1600	* @}
<>	144:ef7eb2e8f9f7	1601	*/
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1604	* @{
<>	144:ef7eb2e8f9f7	1605	*/
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	#define IS_WRPAREA IS_OB_WRPAREA
<>	144:ef7eb2e8f9f7	1608	#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
<>	144:ef7eb2e8f9f7	1609	#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
<>	144:ef7eb2e8f9f7	1610	#define IS_TYPEERASE IS_FLASH_TYPEERASE
<>	144:ef7eb2e8f9f7	1611	#define IS_NBSECTORS IS_FLASH_NBSECTORS
<>	144:ef7eb2e8f9f7	1612	#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/**
<>	144:ef7eb2e8f9f7	1615	* @}
<>	144:ef7eb2e8f9f7	1616	*/
<>	144:ef7eb2e8f9f7	1617
<>	144:ef7eb2e8f9f7	1618	/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1619	* @{
<>	144:ef7eb2e8f9f7	1620	*/
<>	144:ef7eb2e8f9f7	1621
<>	144:ef7eb2e8f9f7	1622	#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
<>	144:ef7eb2e8f9f7	1623	#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
<>	144:ef7eb2e8f9f7	1624	#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
<>	144:ef7eb2e8f9f7	1625	#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
<>	144:ef7eb2e8f9f7	1626	#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
<>	144:ef7eb2e8f9f7	1627	#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
<>	144:ef7eb2e8f9f7	1628	#define __HAL_I2C_SPEED I2C_SPEED
<>	144:ef7eb2e8f9f7	1629	#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
<>	144:ef7eb2e8f9f7	1630	#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
<>	144:ef7eb2e8f9f7	1631	#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
<>	144:ef7eb2e8f9f7	1632	#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
<>	144:ef7eb2e8f9f7	1633	#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
<>	144:ef7eb2e8f9f7	1634	#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
<>	144:ef7eb2e8f9f7	1635	#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
<>	144:ef7eb2e8f9f7	1636	#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
<>	144:ef7eb2e8f9f7	1637	/**
<>	144:ef7eb2e8f9f7	1638	* @}
<>	144:ef7eb2e8f9f7	1639	*/
<>	144:ef7eb2e8f9f7	1640
<>	144:ef7eb2e8f9f7	1641	/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1642	* @{
<>	144:ef7eb2e8f9f7	1643	*/
<>	144:ef7eb2e8f9f7	1644
<>	144:ef7eb2e8f9f7	1645	#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
<>	144:ef7eb2e8f9f7	1646	#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
<>	144:ef7eb2e8f9f7	1647
<>	144:ef7eb2e8f9f7	1648	/**
<>	144:ef7eb2e8f9f7	1649	* @}
<>	144:ef7eb2e8f9f7	1650	*/
<>	144:ef7eb2e8f9f7	1651
<>	144:ef7eb2e8f9f7	1652	/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1653	* @{
<>	144:ef7eb2e8f9f7	1654	*/
<>	144:ef7eb2e8f9f7	1655
<>	144:ef7eb2e8f9f7	1656	#define __IRDA_DISABLE __HAL_IRDA_DISABLE
<>	144:ef7eb2e8f9f7	1657	#define __IRDA_ENABLE __HAL_IRDA_ENABLE
<>	144:ef7eb2e8f9f7	1658
<>	144:ef7eb2e8f9f7	1659	#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	1660	#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<>	144:ef7eb2e8f9f7	1661	#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	1662	#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	/**
<>	144:ef7eb2e8f9f7	1668	* @}
<>	144:ef7eb2e8f9f7	1669	*/
<>	144:ef7eb2e8f9f7	1670
<>	144:ef7eb2e8f9f7	1671
<>	144:ef7eb2e8f9f7	1672	/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1673	* @{
<>	144:ef7eb2e8f9f7	1674	*/
<>	144:ef7eb2e8f9f7	1675	#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
<>	144:ef7eb2e8f9f7	1676	#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
<>	144:ef7eb2e8f9f7	1677	/**
<>	144:ef7eb2e8f9f7	1678	* @}
<>	144:ef7eb2e8f9f7	1679	*/
<>	144:ef7eb2e8f9f7	1680
<>	144:ef7eb2e8f9f7	1681
<>	144:ef7eb2e8f9f7	1682	/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1683	* @{
<>	144:ef7eb2e8f9f7	1684	*/
<>	144:ef7eb2e8f9f7	1685
<>	144:ef7eb2e8f9f7	1686	#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
<>	144:ef7eb2e8f9f7	1687	#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
<>	144:ef7eb2e8f9f7	1688	#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
<>	144:ef7eb2e8f9f7	1689
<>	144:ef7eb2e8f9f7	1690	/**
<>	144:ef7eb2e8f9f7	1691	* @}
<>	144:ef7eb2e8f9f7	1692	*/
<>	144:ef7eb2e8f9f7	1693
<>	144:ef7eb2e8f9f7	1694
<>	144:ef7eb2e8f9f7	1695	/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1696	* @{
<>	144:ef7eb2e8f9f7	1697	*/
<>	144:ef7eb2e8f9f7	1698	#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
<>	144:ef7eb2e8f9f7	1699	#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
<>	144:ef7eb2e8f9f7	1700	#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
<>	144:ef7eb2e8f9f7	1701	#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
<>	144:ef7eb2e8f9f7	1702	#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
<>	144:ef7eb2e8f9f7	1703	#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
<>	144:ef7eb2e8f9f7	1704	#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
<>	144:ef7eb2e8f9f7	1705	#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
<>	144:ef7eb2e8f9f7	1706	#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
<>	144:ef7eb2e8f9f7	1707	#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
<>	144:ef7eb2e8f9f7	1708	#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
<>	144:ef7eb2e8f9f7	1709	#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
<>	144:ef7eb2e8f9f7	1710	#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
<>	144:ef7eb2e8f9f7	1711
<>	144:ef7eb2e8f9f7	1712	/**
<>	144:ef7eb2e8f9f7	1713	* @}
<>	144:ef7eb2e8f9f7	1714	*/
<>	144:ef7eb2e8f9f7	1715
<>	144:ef7eb2e8f9f7	1716
<>	144:ef7eb2e8f9f7	1717	/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1718	* @{
<>	144:ef7eb2e8f9f7	1719	*/
<>	144:ef7eb2e8f9f7	1720	#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<>	144:ef7eb2e8f9f7	1721	#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<>	144:ef7eb2e8f9f7	1722	#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1723	#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1724	#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	1725	#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	1726	#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
<>	144:ef7eb2e8f9f7	1727	#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
<>	144:ef7eb2e8f9f7	1728	#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
<>	144:ef7eb2e8f9f7	1729	#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
<>	144:ef7eb2e8f9f7	1730	#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
<>	144:ef7eb2e8f9f7	1731	#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
<>	144:ef7eb2e8f9f7	1732	#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
<>	144:ef7eb2e8f9f7	1733	#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
<>	144:ef7eb2e8f9f7	1734	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
<>	144:ef7eb2e8f9f7	1735	#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
<>	144:ef7eb2e8f9f7	1736	#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
<>	144:ef7eb2e8f9f7	1737	#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
<>	144:ef7eb2e8f9f7	1738	#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
<>	144:ef7eb2e8f9f7	1739	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1740	#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1741	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	1742	#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	1743	#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1744	#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	1745	#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
<>	144:ef7eb2e8f9f7	1746	#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
<>	144:ef7eb2e8f9f7	1747	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
<>	144:ef7eb2e8f9f7	1748	#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
<>	144:ef7eb2e8f9f7	1749	#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
<>	144:ef7eb2e8f9f7	1750	#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
<>	144:ef7eb2e8f9f7	1751	#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1752	#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	1753	#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
<>	144:ef7eb2e8f9f7	1754	#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
<>	144:ef7eb2e8f9f7	1755
<>	144:ef7eb2e8f9f7	1756	#if defined (STM32F4)
<>	144:ef7eb2e8f9f7	1757	#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
<>	144:ef7eb2e8f9f7	1758	#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
<>	144:ef7eb2e8f9f7	1759	#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
<>	144:ef7eb2e8f9f7	1760	#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
<>	144:ef7eb2e8f9f7	1761	#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
<>	144:ef7eb2e8f9f7	1762	#else
<>	144:ef7eb2e8f9f7	1763	#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	1764	#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	1765	#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	1766	#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
<>	144:ef7eb2e8f9f7	1767	#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
<>	144:ef7eb2e8f9f7	1768	#endif /* STM32F4 */
<>	144:ef7eb2e8f9f7	1769	/**
<>	144:ef7eb2e8f9f7	1770	* @}
<>	144:ef7eb2e8f9f7	1771	*/
<>	144:ef7eb2e8f9f7	1772
<>	144:ef7eb2e8f9f7	1773
<>	144:ef7eb2e8f9f7	1774	/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
<>	144:ef7eb2e8f9f7	1775	* @{
<>	144:ef7eb2e8f9f7	1776	*/
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
<>	144:ef7eb2e8f9f7	1779	#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
<>	144:ef7eb2e8f9f7	1782	#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784	#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1785	#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1786	#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1787	#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1788	#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1789	#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1790	#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1791	#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1792	#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1793	#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1794	#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1795	#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1796	#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1797	#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1798	#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1799	#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1800	#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1801	#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1802	#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
<>	144:ef7eb2e8f9f7	1803	#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1804	#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1805	#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1806	#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1807	#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1808	#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
<>	144:ef7eb2e8f9f7	1809	#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1810	#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1811	#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1812	#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1813	#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1814	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
<>	144:ef7eb2e8f9f7	1815	#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1816	#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1817	#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1818	#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
<>	144:ef7eb2e8f9f7	1819	#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1820	#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
<>	144:ef7eb2e8f9f7	1821	#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1822	#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1823	#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1824	#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1825	#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1826	#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
<>	144:ef7eb2e8f9f7	1827	#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1828	#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1829	#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1830	#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1831	#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1832	#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1833	#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1834	#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
<>	144:ef7eb2e8f9f7	1835	#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1836	#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1837	#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1838	#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1839	#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1840	#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1841	#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1842	#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1843	#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1844	#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1845	#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1846	#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1847	#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1848	#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1849	#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1850	#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1851	#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1852	#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1853	#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1854	#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
<>	144:ef7eb2e8f9f7	1855	#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1856	#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1857	#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1858	#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1859	#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1860	#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1861	#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1862	#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1863	#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1864	#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1865	#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1866	#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1867	#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1868	#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1869	#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1870	#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1871	#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1872	#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1873	#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1874	#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1875	#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1876	#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1877	#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1878	#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
<>	144:ef7eb2e8f9f7	1879	#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1880	#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1881	#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1882	#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1883	#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1884	#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
<>	144:ef7eb2e8f9f7	1885	#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1886	#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1887	#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1888	#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1889	#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1890	#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1891	#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1892	#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1893	#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1894	#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1895	#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1896	#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1897	#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1898	#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1899	#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1900	#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1901	#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1902	#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1903	#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1904	#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1905	#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1906	#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1907	#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1908	#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1909	#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1910	#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1911	#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1912	#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
<>	144:ef7eb2e8f9f7	1913	#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1914	#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1915	#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1916	#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
<>	144:ef7eb2e8f9f7	1917	#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1918	#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1919	#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1920	#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1921	#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1922	#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1923	#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1924	#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1925	#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1926	#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1927	#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1928	#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1929	#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1930	#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1931	#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1932	#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
<>	144:ef7eb2e8f9f7	1933	#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1934	#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1935	#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1936	#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1937	#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1938	#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
<>	144:ef7eb2e8f9f7	1939	#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1940	#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1941	#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1942	#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1943	#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1944	#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
<>	144:ef7eb2e8f9f7	1945	#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1946	#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1947	#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1948	#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1949	#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1950	#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
<>	144:ef7eb2e8f9f7	1951	#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1952	#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1953	#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1954	#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1955	#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1956	#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
<>	144:ef7eb2e8f9f7	1957	#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1958	#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1959	#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1960	#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1961	#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1962	#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
<>	144:ef7eb2e8f9f7	1963	#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1964	#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1965	#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1966	#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1967	#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1968	#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
<>	144:ef7eb2e8f9f7	1969	#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1970	#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1971	#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1972	#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1973	#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1974	#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
<>	144:ef7eb2e8f9f7	1975	#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1976	#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1977	#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1978	#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1979	#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1980	#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
<>	144:ef7eb2e8f9f7	1981	#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1982	#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1983	#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1984	#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1985	#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1986	#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
<>	144:ef7eb2e8f9f7	1987	#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1988	#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1989	#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1990	#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1991	#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1992	#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
<>	144:ef7eb2e8f9f7	1993	#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	1994	#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
<>	144:ef7eb2e8f9f7	1995	#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
<>	144:ef7eb2e8f9f7	1996	#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	1997	#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	1998	#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
<>	144:ef7eb2e8f9f7	1999	#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2000	#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2001	#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2002	#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2003	#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2004	#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2005	#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2006	#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2007	#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2008	#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2009	#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2010	#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2011	#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2012	#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2013	#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2014	#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2015	#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2016	#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2017	#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2018	#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2019	#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2020	#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2021	#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2022	#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
<>	144:ef7eb2e8f9f7	2023	#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2024	#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2025	#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2026	#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2027	#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2028	#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2029	#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2030	#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2031	#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2032	#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2033	#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2034	#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
<>	144:ef7eb2e8f9f7	2035	#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2036	#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2037	#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2038	#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2039	#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2040	#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
<>	144:ef7eb2e8f9f7	2041	#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2042	#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2043	#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2044	#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2045	#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2046	#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
<>	144:ef7eb2e8f9f7	2047	#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2048	#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2049	#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2050	#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2051	#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2052	#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2053	#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2054	#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2055	#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2056	#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2057	#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2058	#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2059	#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2060	#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2061	#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2062	#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2063	#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2064	#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2065	#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2066	#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
<>	144:ef7eb2e8f9f7	2067	#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2068	#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2069	#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2070	#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2071	#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2072	#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2073	#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2074	#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2075	#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2076	#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2077	#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2078	#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2079	#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2080	#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2081	#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2082	#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2083	#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2084	#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
<>	144:ef7eb2e8f9f7	2085	#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2086	#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2087	#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2088	#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2089	#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2090	#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2091	#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2092	#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2093	#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2094	#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2095	#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2096	#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2097	#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2098	#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2099	#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2100	#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2101	#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2102	#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
<>	144:ef7eb2e8f9f7	2103	#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2104	#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2105	#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2106	#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2107	#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2108	#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2109	#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2110	#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2111	#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2112	#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
<>	144:ef7eb2e8f9f7	2113	#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2114	#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2115	#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2116	#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
<>	144:ef7eb2e8f9f7	2117	#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2118	#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2119	#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2120	#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
<>	144:ef7eb2e8f9f7	2121	#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2122	#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2123	#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2124	#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
<>	144:ef7eb2e8f9f7	2125	#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2126	#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2127	#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2128	#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
<>	144:ef7eb2e8f9f7	2129	#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2130	#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2131	#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2132	#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2133	#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2134	#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
<>	144:ef7eb2e8f9f7	2135	#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2136	#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2137	#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2138	#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2139	#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2140	#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
<>	144:ef7eb2e8f9f7	2141	#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2142	#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2143	#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2144	#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2145	#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2146	#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
<>	144:ef7eb2e8f9f7	2147	#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2148	#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2149	#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2150	#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2151	#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2152	#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2153	#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2154	#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2155	#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2156	#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2157	#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2158	#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
<>	144:ef7eb2e8f9f7	2159	#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2160	#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2161	#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2162	#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2163	#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2164	#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
<>	144:ef7eb2e8f9f7	2165	#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2166	#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2167	#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2168	#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2169	#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2170	#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
<>	144:ef7eb2e8f9f7	2171	#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2172	#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2173	#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2174	#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2175	#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2176	#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
<>	144:ef7eb2e8f9f7	2177	#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2178	#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2179	#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2180	#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2181	#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2182	#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
<>	144:ef7eb2e8f9f7	2183	#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2184	#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2185	#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2186	#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2187	#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2188	#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
<>	144:ef7eb2e8f9f7	2189	#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2190	#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2191	#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2192	#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
<>	144:ef7eb2e8f9f7	2193	#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2194	#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2195	#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2196	#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2197	#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2198	#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
<>	144:ef7eb2e8f9f7	2199	#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2200	#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2201	#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2202	#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2203	#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2204	#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
<>	144:ef7eb2e8f9f7	2205	#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2206	#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2207	#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2208	#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2209	#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2210	#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
<>	144:ef7eb2e8f9f7	2211	#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2212	#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2213	#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2214	#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2215	#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2216	#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2217	#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2218	#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2219	#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2220	#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2221	#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2222	#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2223	#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2224	#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2225	#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2226	#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2227	#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2228	#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
<>	144:ef7eb2e8f9f7	2229	#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2230	#define __USART4_CLK_DISABLE __HAL_RCC_USART4_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2231	#define __USART4_CLK_ENABLE __HAL_RCC_USART4_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2232	#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_USART4_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2233	#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_USART4_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2234	#define __USART4_FORCE_RESET __HAL_RCC_USART4_FORCE_RESET
<>	144:ef7eb2e8f9f7	2235	#define __USART4_RELEASE_RESET __HAL_RCC_USART4_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2236	#define __USART5_CLK_DISABLE __HAL_RCC_USART5_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2237	#define __USART5_CLK_ENABLE __HAL_RCC_USART5_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2238	#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_USART5_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2239	#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_USART5_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2240	#define __USART5_FORCE_RESET __HAL_RCC_USART5_FORCE_RESET
<>	144:ef7eb2e8f9f7	2241	#define __USART5_RELEASE_RESET __HAL_RCC_USART5_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2242	#define __USART7_CLK_DISABLE __HAL_RCC_USART7_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2243	#define __USART7_CLK_ENABLE __HAL_RCC_USART7_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2244	#define __USART7_FORCE_RESET __HAL_RCC_USART7_FORCE_RESET
<>	144:ef7eb2e8f9f7	2245	#define __USART7_RELEASE_RESET __HAL_RCC_USART7_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2246	#define __USART8_CLK_DISABLE __HAL_RCC_USART8_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2247	#define __USART8_CLK_ENABLE __HAL_RCC_USART8_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2248	#define __USART8_FORCE_RESET __HAL_RCC_USART8_FORCE_RESET
<>	144:ef7eb2e8f9f7	2249	#define __USART8_RELEASE_RESET __HAL_RCC_USART8_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2250	#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2251	#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2252	#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
<>	144:ef7eb2e8f9f7	2253	#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2254	#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2255	#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2256	#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2257	#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2258	#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2259	#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2260	#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2261	#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2262	#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
<>	144:ef7eb2e8f9f7	2263	#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2264	#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2265	#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2266	#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
<>	144:ef7eb2e8f9f7	2267	#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2268	#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2269	#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2270	#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2271	#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2272	#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
<>	144:ef7eb2e8f9f7	2273	#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2274	#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2275	#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2276	#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2277	#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2278	#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2279	#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2280	#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2281	#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2282	#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
<>	144:ef7eb2e8f9f7	2283	#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
<>	144:ef7eb2e8f9f7	2284
<>	144:ef7eb2e8f9f7	2285	#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2286	#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2287	#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2288	#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2289	#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2290	#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2291	#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2292	#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2293	#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2294	#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2295	#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2296	#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2297	#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2298	#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2299	#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2300	#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2301	#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2302	#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2303	#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2304	#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
<>	144:ef7eb2e8f9f7	2305	#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2306	#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2307	#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2308	#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2309	#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2310	#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2311	#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
<>	144:ef7eb2e8f9f7	2312	#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2313	#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2314	#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2315	#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2316	#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2317	#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
<>	144:ef7eb2e8f9f7	2318	#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2319	#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2320	#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2321	#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2322	#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2323	#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
<>	144:ef7eb2e8f9f7	2324	#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2325	#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2326	#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2327	#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2328	#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2329	#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2330	#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2331	#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2332	#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2333	#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2334	#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2335	#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2336	#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2337	#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2338	#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2339	#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2340	#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2341	#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2342	#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2343	#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2344	#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2345	#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2346	#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
<>	144:ef7eb2e8f9f7	2347	#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2348	#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2349	#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2350	#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2351	#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2352	#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
<>	144:ef7eb2e8f9f7	2353	#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2354	#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2355	#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2356	#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2357	#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2358	#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
<>	144:ef7eb2e8f9f7	2359	#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2360	#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2361	#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2362	#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2363	#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2364	#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
<>	144:ef7eb2e8f9f7	2365	#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2366	#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2367	#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2368	#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2369	#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2370	#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2371	#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2372	#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2373	#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2374	#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2375	#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2376	#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2377	#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
<>	144:ef7eb2e8f9f7	2378	#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2379	#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2380	#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2381	#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2382	#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2383	#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2384	#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
<>	144:ef7eb2e8f9f7	2385	#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2386	#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2387	#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2388	#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2389	#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
<>	144:ef7eb2e8f9f7	2390	#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2391	#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2392	#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2393	#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2394	#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2395	#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2396	#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2397	#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2398	#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2399	#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2400	#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2401	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
<>	144:ef7eb2e8f9f7	2402	#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
<>	144:ef7eb2e8f9f7	2403	#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2404	#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2405	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2406	#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2407	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
<>	144:ef7eb2e8f9f7	2408	#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
<>	144:ef7eb2e8f9f7	2409	#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
<>	144:ef7eb2e8f9f7	2410	#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2411	#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2412	#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2413	#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2414	#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2415	#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2416	#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2417	#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2418	#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2419	#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
<>	144:ef7eb2e8f9f7	2420	#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2421	#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2422	#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2423	#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<>	144:ef7eb2e8f9f7	2424	#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2425	#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2426	#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2427	#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2428	#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2429	#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
<>	144:ef7eb2e8f9f7	2430	#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2431	#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2432	#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2433
<>	144:ef7eb2e8f9f7	2434	/* alias define maintained for legacy */
<>	144:ef7eb2e8f9f7	2435	#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
<>	144:ef7eb2e8f9f7	2436	#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2437
<>	144:ef7eb2e8f9f7	2438	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2439	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2440	#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2441	#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2442	#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2443	#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2444	#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2445	#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2446	#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2447	#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2448	#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2449	#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2450	#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2451	#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2452	#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2453	#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2454	#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2455	#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2456	#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2457	#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2458	#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2459	#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2460
<>	144:ef7eb2e8f9f7	2461	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
<>	144:ef7eb2e8f9f7	2462	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2463	#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
<>	144:ef7eb2e8f9f7	2464	#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2465	#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
<>	144:ef7eb2e8f9f7	2466	#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2467	#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2468	#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2469	#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
<>	144:ef7eb2e8f9f7	2470	#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2471	#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
<>	144:ef7eb2e8f9f7	2472	#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2473	#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
<>	144:ef7eb2e8f9f7	2474	#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2475	#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2476	#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2477	#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2478	#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
<>	144:ef7eb2e8f9f7	2479	#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
<>	144:ef7eb2e8f9f7	2480	#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2481	#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2482	#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2483
<>	144:ef7eb2e8f9f7	2484	#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2485	#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2486	#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2487	#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2488	#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2489	#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2490	#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2491	#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2492	#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2493	#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2494	#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2495	#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2496	#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2497	#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2498	#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2499	#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2500	#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2501	#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2502	#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2503	#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2504	#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2505	#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2506	#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2507	#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2508	#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2509	#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2510	#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2511	#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2512	#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2513	#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2514	#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2515	#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2516	#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2517	#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2518	#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2519	#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2520	#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2521	#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2522	#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2523	#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2524	#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2525	#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2526	#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2527	#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2528	#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2529	#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2530	#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2531	#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2532	#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2533	#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2534	#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2535	#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2536	#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2537	#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2538	#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2539	#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2540	#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2541	#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2542	#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2543	#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2544	#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2545	#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2546	#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2547	#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2548	#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2549	#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2550	#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2551	#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2552	#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2553	#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2554	#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2555	#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2556	#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2557	#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2558	#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2559	#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2560	#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2561	#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2562	#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2563	#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2564	#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2565	#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2566	#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2567	#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2568	#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2569	#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2570	#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2571	#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2572	#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2573	#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2574	#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2575	#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2576	#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2577	#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2578	#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2579	#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2580	#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2581	#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2582	#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2583	#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2584	#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2585	#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2586	#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2587	#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2588	#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2589	#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2590	#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2591	#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2592	#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2593	#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2594	#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2595	#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2596	#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2597	#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2598	#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2599	#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2600
<>	144:ef7eb2e8f9f7	2601	#if defined(STM32F4)
<>	144:ef7eb2e8f9f7	2602	#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
<>	144:ef7eb2e8f9f7	2603	#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2604	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2605	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2606	#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2607	#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2608	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2609	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2610	#define Sdmmc1ClockSelection SdioClockSelection
<>	144:ef7eb2e8f9f7	2611	#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
<>	144:ef7eb2e8f9f7	2612	#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
<>	144:ef7eb2e8f9f7	2613	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2614	#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
<>	144:ef7eb2e8f9f7	2615	#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
<>	144:ef7eb2e8f9f7	2616	#endif
<>	144:ef7eb2e8f9f7	2617
<>	144:ef7eb2e8f9f7	2618	#if defined(STM32F7) \|\| defined(STM32L4)
<>	144:ef7eb2e8f9f7	2619	#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2620	#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2621	#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2622	#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2623	#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2624	#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2625	#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2626	#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2627	#define SdioClockSelection Sdmmc1ClockSelection
<>	144:ef7eb2e8f9f7	2628	#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
<>	144:ef7eb2e8f9f7	2629	#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
<>	144:ef7eb2e8f9f7	2630	#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
<>	144:ef7eb2e8f9f7	2631	#endif
<>	144:ef7eb2e8f9f7	2632
<>	144:ef7eb2e8f9f7	2633	#if defined(STM32F7)
<>	144:ef7eb2e8f9f7	2634	#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
<>	144:ef7eb2e8f9f7	2635	#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2636	#endif
<>	144:ef7eb2e8f9f7	2637
<>	144:ef7eb2e8f9f7	2638	#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
<>	144:ef7eb2e8f9f7	2639	#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
<>	144:ef7eb2e8f9f7	2640
<>	144:ef7eb2e8f9f7	2641	#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
<>	144:ef7eb2e8f9f7	2642
<>	144:ef7eb2e8f9f7	2643	#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
<>	144:ef7eb2e8f9f7	2644	#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
<>	144:ef7eb2e8f9f7	2645	#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
<>	144:ef7eb2e8f9f7	2646	#define IS_RCC_HCLK_DIV IS_RCC_PCLK
<>	144:ef7eb2e8f9f7	2647	#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
<>	144:ef7eb2e8f9f7	2648
<>	144:ef7eb2e8f9f7	2649	#define RCC_IT_HSI14 RCC_IT_HSI14RDY
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	#if defined(STM32L0)
<>	144:ef7eb2e8f9f7	2652	#define RCC_IT_LSECSS RCC_IT_CSSLSE
<>	144:ef7eb2e8f9f7	2653	#define RCC_IT_CSS RCC_IT_CSSHSE
<>	144:ef7eb2e8f9f7	2654	#endif
<>	144:ef7eb2e8f9f7	2655
<>	144:ef7eb2e8f9f7	2656	#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
<>	144:ef7eb2e8f9f7	2657	#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
<>	144:ef7eb2e8f9f7	2658	#define RCC_MCO_NODIV RCC_MCODIV_1
<>	144:ef7eb2e8f9f7	2659	#define RCC_MCO_DIV1 RCC_MCODIV_1
<>	144:ef7eb2e8f9f7	2660	#define RCC_MCO_DIV2 RCC_MCODIV_2
<>	144:ef7eb2e8f9f7	2661	#define RCC_MCO_DIV4 RCC_MCODIV_4
<>	144:ef7eb2e8f9f7	2662	#define RCC_MCO_DIV8 RCC_MCODIV_8
<>	144:ef7eb2e8f9f7	2663	#define RCC_MCO_DIV16 RCC_MCODIV_16
<>	144:ef7eb2e8f9f7	2664	#define RCC_MCO_DIV32 RCC_MCODIV_32
<>	144:ef7eb2e8f9f7	2665	#define RCC_MCO_DIV64 RCC_MCODIV_64
<>	144:ef7eb2e8f9f7	2666	#define RCC_MCO_DIV128 RCC_MCODIV_128
<>	144:ef7eb2e8f9f7	2667	#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
<>	144:ef7eb2e8f9f7	2668	#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
<>	144:ef7eb2e8f9f7	2669	#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
<>	144:ef7eb2e8f9f7	2670	#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2671	#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
<>	144:ef7eb2e8f9f7	2672	#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
<>	144:ef7eb2e8f9f7	2673	#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
<>	144:ef7eb2e8f9f7	2674	#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
<>	144:ef7eb2e8f9f7	2675	#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
<>	144:ef7eb2e8f9f7	2676	#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
<>	144:ef7eb2e8f9f7	2677	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
<>	144:ef7eb2e8f9f7	2678
<>	144:ef7eb2e8f9f7	2679	#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
<>	144:ef7eb2e8f9f7	2680
<>	144:ef7eb2e8f9f7	2681	#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
<>	144:ef7eb2e8f9f7	2682	#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	2683	#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
<>	144:ef7eb2e8f9f7	2684	#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	2685	#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
<>	144:ef7eb2e8f9f7	2686	#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
<>	144:ef7eb2e8f9f7	2687	#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
<>	144:ef7eb2e8f9f7	2688	#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
<>	144:ef7eb2e8f9f7	2689
<>	144:ef7eb2e8f9f7	2690	#define HSION_BitNumber RCC_HSION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2691	#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2692	#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2693	#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2694	#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2695	#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2696	#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2697	#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2698	#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2699	#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2700	#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2701	#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2702	#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2703	#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2704	#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2705	#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2706	#define LSION_BitNumber RCC_LSION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2707	#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2708	#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2709	#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2710	#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2711	#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2712	#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2713	#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2714	#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2715	#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
<>	144:ef7eb2e8f9f7	2716	#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
<>	144:ef7eb2e8f9f7	2717	#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
<>	144:ef7eb2e8f9f7	2718	#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
<>	144:ef7eb2e8f9f7	2719	#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
<>	144:ef7eb2e8f9f7	2720	#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
<>	144:ef7eb2e8f9f7	2721	#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
<>	144:ef7eb2e8f9f7	2722
<>	144:ef7eb2e8f9f7	2723	#define CR_HSION_BB RCC_CR_HSION_BB
<>	144:ef7eb2e8f9f7	2724	#define CR_CSSON_BB RCC_CR_CSSON_BB
<>	144:ef7eb2e8f9f7	2725	#define CR_PLLON_BB RCC_CR_PLLON_BB
<>	144:ef7eb2e8f9f7	2726	#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
<>	144:ef7eb2e8f9f7	2727	#define CR_MSION_BB RCC_CR_MSION_BB
<>	144:ef7eb2e8f9f7	2728	#define CSR_LSION_BB RCC_CSR_LSION_BB
<>	144:ef7eb2e8f9f7	2729	#define CSR_LSEON_BB RCC_CSR_LSEON_BB
<>	144:ef7eb2e8f9f7	2730	#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
<>	144:ef7eb2e8f9f7	2731	#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
<>	144:ef7eb2e8f9f7	2732	#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
<>	144:ef7eb2e8f9f7	2733	#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
<>	144:ef7eb2e8f9f7	2734	#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
<>	144:ef7eb2e8f9f7	2735	#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
<>	144:ef7eb2e8f9f7	2736	#define CR_HSEON_BB RCC_CR_HSEON_BB
<>	144:ef7eb2e8f9f7	2737	#define CSR_RMVF_BB RCC_CSR_RMVF_BB
<>	144:ef7eb2e8f9f7	2738	#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
<>	144:ef7eb2e8f9f7	2739	#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
<>	144:ef7eb2e8f9f7	2740
<>	144:ef7eb2e8f9f7	2741	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
<>	144:ef7eb2e8f9f7	2742	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
<>	144:ef7eb2e8f9f7	2743	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
<>	144:ef7eb2e8f9f7	2744	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
<>	144:ef7eb2e8f9f7	2745	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
<>	144:ef7eb2e8f9f7	2746
<>	144:ef7eb2e8f9f7	2747	#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
<>	144:ef7eb2e8f9f7	2748
<>	144:ef7eb2e8f9f7	2749	#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
<>	144:ef7eb2e8f9f7	2750	#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
<>	144:ef7eb2e8f9f7	2751
<>	144:ef7eb2e8f9f7	2752	#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
<>	144:ef7eb2e8f9f7	2753	#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
<>	144:ef7eb2e8f9f7	2754	#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
<>	144:ef7eb2e8f9f7	2755	#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
<>	144:ef7eb2e8f9f7	2756	#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
<>	144:ef7eb2e8f9f7	2757	#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
<>	144:ef7eb2e8f9f7	2758
<>	144:ef7eb2e8f9f7	2759	#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
<>	144:ef7eb2e8f9f7	2760	#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
<>	144:ef7eb2e8f9f7	2761	#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
<>	144:ef7eb2e8f9f7	2762	#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
<>	144:ef7eb2e8f9f7	2763	#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
<>	144:ef7eb2e8f9f7	2764	#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
<>	144:ef7eb2e8f9f7	2765	#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
<>	144:ef7eb2e8f9f7	2766	#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
<>	144:ef7eb2e8f9f7	2767	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
<>	144:ef7eb2e8f9f7	2768	#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
<>	144:ef7eb2e8f9f7	2769	#define DfsdmClockSelection Dfsdm1ClockSelection
<>	144:ef7eb2e8f9f7	2770	#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
<>	144:ef7eb2e8f9f7	2771	#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
<>	144:ef7eb2e8f9f7	2772	#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
<>	144:ef7eb2e8f9f7	2773	#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
<>	144:ef7eb2e8f9f7	2774	#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
<>	144:ef7eb2e8f9f7	2775
<>	144:ef7eb2e8f9f7	2776	/**
<>	144:ef7eb2e8f9f7	2777	* @}
<>	144:ef7eb2e8f9f7	2778	*/
<>	144:ef7eb2e8f9f7	2779
<>	144:ef7eb2e8f9f7	2780	/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2781	* @{
<>	144:ef7eb2e8f9f7	2782	*/
<>	144:ef7eb2e8f9f7	2783	#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
<>	144:ef7eb2e8f9f7	2784
<>	144:ef7eb2e8f9f7	2785	/**
<>	144:ef7eb2e8f9f7	2786	* @}
<>	144:ef7eb2e8f9f7	2787	*/
<>	144:ef7eb2e8f9f7	2788
<>	144:ef7eb2e8f9f7	2789	/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2790	* @{
<>	144:ef7eb2e8f9f7	2791	*/
<>	144:ef7eb2e8f9f7	2792
<>	144:ef7eb2e8f9f7	2793	#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	2794	#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	2795	#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	2796
<>	144:ef7eb2e8f9f7	2797	#if defined (STM32F1)
<>	144:ef7eb2e8f9f7	2798	#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
<>	144:ef7eb2e8f9f7	2799
<>	144:ef7eb2e8f9f7	2800	#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
<>	144:ef7eb2e8f9f7	2801
<>	144:ef7eb2e8f9f7	2802	#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
<>	144:ef7eb2e8f9f7	2803
<>	144:ef7eb2e8f9f7	2804	#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
<>	144:ef7eb2e8f9f7	2805
<>	144:ef7eb2e8f9f7	2806	#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
<>	144:ef7eb2e8f9f7	2807	#else
<>	144:ef7eb2e8f9f7	2808	#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	2809	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
<>	144:ef7eb2e8f9f7	2810	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
<>	144:ef7eb2e8f9f7	2811	#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	2812	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
<>	144:ef7eb2e8f9f7	2813	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
<>	144:ef7eb2e8f9f7	2814	#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	2815	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
<>	144:ef7eb2e8f9f7	2816	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
<>	144:ef7eb2e8f9f7	2817	#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	2818	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
<>	144:ef7eb2e8f9f7	2819	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
<>	144:ef7eb2e8f9f7	2820	#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
<>	144:ef7eb2e8f9f7	2821	(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
<>	144:ef7eb2e8f9f7	2822	__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
<>	144:ef7eb2e8f9f7	2823	#endif /* STM32F1 */
<>	144:ef7eb2e8f9f7	2824
<>	144:ef7eb2e8f9f7	2825	#define IS_ALARM IS_RTC_ALARM
<>	144:ef7eb2e8f9f7	2826	#define IS_ALARM_MASK IS_RTC_ALARM_MASK
<>	144:ef7eb2e8f9f7	2827	#define IS_TAMPER IS_RTC_TAMPER
<>	144:ef7eb2e8f9f7	2828	#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
<>	144:ef7eb2e8f9f7	2829	#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
<>	144:ef7eb2e8f9f7	2830	#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
<>	144:ef7eb2e8f9f7	2831	#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
<>	144:ef7eb2e8f9f7	2832	#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
<>	144:ef7eb2e8f9f7	2833	#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
<>	144:ef7eb2e8f9f7	2834	#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
<>	144:ef7eb2e8f9f7	2835	#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
<>	144:ef7eb2e8f9f7	2836	#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
<>	144:ef7eb2e8f9f7	2837	#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
<>	144:ef7eb2e8f9f7	2838	#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
<>	144:ef7eb2e8f9f7	2839
<>	144:ef7eb2e8f9f7	2840	#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
<>	144:ef7eb2e8f9f7	2841	#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
<>	144:ef7eb2e8f9f7	2842
<>	144:ef7eb2e8f9f7	2843	/**
<>	144:ef7eb2e8f9f7	2844	* @}
<>	144:ef7eb2e8f9f7	2845	*/
<>	144:ef7eb2e8f9f7	2846
<>	144:ef7eb2e8f9f7	2847	/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2848	* @{
<>	144:ef7eb2e8f9f7	2849	*/
<>	144:ef7eb2e8f9f7	2850
<>	144:ef7eb2e8f9f7	2851	#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
<>	144:ef7eb2e8f9f7	2852	#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
<>	144:ef7eb2e8f9f7	2853
<>	144:ef7eb2e8f9f7	2854	#if defined(STM32F4)
<>	144:ef7eb2e8f9f7	2855	#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
<>	144:ef7eb2e8f9f7	2856	#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
<>	144:ef7eb2e8f9f7	2857	#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
<>	144:ef7eb2e8f9f7	2858	#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
<>	144:ef7eb2e8f9f7	2859	#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
<>	144:ef7eb2e8f9f7	2860	#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
<>	144:ef7eb2e8f9f7	2861	#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
<>	144:ef7eb2e8f9f7	2862	#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
<>	144:ef7eb2e8f9f7	2863	#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
<>	144:ef7eb2e8f9f7	2864	#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
<>	144:ef7eb2e8f9f7	2865	#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
<>	144:ef7eb2e8f9f7	2866	#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
<>	144:ef7eb2e8f9f7	2867	#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
<>	144:ef7eb2e8f9f7	2868	#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
<>	144:ef7eb2e8f9f7	2869	#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	2870	#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
<>	144:ef7eb2e8f9f7	2871	#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
<>	144:ef7eb2e8f9f7	2872	#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
<>	144:ef7eb2e8f9f7	2873	#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
<>	144:ef7eb2e8f9f7	2874	#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
<>	144:ef7eb2e8f9f7	2875	/* alias CMSIS */
<>	144:ef7eb2e8f9f7	2876	#define SDMMC1_IRQn SDIO_IRQn
<>	144:ef7eb2e8f9f7	2877	#define SDMMC1_IRQHandler SDIO_IRQHandler
<>	144:ef7eb2e8f9f7	2878	#endif
<>	144:ef7eb2e8f9f7	2879
<>	144:ef7eb2e8f9f7	2880	#if defined(STM32F7) \|\| defined(STM32L4)
<>	144:ef7eb2e8f9f7	2881	#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
<>	144:ef7eb2e8f9f7	2882	#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
<>	144:ef7eb2e8f9f7	2883	#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
<>	144:ef7eb2e8f9f7	2884	#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
<>	144:ef7eb2e8f9f7	2885	#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
<>	144:ef7eb2e8f9f7	2886	#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
<>	144:ef7eb2e8f9f7	2887	#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
<>	144:ef7eb2e8f9f7	2888	#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
<>	144:ef7eb2e8f9f7	2889	#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
<>	144:ef7eb2e8f9f7	2890	#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
<>	144:ef7eb2e8f9f7	2891	#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
<>	144:ef7eb2e8f9f7	2892	#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
<>	144:ef7eb2e8f9f7	2893	#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
<>	144:ef7eb2e8f9f7	2894	#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
<>	144:ef7eb2e8f9f7	2895	#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	2896	#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
<>	144:ef7eb2e8f9f7	2897	#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
<>	144:ef7eb2e8f9f7	2898	#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
<>	144:ef7eb2e8f9f7	2899	#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
<>	144:ef7eb2e8f9f7	2900	#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
<>	144:ef7eb2e8f9f7	2901	/* alias CMSIS for compatibilities */
<>	144:ef7eb2e8f9f7	2902	#define SDIO_IRQn SDMMC1_IRQn
<>	144:ef7eb2e8f9f7	2903	#define SDIO_IRQHandler SDMMC1_IRQHandler
<>	144:ef7eb2e8f9f7	2904	#endif
<>	144:ef7eb2e8f9f7	2905	/**
<>	144:ef7eb2e8f9f7	2906	* @}
<>	144:ef7eb2e8f9f7	2907	*/
<>	144:ef7eb2e8f9f7	2908
<>	144:ef7eb2e8f9f7	2909	/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2910	* @{
<>	144:ef7eb2e8f9f7	2911	*/
<>	144:ef7eb2e8f9f7	2912
<>	144:ef7eb2e8f9f7	2913	#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
<>	144:ef7eb2e8f9f7	2914	#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
<>	144:ef7eb2e8f9f7	2915	#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
<>	144:ef7eb2e8f9f7	2916	#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
<>	144:ef7eb2e8f9f7	2917	#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
<>	144:ef7eb2e8f9f7	2918	#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
<>	144:ef7eb2e8f9f7	2919
<>	144:ef7eb2e8f9f7	2920	#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2921	#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2922
<>	144:ef7eb2e8f9f7	2923	#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
<>	144:ef7eb2e8f9f7	2924
<>	144:ef7eb2e8f9f7	2925	/**
<>	144:ef7eb2e8f9f7	2926	* @}
<>	144:ef7eb2e8f9f7	2927	*/
<>	144:ef7eb2e8f9f7	2928
<>	144:ef7eb2e8f9f7	2929	/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2930	* @{
<>	144:ef7eb2e8f9f7	2931	*/
<>	144:ef7eb2e8f9f7	2932	#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
<>	144:ef7eb2e8f9f7	2933	#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
<>	144:ef7eb2e8f9f7	2934	#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
<>	144:ef7eb2e8f9f7	2935	#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
<>	144:ef7eb2e8f9f7	2936	#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
<>	144:ef7eb2e8f9f7	2937	#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
<>	144:ef7eb2e8f9f7	2938	#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
<>	144:ef7eb2e8f9f7	2939	#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
<>	144:ef7eb2e8f9f7	2940	/**
<>	144:ef7eb2e8f9f7	2941	* @}
<>	144:ef7eb2e8f9f7	2942	*/
<>	144:ef7eb2e8f9f7	2943
<>	144:ef7eb2e8f9f7	2944	/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2945	* @{
<>	144:ef7eb2e8f9f7	2946	*/
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
<>	144:ef7eb2e8f9f7	2949	#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
<>	144:ef7eb2e8f9f7	2950	#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
<>	144:ef7eb2e8f9f7	2951
<>	144:ef7eb2e8f9f7	2952	/**
<>	144:ef7eb2e8f9f7	2953	* @}
<>	144:ef7eb2e8f9f7	2954	*/
<>	144:ef7eb2e8f9f7	2955
<>	144:ef7eb2e8f9f7	2956	/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2957	* @{
<>	144:ef7eb2e8f9f7	2958	*/
<>	144:ef7eb2e8f9f7	2959
<>	144:ef7eb2e8f9f7	2960	#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2961	#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<>	144:ef7eb2e8f9f7	2962	#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2963	#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
<>	144:ef7eb2e8f9f7	2964
<>	144:ef7eb2e8f9f7	2965	#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
<>	144:ef7eb2e8f9f7	2966
<>	144:ef7eb2e8f9f7	2967	#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
<>	144:ef7eb2e8f9f7	2968	#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
<>	144:ef7eb2e8f9f7	2969
<>	144:ef7eb2e8f9f7	2970	/**
<>	144:ef7eb2e8f9f7	2971	* @}
<>	144:ef7eb2e8f9f7	2972	*/
<>	144:ef7eb2e8f9f7	2973
<>	144:ef7eb2e8f9f7	2974
<>	144:ef7eb2e8f9f7	2975	/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2976	* @{
<>	144:ef7eb2e8f9f7	2977	*/
<>	144:ef7eb2e8f9f7	2978
<>	144:ef7eb2e8f9f7	2979	#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
<>	144:ef7eb2e8f9f7	2980	#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
<>	144:ef7eb2e8f9f7	2981	#define __USART_ENABLE __HAL_USART_ENABLE
<>	144:ef7eb2e8f9f7	2982	#define __USART_DISABLE __HAL_USART_DISABLE
<>	144:ef7eb2e8f9f7	2983
<>	144:ef7eb2e8f9f7	2984	#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2985	#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
<>	144:ef7eb2e8f9f7	2986
<>	144:ef7eb2e8f9f7	2987	/**
<>	144:ef7eb2e8f9f7	2988	* @}
<>	144:ef7eb2e8f9f7	2989	*/
<>	144:ef7eb2e8f9f7	2990
<>	144:ef7eb2e8f9f7	2991	/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	2992	* @{
<>	144:ef7eb2e8f9f7	2993	*/
<>	144:ef7eb2e8f9f7	2994	#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
<>	144:ef7eb2e8f9f7	2995
<>	144:ef7eb2e8f9f7	2996	#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
<>	144:ef7eb2e8f9f7	2997	#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
<>	144:ef7eb2e8f9f7	2998	#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
<>	144:ef7eb2e8f9f7	2999	#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
<>	144:ef7eb2e8f9f7	3002	#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3003	#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3004	#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
<>	144:ef7eb2e8f9f7	3005
<>	144:ef7eb2e8f9f7	3006	#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	3007	#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	3008	#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
<>	144:ef7eb2e8f9f7	3009	#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	3010	#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	3011	#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3012	#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3013
<>	144:ef7eb2e8f9f7	3014	#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	3015	#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	3016	#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
<>	144:ef7eb2e8f9f7	3017	#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	3018	#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	3019	#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3020	#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3021	#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
<>	144:ef7eb2e8f9f7	3022
<>	144:ef7eb2e8f9f7	3023	#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	3024	#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	3025	#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
<>	144:ef7eb2e8f9f7	3026	#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	3027	#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
<>	144:ef7eb2e8f9f7	3028	#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3029	#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
<>	144:ef7eb2e8f9f7	3030	#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
<>	144:ef7eb2e8f9f7	3031
<>	144:ef7eb2e8f9f7	3032	#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
<>	144:ef7eb2e8f9f7	3033	#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
<>	144:ef7eb2e8f9f7	3034
<>	144:ef7eb2e8f9f7	3035	#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
<>	144:ef7eb2e8f9f7	3036	#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
<>	144:ef7eb2e8f9f7	3037	/**
<>	144:ef7eb2e8f9f7	3038	* @}
<>	144:ef7eb2e8f9f7	3039	*/
<>	144:ef7eb2e8f9f7	3040
<>	144:ef7eb2e8f9f7	3041	/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	3042	* @{
<>	144:ef7eb2e8f9f7	3043	*/
<>	144:ef7eb2e8f9f7	3044	#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
<>	144:ef7eb2e8f9f7	3045	#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
<>	144:ef7eb2e8f9f7	3046
<>	144:ef7eb2e8f9f7	3047	#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<>	144:ef7eb2e8f9f7	3048	#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
<>	144:ef7eb2e8f9f7	3049
<>	144:ef7eb2e8f9f7	3050	#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
<>	144:ef7eb2e8f9f7	3051
<>	144:ef7eb2e8f9f7	3052	#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
<>	144:ef7eb2e8f9f7	3053	#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
<>	144:ef7eb2e8f9f7	3054	#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
<>	144:ef7eb2e8f9f7	3055	#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
<>	144:ef7eb2e8f9f7	3056	#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
<>	144:ef7eb2e8f9f7	3057	#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
<>	144:ef7eb2e8f9f7	3058	#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
<>	144:ef7eb2e8f9f7	3059	#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
<>	144:ef7eb2e8f9f7	3060	#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
<>	144:ef7eb2e8f9f7	3061	#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
<>	144:ef7eb2e8f9f7	3062	#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
<>	144:ef7eb2e8f9f7	3063	#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
<>	144:ef7eb2e8f9f7	3064
<>	144:ef7eb2e8f9f7	3065	#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
<>	144:ef7eb2e8f9f7	3066	/**
<>	144:ef7eb2e8f9f7	3067	* @}
<>	144:ef7eb2e8f9f7	3068	*/
<>	144:ef7eb2e8f9f7	3069
<>	144:ef7eb2e8f9f7	3070	/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	3071	* @{
<>	144:ef7eb2e8f9f7	3072	*/
<>	144:ef7eb2e8f9f7	3073
<>	144:ef7eb2e8f9f7	3074	#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
<>	144:ef7eb2e8f9f7	3075	#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
<>	144:ef7eb2e8f9f7	3076	#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
<>	144:ef7eb2e8f9f7	3077	#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
<>	144:ef7eb2e8f9f7	3078	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
<>	144:ef7eb2e8f9f7	3079	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
<>	144:ef7eb2e8f9f7	3080	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
<>	144:ef7eb2e8f9f7	3081
<>	144:ef7eb2e8f9f7	3082	#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
<>	144:ef7eb2e8f9f7	3083	#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
<>	144:ef7eb2e8f9f7	3084	#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
<>	144:ef7eb2e8f9f7	3085	/**
<>	144:ef7eb2e8f9f7	3086	* @}
<>	144:ef7eb2e8f9f7	3087	*/
<>	144:ef7eb2e8f9f7	3088
<>	144:ef7eb2e8f9f7	3089	/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	3090	* @{
<>	144:ef7eb2e8f9f7	3091	*/
<>	144:ef7eb2e8f9f7	3092	#define __HAL_LTDC_LAYER LTDC_LAYER
<>	144:ef7eb2e8f9f7	3093	/**
<>	144:ef7eb2e8f9f7	3094	* @}
<>	144:ef7eb2e8f9f7	3095	*/
<>	144:ef7eb2e8f9f7	3096
<>	144:ef7eb2e8f9f7	3097	/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	3098	* @{
<>	144:ef7eb2e8f9f7	3099	*/
<>	144:ef7eb2e8f9f7	3100	#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
<>	144:ef7eb2e8f9f7	3101	#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
<>	144:ef7eb2e8f9f7	3102	#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
<>	144:ef7eb2e8f9f7	3103	#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
<>	144:ef7eb2e8f9f7	3104	#define SAI_STREOMODE SAI_STEREOMODE
<>	144:ef7eb2e8f9f7	3105	#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
<>	144:ef7eb2e8f9f7	3106	#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
<>	144:ef7eb2e8f9f7	3107	#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
<>	144:ef7eb2e8f9f7	3108	#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
<>	144:ef7eb2e8f9f7	3109	#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
<>	144:ef7eb2e8f9f7	3110	#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
<>	144:ef7eb2e8f9f7	3111	#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
<>	144:ef7eb2e8f9f7	3112	#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
<>	144:ef7eb2e8f9f7	3113	#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
<>	144:ef7eb2e8f9f7	3114	/**
<>	144:ef7eb2e8f9f7	3115	* @}
<>	144:ef7eb2e8f9f7	3116	*/
<>	144:ef7eb2e8f9f7	3117
<>	144:ef7eb2e8f9f7	3118
<>	144:ef7eb2e8f9f7	3119	/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
<>	144:ef7eb2e8f9f7	3120	* @{
<>	144:ef7eb2e8f9f7	3121	*/
<>	144:ef7eb2e8f9f7	3122
<>	144:ef7eb2e8f9f7	3123	/**
<>	144:ef7eb2e8f9f7	3124	* @}
<>	144:ef7eb2e8f9f7	3125	*/
<>	144:ef7eb2e8f9f7	3126
<>	144:ef7eb2e8f9f7	3127	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	3128	}
<>	144:ef7eb2e8f9f7	3129	#endif
<>	144:ef7eb2e8f9f7	3130
<>	144:ef7eb2e8f9f7	3131	#endif /* ___STM32_HAL_LEGACY */
<>	144:ef7eb2e8f9f7	3132
<>	144:ef7eb2e8f9f7	3133	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	3134