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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_i2c.h@167:e84263d55307, 2017-06-21 (annotated)

Committer:: AnnaBridge
Date:: Wed Jun 21 17:46:44 2017 +0100
Revision:: 167:e84263d55307

This updates the lib to the mbed lib v 145

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	167:e84263d55307	1	/**
AnnaBridge	167:e84263d55307	2	******************************************************************************
AnnaBridge	167:e84263d55307	3	* @file stm32f2xx_ll_i2c.h
AnnaBridge	167:e84263d55307	4	* @author MCD Application Team
AnnaBridge	167:e84263d55307	5	* @version V1.2.1
AnnaBridge	167:e84263d55307	6	* @date 14-April-2017
AnnaBridge	167:e84263d55307	7	* @brief Header file of I2C LL module.
AnnaBridge	167:e84263d55307	8	******************************************************************************
AnnaBridge	167:e84263d55307	9	* @attention
AnnaBridge	167:e84263d55307	10	*
AnnaBridge	167:e84263d55307	11	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	167:e84263d55307	12	*
AnnaBridge	167:e84263d55307	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	167:e84263d55307	14	* are permitted provided that the following conditions are met:
AnnaBridge	167:e84263d55307	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	167:e84263d55307	16	* this list of conditions and the following disclaimer.
AnnaBridge	167:e84263d55307	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	167:e84263d55307	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	167:e84263d55307	19	* and/or other materials provided with the distribution.
AnnaBridge	167:e84263d55307	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	167:e84263d55307	21	* may be used to endorse or promote products derived from this software
AnnaBridge	167:e84263d55307	22	* without specific prior written permission.
AnnaBridge	167:e84263d55307	23	*
AnnaBridge	167:e84263d55307	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	167:e84263d55307	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	167:e84263d55307	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	167:e84263d55307	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	167:e84263d55307	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	167:e84263d55307	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	167:e84263d55307	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	167:e84263d55307	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	167:e84263d55307	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	167:e84263d55307	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	167:e84263d55307	34	*
AnnaBridge	167:e84263d55307	35	******************************************************************************
AnnaBridge	167:e84263d55307	36	*/
AnnaBridge	167:e84263d55307	37
AnnaBridge	167:e84263d55307	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	167:e84263d55307	39	#ifndef __STM32F2xx_LL_I2C_H
AnnaBridge	167:e84263d55307	40	#define __STM32F2xx_LL_I2C_H
AnnaBridge	167:e84263d55307	41
AnnaBridge	167:e84263d55307	42	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	43	extern "C" {
AnnaBridge	167:e84263d55307	44	#endif
AnnaBridge	167:e84263d55307	45
AnnaBridge	167:e84263d55307	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	47	#include "stm32f2xx.h"
AnnaBridge	167:e84263d55307	48
AnnaBridge	167:e84263d55307	49	/** @addtogroup STM32F2xx_LL_Driver
AnnaBridge	167:e84263d55307	50	* @{
AnnaBridge	167:e84263d55307	51	*/
AnnaBridge	167:e84263d55307	52
AnnaBridge	167:e84263d55307	53	#if defined (I2C1) \|\| defined (I2C2) \|\| defined (I2C3)
AnnaBridge	167:e84263d55307	54
AnnaBridge	167:e84263d55307	55	/** @defgroup I2C_LL I2C
AnnaBridge	167:e84263d55307	56	* @{
AnnaBridge	167:e84263d55307	57	*/
AnnaBridge	167:e84263d55307	58
AnnaBridge	167:e84263d55307	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	61
AnnaBridge	167:e84263d55307	62	/* Private constants ---------------------------------------------------------*/
AnnaBridge	167:e84263d55307	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge	167:e84263d55307	64	* @{
AnnaBridge	167:e84263d55307	65	*/
AnnaBridge	167:e84263d55307	66
AnnaBridge	167:e84263d55307	67	/* Defines used to perform compute and check in the macros */
AnnaBridge	167:e84263d55307	68	#define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge	167:e84263d55307	69	#define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge	167:e84263d55307	70	/**
AnnaBridge	167:e84263d55307	71	* @}
AnnaBridge	167:e84263d55307	72	*/
AnnaBridge	167:e84263d55307	73
AnnaBridge	167:e84263d55307	74	/* Private macros ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	75	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	76	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge	167:e84263d55307	77	* @{
AnnaBridge	167:e84263d55307	78	*/
AnnaBridge	167:e84263d55307	79	/**
AnnaBridge	167:e84263d55307	80	* @}
AnnaBridge	167:e84263d55307	81	*/
AnnaBridge	167:e84263d55307	82	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	83
AnnaBridge	167:e84263d55307	84	/* Exported types ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	85	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	86	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge	167:e84263d55307	87	* @{
AnnaBridge	167:e84263d55307	88	*/
AnnaBridge	167:e84263d55307	89	typedef struct
AnnaBridge	167:e84263d55307	90	{
AnnaBridge	167:e84263d55307	91	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge	167:e84263d55307	92	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge	167:e84263d55307	93
AnnaBridge	167:e84263d55307	94	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge	167:e84263d55307	95
AnnaBridge	167:e84263d55307	96	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge	167:e84263d55307	97	This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge	167:e84263d55307	98
AnnaBridge	167:e84263d55307	99	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge	167:e84263d55307	100	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge	167:e84263d55307	101
AnnaBridge	167:e84263d55307	102	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge	167:e84263d55307	103	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge	167:e84263d55307	104
AnnaBridge	167:e84263d55307	105	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge	167:e84263d55307	106
AnnaBridge	167:e84263d55307	107	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge	167:e84263d55307	108	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge	167:e84263d55307	109
AnnaBridge	167:e84263d55307	110	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	167:e84263d55307	111
AnnaBridge	167:e84263d55307	112	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	167:e84263d55307	113	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge	167:e84263d55307	114
AnnaBridge	167:e84263d55307	115	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge	167:e84263d55307	116
AnnaBridge	167:e84263d55307	117	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge	167:e84263d55307	118	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge	167:e84263d55307	119
AnnaBridge	167:e84263d55307	120	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	167:e84263d55307	121	} LL_I2C_InitTypeDef;
AnnaBridge	167:e84263d55307	122	/**
AnnaBridge	167:e84263d55307	123	* @}
AnnaBridge	167:e84263d55307	124	*/
AnnaBridge	167:e84263d55307	125	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	167:e84263d55307	126
AnnaBridge	167:e84263d55307	127	/* Exported constants --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	128	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge	167:e84263d55307	129	* @{
AnnaBridge	167:e84263d55307	130	*/
AnnaBridge	167:e84263d55307	131
AnnaBridge	167:e84263d55307	132	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	167:e84263d55307	133	* @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge	167:e84263d55307	134	* @{
AnnaBridge	167:e84263d55307	135	*/
AnnaBridge	167:e84263d55307	136	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
AnnaBridge	167:e84263d55307	137	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge	167:e84263d55307	138	Address matched flag (slave mode) */
AnnaBridge	167:e84263d55307	139	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
AnnaBridge	167:e84263d55307	140	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
AnnaBridge	167:e84263d55307	141	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
AnnaBridge	167:e84263d55307	142	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
AnnaBridge	167:e84263d55307	143	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
AnnaBridge	167:e84263d55307	144	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
AnnaBridge	167:e84263d55307	145	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
AnnaBridge	167:e84263d55307	146	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
AnnaBridge	167:e84263d55307	147	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
AnnaBridge	167:e84263d55307	148	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
AnnaBridge	167:e84263d55307	149	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
AnnaBridge	167:e84263d55307	150	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
AnnaBridge	167:e84263d55307	151	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
AnnaBridge	167:e84263d55307	152	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
AnnaBridge	167:e84263d55307	153	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
AnnaBridge	167:e84263d55307	154	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
AnnaBridge	167:e84263d55307	155	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
AnnaBridge	167:e84263d55307	156	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
AnnaBridge	167:e84263d55307	157	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
AnnaBridge	167:e84263d55307	158	/**
AnnaBridge	167:e84263d55307	159	* @}
AnnaBridge	167:e84263d55307	160	*/
AnnaBridge	167:e84263d55307	161
AnnaBridge	167:e84263d55307	162	/** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge	167:e84263d55307	163	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge	167:e84263d55307	164	* @{
AnnaBridge	167:e84263d55307	165	*/
AnnaBridge	167:e84263d55307	166	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
AnnaBridge	167:e84263d55307	167	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
AnnaBridge	167:e84263d55307	168	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
AnnaBridge	167:e84263d55307	169	/**
AnnaBridge	167:e84263d55307	170	* @}
AnnaBridge	167:e84263d55307	171	*/
AnnaBridge	167:e84263d55307	172
AnnaBridge	167:e84263d55307	173	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge	167:e84263d55307	174	* @{
AnnaBridge	167:e84263d55307	175	*/
AnnaBridge	167:e84263d55307	176	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
AnnaBridge	167:e84263d55307	177	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
AnnaBridge	167:e84263d55307	178	/**
AnnaBridge	167:e84263d55307	179	* @}
AnnaBridge	167:e84263d55307	180	*/
AnnaBridge	167:e84263d55307	181
AnnaBridge	167:e84263d55307	182	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge	167:e84263d55307	183	* @{
AnnaBridge	167:e84263d55307	184	*/
AnnaBridge	167:e84263d55307	185	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
AnnaBridge	167:e84263d55307	186	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
AnnaBridge	167:e84263d55307	187	/**
AnnaBridge	167:e84263d55307	188	* @}
AnnaBridge	167:e84263d55307	189	*/
AnnaBridge	167:e84263d55307	190
AnnaBridge	167:e84263d55307	191	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge	167:e84263d55307	192	* @{
AnnaBridge	167:e84263d55307	193	*/
AnnaBridge	167:e84263d55307	194	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
AnnaBridge	167:e84263d55307	195	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
AnnaBridge	167:e84263d55307	196	/**
AnnaBridge	167:e84263d55307	197	* @}
AnnaBridge	167:e84263d55307	198	*/
AnnaBridge	167:e84263d55307	199
AnnaBridge	167:e84263d55307	200	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge	167:e84263d55307	201	* @{
AnnaBridge	167:e84263d55307	202	*/
AnnaBridge	167:e84263d55307	203	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
AnnaBridge	167:e84263d55307	204	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
AnnaBridge	167:e84263d55307	205	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
AnnaBridge	167:e84263d55307	206	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
AnnaBridge	167:e84263d55307	207	/**
AnnaBridge	167:e84263d55307	208	* @}
AnnaBridge	167:e84263d55307	209	*/
AnnaBridge	167:e84263d55307	210
AnnaBridge	167:e84263d55307	211	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge	167:e84263d55307	212	* @{
AnnaBridge	167:e84263d55307	213	*/
AnnaBridge	167:e84263d55307	214	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
AnnaBridge	167:e84263d55307	215	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
AnnaBridge	167:e84263d55307	216	/**
AnnaBridge	167:e84263d55307	217	* @}
AnnaBridge	167:e84263d55307	218	*/
AnnaBridge	167:e84263d55307	219
AnnaBridge	167:e84263d55307	220	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge	167:e84263d55307	221	* @{
AnnaBridge	167:e84263d55307	222	*/
AnnaBridge	167:e84263d55307	223	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
AnnaBridge	167:e84263d55307	224	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
AnnaBridge	167:e84263d55307	225	/**
AnnaBridge	167:e84263d55307	226	* @}
AnnaBridge	167:e84263d55307	227	*/
AnnaBridge	167:e84263d55307	228
AnnaBridge	167:e84263d55307	229	/**
AnnaBridge	167:e84263d55307	230	* @}
AnnaBridge	167:e84263d55307	231	*/
AnnaBridge	167:e84263d55307	232
AnnaBridge	167:e84263d55307	233	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	167:e84263d55307	234	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge	167:e84263d55307	235	* @{
AnnaBridge	167:e84263d55307	236	*/
AnnaBridge	167:e84263d55307	237
AnnaBridge	167:e84263d55307	238	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	167:e84263d55307	239	* @{
AnnaBridge	167:e84263d55307	240	*/
AnnaBridge	167:e84263d55307	241
AnnaBridge	167:e84263d55307	242	/**
AnnaBridge	167:e84263d55307	243	* @brief Write a value in I2C register
AnnaBridge	167:e84263d55307	244	* @param __INSTANCE__ I2C Instance
AnnaBridge	167:e84263d55307	245	* @param __REG__ Register to be written
AnnaBridge	167:e84263d55307	246	* @param __VALUE__ Value to be written in the register
AnnaBridge	167:e84263d55307	247	* @retval None
AnnaBridge	167:e84263d55307	248	*/
AnnaBridge	167:e84263d55307	249	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	167:e84263d55307	250
AnnaBridge	167:e84263d55307	251	/**
AnnaBridge	167:e84263d55307	252	* @brief Read a value in I2C register
AnnaBridge	167:e84263d55307	253	* @param __INSTANCE__ I2C Instance
AnnaBridge	167:e84263d55307	254	* @param __REG__ Register to be read
AnnaBridge	167:e84263d55307	255	* @retval Register value
AnnaBridge	167:e84263d55307	256	*/
AnnaBridge	167:e84263d55307	257	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	167:e84263d55307	258	/**
AnnaBridge	167:e84263d55307	259	* @}
AnnaBridge	167:e84263d55307	260	*/
AnnaBridge	167:e84263d55307	261
AnnaBridge	167:e84263d55307	262	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge	167:e84263d55307	263	* @{
AnnaBridge	167:e84263d55307	264	*/
AnnaBridge	167:e84263d55307	265
AnnaBridge	167:e84263d55307	266	/**
AnnaBridge	167:e84263d55307	267	* @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge	167:e84263d55307	268	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	167:e84263d55307	269	* @retval Value of peripheral clock (in Mhz)
AnnaBridge	167:e84263d55307	270	*/
AnnaBridge	167:e84263d55307	271	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge	167:e84263d55307	272
AnnaBridge	167:e84263d55307	273	/**
AnnaBridge	167:e84263d55307	274	* @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge	167:e84263d55307	275	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	167:e84263d55307	276	* @retval Value of peripheral clock (in Hz)
AnnaBridge	167:e84263d55307	277	*/
AnnaBridge	167:e84263d55307	278	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge	167:e84263d55307	279
AnnaBridge	167:e84263d55307	280	/**
AnnaBridge	167:e84263d55307	281	* @brief Compute I2C Clock rising time.
AnnaBridge	167:e84263d55307	282	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	167:e84263d55307	283	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	167:e84263d55307	284	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	167:e84263d55307	285	*/
AnnaBridge	167:e84263d55307	286	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge	167:e84263d55307	287
AnnaBridge	167:e84263d55307	288	/**
AnnaBridge	167:e84263d55307	289	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	167:e84263d55307	290	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	167:e84263d55307	291	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	167:e84263d55307	292	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	293	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	167:e84263d55307	294	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	167:e84263d55307	295	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	167:e84263d55307	296	*/
AnnaBridge	167:e84263d55307	297	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge	167:e84263d55307	298	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge	167:e84263d55307	299	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge	167:e84263d55307	300
AnnaBridge	167:e84263d55307	301	/**
AnnaBridge	167:e84263d55307	302	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	167:e84263d55307	303	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	167:e84263d55307	304	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge	167:e84263d55307	305	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge	167:e84263d55307	306	*/
AnnaBridge	167:e84263d55307	307	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge	167:e84263d55307	308
AnnaBridge	167:e84263d55307	309	/**
AnnaBridge	167:e84263d55307	310	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	167:e84263d55307	311	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	167:e84263d55307	312	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge	167:e84263d55307	313	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	314	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	167:e84263d55307	315	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	167:e84263d55307	316	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge	167:e84263d55307	317	*/
AnnaBridge	167:e84263d55307	318	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge	167:e84263d55307	319	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge	167:e84263d55307	320	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge	167:e84263d55307	321
AnnaBridge	167:e84263d55307	322	/**
AnnaBridge	167:e84263d55307	323	* @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge	167:e84263d55307	324	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	167:e84263d55307	325	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	326	*/
AnnaBridge	167:e84263d55307	327	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge	167:e84263d55307	328
AnnaBridge	167:e84263d55307	329	/**
AnnaBridge	167:e84263d55307	330	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge	167:e84263d55307	331	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	167:e84263d55307	332	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge	167:e84263d55307	333	*/
AnnaBridge	167:e84263d55307	334	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
AnnaBridge	167:e84263d55307	335
AnnaBridge	167:e84263d55307	336	/**
AnnaBridge	167:e84263d55307	337	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge	167:e84263d55307	338	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	167:e84263d55307	339	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge	167:e84263d55307	340	*/
AnnaBridge	167:e84263d55307	341	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
AnnaBridge	167:e84263d55307	342
AnnaBridge	167:e84263d55307	343	/**
AnnaBridge	167:e84263d55307	344	* @}
AnnaBridge	167:e84263d55307	345	*/
AnnaBridge	167:e84263d55307	346
AnnaBridge	167:e84263d55307	347	/**
AnnaBridge	167:e84263d55307	348	* @}
AnnaBridge	167:e84263d55307	349	*/
AnnaBridge	167:e84263d55307	350
AnnaBridge	167:e84263d55307	351	/* Exported functions --------------------------------------------------------*/
AnnaBridge	167:e84263d55307	352
AnnaBridge	167:e84263d55307	353	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge	167:e84263d55307	354	* @{
AnnaBridge	167:e84263d55307	355	*/
AnnaBridge	167:e84263d55307	356
AnnaBridge	167:e84263d55307	357	/** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge	167:e84263d55307	358	* @{
AnnaBridge	167:e84263d55307	359	*/
AnnaBridge	167:e84263d55307	360
AnnaBridge	167:e84263d55307	361	/**
AnnaBridge	167:e84263d55307	362	* @brief Enable I2C peripheral (PE = 1).
AnnaBridge	167:e84263d55307	363	* @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge	167:e84263d55307	364	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	365	* @retval None
AnnaBridge	167:e84263d55307	366	*/
AnnaBridge	167:e84263d55307	367	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	368	{
AnnaBridge	167:e84263d55307	369	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	167:e84263d55307	370	}
AnnaBridge	167:e84263d55307	371
AnnaBridge	167:e84263d55307	372	/**
AnnaBridge	167:e84263d55307	373	* @brief Disable I2C peripheral (PE = 0).
AnnaBridge	167:e84263d55307	374	* @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge	167:e84263d55307	375	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	376	* @retval None
AnnaBridge	167:e84263d55307	377	*/
AnnaBridge	167:e84263d55307	378	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	379	{
AnnaBridge	167:e84263d55307	380	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	167:e84263d55307	381	}
AnnaBridge	167:e84263d55307	382
AnnaBridge	167:e84263d55307	383	/**
AnnaBridge	167:e84263d55307	384	* @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge	167:e84263d55307	385	* @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge	167:e84263d55307	386	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	387	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	388	*/
AnnaBridge	167:e84263d55307	389	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	390	{
AnnaBridge	167:e84263d55307	391	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge	167:e84263d55307	392	}
AnnaBridge	167:e84263d55307	393
AnnaBridge	167:e84263d55307	394
AnnaBridge	167:e84263d55307	395	/**
AnnaBridge	167:e84263d55307	396	* @brief Enable DMA transmission requests.
AnnaBridge	167:e84263d55307	397	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge	167:e84263d55307	398	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	399	* @retval None
AnnaBridge	167:e84263d55307	400	*/
AnnaBridge	167:e84263d55307	401	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	402	{
AnnaBridge	167:e84263d55307	403	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	167:e84263d55307	404	}
AnnaBridge	167:e84263d55307	405
AnnaBridge	167:e84263d55307	406	/**
AnnaBridge	167:e84263d55307	407	* @brief Disable DMA transmission requests.
AnnaBridge	167:e84263d55307	408	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge	167:e84263d55307	409	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	410	* @retval None
AnnaBridge	167:e84263d55307	411	*/
AnnaBridge	167:e84263d55307	412	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	413	{
AnnaBridge	167:e84263d55307	414	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	167:e84263d55307	415	}
AnnaBridge	167:e84263d55307	416
AnnaBridge	167:e84263d55307	417	/**
AnnaBridge	167:e84263d55307	418	* @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge	167:e84263d55307	419	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge	167:e84263d55307	420	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	421	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	422	*/
AnnaBridge	167:e84263d55307	423	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	424	{
AnnaBridge	167:e84263d55307	425	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	167:e84263d55307	426	}
AnnaBridge	167:e84263d55307	427
AnnaBridge	167:e84263d55307	428	/**
AnnaBridge	167:e84263d55307	429	* @brief Enable DMA reception requests.
AnnaBridge	167:e84263d55307	430	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge	167:e84263d55307	431	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	432	* @retval None
AnnaBridge	167:e84263d55307	433	*/
AnnaBridge	167:e84263d55307	434	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	435	{
AnnaBridge	167:e84263d55307	436	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	167:e84263d55307	437	}
AnnaBridge	167:e84263d55307	438
AnnaBridge	167:e84263d55307	439	/**
AnnaBridge	167:e84263d55307	440	* @brief Disable DMA reception requests.
AnnaBridge	167:e84263d55307	441	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge	167:e84263d55307	442	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	443	* @retval None
AnnaBridge	167:e84263d55307	444	*/
AnnaBridge	167:e84263d55307	445	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	446	{
AnnaBridge	167:e84263d55307	447	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	167:e84263d55307	448	}
AnnaBridge	167:e84263d55307	449
AnnaBridge	167:e84263d55307	450	/**
AnnaBridge	167:e84263d55307	451	* @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge	167:e84263d55307	452	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge	167:e84263d55307	453	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	454	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	455	*/
AnnaBridge	167:e84263d55307	456	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	457	{
AnnaBridge	167:e84263d55307	458	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	167:e84263d55307	459	}
AnnaBridge	167:e84263d55307	460
AnnaBridge	167:e84263d55307	461	/**
AnnaBridge	167:e84263d55307	462	* @brief Get the data register address used for DMA transfer.
AnnaBridge	167:e84263d55307	463	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge	167:e84263d55307	464	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	465	* @retval Address of data register
AnnaBridge	167:e84263d55307	466	*/
AnnaBridge	167:e84263d55307	467	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	468	{
AnnaBridge	167:e84263d55307	469	return (uint32_t) & (I2Cx->DR);
AnnaBridge	167:e84263d55307	470	}
AnnaBridge	167:e84263d55307	471
AnnaBridge	167:e84263d55307	472	/**
AnnaBridge	167:e84263d55307	473	* @brief Enable Clock stretching.
AnnaBridge	167:e84263d55307	474	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	167:e84263d55307	475	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge	167:e84263d55307	476	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	477	* @retval None
AnnaBridge	167:e84263d55307	478	*/
AnnaBridge	167:e84263d55307	479	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	480	{
AnnaBridge	167:e84263d55307	481	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	167:e84263d55307	482	}
AnnaBridge	167:e84263d55307	483
AnnaBridge	167:e84263d55307	484	/**
AnnaBridge	167:e84263d55307	485	* @brief Disable Clock stretching.
AnnaBridge	167:e84263d55307	486	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	167:e84263d55307	487	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge	167:e84263d55307	488	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	489	* @retval None
AnnaBridge	167:e84263d55307	490	*/
AnnaBridge	167:e84263d55307	491	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	492	{
AnnaBridge	167:e84263d55307	493	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	167:e84263d55307	494	}
AnnaBridge	167:e84263d55307	495
AnnaBridge	167:e84263d55307	496	/**
AnnaBridge	167:e84263d55307	497	* @brief Check if Clock stretching is enabled or disabled.
AnnaBridge	167:e84263d55307	498	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge	167:e84263d55307	499	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	500	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	501	*/
AnnaBridge	167:e84263d55307	502	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	503	{
AnnaBridge	167:e84263d55307	504	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge	167:e84263d55307	505	}
AnnaBridge	167:e84263d55307	506
AnnaBridge	167:e84263d55307	507	/**
AnnaBridge	167:e84263d55307	508	* @brief Enable General Call.
AnnaBridge	167:e84263d55307	509	* @note When enabled the Address 0x00 is ACKed.
AnnaBridge	167:e84263d55307	510	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge	167:e84263d55307	511	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	512	* @retval None
AnnaBridge	167:e84263d55307	513	*/
AnnaBridge	167:e84263d55307	514	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	515	{
AnnaBridge	167:e84263d55307	516	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	167:e84263d55307	517	}
AnnaBridge	167:e84263d55307	518
AnnaBridge	167:e84263d55307	519	/**
AnnaBridge	167:e84263d55307	520	* @brief Disable General Call.
AnnaBridge	167:e84263d55307	521	* @note When disabled the Address 0x00 is NACKed.
AnnaBridge	167:e84263d55307	522	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge	167:e84263d55307	523	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	524	* @retval None
AnnaBridge	167:e84263d55307	525	*/
AnnaBridge	167:e84263d55307	526	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	527	{
AnnaBridge	167:e84263d55307	528	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	167:e84263d55307	529	}
AnnaBridge	167:e84263d55307	530
AnnaBridge	167:e84263d55307	531	/**
AnnaBridge	167:e84263d55307	532	* @brief Check if General Call is enabled or disabled.
AnnaBridge	167:e84263d55307	533	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge	167:e84263d55307	534	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	535	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	536	*/
AnnaBridge	167:e84263d55307	537	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	538	{
AnnaBridge	167:e84263d55307	539	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge	167:e84263d55307	540	}
AnnaBridge	167:e84263d55307	541
AnnaBridge	167:e84263d55307	542	/**
AnnaBridge	167:e84263d55307	543	* @brief Set the Own Address1.
AnnaBridge	167:e84263d55307	544	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge	167:e84263d55307	545	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge	167:e84263d55307	546	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge	167:e84263d55307	547	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge	167:e84263d55307	548	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	549	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge	167:e84263d55307	550	* @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	551	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge	167:e84263d55307	552	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge	167:e84263d55307	553	* @retval None
AnnaBridge	167:e84263d55307	554	*/
AnnaBridge	167:e84263d55307	555	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge	167:e84263d55307	556	{
AnnaBridge	167:e84263d55307	557	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
AnnaBridge	167:e84263d55307	558	}
AnnaBridge	167:e84263d55307	559
AnnaBridge	167:e84263d55307	560	/**
AnnaBridge	167:e84263d55307	561	* @brief Set the 7bits Own Address2.
AnnaBridge	167:e84263d55307	562	* @note This action has no effect if own address2 is enabled.
AnnaBridge	167:e84263d55307	563	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge	167:e84263d55307	564	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	565	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge	167:e84263d55307	566	* @retval None
AnnaBridge	167:e84263d55307	567	*/
AnnaBridge	167:e84263d55307	568	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge	167:e84263d55307	569	{
AnnaBridge	167:e84263d55307	570	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge	167:e84263d55307	571	}
AnnaBridge	167:e84263d55307	572
AnnaBridge	167:e84263d55307	573	/**
AnnaBridge	167:e84263d55307	574	* @brief Enable acknowledge on Own Address2 match address.
AnnaBridge	167:e84263d55307	575	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge	167:e84263d55307	576	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	577	* @retval None
AnnaBridge	167:e84263d55307	578	*/
AnnaBridge	167:e84263d55307	579	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	580	{
AnnaBridge	167:e84263d55307	581	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	167:e84263d55307	582	}
AnnaBridge	167:e84263d55307	583
AnnaBridge	167:e84263d55307	584	/**
AnnaBridge	167:e84263d55307	585	* @brief Disable acknowledge on Own Address2 match address.
AnnaBridge	167:e84263d55307	586	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge	167:e84263d55307	587	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	588	* @retval None
AnnaBridge	167:e84263d55307	589	*/
AnnaBridge	167:e84263d55307	590	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	591	{
AnnaBridge	167:e84263d55307	592	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	167:e84263d55307	593	}
AnnaBridge	167:e84263d55307	594
AnnaBridge	167:e84263d55307	595	/**
AnnaBridge	167:e84263d55307	596	* @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge	167:e84263d55307	597	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge	167:e84263d55307	598	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	599	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	600	*/
AnnaBridge	167:e84263d55307	601	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	602	{
AnnaBridge	167:e84263d55307	603	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge	167:e84263d55307	604	}
AnnaBridge	167:e84263d55307	605
AnnaBridge	167:e84263d55307	606	/**
AnnaBridge	167:e84263d55307	607	* @brief Configure the Peripheral clock frequency.
AnnaBridge	167:e84263d55307	608	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge	167:e84263d55307	609	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	610	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	167:e84263d55307	611	* @retval None
AnnaBridge	167:e84263d55307	612	*/
AnnaBridge	167:e84263d55307	613	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge	167:e84263d55307	614	{
AnnaBridge	167:e84263d55307	615	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge	167:e84263d55307	616	}
AnnaBridge	167:e84263d55307	617
AnnaBridge	167:e84263d55307	618	/**
AnnaBridge	167:e84263d55307	619	* @brief Get the Peripheral clock frequency.
AnnaBridge	167:e84263d55307	620	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge	167:e84263d55307	621	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	622	* @retval Value of Peripheral Clock (in Hz)
AnnaBridge	167:e84263d55307	623	*/
AnnaBridge	167:e84263d55307	624	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	625	{
AnnaBridge	167:e84263d55307	626	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge	167:e84263d55307	627	}
AnnaBridge	167:e84263d55307	628
AnnaBridge	167:e84263d55307	629	/**
AnnaBridge	167:e84263d55307	630	* @brief Configure the Duty cycle (Fast mode only).
AnnaBridge	167:e84263d55307	631	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge	167:e84263d55307	632	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	633	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	634	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	167:e84263d55307	635	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	167:e84263d55307	636	* @retval None
AnnaBridge	167:e84263d55307	637	*/
AnnaBridge	167:e84263d55307	638	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge	167:e84263d55307	639	{
AnnaBridge	167:e84263d55307	640	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge	167:e84263d55307	641	}
AnnaBridge	167:e84263d55307	642
AnnaBridge	167:e84263d55307	643	/**
AnnaBridge	167:e84263d55307	644	* @brief Get the Duty cycle (Fast mode only).
AnnaBridge	167:e84263d55307	645	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge	167:e84263d55307	646	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	647	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	648	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	167:e84263d55307	649	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	167:e84263d55307	650	*/
AnnaBridge	167:e84263d55307	651	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	652	{
AnnaBridge	167:e84263d55307	653	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge	167:e84263d55307	654	}
AnnaBridge	167:e84263d55307	655
AnnaBridge	167:e84263d55307	656	/**
AnnaBridge	167:e84263d55307	657	* @brief Configure the I2C master clock speed mode.
AnnaBridge	167:e84263d55307	658	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge	167:e84263d55307	659	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	660	* @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	661	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	167:e84263d55307	662	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	167:e84263d55307	663	* @retval None
AnnaBridge	167:e84263d55307	664	*/
AnnaBridge	167:e84263d55307	665	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge	167:e84263d55307	666	{
AnnaBridge	167:e84263d55307	667	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge	167:e84263d55307	668	}
AnnaBridge	167:e84263d55307	669
AnnaBridge	167:e84263d55307	670	/**
AnnaBridge	167:e84263d55307	671	* @brief Get the the I2C master speed mode.
AnnaBridge	167:e84263d55307	672	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge	167:e84263d55307	673	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	674	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	675	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	167:e84263d55307	676	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	167:e84263d55307	677	*/
AnnaBridge	167:e84263d55307	678	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	679	{
AnnaBridge	167:e84263d55307	680	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge	167:e84263d55307	681	}
AnnaBridge	167:e84263d55307	682
AnnaBridge	167:e84263d55307	683	/**
AnnaBridge	167:e84263d55307	684	* @brief Configure the SCL, SDA rising time.
AnnaBridge	167:e84263d55307	685	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	167:e84263d55307	686	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge	167:e84263d55307	687	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	688	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge	167:e84263d55307	689	* @retval None
AnnaBridge	167:e84263d55307	690	*/
AnnaBridge	167:e84263d55307	691	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge	167:e84263d55307	692	{
AnnaBridge	167:e84263d55307	693	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge	167:e84263d55307	694	}
AnnaBridge	167:e84263d55307	695
AnnaBridge	167:e84263d55307	696	/**
AnnaBridge	167:e84263d55307	697	* @brief Get the SCL, SDA rising time.
AnnaBridge	167:e84263d55307	698	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge	167:e84263d55307	699	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	700	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	167:e84263d55307	701	*/
AnnaBridge	167:e84263d55307	702	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	703	{
AnnaBridge	167:e84263d55307	704	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge	167:e84263d55307	705	}
AnnaBridge	167:e84263d55307	706
AnnaBridge	167:e84263d55307	707	/**
AnnaBridge	167:e84263d55307	708	* @brief Configure the SCL high and low period.
AnnaBridge	167:e84263d55307	709	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	167:e84263d55307	710	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge	167:e84263d55307	711	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	712	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	167:e84263d55307	713	* @retval None
AnnaBridge	167:e84263d55307	714	*/
AnnaBridge	167:e84263d55307	715	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge	167:e84263d55307	716	{
AnnaBridge	167:e84263d55307	717	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge	167:e84263d55307	718	}
AnnaBridge	167:e84263d55307	719
AnnaBridge	167:e84263d55307	720	/**
AnnaBridge	167:e84263d55307	721	* @brief Get the SCL high and low period.
AnnaBridge	167:e84263d55307	722	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge	167:e84263d55307	723	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	724	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	167:e84263d55307	725	*/
AnnaBridge	167:e84263d55307	726	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	727	{
AnnaBridge	167:e84263d55307	728	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge	167:e84263d55307	729	}
AnnaBridge	167:e84263d55307	730
AnnaBridge	167:e84263d55307	731	/**
AnnaBridge	167:e84263d55307	732	* @brief Configure the SCL speed.
AnnaBridge	167:e84263d55307	733	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	167:e84263d55307	734	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge	167:e84263d55307	735	* TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge	167:e84263d55307	736	* CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge	167:e84263d55307	737	* CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge	167:e84263d55307	738	* CCR CCR LL_I2C_ConfigSpeed
AnnaBridge	167:e84263d55307	739	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	740	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	167:e84263d55307	741	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	167:e84263d55307	742	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	743	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	167:e84263d55307	744	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	167:e84263d55307	745	* @retval None
AnnaBridge	167:e84263d55307	746	*/
AnnaBridge	167:e84263d55307	747	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge	167:e84263d55307	748	uint32_t DutyCycle)
AnnaBridge	167:e84263d55307	749	{
AnnaBridge	167:e84263d55307	750	register uint32_t freqrange = 0x0U;
AnnaBridge	167:e84263d55307	751	register uint32_t clockconfig = 0x0U;
AnnaBridge	167:e84263d55307	752
AnnaBridge	167:e84263d55307	753	/* Compute frequency range */
AnnaBridge	167:e84263d55307	754	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge	167:e84263d55307	755
AnnaBridge	167:e84263d55307	756	/* Configure I2Cx: Frequency range register */
AnnaBridge	167:e84263d55307	757	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge	167:e84263d55307	758
AnnaBridge	167:e84263d55307	759	/* Configure I2Cx: Rise Time register */
AnnaBridge	167:e84263d55307	760	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge	167:e84263d55307	761
AnnaBridge	167:e84263d55307	762	/* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge	167:e84263d55307	763	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge	167:e84263d55307	764	{
AnnaBridge	167:e84263d55307	765	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge	167:e84263d55307	766	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
AnnaBridge	167:e84263d55307	767	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
AnnaBridge	167:e84263d55307	768	DutyCycle;
AnnaBridge	167:e84263d55307	769	}
AnnaBridge	167:e84263d55307	770	else
AnnaBridge	167:e84263d55307	771	{
AnnaBridge	167:e84263d55307	772	/* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge	167:e84263d55307	773	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
AnnaBridge	167:e84263d55307	774	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge	167:e84263d55307	775	}
AnnaBridge	167:e84263d55307	776
AnnaBridge	167:e84263d55307	777	/* Configure I2Cx: Clock control register */
AnnaBridge	167:e84263d55307	778	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
AnnaBridge	167:e84263d55307	779	}
AnnaBridge	167:e84263d55307	780
AnnaBridge	167:e84263d55307	781	/**
AnnaBridge	167:e84263d55307	782	* @brief Configure peripheral mode.
AnnaBridge	167:e84263d55307	783	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	784	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	785	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge	167:e84263d55307	786	* CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge	167:e84263d55307	787	* CR1 ENARP LL_I2C_SetMode
AnnaBridge	167:e84263d55307	788	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	789	* @param PeripheralMode This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	790	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	167:e84263d55307	791	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	167:e84263d55307	792	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	167:e84263d55307	793	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	167:e84263d55307	794	* @retval None
AnnaBridge	167:e84263d55307	795	*/
AnnaBridge	167:e84263d55307	796	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge	167:e84263d55307	797	{
AnnaBridge	167:e84263d55307	798	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
AnnaBridge	167:e84263d55307	799	}
AnnaBridge	167:e84263d55307	800
AnnaBridge	167:e84263d55307	801	/**
AnnaBridge	167:e84263d55307	802	* @brief Get peripheral mode.
AnnaBridge	167:e84263d55307	803	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	804	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	805	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge	167:e84263d55307	806	* CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge	167:e84263d55307	807	* CR1 ENARP LL_I2C_GetMode
AnnaBridge	167:e84263d55307	808	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	809	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	810	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	167:e84263d55307	811	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	167:e84263d55307	812	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	167:e84263d55307	813	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	167:e84263d55307	814	*/
AnnaBridge	167:e84263d55307	815	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	816	{
AnnaBridge	167:e84263d55307	817	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
AnnaBridge	167:e84263d55307	818	}
AnnaBridge	167:e84263d55307	819
AnnaBridge	167:e84263d55307	820	/**
AnnaBridge	167:e84263d55307	821	* @brief Enable SMBus alert (Host or Device mode)
AnnaBridge	167:e84263d55307	822	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	823	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	824	* @note SMBus Device mode:
AnnaBridge	167:e84263d55307	825	* - SMBus Alert pin is drived low and
AnnaBridge	167:e84263d55307	826	* Alert Response Address Header acknowledge is enabled.
AnnaBridge	167:e84263d55307	827	* SMBus Host mode:
AnnaBridge	167:e84263d55307	828	* - SMBus Alert pin management is supported.
AnnaBridge	167:e84263d55307	829	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge	167:e84263d55307	830	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	831	* @retval None
AnnaBridge	167:e84263d55307	832	*/
AnnaBridge	167:e84263d55307	833	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	834	{
AnnaBridge	167:e84263d55307	835	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	167:e84263d55307	836	}
AnnaBridge	167:e84263d55307	837
AnnaBridge	167:e84263d55307	838	/**
AnnaBridge	167:e84263d55307	839	* @brief Disable SMBus alert (Host or Device mode)
AnnaBridge	167:e84263d55307	840	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	841	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	842	* @note SMBus Device mode:
AnnaBridge	167:e84263d55307	843	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge	167:e84263d55307	844	* Alert Response Address Header acknowledge is disabled.
AnnaBridge	167:e84263d55307	845	* SMBus Host mode:
AnnaBridge	167:e84263d55307	846	* - SMBus Alert pin management is not supported.
AnnaBridge	167:e84263d55307	847	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge	167:e84263d55307	848	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	849	* @retval None
AnnaBridge	167:e84263d55307	850	*/
AnnaBridge	167:e84263d55307	851	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	852	{
AnnaBridge	167:e84263d55307	853	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	167:e84263d55307	854	}
AnnaBridge	167:e84263d55307	855
AnnaBridge	167:e84263d55307	856	/**
AnnaBridge	167:e84263d55307	857	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge	167:e84263d55307	858	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	859	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	860	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge	167:e84263d55307	861	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	862	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	863	*/
AnnaBridge	167:e84263d55307	864	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	865	{
AnnaBridge	167:e84263d55307	866	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge	167:e84263d55307	867	}
AnnaBridge	167:e84263d55307	868
AnnaBridge	167:e84263d55307	869	/**
AnnaBridge	167:e84263d55307	870	* @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge	167:e84263d55307	871	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	872	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	873	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge	167:e84263d55307	874	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	875	* @retval None
AnnaBridge	167:e84263d55307	876	*/
AnnaBridge	167:e84263d55307	877	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	878	{
AnnaBridge	167:e84263d55307	879	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	167:e84263d55307	880	}
AnnaBridge	167:e84263d55307	881
AnnaBridge	167:e84263d55307	882	/**
AnnaBridge	167:e84263d55307	883	* @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge	167:e84263d55307	884	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	885	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	886	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge	167:e84263d55307	887	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	888	* @retval None
AnnaBridge	167:e84263d55307	889	*/
AnnaBridge	167:e84263d55307	890	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	891	{
AnnaBridge	167:e84263d55307	892	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	167:e84263d55307	893	}
AnnaBridge	167:e84263d55307	894
AnnaBridge	167:e84263d55307	895	/**
AnnaBridge	167:e84263d55307	896	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge	167:e84263d55307	897	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	898	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	899	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge	167:e84263d55307	900	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	901	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	902	*/
AnnaBridge	167:e84263d55307	903	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	904	{
AnnaBridge	167:e84263d55307	905	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge	167:e84263d55307	906	}
AnnaBridge	167:e84263d55307	907
AnnaBridge	167:e84263d55307	908	/**
AnnaBridge	167:e84263d55307	909	* @}
AnnaBridge	167:e84263d55307	910	*/
AnnaBridge	167:e84263d55307	911
AnnaBridge	167:e84263d55307	912	/** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge	167:e84263d55307	913	* @{
AnnaBridge	167:e84263d55307	914	*/
AnnaBridge	167:e84263d55307	915
AnnaBridge	167:e84263d55307	916	/**
AnnaBridge	167:e84263d55307	917	* @brief Enable TXE interrupt.
AnnaBridge	167:e84263d55307	918	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge	167:e84263d55307	919	* CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge	167:e84263d55307	920	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	921	* @retval None
AnnaBridge	167:e84263d55307	922	*/
AnnaBridge	167:e84263d55307	923	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	924	{
AnnaBridge	167:e84263d55307	925	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	926	}
AnnaBridge	167:e84263d55307	927
AnnaBridge	167:e84263d55307	928	/**
AnnaBridge	167:e84263d55307	929	* @brief Disable TXE interrupt.
AnnaBridge	167:e84263d55307	930	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge	167:e84263d55307	931	* CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge	167:e84263d55307	932	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	933	* @retval None
AnnaBridge	167:e84263d55307	934	*/
AnnaBridge	167:e84263d55307	935	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	936	{
AnnaBridge	167:e84263d55307	937	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	938	}
AnnaBridge	167:e84263d55307	939
AnnaBridge	167:e84263d55307	940	/**
AnnaBridge	167:e84263d55307	941	* @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge	167:e84263d55307	942	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge	167:e84263d55307	943	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge	167:e84263d55307	944	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	945	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	946	*/
AnnaBridge	167:e84263d55307	947	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	948	{
AnnaBridge	167:e84263d55307	949	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	167:e84263d55307	950	}
AnnaBridge	167:e84263d55307	951
AnnaBridge	167:e84263d55307	952	/**
AnnaBridge	167:e84263d55307	953	* @brief Enable RXNE interrupt.
AnnaBridge	167:e84263d55307	954	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge	167:e84263d55307	955	* CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge	167:e84263d55307	956	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	957	* @retval None
AnnaBridge	167:e84263d55307	958	*/
AnnaBridge	167:e84263d55307	959	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	960	{
AnnaBridge	167:e84263d55307	961	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	962	}
AnnaBridge	167:e84263d55307	963
AnnaBridge	167:e84263d55307	964	/**
AnnaBridge	167:e84263d55307	965	* @brief Disable RXNE interrupt.
AnnaBridge	167:e84263d55307	966	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge	167:e84263d55307	967	* CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge	167:e84263d55307	968	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	969	* @retval None
AnnaBridge	167:e84263d55307	970	*/
AnnaBridge	167:e84263d55307	971	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	972	{
AnnaBridge	167:e84263d55307	973	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	974	}
AnnaBridge	167:e84263d55307	975
AnnaBridge	167:e84263d55307	976	/**
AnnaBridge	167:e84263d55307	977	* @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge	167:e84263d55307	978	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge	167:e84263d55307	979	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge	167:e84263d55307	980	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	981	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	982	*/
AnnaBridge	167:e84263d55307	983	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	984	{
AnnaBridge	167:e84263d55307	985	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	167:e84263d55307	986	}
AnnaBridge	167:e84263d55307	987
AnnaBridge	167:e84263d55307	988	/**
AnnaBridge	167:e84263d55307	989	* @brief Enable Events interrupts.
AnnaBridge	167:e84263d55307	990	* @note Any of these events will generate interrupt :
AnnaBridge	167:e84263d55307	991	* Start Bit (SB)
AnnaBridge	167:e84263d55307	992	* Address sent, Address matched (ADDR)
AnnaBridge	167:e84263d55307	993	* 10-bit header sent (ADD10)
AnnaBridge	167:e84263d55307	994	* Stop detection (STOPF)
AnnaBridge	167:e84263d55307	995	* Byte transfer finished (BTF)
AnnaBridge	167:e84263d55307	996	*
AnnaBridge	167:e84263d55307	997	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge	167:e84263d55307	998	* Receive buffer not empty (RXNE)
AnnaBridge	167:e84263d55307	999	* Transmit buffer empty (TXE)
AnnaBridge	167:e84263d55307	1000	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge	167:e84263d55307	1001	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1002	* @retval None
AnnaBridge	167:e84263d55307	1003	*/
AnnaBridge	167:e84263d55307	1004	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1005	{
AnnaBridge	167:e84263d55307	1006	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	167:e84263d55307	1007	}
AnnaBridge	167:e84263d55307	1008
AnnaBridge	167:e84263d55307	1009	/**
AnnaBridge	167:e84263d55307	1010	* @brief Disable Events interrupts.
AnnaBridge	167:e84263d55307	1011	* @note Any of these events will generate interrupt :
AnnaBridge	167:e84263d55307	1012	* Start Bit (SB)
AnnaBridge	167:e84263d55307	1013	* Address sent, Address matched (ADDR)
AnnaBridge	167:e84263d55307	1014	* 10-bit header sent (ADD10)
AnnaBridge	167:e84263d55307	1015	* Stop detection (STOPF)
AnnaBridge	167:e84263d55307	1016	* Byte transfer finished (BTF)
AnnaBridge	167:e84263d55307	1017	* Receive buffer not empty (RXNE)
AnnaBridge	167:e84263d55307	1018	* Transmit buffer empty (TXE)
AnnaBridge	167:e84263d55307	1019	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge	167:e84263d55307	1020	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1021	* @retval None
AnnaBridge	167:e84263d55307	1022	*/
AnnaBridge	167:e84263d55307	1023	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1024	{
AnnaBridge	167:e84263d55307	1025	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	167:e84263d55307	1026	}
AnnaBridge	167:e84263d55307	1027
AnnaBridge	167:e84263d55307	1028	/**
AnnaBridge	167:e84263d55307	1029	* @brief Check if Events interrupts are enabled or disabled.
AnnaBridge	167:e84263d55307	1030	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge	167:e84263d55307	1031	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1032	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1033	*/
AnnaBridge	167:e84263d55307	1034	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1035	{
AnnaBridge	167:e84263d55307	1036	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge	167:e84263d55307	1037	}
AnnaBridge	167:e84263d55307	1038
AnnaBridge	167:e84263d55307	1039	/**
AnnaBridge	167:e84263d55307	1040	* @brief Enable Buffer interrupts.
AnnaBridge	167:e84263d55307	1041	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge	167:e84263d55307	1042	* Receive buffer not empty (RXNE)
AnnaBridge	167:e84263d55307	1043	* Transmit buffer empty (TXE)
AnnaBridge	167:e84263d55307	1044	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge	167:e84263d55307	1045	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1046	* @retval None
AnnaBridge	167:e84263d55307	1047	*/
AnnaBridge	167:e84263d55307	1048	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1049	{
AnnaBridge	167:e84263d55307	1050	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	1051	}
AnnaBridge	167:e84263d55307	1052
AnnaBridge	167:e84263d55307	1053	/**
AnnaBridge	167:e84263d55307	1054	* @brief Disable Buffer interrupts.
AnnaBridge	167:e84263d55307	1055	* @note Any of these Buffer events will generate interrupt :
AnnaBridge	167:e84263d55307	1056	* Receive buffer not empty (RXNE)
AnnaBridge	167:e84263d55307	1057	* Transmit buffer empty (TXE)
AnnaBridge	167:e84263d55307	1058	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge	167:e84263d55307	1059	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1060	* @retval None
AnnaBridge	167:e84263d55307	1061	*/
AnnaBridge	167:e84263d55307	1062	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1063	{
AnnaBridge	167:e84263d55307	1064	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	167:e84263d55307	1065	}
AnnaBridge	167:e84263d55307	1066
AnnaBridge	167:e84263d55307	1067	/**
AnnaBridge	167:e84263d55307	1068	* @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge	167:e84263d55307	1069	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge	167:e84263d55307	1070	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1071	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1072	*/
AnnaBridge	167:e84263d55307	1073	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1074	{
AnnaBridge	167:e84263d55307	1075	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge	167:e84263d55307	1076	}
AnnaBridge	167:e84263d55307	1077
AnnaBridge	167:e84263d55307	1078	/**
AnnaBridge	167:e84263d55307	1079	* @brief Enable Error interrupts.
AnnaBridge	167:e84263d55307	1080	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1081	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1082	* @note Any of these errors will generate interrupt :
AnnaBridge	167:e84263d55307	1083	* Bus Error detection (BERR)
AnnaBridge	167:e84263d55307	1084	* Arbitration Loss (ARLO)
AnnaBridge	167:e84263d55307	1085	* Acknowledge Failure(AF)
AnnaBridge	167:e84263d55307	1086	* Overrun/Underrun (OVR)
AnnaBridge	167:e84263d55307	1087	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	167:e84263d55307	1088	* SMBus PEC error detection (PECERR)
AnnaBridge	167:e84263d55307	1089	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	167:e84263d55307	1090	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge	167:e84263d55307	1091	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1092	* @retval None
AnnaBridge	167:e84263d55307	1093	*/
AnnaBridge	167:e84263d55307	1094	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1095	{
AnnaBridge	167:e84263d55307	1096	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	167:e84263d55307	1097	}
AnnaBridge	167:e84263d55307	1098
AnnaBridge	167:e84263d55307	1099	/**
AnnaBridge	167:e84263d55307	1100	* @brief Disable Error interrupts.
AnnaBridge	167:e84263d55307	1101	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1102	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1103	* @note Any of these errors will generate interrupt :
AnnaBridge	167:e84263d55307	1104	* Bus Error detection (BERR)
AnnaBridge	167:e84263d55307	1105	* Arbitration Loss (ARLO)
AnnaBridge	167:e84263d55307	1106	* Acknowledge Failure(AF)
AnnaBridge	167:e84263d55307	1107	* Overrun/Underrun (OVR)
AnnaBridge	167:e84263d55307	1108	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	167:e84263d55307	1109	* SMBus PEC error detection (PECERR)
AnnaBridge	167:e84263d55307	1110	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	167:e84263d55307	1111	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge	167:e84263d55307	1112	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1113	* @retval None
AnnaBridge	167:e84263d55307	1114	*/
AnnaBridge	167:e84263d55307	1115	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1116	{
AnnaBridge	167:e84263d55307	1117	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	167:e84263d55307	1118	}
AnnaBridge	167:e84263d55307	1119
AnnaBridge	167:e84263d55307	1120	/**
AnnaBridge	167:e84263d55307	1121	* @brief Check if Error interrupts are enabled or disabled.
AnnaBridge	167:e84263d55307	1122	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge	167:e84263d55307	1123	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1124	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1125	*/
AnnaBridge	167:e84263d55307	1126	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1127	{
AnnaBridge	167:e84263d55307	1128	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge	167:e84263d55307	1129	}
AnnaBridge	167:e84263d55307	1130
AnnaBridge	167:e84263d55307	1131	/**
AnnaBridge	167:e84263d55307	1132	* @}
AnnaBridge	167:e84263d55307	1133	*/
AnnaBridge	167:e84263d55307	1134
AnnaBridge	167:e84263d55307	1135	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge	167:e84263d55307	1136	* @{
AnnaBridge	167:e84263d55307	1137	*/
AnnaBridge	167:e84263d55307	1138
AnnaBridge	167:e84263d55307	1139	/**
AnnaBridge	167:e84263d55307	1140	* @brief Indicate the status of Transmit data register empty flag.
AnnaBridge	167:e84263d55307	1141	* @note RESET: When next data is written in Transmit data register.
AnnaBridge	167:e84263d55307	1142	* SET: When Transmit data register is empty.
AnnaBridge	167:e84263d55307	1143	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge	167:e84263d55307	1144	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1145	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1146	*/
AnnaBridge	167:e84263d55307	1147	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1148	{
AnnaBridge	167:e84263d55307	1149	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge	167:e84263d55307	1150	}
AnnaBridge	167:e84263d55307	1151
AnnaBridge	167:e84263d55307	1152	/**
AnnaBridge	167:e84263d55307	1153	* @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge	167:e84263d55307	1154	* RESET: When Data byte transfer not done.
AnnaBridge	167:e84263d55307	1155	* SET: When Data byte transfer succeeded.
AnnaBridge	167:e84263d55307	1156	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge	167:e84263d55307	1157	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1158	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1159	*/
AnnaBridge	167:e84263d55307	1160	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1161	{
AnnaBridge	167:e84263d55307	1162	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge	167:e84263d55307	1163	}
AnnaBridge	167:e84263d55307	1164
AnnaBridge	167:e84263d55307	1165	/**
AnnaBridge	167:e84263d55307	1166	* @brief Indicate the status of Receive data register not empty flag.
AnnaBridge	167:e84263d55307	1167	* @note RESET: When Receive data register is read.
AnnaBridge	167:e84263d55307	1168	* SET: When the received data is copied in Receive data register.
AnnaBridge	167:e84263d55307	1169	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge	167:e84263d55307	1170	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1171	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1172	*/
AnnaBridge	167:e84263d55307	1173	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1174	{
AnnaBridge	167:e84263d55307	1175	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge	167:e84263d55307	1176	}
AnnaBridge	167:e84263d55307	1177
AnnaBridge	167:e84263d55307	1178	/**
AnnaBridge	167:e84263d55307	1179	* @brief Indicate the status of Start Bit (master mode).
AnnaBridge	167:e84263d55307	1180	* @note RESET: When No Start condition.
AnnaBridge	167:e84263d55307	1181	* SET: When Start condition is generated.
AnnaBridge	167:e84263d55307	1182	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge	167:e84263d55307	1183	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1184	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1185	*/
AnnaBridge	167:e84263d55307	1186	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1187	{
AnnaBridge	167:e84263d55307	1188	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge	167:e84263d55307	1189	}
AnnaBridge	167:e84263d55307	1190
AnnaBridge	167:e84263d55307	1191	/**
AnnaBridge	167:e84263d55307	1192	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge	167:e84263d55307	1193	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1194	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge	167:e84263d55307	1195	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge	167:e84263d55307	1196	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1197	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1198	*/
AnnaBridge	167:e84263d55307	1199	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1200	{
AnnaBridge	167:e84263d55307	1201	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge	167:e84263d55307	1202	}
AnnaBridge	167:e84263d55307	1203
AnnaBridge	167:e84263d55307	1204	/**
AnnaBridge	167:e84263d55307	1205	* @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge	167:e84263d55307	1206	* @note RESET: When no ADD10 event occured.
AnnaBridge	167:e84263d55307	1207	* SET: When the master has sent the first address byte (header).
AnnaBridge	167:e84263d55307	1208	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge	167:e84263d55307	1209	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1210	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1211	*/
AnnaBridge	167:e84263d55307	1212	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1213	{
AnnaBridge	167:e84263d55307	1214	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge	167:e84263d55307	1215	}
AnnaBridge	167:e84263d55307	1216
AnnaBridge	167:e84263d55307	1217	/**
AnnaBridge	167:e84263d55307	1218	* @brief Indicate the status of Acknowledge failure flag.
AnnaBridge	167:e84263d55307	1219	* @note RESET: No acknowledge failure.
AnnaBridge	167:e84263d55307	1220	* SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge	167:e84263d55307	1221	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge	167:e84263d55307	1222	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1223	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1224	*/
AnnaBridge	167:e84263d55307	1225	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1226	{
AnnaBridge	167:e84263d55307	1227	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge	167:e84263d55307	1228	}
AnnaBridge	167:e84263d55307	1229
AnnaBridge	167:e84263d55307	1230	/**
AnnaBridge	167:e84263d55307	1231	* @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge	167:e84263d55307	1232	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1233	* SET: When a Stop condition is detected.
AnnaBridge	167:e84263d55307	1234	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge	167:e84263d55307	1235	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1236	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1237	*/
AnnaBridge	167:e84263d55307	1238	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1239	{
AnnaBridge	167:e84263d55307	1240	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge	167:e84263d55307	1241	}
AnnaBridge	167:e84263d55307	1242
AnnaBridge	167:e84263d55307	1243	/**
AnnaBridge	167:e84263d55307	1244	* @brief Indicate the status of Bus error flag.
AnnaBridge	167:e84263d55307	1245	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1246	* SET: When a misplaced Start or Stop condition is detected.
AnnaBridge	167:e84263d55307	1247	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge	167:e84263d55307	1248	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1249	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1250	*/
AnnaBridge	167:e84263d55307	1251	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1252	{
AnnaBridge	167:e84263d55307	1253	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge	167:e84263d55307	1254	}
AnnaBridge	167:e84263d55307	1255
AnnaBridge	167:e84263d55307	1256	/**
AnnaBridge	167:e84263d55307	1257	* @brief Indicate the status of Arbitration lost flag.
AnnaBridge	167:e84263d55307	1258	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1259	* SET: When arbitration lost.
AnnaBridge	167:e84263d55307	1260	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge	167:e84263d55307	1261	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1262	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1263	*/
AnnaBridge	167:e84263d55307	1264	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1265	{
AnnaBridge	167:e84263d55307	1266	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge	167:e84263d55307	1267	}
AnnaBridge	167:e84263d55307	1268
AnnaBridge	167:e84263d55307	1269	/**
AnnaBridge	167:e84263d55307	1270	* @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge	167:e84263d55307	1271	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1272	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge	167:e84263d55307	1273	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge	167:e84263d55307	1274	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1275	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1276	*/
AnnaBridge	167:e84263d55307	1277	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1278	{
AnnaBridge	167:e84263d55307	1279	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge	167:e84263d55307	1280	}
AnnaBridge	167:e84263d55307	1281
AnnaBridge	167:e84263d55307	1282	/**
AnnaBridge	167:e84263d55307	1283	* @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge	167:e84263d55307	1284	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1285	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1286	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge	167:e84263d55307	1287	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1288	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1289	*/
AnnaBridge	167:e84263d55307	1290	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1291	{
AnnaBridge	167:e84263d55307	1292	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge	167:e84263d55307	1293	}
AnnaBridge	167:e84263d55307	1294
AnnaBridge	167:e84263d55307	1295	/**
AnnaBridge	167:e84263d55307	1296	* @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge	167:e84263d55307	1297	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1298	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1299	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge	167:e84263d55307	1300	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1301	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1302	*/
AnnaBridge	167:e84263d55307	1303	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1304	{
AnnaBridge	167:e84263d55307	1305	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge	167:e84263d55307	1306	}
AnnaBridge	167:e84263d55307	1307
AnnaBridge	167:e84263d55307	1308	/**
AnnaBridge	167:e84263d55307	1309	* @brief Indicate the status of SMBus alert flag.
AnnaBridge	167:e84263d55307	1310	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1311	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1312	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge	167:e84263d55307	1313	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1314	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1315	*/
AnnaBridge	167:e84263d55307	1316	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1317	{
AnnaBridge	167:e84263d55307	1318	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge	167:e84263d55307	1319	}
AnnaBridge	167:e84263d55307	1320
AnnaBridge	167:e84263d55307	1321	/**
AnnaBridge	167:e84263d55307	1322	* @brief Indicate the status of Bus Busy flag.
AnnaBridge	167:e84263d55307	1323	* @note RESET: Clear default value.
AnnaBridge	167:e84263d55307	1324	* SET: When a Start condition is detected.
AnnaBridge	167:e84263d55307	1325	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge	167:e84263d55307	1326	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1327	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1328	*/
AnnaBridge	167:e84263d55307	1329	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1330	{
AnnaBridge	167:e84263d55307	1331	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge	167:e84263d55307	1332	}
AnnaBridge	167:e84263d55307	1333
AnnaBridge	167:e84263d55307	1334	/**
AnnaBridge	167:e84263d55307	1335	* @brief Indicate the status of Dual flag.
AnnaBridge	167:e84263d55307	1336	* @note RESET: Received address matched with OAR1.
AnnaBridge	167:e84263d55307	1337	* SET: Received address matched with OAR2.
AnnaBridge	167:e84263d55307	1338	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge	167:e84263d55307	1339	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1340	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1341	*/
AnnaBridge	167:e84263d55307	1342	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1343	{
AnnaBridge	167:e84263d55307	1344	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge	167:e84263d55307	1345	}
AnnaBridge	167:e84263d55307	1346
AnnaBridge	167:e84263d55307	1347	/**
AnnaBridge	167:e84263d55307	1348	* @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge	167:e84263d55307	1349	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1350	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1351	* @note RESET: No SMBus Host address
AnnaBridge	167:e84263d55307	1352	* SET: SMBus Host address received.
AnnaBridge	167:e84263d55307	1353	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	167:e84263d55307	1354	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge	167:e84263d55307	1355	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1356	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1357	*/
AnnaBridge	167:e84263d55307	1358	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1359	{
AnnaBridge	167:e84263d55307	1360	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge	167:e84263d55307	1361	}
AnnaBridge	167:e84263d55307	1362
AnnaBridge	167:e84263d55307	1363	/**
AnnaBridge	167:e84263d55307	1364	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge	167:e84263d55307	1365	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1366	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1367	* @note RESET: No SMBus Device default address
AnnaBridge	167:e84263d55307	1368	* SET: SMBus Device default address received.
AnnaBridge	167:e84263d55307	1369	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	167:e84263d55307	1370	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge	167:e84263d55307	1371	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1372	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1373	*/
AnnaBridge	167:e84263d55307	1374	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1375	{
AnnaBridge	167:e84263d55307	1376	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge	167:e84263d55307	1377	}
AnnaBridge	167:e84263d55307	1378
AnnaBridge	167:e84263d55307	1379	/**
AnnaBridge	167:e84263d55307	1380	* @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge	167:e84263d55307	1381	* @note RESET: No Generall call address
AnnaBridge	167:e84263d55307	1382	* SET: General call address received.
AnnaBridge	167:e84263d55307	1383	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	167:e84263d55307	1384	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge	167:e84263d55307	1385	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1386	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1387	*/
AnnaBridge	167:e84263d55307	1388	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1389	{
AnnaBridge	167:e84263d55307	1390	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge	167:e84263d55307	1391	}
AnnaBridge	167:e84263d55307	1392
AnnaBridge	167:e84263d55307	1393	/**
AnnaBridge	167:e84263d55307	1394	* @brief Indicate the status of Master/Slave flag.
AnnaBridge	167:e84263d55307	1395	* @note RESET: Slave Mode.
AnnaBridge	167:e84263d55307	1396	* SET: Master Mode.
AnnaBridge	167:e84263d55307	1397	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge	167:e84263d55307	1398	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1399	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1400	*/
AnnaBridge	167:e84263d55307	1401	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1402	{
AnnaBridge	167:e84263d55307	1403	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge	167:e84263d55307	1404	}
AnnaBridge	167:e84263d55307	1405
AnnaBridge	167:e84263d55307	1406	/**
AnnaBridge	167:e84263d55307	1407	* @brief Clear Address Matched flag.
AnnaBridge	167:e84263d55307	1408	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	167:e84263d55307	1409	* register followed by a read access to the I2Cx_SR2 register.
AnnaBridge	167:e84263d55307	1410	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge	167:e84263d55307	1411	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1412	* @retval None
AnnaBridge	167:e84263d55307	1413	*/
AnnaBridge	167:e84263d55307	1414	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1415	{
AnnaBridge	167:e84263d55307	1416	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	1417	tmpreg = I2Cx->SR1;
AnnaBridge	167:e84263d55307	1418	(void) tmpreg;
AnnaBridge	167:e84263d55307	1419	tmpreg = I2Cx->SR2;
AnnaBridge	167:e84263d55307	1420	(void) tmpreg;
AnnaBridge	167:e84263d55307	1421	}
AnnaBridge	167:e84263d55307	1422
AnnaBridge	167:e84263d55307	1423	/**
AnnaBridge	167:e84263d55307	1424	* @brief Clear Acknowledge failure flag.
AnnaBridge	167:e84263d55307	1425	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge	167:e84263d55307	1426	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1427	* @retval None
AnnaBridge	167:e84263d55307	1428	*/
AnnaBridge	167:e84263d55307	1429	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1430	{
AnnaBridge	167:e84263d55307	1431	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge	167:e84263d55307	1432	}
AnnaBridge	167:e84263d55307	1433
AnnaBridge	167:e84263d55307	1434	/**
AnnaBridge	167:e84263d55307	1435	* @brief Clear Stop detection flag.
AnnaBridge	167:e84263d55307	1436	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	167:e84263d55307	1437	* register followed by a write access to I2Cx_CR1 register.
AnnaBridge	167:e84263d55307	1438	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge	167:e84263d55307	1439	* CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge	167:e84263d55307	1440	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1441	* @retval None
AnnaBridge	167:e84263d55307	1442	*/
AnnaBridge	167:e84263d55307	1443	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1444	{
AnnaBridge	167:e84263d55307	1445	__IO uint32_t tmpreg;
AnnaBridge	167:e84263d55307	1446	tmpreg = I2Cx->SR1;
AnnaBridge	167:e84263d55307	1447	(void) tmpreg;
AnnaBridge	167:e84263d55307	1448	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	167:e84263d55307	1449	}
AnnaBridge	167:e84263d55307	1450
AnnaBridge	167:e84263d55307	1451	/**
AnnaBridge	167:e84263d55307	1452	* @brief Clear Bus error flag.
AnnaBridge	167:e84263d55307	1453	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge	167:e84263d55307	1454	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1455	* @retval None
AnnaBridge	167:e84263d55307	1456	*/
AnnaBridge	167:e84263d55307	1457	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1458	{
AnnaBridge	167:e84263d55307	1459	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge	167:e84263d55307	1460	}
AnnaBridge	167:e84263d55307	1461
AnnaBridge	167:e84263d55307	1462	/**
AnnaBridge	167:e84263d55307	1463	* @brief Clear Arbitration lost flag.
AnnaBridge	167:e84263d55307	1464	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge	167:e84263d55307	1465	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1466	* @retval None
AnnaBridge	167:e84263d55307	1467	*/
AnnaBridge	167:e84263d55307	1468	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1469	{
AnnaBridge	167:e84263d55307	1470	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge	167:e84263d55307	1471	}
AnnaBridge	167:e84263d55307	1472
AnnaBridge	167:e84263d55307	1473	/**
AnnaBridge	167:e84263d55307	1474	* @brief Clear Overrun/Underrun flag.
AnnaBridge	167:e84263d55307	1475	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge	167:e84263d55307	1476	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1477	* @retval None
AnnaBridge	167:e84263d55307	1478	*/
AnnaBridge	167:e84263d55307	1479	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1480	{
AnnaBridge	167:e84263d55307	1481	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge	167:e84263d55307	1482	}
AnnaBridge	167:e84263d55307	1483
AnnaBridge	167:e84263d55307	1484	/**
AnnaBridge	167:e84263d55307	1485	* @brief Clear SMBus PEC error flag.
AnnaBridge	167:e84263d55307	1486	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge	167:e84263d55307	1487	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1488	* @retval None
AnnaBridge	167:e84263d55307	1489	*/
AnnaBridge	167:e84263d55307	1490	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1491	{
AnnaBridge	167:e84263d55307	1492	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge	167:e84263d55307	1493	}
AnnaBridge	167:e84263d55307	1494
AnnaBridge	167:e84263d55307	1495	/**
AnnaBridge	167:e84263d55307	1496	* @brief Clear SMBus Timeout detection flag.
AnnaBridge	167:e84263d55307	1497	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1498	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1499	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge	167:e84263d55307	1500	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1501	* @retval None
AnnaBridge	167:e84263d55307	1502	*/
AnnaBridge	167:e84263d55307	1503	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1504	{
AnnaBridge	167:e84263d55307	1505	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge	167:e84263d55307	1506	}
AnnaBridge	167:e84263d55307	1507
AnnaBridge	167:e84263d55307	1508	/**
AnnaBridge	167:e84263d55307	1509	* @brief Clear SMBus Alert flag.
AnnaBridge	167:e84263d55307	1510	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1511	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1512	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge	167:e84263d55307	1513	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1514	* @retval None
AnnaBridge	167:e84263d55307	1515	*/
AnnaBridge	167:e84263d55307	1516	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1517	{
AnnaBridge	167:e84263d55307	1518	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge	167:e84263d55307	1519	}
AnnaBridge	167:e84263d55307	1520
AnnaBridge	167:e84263d55307	1521	/**
AnnaBridge	167:e84263d55307	1522	* @}
AnnaBridge	167:e84263d55307	1523	*/
AnnaBridge	167:e84263d55307	1524
AnnaBridge	167:e84263d55307	1525	/** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge	167:e84263d55307	1526	* @{
AnnaBridge	167:e84263d55307	1527	*/
AnnaBridge	167:e84263d55307	1528
AnnaBridge	167:e84263d55307	1529	/**
AnnaBridge	167:e84263d55307	1530	* @brief Enable Reset of I2C peripheral.
AnnaBridge	167:e84263d55307	1531	* @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge	167:e84263d55307	1532	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1533	* @retval None
AnnaBridge	167:e84263d55307	1534	*/
AnnaBridge	167:e84263d55307	1535	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1536	{
AnnaBridge	167:e84263d55307	1537	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	167:e84263d55307	1538	}
AnnaBridge	167:e84263d55307	1539
AnnaBridge	167:e84263d55307	1540	/**
AnnaBridge	167:e84263d55307	1541	* @brief Disable Reset of I2C peripheral.
AnnaBridge	167:e84263d55307	1542	* @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge	167:e84263d55307	1543	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1544	* @retval None
AnnaBridge	167:e84263d55307	1545	*/
AnnaBridge	167:e84263d55307	1546	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1547	{
AnnaBridge	167:e84263d55307	1548	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	167:e84263d55307	1549	}
AnnaBridge	167:e84263d55307	1550
AnnaBridge	167:e84263d55307	1551	/**
AnnaBridge	167:e84263d55307	1552	* @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge	167:e84263d55307	1553	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge	167:e84263d55307	1554	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1555	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1556	*/
AnnaBridge	167:e84263d55307	1557	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1558	{
AnnaBridge	167:e84263d55307	1559	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge	167:e84263d55307	1560	}
AnnaBridge	167:e84263d55307	1561
AnnaBridge	167:e84263d55307	1562	/**
AnnaBridge	167:e84263d55307	1563	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	167:e84263d55307	1564	* @note Usage in Slave or Master mode.
AnnaBridge	167:e84263d55307	1565	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge	167:e84263d55307	1566	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1567	* @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge	167:e84263d55307	1568	* @arg @ref LL_I2C_ACK
AnnaBridge	167:e84263d55307	1569	* @arg @ref LL_I2C_NACK
AnnaBridge	167:e84263d55307	1570	* @retval None
AnnaBridge	167:e84263d55307	1571	*/
AnnaBridge	167:e84263d55307	1572	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge	167:e84263d55307	1573	{
AnnaBridge	167:e84263d55307	1574	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge	167:e84263d55307	1575	}
AnnaBridge	167:e84263d55307	1576
AnnaBridge	167:e84263d55307	1577	/**
AnnaBridge	167:e84263d55307	1578	* @brief Generate a START or RESTART condition
AnnaBridge	167:e84263d55307	1579	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge	167:e84263d55307	1580	* This action has no effect when RELOAD is set.
AnnaBridge	167:e84263d55307	1581	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge	167:e84263d55307	1582	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1583	* @retval None
AnnaBridge	167:e84263d55307	1584	*/
AnnaBridge	167:e84263d55307	1585	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1586	{
AnnaBridge	167:e84263d55307	1587	SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge	167:e84263d55307	1588	}
AnnaBridge	167:e84263d55307	1589
AnnaBridge	167:e84263d55307	1590	/**
AnnaBridge	167:e84263d55307	1591	* @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge	167:e84263d55307	1592	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge	167:e84263d55307	1593	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1594	* @retval None
AnnaBridge	167:e84263d55307	1595	*/
AnnaBridge	167:e84263d55307	1596	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1597	{
AnnaBridge	167:e84263d55307	1598	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge	167:e84263d55307	1599	}
AnnaBridge	167:e84263d55307	1600
AnnaBridge	167:e84263d55307	1601	/**
AnnaBridge	167:e84263d55307	1602	* @brief Enable bit POS (master/host mode).
AnnaBridge	167:e84263d55307	1603	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge	167:e84263d55307	1604	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge	167:e84263d55307	1605	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1606	* @retval None
AnnaBridge	167:e84263d55307	1607	*/
AnnaBridge	167:e84263d55307	1608	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1609	{
AnnaBridge	167:e84263d55307	1610	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	167:e84263d55307	1611	}
AnnaBridge	167:e84263d55307	1612
AnnaBridge	167:e84263d55307	1613	/**
AnnaBridge	167:e84263d55307	1614	* @brief Disable bit POS (master/host mode).
AnnaBridge	167:e84263d55307	1615	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge	167:e84263d55307	1616	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge	167:e84263d55307	1617	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1618	* @retval None
AnnaBridge	167:e84263d55307	1619	*/
AnnaBridge	167:e84263d55307	1620	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1621	{
AnnaBridge	167:e84263d55307	1622	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	167:e84263d55307	1623	}
AnnaBridge	167:e84263d55307	1624
AnnaBridge	167:e84263d55307	1625	/**
AnnaBridge	167:e84263d55307	1626	* @brief Check if bit POS is enabled or disabled.
AnnaBridge	167:e84263d55307	1627	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge	167:e84263d55307	1628	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1629	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1630	*/
AnnaBridge	167:e84263d55307	1631	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1632	{
AnnaBridge	167:e84263d55307	1633	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge	167:e84263d55307	1634	}
AnnaBridge	167:e84263d55307	1635
AnnaBridge	167:e84263d55307	1636	/**
AnnaBridge	167:e84263d55307	1637	* @brief Indicate the value of transfer direction.
AnnaBridge	167:e84263d55307	1638	* @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge	167:e84263d55307	1639	* SET: Bus is in write transfer (peripheral point of view).
AnnaBridge	167:e84263d55307	1640	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge	167:e84263d55307	1641	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1642	* @retval Returned value can be one of the following values:
AnnaBridge	167:e84263d55307	1643	* @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge	167:e84263d55307	1644	* @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge	167:e84263d55307	1645	*/
AnnaBridge	167:e84263d55307	1646	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1647	{
AnnaBridge	167:e84263d55307	1648	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge	167:e84263d55307	1649	}
AnnaBridge	167:e84263d55307	1650
AnnaBridge	167:e84263d55307	1651	/**
AnnaBridge	167:e84263d55307	1652	* @brief Enable DMA last transfer.
AnnaBridge	167:e84263d55307	1653	* @note This action mean that next DMA EOT is the last transfer.
AnnaBridge	167:e84263d55307	1654	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge	167:e84263d55307	1655	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1656	* @retval None
AnnaBridge	167:e84263d55307	1657	*/
AnnaBridge	167:e84263d55307	1658	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1659	{
AnnaBridge	167:e84263d55307	1660	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	167:e84263d55307	1661	}
AnnaBridge	167:e84263d55307	1662
AnnaBridge	167:e84263d55307	1663	/**
AnnaBridge	167:e84263d55307	1664	* @brief Disable DMA last transfer.
AnnaBridge	167:e84263d55307	1665	* @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge	167:e84263d55307	1666	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge	167:e84263d55307	1667	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1668	* @retval None
AnnaBridge	167:e84263d55307	1669	*/
AnnaBridge	167:e84263d55307	1670	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1671	{
AnnaBridge	167:e84263d55307	1672	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	167:e84263d55307	1673	}
AnnaBridge	167:e84263d55307	1674
AnnaBridge	167:e84263d55307	1675	/**
AnnaBridge	167:e84263d55307	1676	* @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge	167:e84263d55307	1677	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge	167:e84263d55307	1678	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1679	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1680	*/
AnnaBridge	167:e84263d55307	1681	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1682	{
AnnaBridge	167:e84263d55307	1683	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge	167:e84263d55307	1684	}
AnnaBridge	167:e84263d55307	1685
AnnaBridge	167:e84263d55307	1686	/**
AnnaBridge	167:e84263d55307	1687	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	167:e84263d55307	1688	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1689	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1690	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge	167:e84263d55307	1691	* or by a START or STOP condition, it is also cleared by software.
AnnaBridge	167:e84263d55307	1692	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge	167:e84263d55307	1693	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1694	* @retval None
AnnaBridge	167:e84263d55307	1695	*/
AnnaBridge	167:e84263d55307	1696	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1697	{
AnnaBridge	167:e84263d55307	1698	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	167:e84263d55307	1699	}
AnnaBridge	167:e84263d55307	1700
AnnaBridge	167:e84263d55307	1701	/**
AnnaBridge	167:e84263d55307	1702	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	167:e84263d55307	1703	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1704	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1705	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge	167:e84263d55307	1706	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1707	* @retval None
AnnaBridge	167:e84263d55307	1708	*/
AnnaBridge	167:e84263d55307	1709	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1710	{
AnnaBridge	167:e84263d55307	1711	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	167:e84263d55307	1712	}
AnnaBridge	167:e84263d55307	1713
AnnaBridge	167:e84263d55307	1714	/**
AnnaBridge	167:e84263d55307	1715	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge	167:e84263d55307	1716	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1717	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1718	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge	167:e84263d55307	1719	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1720	* @retval State of bit (1 or 0).
AnnaBridge	167:e84263d55307	1721	*/
AnnaBridge	167:e84263d55307	1722	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1723	{
AnnaBridge	167:e84263d55307	1724	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge	167:e84263d55307	1725	}
AnnaBridge	167:e84263d55307	1726
AnnaBridge	167:e84263d55307	1727	/**
AnnaBridge	167:e84263d55307	1728	* @brief Get the SMBus Packet Error byte calculated.
AnnaBridge	167:e84263d55307	1729	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	167:e84263d55307	1730	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	167:e84263d55307	1731	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge	167:e84263d55307	1732	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1733	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1734	*/
AnnaBridge	167:e84263d55307	1735	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1736	{
AnnaBridge	167:e84263d55307	1737	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge	167:e84263d55307	1738	}
AnnaBridge	167:e84263d55307	1739
AnnaBridge	167:e84263d55307	1740	/**
AnnaBridge	167:e84263d55307	1741	* @brief Read Receive Data register.
AnnaBridge	167:e84263d55307	1742	* @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge	167:e84263d55307	1743	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1744	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1745	*/
AnnaBridge	167:e84263d55307	1746	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge	167:e84263d55307	1747	{
AnnaBridge	167:e84263d55307	1748	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge	167:e84263d55307	1749	}
AnnaBridge	167:e84263d55307	1750
AnnaBridge	167:e84263d55307	1751	/**
AnnaBridge	167:e84263d55307	1752	* @brief Write in Transmit Data Register .
AnnaBridge	167:e84263d55307	1753	* @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge	167:e84263d55307	1754	* @param I2Cx I2C Instance.
AnnaBridge	167:e84263d55307	1755	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	167:e84263d55307	1756	* @retval None
AnnaBridge	167:e84263d55307	1757	*/
AnnaBridge	167:e84263d55307	1758	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge	167:e84263d55307	1759	{
AnnaBridge	167:e84263d55307	1760	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge	167:e84263d55307	1761	}
AnnaBridge	167:e84263d55307	1762
AnnaBridge	167:e84263d55307	1763	/**
AnnaBridge	167:e84263d55307	1764	* @}
AnnaBridge	167:e84263d55307	1765	*/
AnnaBridge	167:e84263d55307	1766
AnnaBridge	167:e84263d55307	1767	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	167:e84263d55307	1768	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	167:e84263d55307	1769	* @{
AnnaBridge	167:e84263d55307	1770	*/
AnnaBridge	167:e84263d55307	1771
AnnaBridge	167:e84263d55307	1772	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
AnnaBridge	167:e84263d55307	1773	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge	167:e84263d55307	1774	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge	167:e84263d55307	1775
AnnaBridge	167:e84263d55307	1776
AnnaBridge	167:e84263d55307	1777	/**
AnnaBridge	167:e84263d55307	1778	* @}
AnnaBridge	167:e84263d55307	1779	*/
AnnaBridge	167:e84263d55307	1780	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	167:e84263d55307	1781
AnnaBridge	167:e84263d55307	1782	/**
AnnaBridge	167:e84263d55307	1783	* @}
AnnaBridge	167:e84263d55307	1784	*/
AnnaBridge	167:e84263d55307	1785
AnnaBridge	167:e84263d55307	1786	/**
AnnaBridge	167:e84263d55307	1787	* @}
AnnaBridge	167:e84263d55307	1788	*/
AnnaBridge	167:e84263d55307	1789
AnnaBridge	167:e84263d55307	1790	#endif /* I2C1 \|\| I2C2 \|\| I2C3 */
AnnaBridge	167:e84263d55307	1791
AnnaBridge	167:e84263d55307	1792	/**
AnnaBridge	167:e84263d55307	1793	* @}
AnnaBridge	167:e84263d55307	1794	*/
AnnaBridge	167:e84263d55307	1795
AnnaBridge	167:e84263d55307	1796	#ifdef __cplusplus
AnnaBridge	167:e84263d55307	1797	}
AnnaBridge	167:e84263d55307	1798	#endif
AnnaBridge	167:e84263d55307	1799
AnnaBridge	167:e84263d55307	1800	#endif /* __STM32F2xx_LL_I2C_H */
AnnaBridge	167:e84263d55307	1801
AnnaBridge	167:e84263d55307	1802	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/