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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 154:37f96f9d4de2
Child:: 187:0387e8f68319

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_tim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @version V1.1.0
AnnaBridge	165:e614a9f1c9e2	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief Header file of TIM HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32F1xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	40	#define __STM32F1xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32f1xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup TIM
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup TIM_Exported_Types TIM Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61	/**
<>	144:ef7eb2e8f9f7	62	* @brief TIM Time base Configuration Structure definition
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64	typedef struct
<>	144:ef7eb2e8f9f7	65	{
<>	144:ef7eb2e8f9f7	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	144:ef7eb2e8f9f7	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	144:ef7eb2e8f9f7	70	This parameter can be a value of @ref TIM_Counter_Mode */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
<>	144:ef7eb2e8f9f7	73	Auto-Reload Register at the next update event.
<>	144:ef7eb2e8f9f7	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	144:ef7eb2e8f9f7	77	This parameter can be a value of @ref TIM_ClockDivision */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
<>	144:ef7eb2e8f9f7	80	reaches zero, an update event is generated and counting restarts
<>	144:ef7eb2e8f9f7	81	from the RCR value (N).
<>	144:ef7eb2e8f9f7	82	This means in PWM mode that (N+1) corresponds to:
<>	144:ef7eb2e8f9f7	83	- the number of PWM periods in edge-aligned mode
<>	144:ef7eb2e8f9f7	84	- the number of half PWM period in center-aligned mode
<>	144:ef7eb2e8f9f7	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
<>	144:ef7eb2e8f9f7	86	@note This parameter is valid only for TIM1 and TIM8. */
AnnaBridge	165:e614a9f1c9e2	87
AnnaBridge	165:e614a9f1c9e2	88	uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
AnnaBridge	165:e614a9f1c9e2	89	This parameter can be a value of @ref TIM_AutoReloadPreload */
<>	144:ef7eb2e8f9f7	90	} TIM_Base_InitTypeDef;
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	/**
<>	144:ef7eb2e8f9f7	93	* @brief TIM Output Compare Configuration Structure definition
<>	144:ef7eb2e8f9f7	94	*/
<>	144:ef7eb2e8f9f7	95	typedef struct
<>	144:ef7eb2e8f9f7	96	{
<>	144:ef7eb2e8f9f7	97	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	98	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	101	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	104	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	105
<>	144:ef7eb2e8f9f7	106	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	144:ef7eb2e8f9f7	107	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	144:ef7eb2e8f9f7	108	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	109
<>	144:ef7eb2e8f9f7	110	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<>	144:ef7eb2e8f9f7	111	This parameter can be a value of @ref TIM_Output_Fast_State
<>	144:ef7eb2e8f9f7	112	@note This parameter is valid only in PWM1 and PWM2 mode. */
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	116	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	144:ef7eb2e8f9f7	117	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	120	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	144:ef7eb2e8f9f7	121	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	122	} TIM_OC_InitTypeDef;
<>	144:ef7eb2e8f9f7	123
<>	144:ef7eb2e8f9f7	124	/**
<>	144:ef7eb2e8f9f7	125	* @brief TIM One Pulse Mode Configuration Structure definition
<>	144:ef7eb2e8f9f7	126	*/
<>	144:ef7eb2e8f9f7	127	typedef struct
<>	144:ef7eb2e8f9f7	128	{
<>	144:ef7eb2e8f9f7	129	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	130	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	133	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	136	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
<>	144:ef7eb2e8f9f7	139	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
<>	144:ef7eb2e8f9f7	140	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	143	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
<>	144:ef7eb2e8f9f7	144	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	145
<>	144:ef7eb2e8f9f7	146	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
<>	144:ef7eb2e8f9f7	147	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
<>	144:ef7eb2e8f9f7	148	@note This parameter is valid only for TIM1 and TIM8. */
<>	144:ef7eb2e8f9f7	149
<>	144:ef7eb2e8f9f7	150	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	151	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	152
<>	144:ef7eb2e8f9f7	153	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	154	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	157	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	158	} TIM_OnePulse_InitTypeDef;
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160
<>	144:ef7eb2e8f9f7	161	/**
<>	144:ef7eb2e8f9f7	162	* @brief TIM Input Capture Configuration Structure definition
<>	144:ef7eb2e8f9f7	163	*/
<>	144:ef7eb2e8f9f7	164	typedef struct
<>	144:ef7eb2e8f9f7	165	{
<>	144:ef7eb2e8f9f7	166	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	167	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	170	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	171
<>	144:ef7eb2e8f9f7	172	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	173	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	174
<>	144:ef7eb2e8f9f7	175	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	176	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	177	} TIM_IC_InitTypeDef;
<>	144:ef7eb2e8f9f7	178
<>	144:ef7eb2e8f9f7	179	/**
<>	144:ef7eb2e8f9f7	180	* @brief TIM Encoder Configuration Structure definition
<>	144:ef7eb2e8f9f7	181	*/
<>	144:ef7eb2e8f9f7	182	typedef struct
<>	144:ef7eb2e8f9f7	183	{
<>	144:ef7eb2e8f9f7	184	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	185	This parameter can be a value of @ref TIM_Encoder_Mode */
<>	144:ef7eb2e8f9f7	186
<>	144:ef7eb2e8f9f7	187	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	188	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	uint32_t IC1Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	191	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	194	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	195
<>	144:ef7eb2e8f9f7	196	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	197	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	200	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	201
<>	144:ef7eb2e8f9f7	202	uint32_t IC2Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	203	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	206	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	uint32_t IC2Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	209	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	210	} TIM_Encoder_InitTypeDef;
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @brief TIM Clock Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216	typedef struct
<>	144:ef7eb2e8f9f7	217	{
<>	144:ef7eb2e8f9f7	218	uint32_t ClockSource; /*!< TIM clock sources
<>	144:ef7eb2e8f9f7	219	This parameter can be a value of @ref TIM_Clock_Source */
<>	144:ef7eb2e8f9f7	220	uint32_t ClockPolarity; /*!< TIM clock polarity
<>	144:ef7eb2e8f9f7	221	This parameter can be a value of @ref TIM_Clock_Polarity */
<>	144:ef7eb2e8f9f7	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler
<>	144:ef7eb2e8f9f7	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
<>	144:ef7eb2e8f9f7	224	uint32_t ClockFilter; /*!< TIM clock filter
<>	144:ef7eb2e8f9f7	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	226	}TIM_ClockConfigTypeDef;
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228	/**
<>	144:ef7eb2e8f9f7	229	* @brief TIM Clear Input Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	230	*/
<>	144:ef7eb2e8f9f7	231	typedef struct
<>	144:ef7eb2e8f9f7	232	{
<>	144:ef7eb2e8f9f7	233	uint32_t ClearInputState; /*!< TIM clear Input state
<>	144:ef7eb2e8f9f7	234	This parameter can be ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	235	uint32_t ClearInputSource; /*!< TIM clear Input sources
<>	144:ef7eb2e8f9f7	236	This parameter can be a value of @ref TIM_ClearInput_Source */
<>	144:ef7eb2e8f9f7	237	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
<>	144:ef7eb2e8f9f7	238	This parameter can be a value of @ref TIM_ClearInput_Polarity */
<>	144:ef7eb2e8f9f7	239	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
<>	144:ef7eb2e8f9f7	240	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<>	144:ef7eb2e8f9f7	241	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
<>	144:ef7eb2e8f9f7	242	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	243	}TIM_ClearInputConfigTypeDef;
<>	144:ef7eb2e8f9f7	244
<>	144:ef7eb2e8f9f7	245	/**
<>	144:ef7eb2e8f9f7	246	* @brief TIM Slave configuration Structure definition
<>	144:ef7eb2e8f9f7	247	*/
<>	144:ef7eb2e8f9f7	248	typedef struct {
<>	144:ef7eb2e8f9f7	249	uint32_t SlaveMode; /*!< Slave mode selection
<>	144:ef7eb2e8f9f7	250	This parameter can be a value of @ref TIM_Slave_Mode */
<>	144:ef7eb2e8f9f7	251	uint32_t InputTrigger; /*!< Input Trigger source
<>	144:ef7eb2e8f9f7	252	This parameter can be a value of @ref TIM_Trigger_Selection */
<>	144:ef7eb2e8f9f7	253	uint32_t TriggerPolarity; /*!< Input Trigger polarity
<>	144:ef7eb2e8f9f7	254	This parameter can be a value of @ref TIM_Trigger_Polarity */
<>	144:ef7eb2e8f9f7	255	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
<>	144:ef7eb2e8f9f7	256	This parameter can be a value of @ref TIM_Trigger_Prescaler */
<>	144:ef7eb2e8f9f7	257	uint32_t TriggerFilter; /*!< Input trigger filter
<>	144:ef7eb2e8f9f7	258	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	}TIM_SlaveConfigTypeDef;
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/**
<>	144:ef7eb2e8f9f7	263	* @brief HAL State structures definition
<>	144:ef7eb2e8f9f7	264	*/
<>	144:ef7eb2e8f9f7	265	typedef enum
<>	144:ef7eb2e8f9f7	266	{
AnnaBridge	165:e614a9f1c9e2	267	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
AnnaBridge	165:e614a9f1c9e2	268	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
AnnaBridge	165:e614a9f1c9e2	269	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
AnnaBridge	165:e614a9f1c9e2	270	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
AnnaBridge	165:e614a9f1c9e2	271	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
<>	144:ef7eb2e8f9f7	272	}HAL_TIM_StateTypeDef;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/**
<>	144:ef7eb2e8f9f7	275	* @brief HAL Active channel structures definition
<>	144:ef7eb2e8f9f7	276	*/
<>	144:ef7eb2e8f9f7	277	typedef enum
<>	144:ef7eb2e8f9f7	278	{
AnnaBridge	165:e614a9f1c9e2	279	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
AnnaBridge	165:e614a9f1c9e2	280	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
AnnaBridge	165:e614a9f1c9e2	281	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
AnnaBridge	165:e614a9f1c9e2	282	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
AnnaBridge	165:e614a9f1c9e2	283	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
<>	144:ef7eb2e8f9f7	284	}HAL_TIM_ActiveChannel;
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	/**
<>	144:ef7eb2e8f9f7	287	* @brief TIM Time Base Handle Structure definition
<>	144:ef7eb2e8f9f7	288	*/
<>	144:ef7eb2e8f9f7	289	typedef struct
<>	144:ef7eb2e8f9f7	290	{
AnnaBridge	165:e614a9f1c9e2	291	TIM_TypeDef Instance; /!< Register base address */
AnnaBridge	165:e614a9f1c9e2	292	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
AnnaBridge	165:e614a9f1c9e2	293	HAL_TIM_ActiveChannel Channel; /!< Active channel /
AnnaBridge	165:e614a9f1c9e2	294	DMA_HandleTypeDef hdma[7U]; /!< DMA Handlers array
AnnaBridge	165:e614a9f1c9e2	295	This array is accessed by a @ref TIM_DMA_Handle_index */
AnnaBridge	165:e614a9f1c9e2	296	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	297	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
<>	144:ef7eb2e8f9f7	298	}TIM_HandleTypeDef;
<>	144:ef7eb2e8f9f7	299
<>	144:ef7eb2e8f9f7	300	/**
<>	144:ef7eb2e8f9f7	301	* @}
<>	144:ef7eb2e8f9f7	302	*/
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	305	/** @defgroup TIM_Exported_Constants TIM Exported Constants
<>	144:ef7eb2e8f9f7	306	* @{
<>	144:ef7eb2e8f9f7	307	*/
<>	144:ef7eb2e8f9f7	308
<>	144:ef7eb2e8f9f7	309	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
<>	144:ef7eb2e8f9f7	310	* @{
<>	144:ef7eb2e8f9f7	311	*/
AnnaBridge	165:e614a9f1c9e2	312	#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	313	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	314	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	315	/**
<>	144:ef7eb2e8f9f7	316	* @}
<>	144:ef7eb2e8f9f7	317	*/
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
<>	144:ef7eb2e8f9f7	320	* @{
<>	144:ef7eb2e8f9f7	321	*/
<>	144:ef7eb2e8f9f7	322	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
AnnaBridge	165:e614a9f1c9e2	323	#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /!< Polarity for ETR source /
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @}
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327
<>	144:ef7eb2e8f9f7	328	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
<>	144:ef7eb2e8f9f7	329	* @{
<>	144:ef7eb2e8f9f7	330	*/
AnnaBridge	165:e614a9f1c9e2	331	#define TIM_ETRPRESCALER_DIV1 0x00000000U /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	332	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
<>	144:ef7eb2e8f9f7	333	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
<>	144:ef7eb2e8f9f7	334	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
<>	144:ef7eb2e8f9f7	335	/**
<>	144:ef7eb2e8f9f7	336	* @}
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338
<>	144:ef7eb2e8f9f7	339	/** @defgroup TIM_Counter_Mode TIM Counter Mode
<>	144:ef7eb2e8f9f7	340	* @{
<>	144:ef7eb2e8f9f7	341	*/
AnnaBridge	165:e614a9f1c9e2	342	#define TIM_COUNTERMODE_UP 0x00000000U
<>	144:ef7eb2e8f9f7	343	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<>	144:ef7eb2e8f9f7	344	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<>	144:ef7eb2e8f9f7	345	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<>	144:ef7eb2e8f9f7	346	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @}
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/** @defgroup TIM_ClockDivision TIM ClockDivision
<>	144:ef7eb2e8f9f7	352	* @{
<>	144:ef7eb2e8f9f7	353	*/
AnnaBridge	165:e614a9f1c9e2	354	#define TIM_CLOCKDIVISION_DIV1 0x00000000U
<>	144:ef7eb2e8f9f7	355	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<>	144:ef7eb2e8f9f7	356	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<>	144:ef7eb2e8f9f7	357	/**
<>	144:ef7eb2e8f9f7	358	* @}
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360
AnnaBridge	165:e614a9f1c9e2	361	/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
AnnaBridge	165:e614a9f1c9e2	362	* @{
AnnaBridge	165:e614a9f1c9e2	363	*/
AnnaBridge	165:e614a9f1c9e2	364	#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x0000U /!< TIMx_ARR register is not buffered /
AnnaBridge	165:e614a9f1c9e2	365	#define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /!< TIMx_ARR register is buffered /
AnnaBridge	165:e614a9f1c9e2	366	/**
AnnaBridge	165:e614a9f1c9e2	367	* @}
AnnaBridge	165:e614a9f1c9e2	368	*/
AnnaBridge	165:e614a9f1c9e2	369
<>	144:ef7eb2e8f9f7	370	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
<>	144:ef7eb2e8f9f7	371	* @{
<>	144:ef7eb2e8f9f7	372	*/
AnnaBridge	165:e614a9f1c9e2	373	#define TIM_OCMODE_TIMING 0x00000000U
<>	144:ef7eb2e8f9f7	374	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	375	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	376	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	377	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	378	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<>	144:ef7eb2e8f9f7	379	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	380	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	381	/**
<>	144:ef7eb2e8f9f7	382	* @}
<>	144:ef7eb2e8f9f7	383	*/
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
<>	144:ef7eb2e8f9f7	386	* @{
<>	144:ef7eb2e8f9f7	387	*/
AnnaBridge	165:e614a9f1c9e2	388	#define TIM_OUTPUTSTATE_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	389	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
<>	144:ef7eb2e8f9f7	390	/**
<>	144:ef7eb2e8f9f7	391	* @}
<>	144:ef7eb2e8f9f7	392	*/
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
<>	144:ef7eb2e8f9f7	395	* @{
<>	144:ef7eb2e8f9f7	396	*/
AnnaBridge	165:e614a9f1c9e2	397	#define TIM_OCFAST_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	398	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<>	144:ef7eb2e8f9f7	399	/**
<>	144:ef7eb2e8f9f7	400	* @}
<>	144:ef7eb2e8f9f7	401	*/
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
<>	144:ef7eb2e8f9f7	404	* @{
<>	144:ef7eb2e8f9f7	405	*/
AnnaBridge	165:e614a9f1c9e2	406	#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	407	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
<>	144:ef7eb2e8f9f7	408	/**
<>	144:ef7eb2e8f9f7	409	* @}
<>	144:ef7eb2e8f9f7	410	*/
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
<>	144:ef7eb2e8f9f7	413	* @{
<>	144:ef7eb2e8f9f7	414	*/
AnnaBridge	165:e614a9f1c9e2	415	#define TIM_OCPOLARITY_HIGH 0x00000000U
<>	144:ef7eb2e8f9f7	416	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<>	144:ef7eb2e8f9f7	417	/**
<>	144:ef7eb2e8f9f7	418	* @}
<>	144:ef7eb2e8f9f7	419	*/
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
<>	144:ef7eb2e8f9f7	422	* @{
<>	144:ef7eb2e8f9f7	423	*/
AnnaBridge	165:e614a9f1c9e2	424	#define TIM_OCNPOLARITY_HIGH 0x00000000U
<>	144:ef7eb2e8f9f7	425	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
<>	144:ef7eb2e8f9f7	426	/**
<>	144:ef7eb2e8f9f7	427	* @}
<>	144:ef7eb2e8f9f7	428	*/
<>	144:ef7eb2e8f9f7	429
<>	144:ef7eb2e8f9f7	430	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
<>	144:ef7eb2e8f9f7	431	* @{
<>	144:ef7eb2e8f9f7	432	*/
<>	144:ef7eb2e8f9f7	433	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
AnnaBridge	165:e614a9f1c9e2	434	#define TIM_OCIDLESTATE_RESET 0x00000000U
<>	144:ef7eb2e8f9f7	435	/**
<>	144:ef7eb2e8f9f7	436	* @}
<>	144:ef7eb2e8f9f7	437	*/
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
<>	144:ef7eb2e8f9f7	440	* @{
<>	144:ef7eb2e8f9f7	441	*/
<>	144:ef7eb2e8f9f7	442	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
AnnaBridge	165:e614a9f1c9e2	443	#define TIM_OCNIDLESTATE_RESET 0x00000000U
<>	144:ef7eb2e8f9f7	444	/**
<>	144:ef7eb2e8f9f7	445	* @}
<>	144:ef7eb2e8f9f7	446	*/
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/** @defgroup TIM_Channel TIM Channel
<>	144:ef7eb2e8f9f7	449	* @{
<>	144:ef7eb2e8f9f7	450	*/
AnnaBridge	165:e614a9f1c9e2	451	#define TIM_CHANNEL_1 0x00000000U
AnnaBridge	165:e614a9f1c9e2	452	#define TIM_CHANNEL_2 0x00000004U
AnnaBridge	165:e614a9f1c9e2	453	#define TIM_CHANNEL_3 0x00000008U
AnnaBridge	165:e614a9f1c9e2	454	#define TIM_CHANNEL_4 0x0000000CU
AnnaBridge	165:e614a9f1c9e2	455	#define TIM_CHANNEL_ALL 0x00000018U
<>	144:ef7eb2e8f9f7	456	/**
<>	144:ef7eb2e8f9f7	457	* @}
<>	144:ef7eb2e8f9f7	458	*/
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
<>	144:ef7eb2e8f9f7	461	* @{
<>	144:ef7eb2e8f9f7	462	*/
<>	144:ef7eb2e8f9f7	463	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<>	144:ef7eb2e8f9f7	464	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	465	/**
<>	144:ef7eb2e8f9f7	466	* @}
<>	144:ef7eb2e8f9f7	467	*/
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
<>	144:ef7eb2e8f9f7	470	* @{
<>	144:ef7eb2e8f9f7	471	*/
<>	144:ef7eb2e8f9f7	472	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	473	connected to IC1, IC2, IC3 or IC4, respectively */
<>	144:ef7eb2e8f9f7	474	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	475	connected to IC2, IC1, IC4 or IC3, respectively */
<>	144:ef7eb2e8f9f7	476	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
<>	144:ef7eb2e8f9f7	477	/**
<>	144:ef7eb2e8f9f7	478	* @}
<>	144:ef7eb2e8f9f7	479	*/
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
<>	144:ef7eb2e8f9f7	482	* @{
<>	144:ef7eb2e8f9f7	483	*/
AnnaBridge	165:e614a9f1c9e2	484	#define TIM_ICPSC_DIV1 0x00000000U /!< Capture performed each time an edge is detected on the capture input /
<>	144:ef7eb2e8f9f7	485	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
<>	144:ef7eb2e8f9f7	486	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
<>	144:ef7eb2e8f9f7	487	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
<>	144:ef7eb2e8f9f7	488	/**
<>	144:ef7eb2e8f9f7	489	* @}
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
<>	144:ef7eb2e8f9f7	493	* @{
<>	144:ef7eb2e8f9f7	494	*/
<>	144:ef7eb2e8f9f7	495	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
AnnaBridge	165:e614a9f1c9e2	496	#define TIM_OPMODE_REPETITIVE 0x00000000U
<>	144:ef7eb2e8f9f7	497	/**
<>	144:ef7eb2e8f9f7	498	* @}
<>	144:ef7eb2e8f9f7	499	*/
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
<>	144:ef7eb2e8f9f7	502	* @{
<>	144:ef7eb2e8f9f7	503	*/
<>	144:ef7eb2e8f9f7	504	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	505	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<>	144:ef7eb2e8f9f7	506	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @}
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
<>	144:ef7eb2e8f9f7	512	* @{
<>	144:ef7eb2e8f9f7	513	*/
<>	144:ef7eb2e8f9f7	514	#define TIM_IT_UPDATE (TIM_DIER_UIE)
<>	144:ef7eb2e8f9f7	515	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
<>	144:ef7eb2e8f9f7	516	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
<>	144:ef7eb2e8f9f7	517	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
<>	144:ef7eb2e8f9f7	518	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
<>	144:ef7eb2e8f9f7	519	#define TIM_IT_COM (TIM_DIER_COMIE)
<>	144:ef7eb2e8f9f7	520	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
<>	144:ef7eb2e8f9f7	521	#define TIM_IT_BREAK (TIM_DIER_BIE)
<>	144:ef7eb2e8f9f7	522	/**
<>	144:ef7eb2e8f9f7	523	* @}
<>	144:ef7eb2e8f9f7	524	*/
<>	144:ef7eb2e8f9f7	525
<>	144:ef7eb2e8f9f7	526	/** @defgroup TIM_Commutation_Source TIM Commutation Source
<>	144:ef7eb2e8f9f7	527	* @{
<>	144:ef7eb2e8f9f7	528	*/
<>	144:ef7eb2e8f9f7	529	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
AnnaBridge	165:e614a9f1c9e2	530	#define TIM_COMMUTATION_SOFTWARE 0x00000000U
<>	144:ef7eb2e8f9f7	531
<>	144:ef7eb2e8f9f7	532	/**
<>	144:ef7eb2e8f9f7	533	* @}
<>	144:ef7eb2e8f9f7	534	*/
<>	144:ef7eb2e8f9f7	535
<>	144:ef7eb2e8f9f7	536	/** @defgroup TIM_DMA_sources TIM DMA Sources
<>	144:ef7eb2e8f9f7	537	* @{
<>	144:ef7eb2e8f9f7	538	*/
<>	144:ef7eb2e8f9f7	539	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
<>	144:ef7eb2e8f9f7	540	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<>	144:ef7eb2e8f9f7	541	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<>	144:ef7eb2e8f9f7	542	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<>	144:ef7eb2e8f9f7	543	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<>	144:ef7eb2e8f9f7	544	#define TIM_DMA_COM (TIM_DIER_COMDE)
<>	144:ef7eb2e8f9f7	545	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<>	144:ef7eb2e8f9f7	546	/**
<>	144:ef7eb2e8f9f7	547	* @}
<>	144:ef7eb2e8f9f7	548	*/
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	/** @defgroup TIM_Event_Source TIM Event Source
<>	144:ef7eb2e8f9f7	551	* @{
<>	144:ef7eb2e8f9f7	552	*/
<>	144:ef7eb2e8f9f7	553	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<>	144:ef7eb2e8f9f7	554	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<>	144:ef7eb2e8f9f7	555	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<>	144:ef7eb2e8f9f7	556	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<>	144:ef7eb2e8f9f7	557	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<>	144:ef7eb2e8f9f7	558	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
<>	144:ef7eb2e8f9f7	559	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<>	144:ef7eb2e8f9f7	560	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
<>	144:ef7eb2e8f9f7	561	/**
<>	144:ef7eb2e8f9f7	562	* @}
<>	144:ef7eb2e8f9f7	563	*/
<>	144:ef7eb2e8f9f7	564
<>	144:ef7eb2e8f9f7	565	/** @defgroup TIM_Flag_definition TIM Flag Definition
<>	144:ef7eb2e8f9f7	566	* @{
<>	144:ef7eb2e8f9f7	567	*/
<>	144:ef7eb2e8f9f7	568	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
<>	144:ef7eb2e8f9f7	569	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<>	144:ef7eb2e8f9f7	570	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<>	144:ef7eb2e8f9f7	571	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<>	144:ef7eb2e8f9f7	572	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<>	144:ef7eb2e8f9f7	573	#define TIM_FLAG_COM (TIM_SR_COMIF)
<>	144:ef7eb2e8f9f7	574	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<>	144:ef7eb2e8f9f7	575	#define TIM_FLAG_BREAK (TIM_SR_BIF)
<>	144:ef7eb2e8f9f7	576	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<>	144:ef7eb2e8f9f7	577	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<>	144:ef7eb2e8f9f7	578	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<>	144:ef7eb2e8f9f7	579	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<>	144:ef7eb2e8f9f7	580	/**
<>	144:ef7eb2e8f9f7	581	* @}
<>	144:ef7eb2e8f9f7	582	*/
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	/** @defgroup TIM_Clock_Source TIM Clock Source
<>	144:ef7eb2e8f9f7	585	* @{
<>	144:ef7eb2e8f9f7	586	*/
<>	144:ef7eb2e8f9f7	587	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<>	144:ef7eb2e8f9f7	588	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<>	144:ef7eb2e8f9f7	589	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
<>	144:ef7eb2e8f9f7	590	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<>	144:ef7eb2e8f9f7	591	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	592	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	593	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	594	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	595	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	596	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<>	144:ef7eb2e8f9f7	597	/**
<>	144:ef7eb2e8f9f7	598	* @}
<>	144:ef7eb2e8f9f7	599	*/
<>	144:ef7eb2e8f9f7	600
<>	144:ef7eb2e8f9f7	601	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
<>	144:ef7eb2e8f9f7	602	* @{
<>	144:ef7eb2e8f9f7	603	*/
AnnaBridge	165:e614a9f1c9e2	604	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	165:e614a9f1c9e2	605	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
AnnaBridge	165:e614a9f1c9e2	606	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	607	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	608	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	609	/**
<>	144:ef7eb2e8f9f7	610	* @}
<>	144:ef7eb2e8f9f7	611	*/
<>	144:ef7eb2e8f9f7	612
<>	144:ef7eb2e8f9f7	613	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
<>	144:ef7eb2e8f9f7	614	* @{
<>	144:ef7eb2e8f9f7	615	*/
<>	144:ef7eb2e8f9f7	616	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	617	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	618	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	619	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	620	/**
<>	144:ef7eb2e8f9f7	621	* @}
<>	144:ef7eb2e8f9f7	622	*/
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
<>	144:ef7eb2e8f9f7	625	* @{
<>	144:ef7eb2e8f9f7	626	*/
AnnaBridge	165:e614a9f1c9e2	627	#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
AnnaBridge	165:e614a9f1c9e2	628	#define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @}
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
<>	144:ef7eb2e8f9f7	634	* @{
<>	144:ef7eb2e8f9f7	635	*/
<>	144:ef7eb2e8f9f7	636	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
AnnaBridge	165:e614a9f1c9e2	637	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
<>	144:ef7eb2e8f9f7	638	/**
<>	144:ef7eb2e8f9f7	639	* @}
<>	144:ef7eb2e8f9f7	640	*/
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
<>	144:ef7eb2e8f9f7	643	* @{
<>	144:ef7eb2e8f9f7	644	*/
<>	144:ef7eb2e8f9f7	645	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	646	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	647	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	648	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	649	/**
<>	144:ef7eb2e8f9f7	650	* @}
<>	144:ef7eb2e8f9f7	651	*/
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
<>	144:ef7eb2e8f9f7	654	* @{
<>	144:ef7eb2e8f9f7	655	*/
<>	144:ef7eb2e8f9f7	656	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
AnnaBridge	165:e614a9f1c9e2	657	#define TIM_OSSR_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	658	/**
<>	144:ef7eb2e8f9f7	659	* @}
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
<>	144:ef7eb2e8f9f7	663	* @{
<>	144:ef7eb2e8f9f7	664	*/
<>	144:ef7eb2e8f9f7	665	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
AnnaBridge	165:e614a9f1c9e2	666	#define TIM_OSSI_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	667	/**
<>	144:ef7eb2e8f9f7	668	* @}
<>	144:ef7eb2e8f9f7	669	*/
<>	144:ef7eb2e8f9f7	670
<>	144:ef7eb2e8f9f7	671	/** @defgroup TIM_Lock_level TIM Lock level
<>	144:ef7eb2e8f9f7	672	* @{
<>	144:ef7eb2e8f9f7	673	*/
AnnaBridge	165:e614a9f1c9e2	674	#define TIM_LOCKLEVEL_OFF 0x00000000U
<>	144:ef7eb2e8f9f7	675	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
<>	144:ef7eb2e8f9f7	676	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
<>	144:ef7eb2e8f9f7	677	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
<>	144:ef7eb2e8f9f7	678	/**
<>	144:ef7eb2e8f9f7	679	* @}
<>	144:ef7eb2e8f9f7	680	*/
<>	144:ef7eb2e8f9f7	681
<>	144:ef7eb2e8f9f7	682	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
<>	144:ef7eb2e8f9f7	683	* @{
<>	144:ef7eb2e8f9f7	684	*/
<>	144:ef7eb2e8f9f7	685	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
AnnaBridge	165:e614a9f1c9e2	686	#define TIM_BREAK_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	687	/**
<>	144:ef7eb2e8f9f7	688	* @}
<>	144:ef7eb2e8f9f7	689	*/
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
<>	144:ef7eb2e8f9f7	692	* @{
<>	144:ef7eb2e8f9f7	693	*/
AnnaBridge	165:e614a9f1c9e2	694	#define TIM_BREAKPOLARITY_LOW 0x00000000U
<>	144:ef7eb2e8f9f7	695	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
<>	144:ef7eb2e8f9f7	696	/**
<>	144:ef7eb2e8f9f7	697	* @}
<>	144:ef7eb2e8f9f7	698	*/
<>	144:ef7eb2e8f9f7	699	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
<>	144:ef7eb2e8f9f7	700	* @{
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
AnnaBridge	165:e614a9f1c9e2	703	#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	704	/**
<>	144:ef7eb2e8f9f7	705	* @}
<>	144:ef7eb2e8f9f7	706	*/
<>	144:ef7eb2e8f9f7	707
<>	144:ef7eb2e8f9f7	708	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<>	144:ef7eb2e8f9f7	709	* @{
<>	144:ef7eb2e8f9f7	710	*/
AnnaBridge	165:e614a9f1c9e2	711	#define TIM_TRGO_RESET 0x00000000U
<>	144:ef7eb2e8f9f7	712	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<>	144:ef7eb2e8f9f7	713	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<>	144:ef7eb2e8f9f7	714	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	715	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<>	144:ef7eb2e8f9f7	716	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	717	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
<>	144:ef7eb2e8f9f7	718	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	719	/**
<>	144:ef7eb2e8f9f7	720	* @}
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722
<>	144:ef7eb2e8f9f7	723	/** @defgroup TIM_Slave_Mode TIM Slave Mode
<>	144:ef7eb2e8f9f7	724	* @{
<>	144:ef7eb2e8f9f7	725	*/
AnnaBridge	165:e614a9f1c9e2	726	#define TIM_SLAVEMODE_DISABLE 0x00000000U
AnnaBridge	165:e614a9f1c9e2	727	#define TIM_SLAVEMODE_RESET 0x00000004U
AnnaBridge	165:e614a9f1c9e2	728	#define TIM_SLAVEMODE_GATED 0x00000005U
AnnaBridge	165:e614a9f1c9e2	729	#define TIM_SLAVEMODE_TRIGGER 0x00000006U
AnnaBridge	165:e614a9f1c9e2	730	#define TIM_SLAVEMODE_EXTERNAL1 0x00000007U
<>	144:ef7eb2e8f9f7	731	/**
<>	144:ef7eb2e8f9f7	732	* @}
<>	144:ef7eb2e8f9f7	733	*/
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
<>	144:ef7eb2e8f9f7	736	* @{
<>	144:ef7eb2e8f9f7	737	*/
AnnaBridge	165:e614a9f1c9e2	738	#define TIM_MASTERSLAVEMODE_ENABLE 0x00000080U
AnnaBridge	165:e614a9f1c9e2	739	#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	740	/**
<>	144:ef7eb2e8f9f7	741	* @}
<>	144:ef7eb2e8f9f7	742	*/
<>	144:ef7eb2e8f9f7	743
<>	144:ef7eb2e8f9f7	744	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
<>	144:ef7eb2e8f9f7	745	* @{
<>	144:ef7eb2e8f9f7	746	*/
AnnaBridge	165:e614a9f1c9e2	747	#define TIM_TS_ITR0 0x00000000U
AnnaBridge	165:e614a9f1c9e2	748	#define TIM_TS_ITR1 0x00000010U
AnnaBridge	165:e614a9f1c9e2	749	#define TIM_TS_ITR2 0x00000020U
AnnaBridge	165:e614a9f1c9e2	750	#define TIM_TS_ITR3 0x00000030U
AnnaBridge	165:e614a9f1c9e2	751	#define TIM_TS_TI1F_ED 0x00000040U
AnnaBridge	165:e614a9f1c9e2	752	#define TIM_TS_TI1FP1 0x00000050U
AnnaBridge	165:e614a9f1c9e2	753	#define TIM_TS_TI2FP2 0x00000060U
AnnaBridge	165:e614a9f1c9e2	754	#define TIM_TS_ETRF 0x00000070U
AnnaBridge	165:e614a9f1c9e2	755	#define TIM_TS_NONE 0x0000FFFFU
<>	144:ef7eb2e8f9f7	756	/**
<>	144:ef7eb2e8f9f7	757	* @}
<>	144:ef7eb2e8f9f7	758	*/
<>	144:ef7eb2e8f9f7	759
<>	144:ef7eb2e8f9f7	760	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
<>	144:ef7eb2e8f9f7	761	* @{
<>	144:ef7eb2e8f9f7	762	*/
<>	144:ef7eb2e8f9f7	763	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
<>	144:ef7eb2e8f9f7	764	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
<>	144:ef7eb2e8f9f7	765	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	766	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	767	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	768	/**
<>	144:ef7eb2e8f9f7	769	* @}
<>	144:ef7eb2e8f9f7	770	*/
<>	144:ef7eb2e8f9f7	771
<>	144:ef7eb2e8f9f7	772	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
<>	144:ef7eb2e8f9f7	773	* @{
<>	144:ef7eb2e8f9f7	774	*/
<>	144:ef7eb2e8f9f7	775	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	776	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	777	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	778	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	779	/**
<>	144:ef7eb2e8f9f7	780	* @}
<>	144:ef7eb2e8f9f7	781	*/
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
<>	144:ef7eb2e8f9f7	784	* @{
<>	144:ef7eb2e8f9f7	785	*/
AnnaBridge	165:e614a9f1c9e2	786	#define TIM_TI1SELECTION_CH1 0x00000000U
<>	144:ef7eb2e8f9f7	787	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<>	144:ef7eb2e8f9f7	788	/**
<>	144:ef7eb2e8f9f7	789	* @}
<>	144:ef7eb2e8f9f7	790	*/
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
<>	144:ef7eb2e8f9f7	793	* @{
<>	144:ef7eb2e8f9f7	794	*/
AnnaBridge	165:e614a9f1c9e2	795	#define TIM_DMABASE_CR1 0x00000000U
AnnaBridge	165:e614a9f1c9e2	796	#define TIM_DMABASE_CR2 0x00000001U
AnnaBridge	165:e614a9f1c9e2	797	#define TIM_DMABASE_SMCR 0x00000002U
AnnaBridge	165:e614a9f1c9e2	798	#define TIM_DMABASE_DIER 0x00000003U
AnnaBridge	165:e614a9f1c9e2	799	#define TIM_DMABASE_SR 0x00000004U
AnnaBridge	165:e614a9f1c9e2	800	#define TIM_DMABASE_EGR 0x00000005U
AnnaBridge	165:e614a9f1c9e2	801	#define TIM_DMABASE_CCMR1 0x00000006U
AnnaBridge	165:e614a9f1c9e2	802	#define TIM_DMABASE_CCMR2 0x00000007U
AnnaBridge	165:e614a9f1c9e2	803	#define TIM_DMABASE_CCER 0x00000008U
AnnaBridge	165:e614a9f1c9e2	804	#define TIM_DMABASE_CNT 0x00000009U
AnnaBridge	165:e614a9f1c9e2	805	#define TIM_DMABASE_PSC 0x0000000AU
AnnaBridge	165:e614a9f1c9e2	806	#define TIM_DMABASE_ARR 0x0000000BU
AnnaBridge	165:e614a9f1c9e2	807	#define TIM_DMABASE_RCR 0x0000000CU
AnnaBridge	165:e614a9f1c9e2	808	#define TIM_DMABASE_CCR1 0x0000000DU
AnnaBridge	165:e614a9f1c9e2	809	#define TIM_DMABASE_CCR2 0x0000000EU
AnnaBridge	165:e614a9f1c9e2	810	#define TIM_DMABASE_CCR3 0x0000000FU
AnnaBridge	165:e614a9f1c9e2	811	#define TIM_DMABASE_CCR4 0x00000010U
AnnaBridge	165:e614a9f1c9e2	812	#define TIM_DMABASE_BDTR 0x00000011U
AnnaBridge	165:e614a9f1c9e2	813	#define TIM_DMABASE_DCR 0x00000012U
<>	144:ef7eb2e8f9f7	814	/**
<>	144:ef7eb2e8f9f7	815	* @}
<>	144:ef7eb2e8f9f7	816	*/
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
<>	144:ef7eb2e8f9f7	819	* @{
<>	144:ef7eb2e8f9f7	820	*/
AnnaBridge	165:e614a9f1c9e2	821	#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
AnnaBridge	165:e614a9f1c9e2	822	#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
AnnaBridge	165:e614a9f1c9e2	823	#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
AnnaBridge	165:e614a9f1c9e2	824	#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
AnnaBridge	165:e614a9f1c9e2	825	#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
AnnaBridge	165:e614a9f1c9e2	826	#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
AnnaBridge	165:e614a9f1c9e2	827	#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
AnnaBridge	165:e614a9f1c9e2	828	#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
AnnaBridge	165:e614a9f1c9e2	829	#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
AnnaBridge	165:e614a9f1c9e2	830	#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
AnnaBridge	165:e614a9f1c9e2	831	#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
AnnaBridge	165:e614a9f1c9e2	832	#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
AnnaBridge	165:e614a9f1c9e2	833	#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
AnnaBridge	165:e614a9f1c9e2	834	#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
AnnaBridge	165:e614a9f1c9e2	835	#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
AnnaBridge	165:e614a9f1c9e2	836	#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
AnnaBridge	165:e614a9f1c9e2	837	#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
AnnaBridge	165:e614a9f1c9e2	838	#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
<>	144:ef7eb2e8f9f7	839	/**
<>	144:ef7eb2e8f9f7	840	* @}
<>	144:ef7eb2e8f9f7	841	*/
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
<>	144:ef7eb2e8f9f7	844	* @{
<>	144:ef7eb2e8f9f7	845	*/
AnnaBridge	165:e614a9f1c9e2	846	#define TIM_DMA_ID_UPDATE ((uint16_t)0x0) /!< Index of the DMA handle used for Update DMA requests /
AnnaBridge	165:e614a9f1c9e2	847	#define TIM_DMA_ID_CC1 ((uint16_t)0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
AnnaBridge	165:e614a9f1c9e2	848	#define TIM_DMA_ID_CC2 ((uint16_t)0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
AnnaBridge	165:e614a9f1c9e2	849	#define TIM_DMA_ID_CC3 ((uint16_t)0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
AnnaBridge	165:e614a9f1c9e2	850	#define TIM_DMA_ID_CC4 ((uint16_t)0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
AnnaBridge	165:e614a9f1c9e2	851	#define TIM_DMA_ID_COMMUTATION ((uint16_t)0x5) /!< Index of the DMA handle used for Commutation DMA requests /
AnnaBridge	165:e614a9f1c9e2	852	#define TIM_DMA_ID_TRIGGER ((uint16_t)0x6) /!< Index of the DMA handle used for Trigger DMA requests /
<>	144:ef7eb2e8f9f7	853	/**
<>	144:ef7eb2e8f9f7	854	* @}
<>	144:ef7eb2e8f9f7	855	*/
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
<>	144:ef7eb2e8f9f7	858	* @{
<>	144:ef7eb2e8f9f7	859	*/
AnnaBridge	165:e614a9f1c9e2	860	#define TIM_CCx_ENABLE 0x00000001U
AnnaBridge	165:e614a9f1c9e2	861	#define TIM_CCx_DISABLE 0x00000000U
AnnaBridge	165:e614a9f1c9e2	862	#define TIM_CCxN_ENABLE 0x00000004U
AnnaBridge	165:e614a9f1c9e2	863	#define TIM_CCxN_DISABLE 0x00000000U
<>	144:ef7eb2e8f9f7	864	/**
<>	144:ef7eb2e8f9f7	865	* @}
<>	144:ef7eb2e8f9f7	866	*/
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	/**
<>	144:ef7eb2e8f9f7	869	* @}
<>	144:ef7eb2e8f9f7	870	*/
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872	/* Private Constants -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	873	/** @defgroup TIM_Private_Constants TIM Private Constants
<>	144:ef7eb2e8f9f7	874	* @{
<>	144:ef7eb2e8f9f7	875	*/
<>	144:ef7eb2e8f9f7	876
<>	144:ef7eb2e8f9f7	877	/* The counter of a timer instance is disabled only if all the CCx and CCxN
<>	144:ef7eb2e8f9f7	878	channels have been disabled */
<>	144:ef7eb2e8f9f7	879	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
<>	144:ef7eb2e8f9f7	880	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/**
<>	144:ef7eb2e8f9f7	883	* @}
<>	144:ef7eb2e8f9f7	884	*/
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	/* Private Macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	887	/** @defgroup TIM_Private_Macros TIM Private Macros
<>	144:ef7eb2e8f9f7	888	* @{
<>	144:ef7eb2e8f9f7	889	*/
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
<>	144:ef7eb2e8f9f7	892	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
<>	144:ef7eb2e8f9f7	893	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
<>	144:ef7eb2e8f9f7	894	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
<>	144:ef7eb2e8f9f7	895	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
<>	144:ef7eb2e8f9f7	896
<>	144:ef7eb2e8f9f7	897	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	898	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	899	((DIV) == TIM_CLOCKDIVISION_DIV4))
<>	144:ef7eb2e8f9f7	900
AnnaBridge	165:e614a9f1c9e2	901	#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) \|\| \
AnnaBridge	165:e614a9f1c9e2	902	((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
AnnaBridge	165:e614a9f1c9e2	903
<>	144:ef7eb2e8f9f7	904	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	905	((MODE) == TIM_OCMODE_PWM2))
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
<>	144:ef7eb2e8f9f7	908	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	909	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	910	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	911	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	912	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	915	((STATE) == TIM_OCFAST_ENABLE))
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	918	((POLARITY) == TIM_OCPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	921	((POLARITY) == TIM_OCNPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	922
<>	144:ef7eb2e8f9f7	923	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
<>	144:ef7eb2e8f9f7	924	((STATE) == TIM_OCIDLESTATE_RESET))
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
<>	144:ef7eb2e8f9f7	927	((STATE) == TIM_OCNIDLESTATE_RESET))
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	930	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	931	((CHANNEL) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	932	((CHANNEL) == TIM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	933	((CHANNEL) == TIM_CHANNEL_ALL))
AnnaBridge	165:e614a9f1c9e2	934
<>	144:ef7eb2e8f9f7	935	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
AnnaBridge	165:e614a9f1c9e2	936	((CHANNEL) == TIM_CHANNEL_2))
AnnaBridge	165:e614a9f1c9e2	937
<>	144:ef7eb2e8f9f7	938	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	939	((CHANNEL) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	940	((CHANNEL) == TIM_CHANNEL_3))
<>	144:ef7eb2e8f9f7	941
<>	144:ef7eb2e8f9f7	942	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
AnnaBridge	165:e614a9f1c9e2	943	((POLARITY) == TIM_ICPOLARITY_FALLING))
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	946	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	947	((SELECTION) == TIM_ICSELECTION_TRC))
<>	144:ef7eb2e8f9f7	948
<>	144:ef7eb2e8f9f7	949	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	950	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	951	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	952	((PRESCALER) == TIM_ICPSC_DIV8))
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
<>	144:ef7eb2e8f9f7	955	((MODE) == TIM_OPMODE_REPETITIVE))
<>	144:ef7eb2e8f9f7	956
<>	144:ef7eb2e8f9f7	957	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	958	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	959	((MODE) == TIM_ENCODERMODE_TI12))
<>	144:ef7eb2e8f9f7	960
AnnaBridge	165:e614a9f1c9e2	961	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FFU) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	962
AnnaBridge	165:e614a9f1c9e2	963	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00U) == 0x00000000U) && ((SOURCE) != 0x00000000U))
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	966	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
<>	144:ef7eb2e8f9f7	967	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	968	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	969	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	970	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	971	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
<>	144:ef7eb2e8f9f7	972	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	973	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	974	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	977	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	978	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	979	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	980	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
<>	144:ef7eb2e8f9f7	981
<>	144:ef7eb2e8f9f7	982	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	983	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	984	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	985	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	986
AnnaBridge	165:e614a9f1c9e2	987	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	144:ef7eb2e8f9f7	988
<>	144:ef7eb2e8f9f7	989	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
<>	144:ef7eb2e8f9f7	990	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	993	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	996	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	997	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	998	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	999
AnnaBridge	165:e614a9f1c9e2	1000	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	144:ef7eb2e8f9f7	1001
<>	144:ef7eb2e8f9f7	1002	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1003	((STATE) == TIM_OSSR_DISABLE))
<>	144:ef7eb2e8f9f7	1004
<>	144:ef7eb2e8f9f7	1005	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1006	((STATE) == TIM_OSSI_DISABLE))
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
<>	144:ef7eb2e8f9f7	1009	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
<>	144:ef7eb2e8f9f7	1010	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
<>	144:ef7eb2e8f9f7	1011	((LEVEL) == TIM_LOCKLEVEL_3))
<>	144:ef7eb2e8f9f7	1012
<>	144:ef7eb2e8f9f7	1013	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1014	((STATE) == TIM_BREAK_DISABLE))
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
<>	144:ef7eb2e8f9f7	1017	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1020	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
<>	144:ef7eb2e8f9f7	1021
<>	144:ef7eb2e8f9f7	1022	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
<>	144:ef7eb2e8f9f7	1023	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1024	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	1025	((SOURCE) == TIM_TRGO_OC1) \|\| \
<>	144:ef7eb2e8f9f7	1026	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
<>	144:ef7eb2e8f9f7	1027	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
<>	144:ef7eb2e8f9f7	1028	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
<>	144:ef7eb2e8f9f7	1029	((SOURCE) == TIM_TRGO_OC4REF))
<>	144:ef7eb2e8f9f7	1030
<>	144:ef7eb2e8f9f7	1031	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1032	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
<>	144:ef7eb2e8f9f7	1033	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	1034	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	1035	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1038	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	1041	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	1042	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	1043	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	1044	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
<>	144:ef7eb2e8f9f7	1045	((SELECTION) == TIM_TS_TI1FP1) \|\| \
<>	144:ef7eb2e8f9f7	1046	((SELECTION) == TIM_TS_TI2FP2) \|\| \
<>	144:ef7eb2e8f9f7	1047	((SELECTION) == TIM_TS_ETRF))
<>	144:ef7eb2e8f9f7	1048
<>	144:ef7eb2e8f9f7	1049	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	1050	((SELECTION) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	1051	((SELECTION) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	1052	((SELECTION) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	1053	((SELECTION) == TIM_TS_NONE))
<>	144:ef7eb2e8f9f7	1054
<>	144:ef7eb2e8f9f7	1055	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
<>	144:ef7eb2e8f9f7	1056	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	1057	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
<>	144:ef7eb2e8f9f7	1058	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
<>	144:ef7eb2e8f9f7	1059	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<>	144:ef7eb2e8f9f7	1060
<>	144:ef7eb2e8f9f7	1061	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	1062	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1063	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1064	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	1065
AnnaBridge	165:e614a9f1c9e2	1066	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
<>	144:ef7eb2e8f9f7	1069	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
<>	144:ef7eb2e8f9f7	1070
<>	144:ef7eb2e8f9f7	1071	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
<>	144:ef7eb2e8f9f7	1072	((BASE) == TIM_DMABASE_CR2) \|\| \
<>	144:ef7eb2e8f9f7	1073	((BASE) == TIM_DMABASE_SMCR) \|\| \
<>	144:ef7eb2e8f9f7	1074	((BASE) == TIM_DMABASE_DIER) \|\| \
<>	144:ef7eb2e8f9f7	1075	((BASE) == TIM_DMABASE_SR) \|\| \
<>	144:ef7eb2e8f9f7	1076	((BASE) == TIM_DMABASE_EGR) \|\| \
<>	144:ef7eb2e8f9f7	1077	((BASE) == TIM_DMABASE_CCMR1) \|\| \
<>	144:ef7eb2e8f9f7	1078	((BASE) == TIM_DMABASE_CCMR2) \|\| \
<>	144:ef7eb2e8f9f7	1079	((BASE) == TIM_DMABASE_CCER) \|\| \
<>	144:ef7eb2e8f9f7	1080	((BASE) == TIM_DMABASE_CNT) \|\| \
<>	144:ef7eb2e8f9f7	1081	((BASE) == TIM_DMABASE_PSC) \|\| \
<>	144:ef7eb2e8f9f7	1082	((BASE) == TIM_DMABASE_ARR) \|\| \
<>	144:ef7eb2e8f9f7	1083	((BASE) == TIM_DMABASE_RCR) \|\| \
<>	144:ef7eb2e8f9f7	1084	((BASE) == TIM_DMABASE_CCR1) \|\| \
<>	144:ef7eb2e8f9f7	1085	((BASE) == TIM_DMABASE_CCR2) \|\| \
<>	144:ef7eb2e8f9f7	1086	((BASE) == TIM_DMABASE_CCR3) \|\| \
<>	144:ef7eb2e8f9f7	1087	((BASE) == TIM_DMABASE_CCR4) \|\| \
<>	144:ef7eb2e8f9f7	1088	((BASE) == TIM_DMABASE_BDTR) \|\| \
<>	144:ef7eb2e8f9f7	1089	((BASE) == TIM_DMABASE_DCR))
<>	144:ef7eb2e8f9f7	1090
<>	144:ef7eb2e8f9f7	1091	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
<>	144:ef7eb2e8f9f7	1092	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1093	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1094	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1095	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1096	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1097	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1098	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1099	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1100	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1101	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1102	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1103	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1104	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1105	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1106	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1107	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	1108	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
<>	144:ef7eb2e8f9f7	1109
AnnaBridge	165:e614a9f1c9e2	1110	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0x0FU)
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/** @brief Set TIM IC prescaler
<>	144:ef7eb2e8f9f7	1113	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1114	* @param __CHANNEL__: specifies TIM Channel
<>	144:ef7eb2e8f9f7	1115	* @param __ICPSC__: specifies the prescaler value.
<>	144:ef7eb2e8f9f7	1116	* @retval None
<>	144:ef7eb2e8f9f7	1117	*/
<>	144:ef7eb2e8f9f7	1118	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1119	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
AnnaBridge	165:e614a9f1c9e2	1120	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
<>	144:ef7eb2e8f9f7	1121	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
AnnaBridge	165:e614a9f1c9e2	1122	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8U)))
<>	144:ef7eb2e8f9f7	1123
<>	144:ef7eb2e8f9f7	1124	/** @brief Reset TIM IC prescaler
<>	144:ef7eb2e8f9f7	1125	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1126	* @param __CHANNEL__: specifies TIM Channel
<>	144:ef7eb2e8f9f7	1127	* @retval None
<>	144:ef7eb2e8f9f7	1128	*/
<>	144:ef7eb2e8f9f7	1129	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1130	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
<>	144:ef7eb2e8f9f7	1131	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
<>	144:ef7eb2e8f9f7	1132	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
<>	144:ef7eb2e8f9f7	1133	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
<>	144:ef7eb2e8f9f7	1134
<>	144:ef7eb2e8f9f7	1135
<>	144:ef7eb2e8f9f7	1136	/** @brief Set TIM IC polarity
<>	144:ef7eb2e8f9f7	1137	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1138	* @param __CHANNEL__: specifies TIM Channel
<>	144:ef7eb2e8f9f7	1139	* @param __POLARITY__: specifies TIM Channel Polarity
<>	144:ef7eb2e8f9f7	1140	* @retval None
<>	144:ef7eb2e8f9f7	1141	*/
<>	144:ef7eb2e8f9f7	1142	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1143	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
AnnaBridge	165:e614a9f1c9e2	1144	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
AnnaBridge	165:e614a9f1c9e2	1145	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
AnnaBridge	165:e614a9f1c9e2	1146	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
<>	144:ef7eb2e8f9f7	1147
<>	144:ef7eb2e8f9f7	1148	/** @brief Reset TIM IC polarity
<>	144:ef7eb2e8f9f7	1149	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1150	* @param __CHANNEL__: specifies TIM Channel
<>	144:ef7eb2e8f9f7	1151	* @retval None
<>	144:ef7eb2e8f9f7	1152	*/
<>	144:ef7eb2e8f9f7	1153	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1154	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
<>	144:ef7eb2e8f9f7	1155	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
<>	144:ef7eb2e8f9f7	1156	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
<>	144:ef7eb2e8f9f7	1157	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<>	144:ef7eb2e8f9f7	1158
<>	144:ef7eb2e8f9f7	1159	/**
<>	144:ef7eb2e8f9f7	1160	* @}
<>	144:ef7eb2e8f9f7	1161	*/
<>	144:ef7eb2e8f9f7	1162
<>	144:ef7eb2e8f9f7	1163	/* Private Functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1164	/** @addtogroup TIM_Private_Functions
<>	144:ef7eb2e8f9f7	1165	* @{
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
<>	144:ef7eb2e8f9f7	1168	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
<>	144:ef7eb2e8f9f7	1169	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
<>	144:ef7eb2e8f9f7	1170	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1171	void TIM_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1172	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1173	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
<>	144:ef7eb2e8f9f7	1174	/**
<>	144:ef7eb2e8f9f7	1175	* @}
<>	144:ef7eb2e8f9f7	1176	*/
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1179	/** @defgroup TIM_Exported_Macros TIM Exported Macros
<>	144:ef7eb2e8f9f7	1180	* @{
<>	144:ef7eb2e8f9f7	1181	*/
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/** @brief Reset TIM handle state
<>	144:ef7eb2e8f9f7	1184	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1185	* @retval None
<>	144:ef7eb2e8f9f7	1186	*/
<>	144:ef7eb2e8f9f7	1187	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1188
<>	144:ef7eb2e8f9f7	1189	/**
<>	144:ef7eb2e8f9f7	1190	* @brief Enable the TIM peripheral.
<>	144:ef7eb2e8f9f7	1191	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1192	* @retval None
<>	144:ef7eb2e8f9f7	1193	*/
<>	144:ef7eb2e8f9f7	1194	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/**
<>	144:ef7eb2e8f9f7	1197	* @brief Enable the TIM main Output.
<>	144:ef7eb2e8f9f7	1198	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1199	* @retval None
<>	144:ef7eb2e8f9f7	1200	*/
<>	144:ef7eb2e8f9f7	1201	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/**
<>	144:ef7eb2e8f9f7	1204	* @brief Disable the TIM peripheral.
<>	144:ef7eb2e8f9f7	1205	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1206	* @retval None
<>	144:ef7eb2e8f9f7	1207	*/
<>	144:ef7eb2e8f9f7	1208	#define __HAL_TIM_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1209	do { \
AnnaBridge	165:e614a9f1c9e2	1210	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1211	{ \
AnnaBridge	165:e614a9f1c9e2	1212	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1213	{ \
<>	144:ef7eb2e8f9f7	1214	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<>	144:ef7eb2e8f9f7	1215	} \
<>	144:ef7eb2e8f9f7	1216	} \
AnnaBridge	165:e614a9f1c9e2	1217	} while(0U)
<>	144:ef7eb2e8f9f7	1218	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
<>	144:ef7eb2e8f9f7	1219	channels have been disabled */
<>	144:ef7eb2e8f9f7	1220	/**
<>	144:ef7eb2e8f9f7	1221	* @brief Disable the TIM main Output.
<>	144:ef7eb2e8f9f7	1222	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1223	* @retval None
<>	144:ef7eb2e8f9f7	1224	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
<>	144:ef7eb2e8f9f7	1225	*/
<>	144:ef7eb2e8f9f7	1226	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1227	do { \
AnnaBridge	165:e614a9f1c9e2	1228	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1229	{ \
AnnaBridge	165:e614a9f1c9e2	1230	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1231	{ \
<>	144:ef7eb2e8f9f7	1232	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
<>	144:ef7eb2e8f9f7	1233	} \
<>	144:ef7eb2e8f9f7	1234	} \
AnnaBridge	165:e614a9f1c9e2	1235	} while(0U)
AnnaBridge	165:e614a9f1c9e2	1236
AnnaBridge	165:e614a9f1c9e2	1237	/**
AnnaBridge	165:e614a9f1c9e2	1238	* @brief Disable the TIM main Output.
AnnaBridge	165:e614a9f1c9e2	1239	* @param __HANDLE__: TIM handle
AnnaBridge	165:e614a9f1c9e2	1240	* @retval None
AnnaBridge	165:e614a9f1c9e2	1241	* @note The Main Output Enable of a timer instance is disabled unconditionally
AnnaBridge	165:e614a9f1c9e2	1242	*/
AnnaBridge	165:e614a9f1c9e2	1243	#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
<>	144:ef7eb2e8f9f7	1244
<>	144:ef7eb2e8f9f7	1245	/**
<>	144:ef7eb2e8f9f7	1246	* @brief Enables the specified TIM interrupt.
<>	144:ef7eb2e8f9f7	1247	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1248	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
<>	144:ef7eb2e8f9f7	1249	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1250	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	165:e614a9f1c9e2	1251	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<>	144:ef7eb2e8f9f7	1252	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<>	144:ef7eb2e8f9f7	1253	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<>	144:ef7eb2e8f9f7	1254	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	165:e614a9f1c9e2	1255	* @arg TIM_IT_COM: Commutation interrupt
<>	144:ef7eb2e8f9f7	1256	* @arg TIM_IT_TRIGGER: Trigger interrupt
<>	144:ef7eb2e8f9f7	1257	* @arg TIM_IT_BREAK: Break interrupt
<>	144:ef7eb2e8f9f7	1258	* @retval None
<>	144:ef7eb2e8f9f7	1259	*/
<>	144:ef7eb2e8f9f7	1260	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/**
<>	144:ef7eb2e8f9f7	1263	* @brief Disables the specified TIM interrupt.
<>	144:ef7eb2e8f9f7	1264	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1265	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
<>	144:ef7eb2e8f9f7	1266	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1267	* @arg TIM_IT_UPDATE: Update interrupt
AnnaBridge	165:e614a9f1c9e2	1268	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
<>	144:ef7eb2e8f9f7	1269	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
<>	144:ef7eb2e8f9f7	1270	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
<>	144:ef7eb2e8f9f7	1271	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
AnnaBridge	165:e614a9f1c9e2	1272	* @arg TIM_IT_COM: Commutation interrupt
<>	144:ef7eb2e8f9f7	1273	* @arg TIM_IT_TRIGGER: Trigger interrupt
<>	144:ef7eb2e8f9f7	1274	* @arg TIM_IT_BREAK: Break interrupt
<>	144:ef7eb2e8f9f7	1275	* @retval None
<>	144:ef7eb2e8f9f7	1276	*/
<>	144:ef7eb2e8f9f7	1277	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	/**
<>	144:ef7eb2e8f9f7	1280	* @brief Enables the specified DMA request.
<>	144:ef7eb2e8f9f7	1281	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1282	* @param __DMA__: specifies the TIM DMA request to enable.
<>	144:ef7eb2e8f9f7	1283	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1284	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	165:e614a9f1c9e2	1285	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<>	144:ef7eb2e8f9f7	1286	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<>	144:ef7eb2e8f9f7	1287	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<>	144:ef7eb2e8f9f7	1288	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	165:e614a9f1c9e2	1289	* @arg TIM_DMA_COM: Commutation DMA request
<>	144:ef7eb2e8f9f7	1290	* @arg TIM_DMA_TRIGGER: Trigger DMA request
<>	144:ef7eb2e8f9f7	1291	* @retval None
<>	144:ef7eb2e8f9f7	1292	*/
<>	144:ef7eb2e8f9f7	1293	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
<>	144:ef7eb2e8f9f7	1294
<>	144:ef7eb2e8f9f7	1295	/**
<>	144:ef7eb2e8f9f7	1296	* @brief Disables the specified DMA request.
<>	144:ef7eb2e8f9f7	1297	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1298	* @param __DMA__: specifies the TIM DMA request to disable.
<>	144:ef7eb2e8f9f7	1299	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1300	* @arg TIM_DMA_UPDATE: Update DMA request
AnnaBridge	165:e614a9f1c9e2	1301	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
<>	144:ef7eb2e8f9f7	1302	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
<>	144:ef7eb2e8f9f7	1303	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
<>	144:ef7eb2e8f9f7	1304	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
AnnaBridge	165:e614a9f1c9e2	1305	* @arg TIM_DMA_COM: Commutation DMA request
<>	144:ef7eb2e8f9f7	1306	* @arg TIM_DMA_TRIGGER: Trigger DMA request
<>	144:ef7eb2e8f9f7	1307	* @retval None
<>	144:ef7eb2e8f9f7	1308	*/
<>	144:ef7eb2e8f9f7	1309	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/**
<>	144:ef7eb2e8f9f7	1312	* @brief Checks whether the specified TIM interrupt flag is set or not.
<>	144:ef7eb2e8f9f7	1313	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1314	* @param __FLAG__: specifies the TIM interrupt flag to check.
<>	144:ef7eb2e8f9f7	1315	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1316	* @arg TIM_FLAG_UPDATE: Update interrupt flag
<>	144:ef7eb2e8f9f7	1317	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<>	144:ef7eb2e8f9f7	1318	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<>	144:ef7eb2e8f9f7	1319	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<>	144:ef7eb2e8f9f7	1320	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<>	144:ef7eb2e8f9f7	1321	* @arg TIM_FLAG_COM: Commutation interrupt flag
<>	144:ef7eb2e8f9f7	1322	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<>	144:ef7eb2e8f9f7	1323	* @arg TIM_FLAG_BREAK: Break interrupt flag
<>	144:ef7eb2e8f9f7	1324	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<>	144:ef7eb2e8f9f7	1325	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<>	144:ef7eb2e8f9f7	1326	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<>	144:ef7eb2e8f9f7	1327	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<>	144:ef7eb2e8f9f7	1328	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1329	*/
<>	144:ef7eb2e8f9f7	1330	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	1331
<>	144:ef7eb2e8f9f7	1332	/**
<>	144:ef7eb2e8f9f7	1333	* @brief Clears the specified TIM interrupt flag.
<>	144:ef7eb2e8f9f7	1334	* @param __HANDLE__: specifies the TIM Handle.
<>	144:ef7eb2e8f9f7	1335	* @param __FLAG__: specifies the TIM interrupt flag to clear.
<>	144:ef7eb2e8f9f7	1336	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1337	* @arg TIM_FLAG_UPDATE: Update interrupt flag
<>	144:ef7eb2e8f9f7	1338	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
<>	144:ef7eb2e8f9f7	1339	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
<>	144:ef7eb2e8f9f7	1340	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
<>	144:ef7eb2e8f9f7	1341	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
<>	144:ef7eb2e8f9f7	1342	* @arg TIM_FLAG_COM: Commutation interrupt flag
<>	144:ef7eb2e8f9f7	1343	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
<>	144:ef7eb2e8f9f7	1344	* @arg TIM_FLAG_BREAK: Break interrupt flag
<>	144:ef7eb2e8f9f7	1345	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
<>	144:ef7eb2e8f9f7	1346	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
<>	144:ef7eb2e8f9f7	1347	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
<>	144:ef7eb2e8f9f7	1348	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
<>	144:ef7eb2e8f9f7	1349	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1350	*/
<>	144:ef7eb2e8f9f7	1351	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<>	144:ef7eb2e8f9f7	1352
<>	144:ef7eb2e8f9f7	1353	/**
<>	144:ef7eb2e8f9f7	1354	* @brief Checks whether the specified TIM interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1355	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1356	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
<>	144:ef7eb2e8f9f7	1357	* @retval The state of TIM_IT (SET or RESET).
<>	144:ef7eb2e8f9f7	1358	*/
<>	144:ef7eb2e8f9f7	1359	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	1360
<>	144:ef7eb2e8f9f7	1361	/**
<>	144:ef7eb2e8f9f7	1362	* @brief Clear the TIM interrupt pending bits
<>	144:ef7eb2e8f9f7	1363	* @param __HANDLE__: TIM handle
<>	144:ef7eb2e8f9f7	1364	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1365	* @retval None
<>	144:ef7eb2e8f9f7	1366	*/
<>	144:ef7eb2e8f9f7	1367	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1368
<>	144:ef7eb2e8f9f7	1369	/**
<>	144:ef7eb2e8f9f7	1370	* @brief Indicates whether or not the TIM Counter is used as downcounter
<>	144:ef7eb2e8f9f7	1371	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1372	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
<>	144:ef7eb2e8f9f7	1373	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
<>	144:ef7eb2e8f9f7	1374	mode.
<>	144:ef7eb2e8f9f7	1375	*/
<>	144:ef7eb2e8f9f7	1376	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
<>	144:ef7eb2e8f9f7	1377
<>	144:ef7eb2e8f9f7	1378	/**
<>	144:ef7eb2e8f9f7	1379	* @brief Sets the TIM active prescaler register value on update event.
<>	144:ef7eb2e8f9f7	1380	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1381	* @param __PRESC__: specifies the active prescaler register new value.
<>	144:ef7eb2e8f9f7	1382	* @retval None
<>	144:ef7eb2e8f9f7	1383	*/
<>	144:ef7eb2e8f9f7	1384	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<>	144:ef7eb2e8f9f7	1385
<>	144:ef7eb2e8f9f7	1386	/**
<>	144:ef7eb2e8f9f7	1387	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	144:ef7eb2e8f9f7	1388	* calling another time ConfigChannel function.
<>	144:ef7eb2e8f9f7	1389	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1390	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1391	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1392	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1393	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1394	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1395	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1396	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	144:ef7eb2e8f9f7	1397	* @retval None
<>	144:ef7eb2e8f9f7	1398	*/
<>	144:ef7eb2e8f9f7	1399	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
AnnaBridge	165:e614a9f1c9e2	1400	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<>	144:ef7eb2e8f9f7	1401
<>	144:ef7eb2e8f9f7	1402	/**
<>	144:ef7eb2e8f9f7	1403	* @brief Gets the TIM Capture Compare Register value on runtime
<>	144:ef7eb2e8f9f7	1404	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1405	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
<>	144:ef7eb2e8f9f7	1406	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1407	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	144:ef7eb2e8f9f7	1408	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	144:ef7eb2e8f9f7	1409	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	144:ef7eb2e8f9f7	1410	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
AnnaBridge	165:e614a9f1c9e2	1411	* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
<>	144:ef7eb2e8f9f7	1412	*/
<>	144:ef7eb2e8f9f7	1413	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
AnnaBridge	165:e614a9f1c9e2	1414	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<>	144:ef7eb2e8f9f7	1415
<>	144:ef7eb2e8f9f7	1416	/**
<>	144:ef7eb2e8f9f7	1417	* @brief Sets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1418	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1419	* @param __COUNTER__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1420	* @retval None
<>	144:ef7eb2e8f9f7	1421	*/
<>	144:ef7eb2e8f9f7	1422	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<>	144:ef7eb2e8f9f7	1423
<>	144:ef7eb2e8f9f7	1424	/**
<>	144:ef7eb2e8f9f7	1425	* @brief Gets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1426	* @param __HANDLE__: TIM handle.
AnnaBridge	165:e614a9f1c9e2	1427	* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
<>	144:ef7eb2e8f9f7	1428	*/
<>	144:ef7eb2e8f9f7	1429	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1430	((__HANDLE__)->Instance->CNT)
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	/**
<>	144:ef7eb2e8f9f7	1433	* @brief Sets the TIM Autoreload Register value on runtime without calling
<>	144:ef7eb2e8f9f7	1434	* another time any Init function.
<>	144:ef7eb2e8f9f7	1435	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1436	* @param __AUTORELOAD__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1437	* @retval None
<>	144:ef7eb2e8f9f7	1438	*/
<>	144:ef7eb2e8f9f7	1439	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<>	144:ef7eb2e8f9f7	1440	do{ \
<>	144:ef7eb2e8f9f7	1441	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<>	144:ef7eb2e8f9f7	1442	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
AnnaBridge	165:e614a9f1c9e2	1443	} while(0U)
<>	144:ef7eb2e8f9f7	1444
<>	144:ef7eb2e8f9f7	1445	/**
<>	144:ef7eb2e8f9f7	1446	* @brief Gets the TIM Autoreload Register value on runtime
<>	144:ef7eb2e8f9f7	1447	* @param __HANDLE__: TIM handle.
AnnaBridge	165:e614a9f1c9e2	1448	* @retval @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
<>	144:ef7eb2e8f9f7	1449	*/
<>	144:ef7eb2e8f9f7	1450	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1451	((__HANDLE__)->Instance->ARR)
<>	144:ef7eb2e8f9f7	1452
<>	144:ef7eb2e8f9f7	1453	/**
<>	144:ef7eb2e8f9f7	1454	* @brief Sets the TIM Clock Division value on runtime without calling
<>	144:ef7eb2e8f9f7	1455	* another time any Init function.
<>	144:ef7eb2e8f9f7	1456	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1457	* @param __CKD__: specifies the clock division value.
<>	144:ef7eb2e8f9f7	1458	* This parameter can be one of the following value:
AnnaBridge	165:e614a9f1c9e2	1459	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	165:e614a9f1c9e2	1460	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	165:e614a9f1c9e2	1461	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
<>	144:ef7eb2e8f9f7	1462	* @retval None
<>	144:ef7eb2e8f9f7	1463	*/
<>	144:ef7eb2e8f9f7	1464	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
AnnaBridge	165:e614a9f1c9e2	1465	do{ \
<>	144:ef7eb2e8f9f7	1466	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
AnnaBridge	165:e614a9f1c9e2	1467	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
<>	144:ef7eb2e8f9f7	1468	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
AnnaBridge	165:e614a9f1c9e2	1469	} while(0U)
<>	144:ef7eb2e8f9f7	1470
<>	144:ef7eb2e8f9f7	1471	/**
<>	144:ef7eb2e8f9f7	1472	* @brief Gets the TIM Clock Division value on runtime
<>	144:ef7eb2e8f9f7	1473	* @param __HANDLE__: TIM handle.
AnnaBridge	165:e614a9f1c9e2	1474	* @retval The clock division can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1475	* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
AnnaBridge	165:e614a9f1c9e2	1476	* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
AnnaBridge	165:e614a9f1c9e2	1477	* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
<>	144:ef7eb2e8f9f7	1478	*/
<>	144:ef7eb2e8f9f7	1479	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1480	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	/**
<>	144:ef7eb2e8f9f7	1483	* @brief Sets the TIM Input Capture prescaler on runtime without calling
<>	144:ef7eb2e8f9f7	1484	* another time HAL_TIM_IC_ConfigChannel() function.
<>	144:ef7eb2e8f9f7	1485	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1486	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1487	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1488	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1489	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1490	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1491	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1492	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<>	144:ef7eb2e8f9f7	1493	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1494	* @arg TIM_ICPSC_DIV1: no prescaler
<>	144:ef7eb2e8f9f7	1495	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<>	144:ef7eb2e8f9f7	1496	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<>	144:ef7eb2e8f9f7	1497	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	144:ef7eb2e8f9f7	1498	* @retval None
<>	144:ef7eb2e8f9f7	1499	*/
<>	144:ef7eb2e8f9f7	1500	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1501	do{ \
<>	144:ef7eb2e8f9f7	1502	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1503	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
AnnaBridge	165:e614a9f1c9e2	1504	} while(0U)
<>	144:ef7eb2e8f9f7	1505
<>	144:ef7eb2e8f9f7	1506	/**
<>	144:ef7eb2e8f9f7	1507	* @brief Gets the TIM Input Capture prescaler on runtime
<>	144:ef7eb2e8f9f7	1508	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1509	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1510	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1511	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<>	144:ef7eb2e8f9f7	1512	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<>	144:ef7eb2e8f9f7	1513	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<>	144:ef7eb2e8f9f7	1514	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
AnnaBridge	165:e614a9f1c9e2	1515	* @retval The input capture prescaler can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1516	* @arg TIM_ICPSC_DIV1: no prescaler
AnnaBridge	165:e614a9f1c9e2	1517	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
AnnaBridge	165:e614a9f1c9e2	1518	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
AnnaBridge	165:e614a9f1c9e2	1519	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	144:ef7eb2e8f9f7	1520	*/
<>	144:ef7eb2e8f9f7	1521	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1522	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
AnnaBridge	165:e614a9f1c9e2	1523	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
<>	144:ef7eb2e8f9f7	1524	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
AnnaBridge	165:e614a9f1c9e2	1525	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<>	144:ef7eb2e8f9f7	1526
<>	144:ef7eb2e8f9f7	1527	/**
<>	144:ef7eb2e8f9f7	1528	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1529	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1530	* @note When the USR bit of the TIMx_CR1 register is set, only counter
<>	144:ef7eb2e8f9f7	1531	* overflow/underflow generates an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1532	* enabled)
<>	144:ef7eb2e8f9f7	1533	* @retval None
<>	144:ef7eb2e8f9f7	1534	*/
<>	144:ef7eb2e8f9f7	1535	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1536	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1537
<>	144:ef7eb2e8f9f7	1538	/**
<>	144:ef7eb2e8f9f7	1539	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1540	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1541	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
<>	144:ef7eb2e8f9f7	1542	* following events generate an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1543	* enabled):
<>	144:ef7eb2e8f9f7	1544	* (+) Counter overflow/underflow
<>	144:ef7eb2e8f9f7	1545	* (+) Setting the UG bit
<>	144:ef7eb2e8f9f7	1546	* (+) Update generation through the slave mode controller
<>	144:ef7eb2e8f9f7	1547	* @retval None
<>	144:ef7eb2e8f9f7	1548	*/
<>	144:ef7eb2e8f9f7	1549	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1550	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	/**
<>	144:ef7eb2e8f9f7	1553	* @brief Sets the TIM Capture x input polarity on runtime.
<>	144:ef7eb2e8f9f7	1554	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1555	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1556	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1557	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1558	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1559	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1560	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1561	* @param __POLARITY__: Polarity for TIx source
<>	144:ef7eb2e8f9f7	1562	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<>	144:ef7eb2e8f9f7	1563	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<>	144:ef7eb2e8f9f7	1564	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<>	144:ef7eb2e8f9f7	1565	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<>	144:ef7eb2e8f9f7	1566	* @retval None
<>	144:ef7eb2e8f9f7	1567	*/
<>	144:ef7eb2e8f9f7	1568	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1569	do{ \
<>	144:ef7eb2e8f9f7	1570	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1571	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
AnnaBridge	165:e614a9f1c9e2	1572	}while(0U)
<>	144:ef7eb2e8f9f7	1573
<>	144:ef7eb2e8f9f7	1574	/**
<>	144:ef7eb2e8f9f7	1575	* @}
<>	144:ef7eb2e8f9f7	1576	*/
<>	144:ef7eb2e8f9f7	1577
<>	144:ef7eb2e8f9f7	1578	/* Include TIM HAL Extension module */
<>	144:ef7eb2e8f9f7	1579	#include "stm32f1xx_hal_tim_ex.h"
<>	144:ef7eb2e8f9f7	1580
<>	144:ef7eb2e8f9f7	1581	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1582	/** @addtogroup TIM_Exported_Functions
<>	144:ef7eb2e8f9f7	1583	* @{
<>	144:ef7eb2e8f9f7	1584	*/
<>	144:ef7eb2e8f9f7	1585
<>	144:ef7eb2e8f9f7	1586	/** @addtogroup TIM_Exported_Functions_Group1
<>	144:ef7eb2e8f9f7	1587	* @{
<>	144:ef7eb2e8f9f7	1588	*/
<>	144:ef7eb2e8f9f7	1589	/* Time Base functions ********************************************************/
<>	144:ef7eb2e8f9f7	1590	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1591	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1592	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1593	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1594	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1595	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1596	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1597	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1598	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1599	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1600	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1601	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1602	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1603	/**
<>	144:ef7eb2e8f9f7	1604	* @}
<>	144:ef7eb2e8f9f7	1605	*/
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	/** @addtogroup TIM_Exported_Functions_Group2
<>	144:ef7eb2e8f9f7	1608	* @{
<>	144:ef7eb2e8f9f7	1609	*/
<>	144:ef7eb2e8f9f7	1610	/* Timer Output Compare functions **********************************************/
<>	144:ef7eb2e8f9f7	1611	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1612	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1613	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1614	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1615	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1616	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1617	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1618	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1619	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1620	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1621	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1622	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1623	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1624
<>	144:ef7eb2e8f9f7	1625	/**
<>	144:ef7eb2e8f9f7	1626	* @}
<>	144:ef7eb2e8f9f7	1627	*/
<>	144:ef7eb2e8f9f7	1628
<>	144:ef7eb2e8f9f7	1629	/** @addtogroup TIM_Exported_Functions_Group3
<>	144:ef7eb2e8f9f7	1630	* @{
<>	144:ef7eb2e8f9f7	1631	*/
<>	144:ef7eb2e8f9f7	1632	/* Timer PWM functions *********************************************************/
<>	144:ef7eb2e8f9f7	1633	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1634	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1635	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1636	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1637	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1638	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1639	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1640	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1641	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1642	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1643	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1644	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1645	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1646	/**
<>	144:ef7eb2e8f9f7	1647	* @}
<>	144:ef7eb2e8f9f7	1648	*/
<>	144:ef7eb2e8f9f7	1649
<>	144:ef7eb2e8f9f7	1650	/** @addtogroup TIM_Exported_Functions_Group4
<>	144:ef7eb2e8f9f7	1651	* @{
<>	144:ef7eb2e8f9f7	1652	*/
<>	144:ef7eb2e8f9f7	1653	/* Timer Input Capture functions ***********************************************/
<>	144:ef7eb2e8f9f7	1654	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1655	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1656	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1657	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1658	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1659	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1660	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1661	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1662	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1663	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1664	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1665	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1666	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1667	/**
<>	144:ef7eb2e8f9f7	1668	* @}
<>	144:ef7eb2e8f9f7	1669	*/
<>	144:ef7eb2e8f9f7	1670
<>	144:ef7eb2e8f9f7	1671	/** @addtogroup TIM_Exported_Functions_Group5
<>	144:ef7eb2e8f9f7	1672	* @{
<>	144:ef7eb2e8f9f7	1673	*/
<>	144:ef7eb2e8f9f7	1674	/* Timer One Pulse functions ***************************************************/
<>	144:ef7eb2e8f9f7	1675	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<>	144:ef7eb2e8f9f7	1676	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1677	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1678	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1679	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1680	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1681	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1682	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1683	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1684	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1685	/**
<>	144:ef7eb2e8f9f7	1686	* @}
<>	144:ef7eb2e8f9f7	1687	*/
<>	144:ef7eb2e8f9f7	1688
<>	144:ef7eb2e8f9f7	1689	/** @addtogroup TIM_Exported_Functions_Group6
<>	144:ef7eb2e8f9f7	1690	* @{
<>	144:ef7eb2e8f9f7	1691	*/
<>	144:ef7eb2e8f9f7	1692	/* Timer Encoder functions *****************************************************/
<>	144:ef7eb2e8f9f7	1693	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
<>	144:ef7eb2e8f9f7	1694	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1695	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1696	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1697	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1698	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1699	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1700	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1701	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1702	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1703	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1704	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
<>	144:ef7eb2e8f9f7	1705	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1706
<>	144:ef7eb2e8f9f7	1707	/**
<>	144:ef7eb2e8f9f7	1708	* @}
<>	144:ef7eb2e8f9f7	1709	*/
<>	144:ef7eb2e8f9f7	1710
<>	144:ef7eb2e8f9f7	1711	/** @addtogroup TIM_Exported_Functions_Group7
<>	144:ef7eb2e8f9f7	1712	* @{
<>	144:ef7eb2e8f9f7	1713	*/
<>	144:ef7eb2e8f9f7	1714	/* Interrupt Handler functions **********************************************/
<>	144:ef7eb2e8f9f7	1715	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1716	/**
<>	144:ef7eb2e8f9f7	1717	* @}
<>	144:ef7eb2e8f9f7	1718	*/
<>	144:ef7eb2e8f9f7	1719
<>	144:ef7eb2e8f9f7	1720	/** @addtogroup TIM_Exported_Functions_Group8
<>	144:ef7eb2e8f9f7	1721	* @{
<>	144:ef7eb2e8f9f7	1722	*/
<>	144:ef7eb2e8f9f7	1723	/* Control functions *********************************************************/
<>	144:ef7eb2e8f9f7	1724	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1725	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1726	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1727	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<>	144:ef7eb2e8f9f7	1728	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1729	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
<>	144:ef7eb2e8f9f7	1730	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<>	144:ef7eb2e8f9f7	1731	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1732	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1733	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1734	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1735	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1736	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1737	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1738	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1739	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<>	144:ef7eb2e8f9f7	1740	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1741
<>	144:ef7eb2e8f9f7	1742	/**
<>	144:ef7eb2e8f9f7	1743	* @}
<>	144:ef7eb2e8f9f7	1744	*/
<>	144:ef7eb2e8f9f7	1745
<>	144:ef7eb2e8f9f7	1746	/** @addtogroup TIM_Exported_Functions_Group9
<>	144:ef7eb2e8f9f7	1747	* @{
<>	144:ef7eb2e8f9f7	1748	*/
<>	144:ef7eb2e8f9f7	1749	/* Callback in non blocking modes (Interrupt and DMA) *************************/
<>	144:ef7eb2e8f9f7	1750	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1751	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1752	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1753	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1754	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1755	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1756	/**
<>	144:ef7eb2e8f9f7	1757	* @}
<>	144:ef7eb2e8f9f7	1758	*/
<>	144:ef7eb2e8f9f7	1759
<>	144:ef7eb2e8f9f7	1760	/** @addtogroup TIM_Exported_Functions_Group10
<>	144:ef7eb2e8f9f7	1761	* @{
<>	144:ef7eb2e8f9f7	1762	*/
<>	144:ef7eb2e8f9f7	1763	/* Peripheral State functions **************************************************/
<>	144:ef7eb2e8f9f7	1764	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1765	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1766	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1767	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1768	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1769	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	/**
<>	144:ef7eb2e8f9f7	1772	* @}
<>	144:ef7eb2e8f9f7	1773	*/
<>	144:ef7eb2e8f9f7	1774
<>	144:ef7eb2e8f9f7	1775	/**
<>	144:ef7eb2e8f9f7	1776	* @}
<>	144:ef7eb2e8f9f7	1777	*/
<>	144:ef7eb2e8f9f7	1778
<>	144:ef7eb2e8f9f7	1779	/**
<>	144:ef7eb2e8f9f7	1780	* @}
<>	144:ef7eb2e8f9f7	1781	*/
<>	144:ef7eb2e8f9f7	1782
<>	144:ef7eb2e8f9f7	1783	/**
<>	144:ef7eb2e8f9f7	1784	* @}
<>	144:ef7eb2e8f9f7	1785	*/
<>	144:ef7eb2e8f9f7	1786
<>	144:ef7eb2e8f9f7	1787	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1788	}
<>	144:ef7eb2e8f9f7	1789	#endif
<>	144:ef7eb2e8f9f7	1790
<>	144:ef7eb2e8f9f7	1791	#endif /* __STM32F1xx_HAL_TIM_H */
<>	144:ef7eb2e8f9f7	1792
<>	144:ef7eb2e8f9f7	1793	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	23 Jun 2015
Imports:	10846
Forks:	45
Commits:	190
Dependents:	95
Dependencies:	0
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The code in this repository is Apache licensed.

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

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