mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_spi.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_spi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SPI HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
AnnaBridge 165:e614a9f1c9e2 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
AnnaBridge 165:e614a9f1c9e2 62 /**
AnnaBridge 165:e614a9f1c9e2 63 * @brief SPI Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
AnnaBridge 165:e614a9f1c9e2 68 This parameter can be a value of @ref SPI_Mode */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
AnnaBridge 165:e614a9f1c9e2 71 This parameter can be a value of @ref SPI_Direction */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t DataSize; /*!< Specifies the SPI data size.
AnnaBridge 165:e614a9f1c9e2 74 This parameter can be a value of @ref SPI_Data_Size */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref SPI_Clock_Phase */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 144:ef7eb2e8f9f7 83 hardware (NSS pin) or by software using the SSI bit.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 144:ef7eb2e8f9f7 87 used to configure the transmit and receive SCK clock.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 89 @note The communication clock is derived from the master
AnnaBridge 165:e614a9f1c9e2 90 clock. The slave clock does not need to be set. */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref SPI_TI_mode */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 144:ef7eb2e8f9f7 102 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
<> 144:ef7eb2e8f9f7 103 }SPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * @brief HAL SPI State structure definition
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 typedef enum
<> 144:ef7eb2e8f9f7 109 {
AnnaBridge 165:e614a9f1c9e2 110 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
AnnaBridge 165:e614a9f1c9e2 111 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 165:e614a9f1c9e2 112 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
AnnaBridge 165:e614a9f1c9e2 113 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
AnnaBridge 165:e614a9f1c9e2 114 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
AnnaBridge 165:e614a9f1c9e2 115 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
AnnaBridge 165:e614a9f1c9e2 116 HAL_SPI_STATE_ERROR = 0x06U /*!< SPI error state */
<> 144:ef7eb2e8f9f7 117 }HAL_SPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 118
AnnaBridge 165:e614a9f1c9e2 119 /**
<> 144:ef7eb2e8f9f7 120 * @brief SPI handle Structure definition
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 typedef struct __SPI_HandleTypeDef
<> 144:ef7eb2e8f9f7 123 {
<> 144:ef7eb2e8f9f7 124 SPI_TypeDef *Instance; /*!< SPI registers base address */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 SPI_InitTypeDef Init; /*!< SPI communication parameters */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 129
AnnaBridge 165:e614a9f1c9e2 130 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
AnnaBridge 165:e614a9f1c9e2 131
AnnaBridge 165:e614a9f1c9e2 132 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 135
AnnaBridge 165:e614a9f1c9e2 136 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
<> 144:ef7eb2e8f9f7 137
AnnaBridge 165:e614a9f1c9e2 138 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */
<> 144:ef7eb2e8f9f7 143
AnnaBridge 165:e614a9f1c9e2 144 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
AnnaBridge 165:e614a9f1c9e2 145
AnnaBridge 165:e614a9f1c9e2 146 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
AnnaBridge 165:e614a9f1c9e2 147
AnnaBridge 165:e614a9f1c9e2 148 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
<> 144:ef7eb2e8f9f7 151
AnnaBridge 165:e614a9f1c9e2 152 __IO uint32_t ErrorCode; /*!< SPI Error code */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 }SPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
AnnaBridge 165:e614a9f1c9e2 160 /* Exported constants --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 161 /** @defgroup SPI_Exported_Constants SPI Exported Constants
AnnaBridge 165:e614a9f1c9e2 162 * @{
AnnaBridge 165:e614a9f1c9e2 163 */
AnnaBridge 165:e614a9f1c9e2 164
AnnaBridge 165:e614a9f1c9e2 165 /** @defgroup SPI_Error_Code SPI Error Code
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
AnnaBridge 165:e614a9f1c9e2 168 #define HAL_SPI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 165:e614a9f1c9e2 169 #define HAL_SPI_ERROR_MODF 0x00000001U /*!< MODF error */
AnnaBridge 165:e614a9f1c9e2 170 #define HAL_SPI_ERROR_CRC 0x00000002U /*!< CRC error */
AnnaBridge 165:e614a9f1c9e2 171 #define HAL_SPI_ERROR_OVR 0x00000004U /*!< OVR error */
AnnaBridge 165:e614a9f1c9e2 172 #define HAL_SPI_ERROR_FRE 0x00000008U /*!< FRE error */
AnnaBridge 165:e614a9f1c9e2 173 #define HAL_SPI_ERROR_DMA 0x00000010U /*!< DMA transfer error */
AnnaBridge 165:e614a9f1c9e2 174 #define HAL_SPI_ERROR_FLAG 0x00000020U /*!< Flag: RXNE,TXE, BSY */
<> 144:ef7eb2e8f9f7 175 /**
<> 144:ef7eb2e8f9f7 176 * @}
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
AnnaBridge 165:e614a9f1c9e2 179 /** @defgroup SPI_Mode SPI Mode
AnnaBridge 165:e614a9f1c9e2 180 * @{
AnnaBridge 165:e614a9f1c9e2 181 */
AnnaBridge 165:e614a9f1c9e2 182 #define SPI_MODE_SLAVE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 183 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
AnnaBridge 165:e614a9f1c9e2 184 /**
AnnaBridge 165:e614a9f1c9e2 185 * @}
AnnaBridge 165:e614a9f1c9e2 186 */
AnnaBridge 165:e614a9f1c9e2 187
AnnaBridge 165:e614a9f1c9e2 188 /** @defgroup SPI_Direction SPI Direction Mode
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
AnnaBridge 165:e614a9f1c9e2 191 #define SPI_DIRECTION_2LINES 0x00000000U
AnnaBridge 165:e614a9f1c9e2 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
AnnaBridge 165:e614a9f1c9e2 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 144:ef7eb2e8f9f7 194 /**
<> 144:ef7eb2e8f9f7 195 * @}
AnnaBridge 165:e614a9f1c9e2 196 */
AnnaBridge 165:e614a9f1c9e2 197
AnnaBridge 165:e614a9f1c9e2 198 /** @defgroup SPI_Data_Size SPI Data Size
AnnaBridge 165:e614a9f1c9e2 199 * @{
AnnaBridge 165:e614a9f1c9e2 200 */
AnnaBridge 165:e614a9f1c9e2 201 #define SPI_DATASIZE_8BIT 0x00000000U
AnnaBridge 165:e614a9f1c9e2 202 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
AnnaBridge 165:e614a9f1c9e2 203 /**
AnnaBridge 165:e614a9f1c9e2 204 * @}
AnnaBridge 165:e614a9f1c9e2 205 */
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 144:ef7eb2e8f9f7 208 * @{
<> 144:ef7eb2e8f9f7 209 */
AnnaBridge 165:e614a9f1c9e2 210 #define SPI_POLARITY_LOW 0x00000000U
<> 144:ef7eb2e8f9f7 211 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 144:ef7eb2e8f9f7 217 * @{
<> 144:ef7eb2e8f9f7 218 */
AnnaBridge 165:e614a9f1c9e2 219 #define SPI_PHASE_1EDGE 0x00000000U
<> 144:ef7eb2e8f9f7 220 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
AnnaBridge 165:e614a9f1c9e2 221 /**
AnnaBridge 165:e614a9f1c9e2 222 * @}
AnnaBridge 165:e614a9f1c9e2 223 */
AnnaBridge 165:e614a9f1c9e2 224
AnnaBridge 165:e614a9f1c9e2 225 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
AnnaBridge 165:e614a9f1c9e2 226 * @{
AnnaBridge 165:e614a9f1c9e2 227 */
AnnaBridge 165:e614a9f1c9e2 228 #define SPI_NSS_SOFT SPI_CR1_SSM
AnnaBridge 165:e614a9f1c9e2 229 #define SPI_NSS_HARD_INPUT 0x00000000U
AnnaBridge 165:e614a9f1c9e2 230 #define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16))
AnnaBridge 165:e614a9f1c9e2 231 /**
AnnaBridge 165:e614a9f1c9e2 232 * @}
AnnaBridge 165:e614a9f1c9e2 233 */
AnnaBridge 165:e614a9f1c9e2 234
AnnaBridge 165:e614a9f1c9e2 235 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
AnnaBridge 165:e614a9f1c9e2 236 * @{
AnnaBridge 165:e614a9f1c9e2 237 */
AnnaBridge 165:e614a9f1c9e2 238 #define SPI_BAUDRATEPRESCALER_2 0x00000000U
AnnaBridge 165:e614a9f1c9e2 239 #define SPI_BAUDRATEPRESCALER_4 SPI_CR1_BR_0
AnnaBridge 165:e614a9f1c9e2 240 #define SPI_BAUDRATEPRESCALER_8 SPI_CR1_BR_1
AnnaBridge 165:e614a9f1c9e2 241 #define SPI_BAUDRATEPRESCALER_16 (uint32_t)(SPI_CR1_BR_1 | SPI_CR1_BR_0)
AnnaBridge 165:e614a9f1c9e2 242 #define SPI_BAUDRATEPRESCALER_32 SPI_CR1_BR_2
AnnaBridge 165:e614a9f1c9e2 243 #define SPI_BAUDRATEPRESCALER_64 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_0)
AnnaBridge 165:e614a9f1c9e2 244 #define SPI_BAUDRATEPRESCALER_128 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1)
AnnaBridge 165:e614a9f1c9e2 245 #define SPI_BAUDRATEPRESCALER_256 (uint32_t)(SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
AnnaBridge 165:e614a9f1c9e2 251 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
AnnaBridge 165:e614a9f1c9e2 254 #define SPI_FIRSTBIT_MSB 0x00000000U
<> 144:ef7eb2e8f9f7 255 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
AnnaBridge 165:e614a9f1c9e2 260 /** @defgroup SPI_TI_mode SPI TI Mode
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
AnnaBridge 165:e614a9f1c9e2 263 #define SPI_TIMODE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @}
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267
AnnaBridge 165:e614a9f1c9e2 268 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
AnnaBridge 165:e614a9f1c9e2 269 * @{
AnnaBridge 165:e614a9f1c9e2 270 */
AnnaBridge 165:e614a9f1c9e2 271 #define SPI_CRCCALCULATION_DISABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 272 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
AnnaBridge 165:e614a9f1c9e2 273 /**
AnnaBridge 165:e614a9f1c9e2 274 * @}
AnnaBridge 165:e614a9f1c9e2 275 */
AnnaBridge 165:e614a9f1c9e2 276
AnnaBridge 165:e614a9f1c9e2 277 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
<> 144:ef7eb2e8f9f7 278 * @{
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 281 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 282 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
AnnaBridge 165:e614a9f1c9e2 287 /** @defgroup SPI_Flags_definition SPI Flags Definition
<> 144:ef7eb2e8f9f7 288 * @{
<> 144:ef7eb2e8f9f7 289 */
AnnaBridge 165:e614a9f1c9e2 290 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
AnnaBridge 165:e614a9f1c9e2 291 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
AnnaBridge 165:e614a9f1c9e2 292 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
AnnaBridge 165:e614a9f1c9e2 293 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
AnnaBridge 165:e614a9f1c9e2 294 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
AnnaBridge 165:e614a9f1c9e2 295 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /**
<> 144:ef7eb2e8f9f7 301 * @}
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 305 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 144:ef7eb2e8f9f7 306 * @{
<> 144:ef7eb2e8f9f7 307 */
<> 144:ef7eb2e8f9f7 308
AnnaBridge 165:e614a9f1c9e2 309 /** @brief Reset SPI handle state.
AnnaBridge 165:e614a9f1c9e2 310 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 311 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 312 * @retval None
<> 144:ef7eb2e8f9f7 313 */
<> 144:ef7eb2e8f9f7 314 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /** @brief Enable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 317 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 318 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 319 * @param __INTERRUPT__: specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 320 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 321 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 322 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 323 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 324 * @retval None
<> 144:ef7eb2e8f9f7 325 */
AnnaBridge 165:e614a9f1c9e2 326 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /** @brief Disable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 329 * @param __HANDLE__: specifies the SPI handle.
<> 144:ef7eb2e8f9f7 330 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 331 * @param __INTERRUPT__: specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 332 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 333 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 334 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 335 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 336 * @retval None
<> 144:ef7eb2e8f9f7 337 */
AnnaBridge 165:e614a9f1c9e2 338 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 339
AnnaBridge 165:e614a9f1c9e2 340 /** @brief Check whether the specified SPI interrupt source is enabled or not.
AnnaBridge 165:e614a9f1c9e2 341 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 342 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 343 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 144:ef7eb2e8f9f7 344 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 345 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 346 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 347 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 348 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /** @brief Check whether the specified SPI flag is set or not.
AnnaBridge 165:e614a9f1c9e2 353 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 354 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 355 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 356 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 357 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 358 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 359 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 144:ef7eb2e8f9f7 360 * @arg SPI_FLAG_MODF: Mode fault flag
<> 144:ef7eb2e8f9f7 361 * @arg SPI_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 362 * @arg SPI_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 363 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /** @brief Clear the SPI CRCERR pending flag.
<> 144:ef7eb2e8f9f7 368 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 369 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 370 * @retval None
<> 144:ef7eb2e8f9f7 371 */
AnnaBridge 165:e614a9f1c9e2 372 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 373
AnnaBridge 165:e614a9f1c9e2 374 /** @brief Clear the SPI MODF pending flag.
<> 144:ef7eb2e8f9f7 375 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 376 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 377 * @retval None
<> 144:ef7eb2e8f9f7 378 */
AnnaBridge 165:e614a9f1c9e2 379 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
AnnaBridge 165:e614a9f1c9e2 380 do{ \
AnnaBridge 165:e614a9f1c9e2 381 __IO uint32_t tmpreg_modf = 0x00U; \
AnnaBridge 165:e614a9f1c9e2 382 tmpreg_modf = (__HANDLE__)->Instance->SR; \
AnnaBridge 165:e614a9f1c9e2 383 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
AnnaBridge 165:e614a9f1c9e2 384 UNUSED(tmpreg_modf); \
AnnaBridge 165:e614a9f1c9e2 385 } while(0U)
<> 144:ef7eb2e8f9f7 386
AnnaBridge 165:e614a9f1c9e2 387 /** @brief Clear the SPI OVR pending flag.
<> 144:ef7eb2e8f9f7 388 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 389 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 390 * @retval None
<> 144:ef7eb2e8f9f7 391 */
AnnaBridge 165:e614a9f1c9e2 392 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
AnnaBridge 165:e614a9f1c9e2 393 do{ \
AnnaBridge 165:e614a9f1c9e2 394 __IO uint32_t tmpreg_ovr = 0x00U; \
AnnaBridge 165:e614a9f1c9e2 395 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
AnnaBridge 165:e614a9f1c9e2 396 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
AnnaBridge 165:e614a9f1c9e2 397 UNUSED(tmpreg_ovr); \
AnnaBridge 165:e614a9f1c9e2 398 } while(0U)
AnnaBridge 165:e614a9f1c9e2 399
<> 144:ef7eb2e8f9f7 400
AnnaBridge 165:e614a9f1c9e2 401 /** @brief Enable the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 402 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 165:e614a9f1c9e2 403 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 404 * @retval None
AnnaBridge 165:e614a9f1c9e2 405 */
AnnaBridge 165:e614a9f1c9e2 406 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
AnnaBridge 165:e614a9f1c9e2 407
AnnaBridge 165:e614a9f1c9e2 408 /** @brief Disable the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 409 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 165:e614a9f1c9e2 410 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 411 * @retval None
AnnaBridge 165:e614a9f1c9e2 412 */
AnnaBridge 165:e614a9f1c9e2 413 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 419 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 420 * @{
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 424 * @{
<> 144:ef7eb2e8f9f7 425 */
AnnaBridge 165:e614a9f1c9e2 426 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 427 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 428 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 429 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 430 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 * @}
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 436 * @{
<> 144:ef7eb2e8f9f7 437 */
AnnaBridge 165:e614a9f1c9e2 438 /* I/O operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 439 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 440 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 441 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 442 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 443 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 444 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 445 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 446 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 447 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
<> 144:ef7eb2e8f9f7 448 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 449 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 450 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 451 /* Transfer Abort functions */
AnnaBridge 165:e614a9f1c9e2 452 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 453 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 456 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 457 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 458 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 459 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 460 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 461 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 462 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 463 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 464 /**
AnnaBridge 165:e614a9f1c9e2 465 * @}
AnnaBridge 165:e614a9f1c9e2 466 */
AnnaBridge 165:e614a9f1c9e2 467
AnnaBridge 165:e614a9f1c9e2 468 /** @addtogroup SPI_Exported_Functions_Group3
AnnaBridge 165:e614a9f1c9e2 469 * @{
AnnaBridge 165:e614a9f1c9e2 470 */
AnnaBridge 165:e614a9f1c9e2 471 /* Peripheral State and Error functions ***************************************/
AnnaBridge 165:e614a9f1c9e2 472 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 473 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 474 /**
AnnaBridge 165:e614a9f1c9e2 475 * @}
AnnaBridge 165:e614a9f1c9e2 476 */
AnnaBridge 165:e614a9f1c9e2 477
<> 144:ef7eb2e8f9f7 478 /**
<> 144:ef7eb2e8f9f7 479 * @}
<> 144:ef7eb2e8f9f7 480 */
<> 144:ef7eb2e8f9f7 481
AnnaBridge 165:e614a9f1c9e2 482 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 483 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 484 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 485 /** @defgroup SPI_Private_Constants SPI Private Constants
AnnaBridge 165:e614a9f1c9e2 486 * @{
AnnaBridge 165:e614a9f1c9e2 487 */
AnnaBridge 165:e614a9f1c9e2 488 #define SPI_INVALID_CRC_ERROR 0U /* CRC error wrongly detected */
AnnaBridge 165:e614a9f1c9e2 489 #define SPI_VALID_CRC_ERROR 1U /* CRC error is true */
AnnaBridge 165:e614a9f1c9e2 490 /**
AnnaBridge 165:e614a9f1c9e2 491 * @}
AnnaBridge 165:e614a9f1c9e2 492 */
AnnaBridge 165:e614a9f1c9e2 493 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 494 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 495 * @{
<> 144:ef7eb2e8f9f7 496 */
AnnaBridge 165:e614a9f1c9e2 497
AnnaBridge 165:e614a9f1c9e2 498 /** @brief Set the SPI transmit-only mode.
AnnaBridge 165:e614a9f1c9e2 499 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 165:e614a9f1c9e2 500 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 501 * @retval None
AnnaBridge 165:e614a9f1c9e2 502 */
AnnaBridge 165:e614a9f1c9e2 503 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
AnnaBridge 165:e614a9f1c9e2 504
AnnaBridge 165:e614a9f1c9e2 505 /** @brief Set the SPI receive-only mode.
AnnaBridge 165:e614a9f1c9e2 506 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 165:e614a9f1c9e2 507 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 508 * @retval None
AnnaBridge 165:e614a9f1c9e2 509 */
AnnaBridge 165:e614a9f1c9e2 510 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
AnnaBridge 165:e614a9f1c9e2 511
AnnaBridge 165:e614a9f1c9e2 512 /** @brief Reset the CRC calculation of the SPI.
AnnaBridge 165:e614a9f1c9e2 513 * @param __HANDLE__: specifies the SPI Handle.
AnnaBridge 165:e614a9f1c9e2 514 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
AnnaBridge 165:e614a9f1c9e2 515 * @retval None
AnnaBridge 165:e614a9f1c9e2 516 */
AnnaBridge 165:e614a9f1c9e2 517 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
AnnaBridge 165:e614a9f1c9e2 518 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0U)
AnnaBridge 165:e614a9f1c9e2 519
AnnaBridge 165:e614a9f1c9e2 520 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
AnnaBridge 165:e614a9f1c9e2 521 ((MODE) == SPI_MODE_MASTER))
AnnaBridge 165:e614a9f1c9e2 522
AnnaBridge 165:e614a9f1c9e2 523 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
AnnaBridge 165:e614a9f1c9e2 524 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
AnnaBridge 165:e614a9f1c9e2 525 ((MODE) == SPI_DIRECTION_1LINE))
AnnaBridge 165:e614a9f1c9e2 526
AnnaBridge 165:e614a9f1c9e2 527 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
AnnaBridge 165:e614a9f1c9e2 528
AnnaBridge 165:e614a9f1c9e2 529 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
AnnaBridge 165:e614a9f1c9e2 530 ((MODE) == SPI_DIRECTION_1LINE))
AnnaBridge 165:e614a9f1c9e2 531
AnnaBridge 165:e614a9f1c9e2 532 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
AnnaBridge 165:e614a9f1c9e2 533 ((DATASIZE) == SPI_DATASIZE_8BIT))
AnnaBridge 165:e614a9f1c9e2 534
AnnaBridge 165:e614a9f1c9e2 535 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
AnnaBridge 165:e614a9f1c9e2 536 ((CPOL) == SPI_POLARITY_HIGH))
AnnaBridge 165:e614a9f1c9e2 537
AnnaBridge 165:e614a9f1c9e2 538 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
AnnaBridge 165:e614a9f1c9e2 539 ((CPHA) == SPI_PHASE_2EDGE))
AnnaBridge 165:e614a9f1c9e2 540
AnnaBridge 165:e614a9f1c9e2 541 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
AnnaBridge 165:e614a9f1c9e2 542 ((NSS) == SPI_NSS_HARD_INPUT) || \
AnnaBridge 165:e614a9f1c9e2 543 ((NSS) == SPI_NSS_HARD_OUTPUT))
AnnaBridge 165:e614a9f1c9e2 544
AnnaBridge 165:e614a9f1c9e2 545 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
AnnaBridge 165:e614a9f1c9e2 546 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
AnnaBridge 165:e614a9f1c9e2 547 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
AnnaBridge 165:e614a9f1c9e2 548 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
AnnaBridge 165:e614a9f1c9e2 549 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
AnnaBridge 165:e614a9f1c9e2 550 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
AnnaBridge 165:e614a9f1c9e2 551 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
AnnaBridge 165:e614a9f1c9e2 552 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
AnnaBridge 165:e614a9f1c9e2 553
AnnaBridge 165:e614a9f1c9e2 554 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
AnnaBridge 165:e614a9f1c9e2 555 ((BIT) == SPI_FIRSTBIT_LSB))
AnnaBridge 165:e614a9f1c9e2 556
AnnaBridge 165:e614a9f1c9e2 557 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
AnnaBridge 165:e614a9f1c9e2 558 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
AnnaBridge 165:e614a9f1c9e2 559
AnnaBridge 165:e614a9f1c9e2 560 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x01U) && ((POLYNOMIAL) <= 0xFFFFU))
AnnaBridge 165:e614a9f1c9e2 561
AnnaBridge 165:e614a9f1c9e2 562 /**
AnnaBridge 165:e614a9f1c9e2 563 * @}
AnnaBridge 165:e614a9f1c9e2 564 */
AnnaBridge 165:e614a9f1c9e2 565
AnnaBridge 165:e614a9f1c9e2 566 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 567 /** @defgroup SPI_Private_Functions SPI Private Functions
AnnaBridge 165:e614a9f1c9e2 568 * @{
AnnaBridge 165:e614a9f1c9e2 569 */
AnnaBridge 165:e614a9f1c9e2 570 uint8_t SPI_ISCRCErrorValid(SPI_HandleTypeDef *hspi);
AnnaBridge 165:e614a9f1c9e2 571 /**
AnnaBridge 165:e614a9f1c9e2 572 * @}
AnnaBridge 165:e614a9f1c9e2 573 */
<> 144:ef7eb2e8f9f7 574
<> 144:ef7eb2e8f9f7 575 /**
<> 144:ef7eb2e8f9f7 576 * @}
<> 144:ef7eb2e8f9f7 577 */
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @}
<> 144:ef7eb2e8f9f7 581 */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585 #endif
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 #endif /* __STM32F1xx_HAL_SPI_H */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/