mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_i2c.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Parent:: 154:37f96f9d4de2
Child:: 167:e84263d55307

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f1xx_hal_i2c.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @version V1.1.0
AnnaBridge	165:e614a9f1c9e2	6	* @date 14-April-2017
<>	144:ef7eb2e8f9f7	7	* @brief I2C HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Inter Integrated Circuit (I2C) peripheral:
<>	144:ef7eb2e8f9f7	10	* + Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	11	* + IO operation functions
<>	154:37f96f9d4de2	12	* + Peripheral State, Mode and Error functions
<>	154:37f96f9d4de2	13	*
<>	144:ef7eb2e8f9f7	14	@verbatim
<>	144:ef7eb2e8f9f7	15	==============================================================================
<>	144:ef7eb2e8f9f7	16	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	17	==============================================================================
<>	144:ef7eb2e8f9f7	18	[..]
<>	144:ef7eb2e8f9f7	19	The I2C HAL driver can be used as follows:
<>	144:ef7eb2e8f9f7	20
<>	144:ef7eb2e8f9f7	21	(#) Declare a I2C_HandleTypeDef handle structure, for example:
<>	144:ef7eb2e8f9f7	22	I2C_HandleTypeDef hi2c;
<>	144:ef7eb2e8f9f7	23
<>	144:ef7eb2e8f9f7	24	(#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
<>	144:ef7eb2e8f9f7	25	(##) Enable the I2Cx interface clock
<>	144:ef7eb2e8f9f7	26	(##) I2C pins configuration
<>	144:ef7eb2e8f9f7	27	(+++) Enable the clock for the I2C GPIOs
<>	144:ef7eb2e8f9f7	28	(+++) Configure I2C pins as alternate function open-drain
<>	144:ef7eb2e8f9f7	29	(##) NVIC configuration if you need to use interrupt process
<>	144:ef7eb2e8f9f7	30	(+++) Configure the I2Cx interrupt priority
<>	144:ef7eb2e8f9f7	31	(+++) Enable the NVIC I2C IRQ Channel
<>	144:ef7eb2e8f9f7	32	(##) DMA Configuration if you need to use DMA process
<>	144:ef7eb2e8f9f7	33	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
<>	144:ef7eb2e8f9f7	34	(+++) Enable the DMAx interface clock using
<>	144:ef7eb2e8f9f7	35	(+++) Configure the DMA handle parameters
<>	144:ef7eb2e8f9f7	36	(+++) Configure the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	37	(+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
<>	144:ef7eb2e8f9f7	38	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
<>	144:ef7eb2e8f9f7	39	the DMA Tx or Rx channel
<>	144:ef7eb2e8f9f7	40
<>	144:ef7eb2e8f9f7	41	(#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
<>	144:ef7eb2e8f9f7	42	Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	(#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
<>	144:ef7eb2e8f9f7	45	(GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	(#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	(#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	* Polling mode IO operation *
<>	144:ef7eb2e8f9f7	52	=================================
<>	144:ef7eb2e8f9f7	53	[..]
<>	144:ef7eb2e8f9f7	54	(+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	55	(+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	56	(+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	57	(+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	58
<>	144:ef7eb2e8f9f7	59	* Polling mode IO MEM operation *
<>	144:ef7eb2e8f9f7	60	=====================================
<>	144:ef7eb2e8f9f7	61	[..]
<>	144:ef7eb2e8f9f7	62	(+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	63	(+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	64
<>	144:ef7eb2e8f9f7	65
<>	144:ef7eb2e8f9f7	66	* Interrupt mode IO operation *
<>	144:ef7eb2e8f9f7	67	===================================
<>	144:ef7eb2e8f9f7	68	[..]
<>	154:37f96f9d4de2	69	(+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
<>	154:37f96f9d4de2	70	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	71	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	154:37f96f9d4de2	72	(+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
<>	154:37f96f9d4de2	73	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	74	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	154:37f96f9d4de2	75	(+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
<>	154:37f96f9d4de2	76	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	77	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	154:37f96f9d4de2	78	(+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
<>	154:37f96f9d4de2	79	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	80	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	154:37f96f9d4de2	81	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	154:37f96f9d4de2	82	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	154:37f96f9d4de2	83	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	154:37f96f9d4de2	84	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	154:37f96f9d4de2	85	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	154:37f96f9d4de2	86
<>	154:37f96f9d4de2	87	* Interrupt mode IO sequential operation *
<>	154:37f96f9d4de2	88	==============================================
<>	154:37f96f9d4de2	89	[..]
<>	154:37f96f9d4de2	90	(@) These interfaces allow to manage a sequential transfer with a repeated start condition
<>	154:37f96f9d4de2	91	when a direction change during transfer
<>	154:37f96f9d4de2	92	[..]
<>	154:37f96f9d4de2	93	(+) A specific option field manage the different steps of a sequential transfer
<>	154:37f96f9d4de2	94	(+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
<>	154:37f96f9d4de2	95	(++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
<>	154:37f96f9d4de2	96	(++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
<>	154:37f96f9d4de2	97	and data to transfer without a final stop condition
<>	154:37f96f9d4de2	98	(++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
<>	154:37f96f9d4de2	99	and with new data to transfer if the direction change or manage only the new data to transfer
<>	154:37f96f9d4de2	100	if no direction change and without a final stop condition in both cases
<>	154:37f96f9d4de2	101	(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
<>	154:37f96f9d4de2	102	and with new data to transfer if the direction change or manage only the new data to transfer
<>	154:37f96f9d4de2	103	if no direction change and with a final stop condition in both cases
<>	154:37f96f9d4de2	104
<>	154:37f96f9d4de2	105	(+) Differents sequential I2C interfaces are listed below:
<>	154:37f96f9d4de2	106	(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
<>	154:37f96f9d4de2	107	(+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	108	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
<>	154:37f96f9d4de2	109	(++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
<>	154:37f96f9d4de2	110	(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	111	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
<>	154:37f96f9d4de2	112	(++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	154:37f96f9d4de2	113	(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	154:37f96f9d4de2	114	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	154:37f96f9d4de2	115	(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
<>	154:37f96f9d4de2	116	(+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
<>	154:37f96f9d4de2	117	add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
<>	154:37f96f9d4de2	118	(+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
<>	154:37f96f9d4de2	119	add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
<>	154:37f96f9d4de2	120	(++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
<>	154:37f96f9d4de2	121	(+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	122	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
<>	154:37f96f9d4de2	123	(++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
<>	154:37f96f9d4de2	124	(+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
<>	144:ef7eb2e8f9f7	125	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
<>	154:37f96f9d4de2	126	(++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	144:ef7eb2e8f9f7	127	add his own code by customization of function pointer HAL_I2C_ErrorCallback()
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	* Interrupt mode IO MEM operation *
<>	144:ef7eb2e8f9f7	130	=======================================
<>	144:ef7eb2e8f9f7	131	[..]
<>	154:37f96f9d4de2	132	(+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
<>	144:ef7eb2e8f9f7	133	HAL_I2C_Mem_Write_IT()
<>	154:37f96f9d4de2	134	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	135	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	154:37f96f9d4de2	136	(+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
<>	144:ef7eb2e8f9f7	137	HAL_I2C_Mem_Read_IT()
<>	154:37f96f9d4de2	138	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	139	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	140	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	154:37f96f9d4de2	141	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143	* DMA mode IO operation *
<>	144:ef7eb2e8f9f7	144	==============================
<>	144:ef7eb2e8f9f7	145	[..]
<>	154:37f96f9d4de2	146	(+) Transmit in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	147	HAL_I2C_Master_Transmit_DMA()
<>	154:37f96f9d4de2	148	(+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	149	add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
<>	154:37f96f9d4de2	150	(+) Receive in master mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	151	HAL_I2C_Master_Receive_DMA()
<>	154:37f96f9d4de2	152	(+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	153	add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
<>	154:37f96f9d4de2	154	(+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	155	HAL_I2C_Slave_Transmit_DMA()
<>	154:37f96f9d4de2	156	(+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	157	add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
<>	154:37f96f9d4de2	158	(+) Receive in slave mode an amount of data in non blocking mode (DMA) using
<>	144:ef7eb2e8f9f7	159	HAL_I2C_Slave_Receive_DMA()
<>	154:37f96f9d4de2	160	(+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	161	add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
<>	144:ef7eb2e8f9f7	162	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	154:37f96f9d4de2	163	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	154:37f96f9d4de2	164	(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
<>	154:37f96f9d4de2	165	(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
<>	154:37f96f9d4de2	166	add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	167
<>	144:ef7eb2e8f9f7	168	* DMA mode IO MEM operation *
<>	144:ef7eb2e8f9f7	169	=================================
<>	144:ef7eb2e8f9f7	170	[..]
<>	154:37f96f9d4de2	171	(+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
<>	144:ef7eb2e8f9f7	172	HAL_I2C_Mem_Write_DMA()
<>	154:37f96f9d4de2	173	(+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
<>	154:37f96f9d4de2	174	add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
<>	154:37f96f9d4de2	175	(+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
<>	144:ef7eb2e8f9f7	176	HAL_I2C_Mem_Read_DMA()
<>	154:37f96f9d4de2	177	(+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
<>	154:37f96f9d4de2	178	add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
<>	144:ef7eb2e8f9f7	179	(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
<>	154:37f96f9d4de2	180	add his own code by customization of function pointer HAL_I2C_ErrorCallback
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182
<>	144:ef7eb2e8f9f7	183	* I2C HAL driver macros list *
<>	144:ef7eb2e8f9f7	184	==================================
<>	144:ef7eb2e8f9f7	185	[..]
<>	144:ef7eb2e8f9f7	186	Below the list of most used macros in I2C HAL driver.
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	(+) __HAL_I2C_ENABLE: Enable the I2C peripheral
<>	144:ef7eb2e8f9f7	189	(+) __HAL_I2C_DISABLE: Disable the I2C peripheral
<>	154:37f96f9d4de2	190	(+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
<>	144:ef7eb2e8f9f7	191	(+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
<>	144:ef7eb2e8f9f7	192	(+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
<>	144:ef7eb2e8f9f7	193	(+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
<>	154:37f96f9d4de2	194
<>	154:37f96f9d4de2	195	[..]
<>	144:ef7eb2e8f9f7	196	(@) You can refer to the I2C HAL driver header file for more useful macros
<>	144:ef7eb2e8f9f7	197
<>	144:ef7eb2e8f9f7	198	* I2C Workarounds linked to Silicon Limitation *
<>	144:ef7eb2e8f9f7	199	====================================================
<>	144:ef7eb2e8f9f7	200	[..]
<>	144:ef7eb2e8f9f7	201	Below the list of all silicon limitations implemented for HAL on STM32F1xx product.
<>	144:ef7eb2e8f9f7	202	(@) See ErrataSheet to know full silicon limitation list of your product.
<>	144:ef7eb2e8f9f7	203
<>	144:ef7eb2e8f9f7	204	(#) Workarounds Implemented inside I2C HAL Driver
<>	144:ef7eb2e8f9f7	205	(##) Wrong data read into data register (Polling and Interrupt mode)
<>	144:ef7eb2e8f9f7	206	(##) Start cannot be generated after a misplaced Stop
<>	144:ef7eb2e8f9f7	207	(##) Some software events must be managed before the current byte is being transferred:
<>	144:ef7eb2e8f9f7	208	Workaround: Use DMA in general, except when the Master is receiving a single byte.
<>	144:ef7eb2e8f9f7	209	For Interupt mode, I2C should have the highest priority in the application.
<>	144:ef7eb2e8f9f7	210	(##) Mismatch on the "Setup time for a repeated Start condition" timing parameter:
<>	144:ef7eb2e8f9f7	211	Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if
<>	144:ef7eb2e8f9f7	212	supported by the slave.
<>	144:ef7eb2e8f9f7	213	(##) Data valid time (tVD;DAT) violated without the OVR flag being set:
<>	144:ef7eb2e8f9f7	214	Workaround: If the slave device allows it, use the clock stretching mechanism
<>	144:ef7eb2e8f9f7	215	by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init.
<>	144:ef7eb2e8f9f7	216
<>	144:ef7eb2e8f9f7	217	@endverbatim
<>	144:ef7eb2e8f9f7	218	******************************************************************************
<>	144:ef7eb2e8f9f7	219	* @attention
<>	144:ef7eb2e8f9f7	220	*
<>	144:ef7eb2e8f9f7	221	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	222	*
<>	144:ef7eb2e8f9f7	223	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	224	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	225	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	226	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	227	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	228	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	229	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	230	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	231	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	232	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	233	*
<>	144:ef7eb2e8f9f7	234	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	235	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	236	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	237	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	238	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	239	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	240	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	241	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	242	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	243	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	244	*
<>	144:ef7eb2e8f9f7	245	******************************************************************************
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	249	#include "stm32f1xx_hal.h"
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/** @addtogroup STM32F1xx_HAL_Driver
<>	144:ef7eb2e8f9f7	252	* @{
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/** @defgroup I2C I2C
<>	144:ef7eb2e8f9f7	256	* @brief I2C HAL module driver
<>	144:ef7eb2e8f9f7	257	* @{
<>	144:ef7eb2e8f9f7	258	*/
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	#ifdef HAL_I2C_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/* Private typedef -----------------------------------------------------------*/
<>	154:37f96f9d4de2	263	/* Private define ------------------------------------------------------------*/
<>	154:37f96f9d4de2	264	/** @addtogroup I2C_Private_Define
<>	144:ef7eb2e8f9f7	265	* @{
<>	154:37f96f9d4de2	266	*/
<>	154:37f96f9d4de2	267	#define I2C_TIMEOUT_FLAG 35U /!< Timeout 35 ms /
<>	154:37f96f9d4de2	268	#define I2C_TIMEOUT_BUSY_FLAG 25U /!< Timeout 25 ms /
<>	154:37f96f9d4de2	269	#define I2C_NO_OPTION_FRAME 0xFFFF0000U /!< XferOptions default value /
<>	154:37f96f9d4de2	270
<>	154:37f96f9d4de2	271	/* Private define for @ref PreviousState usage */
<>	154:37f96f9d4de2	272	#define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX \| HAL_I2C_STATE_BUSY_RX) & (~(uint32_t)HAL_I2C_STATE_READY))) /!< Mask State define, keep only RX and TX bits /
<>	154:37f96f9d4de2	273	#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /!< Default Value /
<>	154:37f96f9d4de2	274	#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy TX, combinaison of State LSB and Mode enum /
<>	154:37f96f9d4de2	275	#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_MASTER)) /!< Master Busy RX, combinaison of State LSB and Mode enum /
<>	154:37f96f9d4de2	276	#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy TX, combinaison of State LSB and Mode enum /
<>	154:37f96f9d4de2	277	#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) \| HAL_I2C_MODE_SLAVE)) /!< Slave Busy RX, combinaison of State LSB and Mode enum /
<>	154:37f96f9d4de2	278
<>	144:ef7eb2e8f9f7	279	/**
<>	144:ef7eb2e8f9f7	280	* @}
<>	154:37f96f9d4de2	281	*/
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	284	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	285	/* Private function prototypes -----------------------------------------------*/
<>	154:37f96f9d4de2	286	/** @addtogroup I2C_Private_Functions
<>	144:ef7eb2e8f9f7	287	* @{
<>	144:ef7eb2e8f9f7	288	*/
<>	154:37f96f9d4de2	289	/* Private functions to handle DMA transfer */
<>	154:37f96f9d4de2	290	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	291	static void I2C_DMAError(DMA_HandleTypeDef *hdma);
<>	154:37f96f9d4de2	292	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
<>	154:37f96f9d4de2	293
<>	154:37f96f9d4de2	294	static void I2C_ITError(I2C_HandleTypeDef *hi2c);
<>	154:37f96f9d4de2	295
<>	154:37f96f9d4de2	296	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	297	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	298	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	299	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	300	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	301	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	302	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	303	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	304	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	154:37f96f9d4de2	305	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
<>	144:ef7eb2e8f9f7	306	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	307
<>	154:37f96f9d4de2	308	/* Private functions for I2C transfer IRQ handler */
<>	144:ef7eb2e8f9f7	309	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	310	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	311	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	312	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	154:37f96f9d4de2	313	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c);
<>	154:37f96f9d4de2	314	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c);
<>	154:37f96f9d4de2	315	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	316
<>	144:ef7eb2e8f9f7	317	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	318	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	319	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	320	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	321	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	322	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	323	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
<>	144:ef7eb2e8f9f7	324	/**
<>	144:ef7eb2e8f9f7	325	* @}
<>	154:37f96f9d4de2	326	*/
<>	154:37f96f9d4de2	327
<>	154:37f96f9d4de2	328	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	329	/** @defgroup I2C_Exported_Functions I2C Exported Functions
<>	144:ef7eb2e8f9f7	330	* @{
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	334	* @brief Initialization and Configuration functions
<>	144:ef7eb2e8f9f7	335	*
<>	144:ef7eb2e8f9f7	336	@verbatim
<>	144:ef7eb2e8f9f7	337	===============================================================================
<>	144:ef7eb2e8f9f7	338	##### Initialization and de-initialization functions #####
<>	144:ef7eb2e8f9f7	339	===============================================================================
<>	144:ef7eb2e8f9f7	340	[..] This subsection provides a set of functions allowing to initialize and
<>	154:37f96f9d4de2	341	de-initialize the I2Cx peripheral:
<>	144:ef7eb2e8f9f7	342
<>	144:ef7eb2e8f9f7	343	(+) User must Implement HAL_I2C_MspInit() function in which he configures
<>	144:ef7eb2e8f9f7	344	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	(+) Call the function HAL_I2C_Init() to configure the selected device with
<>	144:ef7eb2e8f9f7	347	the selected configuration:
<>	144:ef7eb2e8f9f7	348	(++) Communication Speed
<>	144:ef7eb2e8f9f7	349	(++) Duty cycle
<>	144:ef7eb2e8f9f7	350	(++) Addressing mode
<>	144:ef7eb2e8f9f7	351	(++) Own Address 1
<>	144:ef7eb2e8f9f7	352	(++) Dual Addressing mode
<>	144:ef7eb2e8f9f7	353	(++) Own Address 2
<>	144:ef7eb2e8f9f7	354	(++) General call mode
<>	144:ef7eb2e8f9f7	355	(++) Nostretch mode
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	(+) Call the function HAL_I2C_DeInit() to restore the default configuration
<>	154:37f96f9d4de2	358	of the selected I2Cx peripheral.
<>	144:ef7eb2e8f9f7	359
<>	144:ef7eb2e8f9f7	360	@endverbatim
<>	144:ef7eb2e8f9f7	361	* @{
<>	144:ef7eb2e8f9f7	362	*/
<>	144:ef7eb2e8f9f7	363
<>	144:ef7eb2e8f9f7	364	/**
<>	144:ef7eb2e8f9f7	365	* @brief Initializes the I2C according to the specified parameters
<>	154:37f96f9d4de2	366	* in the I2C_InitTypeDef and create the associated handle.
<>	154:37f96f9d4de2	367	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	368	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	369	* @retval HAL status
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371	HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	372	{
<>	154:37f96f9d4de2	373	uint32_t freqrange = 0U;
<>	154:37f96f9d4de2	374	uint32_t pclk1 = 0U;
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	377	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	378	{
<>	144:ef7eb2e8f9f7	379	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	380	}
<>	144:ef7eb2e8f9f7	381
<>	144:ef7eb2e8f9f7	382	/* Check the parameters */
<>	144:ef7eb2e8f9f7	383	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	384	assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
<>	144:ef7eb2e8f9f7	385	assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
<>	144:ef7eb2e8f9f7	386	assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
<>	144:ef7eb2e8f9f7	387	assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
<>	144:ef7eb2e8f9f7	388	assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
<>	144:ef7eb2e8f9f7	389	assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
<>	144:ef7eb2e8f9f7	390	assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
<>	144:ef7eb2e8f9f7	391	assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
<>	144:ef7eb2e8f9f7	392
<>	144:ef7eb2e8f9f7	393	if(hi2c->State == HAL_I2C_STATE_RESET)
<>	144:ef7eb2e8f9f7	394	{
<>	144:ef7eb2e8f9f7	395	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	396	hi2c->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	397	/* Init the low level hardware : GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	398	HAL_I2C_MspInit(hi2c);
<>	144:ef7eb2e8f9f7	399	}
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	402
<>	144:ef7eb2e8f9f7	403	/* Disable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	404	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	405
<>	144:ef7eb2e8f9f7	406	/* Get PCLK1 frequency */
<>	144:ef7eb2e8f9f7	407	pclk1 = HAL_RCC_GetPCLK1Freq();
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/* Calculate frequency range */
<>	154:37f96f9d4de2	410	freqrange = I2C_FREQRANGE(pclk1);
<>	144:ef7eb2e8f9f7	411
<>	144:ef7eb2e8f9f7	412	/---------------------------- I2Cx CR2 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	413	/* Configure I2Cx: Frequency range */
<>	144:ef7eb2e8f9f7	414	hi2c->Instance->CR2 = freqrange;
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/---------------------------- I2Cx TRISE Configuration --------------------/
<>	144:ef7eb2e8f9f7	417	/* Configure I2Cx: Rise Time */
<>	144:ef7eb2e8f9f7	418	hi2c->Instance->TRISE = I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed);
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420	/---------------------------- I2Cx CCR Configuration ----------------------/
<>	144:ef7eb2e8f9f7	421	/* Configure I2Cx: Speed */
<>	154:37f96f9d4de2	422	hi2c->Instance->CCR = I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle);
<>	144:ef7eb2e8f9f7	423
<>	144:ef7eb2e8f9f7	424	/---------------------------- I2Cx CR1 Configuration ----------------------/
<>	144:ef7eb2e8f9f7	425	/* Configure I2Cx: Generalcall and NoStretch mode */
<>	144:ef7eb2e8f9f7	426	hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode \| hi2c->Init.NoStretchMode);
<>	144:ef7eb2e8f9f7	427
<>	144:ef7eb2e8f9f7	428	/---------------------------- I2Cx OAR1 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	429	/* Configure I2Cx: Own Address1 and addressing mode */
<>	144:ef7eb2e8f9f7	430	hi2c->Instance->OAR1 = (hi2c->Init.AddressingMode \| hi2c->Init.OwnAddress1);
<>	144:ef7eb2e8f9f7	431
<>	144:ef7eb2e8f9f7	432	/---------------------------- I2Cx OAR2 Configuration ---------------------/
<>	144:ef7eb2e8f9f7	433	/* Configure I2Cx: Dual mode and Own Address2 */
<>	144:ef7eb2e8f9f7	434	hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode \| hi2c->Init.OwnAddress2);
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	/* Enable the selected I2C peripheral */
<>	144:ef7eb2e8f9f7	437	__HAL_I2C_ENABLE(hi2c);
<>	144:ef7eb2e8f9f7	438
<>	144:ef7eb2e8f9f7	439	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	440	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	441	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	442	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	return HAL_OK;
<>	144:ef7eb2e8f9f7	445	}
<>	144:ef7eb2e8f9f7	446
<>	144:ef7eb2e8f9f7	447	/**
<>	154:37f96f9d4de2	448	* @brief DeInitializes the I2C peripheral.
<>	154:37f96f9d4de2	449	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	450	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	451	* @retval HAL status
<>	144:ef7eb2e8f9f7	452	*/
<>	144:ef7eb2e8f9f7	453	HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	454	{
<>	144:ef7eb2e8f9f7	455	/* Check the I2C handle allocation */
<>	144:ef7eb2e8f9f7	456	if(hi2c == NULL)
<>	144:ef7eb2e8f9f7	457	{
<>	144:ef7eb2e8f9f7	458	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	459	}
<>	144:ef7eb2e8f9f7	460
<>	144:ef7eb2e8f9f7	461	/* Check the parameters */
<>	144:ef7eb2e8f9f7	462	assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/* Disable the I2C Peripheral Clock */
<>	144:ef7eb2e8f9f7	467	__HAL_I2C_DISABLE(hi2c);
<>	144:ef7eb2e8f9f7	468
<>	144:ef7eb2e8f9f7	469	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	470	HAL_I2C_MspDeInit(hi2c);
<>	144:ef7eb2e8f9f7	471
<>	154:37f96f9d4de2	472	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	473	hi2c->State = HAL_I2C_STATE_RESET;
<>	154:37f96f9d4de2	474	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	475	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/* Release Lock */
<>	144:ef7eb2e8f9f7	478	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	return HAL_OK;
<>	144:ef7eb2e8f9f7	481	}
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/**
<>	154:37f96f9d4de2	484	* @brief I2C MSP Init.
<>	154:37f96f9d4de2	485	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	486	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	487	* @retval None
<>	144:ef7eb2e8f9f7	488	*/
<>	144:ef7eb2e8f9f7	489	__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	490	{
<>	144:ef7eb2e8f9f7	491	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	492	UNUSED(hi2c);
<>	154:37f96f9d4de2	493	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	494	the HAL_I2C_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	495	*/
<>	144:ef7eb2e8f9f7	496	}
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/**
<>	154:37f96f9d4de2	499	* @brief I2C MSP DeInit
<>	154:37f96f9d4de2	500	* @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	501	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	502	* @retval None
<>	144:ef7eb2e8f9f7	503	*/
<>	144:ef7eb2e8f9f7	504	__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	505	{
<>	144:ef7eb2e8f9f7	506	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	507	UNUSED(hi2c);
<>	154:37f96f9d4de2	508	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	509	the HAL_I2C_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	510	*/
<>	144:ef7eb2e8f9f7	511	}
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/**
<>	144:ef7eb2e8f9f7	514	* @}
<>	144:ef7eb2e8f9f7	515	*/
<>	144:ef7eb2e8f9f7	516
<>	154:37f96f9d4de2	517	/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	518	* @brief Data transfers functions
<>	144:ef7eb2e8f9f7	519	*
<>	144:ef7eb2e8f9f7	520	@verbatim
<>	144:ef7eb2e8f9f7	521	===============================================================================
<>	144:ef7eb2e8f9f7	522	##### IO operation functions #####
<>	144:ef7eb2e8f9f7	523	===============================================================================
<>	144:ef7eb2e8f9f7	524	[..]
<>	144:ef7eb2e8f9f7	525	This subsection provides a set of functions allowing to manage the I2C data
<>	144:ef7eb2e8f9f7	526	transfers.
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	(#) There are two modes of transfer:
<>	144:ef7eb2e8f9f7	529	(++) Blocking mode : The communication is performed in the polling mode.
<>	144:ef7eb2e8f9f7	530	The status of all data processing is returned by the same function
<>	144:ef7eb2e8f9f7	531	after finishing transfer.
<>	154:37f96f9d4de2	532	(++) No-Blocking mode : The communication is performed using Interrupts
<>	144:ef7eb2e8f9f7	533	or DMA. These functions return the status of the transfer startup.
<>	144:ef7eb2e8f9f7	534	The end of the data processing will be indicated through the
<>	144:ef7eb2e8f9f7	535	dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
<>	144:ef7eb2e8f9f7	536	using DMA mode.
<>	144:ef7eb2e8f9f7	537
<>	144:ef7eb2e8f9f7	538	(#) Blocking mode functions are :
<>	144:ef7eb2e8f9f7	539	(++) HAL_I2C_Master_Transmit()
<>	144:ef7eb2e8f9f7	540	(++) HAL_I2C_Master_Receive()
<>	144:ef7eb2e8f9f7	541	(++) HAL_I2C_Slave_Transmit()
<>	144:ef7eb2e8f9f7	542	(++) HAL_I2C_Slave_Receive()
<>	144:ef7eb2e8f9f7	543	(++) HAL_I2C_Mem_Write()
<>	144:ef7eb2e8f9f7	544	(++) HAL_I2C_Mem_Read()
<>	144:ef7eb2e8f9f7	545	(++) HAL_I2C_IsDeviceReady()
<>	144:ef7eb2e8f9f7	546
<>	144:ef7eb2e8f9f7	547	(#) No-Blocking mode functions with Interrupt are :
<>	144:ef7eb2e8f9f7	548	(++) HAL_I2C_Master_Transmit_IT()
<>	144:ef7eb2e8f9f7	549	(++) HAL_I2C_Master_Receive_IT()
<>	144:ef7eb2e8f9f7	550	(++) HAL_I2C_Slave_Transmit_IT()
<>	144:ef7eb2e8f9f7	551	(++) HAL_I2C_Slave_Receive_IT()
<>	154:37f96f9d4de2	552	(++) HAL_I2C_Master_Sequential_Transmit_IT()
<>	154:37f96f9d4de2	553	(++) HAL_I2C_Master_Sequential_Receive_IT()
<>	154:37f96f9d4de2	554	(++) HAL_I2C_Slave_Sequential_Transmit_IT()
<>	154:37f96f9d4de2	555	(++) HAL_I2C_Slave_Sequential_Receive_IT()
<>	144:ef7eb2e8f9f7	556	(++) HAL_I2C_Mem_Write_IT()
<>	144:ef7eb2e8f9f7	557	(++) HAL_I2C_Mem_Read_IT()
<>	144:ef7eb2e8f9f7	558
<>	144:ef7eb2e8f9f7	559	(#) No-Blocking mode functions with DMA are :
<>	144:ef7eb2e8f9f7	560	(++) HAL_I2C_Master_Transmit_DMA()
<>	144:ef7eb2e8f9f7	561	(++) HAL_I2C_Master_Receive_DMA()
<>	144:ef7eb2e8f9f7	562	(++) HAL_I2C_Slave_Transmit_DMA()
<>	144:ef7eb2e8f9f7	563	(++) HAL_I2C_Slave_Receive_DMA()
<>	144:ef7eb2e8f9f7	564	(++) HAL_I2C_Mem_Write_DMA()
<>	144:ef7eb2e8f9f7	565	(++) HAL_I2C_Mem_Read_DMA()
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
<>	144:ef7eb2e8f9f7	568	(++) HAL_I2C_MemTxCpltCallback()
<>	144:ef7eb2e8f9f7	569	(++) HAL_I2C_MemRxCpltCallback()
<>	144:ef7eb2e8f9f7	570	(++) HAL_I2C_MasterTxCpltCallback()
<>	144:ef7eb2e8f9f7	571	(++) HAL_I2C_MasterRxCpltCallback()
<>	144:ef7eb2e8f9f7	572	(++) HAL_I2C_SlaveTxCpltCallback()
<>	144:ef7eb2e8f9f7	573	(++) HAL_I2C_SlaveRxCpltCallback()
<>	144:ef7eb2e8f9f7	574	(++) HAL_I2C_ErrorCallback()
<>	154:37f96f9d4de2	575	(++) HAL_I2C_AbortCpltCallback()
<>	144:ef7eb2e8f9f7	576
<>	144:ef7eb2e8f9f7	577	@endverbatim
<>	144:ef7eb2e8f9f7	578	* @{
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/**
<>	144:ef7eb2e8f9f7	582	* @brief Transmits in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	583	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	584	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	585	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	586	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	587	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	588	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	589	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	590	* @retval HAL status
<>	144:ef7eb2e8f9f7	591	*/
<>	144:ef7eb2e8f9f7	592	HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	593	{
<>	154:37f96f9d4de2	594	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	595
<>	154:37f96f9d4de2	596	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	597	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	598
<>	144:ef7eb2e8f9f7	599	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	600	{
<>	144:ef7eb2e8f9f7	601	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	602	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	603	{
<>	144:ef7eb2e8f9f7	604	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	605	}
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	/* Process Locked */
<>	144:ef7eb2e8f9f7	608	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	609
<>	154:37f96f9d4de2	610	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	611	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	612	{
<>	154:37f96f9d4de2	613	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	614	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	615	}
<>	154:37f96f9d4de2	616
<>	144:ef7eb2e8f9f7	617	/* Disable Pos */
<>	154:37f96f9d4de2	618	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	619
<>	154:37f96f9d4de2	620	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	621	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	622	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	623
<>	154:37f96f9d4de2	624	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	625	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	626	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	627	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	628	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	629
<>	144:ef7eb2e8f9f7	630	/* Send Slave Address */
<>	154:37f96f9d4de2	631	if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	632	{
<>	144:ef7eb2e8f9f7	633	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	634	{
<>	144:ef7eb2e8f9f7	635	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	636	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	637	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	638	}
<>	144:ef7eb2e8f9f7	639	else
<>	144:ef7eb2e8f9f7	640	{
<>	144:ef7eb2e8f9f7	641	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	642	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	643	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	644	}
<>	144:ef7eb2e8f9f7	645	}
<>	144:ef7eb2e8f9f7	646
<>	144:ef7eb2e8f9f7	647	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	648	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	649
<>	154:37f96f9d4de2	650	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	651	{
<>	144:ef7eb2e8f9f7	652	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	653	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	656	{
<>	144:ef7eb2e8f9f7	657	/* Generate Stop */
<>	154:37f96f9d4de2	658	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	659	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	660	}
<>	144:ef7eb2e8f9f7	661	else
<>	144:ef7eb2e8f9f7	662	{
<>	144:ef7eb2e8f9f7	663	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	664	}
<>	144:ef7eb2e8f9f7	665	}
<>	144:ef7eb2e8f9f7	666
<>	144:ef7eb2e8f9f7	667	/* Write data to DR */
<>	154:37f96f9d4de2	668	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	669	hi2c->XferCount--;
<>	154:37f96f9d4de2	670	hi2c->XferSize--;
<>	154:37f96f9d4de2	671
AnnaBridge	165:e614a9f1c9e2	672	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	673	{
<>	144:ef7eb2e8f9f7	674	/* Write data to DR */
<>	154:37f96f9d4de2	675	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	676	hi2c->XferCount--;
<>	154:37f96f9d4de2	677	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	678	}
<>	154:37f96f9d4de2	679
<>	154:37f96f9d4de2	680	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	681	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	682	{
<>	154:37f96f9d4de2	683	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	154:37f96f9d4de2	684	{
<>	154:37f96f9d4de2	685	/* Generate Stop */
<>	154:37f96f9d4de2	686	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	687	return HAL_ERROR;
<>	154:37f96f9d4de2	688	}
<>	154:37f96f9d4de2	689	else
<>	154:37f96f9d4de2	690	{
<>	154:37f96f9d4de2	691	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	692	}
<>	144:ef7eb2e8f9f7	693	}
<>	144:ef7eb2e8f9f7	694	}
<>	144:ef7eb2e8f9f7	695
<>	144:ef7eb2e8f9f7	696	/* Generate Stop */
<>	154:37f96f9d4de2	697	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	700	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	701
<>	144:ef7eb2e8f9f7	702	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	703	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	704
<>	144:ef7eb2e8f9f7	705	return HAL_OK;
<>	144:ef7eb2e8f9f7	706	}
<>	144:ef7eb2e8f9f7	707	else
<>	144:ef7eb2e8f9f7	708	{
<>	144:ef7eb2e8f9f7	709	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	710	}
<>	144:ef7eb2e8f9f7	711	}
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/**
<>	144:ef7eb2e8f9f7	714	* @brief Receives in master mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	715	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	716	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	717	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	718	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	719	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	720	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	721	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	722	* @retval HAL status
<>	144:ef7eb2e8f9f7	723	*/
<>	144:ef7eb2e8f9f7	724	HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	725	{
<>	154:37f96f9d4de2	726	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	727
<>	154:37f96f9d4de2	728	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	729	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	730
<>	144:ef7eb2e8f9f7	731	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	732	{
<>	144:ef7eb2e8f9f7	733	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	734	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	735	{
<>	144:ef7eb2e8f9f7	736	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	737	}
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	/* Process Locked */
<>	144:ef7eb2e8f9f7	740	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	741
<>	154:37f96f9d4de2	742	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	743	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	744	{
<>	154:37f96f9d4de2	745	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	746	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	747	}
<>	154:37f96f9d4de2	748
<>	144:ef7eb2e8f9f7	749	/* Disable Pos */
<>	154:37f96f9d4de2	750	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	751
<>	154:37f96f9d4de2	752	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	753	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	154:37f96f9d4de2	754	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	755
<>	154:37f96f9d4de2	756	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	757	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	758	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	759	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	760	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	/* Send Slave Address */
<>	154:37f96f9d4de2	763	if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	764	{
<>	144:ef7eb2e8f9f7	765	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	766	{
<>	144:ef7eb2e8f9f7	767	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	768	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	769	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	770	}
<>	144:ef7eb2e8f9f7	771	else
<>	144:ef7eb2e8f9f7	772	{
<>	144:ef7eb2e8f9f7	773	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	774	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	775	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	776	}
<>	144:ef7eb2e8f9f7	777	}
<>	144:ef7eb2e8f9f7	778
<>	154:37f96f9d4de2	779	if(hi2c->XferSize == 0U)
<>	154:37f96f9d4de2	780	{
<>	154:37f96f9d4de2	781	/* Clear ADDR flag */
<>	154:37f96f9d4de2	782	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	783
<>	154:37f96f9d4de2	784	/* Generate Stop */
<>	154:37f96f9d4de2	785	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	786	}
<>	154:37f96f9d4de2	787	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	788	{
<>	144:ef7eb2e8f9f7	789	/* Disable Acknowledge */
<>	154:37f96f9d4de2	790	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	791
<>	144:ef7eb2e8f9f7	792	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	154:37f96f9d4de2	793	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	794	__disable_irq();
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	797	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Generate Stop */
<>	154:37f96f9d4de2	800	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	801
<>	144:ef7eb2e8f9f7	802	/* Re-enable IRQs */
<>	144:ef7eb2e8f9f7	803	__enable_irq();
<>	144:ef7eb2e8f9f7	804	}
<>	154:37f96f9d4de2	805	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	806	{
<>	144:ef7eb2e8f9f7	807	/* Enable Pos */
<>	154:37f96f9d4de2	808	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	809
<>	144:ef7eb2e8f9f7	810	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	154:37f96f9d4de2	811	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	812	__disable_irq();
<>	144:ef7eb2e8f9f7	813
<>	144:ef7eb2e8f9f7	814	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	815	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	/* Disable Acknowledge */
<>	154:37f96f9d4de2	818	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	819
<>	154:37f96f9d4de2	820	/* Re-enable IRQs */
<>	154:37f96f9d4de2	821	__enable_irq();
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823	else
<>	144:ef7eb2e8f9f7	824	{
<>	144:ef7eb2e8f9f7	825	/* Enable Acknowledge */
<>	154:37f96f9d4de2	826	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	827
<>	144:ef7eb2e8f9f7	828	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	829	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	830	}
<>	144:ef7eb2e8f9f7	831
<>	154:37f96f9d4de2	832	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	833	{
<>	154:37f96f9d4de2	834	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	835	{
<>	144:ef7eb2e8f9f7	836	/* One byte */
<>	154:37f96f9d4de2	837	if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	838	{
<>	144:ef7eb2e8f9f7	839	/* Wait until RXNE flag is set */
<>	154:37f96f9d4de2	840	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	841	{
<>	144:ef7eb2e8f9f7	842	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	843	{
<>	144:ef7eb2e8f9f7	844	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	845	}
<>	144:ef7eb2e8f9f7	846	else
<>	144:ef7eb2e8f9f7	847	{
<>	144:ef7eb2e8f9f7	848	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	849	}
<>	144:ef7eb2e8f9f7	850	}
<>	144:ef7eb2e8f9f7	851
<>	144:ef7eb2e8f9f7	852	/* Read data from DR */
<>	154:37f96f9d4de2	853	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	854	hi2c->XferSize--;
<>	154:37f96f9d4de2	855	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	856	}
<>	144:ef7eb2e8f9f7	857	/* Two bytes */
<>	154:37f96f9d4de2	858	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	859	{
<>	144:ef7eb2e8f9f7	860	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	861	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	862	{
<>	144:ef7eb2e8f9f7	863	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	864	}
<>	144:ef7eb2e8f9f7	865
<>	144:ef7eb2e8f9f7	866	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	867	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	868	__disable_irq();
<>	144:ef7eb2e8f9f7	869
<>	144:ef7eb2e8f9f7	870	/* Generate Stop */
<>	154:37f96f9d4de2	871	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	/* Read data from DR */
<>	154:37f96f9d4de2	874	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	875	hi2c->XferSize--;
<>	154:37f96f9d4de2	876	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Re-enable IRQs */
<>	144:ef7eb2e8f9f7	879	__enable_irq();
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Read data from DR */
<>	154:37f96f9d4de2	882	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	883	hi2c->XferSize--;
<>	154:37f96f9d4de2	884	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	885	}
<>	144:ef7eb2e8f9f7	886	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	887	else
<>	144:ef7eb2e8f9f7	888	{
<>	144:ef7eb2e8f9f7	889	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	890	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	891	{
<>	144:ef7eb2e8f9f7	892	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	893	}
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/* Disable Acknowledge */
<>	154:37f96f9d4de2	896	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	897
<>	144:ef7eb2e8f9f7	898	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	899	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	900	__disable_irq();
<>	144:ef7eb2e8f9f7	901
<>	144:ef7eb2e8f9f7	902	/* Read data from DR */
<>	154:37f96f9d4de2	903	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	904	hi2c->XferSize--;
<>	154:37f96f9d4de2	905	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	906
<>	144:ef7eb2e8f9f7	907	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	908	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	909	{
<>	144:ef7eb2e8f9f7	910	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	911	}
<>	144:ef7eb2e8f9f7	912
<>	144:ef7eb2e8f9f7	913	/* Generate Stop */
<>	154:37f96f9d4de2	914	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916	/* Read data from DR */
<>	154:37f96f9d4de2	917	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	918	hi2c->XferSize--;
<>	154:37f96f9d4de2	919	hi2c->XferCount--;
<>	154:37f96f9d4de2	920
<>	144:ef7eb2e8f9f7	921	/* Re-enable IRQs */
<>	144:ef7eb2e8f9f7	922	__enable_irq();
<>	144:ef7eb2e8f9f7	923
<>	144:ef7eb2e8f9f7	924	/* Read data from DR */
<>	154:37f96f9d4de2	925	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	926	hi2c->XferSize--;
<>	154:37f96f9d4de2	927	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	928	}
<>	144:ef7eb2e8f9f7	929	}
<>	144:ef7eb2e8f9f7	930	else
<>	144:ef7eb2e8f9f7	931	{
<>	144:ef7eb2e8f9f7	932	/* Wait until RXNE flag is set */
<>	154:37f96f9d4de2	933	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	934	{
<>	144:ef7eb2e8f9f7	935	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	936	{
<>	144:ef7eb2e8f9f7	937	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	938	}
<>	144:ef7eb2e8f9f7	939	else
<>	144:ef7eb2e8f9f7	940	{
<>	144:ef7eb2e8f9f7	941	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	942	}
<>	144:ef7eb2e8f9f7	943	}
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/* Read data from DR */
<>	154:37f96f9d4de2	946	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	947	hi2c->XferSize--;
<>	154:37f96f9d4de2	948	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	951	{
<>	144:ef7eb2e8f9f7	952	/* Read data from DR */
<>	154:37f96f9d4de2	953	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	954	hi2c->XferSize--;
<>	154:37f96f9d4de2	955	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	956	}
<>	144:ef7eb2e8f9f7	957	}
<>	144:ef7eb2e8f9f7	958	}
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	961	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	962
<>	144:ef7eb2e8f9f7	963	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	964	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	965
<>	144:ef7eb2e8f9f7	966	return HAL_OK;
<>	144:ef7eb2e8f9f7	967	}
<>	144:ef7eb2e8f9f7	968	else
<>	144:ef7eb2e8f9f7	969	{
<>	144:ef7eb2e8f9f7	970	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	971	}
<>	144:ef7eb2e8f9f7	972	}
<>	144:ef7eb2e8f9f7	973
<>	144:ef7eb2e8f9f7	974	/**
<>	144:ef7eb2e8f9f7	975	* @brief Transmits in slave mode an amount of data in blocking mode.
<>	144:ef7eb2e8f9f7	976	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	977	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	978	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	979	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	980	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	981	* @retval HAL status
<>	144:ef7eb2e8f9f7	982	*/
<>	144:ef7eb2e8f9f7	983	HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	984	{
<>	154:37f96f9d4de2	985	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	986
<>	154:37f96f9d4de2	987	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	988	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	989
<>	144:ef7eb2e8f9f7	990	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	991	{
<>	154:37f96f9d4de2	992	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	993	{
<>	144:ef7eb2e8f9f7	994	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	995	}
<>	144:ef7eb2e8f9f7	996
<>	144:ef7eb2e8f9f7	997	/* Process Locked */
<>	144:ef7eb2e8f9f7	998	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	999
<>	154:37f96f9d4de2	1000	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1001	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1002	{
<>	154:37f96f9d4de2	1003	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1004	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1005	}
<>	144:ef7eb2e8f9f7	1006
<>	144:ef7eb2e8f9f7	1007	/* Disable Pos */
<>	154:37f96f9d4de2	1008	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1009
<>	154:37f96f9d4de2	1010	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	1011	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	1012	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1013
<>	154:37f96f9d4de2	1014	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1015	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1016	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1017	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1018	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1019
<>	144:ef7eb2e8f9f7	1020	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	1021	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	1024	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1025	{
<>	144:ef7eb2e8f9f7	1026	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028
<>	144:ef7eb2e8f9f7	1029	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1030	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	/* If 10bit addressing mode is selected */
<>	144:ef7eb2e8f9f7	1033	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
<>	144:ef7eb2e8f9f7	1034	{
<>	144:ef7eb2e8f9f7	1035	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	1036	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1037	{
<>	144:ef7eb2e8f9f7	1038	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1039	}
<>	144:ef7eb2e8f9f7	1040
<>	144:ef7eb2e8f9f7	1041	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1042	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1043	}
<>	144:ef7eb2e8f9f7	1044
<>	154:37f96f9d4de2	1045	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1046	{
<>	144:ef7eb2e8f9f7	1047	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	1048	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1049	{
<>	144:ef7eb2e8f9f7	1050	/* Disable Address Acknowledge */
<>	154:37f96f9d4de2	1051	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	1052
<>	144:ef7eb2e8f9f7	1053	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1054	{
<>	144:ef7eb2e8f9f7	1055	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1056	}
<>	144:ef7eb2e8f9f7	1057	else
<>	144:ef7eb2e8f9f7	1058	{
<>	144:ef7eb2e8f9f7	1059	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1060	}
<>	144:ef7eb2e8f9f7	1061	}
<>	144:ef7eb2e8f9f7	1062
<>	144:ef7eb2e8f9f7	1063	/* Write data to DR */
<>	154:37f96f9d4de2	1064	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	1065	hi2c->XferCount--;
<>	154:37f96f9d4de2	1066	hi2c->XferSize--;
<>	154:37f96f9d4de2	1067
AnnaBridge	165:e614a9f1c9e2	1068	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	1069	{
<>	144:ef7eb2e8f9f7	1070	/* Write data to DR */
<>	154:37f96f9d4de2	1071	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	1072	hi2c->XferCount--;
<>	154:37f96f9d4de2	1073	hi2c->XferSize--;
<>	144:ef7eb2e8f9f7	1074	}
<>	144:ef7eb2e8f9f7	1075	}
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	/* Wait until AF flag is set */
<>	154:37f96f9d4de2	1078	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1079	{
<>	144:ef7eb2e8f9f7	1080	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1081	}
<>	144:ef7eb2e8f9f7	1082
<>	144:ef7eb2e8f9f7	1083	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	1084	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/* Disable Address Acknowledge */
<>	154:37f96f9d4de2	1087	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1088
<>	144:ef7eb2e8f9f7	1089	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1090	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1093	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1094
<>	144:ef7eb2e8f9f7	1095	return HAL_OK;
<>	144:ef7eb2e8f9f7	1096	}
<>	144:ef7eb2e8f9f7	1097	else
<>	144:ef7eb2e8f9f7	1098	{
<>	144:ef7eb2e8f9f7	1099	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1100	}
<>	144:ef7eb2e8f9f7	1101	}
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/**
<>	144:ef7eb2e8f9f7	1104	* @brief Receive in slave mode an amount of data in blocking mode
<>	144:ef7eb2e8f9f7	1105	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1106	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1107	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1108	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1109	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	1110	* @retval HAL status
<>	144:ef7eb2e8f9f7	1111	*/
<>	144:ef7eb2e8f9f7	1112	HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	1113	{
<>	154:37f96f9d4de2	1114	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	1115
<>	154:37f96f9d4de2	1116	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	1117	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	1118
<>	144:ef7eb2e8f9f7	1119	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1120	{
<>	154:37f96f9d4de2	1121	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1122	{
<>	144:ef7eb2e8f9f7	1123	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1124	}
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/* Process Locked */
<>	144:ef7eb2e8f9f7	1127	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1128
<>	154:37f96f9d4de2	1129	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1130	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1131	{
<>	154:37f96f9d4de2	1132	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1133	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1134	}
<>	154:37f96f9d4de2	1135
<>	144:ef7eb2e8f9f7	1136	/* Disable Pos */
<>	154:37f96f9d4de2	1137	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1138
<>	154:37f96f9d4de2	1139	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	1140	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	1141	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1142
<>	154:37f96f9d4de2	1143	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1144	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1145	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1146	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1147	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1148
<>	144:ef7eb2e8f9f7	1149	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	1150	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1151
<>	144:ef7eb2e8f9f7	1152	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	1153	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1154	{
<>	144:ef7eb2e8f9f7	1155	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1156	}
<>	144:ef7eb2e8f9f7	1157
<>	144:ef7eb2e8f9f7	1158	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	1159	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1160
<>	154:37f96f9d4de2	1161	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	1162	{
<>	144:ef7eb2e8f9f7	1163	/* Wait until RXNE flag is set */
<>	154:37f96f9d4de2	1164	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1165	{
<>	144:ef7eb2e8f9f7	1166	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1167	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	1168
<>	144:ef7eb2e8f9f7	1169	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	1170	{
<>	144:ef7eb2e8f9f7	1171	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1172	}
<>	144:ef7eb2e8f9f7	1173	else
<>	144:ef7eb2e8f9f7	1174	{
<>	144:ef7eb2e8f9f7	1175	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1176	}
<>	144:ef7eb2e8f9f7	1177	}
<>	144:ef7eb2e8f9f7	1178
<>	144:ef7eb2e8f9f7	1179	/* Read data from DR */
<>	154:37f96f9d4de2	1180	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	1181	hi2c->XferSize--;
<>	154:37f96f9d4de2	1182	hi2c->XferCount--;
<>	154:37f96f9d4de2	1183
<>	154:37f96f9d4de2	1184	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0U))
<>	144:ef7eb2e8f9f7	1185	{
<>	144:ef7eb2e8f9f7	1186	/* Read data from DR */
<>	154:37f96f9d4de2	1187	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	1188	hi2c->XferSize--;
<>	154:37f96f9d4de2	1189	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	1190	}
<>	144:ef7eb2e8f9f7	1191	}
<>	144:ef7eb2e8f9f7	1192
<>	144:ef7eb2e8f9f7	1193	/* Wait until STOP flag is set */
<>	154:37f96f9d4de2	1194	if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	1195	{
<>	144:ef7eb2e8f9f7	1196	/* Disable Address Acknowledge */
<>	144:ef7eb2e8f9f7	1197	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	1200	{
<>	144:ef7eb2e8f9f7	1201	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1202	}
<>	144:ef7eb2e8f9f7	1203	else
<>	144:ef7eb2e8f9f7	1204	{
<>	144:ef7eb2e8f9f7	1205	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	1206	}
<>	144:ef7eb2e8f9f7	1207	}
<>	144:ef7eb2e8f9f7	1208
<>	144:ef7eb2e8f9f7	1209	/* Clear STOP flag */
<>	144:ef7eb2e8f9f7	1210	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/* Disable Address Acknowledge */
<>	154:37f96f9d4de2	1213	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	1216	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1219	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1220
<>	144:ef7eb2e8f9f7	1221	return HAL_OK;
<>	144:ef7eb2e8f9f7	1222	}
<>	144:ef7eb2e8f9f7	1223	else
<>	144:ef7eb2e8f9f7	1224	{
<>	144:ef7eb2e8f9f7	1225	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1226	}
<>	144:ef7eb2e8f9f7	1227	}
<>	144:ef7eb2e8f9f7	1228
<>	144:ef7eb2e8f9f7	1229	/**
<>	144:ef7eb2e8f9f7	1230	* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1231	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1232	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1233	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	1234	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1235	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1236	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1237	* @retval HAL status
<>	144:ef7eb2e8f9f7	1238	*/
<>	144:ef7eb2e8f9f7	1239	HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1240	{
<>	154:37f96f9d4de2	1241	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1242
<>	144:ef7eb2e8f9f7	1243	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1244	{
<>	154:37f96f9d4de2	1245	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1246	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1247	do
<>	144:ef7eb2e8f9f7	1248	{
<>	154:37f96f9d4de2	1249	if(count-- == 0U)
<>	154:37f96f9d4de2	1250	{
<>	154:37f96f9d4de2	1251	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1252	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1253
<>	154:37f96f9d4de2	1254	/* Process Unlocked */
<>	154:37f96f9d4de2	1255	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1256
<>	154:37f96f9d4de2	1257	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1258	}
<>	144:ef7eb2e8f9f7	1259	}
<>	154:37f96f9d4de2	1260	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1261
<>	144:ef7eb2e8f9f7	1262	/* Process Locked */
<>	144:ef7eb2e8f9f7	1263	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1264
<>	154:37f96f9d4de2	1265	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1266	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1267	{
<>	154:37f96f9d4de2	1268	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1269	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1270	}
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	/* Disable Pos */
<>	154:37f96f9d4de2	1273	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1274
<>	154:37f96f9d4de2	1275	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	1276	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1277	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1278
<>	154:37f96f9d4de2	1279	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1280	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1281	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1282	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1283	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1284	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	1285
<>	154:37f96f9d4de2	1286	/* Generate Start */
<>	154:37f96f9d4de2	1287	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1288
<>	144:ef7eb2e8f9f7	1289	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1290	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1293	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1294	process unlock */
<>	144:ef7eb2e8f9f7	1295	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1296	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1297
<>	144:ef7eb2e8f9f7	1298	return HAL_OK;
<>	144:ef7eb2e8f9f7	1299	}
<>	144:ef7eb2e8f9f7	1300	else
<>	144:ef7eb2e8f9f7	1301	{
<>	144:ef7eb2e8f9f7	1302	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1303	}
<>	144:ef7eb2e8f9f7	1304	}
<>	144:ef7eb2e8f9f7	1305
<>	144:ef7eb2e8f9f7	1306	/**
<>	144:ef7eb2e8f9f7	1307	* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1308	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1309	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1310	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	1311	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1312	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1313	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1314	* @retval HAL status
<>	144:ef7eb2e8f9f7	1315	*/
<>	144:ef7eb2e8f9f7	1316	HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1317	{
<>	154:37f96f9d4de2	1318	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1319
<>	144:ef7eb2e8f9f7	1320	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1321	{
<>	154:37f96f9d4de2	1322	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1323	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1324	do
<>	144:ef7eb2e8f9f7	1325	{
<>	154:37f96f9d4de2	1326	if(count-- == 0U)
<>	154:37f96f9d4de2	1327	{
<>	154:37f96f9d4de2	1328	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1329	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1330
<>	154:37f96f9d4de2	1331	/* Process Unlocked */
<>	154:37f96f9d4de2	1332	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1333
<>	154:37f96f9d4de2	1334	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1335	}
<>	144:ef7eb2e8f9f7	1336	}
<>	154:37f96f9d4de2	1337	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1338
<>	144:ef7eb2e8f9f7	1339	/* Process Locked */
<>	144:ef7eb2e8f9f7	1340	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1341
<>	154:37f96f9d4de2	1342	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1343	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1344	{
<>	154:37f96f9d4de2	1345	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1346	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1347	}
<>	144:ef7eb2e8f9f7	1348
<>	144:ef7eb2e8f9f7	1349	/* Disable Pos */
<>	154:37f96f9d4de2	1350	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1351
<>	154:37f96f9d4de2	1352	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	1353	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	1354	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1355
<>	154:37f96f9d4de2	1356	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1357	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1358	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1359	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1360	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1361	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	1362
<>	154:37f96f9d4de2	1363	/* Enable Acknowledge */
<>	154:37f96f9d4de2	1364	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	1365
<>	154:37f96f9d4de2	1366	/* Generate Start */
<>	154:37f96f9d4de2	1367	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	1368
<>	144:ef7eb2e8f9f7	1369	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1370	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	1373	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	1374	process unlock */
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1377	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	return HAL_OK;
<>	144:ef7eb2e8f9f7	1380	}
<>	144:ef7eb2e8f9f7	1381	else
<>	144:ef7eb2e8f9f7	1382	{
<>	144:ef7eb2e8f9f7	1383	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1384	}
<>	144:ef7eb2e8f9f7	1385	}
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	/**
<>	154:37f96f9d4de2	1388	* @brief Sequential transmit in master mode an amount of data in non-blocking mode with Interrupt
<>	154:37f96f9d4de2	1389	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	154:37f96f9d4de2	1390	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1391	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1392	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	1393	* in datasheet must be shift at right before call interface
<>	154:37f96f9d4de2	1394	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	1395	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	1396	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	154:37f96f9d4de2	1397	* @retval HAL status
<>	154:37f96f9d4de2	1398	*/
<>	154:37f96f9d4de2	1399	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	154:37f96f9d4de2	1400	{
<>	154:37f96f9d4de2	1401	__IO uint32_t Prev_State = 0x00U;
<>	154:37f96f9d4de2	1402	__IO uint32_t count = 0x00U;
<>	154:37f96f9d4de2	1403
<>	154:37f96f9d4de2	1404	/* Check the parameters */
<>	154:37f96f9d4de2	1405	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	154:37f96f9d4de2	1406
<>	154:37f96f9d4de2	1407	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	1408	{
<>	154:37f96f9d4de2	1409	/* Check Busy Flag only if FIRST call of Master interface */
<>	154:37f96f9d4de2	1410	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	154:37f96f9d4de2	1411	{
<>	154:37f96f9d4de2	1412	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1413	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1414	do
<>	154:37f96f9d4de2	1415	{
<>	154:37f96f9d4de2	1416	if(count-- == 0U)
<>	154:37f96f9d4de2	1417	{
<>	154:37f96f9d4de2	1418	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1419	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1420
<>	154:37f96f9d4de2	1421	/* Process Unlocked */
<>	154:37f96f9d4de2	1422	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1423
<>	154:37f96f9d4de2	1424	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1425	}
<>	154:37f96f9d4de2	1426	}
<>	154:37f96f9d4de2	1427	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	1428	}
<>	154:37f96f9d4de2	1429
<>	154:37f96f9d4de2	1430	/* Process Locked */
<>	154:37f96f9d4de2	1431	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1432
<>	154:37f96f9d4de2	1433	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1434	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1435	{
<>	154:37f96f9d4de2	1436	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1437	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1438	}
<>	154:37f96f9d4de2	1439
<>	154:37f96f9d4de2	1440	/* Disable Pos */
<>	154:37f96f9d4de2	1441	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1442
<>	154:37f96f9d4de2	1443	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	1444	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	154:37f96f9d4de2	1445	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1446
<>	154:37f96f9d4de2	1447	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1448	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1449	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1450	hi2c->XferOptions = XferOptions;
<>	154:37f96f9d4de2	1451	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1452	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	1453
<>	154:37f96f9d4de2	1454	Prev_State = hi2c->PreviousState;
<>	154:37f96f9d4de2	1455
<>	154:37f96f9d4de2	1456	/* Generate Start */
<>	154:37f96f9d4de2	1457	if((Prev_State == I2C_STATE_MASTER_BUSY_RX) \|\| (Prev_State == I2C_STATE_NONE))
<>	154:37f96f9d4de2	1458	{
<>	154:37f96f9d4de2	1459	/* Generate Start condition if first transfer */
<>	154:37f96f9d4de2	1460	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	154:37f96f9d4de2	1461	{
<>	154:37f96f9d4de2	1462	/* Generate Start */
<>	154:37f96f9d4de2	1463	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	1464	}
<>	154:37f96f9d4de2	1465	else if(Prev_State == I2C_STATE_MASTER_BUSY_RX)
<>	154:37f96f9d4de2	1466	{
<>	154:37f96f9d4de2	1467	/* Generate ReStart */
<>	154:37f96f9d4de2	1468	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	1469	}
<>	154:37f96f9d4de2	1470	}
<>	154:37f96f9d4de2	1471
<>	154:37f96f9d4de2	1472	/* Process Unlocked */
<>	154:37f96f9d4de2	1473	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1474
<>	154:37f96f9d4de2	1475	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	1476	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	1477	process unlock */
<>	154:37f96f9d4de2	1478
<>	154:37f96f9d4de2	1479	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	1480	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1481
<>	154:37f96f9d4de2	1482	return HAL_OK;
<>	154:37f96f9d4de2	1483	}
<>	154:37f96f9d4de2	1484	else
<>	154:37f96f9d4de2	1485	{
<>	154:37f96f9d4de2	1486	return HAL_BUSY;
<>	154:37f96f9d4de2	1487	}
<>	154:37f96f9d4de2	1488	}
<>	154:37f96f9d4de2	1489
<>	154:37f96f9d4de2	1490	/**
<>	154:37f96f9d4de2	1491	* @brief Sequential receive in master mode an amount of data in non-blocking mode with Interrupt
<>	154:37f96f9d4de2	1492	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	144:ef7eb2e8f9f7	1493	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1494	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1495	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	1496	* in datasheet must be shift at right before call interface
<>	154:37f96f9d4de2	1497	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	1498	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	1499	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	154:37f96f9d4de2	1500	* @retval HAL status
<>	154:37f96f9d4de2	1501	*/
<>	154:37f96f9d4de2	1502	HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	154:37f96f9d4de2	1503	{
<>	154:37f96f9d4de2	1504	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1505
<>	154:37f96f9d4de2	1506	/* Check the parameters */
<>	154:37f96f9d4de2	1507	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	154:37f96f9d4de2	1508
<>	154:37f96f9d4de2	1509	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	1510	{
<>	154:37f96f9d4de2	1511	/* Check Busy Flag only if FIRST call of Master interface */
<>	154:37f96f9d4de2	1512	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME))
<>	154:37f96f9d4de2	1513	{
<>	154:37f96f9d4de2	1514	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1515	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1516	do
<>	154:37f96f9d4de2	1517	{
<>	154:37f96f9d4de2	1518	if(count-- == 0U)
<>	154:37f96f9d4de2	1519	{
<>	154:37f96f9d4de2	1520	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1521	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1522
<>	154:37f96f9d4de2	1523	/* Process Unlocked */
<>	154:37f96f9d4de2	1524	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1525
<>	154:37f96f9d4de2	1526	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1527	}
<>	154:37f96f9d4de2	1528	}
<>	154:37f96f9d4de2	1529	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	1530	}
<>	154:37f96f9d4de2	1531
<>	154:37f96f9d4de2	1532	/* Process Locked */
<>	154:37f96f9d4de2	1533	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1534
<>	154:37f96f9d4de2	1535	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1536	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1537	{
<>	154:37f96f9d4de2	1538	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1539	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1540	}
<>	154:37f96f9d4de2	1541
<>	154:37f96f9d4de2	1542	/* Disable Pos */
<>	154:37f96f9d4de2	1543	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1544
<>	154:37f96f9d4de2	1545	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	1546	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	154:37f96f9d4de2	1547	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1548
<>	154:37f96f9d4de2	1549	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1550	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1551	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1552	hi2c->XferOptions = XferOptions;
<>	154:37f96f9d4de2	1553	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1554	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	1555
<>	154:37f96f9d4de2	1556	if((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) \|\| (hi2c->PreviousState == I2C_STATE_NONE))
<>	154:37f96f9d4de2	1557	{
<>	154:37f96f9d4de2	1558	/* Generate Start condition if first transfer */
<>	154:37f96f9d4de2	1559	if((XferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (XferOptions == I2C_FIRST_FRAME) \|\| (XferOptions == I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	1560	{
<>	154:37f96f9d4de2	1561	/* Enable Acknowledge */
<>	154:37f96f9d4de2	1562	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	1563
<>	154:37f96f9d4de2	1564	/* Generate Start */
<>	154:37f96f9d4de2	1565	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	1566	}
<>	154:37f96f9d4de2	1567	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	154:37f96f9d4de2	1568	{
<>	154:37f96f9d4de2	1569	/* Enable Acknowledge */
<>	154:37f96f9d4de2	1570	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	1571
<>	154:37f96f9d4de2	1572	/* Generate ReStart */
<>	154:37f96f9d4de2	1573	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	1574	}
<>	154:37f96f9d4de2	1575	}
<>	154:37f96f9d4de2	1576
<>	154:37f96f9d4de2	1577	/* Process Unlocked */
<>	154:37f96f9d4de2	1578	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1579
<>	154:37f96f9d4de2	1580	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	1581	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	1582	process unlock */
<>	154:37f96f9d4de2	1583
<>	154:37f96f9d4de2	1584	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	1585	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1586
<>	154:37f96f9d4de2	1587	return HAL_OK;
<>	154:37f96f9d4de2	1588	}
<>	154:37f96f9d4de2	1589	else
<>	154:37f96f9d4de2	1590	{
<>	154:37f96f9d4de2	1591	return HAL_BUSY;
<>	154:37f96f9d4de2	1592	}
<>	154:37f96f9d4de2	1593	}
<>	154:37f96f9d4de2	1594
<>	154:37f96f9d4de2	1595	/**
<>	154:37f96f9d4de2	1596	* @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
<>	154:37f96f9d4de2	1597	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1598	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1599	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1600	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1601	* @retval HAL status
<>	144:ef7eb2e8f9f7	1602	*/
<>	144:ef7eb2e8f9f7	1603	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1604	{
<>	154:37f96f9d4de2	1605	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1606
<>	144:ef7eb2e8f9f7	1607	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1608	{
<>	154:37f96f9d4de2	1609	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1610	{
<>	144:ef7eb2e8f9f7	1611	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1612	}
<>	144:ef7eb2e8f9f7	1613
<>	144:ef7eb2e8f9f7	1614	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1615	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1616	do
<>	144:ef7eb2e8f9f7	1617	{
<>	154:37f96f9d4de2	1618	if(count-- == 0U)
<>	154:37f96f9d4de2	1619	{
<>	154:37f96f9d4de2	1620	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1621	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1622
<>	154:37f96f9d4de2	1623	/* Process Unlocked */
<>	154:37f96f9d4de2	1624	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1625
<>	154:37f96f9d4de2	1626	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1627	}
<>	144:ef7eb2e8f9f7	1628	}
<>	154:37f96f9d4de2	1629	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1630
<>	144:ef7eb2e8f9f7	1631	/* Process Locked */
<>	144:ef7eb2e8f9f7	1632	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1633
<>	154:37f96f9d4de2	1634	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1635	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1636	{
<>	154:37f96f9d4de2	1637	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1638	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1639	}
<>	154:37f96f9d4de2	1640
<>	144:ef7eb2e8f9f7	1641	/* Disable Pos */
<>	154:37f96f9d4de2	1642	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1643
<>	154:37f96f9d4de2	1644	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	1645	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1646	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1647
<>	154:37f96f9d4de2	1648	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1649	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1650	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1651	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1652	hi2c->XferSize = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	1653
<>	144:ef7eb2e8f9f7	1654	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	1655	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	1656
<>	144:ef7eb2e8f9f7	1657	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1658	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1659
<>	144:ef7eb2e8f9f7	1660	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1661	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1662	process unlock */
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1665	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1666
<>	144:ef7eb2e8f9f7	1667	return HAL_OK;
<>	144:ef7eb2e8f9f7	1668	}
<>	144:ef7eb2e8f9f7	1669	else
<>	144:ef7eb2e8f9f7	1670	{
<>	144:ef7eb2e8f9f7	1671	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1672	}
<>	144:ef7eb2e8f9f7	1673	}
<>	144:ef7eb2e8f9f7	1674
<>	144:ef7eb2e8f9f7	1675	/**
<>	144:ef7eb2e8f9f7	1676	* @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	144:ef7eb2e8f9f7	1677	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1678	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	1679	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1680	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1681	* @retval HAL status
<>	144:ef7eb2e8f9f7	1682	*/
<>	144:ef7eb2e8f9f7	1683	HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1684	{
<>	154:37f96f9d4de2	1685	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1686
<>	144:ef7eb2e8f9f7	1687	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1688	{
<>	154:37f96f9d4de2	1689	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	1690	{
<>	144:ef7eb2e8f9f7	1691	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1692	}
<>	144:ef7eb2e8f9f7	1693
<>	154:37f96f9d4de2	1694	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1695	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1696	do
<>	154:37f96f9d4de2	1697	{
<>	154:37f96f9d4de2	1698	if(count-- == 0U)
<>	154:37f96f9d4de2	1699	{
<>	154:37f96f9d4de2	1700	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1701	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1702
<>	154:37f96f9d4de2	1703	/* Process Unlocked */
<>	154:37f96f9d4de2	1704	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1705
<>	154:37f96f9d4de2	1706	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1707	}
<>	154:37f96f9d4de2	1708	}
<>	154:37f96f9d4de2	1709	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	1710
<>	154:37f96f9d4de2	1711	/* Process Locked */
<>	154:37f96f9d4de2	1712	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1713
<>	154:37f96f9d4de2	1714	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1715	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	144:ef7eb2e8f9f7	1716	{
<>	154:37f96f9d4de2	1717	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1718	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1719	}
<>	154:37f96f9d4de2	1720
<>	154:37f96f9d4de2	1721	/* Disable Pos */
<>	154:37f96f9d4de2	1722	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1723
<>	154:37f96f9d4de2	1724	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	1725	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	1726	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1727
<>	154:37f96f9d4de2	1728	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1729	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1730	hi2c->XferSize = Size;
<>	154:37f96f9d4de2	1731	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1732	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	1733
<>	154:37f96f9d4de2	1734	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	1735	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	1736
<>	154:37f96f9d4de2	1737	/* Process Unlocked */
<>	154:37f96f9d4de2	1738	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1739
<>	154:37f96f9d4de2	1740	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	1741	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	1742	process unlock */
<>	154:37f96f9d4de2	1743
<>	154:37f96f9d4de2	1744	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	1745	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1746
<>	154:37f96f9d4de2	1747	return HAL_OK;
<>	154:37f96f9d4de2	1748	}
<>	154:37f96f9d4de2	1749	else
<>	154:37f96f9d4de2	1750	{
<>	154:37f96f9d4de2	1751	return HAL_BUSY;
<>	154:37f96f9d4de2	1752	}
<>	154:37f96f9d4de2	1753	}
<>	154:37f96f9d4de2	1754
<>	154:37f96f9d4de2	1755	/**
<>	154:37f96f9d4de2	1756	* @brief Sequential transmit in slave mode an amount of data in no-blocking mode with Interrupt
<>	154:37f96f9d4de2	1757	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	154:37f96f9d4de2	1758	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1759	* the configuration information for I2C module
<>	154:37f96f9d4de2	1760	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	1761	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	1762	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	154:37f96f9d4de2	1763	* @retval HAL status
<>	154:37f96f9d4de2	1764	*/
<>	154:37f96f9d4de2	1765	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	154:37f96f9d4de2	1766	{
<>	154:37f96f9d4de2	1767	/* Check the parameters */
<>	154:37f96f9d4de2	1768	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	154:37f96f9d4de2	1769
<>	154:37f96f9d4de2	1770	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	154:37f96f9d4de2	1771	{
<>	154:37f96f9d4de2	1772	if((pData == NULL) \|\| (Size == 0U))
<>	154:37f96f9d4de2	1773	{
<>	154:37f96f9d4de2	1774	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1775	}
<>	144:ef7eb2e8f9f7	1776
<>	144:ef7eb2e8f9f7	1777	/* Process Locked */
<>	144:ef7eb2e8f9f7	1778	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1779
<>	154:37f96f9d4de2	1780	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1781	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1782	{
<>	154:37f96f9d4de2	1783	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1784	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1785	}
<>	154:37f96f9d4de2	1786
<>	144:ef7eb2e8f9f7	1787	/* Disable Pos */
<>	154:37f96f9d4de2	1788	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1789
<>	154:37f96f9d4de2	1790	hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
<>	154:37f96f9d4de2	1791	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	144:ef7eb2e8f9f7	1792	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	1793
<>	154:37f96f9d4de2	1794	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1795	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1796	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1797	hi2c->XferOptions = XferOptions;
<>	154:37f96f9d4de2	1798	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1799
<>	154:37f96f9d4de2	1800	/* Clear ADDR flag */
<>	154:37f96f9d4de2	1801	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	1802
<>	154:37f96f9d4de2	1803	/* Process Unlocked */
<>	154:37f96f9d4de2	1804	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1805
<>	154:37f96f9d4de2	1806	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	1807	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	1808	process unlock */
<>	154:37f96f9d4de2	1809
<>	154:37f96f9d4de2	1810	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	1811	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1812
<>	154:37f96f9d4de2	1813	return HAL_OK;
<>	154:37f96f9d4de2	1814	}
<>	154:37f96f9d4de2	1815	else
<>	154:37f96f9d4de2	1816	{
<>	154:37f96f9d4de2	1817	return HAL_BUSY;
<>	154:37f96f9d4de2	1818	}
<>	154:37f96f9d4de2	1819	}
<>	154:37f96f9d4de2	1820
<>	154:37f96f9d4de2	1821	/**
<>	154:37f96f9d4de2	1822	* @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt
<>	154:37f96f9d4de2	1823	* @note This interface allow to manage repeated start condition when a direction change during transfer
<>	154:37f96f9d4de2	1824	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1825	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1826	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	1827	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	1828	* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
<>	154:37f96f9d4de2	1829	* @retval HAL status
<>	154:37f96f9d4de2	1830	*/
<>	154:37f96f9d4de2	1831	HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size, uint32_t XferOptions)
<>	154:37f96f9d4de2	1832	{
<>	154:37f96f9d4de2	1833	/* Check the parameters */
<>	154:37f96f9d4de2	1834	assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
<>	154:37f96f9d4de2	1835
<>	154:37f96f9d4de2	1836	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	154:37f96f9d4de2	1837	{
<>	154:37f96f9d4de2	1838	if((pData == NULL) \|\| (Size == 0U))
<>	154:37f96f9d4de2	1839	{
<>	154:37f96f9d4de2	1840	return HAL_ERROR;
<>	154:37f96f9d4de2	1841	}
<>	154:37f96f9d4de2	1842
<>	154:37f96f9d4de2	1843	/* Process Locked */
<>	154:37f96f9d4de2	1844	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	1845
<>	154:37f96f9d4de2	1846	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1847	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1848	{
<>	154:37f96f9d4de2	1849	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1850	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1851	}
<>	154:37f96f9d4de2	1852
<>	154:37f96f9d4de2	1853	/* Disable Pos */
<>	154:37f96f9d4de2	1854	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1855
<>	154:37f96f9d4de2	1856	hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
<>	154:37f96f9d4de2	1857	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	1858	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	1859
<>	154:37f96f9d4de2	1860	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	1861	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	1862	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	1863	hi2c->XferOptions = XferOptions;
<>	154:37f96f9d4de2	1864	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	1865
<>	154:37f96f9d4de2	1866	/* Clear ADDR flag */
<>	154:37f96f9d4de2	1867	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	1868
<>	144:ef7eb2e8f9f7	1869	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	1870	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	1871
<>	144:ef7eb2e8f9f7	1872	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	144:ef7eb2e8f9f7	1873	to avoid the risk of I2C interrupt handle execution before current
<>	144:ef7eb2e8f9f7	1874	process unlock */
<>	144:ef7eb2e8f9f7	1875
<>	144:ef7eb2e8f9f7	1876	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	1877	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	1878
<>	144:ef7eb2e8f9f7	1879	return HAL_OK;
<>	144:ef7eb2e8f9f7	1880	}
<>	144:ef7eb2e8f9f7	1881	else
<>	144:ef7eb2e8f9f7	1882	{
<>	144:ef7eb2e8f9f7	1883	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1884	}
<>	144:ef7eb2e8f9f7	1885	}
<>	144:ef7eb2e8f9f7	1886
<>	154:37f96f9d4de2	1887	/**
<>	154:37f96f9d4de2	1888	* @brief Enable the Address listen mode with Interrupt.
<>	154:37f96f9d4de2	1889	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1890	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1891	* @retval HAL status
<>	154:37f96f9d4de2	1892	*/
<>	154:37f96f9d4de2	1893	HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	1894	{
<>	154:37f96f9d4de2	1895	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	1896	{
<>	154:37f96f9d4de2	1897	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	154:37f96f9d4de2	1898
<>	154:37f96f9d4de2	1899	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1900	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1901	{
<>	154:37f96f9d4de2	1902	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1903	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1904	}
<>	154:37f96f9d4de2	1905
<>	154:37f96f9d4de2	1906	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	1907	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	1908
<>	154:37f96f9d4de2	1909	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	1910	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1911
<>	154:37f96f9d4de2	1912	return HAL_OK;
<>	154:37f96f9d4de2	1913	}
<>	154:37f96f9d4de2	1914	else
<>	154:37f96f9d4de2	1915	{
<>	154:37f96f9d4de2	1916	return HAL_BUSY;
<>	154:37f96f9d4de2	1917	}
<>	154:37f96f9d4de2	1918	}
<>	154:37f96f9d4de2	1919
<>	154:37f96f9d4de2	1920	/**
<>	154:37f96f9d4de2	1921	* @brief Disable the Address listen mode with Interrupt.
<>	154:37f96f9d4de2	1922	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	1923	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1924	* @retval HAL status
<>	154:37f96f9d4de2	1925	*/
<>	154:37f96f9d4de2	1926	HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	1927	{
<>	154:37f96f9d4de2	1928	/* Declaration of tmp to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	1929	uint32_t tmp;
<>	154:37f96f9d4de2	1930
<>	154:37f96f9d4de2	1931	/* Disable Address listen mode only if a transfer is not ongoing */
<>	154:37f96f9d4de2	1932	if(hi2c->State == HAL_I2C_STATE_LISTEN)
<>	154:37f96f9d4de2	1933	{
<>	154:37f96f9d4de2	1934	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	154:37f96f9d4de2	1935	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	154:37f96f9d4de2	1936	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1937	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	1938
<>	154:37f96f9d4de2	1939	/* Disable Address Acknowledge */
<>	154:37f96f9d4de2	1940	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	1941
<>	154:37f96f9d4de2	1942	/* Disable EVT and ERR interrupt */
<>	154:37f96f9d4de2	1943	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	1944
<>	154:37f96f9d4de2	1945	return HAL_OK;
<>	154:37f96f9d4de2	1946	}
<>	154:37f96f9d4de2	1947	else
<>	154:37f96f9d4de2	1948	{
<>	154:37f96f9d4de2	1949	return HAL_BUSY;
<>	154:37f96f9d4de2	1950	}
<>	154:37f96f9d4de2	1951	}
<>	154:37f96f9d4de2	1952
<>	144:ef7eb2e8f9f7	1953	/**
<>	144:ef7eb2e8f9f7	1954	* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	1955	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	1956	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	1957	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	1958	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	1959	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	1960	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	1961	* @retval HAL status
<>	144:ef7eb2e8f9f7	1962	*/
<>	144:ef7eb2e8f9f7	1963	HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	1964	{
<>	154:37f96f9d4de2	1965	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	1966
<>	144:ef7eb2e8f9f7	1967	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	1968	{
<>	154:37f96f9d4de2	1969	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	1970	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	1971	do
<>	144:ef7eb2e8f9f7	1972	{
<>	154:37f96f9d4de2	1973	if(count-- == 0U)
<>	154:37f96f9d4de2	1974	{
<>	154:37f96f9d4de2	1975	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	1976	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	1977
<>	154:37f96f9d4de2	1978	/* Process Unlocked */
<>	154:37f96f9d4de2	1979	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	1980
<>	154:37f96f9d4de2	1981	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	1982	}
<>	144:ef7eb2e8f9f7	1983	}
<>	154:37f96f9d4de2	1984	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	/* Process Locked */
<>	144:ef7eb2e8f9f7	1987	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	1988
<>	154:37f96f9d4de2	1989	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	1990	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	1991	{
<>	154:37f96f9d4de2	1992	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	1993	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	1994	}
<>	154:37f96f9d4de2	1995
<>	144:ef7eb2e8f9f7	1996	/* Disable Pos */
<>	154:37f96f9d4de2	1997	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	1998
<>	154:37f96f9d4de2	1999	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	2000	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	144:ef7eb2e8f9f7	2001	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2002
<>	154:37f96f9d4de2	2003	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2004	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2005	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2006	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2007	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2008	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	2009
<>	154:37f96f9d4de2	2010	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2011	{
<>	154:37f96f9d4de2	2012	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	2013	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	2014
<>	154:37f96f9d4de2	2015	/* Set the DMA error callback */
<>	154:37f96f9d4de2	2016	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	2017
<>	154:37f96f9d4de2	2018	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	2019	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	154:37f96f9d4de2	2020	hi2c->hdmatx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	2021
<>	154:37f96f9d4de2	2022	/* Enable the DMA channel */
<>	154:37f96f9d4de2	2023	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	154:37f96f9d4de2	2024
<>	154:37f96f9d4de2	2025	/* Enable Acknowledge */
<>	154:37f96f9d4de2	2026	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2027
<>	154:37f96f9d4de2	2028	/* Generate Start */
<>	154:37f96f9d4de2	2029	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	2030
<>	154:37f96f9d4de2	2031	/* Process Unlocked */
<>	154:37f96f9d4de2	2032	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2033
<>	154:37f96f9d4de2	2034	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2035	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2036	process unlock */
<>	154:37f96f9d4de2	2037
<>	154:37f96f9d4de2	2038	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	2039	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2040
<>	154:37f96f9d4de2	2041	/* Enable DMA Request */
<>	154:37f96f9d4de2	2042	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	2043	}
<>	154:37f96f9d4de2	2044	else
<>	154:37f96f9d4de2	2045	{
<>	154:37f96f9d4de2	2046	/* Enable Acknowledge */
<>	154:37f96f9d4de2	2047	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2048
<>	154:37f96f9d4de2	2049	/* Generate Start */
<>	154:37f96f9d4de2	2050	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	2051
<>	154:37f96f9d4de2	2052	/* Process Unlocked */
<>	154:37f96f9d4de2	2053	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2054
<>	154:37f96f9d4de2	2055	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2056	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2057	process unlock */
<>	154:37f96f9d4de2	2058
<>	154:37f96f9d4de2	2059	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	2060	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2061	}
<>	144:ef7eb2e8f9f7	2062
<>	144:ef7eb2e8f9f7	2063	return HAL_OK;
<>	144:ef7eb2e8f9f7	2064	}
<>	144:ef7eb2e8f9f7	2065	else
<>	144:ef7eb2e8f9f7	2066	{
<>	144:ef7eb2e8f9f7	2067	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2068	}
<>	144:ef7eb2e8f9f7	2069	}
<>	144:ef7eb2e8f9f7	2070
<>	144:ef7eb2e8f9f7	2071	/**
<>	154:37f96f9d4de2	2072	* @brief Receive in master mode an amount of data in non-blocking mode with DMA
<>	144:ef7eb2e8f9f7	2073	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2074	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	2075	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	2076	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	2077	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2078	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2079	* @retval HAL status
<>	144:ef7eb2e8f9f7	2080	*/
<>	144:ef7eb2e8f9f7	2081	HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2082	{
<>	154:37f96f9d4de2	2083	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	2084
<>	144:ef7eb2e8f9f7	2085	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2086	{
<>	154:37f96f9d4de2	2087	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2088	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	2089	do
<>	154:37f96f9d4de2	2090	{
<>	154:37f96f9d4de2	2091	if(count-- == 0U)
<>	154:37f96f9d4de2	2092	{
<>	154:37f96f9d4de2	2093	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2094	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	2095
<>	154:37f96f9d4de2	2096	/* Process Unlocked */
<>	154:37f96f9d4de2	2097	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2098
<>	154:37f96f9d4de2	2099	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	2100	}
<>	154:37f96f9d4de2	2101	}
<>	154:37f96f9d4de2	2102	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	2103
<>	154:37f96f9d4de2	2104	/* Process Locked */
<>	154:37f96f9d4de2	2105	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2106
<>	154:37f96f9d4de2	2107	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2108	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2109	{
<>	154:37f96f9d4de2	2110	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2111	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2112	}
<>	154:37f96f9d4de2	2113
<>	154:37f96f9d4de2	2114	/* Disable Pos */
<>	154:37f96f9d4de2	2115	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	2116
<>	154:37f96f9d4de2	2117	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	2118	hi2c->Mode = HAL_I2C_MODE_MASTER;
<>	154:37f96f9d4de2	2119	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	2120
<>	154:37f96f9d4de2	2121	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2122	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2123	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2124	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2125	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2126	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	2127
<>	154:37f96f9d4de2	2128	if(hi2c->XferSize > 0U)
<>	154:37f96f9d4de2	2129	{
<>	154:37f96f9d4de2	2130	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	2131	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	2132
<>	154:37f96f9d4de2	2133	/* Set the DMA error callback */
<>	154:37f96f9d4de2	2134	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	2135
<>	154:37f96f9d4de2	2136	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	2137	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	154:37f96f9d4de2	2138	hi2c->hdmarx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	2139
<>	154:37f96f9d4de2	2140	/* Enable the DMA channel */
<>	154:37f96f9d4de2	2141	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	154:37f96f9d4de2	2142
<>	154:37f96f9d4de2	2143	/* Enable Acknowledge */
<>	154:37f96f9d4de2	2144	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2145
<>	154:37f96f9d4de2	2146	/* Generate Start */
<>	154:37f96f9d4de2	2147	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	2148
<>	154:37f96f9d4de2	2149	/* Process Unlocked */
<>	154:37f96f9d4de2	2150	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2151
<>	154:37f96f9d4de2	2152	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2153	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2154	process unlock */
<>	154:37f96f9d4de2	2155
<>	154:37f96f9d4de2	2156	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	2157	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2158
<>	154:37f96f9d4de2	2159	/* Enable DMA Request */
<>	154:37f96f9d4de2	2160	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	2161	}
<>	154:37f96f9d4de2	2162	else
<>	154:37f96f9d4de2	2163	{
<>	154:37f96f9d4de2	2164	/* Enable Acknowledge */
<>	154:37f96f9d4de2	2165	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2166
<>	154:37f96f9d4de2	2167	/* Generate Start */
<>	154:37f96f9d4de2	2168	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	2169
<>	154:37f96f9d4de2	2170	/* Process Unlocked */
<>	154:37f96f9d4de2	2171	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2172
<>	154:37f96f9d4de2	2173	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2174	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2175	process unlock */
<>	154:37f96f9d4de2	2176
<>	154:37f96f9d4de2	2177	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	2178	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2179	}
<>	154:37f96f9d4de2	2180
<>	154:37f96f9d4de2	2181	return HAL_OK;
<>	154:37f96f9d4de2	2182	}
<>	154:37f96f9d4de2	2183	else
<>	154:37f96f9d4de2	2184	{
<>	154:37f96f9d4de2	2185	return HAL_BUSY;
<>	154:37f96f9d4de2	2186	}
<>	154:37f96f9d4de2	2187	}
<>	154:37f96f9d4de2	2188
<>	154:37f96f9d4de2	2189	/**
<>	154:37f96f9d4de2	2190	* @brief Abort a master I2C process communication with Interrupt.
<>	154:37f96f9d4de2	2191	* @note This abort can be called only if state is ready
<>	154:37f96f9d4de2	2192	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	2193	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	2194	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	2195	* in datasheet must be shift at right before call interface
<>	154:37f96f9d4de2	2196	* @retval HAL status
<>	154:37f96f9d4de2	2197	*/
<>	154:37f96f9d4de2	2198	HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
<>	154:37f96f9d4de2	2199	{
AnnaBridge	165:e614a9f1c9e2	2200	/* Prevent unused argument(s) compilation warning */
AnnaBridge	165:e614a9f1c9e2	2201	UNUSED(DevAddress);
AnnaBridge	165:e614a9f1c9e2	2202
<>	154:37f96f9d4de2	2203	/* Abort Master transfer during Receive or Transmit process */
<>	154:37f96f9d4de2	2204	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	154:37f96f9d4de2	2205	{
<>	154:37f96f9d4de2	2206	/* Process Locked */
<>	154:37f96f9d4de2	2207	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2208
<>	154:37f96f9d4de2	2209	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2210	hi2c->State = HAL_I2C_STATE_ABORT;
<>	154:37f96f9d4de2	2211
<>	154:37f96f9d4de2	2212	/* Disable Acknowledge */
<>	154:37f96f9d4de2	2213	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	2214
<>	154:37f96f9d4de2	2215	/* Generate Stop */
<>	154:37f96f9d4de2	2216	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	2217
<>	154:37f96f9d4de2	2218	hi2c->XferCount = 0U;
<>	154:37f96f9d4de2	2219
<>	154:37f96f9d4de2	2220	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	2221	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2222
<>	154:37f96f9d4de2	2223	/* Process Unlocked */
<>	154:37f96f9d4de2	2224	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2225
<>	154:37f96f9d4de2	2226	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	154:37f96f9d4de2	2227	I2C_ITError(hi2c);
<>	154:37f96f9d4de2	2228
<>	154:37f96f9d4de2	2229	return HAL_OK;
<>	154:37f96f9d4de2	2230	}
<>	154:37f96f9d4de2	2231	else
<>	154:37f96f9d4de2	2232	{
<>	154:37f96f9d4de2	2233	/* Wrong usage of abort function */
<>	154:37f96f9d4de2	2234	/* This function should be used only in case of abort monitored by master device */
<>	154:37f96f9d4de2	2235	return HAL_ERROR;
<>	154:37f96f9d4de2	2236	}
<>	154:37f96f9d4de2	2237	}
<>	154:37f96f9d4de2	2238
<>	154:37f96f9d4de2	2239	/**
<>	154:37f96f9d4de2	2240	* @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
<>	154:37f96f9d4de2	2241	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	2242	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	2243	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	2244	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	2245	* @retval HAL status
<>	154:37f96f9d4de2	2246	*/
<>	154:37f96f9d4de2	2247	HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	154:37f96f9d4de2	2248	{
<>	154:37f96f9d4de2	2249	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	2250
<>	154:37f96f9d4de2	2251	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	2252	{
<>	154:37f96f9d4de2	2253	if((pData == NULL) \|\| (Size == 0U))
<>	144:ef7eb2e8f9f7	2254	{
<>	144:ef7eb2e8f9f7	2255	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2256	}
<>	144:ef7eb2e8f9f7	2257
<>	144:ef7eb2e8f9f7	2258	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2259	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	2260	do
<>	154:37f96f9d4de2	2261	{
<>	154:37f96f9d4de2	2262	if(count-- == 0U)
<>	154:37f96f9d4de2	2263	{
<>	154:37f96f9d4de2	2264	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2265	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	2266
<>	154:37f96f9d4de2	2267	/* Process Unlocked */
<>	154:37f96f9d4de2	2268	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2269
<>	154:37f96f9d4de2	2270	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	2271	}
<>	154:37f96f9d4de2	2272	}
<>	154:37f96f9d4de2	2273	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	2274
<>	154:37f96f9d4de2	2275	/* Process Locked */
<>	154:37f96f9d4de2	2276	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2277
<>	154:37f96f9d4de2	2278	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2279	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2280	{
<>	154:37f96f9d4de2	2281	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2282	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2283	}
<>	154:37f96f9d4de2	2284
<>	154:37f96f9d4de2	2285	/* Disable Pos */
<>	154:37f96f9d4de2	2286	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	2287
<>	154:37f96f9d4de2	2288	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	2289	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	2290	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	2291
<>	154:37f96f9d4de2	2292	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2293	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2294	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2295	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2296	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2297
<>	154:37f96f9d4de2	2298	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	2299	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	2300
<>	154:37f96f9d4de2	2301	/* Set the DMA error callback */
<>	154:37f96f9d4de2	2302	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	2303
<>	154:37f96f9d4de2	2304	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	2305	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	154:37f96f9d4de2	2306	hi2c->hdmatx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	2307
<>	154:37f96f9d4de2	2308	/* Enable the DMA channel */
<>	154:37f96f9d4de2	2309	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	154:37f96f9d4de2	2310
<>	154:37f96f9d4de2	2311	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	2312	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2313
<>	154:37f96f9d4de2	2314	/* Process Unlocked */
<>	154:37f96f9d4de2	2315	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2316
<>	154:37f96f9d4de2	2317	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2318	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2319	process unlock */
<>	154:37f96f9d4de2	2320	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	2321	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2322
<>	154:37f96f9d4de2	2323	/* Enable DMA Request */
<>	154:37f96f9d4de2	2324	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	2325
<>	154:37f96f9d4de2	2326	return HAL_OK;
<>	154:37f96f9d4de2	2327	}
<>	154:37f96f9d4de2	2328	else
<>	154:37f96f9d4de2	2329	{
<>	154:37f96f9d4de2	2330	return HAL_BUSY;
<>	154:37f96f9d4de2	2331	}
<>	154:37f96f9d4de2	2332	}
<>	154:37f96f9d4de2	2333
<>	154:37f96f9d4de2	2334	/**
<>	154:37f96f9d4de2	2335	* @brief Receive in slave mode an amount of data in non-blocking mode with DMA
<>	154:37f96f9d4de2	2336	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	2337	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	2338	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	2339	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	2340	* @retval HAL status
<>	154:37f96f9d4de2	2341	*/
<>	154:37f96f9d4de2	2342	HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef hi2c, uint8_t pData, uint16_t Size)
<>	154:37f96f9d4de2	2343	{
<>	154:37f96f9d4de2	2344	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	2345
<>	154:37f96f9d4de2	2346	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	2347	{
<>	154:37f96f9d4de2	2348	if((pData == NULL) \|\| (Size == 0U))
<>	154:37f96f9d4de2	2349	{
<>	154:37f96f9d4de2	2350	return HAL_ERROR;
<>	154:37f96f9d4de2	2351	}
<>	154:37f96f9d4de2	2352
<>	154:37f96f9d4de2	2353	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2354	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	2355	do
<>	154:37f96f9d4de2	2356	{
<>	154:37f96f9d4de2	2357	if(count-- == 0U)
<>	154:37f96f9d4de2	2358	{
<>	154:37f96f9d4de2	2359	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2360	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	2361
<>	154:37f96f9d4de2	2362	/* Process Unlocked */
<>	154:37f96f9d4de2	2363	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2364
<>	154:37f96f9d4de2	2365	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	2366	}
<>	154:37f96f9d4de2	2367	}
<>	154:37f96f9d4de2	2368	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	154:37f96f9d4de2	2369
<>	154:37f96f9d4de2	2370	/* Process Locked */
<>	154:37f96f9d4de2	2371	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2372
<>	154:37f96f9d4de2	2373	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2374	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2375	{
<>	154:37f96f9d4de2	2376	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2377	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2378	}
<>	154:37f96f9d4de2	2379
<>	154:37f96f9d4de2	2380	/* Disable Pos */
<>	154:37f96f9d4de2	2381	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	2382
<>	154:37f96f9d4de2	2383	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	2384	hi2c->Mode = HAL_I2C_MODE_SLAVE;
<>	154:37f96f9d4de2	2385	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	2386
<>	154:37f96f9d4de2	2387	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2388	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2389	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2390	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2391	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2392
<>	154:37f96f9d4de2	2393	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	2394	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	2395
<>	154:37f96f9d4de2	2396	/* Set the DMA error callback */
<>	154:37f96f9d4de2	2397	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	2398
<>	154:37f96f9d4de2	2399	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	2400	hi2c->hdmarx->XferHalfCpltCallback = NULL;
<>	154:37f96f9d4de2	2401	hi2c->hdmarx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	2402
<>	154:37f96f9d4de2	2403	/* Enable the DMA channel */
<>	154:37f96f9d4de2	2404	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	154:37f96f9d4de2	2405
<>	154:37f96f9d4de2	2406	/* Enable Address Acknowledge */
<>	154:37f96f9d4de2	2407	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2408
<>	154:37f96f9d4de2	2409	/* Process Unlocked */
<>	154:37f96f9d4de2	2410	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2411
<>	154:37f96f9d4de2	2412	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2413	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2414	process unlock */
<>	154:37f96f9d4de2	2415	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	2416	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2417
<>	154:37f96f9d4de2	2418	/* Enable DMA Request */
<>	154:37f96f9d4de2	2419	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	2420
<>	154:37f96f9d4de2	2421	return HAL_OK;
<>	154:37f96f9d4de2	2422	}
<>	154:37f96f9d4de2	2423	else
<>	154:37f96f9d4de2	2424	{
<>	154:37f96f9d4de2	2425	return HAL_BUSY;
<>	154:37f96f9d4de2	2426	}
<>	154:37f96f9d4de2	2427	}
<>	154:37f96f9d4de2	2428	/**
<>	154:37f96f9d4de2	2429	* @brief Write an amount of data in blocking mode to a specific memory address
<>	154:37f96f9d4de2	2430	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	2431	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	2432	* @param DevAddress Target device address
<>	154:37f96f9d4de2	2433	* @param MemAddress Internal memory address
<>	154:37f96f9d4de2	2434	* @param MemAddSize Size of internal memory address
<>	154:37f96f9d4de2	2435	* @param pData Pointer to data buffer
<>	154:37f96f9d4de2	2436	* @param Size Amount of data to be sent
<>	154:37f96f9d4de2	2437	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	2438	* @retval HAL status
<>	154:37f96f9d4de2	2439	*/
<>	154:37f96f9d4de2	2440	HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	154:37f96f9d4de2	2441	{
<>	154:37f96f9d4de2	2442	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	2443
<>	154:37f96f9d4de2	2444	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	2445	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	2446
<>	154:37f96f9d4de2	2447	/* Check the parameters */
<>	154:37f96f9d4de2	2448	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	154:37f96f9d4de2	2449
<>	154:37f96f9d4de2	2450	if(hi2c->State == HAL_I2C_STATE_READY)
<>	154:37f96f9d4de2	2451	{
<>	154:37f96f9d4de2	2452	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2453	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2454	{
<>	144:ef7eb2e8f9f7	2455	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2456	}
<>	144:ef7eb2e8f9f7	2457
<>	144:ef7eb2e8f9f7	2458	/* Process Locked */
<>	144:ef7eb2e8f9f7	2459	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2460
<>	154:37f96f9d4de2	2461	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2462	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2463	{
<>	154:37f96f9d4de2	2464	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2465	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2466	}
<>	144:ef7eb2e8f9f7	2467
<>	144:ef7eb2e8f9f7	2468	/* Disable Pos */
<>	154:37f96f9d4de2	2469	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	2470
<>	154:37f96f9d4de2	2471	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	2472	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2473	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2474
<>	154:37f96f9d4de2	2475	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2476	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2477	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2478	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2479	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2480
<>	154:37f96f9d4de2	2481	/* Send Slave Address and Memory Address */
<>	154:37f96f9d4de2	2482	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2483	{
<>	144:ef7eb2e8f9f7	2484	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2485	{
<>	144:ef7eb2e8f9f7	2486	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2487	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2488	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2489	}
<>	144:ef7eb2e8f9f7	2490	else
<>	144:ef7eb2e8f9f7	2491	{
<>	144:ef7eb2e8f9f7	2492	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2493	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2494	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2495	}
<>	144:ef7eb2e8f9f7	2496	}
<>	144:ef7eb2e8f9f7	2497
<>	154:37f96f9d4de2	2498	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2499	{
<>	144:ef7eb2e8f9f7	2500	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	2501	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2502	{
<>	144:ef7eb2e8f9f7	2503	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2504	{
<>	144:ef7eb2e8f9f7	2505	/* Generate Stop */
<>	154:37f96f9d4de2	2506	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2507	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2508	}
<>	144:ef7eb2e8f9f7	2509	else
<>	144:ef7eb2e8f9f7	2510	{
<>	144:ef7eb2e8f9f7	2511	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2512	}
<>	144:ef7eb2e8f9f7	2513	}
<>	144:ef7eb2e8f9f7	2514
<>	144:ef7eb2e8f9f7	2515	/* Write data to DR */
<>	154:37f96f9d4de2	2516	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	2517	hi2c->XferSize--;
<>	154:37f96f9d4de2	2518	hi2c->XferCount--;
<>	154:37f96f9d4de2	2519
<>	154:37f96f9d4de2	2520	if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
<>	144:ef7eb2e8f9f7	2521	{
<>	144:ef7eb2e8f9f7	2522	/* Write data to DR */
<>	154:37f96f9d4de2	2523	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	2524	hi2c->XferSize--;
<>	154:37f96f9d4de2	2525	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2526	}
<>	144:ef7eb2e8f9f7	2527	}
<>	154:37f96f9d4de2	2528
<>	154:37f96f9d4de2	2529	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	2530	if(I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2531	{
<>	144:ef7eb2e8f9f7	2532	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2533	{
<>	144:ef7eb2e8f9f7	2534	/* Generate Stop */
<>	154:37f96f9d4de2	2535	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2536	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2537	}
<>	144:ef7eb2e8f9f7	2538	else
<>	144:ef7eb2e8f9f7	2539	{
<>	144:ef7eb2e8f9f7	2540	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2541	}
<>	144:ef7eb2e8f9f7	2542	}
<>	144:ef7eb2e8f9f7	2543
<>	144:ef7eb2e8f9f7	2544	/* Generate Stop */
<>	154:37f96f9d4de2	2545	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2546
<>	144:ef7eb2e8f9f7	2547	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2548	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	2549
<>	144:ef7eb2e8f9f7	2550	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2551	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2552
<>	144:ef7eb2e8f9f7	2553	return HAL_OK;
<>	144:ef7eb2e8f9f7	2554	}
<>	144:ef7eb2e8f9f7	2555	else
<>	144:ef7eb2e8f9f7	2556	{
<>	144:ef7eb2e8f9f7	2557	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2558	}
<>	144:ef7eb2e8f9f7	2559	}
<>	144:ef7eb2e8f9f7	2560
<>	144:ef7eb2e8f9f7	2561	/**
<>	144:ef7eb2e8f9f7	2562	* @brief Read an amount of data in blocking mode from a specific memory address
<>	144:ef7eb2e8f9f7	2563	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2564	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2565	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2566	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2567	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2568	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2569	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2570	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	2571	* @retval HAL status
<>	144:ef7eb2e8f9f7	2572	*/
<>	144:ef7eb2e8f9f7	2573	HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	2574	{
<>	154:37f96f9d4de2	2575	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	2576
<>	154:37f96f9d4de2	2577	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	2578	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	2579
<>	144:ef7eb2e8f9f7	2580	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2581	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2582
<>	144:ef7eb2e8f9f7	2583	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2584	{
<>	144:ef7eb2e8f9f7	2585	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2586	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2587	{
<>	144:ef7eb2e8f9f7	2588	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2589	}
<>	144:ef7eb2e8f9f7	2590
<>	144:ef7eb2e8f9f7	2591	/* Process Locked */
<>	144:ef7eb2e8f9f7	2592	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	2593
<>	154:37f96f9d4de2	2594	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2595	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2596	{
<>	154:37f96f9d4de2	2597	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2598	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2599	}
<>	144:ef7eb2e8f9f7	2600
<>	144:ef7eb2e8f9f7	2601	/* Disable Pos */
<>	154:37f96f9d4de2	2602	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	2603
<>	154:37f96f9d4de2	2604	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	2605	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2606	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2607
<>	154:37f96f9d4de2	2608	/* Prepare transfer parameters */
<>	154:37f96f9d4de2	2609	hi2c->pBuffPtr = pData;
<>	154:37f96f9d4de2	2610	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2611	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2612	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	2613
<>	144:ef7eb2e8f9f7	2614	/* Send Slave Address and Memory Address */
<>	154:37f96f9d4de2	2615	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2616	{
<>	144:ef7eb2e8f9f7	2617	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	2618	{
<>	144:ef7eb2e8f9f7	2619	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2620	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2621	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2622	}
<>	144:ef7eb2e8f9f7	2623	else
<>	144:ef7eb2e8f9f7	2624	{
<>	144:ef7eb2e8f9f7	2625	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2626	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2627	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2628	}
<>	144:ef7eb2e8f9f7	2629	}
<>	144:ef7eb2e8f9f7	2630
<>	154:37f96f9d4de2	2631	if(hi2c->XferSize == 0U)
<>	154:37f96f9d4de2	2632	{
<>	154:37f96f9d4de2	2633	/* Clear ADDR flag */
<>	154:37f96f9d4de2	2634	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	2635
<>	154:37f96f9d4de2	2636	/* Generate Stop */
<>	154:37f96f9d4de2	2637	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	2638	}
<>	154:37f96f9d4de2	2639	else if(hi2c->XferSize == 1U)
<>	144:ef7eb2e8f9f7	2640	{
<>	144:ef7eb2e8f9f7	2641	/* Disable Acknowledge */
<>	154:37f96f9d4de2	2642	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2643
<>	144:ef7eb2e8f9f7	2644	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	2645	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	2646	__disable_irq();
<>	144:ef7eb2e8f9f7	2647
<>	144:ef7eb2e8f9f7	2648	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2649	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2650
<>	144:ef7eb2e8f9f7	2651	/* Generate Stop */
<>	154:37f96f9d4de2	2652	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2653
<>	144:ef7eb2e8f9f7	2654	/* Re-enable IRQs */
<>	154:37f96f9d4de2	2655	__enable_irq();
<>	144:ef7eb2e8f9f7	2656	}
<>	154:37f96f9d4de2	2657	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	2658	{
<>	144:ef7eb2e8f9f7	2659	/* Enable Pos */
<>	154:37f96f9d4de2	2660	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2661
<>	144:ef7eb2e8f9f7	2662	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	2663	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	2664	__disable_irq();
<>	144:ef7eb2e8f9f7	2665
<>	144:ef7eb2e8f9f7	2666	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2667	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	2668
<>	144:ef7eb2e8f9f7	2669	/* Disable Acknowledge */
<>	154:37f96f9d4de2	2670	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	2671
<>	144:ef7eb2e8f9f7	2672	/* Re-enable IRQs */
<>	144:ef7eb2e8f9f7	2673	__enable_irq();
<>	144:ef7eb2e8f9f7	2674	}
<>	144:ef7eb2e8f9f7	2675	else
<>	144:ef7eb2e8f9f7	2676	{
<>	144:ef7eb2e8f9f7	2677	/* Enable Acknowledge */
<>	144:ef7eb2e8f9f7	2678	SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
<>	144:ef7eb2e8f9f7	2679
<>	144:ef7eb2e8f9f7	2680	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	2681	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	2682	}
<>	144:ef7eb2e8f9f7	2683
<>	154:37f96f9d4de2	2684	while(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	2685	{
<>	154:37f96f9d4de2	2686	if(hi2c->XferSize <= 3U)
<>	144:ef7eb2e8f9f7	2687	{
<>	144:ef7eb2e8f9f7	2688	/* One byte */
<>	154:37f96f9d4de2	2689	if(hi2c->XferSize== 1U)
<>	144:ef7eb2e8f9f7	2690	{
<>	144:ef7eb2e8f9f7	2691	/* Wait until RXNE flag is set */
<>	154:37f96f9d4de2	2692	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2693	{
<>	144:ef7eb2e8f9f7	2694	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2695	{
<>	144:ef7eb2e8f9f7	2696	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2697	}
<>	144:ef7eb2e8f9f7	2698	else
<>	144:ef7eb2e8f9f7	2699	{
<>	144:ef7eb2e8f9f7	2700	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2701	}
<>	144:ef7eb2e8f9f7	2702	}
<>	144:ef7eb2e8f9f7	2703
<>	144:ef7eb2e8f9f7	2704	/* Read data from DR */
<>	154:37f96f9d4de2	2705	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2706	hi2c->XferSize--;
<>	154:37f96f9d4de2	2707	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2708	}
<>	144:ef7eb2e8f9f7	2709	/* Two bytes */
AnnaBridge	165:e614a9f1c9e2	2710	else if(hi2c->XferSize == 2U)
<>	144:ef7eb2e8f9f7	2711	{
<>	144:ef7eb2e8f9f7	2712	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	2713	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2714	{
<>	144:ef7eb2e8f9f7	2715	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2716	}
<>	144:ef7eb2e8f9f7	2717
<>	144:ef7eb2e8f9f7	2718	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	2719	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	2720	__disable_irq();
<>	144:ef7eb2e8f9f7	2721
<>	144:ef7eb2e8f9f7	2722	/* Generate Stop */
<>	154:37f96f9d4de2	2723	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2724
<>	144:ef7eb2e8f9f7	2725	/* Read data from DR */
<>	154:37f96f9d4de2	2726	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2727	hi2c->XferSize--;
<>	154:37f96f9d4de2	2728	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2729
<>	144:ef7eb2e8f9f7	2730	/* Re-enable IRQs */
<>	144:ef7eb2e8f9f7	2731	__enable_irq();
<>	144:ef7eb2e8f9f7	2732
<>	144:ef7eb2e8f9f7	2733	/* Read data from DR */
<>	154:37f96f9d4de2	2734	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2735	hi2c->XferSize--;
<>	154:37f96f9d4de2	2736	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2737	}
<>	144:ef7eb2e8f9f7	2738	/* 3 Last bytes */
<>	144:ef7eb2e8f9f7	2739	else
<>	144:ef7eb2e8f9f7	2740	{
<>	144:ef7eb2e8f9f7	2741	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	2742	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2743	{
<>	144:ef7eb2e8f9f7	2744	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2745	}
<>	144:ef7eb2e8f9f7	2746
<>	144:ef7eb2e8f9f7	2747	/* Disable Acknowledge */
<>	154:37f96f9d4de2	2748	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	2749
<>	144:ef7eb2e8f9f7	2750	/* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3
<>	144:ef7eb2e8f9f7	2751	software sequence must complete before the current byte end of transfer */
<>	144:ef7eb2e8f9f7	2752	__disable_irq();
<>	144:ef7eb2e8f9f7	2753
<>	144:ef7eb2e8f9f7	2754	/* Read data from DR */
<>	154:37f96f9d4de2	2755	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2756	hi2c->XferSize--;
<>	154:37f96f9d4de2	2757	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2758
<>	144:ef7eb2e8f9f7	2759	/* Wait until BTF flag is set */
<>	154:37f96f9d4de2	2760	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2761	{
<>	144:ef7eb2e8f9f7	2762	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2763	}
<>	144:ef7eb2e8f9f7	2764
<>	144:ef7eb2e8f9f7	2765	/* Generate Stop */
<>	154:37f96f9d4de2	2766	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	2767
<>	144:ef7eb2e8f9f7	2768	/* Read data from DR */
<>	154:37f96f9d4de2	2769	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2770	hi2c->XferSize--;
<>	154:37f96f9d4de2	2771	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2772
<>	144:ef7eb2e8f9f7	2773	/* Re-enable IRQs */
<>	154:37f96f9d4de2	2774	__enable_irq();
<>	144:ef7eb2e8f9f7	2775
<>	144:ef7eb2e8f9f7	2776	/* Read data from DR */
<>	154:37f96f9d4de2	2777	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2778	hi2c->XferSize--;
<>	154:37f96f9d4de2	2779	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2780	}
<>	144:ef7eb2e8f9f7	2781	}
<>	144:ef7eb2e8f9f7	2782	else
<>	144:ef7eb2e8f9f7	2783	{
<>	144:ef7eb2e8f9f7	2784	/* Wait until RXNE flag is set */
<>	154:37f96f9d4de2	2785	if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	2786	{
<>	144:ef7eb2e8f9f7	2787	if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
<>	144:ef7eb2e8f9f7	2788	{
<>	144:ef7eb2e8f9f7	2789	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	2790	}
<>	144:ef7eb2e8f9f7	2791	else
<>	144:ef7eb2e8f9f7	2792	{
<>	144:ef7eb2e8f9f7	2793	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	2794	}
<>	144:ef7eb2e8f9f7	2795	}
<>	144:ef7eb2e8f9f7	2796
<>	144:ef7eb2e8f9f7	2797	/* Read data from DR */
<>	154:37f96f9d4de2	2798	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2799	hi2c->XferSize--;
<>	154:37f96f9d4de2	2800	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2801
<>	144:ef7eb2e8f9f7	2802	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	144:ef7eb2e8f9f7	2803	{
<>	144:ef7eb2e8f9f7	2804	/* Read data from DR */
<>	154:37f96f9d4de2	2805	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	2806	hi2c->XferSize--;
<>	154:37f96f9d4de2	2807	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	2808	}
<>	144:ef7eb2e8f9f7	2809	}
<>	144:ef7eb2e8f9f7	2810	}
<>	144:ef7eb2e8f9f7	2811
<>	144:ef7eb2e8f9f7	2812	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	2813	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	2814
<>	144:ef7eb2e8f9f7	2815	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2816	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2817
<>	144:ef7eb2e8f9f7	2818	return HAL_OK;
<>	144:ef7eb2e8f9f7	2819	}
<>	144:ef7eb2e8f9f7	2820	else
<>	144:ef7eb2e8f9f7	2821	{
<>	144:ef7eb2e8f9f7	2822	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2823	}
<>	144:ef7eb2e8f9f7	2824	}
<>	144:ef7eb2e8f9f7	2825
<>	144:ef7eb2e8f9f7	2826	/**
<>	144:ef7eb2e8f9f7	2827	* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
<>	144:ef7eb2e8f9f7	2828	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2829	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2830	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2831	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2832	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2833	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2834	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2835	* @retval HAL status
<>	144:ef7eb2e8f9f7	2836	*/
<>	144:ef7eb2e8f9f7	2837	HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2838	{
<>	154:37f96f9d4de2	2839	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	2840
<>	144:ef7eb2e8f9f7	2841	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2842	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2843
<>	144:ef7eb2e8f9f7	2844	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2845	{
<>	154:37f96f9d4de2	2846	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2847	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	2848	do
<>	144:ef7eb2e8f9f7	2849	{
<>	154:37f96f9d4de2	2850	if(count-- == 0U)
<>	154:37f96f9d4de2	2851	{
<>	154:37f96f9d4de2	2852	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2853	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	2854
<>	154:37f96f9d4de2	2855	/* Process Unlocked */
<>	154:37f96f9d4de2	2856	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2857
<>	154:37f96f9d4de2	2858	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	2859	}
<>	144:ef7eb2e8f9f7	2860	}
<>	154:37f96f9d4de2	2861	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2862
<>	144:ef7eb2e8f9f7	2863	/* Process Locked */
<>	144:ef7eb2e8f9f7	2864	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2865
<>	154:37f96f9d4de2	2866	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2867	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2868	{
<>	154:37f96f9d4de2	2869	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2870	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2871	}
<>	154:37f96f9d4de2	2872
<>	144:ef7eb2e8f9f7	2873	/* Disable Pos */
<>	154:37f96f9d4de2	2874	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2875
<>	144:ef7eb2e8f9f7	2876	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	144:ef7eb2e8f9f7	2877	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2878	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2879
<>	154:37f96f9d4de2	2880	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2881	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2882	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2883	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2884	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2885	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	2886	hi2c->Memaddress = MemAddress;
<>	154:37f96f9d4de2	2887	hi2c->MemaddSize = MemAddSize;
<>	154:37f96f9d4de2	2888	hi2c->EventCount = 0U;
<>	154:37f96f9d4de2	2889
<>	154:37f96f9d4de2	2890	/* Generate Start */
<>	154:37f96f9d4de2	2891	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2892
<>	144:ef7eb2e8f9f7	2893	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2894	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2895
<>	144:ef7eb2e8f9f7	2896	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2897	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2898	process unlock */
<>	144:ef7eb2e8f9f7	2899
<>	144:ef7eb2e8f9f7	2900	/* Enable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	2901	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	2902
<>	144:ef7eb2e8f9f7	2903	return HAL_OK;
<>	144:ef7eb2e8f9f7	2904	}
<>	144:ef7eb2e8f9f7	2905	else
<>	144:ef7eb2e8f9f7	2906	{
<>	144:ef7eb2e8f9f7	2907	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2908	}
<>	144:ef7eb2e8f9f7	2909	}
<>	144:ef7eb2e8f9f7	2910
<>	144:ef7eb2e8f9f7	2911	/**
<>	144:ef7eb2e8f9f7	2912	* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
<>	144:ef7eb2e8f9f7	2913	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	2914	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	2915	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	2916	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	2917	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	2918	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	2919	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	2920	* @retval HAL status
<>	144:ef7eb2e8f9f7	2921	*/
<>	144:ef7eb2e8f9f7	2922	HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	2923	{
<>	154:37f96f9d4de2	2924	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	2925
<>	144:ef7eb2e8f9f7	2926	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2927	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	2928
<>	144:ef7eb2e8f9f7	2929	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	2930	{
<>	154:37f96f9d4de2	2931	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	2932	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	2933	do
<>	144:ef7eb2e8f9f7	2934	{
<>	154:37f96f9d4de2	2935	if(count-- == 0U)
<>	154:37f96f9d4de2	2936	{
<>	154:37f96f9d4de2	2937	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	2938	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	2939
<>	154:37f96f9d4de2	2940	/* Process Unlocked */
<>	154:37f96f9d4de2	2941	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	2942
<>	154:37f96f9d4de2	2943	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	2944	}
<>	144:ef7eb2e8f9f7	2945	}
<>	154:37f96f9d4de2	2946	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	2947
<>	144:ef7eb2e8f9f7	2948	/* Process Locked */
<>	144:ef7eb2e8f9f7	2949	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	2950
<>	154:37f96f9d4de2	2951	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	2952	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	2953	{
<>	154:37f96f9d4de2	2954	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	2955	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	2956	}
<>	154:37f96f9d4de2	2957
<>	144:ef7eb2e8f9f7	2958	/* Disable Pos */
<>	154:37f96f9d4de2	2959	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	2960
<>	144:ef7eb2e8f9f7	2961	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	144:ef7eb2e8f9f7	2962	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	2963	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	2964
<>	154:37f96f9d4de2	2965	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	2966	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	2967	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	2968	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	2969	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	2970	hi2c->Devaddress = DevAddress;
<>	154:37f96f9d4de2	2971	hi2c->Memaddress = MemAddress;
<>	154:37f96f9d4de2	2972	hi2c->MemaddSize = MemAddSize;
<>	154:37f96f9d4de2	2973	hi2c->EventCount = 0U;
<>	154:37f96f9d4de2	2974
<>	154:37f96f9d4de2	2975	/* Enable Acknowledge */
<>	154:37f96f9d4de2	2976	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	2977
<>	154:37f96f9d4de2	2978	/* Generate Start */
<>	154:37f96f9d4de2	2979	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	2980
<>	144:ef7eb2e8f9f7	2981	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	2982	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	2983
<>	154:37f96f9d4de2	2984	if(hi2c->XferSize > 0U)
<>	154:37f96f9d4de2	2985	{
<>	154:37f96f9d4de2	2986	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	2987	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	2988	process unlock */
<>	154:37f96f9d4de2	2989
<>	154:37f96f9d4de2	2990	/* Enable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	2991	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	2992	}
<>	144:ef7eb2e8f9f7	2993	return HAL_OK;
<>	144:ef7eb2e8f9f7	2994	}
<>	144:ef7eb2e8f9f7	2995	else
<>	144:ef7eb2e8f9f7	2996	{
<>	144:ef7eb2e8f9f7	2997	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	2998	}
<>	144:ef7eb2e8f9f7	2999	}
<>	144:ef7eb2e8f9f7	3000
<>	144:ef7eb2e8f9f7	3001	/**
<>	144:ef7eb2e8f9f7	3002	* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
<>	144:ef7eb2e8f9f7	3003	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3004	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3005	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3006	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3007	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3008	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	3009	* @param Size Amount of data to be sent
<>	144:ef7eb2e8f9f7	3010	* @retval HAL status
<>	144:ef7eb2e8f9f7	3011	*/
<>	144:ef7eb2e8f9f7	3012	HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	3013	{
<>	154:37f96f9d4de2	3014	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	3015
<>	154:37f96f9d4de2	3016	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	3017
<>	154:37f96f9d4de2	3018	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	3019	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	3020
<>	144:ef7eb2e8f9f7	3021	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3022	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	3023
<>	144:ef7eb2e8f9f7	3024	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3025	{
<>	154:37f96f9d4de2	3026	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	3027	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	3028	do
<>	144:ef7eb2e8f9f7	3029	{
<>	154:37f96f9d4de2	3030	if(count-- == 0U)
<>	154:37f96f9d4de2	3031	{
<>	154:37f96f9d4de2	3032	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	3033	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3034
<>	154:37f96f9d4de2	3035	/* Process Unlocked */
<>	154:37f96f9d4de2	3036	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3037
<>	154:37f96f9d4de2	3038	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	3039	}
<>	144:ef7eb2e8f9f7	3040	}
<>	154:37f96f9d4de2	3041	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	3042
<>	144:ef7eb2e8f9f7	3043	/* Process Locked */
<>	144:ef7eb2e8f9f7	3044	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3045
<>	154:37f96f9d4de2	3046	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	3047	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	3048	{
<>	154:37f96f9d4de2	3049	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	3050	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	3051	}
<>	154:37f96f9d4de2	3052
<>	144:ef7eb2e8f9f7	3053	/* Disable Pos */
<>	154:37f96f9d4de2	3054	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	3055
<>	154:37f96f9d4de2	3056	hi2c->State = HAL_I2C_STATE_BUSY_TX;
<>	154:37f96f9d4de2	3057	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	3058	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3059
<>	154:37f96f9d4de2	3060	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	3061	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	3062	hi2c->XferSize = Size;
<>	144:ef7eb2e8f9f7	3063	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	3064	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	3065
<>	154:37f96f9d4de2	3066	if(hi2c->XferSize > 0U)
<>	154:37f96f9d4de2	3067	{
<>	154:37f96f9d4de2	3068	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	3069	hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	3070
<>	154:37f96f9d4de2	3071	/* Set the DMA error callback */
<>	154:37f96f9d4de2	3072	hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	3073
<>	154:37f96f9d4de2	3074	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	3075	hi2c->hdmatx->XferHalfCpltCallback = NULL;
<>	154:37f96f9d4de2	3076	hi2c->hdmatx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	3077
<>	154:37f96f9d4de2	3078	/* Enable the DMA channel */
<>	154:37f96f9d4de2	3079	HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize);
<>	154:37f96f9d4de2	3080
<>	154:37f96f9d4de2	3081	/* Send Slave Address and Memory Address */
<>	154:37f96f9d4de2	3082	if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3083	{
<>	154:37f96f9d4de2	3084	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	154:37f96f9d4de2	3085	{
<>	154:37f96f9d4de2	3086	/* Process Unlocked */
<>	154:37f96f9d4de2	3087	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3088	return HAL_ERROR;
<>	154:37f96f9d4de2	3089	}
<>	154:37f96f9d4de2	3090	else
<>	154:37f96f9d4de2	3091	{
<>	154:37f96f9d4de2	3092	/* Process Unlocked */
<>	154:37f96f9d4de2	3093	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3094	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	3095	}
<>	144:ef7eb2e8f9f7	3096	}
<>	154:37f96f9d4de2	3097
<>	154:37f96f9d4de2	3098	/* Clear ADDR flag */
<>	154:37f96f9d4de2	3099	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	3100
<>	154:37f96f9d4de2	3101	/* Process Unlocked */
<>	154:37f96f9d4de2	3102	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3103
<>	154:37f96f9d4de2	3104	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	3105	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	3106	process unlock */
<>	154:37f96f9d4de2	3107	/* Enable ERR interrupt */
<>	154:37f96f9d4de2	3108	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	154:37f96f9d4de2	3109
<>	154:37f96f9d4de2	3110	/* Enable DMA Request */
<>	154:37f96f9d4de2	3111	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3112	}
<>	144:ef7eb2e8f9f7	3113	return HAL_OK;
<>	144:ef7eb2e8f9f7	3114	}
<>	144:ef7eb2e8f9f7	3115	else
<>	144:ef7eb2e8f9f7	3116	{
<>	144:ef7eb2e8f9f7	3117	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3118	}
<>	144:ef7eb2e8f9f7	3119	}
<>	144:ef7eb2e8f9f7	3120
<>	144:ef7eb2e8f9f7	3121	/**
<>	144:ef7eb2e8f9f7	3122	* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
<>	144:ef7eb2e8f9f7	3123	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3124	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3125	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3126	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	3127	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	3128	* @param pData Pointer to data buffer
<>	144:ef7eb2e8f9f7	3129	* @param Size Amount of data to be read
<>	144:ef7eb2e8f9f7	3130	* @retval HAL status
<>	144:ef7eb2e8f9f7	3131	*/
<>	144:ef7eb2e8f9f7	3132	HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t pData, uint16_t Size)
<>	144:ef7eb2e8f9f7	3133	{
<>	154:37f96f9d4de2	3134	uint32_t tickstart = 0x00U;
<>	154:37f96f9d4de2	3135
<>	154:37f96f9d4de2	3136	/* Init tickstart for timeout management*/
<>	154:37f96f9d4de2	3137	tickstart = HAL_GetTick();
<>	154:37f96f9d4de2	3138
<>	154:37f96f9d4de2	3139	__IO uint32_t count = 0U;
<>	154:37f96f9d4de2	3140
<>	144:ef7eb2e8f9f7	3141	/* Check the parameters */
<>	144:ef7eb2e8f9f7	3142	assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
<>	144:ef7eb2e8f9f7	3143
<>	144:ef7eb2e8f9f7	3144	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3145	{
<>	154:37f96f9d4de2	3146	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	3147	count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock /25U /1000U);
<>	154:37f96f9d4de2	3148	do
<>	144:ef7eb2e8f9f7	3149	{
<>	154:37f96f9d4de2	3150	if(count-- == 0U)
<>	154:37f96f9d4de2	3151	{
<>	154:37f96f9d4de2	3152	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	3153	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3154
<>	154:37f96f9d4de2	3155	/* Process Unlocked */
<>	154:37f96f9d4de2	3156	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3157
<>	154:37f96f9d4de2	3158	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	3159	}
<>	144:ef7eb2e8f9f7	3160	}
<>	154:37f96f9d4de2	3161	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET);
<>	144:ef7eb2e8f9f7	3162
<>	144:ef7eb2e8f9f7	3163	/* Process Locked */
<>	144:ef7eb2e8f9f7	3164	__HAL_LOCK(hi2c);
<>	144:ef7eb2e8f9f7	3165
<>	154:37f96f9d4de2	3166	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	3167	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	3168	{
<>	154:37f96f9d4de2	3169	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	3170	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	3171	}
<>	154:37f96f9d4de2	3172
<>	144:ef7eb2e8f9f7	3173	/* Disable Pos */
<>	154:37f96f9d4de2	3174	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	3175
<>	154:37f96f9d4de2	3176	hi2c->State = HAL_I2C_STATE_BUSY_RX;
<>	154:37f96f9d4de2	3177	hi2c->Mode = HAL_I2C_MODE_MEM;
<>	144:ef7eb2e8f9f7	3178	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	144:ef7eb2e8f9f7	3179
<>	154:37f96f9d4de2	3180	/* Prepare transfer parameters */
<>	144:ef7eb2e8f9f7	3181	hi2c->pBuffPtr = pData;
<>	144:ef7eb2e8f9f7	3182	hi2c->XferCount = Size;
<>	154:37f96f9d4de2	3183	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	3184	hi2c->XferSize = hi2c->XferCount;
<>	154:37f96f9d4de2	3185
<>	154:37f96f9d4de2	3186	if(hi2c->XferSize > 0U)
<>	144:ef7eb2e8f9f7	3187	{
<>	154:37f96f9d4de2	3188	/* Set the I2C DMA transfer complete callback */
<>	154:37f96f9d4de2	3189	hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt;
<>	154:37f96f9d4de2	3190
<>	154:37f96f9d4de2	3191	/* Set the DMA error callback */
<>	154:37f96f9d4de2	3192	hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
<>	154:37f96f9d4de2	3193
<>	154:37f96f9d4de2	3194	/* Set the unused DMA callbacks to NULL */
<>	154:37f96f9d4de2	3195	hi2c->hdmarx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	3196
<>	154:37f96f9d4de2	3197	/* Enable the DMA channel */
<>	154:37f96f9d4de2	3198	HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
<>	154:37f96f9d4de2	3199
<>	154:37f96f9d4de2	3200	/* Send Slave Address and Memory Address */
<>	154:37f96f9d4de2	3201	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3202	{
<>	154:37f96f9d4de2	3203	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	154:37f96f9d4de2	3204	{
<>	154:37f96f9d4de2	3205	/* Process Unlocked */
<>	154:37f96f9d4de2	3206	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3207	return HAL_ERROR;
<>	154:37f96f9d4de2	3208	}
<>	154:37f96f9d4de2	3209	else
<>	154:37f96f9d4de2	3210	{
<>	154:37f96f9d4de2	3211	/* Process Unlocked */
<>	154:37f96f9d4de2	3212	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3213	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	3214	}
<>	154:37f96f9d4de2	3215	}
<>	154:37f96f9d4de2	3216
<>	154:37f96f9d4de2	3217	if(Size == 1U)
<>	154:37f96f9d4de2	3218	{
<>	154:37f96f9d4de2	3219	/* Disable Acknowledge */
<>	154:37f96f9d4de2	3220	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	3221	}
<>	144:ef7eb2e8f9f7	3222	else
<>	144:ef7eb2e8f9f7	3223	{
<>	154:37f96f9d4de2	3224	/* Enable Last DMA bit */
<>	154:37f96f9d4de2	3225	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	144:ef7eb2e8f9f7	3226	}
<>	154:37f96f9d4de2	3227
<>	154:37f96f9d4de2	3228	/* Clear ADDR flag */
<>	154:37f96f9d4de2	3229	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	3230
<>	154:37f96f9d4de2	3231	/* Process Unlocked */
<>	154:37f96f9d4de2	3232	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3233
<>	154:37f96f9d4de2	3234	/* Note : The I2C interrupts must be enabled after unlocking current process
<>	154:37f96f9d4de2	3235	to avoid the risk of I2C interrupt handle execution before current
<>	154:37f96f9d4de2	3236	process unlock */
<>	154:37f96f9d4de2	3237	/* Enable ERR interrupt */
<>	154:37f96f9d4de2	3238	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR);
<>	154:37f96f9d4de2	3239
<>	154:37f96f9d4de2	3240	/* Enable DMA Request */
<>	154:37f96f9d4de2	3241	hi2c->Instance->CR2 \|= I2C_CR2_DMAEN;
<>	144:ef7eb2e8f9f7	3242	}
<>	144:ef7eb2e8f9f7	3243	else
<>	144:ef7eb2e8f9f7	3244	{
<>	154:37f96f9d4de2	3245	/* Send Slave Address and Memory Address */
<>	154:37f96f9d4de2	3246	if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
<>	154:37f96f9d4de2	3247	{
<>	154:37f96f9d4de2	3248	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	154:37f96f9d4de2	3249	{
<>	154:37f96f9d4de2	3250	/* Process Unlocked */
<>	154:37f96f9d4de2	3251	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3252	return HAL_ERROR;
<>	154:37f96f9d4de2	3253	}
<>	154:37f96f9d4de2	3254	else
<>	154:37f96f9d4de2	3255	{
<>	154:37f96f9d4de2	3256	/* Process Unlocked */
<>	154:37f96f9d4de2	3257	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	3258	return HAL_TIMEOUT;
<>	154:37f96f9d4de2	3259	}
<>	154:37f96f9d4de2	3260	}
<>	154:37f96f9d4de2	3261
<>	154:37f96f9d4de2	3262	/* Clear ADDR flag */
<>	154:37f96f9d4de2	3263	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	3264
<>	154:37f96f9d4de2	3265	/* Generate Stop */
<>	154:37f96f9d4de2	3266	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	3267
<>	154:37f96f9d4de2	3268	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3269
<>	154:37f96f9d4de2	3270	/* Process Unlocked */
<>	154:37f96f9d4de2	3271	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3272	}
<>	144:ef7eb2e8f9f7	3273
<>	144:ef7eb2e8f9f7	3274	return HAL_OK;
<>	144:ef7eb2e8f9f7	3275	}
<>	144:ef7eb2e8f9f7	3276	else
<>	144:ef7eb2e8f9f7	3277	{
<>	144:ef7eb2e8f9f7	3278	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3279	}
<>	144:ef7eb2e8f9f7	3280	}
<>	144:ef7eb2e8f9f7	3281
<>	144:ef7eb2e8f9f7	3282	/**
<>	144:ef7eb2e8f9f7	3283	* @brief Checks if target device is ready for communication.
<>	144:ef7eb2e8f9f7	3284	* @note This function is used with Memory devices
<>	144:ef7eb2e8f9f7	3285	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3286	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3287	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	3288	* @param Trials Number of trials
<>	144:ef7eb2e8f9f7	3289	* @param Timeout Timeout duration
<>	144:ef7eb2e8f9f7	3290	* @retval HAL status
<>	144:ef7eb2e8f9f7	3291	*/
<>	144:ef7eb2e8f9f7	3292	HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
<>	144:ef7eb2e8f9f7	3293	{
<>	154:37f96f9d4de2	3294	uint32_t tickstart = 0U, tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, I2C_Trials = 1U;
<>	154:37f96f9d4de2	3295
<>	154:37f96f9d4de2	3296	/* Get tick */
<>	154:37f96f9d4de2	3297	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3298
<>	144:ef7eb2e8f9f7	3299	if(hi2c->State == HAL_I2C_STATE_READY)
<>	144:ef7eb2e8f9f7	3300	{
<>	144:ef7eb2e8f9f7	3301	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	3302	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3303	{
<>	144:ef7eb2e8f9f7	3304	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3305	}
<>	144:ef7eb2e8f9f7	3306
<>	144:ef7eb2e8f9f7	3307	/* Process Locked */
<>	144:ef7eb2e8f9f7	3308	__HAL_LOCK(hi2c);
<>	154:37f96f9d4de2	3309
<>	154:37f96f9d4de2	3310	/* Check if the I2C is already enabled */
<>	154:37f96f9d4de2	3311	if((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
<>	154:37f96f9d4de2	3312	{
<>	154:37f96f9d4de2	3313	/* Enable I2C peripheral */
<>	154:37f96f9d4de2	3314	__HAL_I2C_ENABLE(hi2c);
<>	154:37f96f9d4de2	3315	}
<>	144:ef7eb2e8f9f7	3316
<>	144:ef7eb2e8f9f7	3317	/* Disable Pos */
<>	154:37f96f9d4de2	3318	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	144:ef7eb2e8f9f7	3319
<>	144:ef7eb2e8f9f7	3320	hi2c->State = HAL_I2C_STATE_BUSY;
<>	144:ef7eb2e8f9f7	3321	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	3322	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	3323
<>	144:ef7eb2e8f9f7	3324	do
<>	144:ef7eb2e8f9f7	3325	{
<>	144:ef7eb2e8f9f7	3326	/* Generate Start */
<>	154:37f96f9d4de2	3327	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	3328
<>	144:ef7eb2e8f9f7	3329	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	3330	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3331	{
<>	144:ef7eb2e8f9f7	3332	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3333	}
<>	144:ef7eb2e8f9f7	3334
<>	144:ef7eb2e8f9f7	3335	/* Send slave address */
<>	144:ef7eb2e8f9f7	3336	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	154:37f96f9d4de2	3337
<>	144:ef7eb2e8f9f7	3338	/* Wait until ADDR or AF flag are set */
<>	144:ef7eb2e8f9f7	3339	/* Get tick */
<>	144:ef7eb2e8f9f7	3340	tickstart = HAL_GetTick();
<>	144:ef7eb2e8f9f7	3341
<>	144:ef7eb2e8f9f7	3342	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3343	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3344	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3345	while((tmp1 == RESET) && (tmp2 == RESET) && (tmp3 != HAL_I2C_STATE_TIMEOUT))
<>	144:ef7eb2e8f9f7	3346	{
<>	154:37f96f9d4de2	3347	if((Timeout == 0U)\|\|((HAL_GetTick() - tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	3348	{
<>	144:ef7eb2e8f9f7	3349	hi2c->State = HAL_I2C_STATE_TIMEOUT;
<>	144:ef7eb2e8f9f7	3350	}
<>	144:ef7eb2e8f9f7	3351	tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
<>	144:ef7eb2e8f9f7	3352	tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3353	tmp3 = hi2c->State;
<>	144:ef7eb2e8f9f7	3354	}
<>	144:ef7eb2e8f9f7	3355
<>	144:ef7eb2e8f9f7	3356	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3357
<>	144:ef7eb2e8f9f7	3358	/* Check if the ADDR flag has been set */
<>	144:ef7eb2e8f9f7	3359	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
<>	144:ef7eb2e8f9f7	3360	{
<>	144:ef7eb2e8f9f7	3361	/* Generate Stop */
<>	154:37f96f9d4de2	3362	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3363
<>	144:ef7eb2e8f9f7	3364	/* Clear ADDR Flag */
<>	144:ef7eb2e8f9f7	3365	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	3366
<>	144:ef7eb2e8f9f7	3367	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	3368	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3369	{
<>	144:ef7eb2e8f9f7	3370	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3371	}
<>	144:ef7eb2e8f9f7	3372
<>	144:ef7eb2e8f9f7	3373	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3374
<>	144:ef7eb2e8f9f7	3375	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3376	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3377
<>	144:ef7eb2e8f9f7	3378	return HAL_OK;
<>	144:ef7eb2e8f9f7	3379	}
<>	144:ef7eb2e8f9f7	3380	else
<>	144:ef7eb2e8f9f7	3381	{
<>	144:ef7eb2e8f9f7	3382	/* Generate Stop */
<>	154:37f96f9d4de2	3383	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	3384
<>	144:ef7eb2e8f9f7	3385	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	3386	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3387
<>	144:ef7eb2e8f9f7	3388	/* Wait until BUSY flag is reset */
<>	154:37f96f9d4de2	3389	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	3390	{
<>	144:ef7eb2e8f9f7	3391	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	3392	}
<>	144:ef7eb2e8f9f7	3393	}
<>	144:ef7eb2e8f9f7	3394	}while(I2C_Trials++ < Trials);
<>	144:ef7eb2e8f9f7	3395
<>	144:ef7eb2e8f9f7	3396	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	3397
<>	144:ef7eb2e8f9f7	3398	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	3399	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	3400
<>	144:ef7eb2e8f9f7	3401	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	3402	}
<>	144:ef7eb2e8f9f7	3403	else
<>	144:ef7eb2e8f9f7	3404	{
<>	144:ef7eb2e8f9f7	3405	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	3406	}
<>	144:ef7eb2e8f9f7	3407	}
<>	144:ef7eb2e8f9f7	3408
<>	144:ef7eb2e8f9f7	3409	/**
<>	144:ef7eb2e8f9f7	3410	* @brief This function handles I2C event interrupt request.
<>	144:ef7eb2e8f9f7	3411	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3412	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3413	* @retval None
<>	144:ef7eb2e8f9f7	3414	*/
<>	144:ef7eb2e8f9f7	3415	void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3416	{
<>	154:37f96f9d4de2	3417	uint32_t sr2itflags = READ_REG(hi2c->Instance->SR2);
<>	154:37f96f9d4de2	3418	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	154:37f96f9d4de2	3419	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	154:37f96f9d4de2	3420
<>	154:37f96f9d4de2	3421	uint32_t CurrentMode = hi2c->Mode;
<>	154:37f96f9d4de2	3422
<>	144:ef7eb2e8f9f7	3423	/* Master or Memory mode selected */
<>	154:37f96f9d4de2	3424	if((CurrentMode == HAL_I2C_MODE_MASTER) \|\| (CurrentMode == HAL_I2C_MODE_MEM))
<>	144:ef7eb2e8f9f7	3425	{
<>	154:37f96f9d4de2	3426	/* SB Set ----------------------------------------------------------------*/
<>	154:37f96f9d4de2	3427	if(((sr1itflags & I2C_FLAG_SB) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	154:37f96f9d4de2	3428	{
<>	154:37f96f9d4de2	3429	I2C_Master_SB(hi2c);
<>	154:37f96f9d4de2	3430	}
<>	154:37f96f9d4de2	3431	/* ADD10 Set -------------------------------------------------------------*/
<>	154:37f96f9d4de2	3432	else if(((sr1itflags & I2C_FLAG_ADD10) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	154:37f96f9d4de2	3433	{
<>	154:37f96f9d4de2	3434	I2C_Master_ADD10(hi2c);
<>	154:37f96f9d4de2	3435	}
<>	154:37f96f9d4de2	3436	/* ADDR Set --------------------------------------------------------------*/
<>	154:37f96f9d4de2	3437	else if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	154:37f96f9d4de2	3438	{
<>	154:37f96f9d4de2	3439	I2C_Master_ADDR(hi2c);
<>	154:37f96f9d4de2	3440	}
<>	154:37f96f9d4de2	3441
<>	144:ef7eb2e8f9f7	3442	/* I2C in mode Transmitter -----------------------------------------------*/
<>	154:37f96f9d4de2	3443	if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3444	{
<>	144:ef7eb2e8f9f7	3445	/* TXE set and BTF reset -----------------------------------------------*/
<>	154:37f96f9d4de2	3446	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3447	{
<>	144:ef7eb2e8f9f7	3448	I2C_MasterTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3449	}
<>	144:ef7eb2e8f9f7	3450	/* BTF set -------------------------------------------------------------*/
<>	154:37f96f9d4de2	3451	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3452	{
<>	144:ef7eb2e8f9f7	3453	I2C_MasterTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3454	}
<>	144:ef7eb2e8f9f7	3455	}
<>	144:ef7eb2e8f9f7	3456	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3457	else
<>	144:ef7eb2e8f9f7	3458	{
<>	144:ef7eb2e8f9f7	3459	/* RXNE set and BTF reset -----------------------------------------------*/
<>	154:37f96f9d4de2	3460	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3461	{
<>	144:ef7eb2e8f9f7	3462	I2C_MasterReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3463	}
<>	144:ef7eb2e8f9f7	3464	/* BTF set -------------------------------------------------------------*/
<>	154:37f96f9d4de2	3465	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3466	{
<>	144:ef7eb2e8f9f7	3467	I2C_MasterReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3468	}
<>	144:ef7eb2e8f9f7	3469	}
<>	144:ef7eb2e8f9f7	3470	}
<>	144:ef7eb2e8f9f7	3471	/* Slave mode selected */
<>	144:ef7eb2e8f9f7	3472	else
<>	144:ef7eb2e8f9f7	3473	{
<>	144:ef7eb2e8f9f7	3474	/* ADDR set --------------------------------------------------------------*/
<>	154:37f96f9d4de2	3475	if(((sr1itflags & I2C_FLAG_ADDR) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3476	{
<>	144:ef7eb2e8f9f7	3477	I2C_Slave_ADDR(hi2c);
<>	144:ef7eb2e8f9f7	3478	}
<>	144:ef7eb2e8f9f7	3479	/* STOPF set --------------------------------------------------------------*/
<>	154:37f96f9d4de2	3480	else if(((sr1itflags & I2C_FLAG_STOPF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3481	{
<>	144:ef7eb2e8f9f7	3482	I2C_Slave_STOPF(hi2c);
<>	144:ef7eb2e8f9f7	3483	}
<>	144:ef7eb2e8f9f7	3484	/* I2C in mode Transmitter -----------------------------------------------*/
<>	154:37f96f9d4de2	3485	else if((sr2itflags & I2C_FLAG_TRA) != RESET)
<>	144:ef7eb2e8f9f7	3486	{
<>	144:ef7eb2e8f9f7	3487	/* TXE set and BTF reset -----------------------------------------------*/
<>	154:37f96f9d4de2	3488	if(((sr1itflags & I2C_FLAG_TXE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3489	{
<>	144:ef7eb2e8f9f7	3490	I2C_SlaveTransmit_TXE(hi2c);
<>	144:ef7eb2e8f9f7	3491	}
<>	144:ef7eb2e8f9f7	3492	/* BTF set -------------------------------------------------------------*/
<>	154:37f96f9d4de2	3493	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3494	{
<>	144:ef7eb2e8f9f7	3495	I2C_SlaveTransmit_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3496	}
<>	144:ef7eb2e8f9f7	3497	}
<>	144:ef7eb2e8f9f7	3498	/* I2C in mode Receiver --------------------------------------------------*/
<>	144:ef7eb2e8f9f7	3499	else
<>	144:ef7eb2e8f9f7	3500	{
<>	144:ef7eb2e8f9f7	3501	/* RXNE set and BTF reset ----------------------------------------------*/
<>	154:37f96f9d4de2	3502	if(((sr1itflags & I2C_FLAG_RXNE) != RESET) && ((itsources & I2C_IT_BUF) != RESET) && ((sr1itflags & I2C_FLAG_BTF) == RESET))
<>	144:ef7eb2e8f9f7	3503	{
<>	144:ef7eb2e8f9f7	3504	I2C_SlaveReceive_RXNE(hi2c);
<>	144:ef7eb2e8f9f7	3505	}
<>	144:ef7eb2e8f9f7	3506	/* BTF set -------------------------------------------------------------*/
<>	154:37f96f9d4de2	3507	else if(((sr1itflags & I2C_FLAG_BTF) != RESET) && ((itsources & I2C_IT_EVT) != RESET))
<>	144:ef7eb2e8f9f7	3508	{
<>	144:ef7eb2e8f9f7	3509	I2C_SlaveReceive_BTF(hi2c);
<>	144:ef7eb2e8f9f7	3510	}
<>	144:ef7eb2e8f9f7	3511	}
<>	144:ef7eb2e8f9f7	3512	}
<>	144:ef7eb2e8f9f7	3513	}
<>	144:ef7eb2e8f9f7	3514
<>	144:ef7eb2e8f9f7	3515	/**
<>	144:ef7eb2e8f9f7	3516	* @brief This function handles I2C error interrupt request.
<>	154:37f96f9d4de2	3517	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3518	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	3519	* @retval None
<>	144:ef7eb2e8f9f7	3520	*/
<>	144:ef7eb2e8f9f7	3521	void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3522	{
<>	154:37f96f9d4de2	3523	uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U, tmp4 = 0U;
<>	154:37f96f9d4de2	3524	uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1);
<>	154:37f96f9d4de2	3525	uint32_t itsources = READ_REG(hi2c->Instance->CR2);
<>	154:37f96f9d4de2	3526
<>	144:ef7eb2e8f9f7	3527	/* I2C Bus error interrupt occurred ----------------------------------------*/
<>	154:37f96f9d4de2	3528	if(((sr1itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3529	{
<>	144:ef7eb2e8f9f7	3530	hi2c->ErrorCode \|= HAL_I2C_ERROR_BERR;
<>	144:ef7eb2e8f9f7	3531
<>	144:ef7eb2e8f9f7	3532	/* Clear BERR flag */
<>	144:ef7eb2e8f9f7	3533	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
<>	154:37f96f9d4de2	3534
<>	144:ef7eb2e8f9f7	3535	/* Workaround: Start cannot be generated after a misplaced Stop */
<>	144:ef7eb2e8f9f7	3536	SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST);
<>	144:ef7eb2e8f9f7	3537	}
<>	144:ef7eb2e8f9f7	3538
<>	144:ef7eb2e8f9f7	3539	/* I2C Arbitration Loss error interrupt occurred ---------------------------*/
<>	154:37f96f9d4de2	3540	if(((sr1itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3541	{
<>	144:ef7eb2e8f9f7	3542	hi2c->ErrorCode \|= HAL_I2C_ERROR_ARLO;
<>	144:ef7eb2e8f9f7	3543
<>	144:ef7eb2e8f9f7	3544	/* Clear ARLO flag */
<>	144:ef7eb2e8f9f7	3545	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
<>	144:ef7eb2e8f9f7	3546	}
<>	144:ef7eb2e8f9f7	3547
<>	144:ef7eb2e8f9f7	3548	/* I2C Acknowledge failure error interrupt occurred ------------------------*/
<>	154:37f96f9d4de2	3549	if(((sr1itflags & I2C_FLAG_AF) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3550	{
<>	144:ef7eb2e8f9f7	3551	tmp1 = hi2c->Mode;
<>	144:ef7eb2e8f9f7	3552	tmp2 = hi2c->XferCount;
<>	144:ef7eb2e8f9f7	3553	tmp3 = hi2c->State;
<>	154:37f96f9d4de2	3554	tmp4 = hi2c->PreviousState;
<>	154:37f96f9d4de2	3555	if((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \
<>	154:37f96f9d4de2	3556	((tmp3 == HAL_I2C_STATE_BUSY_TX) \|\| (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| \
<>	154:37f96f9d4de2	3557	((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX))))
<>	144:ef7eb2e8f9f7	3558	{
<>	144:ef7eb2e8f9f7	3559	I2C_Slave_AF(hi2c);
<>	144:ef7eb2e8f9f7	3560	}
<>	144:ef7eb2e8f9f7	3561	else
<>	144:ef7eb2e8f9f7	3562	{
<>	144:ef7eb2e8f9f7	3563	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	154:37f96f9d4de2	3564
<>	154:37f96f9d4de2	3565	/* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */
<>	154:37f96f9d4de2	3566	if(hi2c->Mode == HAL_I2C_MODE_MASTER)
<>	154:37f96f9d4de2	3567	{
<>	154:37f96f9d4de2	3568	/* Generate Stop */
<>	154:37f96f9d4de2	3569	SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
<>	154:37f96f9d4de2	3570	}
<>	154:37f96f9d4de2	3571
<>	144:ef7eb2e8f9f7	3572	/* Clear AF flag */
<>	144:ef7eb2e8f9f7	3573	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	3574	}
<>	144:ef7eb2e8f9f7	3575	}
<>	144:ef7eb2e8f9f7	3576
<>	144:ef7eb2e8f9f7	3577	/* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
<>	154:37f96f9d4de2	3578	if(((sr1itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERR) != RESET))
<>	144:ef7eb2e8f9f7	3579	{
<>	144:ef7eb2e8f9f7	3580	hi2c->ErrorCode \|= HAL_I2C_ERROR_OVR;
<>	144:ef7eb2e8f9f7	3581	/* Clear OVR flag */
<>	144:ef7eb2e8f9f7	3582	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
<>	144:ef7eb2e8f9f7	3583	}
<>	144:ef7eb2e8f9f7	3584
<>	154:37f96f9d4de2	3585	/* Call the Error Callback in case of Error detected -----------------------*/
<>	144:ef7eb2e8f9f7	3586	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	3587	{
<>	154:37f96f9d4de2	3588	I2C_ITError(hi2c);
<>	144:ef7eb2e8f9f7	3589	}
<>	144:ef7eb2e8f9f7	3590	}
<>	144:ef7eb2e8f9f7	3591
<>	144:ef7eb2e8f9f7	3592	/**
<>	144:ef7eb2e8f9f7	3593	* @brief Master Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3594	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3595	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3596	* @retval None
<>	144:ef7eb2e8f9f7	3597	*/
<>	154:37f96f9d4de2	3598	__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3599	{
<>	144:ef7eb2e8f9f7	3600	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3601	UNUSED(hi2c);
<>	154:37f96f9d4de2	3602
<>	144:ef7eb2e8f9f7	3603	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3604	the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3605	*/
<>	144:ef7eb2e8f9f7	3606	}
<>	144:ef7eb2e8f9f7	3607
<>	144:ef7eb2e8f9f7	3608	/**
<>	144:ef7eb2e8f9f7	3609	* @brief Master Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3610	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3611	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3612	* @retval None
<>	144:ef7eb2e8f9f7	3613	*/
<>	144:ef7eb2e8f9f7	3614	__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3615	{
<>	144:ef7eb2e8f9f7	3616	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3617	UNUSED(hi2c);
<>	154:37f96f9d4de2	3618
<>	144:ef7eb2e8f9f7	3619	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3620	the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3621	*/
<>	144:ef7eb2e8f9f7	3622	}
<>	144:ef7eb2e8f9f7	3623
<>	144:ef7eb2e8f9f7	3624	/** @brief Slave Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3625	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3626	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3627	* @retval None
<>	144:ef7eb2e8f9f7	3628	*/
<>	154:37f96f9d4de2	3629	__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3630	{
<>	144:ef7eb2e8f9f7	3631	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3632	UNUSED(hi2c);
<>	154:37f96f9d4de2	3633
<>	144:ef7eb2e8f9f7	3634	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3635	the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3636	*/
<>	144:ef7eb2e8f9f7	3637	}
<>	144:ef7eb2e8f9f7	3638
<>	144:ef7eb2e8f9f7	3639	/**
<>	144:ef7eb2e8f9f7	3640	* @brief Slave Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3641	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3642	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3643	* @retval None
<>	144:ef7eb2e8f9f7	3644	*/
<>	144:ef7eb2e8f9f7	3645	__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3646	{
<>	144:ef7eb2e8f9f7	3647	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3648	UNUSED(hi2c);
<>	154:37f96f9d4de2	3649
<>	144:ef7eb2e8f9f7	3650	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3651	the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
<>	154:37f96f9d4de2	3652	*/
<>	154:37f96f9d4de2	3653	}
<>	154:37f96f9d4de2	3654
<>	154:37f96f9d4de2	3655	/**
<>	154:37f96f9d4de2	3656	* @brief Slave Address Match callback.
<>	154:37f96f9d4de2	3657	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3658	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	3659	* @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferOptions_definition
<>	154:37f96f9d4de2	3660	* @param AddrMatchCode Address Match Code
<>	154:37f96f9d4de2	3661	* @retval None
<>	154:37f96f9d4de2	3662	*/
<>	154:37f96f9d4de2	3663	__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
<>	154:37f96f9d4de2	3664	{
<>	154:37f96f9d4de2	3665	/* Prevent unused argument(s) compilation warning */
<>	154:37f96f9d4de2	3666	UNUSED(hi2c);
<>	154:37f96f9d4de2	3667	UNUSED(TransferDirection);
<>	154:37f96f9d4de2	3668	UNUSED(AddrMatchCode);
<>	154:37f96f9d4de2	3669
<>	154:37f96f9d4de2	3670	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3671	the HAL_I2C_AddrCallback can be implemented in the user file
<>	154:37f96f9d4de2	3672	*/
<>	154:37f96f9d4de2	3673	}
<>	154:37f96f9d4de2	3674
<>	154:37f96f9d4de2	3675	/**
<>	154:37f96f9d4de2	3676	* @brief Listen Complete callback.
<>	154:37f96f9d4de2	3677	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3678	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	3679	* @retval None
<>	154:37f96f9d4de2	3680	*/
<>	154:37f96f9d4de2	3681	__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	3682	{
<>	154:37f96f9d4de2	3683	/* Prevent unused argument(s) compilation warning */
<>	154:37f96f9d4de2	3684	UNUSED(hi2c);
<>	154:37f96f9d4de2	3685
<>	154:37f96f9d4de2	3686	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3687	the HAL_I2C_ListenCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3688	*/
<>	144:ef7eb2e8f9f7	3689	}
<>	144:ef7eb2e8f9f7	3690
<>	144:ef7eb2e8f9f7	3691	/**
<>	144:ef7eb2e8f9f7	3692	* @brief Memory Tx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3693	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3694	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3695	* @retval None
<>	144:ef7eb2e8f9f7	3696	*/
<>	154:37f96f9d4de2	3697	__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3698	{
<>	144:ef7eb2e8f9f7	3699	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3700	UNUSED(hi2c);
<>	154:37f96f9d4de2	3701
<>	144:ef7eb2e8f9f7	3702	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3703	the HAL_I2C_MemTxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3704	*/
<>	144:ef7eb2e8f9f7	3705	}
<>	144:ef7eb2e8f9f7	3706
<>	144:ef7eb2e8f9f7	3707	/**
<>	144:ef7eb2e8f9f7	3708	* @brief Memory Rx Transfer completed callback.
<>	144:ef7eb2e8f9f7	3709	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3710	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3711	* @retval None
<>	144:ef7eb2e8f9f7	3712	*/
<>	144:ef7eb2e8f9f7	3713	__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3714	{
<>	144:ef7eb2e8f9f7	3715	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3716	UNUSED(hi2c);
<>	154:37f96f9d4de2	3717
<>	144:ef7eb2e8f9f7	3718	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3719	the HAL_I2C_MemRxCpltCallback can be implemented in the user file
<>	144:ef7eb2e8f9f7	3720	*/
<>	144:ef7eb2e8f9f7	3721	}
<>	144:ef7eb2e8f9f7	3722
<>	144:ef7eb2e8f9f7	3723	/**
<>	144:ef7eb2e8f9f7	3724	* @brief I2C error callback.
<>	144:ef7eb2e8f9f7	3725	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3726	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3727	* @retval None
<>	144:ef7eb2e8f9f7	3728	*/
<>	154:37f96f9d4de2	3729	__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3730	{
<>	144:ef7eb2e8f9f7	3731	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	3732	UNUSED(hi2c);
<>	154:37f96f9d4de2	3733
<>	144:ef7eb2e8f9f7	3734	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3735	the HAL_I2C_ErrorCallback can be implemented in the user file
<>	154:37f96f9d4de2	3736	*/
<>	154:37f96f9d4de2	3737	}
<>	154:37f96f9d4de2	3738
<>	154:37f96f9d4de2	3739	/**
<>	154:37f96f9d4de2	3740	* @brief I2C abort callback.
<>	154:37f96f9d4de2	3741	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3742	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	3743	* @retval None
<>	154:37f96f9d4de2	3744	*/
<>	154:37f96f9d4de2	3745	__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	3746	{
<>	154:37f96f9d4de2	3747	/* Prevent unused argument(s) compilation warning */
<>	154:37f96f9d4de2	3748	UNUSED(hi2c);
<>	154:37f96f9d4de2	3749
<>	154:37f96f9d4de2	3750	/* NOTE : This function should not be modified, when the callback is needed,
<>	154:37f96f9d4de2	3751	the HAL_I2C_AbortCpltCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	3752	*/
<>	144:ef7eb2e8f9f7	3753	}
<>	144:ef7eb2e8f9f7	3754
<>	144:ef7eb2e8f9f7	3755	/**
<>	144:ef7eb2e8f9f7	3756	* @}
<>	144:ef7eb2e8f9f7	3757	*/
<>	144:ef7eb2e8f9f7	3758
<>	154:37f96f9d4de2	3759	/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
<>	154:37f96f9d4de2	3760	* @brief Peripheral State and Errors functions
<>	154:37f96f9d4de2	3761	*
<>	144:ef7eb2e8f9f7	3762	@verbatim
<>	144:ef7eb2e8f9f7	3763	===============================================================================
<>	154:37f96f9d4de2	3764	##### Peripheral State, Mode and Error functions #####
<>	144:ef7eb2e8f9f7	3765	===============================================================================
<>	144:ef7eb2e8f9f7	3766	[..]
<>	144:ef7eb2e8f9f7	3767	This subsection permits to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	3768	and the data flow.
<>	144:ef7eb2e8f9f7	3769
<>	144:ef7eb2e8f9f7	3770	@endverbatim
<>	144:ef7eb2e8f9f7	3771	* @{
<>	144:ef7eb2e8f9f7	3772	*/
<>	144:ef7eb2e8f9f7	3773
<>	144:ef7eb2e8f9f7	3774	/**
<>	144:ef7eb2e8f9f7	3775	* @brief Return the I2C handle state.
<>	144:ef7eb2e8f9f7	3776	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	3777	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	3778	* @retval HAL state
<>	144:ef7eb2e8f9f7	3779	*/
<>	144:ef7eb2e8f9f7	3780	HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3781	{
<>	144:ef7eb2e8f9f7	3782	/* Return I2C handle state */
<>	144:ef7eb2e8f9f7	3783	return hi2c->State;
<>	144:ef7eb2e8f9f7	3784	}
<>	144:ef7eb2e8f9f7	3785
<>	144:ef7eb2e8f9f7	3786	/**
<>	154:37f96f9d4de2	3787	* @brief Return the I2C Master, Slave, Memory or no mode.
<>	144:ef7eb2e8f9f7	3788	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3789	* the configuration information for I2C module
<>	154:37f96f9d4de2	3790	* @retval HAL mode
<>	154:37f96f9d4de2	3791	*/
<>	154:37f96f9d4de2	3792	HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	3793	{
<>	154:37f96f9d4de2	3794	return hi2c->Mode;
<>	154:37f96f9d4de2	3795	}
<>	154:37f96f9d4de2	3796
<>	154:37f96f9d4de2	3797	/**
<>	154:37f96f9d4de2	3798	* @brief Return the I2C error code
<>	154:37f96f9d4de2	3799	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3800	* the configuration information for the specified I2C.
<>	154:37f96f9d4de2	3801	* @retval I2C Error Code
<>	154:37f96f9d4de2	3802	*/
<>	144:ef7eb2e8f9f7	3803	uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3804	{
<>	144:ef7eb2e8f9f7	3805	return hi2c->ErrorCode;
<>	144:ef7eb2e8f9f7	3806	}
<>	144:ef7eb2e8f9f7	3807
<>	144:ef7eb2e8f9f7	3808	/**
<>	144:ef7eb2e8f9f7	3809	* @}
<>	144:ef7eb2e8f9f7	3810	*/
<>	144:ef7eb2e8f9f7	3811
<>	144:ef7eb2e8f9f7	3812	/**
<>	154:37f96f9d4de2	3813	* @brief Handle TXE flag for Master
<>	144:ef7eb2e8f9f7	3814	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3815	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3816	* @retval HAL status
<>	144:ef7eb2e8f9f7	3817	*/
<>	144:ef7eb2e8f9f7	3818	static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3819	{
<>	154:37f96f9d4de2	3820	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	3821	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	3822	uint32_t CurrentMode = hi2c->Mode;
<>	154:37f96f9d4de2	3823	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	3824
<>	154:37f96f9d4de2	3825	if((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX))
<>	144:ef7eb2e8f9f7	3826	{
<>	154:37f96f9d4de2	3827	/* Call TxCpltCallback() directly if no stop mode is set */
<>	154:37f96f9d4de2	3828	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	3829	{
<>	154:37f96f9d4de2	3830	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	3831
<>	154:37f96f9d4de2	3832	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	154:37f96f9d4de2	3833	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3834	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3835
<>	154:37f96f9d4de2	3836	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3837	}
<>	154:37f96f9d4de2	3838	else /* Generate Stop condition then Call TxCpltCallback() */
<>	154:37f96f9d4de2	3839	{
<>	154:37f96f9d4de2	3840	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	3841	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	3842
<>	154:37f96f9d4de2	3843	/* Generate Stop */
<>	154:37f96f9d4de2	3844	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	3845
<>	154:37f96f9d4de2	3846	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	3847	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3848
<>	154:37f96f9d4de2	3849	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	3850	{
<>	154:37f96f9d4de2	3851	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3852	HAL_I2C_MemTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3853	}
<>	154:37f96f9d4de2	3854	else
<>	154:37f96f9d4de2	3855	{
<>	154:37f96f9d4de2	3856	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3857	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3858	}
<>	154:37f96f9d4de2	3859	}
<>	144:ef7eb2e8f9f7	3860	}
<>	154:37f96f9d4de2	3861	else if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| \
<>	154:37f96f9d4de2	3862	((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX)))
<>	144:ef7eb2e8f9f7	3863	{
<>	154:37f96f9d4de2	3864	if(hi2c->XferCount == 0U)
<>	144:ef7eb2e8f9f7	3865	{
<>	154:37f96f9d4de2	3866	/* Disable BUF interrupt */
<>	154:37f96f9d4de2	3867	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	3868	}
<>	144:ef7eb2e8f9f7	3869	else
<>	144:ef7eb2e8f9f7	3870	{
<>	154:37f96f9d4de2	3871	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	3872	{
<>	154:37f96f9d4de2	3873	if(hi2c->EventCount == 0)
<>	154:37f96f9d4de2	3874	{
<>	154:37f96f9d4de2	3875	/* If Memory address size is 8Bit */
<>	154:37f96f9d4de2	3876	if(hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT)
<>	154:37f96f9d4de2	3877	{
<>	154:37f96f9d4de2	3878	/* Send Memory Address */
<>	154:37f96f9d4de2	3879	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	154:37f96f9d4de2	3880
<>	154:37f96f9d4de2	3881	hi2c->EventCount += 2;
<>	154:37f96f9d4de2	3882	}
<>	154:37f96f9d4de2	3883	/* If Memory address size is 16Bit */
<>	154:37f96f9d4de2	3884	else
<>	154:37f96f9d4de2	3885	{
<>	154:37f96f9d4de2	3886	/* Send MSB of Memory Address */
<>	154:37f96f9d4de2	3887	hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress);
<>	154:37f96f9d4de2	3888
<>	154:37f96f9d4de2	3889	hi2c->EventCount++;
<>	154:37f96f9d4de2	3890	}
<>	154:37f96f9d4de2	3891	}
<>	154:37f96f9d4de2	3892	else if(hi2c->EventCount == 1)
<>	154:37f96f9d4de2	3893	{
<>	154:37f96f9d4de2	3894	/* Send LSB of Memory Address */
<>	154:37f96f9d4de2	3895	hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress);
<>	154:37f96f9d4de2	3896
<>	154:37f96f9d4de2	3897	hi2c->EventCount++;
<>	154:37f96f9d4de2	3898	}
<>	154:37f96f9d4de2	3899	else if(hi2c->EventCount == 2)
<>	154:37f96f9d4de2	3900	{
<>	154:37f96f9d4de2	3901	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	154:37f96f9d4de2	3902	{
<>	154:37f96f9d4de2	3903	/* Generate Restart */
<>	154:37f96f9d4de2	3904	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	3905	}
<>	154:37f96f9d4de2	3906	else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	154:37f96f9d4de2	3907	{
<>	154:37f96f9d4de2	3908	/* Write data to DR */
<>	154:37f96f9d4de2	3909	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	3910	hi2c->XferCount--;
<>	154:37f96f9d4de2	3911	}
<>	154:37f96f9d4de2	3912	}
<>	154:37f96f9d4de2	3913	}
<>	154:37f96f9d4de2	3914	else
<>	154:37f96f9d4de2	3915	{
<>	154:37f96f9d4de2	3916	/* Write data to DR */
<>	154:37f96f9d4de2	3917	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	3918	hi2c->XferCount--;
<>	154:37f96f9d4de2	3919	}
<>	144:ef7eb2e8f9f7	3920	}
<>	144:ef7eb2e8f9f7	3921	}
<>	144:ef7eb2e8f9f7	3922	return HAL_OK;
<>	144:ef7eb2e8f9f7	3923	}
<>	144:ef7eb2e8f9f7	3924
<>	144:ef7eb2e8f9f7	3925	/**
<>	154:37f96f9d4de2	3926	* @brief Handle BTF flag for Master transmitter
<>	144:ef7eb2e8f9f7	3927	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3928	* the configuration information for I2C module
<>	154:37f96f9d4de2	3929	* @retval HAL status
<>	154:37f96f9d4de2	3930	*/
<>	154:37f96f9d4de2	3931	static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	3932	{
<>	154:37f96f9d4de2	3933	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	3934	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	3935
<>	154:37f96f9d4de2	3936	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	154:37f96f9d4de2	3937	{
<>	154:37f96f9d4de2	3938	if(hi2c->XferCount != 0U)
<>	154:37f96f9d4de2	3939	{
<>	154:37f96f9d4de2	3940	/* Write data to DR */
<>	154:37f96f9d4de2	3941	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	3942	hi2c->XferCount--;
<>	154:37f96f9d4de2	3943	}
<>	154:37f96f9d4de2	3944	else
<>	154:37f96f9d4de2	3945	{
<>	154:37f96f9d4de2	3946	/* Call TxCpltCallback() directly if no stop mode is set */
<>	154:37f96f9d4de2	3947	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	3948	{
<>	154:37f96f9d4de2	3949	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	3950
<>	154:37f96f9d4de2	3951	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
<>	154:37f96f9d4de2	3952	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3953	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3954
<>	154:37f96f9d4de2	3955	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3956	}
<>	154:37f96f9d4de2	3957	else /* Generate Stop condition then Call TxCpltCallback() */
<>	154:37f96f9d4de2	3958	{
<>	154:37f96f9d4de2	3959	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	3960	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	3961
<>	154:37f96f9d4de2	3962	/* Generate Stop */
<>	154:37f96f9d4de2	3963	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	3964
<>	154:37f96f9d4de2	3965	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	3966	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	3967
<>	154:37f96f9d4de2	3968	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	3969	{
<>	154:37f96f9d4de2	3970	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3971
<>	154:37f96f9d4de2	3972	HAL_I2C_MemTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3973	}
<>	154:37f96f9d4de2	3974	else
<>	154:37f96f9d4de2	3975	{
<>	154:37f96f9d4de2	3976	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	3977
<>	154:37f96f9d4de2	3978	HAL_I2C_MasterTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	3979	}
<>	154:37f96f9d4de2	3980	}
<>	154:37f96f9d4de2	3981	}
<>	154:37f96f9d4de2	3982	}
<>	154:37f96f9d4de2	3983	return HAL_OK;
<>	154:37f96f9d4de2	3984	}
<>	154:37f96f9d4de2	3985
<>	154:37f96f9d4de2	3986
<>	154:37f96f9d4de2	3987	/**
<>	154:37f96f9d4de2	3988	* @brief Handle RXNE flag for Master
<>	154:37f96f9d4de2	3989	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	3990	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	3991	* @retval HAL status
<>	144:ef7eb2e8f9f7	3992	*/
<>	144:ef7eb2e8f9f7	3993	static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	3994	{
<>	154:37f96f9d4de2	3995
<>	154:37f96f9d4de2	3996	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	144:ef7eb2e8f9f7	3997	{
<>	154:37f96f9d4de2	3998	uint32_t tmp = 0U;
<>	154:37f96f9d4de2	3999
<>	154:37f96f9d4de2	4000	tmp = hi2c->XferCount;
<>	154:37f96f9d4de2	4001	if(tmp > 3U)
<>	144:ef7eb2e8f9f7	4002	{
<>	154:37f96f9d4de2	4003	/* Read data from DR */
<>	154:37f96f9d4de2	4004	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4005	hi2c->XferCount--;
<>	154:37f96f9d4de2	4006	}
<>	154:37f96f9d4de2	4007	else if((tmp == 2U) \|\| (tmp == 3U))
<>	154:37f96f9d4de2	4008	{
<>	154:37f96f9d4de2	4009	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4010	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4011
<>	154:37f96f9d4de2	4012	/* Enable Pos */
<>	154:37f96f9d4de2	4013	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	154:37f96f9d4de2	4014
<>	154:37f96f9d4de2	4015	/* Disable BUF interrupt */
<>	154:37f96f9d4de2	4016	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	144:ef7eb2e8f9f7	4017	}
<>	144:ef7eb2e8f9f7	4018	else
<>	144:ef7eb2e8f9f7	4019	{
<>	154:37f96f9d4de2	4020	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4021	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4022
<>	154:37f96f9d4de2	4023	if(hi2c->XferOptions == I2C_NEXT_FRAME)
<>	154:37f96f9d4de2	4024	{
<>	154:37f96f9d4de2	4025	/* Enable Pos */
<>	154:37f96f9d4de2	4026	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	154:37f96f9d4de2	4027	}
<>	154:37f96f9d4de2	4028
<>	154:37f96f9d4de2	4029	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	4030	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	4031
<>	154:37f96f9d4de2	4032	/* Read data from DR */
<>	154:37f96f9d4de2	4033	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4034	hi2c->XferCount--;
<>	154:37f96f9d4de2	4035
<>	154:37f96f9d4de2	4036	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	154:37f96f9d4de2	4037	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	144:ef7eb2e8f9f7	4038	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	4039
<>	154:37f96f9d4de2	4040	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	4041	{
<>	154:37f96f9d4de2	4042	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4043	HAL_I2C_MemRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4044	}
<>	154:37f96f9d4de2	4045	else
<>	154:37f96f9d4de2	4046	{
<>	154:37f96f9d4de2	4047	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4048	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4049	}
<>	144:ef7eb2e8f9f7	4050	}
<>	144:ef7eb2e8f9f7	4051	}
<>	144:ef7eb2e8f9f7	4052	return HAL_OK;
<>	144:ef7eb2e8f9f7	4053	}
<>	144:ef7eb2e8f9f7	4054
<>	144:ef7eb2e8f9f7	4055	/**
<>	154:37f96f9d4de2	4056	* @brief Handle BTF flag for Master receiver
<>	144:ef7eb2e8f9f7	4057	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4058	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4059	* @retval HAL status
<>	144:ef7eb2e8f9f7	4060	*/
<>	144:ef7eb2e8f9f7	4061	static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4062	{
<>	154:37f96f9d4de2	4063	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4064	uint32_t tmp;
<>	154:37f96f9d4de2	4065	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	4066
<>	154:37f96f9d4de2	4067	if(hi2c->XferCount == 3U)
<>	144:ef7eb2e8f9f7	4068	{
<>	154:37f96f9d4de2	4069	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	4070	{
<>	154:37f96f9d4de2	4071	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4072	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4073	}
<>	144:ef7eb2e8f9f7	4074
<>	144:ef7eb2e8f9f7	4075	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4076	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4077	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4078	}
<>	154:37f96f9d4de2	4079	else if(hi2c->XferCount == 2U)
<>	144:ef7eb2e8f9f7	4080	{
<>	154:37f96f9d4de2	4081	/* Prepare next transfer or stop current transfer */
<>	154:37f96f9d4de2	4082	if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	4083	{
<>	154:37f96f9d4de2	4084	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4085	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4086
<>	154:37f96f9d4de2	4087	if((CurrentXferOptions == I2C_NEXT_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME))
<>	154:37f96f9d4de2	4088	{
<>	154:37f96f9d4de2	4089	/* Generate Start */
<>	154:37f96f9d4de2	4090	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4091	}
<>	154:37f96f9d4de2	4092	tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
<>	154:37f96f9d4de2	4093	hi2c->PreviousState = tmp \| (uint32_t)(hi2c->Mode);
<>	154:37f96f9d4de2	4094	}
<>	154:37f96f9d4de2	4095	else
<>	154:37f96f9d4de2	4096	{
<>	154:37f96f9d4de2	4097	hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
<>	154:37f96f9d4de2	4098
<>	154:37f96f9d4de2	4099	/* Generate Stop */
<>	154:37f96f9d4de2	4100	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	4101	}
<>	144:ef7eb2e8f9f7	4102
<>	144:ef7eb2e8f9f7	4103	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4104	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4105	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4106
<>	144:ef7eb2e8f9f7	4107	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4108	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4109	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4110
<>	154:37f96f9d4de2	4111	/* Disable EVT and ERR interrupt */
<>	154:37f96f9d4de2	4112	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	154:37f96f9d4de2	4113
<>	154:37f96f9d4de2	4114	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4115	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4116
<>	144:ef7eb2e8f9f7	4117	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	144:ef7eb2e8f9f7	4118	{
<>	154:37f96f9d4de2	4119	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4120
<>	144:ef7eb2e8f9f7	4121	HAL_I2C_MemRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4122	}
<>	144:ef7eb2e8f9f7	4123	else
<>	144:ef7eb2e8f9f7	4124	{
<>	154:37f96f9d4de2	4125	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	144:ef7eb2e8f9f7	4126
<>	144:ef7eb2e8f9f7	4127	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	144:ef7eb2e8f9f7	4128	}
<>	144:ef7eb2e8f9f7	4129	}
<>	144:ef7eb2e8f9f7	4130	else
<>	144:ef7eb2e8f9f7	4131	{
<>	144:ef7eb2e8f9f7	4132	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4133	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4134	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4135	}
<>	144:ef7eb2e8f9f7	4136	return HAL_OK;
<>	144:ef7eb2e8f9f7	4137	}
<>	144:ef7eb2e8f9f7	4138
<>	154:37f96f9d4de2	4139
<>	144:ef7eb2e8f9f7	4140	/**
<>	154:37f96f9d4de2	4141	* @brief Handle SB flag for Master
<>	154:37f96f9d4de2	4142	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4143	* the configuration information for I2C module
<>	154:37f96f9d4de2	4144	* @retval HAL status
<>	154:37f96f9d4de2	4145	*/
<>	154:37f96f9d4de2	4146	static HAL_StatusTypeDef I2C_Master_SB(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	4147	{
<>	154:37f96f9d4de2	4148	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	4149	{
<>	154:37f96f9d4de2	4150	if(hi2c->EventCount == 0U)
<>	154:37f96f9d4de2	4151	{
<>	154:37f96f9d4de2	4152	/* Send slave address */
<>	154:37f96f9d4de2	4153	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	154:37f96f9d4de2	4154	}
<>	154:37f96f9d4de2	4155	else
<>	154:37f96f9d4de2	4156	{
<>	154:37f96f9d4de2	4157	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	154:37f96f9d4de2	4158	}
<>	154:37f96f9d4de2	4159	}
<>	154:37f96f9d4de2	4160	else
<>	154:37f96f9d4de2	4161	{
<>	154:37f96f9d4de2	4162	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	154:37f96f9d4de2	4163	{
<>	154:37f96f9d4de2	4164	/* Send slave 7 Bits address */
<>	154:37f96f9d4de2	4165	if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
<>	154:37f96f9d4de2	4166	{
<>	154:37f96f9d4de2	4167	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress);
<>	154:37f96f9d4de2	4168	}
<>	154:37f96f9d4de2	4169	else
<>	154:37f96f9d4de2	4170	{
<>	154:37f96f9d4de2	4171	hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress);
<>	154:37f96f9d4de2	4172	}
<>	154:37f96f9d4de2	4173	}
<>	154:37f96f9d4de2	4174	else
<>	154:37f96f9d4de2	4175	{
<>	154:37f96f9d4de2	4176	if(hi2c->EventCount == 0U)
<>	154:37f96f9d4de2	4177	{
<>	154:37f96f9d4de2	4178	/* Send header of slave address */
<>	154:37f96f9d4de2	4179	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress);
<>	154:37f96f9d4de2	4180	}
<>	154:37f96f9d4de2	4181	else if(hi2c->EventCount == 1U)
<>	154:37f96f9d4de2	4182	{
<>	154:37f96f9d4de2	4183	/* Send header of slave address */
<>	154:37f96f9d4de2	4184	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress);
<>	154:37f96f9d4de2	4185	}
<>	154:37f96f9d4de2	4186	}
<>	154:37f96f9d4de2	4187	}
<>	154:37f96f9d4de2	4188
<>	154:37f96f9d4de2	4189	return HAL_OK;
<>	154:37f96f9d4de2	4190	}
<>	154:37f96f9d4de2	4191
<>	154:37f96f9d4de2	4192	/**
<>	154:37f96f9d4de2	4193	* @brief Handle ADD10 flag for Master
<>	154:37f96f9d4de2	4194	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4195	* the configuration information for I2C module
<>	154:37f96f9d4de2	4196	* @retval HAL status
<>	154:37f96f9d4de2	4197	*/
<>	154:37f96f9d4de2	4198	static HAL_StatusTypeDef I2C_Master_ADD10(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	4199	{
<>	154:37f96f9d4de2	4200	/* Send slave address */
<>	154:37f96f9d4de2	4201	hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress);
<>	154:37f96f9d4de2	4202
<>	154:37f96f9d4de2	4203	return HAL_OK;
<>	154:37f96f9d4de2	4204	}
<>	154:37f96f9d4de2	4205
<>	154:37f96f9d4de2	4206	/**
<>	154:37f96f9d4de2	4207	* @brief Handle ADDR flag for Master
<>	144:ef7eb2e8f9f7	4208	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4209	* the configuration information for I2C module
<>	154:37f96f9d4de2	4210	* @retval HAL status
<>	154:37f96f9d4de2	4211	*/
<>	154:37f96f9d4de2	4212	static HAL_StatusTypeDef I2C_Master_ADDR(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	4213	{
<>	154:37f96f9d4de2	4214	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4215	uint32_t CurrentMode = hi2c->Mode;
<>	154:37f96f9d4de2	4216	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	4217	uint32_t Prev_State = hi2c->PreviousState;
<>	154:37f96f9d4de2	4218
<>	154:37f96f9d4de2	4219	if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
<>	154:37f96f9d4de2	4220	{
<>	154:37f96f9d4de2	4221	if((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM))
<>	154:37f96f9d4de2	4222	{
<>	154:37f96f9d4de2	4223	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4224	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4225	}
<>	154:37f96f9d4de2	4226	else if((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT))
<>	154:37f96f9d4de2	4227	{
<>	154:37f96f9d4de2	4228	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4229	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4230
<>	154:37f96f9d4de2	4231	/* Generate Restart */
<>	154:37f96f9d4de2	4232	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4233
<>	154:37f96f9d4de2	4234	hi2c->EventCount++;
<>	154:37f96f9d4de2	4235	}
<>	154:37f96f9d4de2	4236	else
<>	154:37f96f9d4de2	4237	{
<>	154:37f96f9d4de2	4238	if(hi2c->XferCount == 0U)
<>	154:37f96f9d4de2	4239	{
<>	154:37f96f9d4de2	4240	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4241	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4242
<>	154:37f96f9d4de2	4243	/* Generate Stop */
<>	154:37f96f9d4de2	4244	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	4245	}
<>	154:37f96f9d4de2	4246	else if(hi2c->XferCount == 1U)
<>	154:37f96f9d4de2	4247	{
<>	154:37f96f9d4de2	4248	if(CurrentXferOptions == I2C_NO_OPTION_FRAME)
<>	154:37f96f9d4de2	4249	{
<>	154:37f96f9d4de2	4250	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4251	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4252
<>	154:37f96f9d4de2	4253	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	154:37f96f9d4de2	4254	{
<>	154:37f96f9d4de2	4255	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4256	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4257
<>	154:37f96f9d4de2	4258	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4259	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4260	}
<>	154:37f96f9d4de2	4261	else
<>	154:37f96f9d4de2	4262	{
<>	154:37f96f9d4de2	4263	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4264	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4265
<>	154:37f96f9d4de2	4266	/* Generate Stop */
<>	154:37f96f9d4de2	4267	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	4268	}
<>	154:37f96f9d4de2	4269	}
<>	154:37f96f9d4de2	4270	/* Prepare next transfer or stop current transfer */
<>	154:37f96f9d4de2	4271	else if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \
<>	154:37f96f9d4de2	4272	&& (Prev_State != I2C_STATE_MASTER_BUSY_RX))
<>	154:37f96f9d4de2	4273	{
<>	154:37f96f9d4de2	4274	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	154:37f96f9d4de2	4275	{
<>	154:37f96f9d4de2	4276	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4277	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4278	}
<>	154:37f96f9d4de2	4279	else
<>	154:37f96f9d4de2	4280	{
<>	154:37f96f9d4de2	4281	/* Enable Acknowledge */
<>	154:37f96f9d4de2	4282	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	4283	}
<>	154:37f96f9d4de2	4284
<>	154:37f96f9d4de2	4285	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4286	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4287	}
<>	154:37f96f9d4de2	4288	else
<>	154:37f96f9d4de2	4289	{
<>	154:37f96f9d4de2	4290	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4291	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4292
<>	154:37f96f9d4de2	4293	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4294	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4295
<>	154:37f96f9d4de2	4296	/* Generate Stop */
<>	154:37f96f9d4de2	4297	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	4298	}
<>	154:37f96f9d4de2	4299	}
<>	154:37f96f9d4de2	4300	else if(hi2c->XferCount == 2U)
<>	154:37f96f9d4de2	4301	{
<>	154:37f96f9d4de2	4302	if(hi2c->XferOptions != I2C_NEXT_FRAME)
<>	154:37f96f9d4de2	4303	{
<>	154:37f96f9d4de2	4304	/* Enable Pos */
<>	154:37f96f9d4de2	4305	hi2c->Instance->CR1 \|= I2C_CR1_POS;
<>	154:37f96f9d4de2	4306
<>	154:37f96f9d4de2	4307	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4308	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4309
<>	154:37f96f9d4de2	4310	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4311	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4312	}
<>	154:37f96f9d4de2	4313	else
<>	154:37f96f9d4de2	4314	{
<>	154:37f96f9d4de2	4315	/* Enable Acknowledge */
<>	154:37f96f9d4de2	4316	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	4317
<>	154:37f96f9d4de2	4318	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4319	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4320	}
<>	154:37f96f9d4de2	4321
<>	154:37f96f9d4de2	4322	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	154:37f96f9d4de2	4323	{
<>	154:37f96f9d4de2	4324	/* Enable Last DMA bit */
<>	154:37f96f9d4de2	4325	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	154:37f96f9d4de2	4326	}
<>	154:37f96f9d4de2	4327	}
<>	154:37f96f9d4de2	4328	else
<>	154:37f96f9d4de2	4329	{
<>	154:37f96f9d4de2	4330	/* Enable Acknowledge */
<>	154:37f96f9d4de2	4331	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	4332
<>	154:37f96f9d4de2	4333	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	154:37f96f9d4de2	4334	{
<>	154:37f96f9d4de2	4335	/* Enable Last DMA bit */
<>	154:37f96f9d4de2	4336	hi2c->Instance->CR2 \|= I2C_CR2_LAST;
<>	154:37f96f9d4de2	4337	}
<>	154:37f96f9d4de2	4338
<>	154:37f96f9d4de2	4339	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4340	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4341	}
<>	154:37f96f9d4de2	4342
<>	154:37f96f9d4de2	4343	/* Reset Event counter */
<>	154:37f96f9d4de2	4344	hi2c->EventCount = 0U;
<>	154:37f96f9d4de2	4345	}
<>	154:37f96f9d4de2	4346	}
<>	154:37f96f9d4de2	4347	else
<>	154:37f96f9d4de2	4348	{
<>	154:37f96f9d4de2	4349	/* Clear ADDR flag */
<>	154:37f96f9d4de2	4350	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	154:37f96f9d4de2	4351	}
<>	154:37f96f9d4de2	4352
<>	154:37f96f9d4de2	4353	return HAL_OK;
<>	154:37f96f9d4de2	4354	}
<>	154:37f96f9d4de2	4355
<>	154:37f96f9d4de2	4356	/**
<>	154:37f96f9d4de2	4357	* @brief Handle TXE flag for Slave
<>	154:37f96f9d4de2	4358	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4359	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4360	* @retval HAL status
<>	144:ef7eb2e8f9f7	4361	*/
<>	144:ef7eb2e8f9f7	4362	static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4363	{
<>	154:37f96f9d4de2	4364	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4365	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	4366
<>	154:37f96f9d4de2	4367	if(hi2c->XferCount != 0U)
<>	154:37f96f9d4de2	4368	{
<>	154:37f96f9d4de2	4369	/* Write data to DR */
<>	154:37f96f9d4de2	4370	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	154:37f96f9d4de2	4371	hi2c->XferCount--;
<>	154:37f96f9d4de2	4372
<>	154:37f96f9d4de2	4373	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	154:37f96f9d4de2	4374	{
<>	154:37f96f9d4de2	4375	/* Last Byte is received, disable Interrupt */
<>	154:37f96f9d4de2	4376	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	154:37f96f9d4de2	4377
<>	154:37f96f9d4de2	4378	/* Set state at HAL_I2C_STATE_LISTEN */
<>	154:37f96f9d4de2	4379	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	154:37f96f9d4de2	4380	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	154:37f96f9d4de2	4381
<>	154:37f96f9d4de2	4382	/* Call the Tx complete callback to inform upper layer of the end of receive process */
<>	154:37f96f9d4de2	4383	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4384	}
<>	154:37f96f9d4de2	4385	}
<>	154:37f96f9d4de2	4386	return HAL_OK;
<>	154:37f96f9d4de2	4387	}
<>	154:37f96f9d4de2	4388
<>	154:37f96f9d4de2	4389	/**
<>	154:37f96f9d4de2	4390	* @brief Handle BTF flag for Slave transmitter
<>	154:37f96f9d4de2	4391	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4392	* the configuration information for I2C module
<>	154:37f96f9d4de2	4393	* @retval HAL status
<>	154:37f96f9d4de2	4394	*/
<>	154:37f96f9d4de2	4395	static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	4396	{
<>	154:37f96f9d4de2	4397	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4398	{
<>	144:ef7eb2e8f9f7	4399	/* Write data to DR */
<>	144:ef7eb2e8f9f7	4400	hi2c->Instance->DR = (*hi2c->pBuffPtr++);
<>	144:ef7eb2e8f9f7	4401	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4402	}
<>	144:ef7eb2e8f9f7	4403	return HAL_OK;
<>	144:ef7eb2e8f9f7	4404	}
<>	144:ef7eb2e8f9f7	4405
<>	144:ef7eb2e8f9f7	4406	/**
<>	154:37f96f9d4de2	4407	* @brief Handle RXNE flag for Slave
<>	144:ef7eb2e8f9f7	4408	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4409	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4410	* @retval HAL status
<>	144:ef7eb2e8f9f7	4411	*/
<>	154:37f96f9d4de2	4412	static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4413	{
<>	154:37f96f9d4de2	4414	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4415	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	4416
<>	154:37f96f9d4de2	4417	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4418	{
<>	154:37f96f9d4de2	4419	/* Read data from DR */
<>	154:37f96f9d4de2	4420	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4421	hi2c->XferCount--;
<>	154:37f96f9d4de2	4422
<>	154:37f96f9d4de2	4423	if((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	154:37f96f9d4de2	4424	{
<>	154:37f96f9d4de2	4425	/* Last Byte is received, disable Interrupt */
<>	154:37f96f9d4de2	4426	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
<>	154:37f96f9d4de2	4427
<>	154:37f96f9d4de2	4428	/* Set state at HAL_I2C_STATE_LISTEN */
<>	154:37f96f9d4de2	4429	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
<>	154:37f96f9d4de2	4430	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	154:37f96f9d4de2	4431
<>	154:37f96f9d4de2	4432	/* Call the Rx complete callback to inform upper layer of the end of receive process */
<>	154:37f96f9d4de2	4433	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4434	}
<>	144:ef7eb2e8f9f7	4435	}
<>	144:ef7eb2e8f9f7	4436	return HAL_OK;
<>	144:ef7eb2e8f9f7	4437	}
<>	144:ef7eb2e8f9f7	4438
<>	144:ef7eb2e8f9f7	4439	/**
<>	154:37f96f9d4de2	4440	* @brief Handle BTF flag for Slave receiver
<>	144:ef7eb2e8f9f7	4441	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4442	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4443	* @retval HAL status
<>	144:ef7eb2e8f9f7	4444	*/
<>	144:ef7eb2e8f9f7	4445	static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4446	{
<>	154:37f96f9d4de2	4447	if(hi2c->XferCount != 0U)
<>	144:ef7eb2e8f9f7	4448	{
<>	144:ef7eb2e8f9f7	4449	/* Read data from DR */
<>	144:ef7eb2e8f9f7	4450	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	144:ef7eb2e8f9f7	4451	hi2c->XferCount--;
<>	144:ef7eb2e8f9f7	4452	}
<>	144:ef7eb2e8f9f7	4453	return HAL_OK;
<>	144:ef7eb2e8f9f7	4454	}
<>	144:ef7eb2e8f9f7	4455
<>	144:ef7eb2e8f9f7	4456	/**
<>	144:ef7eb2e8f9f7	4457	* @brief Handle ADD flag for Slave
<>	144:ef7eb2e8f9f7	4458	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4459	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4460	* @retval HAL status
<>	144:ef7eb2e8f9f7	4461	*/
<>	144:ef7eb2e8f9f7	4462	static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4463	{
<>	154:37f96f9d4de2	4464	uint8_t TransferDirection = I2C_DIRECTION_RECEIVE;
<>	154:37f96f9d4de2	4465	uint16_t SlaveAddrCode = 0U;
<>	154:37f96f9d4de2	4466
<>	154:37f96f9d4de2	4467	/* Transfer Direction requested by Master */
<>	154:37f96f9d4de2	4468	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == RESET)
<>	154:37f96f9d4de2	4469	{
<>	154:37f96f9d4de2	4470	TransferDirection = I2C_DIRECTION_TRANSMIT;
<>	154:37f96f9d4de2	4471	}
<>	154:37f96f9d4de2	4472
<>	154:37f96f9d4de2	4473	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_DUALF) == RESET)
<>	154:37f96f9d4de2	4474	{
<>	154:37f96f9d4de2	4475	SlaveAddrCode = hi2c->Init.OwnAddress1;
<>	154:37f96f9d4de2	4476	}
<>	154:37f96f9d4de2	4477	else
<>	154:37f96f9d4de2	4478	{
<>	154:37f96f9d4de2	4479	SlaveAddrCode = hi2c->Init.OwnAddress2;
<>	154:37f96f9d4de2	4480	}
<>	154:37f96f9d4de2	4481
<>	154:37f96f9d4de2	4482	/* Call Slave Addr callback */
<>	154:37f96f9d4de2	4483	HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode);
<>	144:ef7eb2e8f9f7	4484
<>	144:ef7eb2e8f9f7	4485	return HAL_OK;
<>	144:ef7eb2e8f9f7	4486	}
<>	144:ef7eb2e8f9f7	4487
<>	144:ef7eb2e8f9f7	4488	/**
<>	154:37f96f9d4de2	4489	* @brief Handle STOPF flag for Slave
<>	144:ef7eb2e8f9f7	4490	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4491	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4492	* @retval HAL status
<>	144:ef7eb2e8f9f7	4493	*/
<>	144:ef7eb2e8f9f7	4494	static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4495	{
<>	154:37f96f9d4de2	4496	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4497	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	4498
<>	144:ef7eb2e8f9f7	4499	/* Disable EVT, BUF and ERR interrupt */
<>	144:ef7eb2e8f9f7	4500	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	4501
<>	144:ef7eb2e8f9f7	4502	/* Clear STOPF flag */
<>	144:ef7eb2e8f9f7	4503	__HAL_I2C_CLEAR_STOPFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4504
<>	144:ef7eb2e8f9f7	4505	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4506	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4507
<>	154:37f96f9d4de2	4508	/* If a DMA is ongoing, Update handle size context */
<>	154:37f96f9d4de2	4509	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	154:37f96f9d4de2	4510	{
<>	154:37f96f9d4de2	4511	if((hi2c->State == HAL_I2C_STATE_BUSY_RX) \|\| (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	154:37f96f9d4de2	4512	{
<>	154:37f96f9d4de2	4513	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmarx);
<>	154:37f96f9d4de2	4514	}
<>	154:37f96f9d4de2	4515	else
<>	154:37f96f9d4de2	4516	{
<>	154:37f96f9d4de2	4517	hi2c->XferCount = __HAL_DMA_GET_COUNTER(hi2c->hdmatx);
<>	154:37f96f9d4de2	4518	}
<>	154:37f96f9d4de2	4519	}
<>	154:37f96f9d4de2	4520
<>	154:37f96f9d4de2	4521	/* All data are not transferred, so set error code accordingly */
<>	154:37f96f9d4de2	4522	if(hi2c->XferCount != 0U)
<>	154:37f96f9d4de2	4523	{
<>	154:37f96f9d4de2	4524	/* Store Last receive data if any */
<>	154:37f96f9d4de2	4525	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
<>	154:37f96f9d4de2	4526	{
<>	154:37f96f9d4de2	4527	/* Read data from DR */
<>	154:37f96f9d4de2	4528	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4529	hi2c->XferCount--;
<>	154:37f96f9d4de2	4530	}
<>	154:37f96f9d4de2	4531
<>	154:37f96f9d4de2	4532	/* Store Last receive data if any */
<>	154:37f96f9d4de2	4533	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	154:37f96f9d4de2	4534	{
<>	154:37f96f9d4de2	4535	/* Read data from DR */
<>	154:37f96f9d4de2	4536	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4537	hi2c->XferCount--;
<>	154:37f96f9d4de2	4538	}
<>	154:37f96f9d4de2	4539
<>	154:37f96f9d4de2	4540	/* Set ErrorCode corresponding to a Non-Acknowledge */
<>	154:37f96f9d4de2	4541	hi2c->ErrorCode \|= HAL_I2C_ERROR_AF;
<>	154:37f96f9d4de2	4542	}
<>	154:37f96f9d4de2	4543
<>	154:37f96f9d4de2	4544	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	154:37f96f9d4de2	4545	{
<>	154:37f96f9d4de2	4546	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	154:37f96f9d4de2	4547	I2C_ITError(hi2c);
<>	154:37f96f9d4de2	4548	}
<>	154:37f96f9d4de2	4549	else
<>	154:37f96f9d4de2	4550	{
<>	154:37f96f9d4de2	4551	if((CurrentState == HAL_I2C_STATE_LISTEN ) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) \|\| \
<>	154:37f96f9d4de2	4552	(CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN))
<>	154:37f96f9d4de2	4553	{
<>	154:37f96f9d4de2	4554	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	4555	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4556	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4557	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4558
<>	154:37f96f9d4de2	4559	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	154:37f96f9d4de2	4560	HAL_I2C_ListenCpltCallback(hi2c);
<>	154:37f96f9d4de2	4561	}
<>	154:37f96f9d4de2	4562	else
<>	154:37f96f9d4de2	4563	{
<>	154:37f96f9d4de2	4564	if((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX))
<>	154:37f96f9d4de2	4565	{
<>	154:37f96f9d4de2	4566	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4567	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4568	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4569
<>	154:37f96f9d4de2	4570	HAL_I2C_SlaveRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4571	}
<>	154:37f96f9d4de2	4572	}
<>	154:37f96f9d4de2	4573	}
<>	144:ef7eb2e8f9f7	4574	return HAL_OK;
<>	144:ef7eb2e8f9f7	4575	}
<>	144:ef7eb2e8f9f7	4576
<>	144:ef7eb2e8f9f7	4577	/**
<>	144:ef7eb2e8f9f7	4578	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4579	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4580	* @retval HAL status
<>	144:ef7eb2e8f9f7	4581	*/
<>	144:ef7eb2e8f9f7	4582	static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	4583	{
<>	154:37f96f9d4de2	4584	/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4585	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	4586	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	4587
<>	154:37f96f9d4de2	4588	if(((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_LAST_FRAME)) && \
<>	154:37f96f9d4de2	4589	(CurrentState == HAL_I2C_STATE_LISTEN))
<>	154:37f96f9d4de2	4590	{
<>	154:37f96f9d4de2	4591	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	4592
<>	154:37f96f9d4de2	4593	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	4594	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	4595
<>	154:37f96f9d4de2	4596	/* Clear AF flag */
<>	154:37f96f9d4de2	4597	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	154:37f96f9d4de2	4598
<>	154:37f96f9d4de2	4599	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4600	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4601
<>	154:37f96f9d4de2	4602	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4603	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4604	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4605
<>	154:37f96f9d4de2	4606	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	154:37f96f9d4de2	4607	HAL_I2C_ListenCpltCallback(hi2c);
<>	154:37f96f9d4de2	4608	}
<>	154:37f96f9d4de2	4609	else if(CurrentState == HAL_I2C_STATE_BUSY_TX)
<>	154:37f96f9d4de2	4610	{
<>	154:37f96f9d4de2	4611	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	4612	hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
<>	154:37f96f9d4de2	4613	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4614	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4615
<>	154:37f96f9d4de2	4616	/* Disable EVT, BUF and ERR interrupt */
<>	154:37f96f9d4de2	4617	__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_BUF \| I2C_IT_ERR);
<>	154:37f96f9d4de2	4618
<>	154:37f96f9d4de2	4619	/* Clear AF flag */
<>	154:37f96f9d4de2	4620	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	154:37f96f9d4de2	4621
<>	154:37f96f9d4de2	4622	/* Disable Acknowledge */
<>	154:37f96f9d4de2	4623	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	4624
<>	154:37f96f9d4de2	4625	HAL_I2C_SlaveTxCpltCallback(hi2c);
<>	154:37f96f9d4de2	4626	}
<>	154:37f96f9d4de2	4627	else
<>	154:37f96f9d4de2	4628	{
<>	154:37f96f9d4de2	4629	/* Clear AF flag only */
<>	154:37f96f9d4de2	4630	/* State Listen, but XferOptions == FIRST or NEXT */
<>	154:37f96f9d4de2	4631	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	154:37f96f9d4de2	4632	}
<>	154:37f96f9d4de2	4633
<>	144:ef7eb2e8f9f7	4634	return HAL_OK;
<>	144:ef7eb2e8f9f7	4635	}
<>	144:ef7eb2e8f9f7	4636
<>	144:ef7eb2e8f9f7	4637	/**
<>	154:37f96f9d4de2	4638	* @brief I2C interrupts error process
<>	154:37f96f9d4de2	4639	* @param hi2c I2C handle.
<>	154:37f96f9d4de2	4640	* @retval None
<>	154:37f96f9d4de2	4641	*/
<>	154:37f96f9d4de2	4642	static void I2C_ITError(I2C_HandleTypeDef *hi2c)
<>	154:37f96f9d4de2	4643	{
<>	154:37f96f9d4de2	4644	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4645	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	4646
<>	154:37f96f9d4de2	4647	if((CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) \|\| (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN))
<>	154:37f96f9d4de2	4648	{
<>	154:37f96f9d4de2	4649	/* keep HAL_I2C_STATE_LISTEN */
<>	154:37f96f9d4de2	4650	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4651	hi2c->State = HAL_I2C_STATE_LISTEN;
<>	154:37f96f9d4de2	4652	}
<>	154:37f96f9d4de2	4653	else
<>	154:37f96f9d4de2	4654	{
<>	154:37f96f9d4de2	4655	/* If state is an abort treatment on going, don't change state */
<>	154:37f96f9d4de2	4656	/* This change will be do later */
<>	154:37f96f9d4de2	4657	if((hi2c->State != HAL_I2C_STATE_ABORT) && ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) != I2C_CR2_DMAEN))
<>	154:37f96f9d4de2	4658	{
<>	154:37f96f9d4de2	4659	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4660	}
<>	154:37f96f9d4de2	4661	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4662	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4663	}
<>	154:37f96f9d4de2	4664
<>	154:37f96f9d4de2	4665	/* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */
<>	154:37f96f9d4de2	4666	hi2c->Instance->CR1 &= ~I2C_CR1_POS;
<>	154:37f96f9d4de2	4667
<>	154:37f96f9d4de2	4668	/* Abort DMA transfer */
<>	154:37f96f9d4de2	4669	if((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN)
<>	154:37f96f9d4de2	4670	{
<>	154:37f96f9d4de2	4671	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	4672
<>	154:37f96f9d4de2	4673	if(hi2c->hdmatx->State != HAL_DMA_STATE_READY)
<>	154:37f96f9d4de2	4674	{
<>	154:37f96f9d4de2	4675	/* Set the DMA Abort callback :
<>	154:37f96f9d4de2	4676	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	154:37f96f9d4de2	4677	hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
<>	154:37f96f9d4de2	4678
<>	154:37f96f9d4de2	4679	if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
<>	154:37f96f9d4de2	4680	{
<>	154:37f96f9d4de2	4681	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	154:37f96f9d4de2	4682	__HAL_I2C_DISABLE(hi2c);
<>	154:37f96f9d4de2	4683
<>	154:37f96f9d4de2	4684	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4685
<>	154:37f96f9d4de2	4686	/* Call Directly XferAbortCallback function in case of error */
<>	154:37f96f9d4de2	4687	hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
<>	154:37f96f9d4de2	4688	}
<>	154:37f96f9d4de2	4689	}
<>	154:37f96f9d4de2	4690	else
<>	154:37f96f9d4de2	4691	{
<>	154:37f96f9d4de2	4692	/* Set the DMA Abort callback :
<>	154:37f96f9d4de2	4693	will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
<>	154:37f96f9d4de2	4694	hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
<>	154:37f96f9d4de2	4695
<>	154:37f96f9d4de2	4696	if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
<>	154:37f96f9d4de2	4697	{
<>	154:37f96f9d4de2	4698	/* Store Last receive data if any */
<>	154:37f96f9d4de2	4699	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	154:37f96f9d4de2	4700	{
<>	154:37f96f9d4de2	4701	/* Read data from DR */
<>	154:37f96f9d4de2	4702	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4703	}
<>	154:37f96f9d4de2	4704
<>	154:37f96f9d4de2	4705	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	154:37f96f9d4de2	4706	__HAL_I2C_DISABLE(hi2c);
<>	154:37f96f9d4de2	4707
<>	154:37f96f9d4de2	4708	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4709
<>	154:37f96f9d4de2	4710	/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
<>	154:37f96f9d4de2	4711	hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
<>	154:37f96f9d4de2	4712	}
<>	154:37f96f9d4de2	4713	}
<>	154:37f96f9d4de2	4714	}
<>	154:37f96f9d4de2	4715	else if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	154:37f96f9d4de2	4716	{
<>	154:37f96f9d4de2	4717	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4718	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	4719
<>	154:37f96f9d4de2	4720	/* Store Last receive data if any */
<>	154:37f96f9d4de2	4721	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	154:37f96f9d4de2	4722	{
<>	154:37f96f9d4de2	4723	/* Read data from DR */
<>	154:37f96f9d4de2	4724	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4725	}
<>	154:37f96f9d4de2	4726
<>	154:37f96f9d4de2	4727	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	154:37f96f9d4de2	4728	__HAL_I2C_DISABLE(hi2c);
<>	154:37f96f9d4de2	4729
<>	154:37f96f9d4de2	4730	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	154:37f96f9d4de2	4731	HAL_I2C_AbortCpltCallback(hi2c);
<>	154:37f96f9d4de2	4732	}
<>	154:37f96f9d4de2	4733	else
<>	154:37f96f9d4de2	4734	{
<>	154:37f96f9d4de2	4735	/* Store Last receive data if any */
<>	154:37f96f9d4de2	4736	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
<>	154:37f96f9d4de2	4737	{
<>	154:37f96f9d4de2	4738	/* Read data from DR */
<>	154:37f96f9d4de2	4739	(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
<>	154:37f96f9d4de2	4740	}
<>	154:37f96f9d4de2	4741
<>	154:37f96f9d4de2	4742	/* Call user error callback */
<>	154:37f96f9d4de2	4743	HAL_I2C_ErrorCallback(hi2c);
<>	154:37f96f9d4de2	4744	}
<>	154:37f96f9d4de2	4745	/* STOP Flag is not set after a NACK reception */
<>	154:37f96f9d4de2	4746	/* So may inform upper layer that listen phase is stopped */
<>	154:37f96f9d4de2	4747	/* during NACK error treatment */
<>	154:37f96f9d4de2	4748	if((hi2c->State == HAL_I2C_STATE_LISTEN) && ((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF))
<>	154:37f96f9d4de2	4749	{
<>	154:37f96f9d4de2	4750	hi2c->XferOptions = I2C_NO_OPTION_FRAME;
<>	154:37f96f9d4de2	4751	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	4752	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	4753	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	4754
<>	154:37f96f9d4de2	4755	/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
<>	154:37f96f9d4de2	4756	HAL_I2C_ListenCpltCallback(hi2c);
<>	154:37f96f9d4de2	4757	}
<>	154:37f96f9d4de2	4758	}
<>	154:37f96f9d4de2	4759
<>	154:37f96f9d4de2	4760	/**
<>	144:ef7eb2e8f9f7	4761	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4762	* the configuration information for I2C module
<>	154:37f96f9d4de2	4763	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	4764	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4765	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	4766	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4767	* @retval HAL status
<>	144:ef7eb2e8f9f7	4768	*/
<>	154:37f96f9d4de2	4769	static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4770	{
<>	154:37f96f9d4de2	4771	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4772	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	4773
<>	154:37f96f9d4de2	4774	/* Generate Start condition if first transfer */
<>	154:37f96f9d4de2	4775	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	4776	{
<>	154:37f96f9d4de2	4777	/* Generate Start */
<>	154:37f96f9d4de2	4778	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4779	}
<>	154:37f96f9d4de2	4780	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
<>	154:37f96f9d4de2	4781	{
<>	154:37f96f9d4de2	4782	/* Generate ReStart */
<>	154:37f96f9d4de2	4783	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4784	}
<>	144:ef7eb2e8f9f7	4785
<>	144:ef7eb2e8f9f7	4786	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	4787	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4788	{
<>	144:ef7eb2e8f9f7	4789	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4790	}
<>	144:ef7eb2e8f9f7	4791
<>	144:ef7eb2e8f9f7	4792	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4793	{
<>	144:ef7eb2e8f9f7	4794	/* Send slave address */
<>	144:ef7eb2e8f9f7	4795	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4796	}
<>	144:ef7eb2e8f9f7	4797	else
<>	144:ef7eb2e8f9f7	4798	{
<>	144:ef7eb2e8f9f7	4799	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4800	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4801
<>	144:ef7eb2e8f9f7	4802	/* Wait until ADD10 flag is set */
<>	154:37f96f9d4de2	4803	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4804	{
<>	144:ef7eb2e8f9f7	4805	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4806	{
<>	144:ef7eb2e8f9f7	4807	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4808	}
<>	144:ef7eb2e8f9f7	4809	else
<>	144:ef7eb2e8f9f7	4810	{
<>	144:ef7eb2e8f9f7	4811	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4812	}
<>	144:ef7eb2e8f9f7	4813	}
<>	144:ef7eb2e8f9f7	4814
<>	144:ef7eb2e8f9f7	4815	/* Send slave address */
<>	144:ef7eb2e8f9f7	4816	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4817	}
<>	144:ef7eb2e8f9f7	4818
<>	144:ef7eb2e8f9f7	4819	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	4820	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4821	{
<>	144:ef7eb2e8f9f7	4822	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4823	{
<>	144:ef7eb2e8f9f7	4824	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4825	}
<>	144:ef7eb2e8f9f7	4826	else
<>	144:ef7eb2e8f9f7	4827	{
<>	144:ef7eb2e8f9f7	4828	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4829	}
<>	144:ef7eb2e8f9f7	4830	}
<>	144:ef7eb2e8f9f7	4831
<>	144:ef7eb2e8f9f7	4832	return HAL_OK;
<>	144:ef7eb2e8f9f7	4833	}
<>	144:ef7eb2e8f9f7	4834
<>	144:ef7eb2e8f9f7	4835	/**
<>	154:37f96f9d4de2	4836	* @brief Master sends target device address for read request.
<>	144:ef7eb2e8f9f7	4837	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4838	* the configuration information for I2C module
<>	154:37f96f9d4de2	4839	* @param DevAddress Target device address: The device 7 bits address value
<>	154:37f96f9d4de2	4840	* in datasheet must be shift at right before call interface
<>	144:ef7eb2e8f9f7	4841	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	4842	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4843	* @retval HAL status
<>	144:ef7eb2e8f9f7	4844	*/
<>	154:37f96f9d4de2	4845	static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4846	{
<>	154:37f96f9d4de2	4847	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	4848	uint32_t CurrentXferOptions = hi2c->XferOptions;
<>	154:37f96f9d4de2	4849
<>	144:ef7eb2e8f9f7	4850	/* Enable Acknowledge */
<>	154:37f96f9d4de2	4851	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	154:37f96f9d4de2	4852
<>	154:37f96f9d4de2	4853	/* Generate Start condition if first transfer */
<>	154:37f96f9d4de2	4854	if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) \|\| (CurrentXferOptions == I2C_FIRST_FRAME) \|\| (CurrentXferOptions == I2C_NO_OPTION_FRAME))
<>	154:37f96f9d4de2	4855	{
<>	154:37f96f9d4de2	4856	/* Generate Start */
<>	154:37f96f9d4de2	4857	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4858	}
<>	154:37f96f9d4de2	4859	else if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
<>	154:37f96f9d4de2	4860	{
<>	154:37f96f9d4de2	4861	/* Generate ReStart */
<>	154:37f96f9d4de2	4862	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	154:37f96f9d4de2	4863	}
<>	144:ef7eb2e8f9f7	4864
<>	144:ef7eb2e8f9f7	4865	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	4866	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4867	{
<>	144:ef7eb2e8f9f7	4868	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4869	}
<>	144:ef7eb2e8f9f7	4870
<>	144:ef7eb2e8f9f7	4871	if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
<>	144:ef7eb2e8f9f7	4872	{
<>	144:ef7eb2e8f9f7	4873	/* Send slave address */
<>	144:ef7eb2e8f9f7	4874	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4875	}
<>	144:ef7eb2e8f9f7	4876	else
<>	144:ef7eb2e8f9f7	4877	{
<>	144:ef7eb2e8f9f7	4878	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4879	hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4880
<>	144:ef7eb2e8f9f7	4881	/* Wait until ADD10 flag is set */
<>	154:37f96f9d4de2	4882	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4883	{
<>	144:ef7eb2e8f9f7	4884	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4885	{
<>	144:ef7eb2e8f9f7	4886	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4887	}
<>	144:ef7eb2e8f9f7	4888	else
<>	144:ef7eb2e8f9f7	4889	{
<>	144:ef7eb2e8f9f7	4890	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4891	}
<>	144:ef7eb2e8f9f7	4892	}
<>	144:ef7eb2e8f9f7	4893
<>	144:ef7eb2e8f9f7	4894	/* Send slave address */
<>	144:ef7eb2e8f9f7	4895	hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
<>	144:ef7eb2e8f9f7	4896
<>	144:ef7eb2e8f9f7	4897	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	4898	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4899	{
<>	144:ef7eb2e8f9f7	4900	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4901	{
<>	144:ef7eb2e8f9f7	4902	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4903	}
<>	144:ef7eb2e8f9f7	4904	else
<>	144:ef7eb2e8f9f7	4905	{
<>	144:ef7eb2e8f9f7	4906	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4907	}
<>	144:ef7eb2e8f9f7	4908	}
<>	144:ef7eb2e8f9f7	4909
<>	144:ef7eb2e8f9f7	4910	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4911	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4912
<>	144:ef7eb2e8f9f7	4913	/* Generate Restart */
<>	154:37f96f9d4de2	4914	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4915
<>	144:ef7eb2e8f9f7	4916	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	4917	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4918	{
<>	144:ef7eb2e8f9f7	4919	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4920	}
<>	144:ef7eb2e8f9f7	4921
<>	144:ef7eb2e8f9f7	4922	/* Send header of slave address */
<>	144:ef7eb2e8f9f7	4923	hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
<>	144:ef7eb2e8f9f7	4924	}
<>	144:ef7eb2e8f9f7	4925
<>	144:ef7eb2e8f9f7	4926	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	4927	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4928	{
<>	144:ef7eb2e8f9f7	4929	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4930	{
<>	144:ef7eb2e8f9f7	4931	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4932	}
<>	144:ef7eb2e8f9f7	4933	else
<>	144:ef7eb2e8f9f7	4934	{
<>	144:ef7eb2e8f9f7	4935	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4936	}
<>	144:ef7eb2e8f9f7	4937	}
<>	144:ef7eb2e8f9f7	4938
<>	144:ef7eb2e8f9f7	4939	return HAL_OK;
<>	144:ef7eb2e8f9f7	4940	}
<>	144:ef7eb2e8f9f7	4941
<>	144:ef7eb2e8f9f7	4942	/**
<>	144:ef7eb2e8f9f7	4943	* @brief Master sends target device address followed by internal memory address for write request.
<>	144:ef7eb2e8f9f7	4944	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	4945	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	4946	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	4947	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	4948	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	4949	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	4950	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	4951	* @retval HAL status
<>	144:ef7eb2e8f9f7	4952	*/
<>	154:37f96f9d4de2	4953	static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	4954	{
<>	144:ef7eb2e8f9f7	4955	/* Generate Start */
<>	154:37f96f9d4de2	4956	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	4957
<>	144:ef7eb2e8f9f7	4958	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	4959	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4960	{
<>	144:ef7eb2e8f9f7	4961	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4962	}
<>	144:ef7eb2e8f9f7	4963
<>	144:ef7eb2e8f9f7	4964	/* Send slave address */
<>	144:ef7eb2e8f9f7	4965	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	4966
<>	144:ef7eb2e8f9f7	4967	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	4968	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4969	{
<>	144:ef7eb2e8f9f7	4970	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4971	{
<>	144:ef7eb2e8f9f7	4972	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4973	}
<>	144:ef7eb2e8f9f7	4974	else
<>	144:ef7eb2e8f9f7	4975	{
<>	144:ef7eb2e8f9f7	4976	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4977	}
<>	144:ef7eb2e8f9f7	4978	}
<>	144:ef7eb2e8f9f7	4979
<>	144:ef7eb2e8f9f7	4980	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	4981	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	4982
<>	144:ef7eb2e8f9f7	4983	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	4984	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	4985	{
<>	144:ef7eb2e8f9f7	4986	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	4987	{
<>	144:ef7eb2e8f9f7	4988	/* Generate Stop */
<>	154:37f96f9d4de2	4989	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	4990	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	4991	}
<>	144:ef7eb2e8f9f7	4992	else
<>	144:ef7eb2e8f9f7	4993	{
<>	144:ef7eb2e8f9f7	4994	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	4995	}
<>	144:ef7eb2e8f9f7	4996	}
<>	144:ef7eb2e8f9f7	4997
<>	144:ef7eb2e8f9f7	4998	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	4999	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	5000	{
<>	144:ef7eb2e8f9f7	5001	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	5002	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5003	}
<>	144:ef7eb2e8f9f7	5004	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	5005	else
<>	144:ef7eb2e8f9f7	5006	{
<>	144:ef7eb2e8f9f7	5007	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	5008	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	5009
<>	144:ef7eb2e8f9f7	5010	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	5011	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5012	{
<>	144:ef7eb2e8f9f7	5013	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5014	{
<>	144:ef7eb2e8f9f7	5015	/* Generate Stop */
<>	154:37f96f9d4de2	5016	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5017	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5018	}
<>	144:ef7eb2e8f9f7	5019	else
<>	144:ef7eb2e8f9f7	5020	{
<>	144:ef7eb2e8f9f7	5021	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5022	}
<>	144:ef7eb2e8f9f7	5023	}
<>	144:ef7eb2e8f9f7	5024
<>	144:ef7eb2e8f9f7	5025	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	5026	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5027	}
<>	144:ef7eb2e8f9f7	5028
<>	144:ef7eb2e8f9f7	5029	return HAL_OK;
<>	144:ef7eb2e8f9f7	5030	}
<>	144:ef7eb2e8f9f7	5031
<>	144:ef7eb2e8f9f7	5032	/**
<>	144:ef7eb2e8f9f7	5033	* @brief Master sends target device address followed by internal memory address for read request.
<>	144:ef7eb2e8f9f7	5034	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	5035	* the configuration information for I2C module
<>	144:ef7eb2e8f9f7	5036	* @param DevAddress Target device address
<>	144:ef7eb2e8f9f7	5037	* @param MemAddress Internal memory address
<>	144:ef7eb2e8f9f7	5038	* @param MemAddSize Size of internal memory address
<>	144:ef7eb2e8f9f7	5039	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5040	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5041	* @retval HAL status
<>	144:ef7eb2e8f9f7	5042	*/
<>	154:37f96f9d4de2	5043	static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5044	{
<>	144:ef7eb2e8f9f7	5045	/* Enable Acknowledge */
<>	154:37f96f9d4de2	5046	hi2c->Instance->CR1 \|= I2C_CR1_ACK;
<>	144:ef7eb2e8f9f7	5047
<>	144:ef7eb2e8f9f7	5048	/* Generate Start */
<>	154:37f96f9d4de2	5049	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	5050
<>	144:ef7eb2e8f9f7	5051	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	5052	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5053	{
<>	144:ef7eb2e8f9f7	5054	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5055	}
<>	144:ef7eb2e8f9f7	5056
<>	144:ef7eb2e8f9f7	5057	/* Send slave address */
<>	144:ef7eb2e8f9f7	5058	hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
<>	144:ef7eb2e8f9f7	5059
<>	144:ef7eb2e8f9f7	5060	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	5061	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5062	{
<>	144:ef7eb2e8f9f7	5063	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5064	{
<>	144:ef7eb2e8f9f7	5065	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5066	}
<>	144:ef7eb2e8f9f7	5067	else
<>	144:ef7eb2e8f9f7	5068	{
<>	144:ef7eb2e8f9f7	5069	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5070	}
<>	144:ef7eb2e8f9f7	5071	}
<>	144:ef7eb2e8f9f7	5072
<>	144:ef7eb2e8f9f7	5073	/* Clear ADDR flag */
<>	144:ef7eb2e8f9f7	5074	__HAL_I2C_CLEAR_ADDRFLAG(hi2c);
<>	144:ef7eb2e8f9f7	5075
<>	144:ef7eb2e8f9f7	5076	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	5077	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5078	{
<>	144:ef7eb2e8f9f7	5079	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5080	{
<>	144:ef7eb2e8f9f7	5081	/* Generate Stop */
<>	154:37f96f9d4de2	5082	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5083	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5084	}
<>	144:ef7eb2e8f9f7	5085	else
<>	144:ef7eb2e8f9f7	5086	{
<>	144:ef7eb2e8f9f7	5087	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5088	}
<>	144:ef7eb2e8f9f7	5089	}
<>	144:ef7eb2e8f9f7	5090
<>	144:ef7eb2e8f9f7	5091	/* If Memory address size is 8Bit */
<>	144:ef7eb2e8f9f7	5092	if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
<>	144:ef7eb2e8f9f7	5093	{
<>	144:ef7eb2e8f9f7	5094	/* Send Memory Address */
<>	144:ef7eb2e8f9f7	5095	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5096	}
<>	144:ef7eb2e8f9f7	5097	/* If Memory address size is 16Bit */
<>	144:ef7eb2e8f9f7	5098	else
<>	144:ef7eb2e8f9f7	5099	{
<>	144:ef7eb2e8f9f7	5100	/* Send MSB of Memory Address */
<>	144:ef7eb2e8f9f7	5101	hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
<>	144:ef7eb2e8f9f7	5102
<>	144:ef7eb2e8f9f7	5103	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	5104	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5105	{
<>	144:ef7eb2e8f9f7	5106	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5107	{
<>	144:ef7eb2e8f9f7	5108	/* Generate Stop */
<>	154:37f96f9d4de2	5109	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5110	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5111	}
<>	144:ef7eb2e8f9f7	5112	else
<>	144:ef7eb2e8f9f7	5113	{
<>	144:ef7eb2e8f9f7	5114	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5115	}
<>	144:ef7eb2e8f9f7	5116	}
<>	144:ef7eb2e8f9f7	5117
<>	144:ef7eb2e8f9f7	5118	/* Send LSB of Memory Address */
<>	144:ef7eb2e8f9f7	5119	hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
<>	144:ef7eb2e8f9f7	5120	}
<>	144:ef7eb2e8f9f7	5121
<>	144:ef7eb2e8f9f7	5122	/* Wait until TXE flag is set */
<>	154:37f96f9d4de2	5123	if(I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5124	{
<>	144:ef7eb2e8f9f7	5125	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5126	{
<>	144:ef7eb2e8f9f7	5127	/* Generate Stop */
<>	154:37f96f9d4de2	5128	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5129	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5130	}
<>	144:ef7eb2e8f9f7	5131	else
<>	144:ef7eb2e8f9f7	5132	{
<>	144:ef7eb2e8f9f7	5133	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5134	}
<>	144:ef7eb2e8f9f7	5135	}
<>	144:ef7eb2e8f9f7	5136
<>	144:ef7eb2e8f9f7	5137	/* Generate Restart */
<>	154:37f96f9d4de2	5138	hi2c->Instance->CR1 \|= I2C_CR1_START;
<>	144:ef7eb2e8f9f7	5139
<>	144:ef7eb2e8f9f7	5140	/* Wait until SB flag is set */
<>	154:37f96f9d4de2	5141	if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5142	{
<>	144:ef7eb2e8f9f7	5143	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5144	}
<>	144:ef7eb2e8f9f7	5145
<>	144:ef7eb2e8f9f7	5146	/* Send slave address */
<>	144:ef7eb2e8f9f7	5147	hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
<>	144:ef7eb2e8f9f7	5148
<>	144:ef7eb2e8f9f7	5149	/* Wait until ADDR flag is set */
<>	154:37f96f9d4de2	5150	if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
<>	144:ef7eb2e8f9f7	5151	{
<>	144:ef7eb2e8f9f7	5152	if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
<>	144:ef7eb2e8f9f7	5153	{
<>	144:ef7eb2e8f9f7	5154	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5155	}
<>	144:ef7eb2e8f9f7	5156	else
<>	144:ef7eb2e8f9f7	5157	{
<>	144:ef7eb2e8f9f7	5158	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5159	}
<>	144:ef7eb2e8f9f7	5160	}
<>	144:ef7eb2e8f9f7	5161
<>	144:ef7eb2e8f9f7	5162	return HAL_OK;
<>	144:ef7eb2e8f9f7	5163	}
<>	144:ef7eb2e8f9f7	5164
<>	144:ef7eb2e8f9f7	5165	/**
<>	154:37f96f9d4de2	5166	* @brief DMA I2C process complete callback.
<>	154:37f96f9d4de2	5167	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5168	* @retval None
<>	144:ef7eb2e8f9f7	5169	*/
<>	154:37f96f9d4de2	5170	static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5171	{
<>	144:ef7eb2e8f9f7	5172	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	154:37f96f9d4de2	5173
<>	154:37f96f9d4de2	5174	/* Declaration of temporary variable to prevent undefined behavior of volatile usage */
<>	154:37f96f9d4de2	5175	uint32_t CurrentState = hi2c->State;
<>	154:37f96f9d4de2	5176	uint32_t CurrentMode = hi2c->Mode;
<>	154:37f96f9d4de2	5177
<>	154:37f96f9d4de2	5178	if((CurrentState == HAL_I2C_STATE_BUSY_TX) \|\| ((CurrentState == HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE)))
<>	144:ef7eb2e8f9f7	5179	{
<>	154:37f96f9d4de2	5180	/* Disable DMA Request */
<>	154:37f96f9d4de2	5181	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	5182
<>	154:37f96f9d4de2	5183	hi2c->XferCount = 0U;
<>	154:37f96f9d4de2	5184
<>	154:37f96f9d4de2	5185	/* Enable EVT and ERR interrupt */
<>	154:37f96f9d4de2	5186	__HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT \| I2C_IT_ERR);
<>	144:ef7eb2e8f9f7	5187	}
<>	144:ef7eb2e8f9f7	5188	else
<>	144:ef7eb2e8f9f7	5189	{
<>	154:37f96f9d4de2	5190	/* Disable Acknowledge */
<>	154:37f96f9d4de2	5191	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	5192
<>	154:37f96f9d4de2	5193	/* Generate Stop */
<>	154:37f96f9d4de2	5194	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	154:37f96f9d4de2	5195
<>	154:37f96f9d4de2	5196	/* Disable Last DMA */
<>	154:37f96f9d4de2	5197	hi2c->Instance->CR2 &= ~I2C_CR2_LAST;
<>	154:37f96f9d4de2	5198
<>	154:37f96f9d4de2	5199	/* Disable DMA Request */
<>	154:37f96f9d4de2	5200	hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN;
<>	154:37f96f9d4de2	5201
<>	154:37f96f9d4de2	5202	hi2c->XferCount = 0U;
<>	154:37f96f9d4de2	5203
<>	154:37f96f9d4de2	5204	/* Check if Errors has been detected during transfer */
<>	154:37f96f9d4de2	5205	if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
<>	144:ef7eb2e8f9f7	5206	{
<>	154:37f96f9d4de2	5207	HAL_I2C_ErrorCallback(hi2c);
<>	144:ef7eb2e8f9f7	5208	}
<>	144:ef7eb2e8f9f7	5209	else
<>	144:ef7eb2e8f9f7	5210	{
<>	154:37f96f9d4de2	5211	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	5212
<>	154:37f96f9d4de2	5213	if(hi2c->Mode == HAL_I2C_MODE_MEM)
<>	154:37f96f9d4de2	5214	{
<>	154:37f96f9d4de2	5215	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5216
<>	154:37f96f9d4de2	5217	HAL_I2C_MemRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	5218	}
<>	154:37f96f9d4de2	5219	else
<>	154:37f96f9d4de2	5220	{
<>	154:37f96f9d4de2	5221	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5222
<>	154:37f96f9d4de2	5223	HAL_I2C_MasterRxCpltCallback(hi2c);
<>	154:37f96f9d4de2	5224	}
<>	144:ef7eb2e8f9f7	5225	}
<>	144:ef7eb2e8f9f7	5226	}
<>	144:ef7eb2e8f9f7	5227	}
<>	144:ef7eb2e8f9f7	5228
<>	144:ef7eb2e8f9f7	5229	/**
<>	144:ef7eb2e8f9f7	5230	* @brief DMA I2C communication error callback.
<>	154:37f96f9d4de2	5231	* @param hdma DMA handle
<>	144:ef7eb2e8f9f7	5232	* @retval None
<>	144:ef7eb2e8f9f7	5233	*/
<>	144:ef7eb2e8f9f7	5234	static void I2C_DMAError(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	5235	{
<>	144:ef7eb2e8f9f7	5236	I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef)((DMA_HandleTypeDef)hdma)->Parent;
<>	154:37f96f9d4de2	5237
<>	144:ef7eb2e8f9f7	5238	/* Disable Acknowledge */
<>	154:37f96f9d4de2	5239	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	5240
<>	154:37f96f9d4de2	5241	hi2c->XferCount = 0U;
<>	154:37f96f9d4de2	5242
<>	144:ef7eb2e8f9f7	5243	hi2c->State = HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5244	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5245
<>	144:ef7eb2e8f9f7	5246	hi2c->ErrorCode \|= HAL_I2C_ERROR_DMA;
<>	154:37f96f9d4de2	5247
<>	154:37f96f9d4de2	5248	HAL_I2C_ErrorCallback(hi2c);
<>	154:37f96f9d4de2	5249	}
<>	154:37f96f9d4de2	5250
<>	154:37f96f9d4de2	5251	/**
<>	154:37f96f9d4de2	5252	* @brief DMA I2C communication abort callback
<>	154:37f96f9d4de2	5253	* (To be called at end of DMA Abort procedure).
<>	154:37f96f9d4de2	5254	* @param hdma: DMA handle.
<>	154:37f96f9d4de2	5255	* @retval None
<>	154:37f96f9d4de2	5256	*/
<>	154:37f96f9d4de2	5257	static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
<>	154:37f96f9d4de2	5258	{
<>	154:37f96f9d4de2	5259	I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	154:37f96f9d4de2	5260
<>	154:37f96f9d4de2	5261	/* Disable Acknowledge */
<>	154:37f96f9d4de2	5262	hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
<>	154:37f96f9d4de2	5263
<>	154:37f96f9d4de2	5264	hi2c->XferCount = 0U;
<>	154:37f96f9d4de2	5265
<>	154:37f96f9d4de2	5266	/* Reset XferAbortCallback */
<>	154:37f96f9d4de2	5267	hi2c->hdmatx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	5268	hi2c->hdmarx->XferAbortCallback = NULL;
<>	154:37f96f9d4de2	5269
<>	154:37f96f9d4de2	5270	/* Check if come from abort from user */
<>	154:37f96f9d4de2	5271	if(hi2c->State == HAL_I2C_STATE_ABORT)
<>	154:37f96f9d4de2	5272	{
<>	154:37f96f9d4de2	5273	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	5274	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5275	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	5276
<>	154:37f96f9d4de2	5277	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	154:37f96f9d4de2	5278	__HAL_I2C_DISABLE(hi2c);
<>	154:37f96f9d4de2	5279
<>	154:37f96f9d4de2	5280	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	154:37f96f9d4de2	5281	HAL_I2C_AbortCpltCallback(hi2c);
<>	154:37f96f9d4de2	5282	}
<>	154:37f96f9d4de2	5283	else
<>	154:37f96f9d4de2	5284	{
<>	154:37f96f9d4de2	5285	hi2c->State = HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	5286	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5287
<>	154:37f96f9d4de2	5288	/* Disable I2C peripheral to prevent dummy data in buffer */
<>	154:37f96f9d4de2	5289	__HAL_I2C_DISABLE(hi2c);
<>	154:37f96f9d4de2	5290
<>	154:37f96f9d4de2	5291	/* Call the corresponding callback to inform upper layer of End of Transfer */
<>	154:37f96f9d4de2	5292	HAL_I2C_ErrorCallback(hi2c);
<>	154:37f96f9d4de2	5293	}
<>	144:ef7eb2e8f9f7	5294	}
<>	144:ef7eb2e8f9f7	5295
<>	144:ef7eb2e8f9f7	5296	/**
<>	144:ef7eb2e8f9f7	5297	* @brief This function handles I2C Communication Timeout.
<>	144:ef7eb2e8f9f7	5298	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	5299	* the configuration information for I2C module
<>	154:37f96f9d4de2	5300	* @param Flag specifies the I2C flag to check.
<>	154:37f96f9d4de2	5301	* @param Status The new Flag status (SET or RESET).
<>	144:ef7eb2e8f9f7	5302	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5303	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5304	* @retval HAL status
<>	144:ef7eb2e8f9f7	5305	*/
<>	154:37f96f9d4de2	5306	static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5307	{
<>	144:ef7eb2e8f9f7	5308	/* Wait until flag is set */
<>	154:37f96f9d4de2	5309	while((__HAL_I2C_GET_FLAG(hi2c, Flag) ? SET : RESET) == Status)
<>	144:ef7eb2e8f9f7	5310	{
<>	154:37f96f9d4de2	5311	/* Check for the Timeout */
<>	154:37f96f9d4de2	5312	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5313	{
<>	154:37f96f9d4de2	5314	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5315	{
<>	154:37f96f9d4de2	5316	hi2c->PreviousState = I2C_STATE_NONE;
<>	154:37f96f9d4de2	5317	hi2c->State= HAL_I2C_STATE_READY;
<>	154:37f96f9d4de2	5318	hi2c->Mode = HAL_I2C_MODE_NONE;
<>	154:37f96f9d4de2	5319
<>	154:37f96f9d4de2	5320	/* Process Unlocked */
<>	154:37f96f9d4de2	5321	__HAL_UNLOCK(hi2c);
<>	154:37f96f9d4de2	5322
<>	154:37f96f9d4de2	5323	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5324	}
<>	144:ef7eb2e8f9f7	5325	}
<>	144:ef7eb2e8f9f7	5326	}
<>	154:37f96f9d4de2	5327
<>	144:ef7eb2e8f9f7	5328	return HAL_OK;
<>	144:ef7eb2e8f9f7	5329	}
<>	144:ef7eb2e8f9f7	5330
<>	144:ef7eb2e8f9f7	5331	/**
<>	144:ef7eb2e8f9f7	5332	* @brief This function handles I2C Communication Timeout for Master addressing phase.
<>	144:ef7eb2e8f9f7	5333	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	154:37f96f9d4de2	5334	* the configuration information for I2C module
<>	154:37f96f9d4de2	5335	* @param Flag specifies the I2C flag to check.
<>	144:ef7eb2e8f9f7	5336	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5337	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5338	* @retval HAL status
<>	144:ef7eb2e8f9f7	5339	*/
<>	154:37f96f9d4de2	5340	static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5341	{
<>	144:ef7eb2e8f9f7	5342	while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
<>	144:ef7eb2e8f9f7	5343	{
<>	144:ef7eb2e8f9f7	5344	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5345	{
<>	144:ef7eb2e8f9f7	5346	/* Generate Stop */
<>	154:37f96f9d4de2	5347	hi2c->Instance->CR1 \|= I2C_CR1_STOP;
<>	144:ef7eb2e8f9f7	5348
<>	144:ef7eb2e8f9f7	5349	/* Clear AF Flag */
<>	144:ef7eb2e8f9f7	5350	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5351
<>	144:ef7eb2e8f9f7	5352	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	154:37f96f9d4de2	5353	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5354	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5355
<>	144:ef7eb2e8f9f7	5356	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5357	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5358
<>	144:ef7eb2e8f9f7	5359	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5360	}
<>	144:ef7eb2e8f9f7	5361
<>	144:ef7eb2e8f9f7	5362	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5363	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5364	{
<>	154:37f96f9d4de2	5365	if((Timeout == 0U)\|\|((HAL_GetTick() - Tickstart ) > Timeout))
<>	144:ef7eb2e8f9f7	5366	{
<>	154:37f96f9d4de2	5367	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5368	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5369
<>	144:ef7eb2e8f9f7	5370	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5371	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5372
<>	144:ef7eb2e8f9f7	5373	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5374	}
<>	144:ef7eb2e8f9f7	5375	}
<>	144:ef7eb2e8f9f7	5376	}
<>	144:ef7eb2e8f9f7	5377	return HAL_OK;
<>	144:ef7eb2e8f9f7	5378	}
<>	144:ef7eb2e8f9f7	5379
<>	144:ef7eb2e8f9f7	5380	/**
<>	144:ef7eb2e8f9f7	5381	* @brief This function handles I2C Communication Timeout for specific usage of TXE flag.
<>	144:ef7eb2e8f9f7	5382	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5383	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5384	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5385	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5386	* @retval HAL status
<>	144:ef7eb2e8f9f7	5387	*/
<>	154:37f96f9d4de2	5388	static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	154:37f96f9d4de2	5389	{
<>	144:ef7eb2e8f9f7	5390	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
<>	144:ef7eb2e8f9f7	5391	{
<>	144:ef7eb2e8f9f7	5392	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5393	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5394	{
<>	144:ef7eb2e8f9f7	5395	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5396	}
<>	144:ef7eb2e8f9f7	5397
<>	144:ef7eb2e8f9f7	5398	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5399	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5400	{
<>	154:37f96f9d4de2	5401	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5402	{
<>	144:ef7eb2e8f9f7	5403	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	154:37f96f9d4de2	5404	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5405	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5406
<>	144:ef7eb2e8f9f7	5407	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5408	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5409
<>	144:ef7eb2e8f9f7	5410	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5411	}
<>	144:ef7eb2e8f9f7	5412	}
<>	144:ef7eb2e8f9f7	5413	}
<>	144:ef7eb2e8f9f7	5414	return HAL_OK;
<>	144:ef7eb2e8f9f7	5415	}
<>	144:ef7eb2e8f9f7	5416
<>	144:ef7eb2e8f9f7	5417	/**
<>	144:ef7eb2e8f9f7	5418	* @brief This function handles I2C Communication Timeout for specific usage of BTF flag.
<>	144:ef7eb2e8f9f7	5419	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5420	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5421	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5422	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5423	* @retval HAL status
<>	144:ef7eb2e8f9f7	5424	*/
<>	154:37f96f9d4de2	5425	static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5426	{
<>	144:ef7eb2e8f9f7	5427	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
<>	144:ef7eb2e8f9f7	5428	{
<>	144:ef7eb2e8f9f7	5429	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5430	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5431	{
<>	144:ef7eb2e8f9f7	5432	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5433	}
<>	154:37f96f9d4de2	5434
<>	144:ef7eb2e8f9f7	5435	/* Check for the Timeout */
<>	144:ef7eb2e8f9f7	5436	if(Timeout != HAL_MAX_DELAY)
<>	144:ef7eb2e8f9f7	5437	{
<>	154:37f96f9d4de2	5438	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5439	{
<>	144:ef7eb2e8f9f7	5440	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	154:37f96f9d4de2	5441	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5442	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5443
<>	144:ef7eb2e8f9f7	5444	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5445	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5446
<>	144:ef7eb2e8f9f7	5447	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5448	}
<>	144:ef7eb2e8f9f7	5449	}
<>	144:ef7eb2e8f9f7	5450	}
<>	154:37f96f9d4de2	5451	return HAL_OK;
<>	144:ef7eb2e8f9f7	5452	}
<>	144:ef7eb2e8f9f7	5453
<>	144:ef7eb2e8f9f7	5454	/**
<>	144:ef7eb2e8f9f7	5455	* @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
<>	144:ef7eb2e8f9f7	5456	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5457	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5458	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5459	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5460	* @retval HAL status
<>	144:ef7eb2e8f9f7	5461	*/
<>	154:37f96f9d4de2	5462	static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5463	{
<>	144:ef7eb2e8f9f7	5464	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
<>	144:ef7eb2e8f9f7	5465	{
<>	144:ef7eb2e8f9f7	5466	/* Check if a NACK is detected */
<>	144:ef7eb2e8f9f7	5467	if(I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
<>	144:ef7eb2e8f9f7	5468	{
<>	144:ef7eb2e8f9f7	5469	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5470	}
<>	154:37f96f9d4de2	5471
<>	144:ef7eb2e8f9f7	5472	/* Check for the Timeout */
<>	154:37f96f9d4de2	5473	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5474	{
<>	144:ef7eb2e8f9f7	5475	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	154:37f96f9d4de2	5476	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5477	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5478
<>	144:ef7eb2e8f9f7	5479	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5480	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5481
<>	144:ef7eb2e8f9f7	5482	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5483	}
<>	144:ef7eb2e8f9f7	5484	}
<>	144:ef7eb2e8f9f7	5485	return HAL_OK;
<>	144:ef7eb2e8f9f7	5486	}
<>	144:ef7eb2e8f9f7	5487
<>	144:ef7eb2e8f9f7	5488	/**
<>	144:ef7eb2e8f9f7	5489	* @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
<>	144:ef7eb2e8f9f7	5490	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5491	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5492	* @param Timeout Timeout duration
<>	154:37f96f9d4de2	5493	* @param Tickstart Tick start value
<>	144:ef7eb2e8f9f7	5494	* @retval HAL status
<>	144:ef7eb2e8f9f7	5495	*/
<>	154:37f96f9d4de2	5496	static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
<>	144:ef7eb2e8f9f7	5497	{
<>	154:37f96f9d4de2	5498
<>	144:ef7eb2e8f9f7	5499	while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
<>	144:ef7eb2e8f9f7	5500	{
<>	144:ef7eb2e8f9f7	5501	/* Check if a STOPF is detected */
<>	144:ef7eb2e8f9f7	5502	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
<>	144:ef7eb2e8f9f7	5503	{
<>	144:ef7eb2e8f9f7	5504	/* Clear STOP Flag */
<>	144:ef7eb2e8f9f7	5505	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
<>	144:ef7eb2e8f9f7	5506
<>	144:ef7eb2e8f9f7	5507	hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
<>	154:37f96f9d4de2	5508	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5509	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5510
<>	144:ef7eb2e8f9f7	5511	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5512	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5513
<>	144:ef7eb2e8f9f7	5514	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5515	}
<>	154:37f96f9d4de2	5516
<>	144:ef7eb2e8f9f7	5517	/* Check for the Timeout */
<>	154:37f96f9d4de2	5518	if((Timeout == 0U) \|\| ((HAL_GetTick()-Tickstart) > Timeout))
<>	144:ef7eb2e8f9f7	5519	{
<>	144:ef7eb2e8f9f7	5520	hi2c->ErrorCode \|= HAL_I2C_ERROR_TIMEOUT;
<>	144:ef7eb2e8f9f7	5521	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5522
<>	144:ef7eb2e8f9f7	5523	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5524	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5525
<>	144:ef7eb2e8f9f7	5526	return HAL_TIMEOUT;
<>	144:ef7eb2e8f9f7	5527	}
<>	144:ef7eb2e8f9f7	5528	}
<>	144:ef7eb2e8f9f7	5529	return HAL_OK;
<>	144:ef7eb2e8f9f7	5530	}
<>	144:ef7eb2e8f9f7	5531
<>	144:ef7eb2e8f9f7	5532	/**
<>	144:ef7eb2e8f9f7	5533	* @brief This function handles Acknowledge failed detection during an I2C Communication.
<>	144:ef7eb2e8f9f7	5534	* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
<>	144:ef7eb2e8f9f7	5535	* the configuration information for the specified I2C.
<>	144:ef7eb2e8f9f7	5536	* @retval HAL status
<>	144:ef7eb2e8f9f7	5537	*/
<>	144:ef7eb2e8f9f7	5538	static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
<>	144:ef7eb2e8f9f7	5539	{
<>	144:ef7eb2e8f9f7	5540	if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
<>	144:ef7eb2e8f9f7	5541	{
<>	144:ef7eb2e8f9f7	5542	/* Clear NACKF Flag */
<>	144:ef7eb2e8f9f7	5543	__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
<>	144:ef7eb2e8f9f7	5544
<>	144:ef7eb2e8f9f7	5545	hi2c->ErrorCode = HAL_I2C_ERROR_AF;
<>	154:37f96f9d4de2	5546	hi2c->PreviousState = I2C_STATE_NONE;
<>	144:ef7eb2e8f9f7	5547	hi2c->State= HAL_I2C_STATE_READY;
<>	144:ef7eb2e8f9f7	5548
<>	144:ef7eb2e8f9f7	5549	/* Process Unlocked */
<>	144:ef7eb2e8f9f7	5550	__HAL_UNLOCK(hi2c);
<>	144:ef7eb2e8f9f7	5551
<>	144:ef7eb2e8f9f7	5552	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	5553	}
<>	144:ef7eb2e8f9f7	5554	return HAL_OK;
<>	144:ef7eb2e8f9f7	5555	}
<>	144:ef7eb2e8f9f7	5556	/**
<>	144:ef7eb2e8f9f7	5557	* @}
<>	144:ef7eb2e8f9f7	5558	*/
<>	144:ef7eb2e8f9f7	5559
<>	144:ef7eb2e8f9f7	5560	#endif /* HAL_I2C_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	5561
<>	144:ef7eb2e8f9f7	5562	/**
<>	144:ef7eb2e8f9f7	5563	* @}
<>	144:ef7eb2e8f9f7	5564	*/
<>	144:ef7eb2e8f9f7	5565
<>	144:ef7eb2e8f9f7	5566	/**
<>	144:ef7eb2e8f9f7	5567	* @}
<>	144:ef7eb2e8f9f7	5568	*/
<>	144:ef7eb2e8f9f7	5569
<>	144:ef7eb2e8f9f7	5570	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/