mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_gpio.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_gpio.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief GPIO HAL module driver.
AnnaBridge 165:e614a9f1c9e2 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the General Purpose Input/Output (GPIO) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + IO operation functions
AnnaBridge 165:e614a9f1c9e2 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### GPIO Peripheral features #####
AnnaBridge 165:e614a9f1c9e2 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
<> 144:ef7eb2e8f9f7 19 port bit of the General Purpose IO (GPIO) Ports, can be individually configured by software
<> 144:ef7eb2e8f9f7 20 in several modes:
<> 144:ef7eb2e8f9f7 21 (+) Input mode
<> 144:ef7eb2e8f9f7 22 (+) Analog mode
<> 144:ef7eb2e8f9f7 23 (+) Output mode
<> 144:ef7eb2e8f9f7 24 (+) Alternate function mode
<> 144:ef7eb2e8f9f7 25 (+) External interrupt/event lines
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 [..]
<> 144:ef7eb2e8f9f7 28 During and just after reset, the alternate functions and external interrupt
<> 144:ef7eb2e8f9f7 29 lines are not active and the I/O ports are configured in input floating mode.
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 [..]
<> 144:ef7eb2e8f9f7 32 All GPIO pins have weak internal pull-up and pull-down resistors, which can be
<> 144:ef7eb2e8f9f7 33 activated or not.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 [..]
<> 144:ef7eb2e8f9f7 36 In Output or Alternate mode, each IO can be configured on open-drain or push-pull
<> 144:ef7eb2e8f9f7 37 type and the IO speed can be selected depending on the VDD value.
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 [..]
<> 144:ef7eb2e8f9f7 40 All ports have external interrupt/event capability. To use external interrupt
<> 144:ef7eb2e8f9f7 41 lines, the port must be configured in input mode. All available GPIO pins are
<> 144:ef7eb2e8f9f7 42 connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 The external interrupt/event controller consists of up to 20 edge detectors in connectivity
<> 144:ef7eb2e8f9f7 46 line devices, or 19 edge detectors in other devices for generating event/interrupt requests.
<> 144:ef7eb2e8f9f7 47 Each input line can be independently configured to select the type (event or interrupt) and
<> 144:ef7eb2e8f9f7 48 the corresponding trigger event (rising or falling or both). Each line can also masked
<> 144:ef7eb2e8f9f7 49 independently. A pending register maintains the status line of the interrupt requests
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 52 ==============================================================================
AnnaBridge 165:e614a9f1c9e2 53 [..]
<> 144:ef7eb2e8f9f7 54 (#) Enable the GPIO APB2 clock using the following function : __HAL_RCC_GPIOx_CLK_ENABLE().
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
<> 144:ef7eb2e8f9f7 57 (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 58 (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
<> 144:ef7eb2e8f9f7 59 structure.
<> 144:ef7eb2e8f9f7 60 (++) In case of Output or alternate function mode selection: the speed is
<> 144:ef7eb2e8f9f7 61 configured through "Speed" member from GPIO_InitTypeDef structure
<> 144:ef7eb2e8f9f7 62 (++) Analog mode is required when a pin is to be used as ADC channel
<> 144:ef7eb2e8f9f7 63 or DAC output.
<> 144:ef7eb2e8f9f7 64 (++) In case of external interrupt/event selection the "Mode" member from
<> 144:ef7eb2e8f9f7 65 GPIO_InitTypeDef structure select the type (interrupt or event) and
<> 144:ef7eb2e8f9f7 66 the corresponding trigger event (rising or falling or both).
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
<> 144:ef7eb2e8f9f7 69 mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
<> 144:ef7eb2e8f9f7 70 HAL_NVIC_EnableIRQ().
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 (#) To set/reset the level of a pin configured in output mode use
<> 144:ef7eb2e8f9f7 75 HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 (#) During and just after reset, the alternate functions are not
<> 144:ef7eb2e8f9f7 80 active and the GPIO pins are configured in input floating mode (except JTAG
<> 144:ef7eb2e8f9f7 81 pins).
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
<> 144:ef7eb2e8f9f7 84 (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
<> 144:ef7eb2e8f9f7 85 priority over the GPIO function.
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
<> 144:ef7eb2e8f9f7 88 general purpose PD0 and PD1, respectively, when the HSE oscillator is off.
<> 144:ef7eb2e8f9f7 89 The HSE has priority over the GPIO function.
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 @endverbatim
<> 144:ef7eb2e8f9f7 92 ******************************************************************************
<> 144:ef7eb2e8f9f7 93 * @attention
<> 144:ef7eb2e8f9f7 94 *
<> 144:ef7eb2e8f9f7 95 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 98 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 99 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 100 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 101 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 102 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 103 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 104 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 105 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 106 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 107 *
<> 144:ef7eb2e8f9f7 108 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 109 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 110 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 111 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 112 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 113 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 114 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 115 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 116 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 117 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 118 *
<> 144:ef7eb2e8f9f7 119 ******************************************************************************
<> 144:ef7eb2e8f9f7 120 */
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 123 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 126 * @{
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup GPIO GPIO
<> 144:ef7eb2e8f9f7 130 * @brief GPIO HAL module driver
<> 144:ef7eb2e8f9f7 131 * @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #ifdef HAL_GPIO_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 137 /* Private define ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 138 /** @addtogroup GPIO_Private_Constants GPIO Private Constants
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
AnnaBridge 165:e614a9f1c9e2 141 #define GPIO_MODE 0x00000003U
AnnaBridge 165:e614a9f1c9e2 142 #define EXTI_MODE 0x10000000U
AnnaBridge 165:e614a9f1c9e2 143 #define GPIO_MODE_IT 0x00010000U
AnnaBridge 165:e614a9f1c9e2 144 #define GPIO_MODE_EVT 0x00020000U
AnnaBridge 165:e614a9f1c9e2 145 #define RISING_EDGE 0x00100000U
AnnaBridge 165:e614a9f1c9e2 146 #define FALLING_EDGE 0x00200000U
AnnaBridge 165:e614a9f1c9e2 147 #define GPIO_OUTPUT_TYPE 0x00000010U
AnnaBridge 165:e614a9f1c9e2 148
AnnaBridge 165:e614a9f1c9e2 149 #define GPIO_NUMBER 16U
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* Definitions for bit manipulation of CRL and CRH register */
AnnaBridge 165:e614a9f1c9e2 152 #define GPIO_CR_MODE_INPUT 0x00000000U /*!< 00: Input mode (reset state) */
AnnaBridge 165:e614a9f1c9e2 153 #define GPIO_CR_CNF_ANALOG 0x00000000U /*!< 00: Analog mode */
AnnaBridge 165:e614a9f1c9e2 154 #define GPIO_CR_CNF_INPUT_FLOATING 0x00000004U /*!< 01: Floating input (reset state) */
AnnaBridge 165:e614a9f1c9e2 155 #define GPIO_CR_CNF_INPUT_PU_PD 0x00000008U /*!< 10: Input with pull-up / pull-down */
AnnaBridge 165:e614a9f1c9e2 156 #define GPIO_CR_CNF_GP_OUTPUT_PP 0x00000000U /*!< 00: General purpose output push-pull */
AnnaBridge 165:e614a9f1c9e2 157 #define GPIO_CR_CNF_GP_OUTPUT_OD 0x00000004U /*!< 01: General purpose output Open-drain */
AnnaBridge 165:e614a9f1c9e2 158 #define GPIO_CR_CNF_AF_OUTPUT_PP 0x00000008U /*!< 10: Alternate function output Push-pull */
AnnaBridge 165:e614a9f1c9e2 159 #define GPIO_CR_CNF_AF_OUTPUT_OD 0x0000000CU /*!< 11: Alternate function output Open-drain */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 165 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 166 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 167 /* Private functions ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 168 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 169 /** @defgroup GPIO_Exported_Functions GPIO Exported Functions
<> 144:ef7eb2e8f9f7 170 * @{
<> 144:ef7eb2e8f9f7 171 */
<> 144:ef7eb2e8f9f7 172
AnnaBridge 165:e614a9f1c9e2 173 /** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 174 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 175 *
<> 144:ef7eb2e8f9f7 176 @verbatim
<> 144:ef7eb2e8f9f7 177 ===============================================================================
AnnaBridge 165:e614a9f1c9e2 178 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 179 ===============================================================================
<> 144:ef7eb2e8f9f7 180 [..]
<> 144:ef7eb2e8f9f7 181 This section provides functions allowing to initialize and de-initialize the GPIOs
<> 144:ef7eb2e8f9f7 182 to be ready for use.
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 @endverbatim
<> 144:ef7eb2e8f9f7 185 * @{
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
AnnaBridge 165:e614a9f1c9e2 188
<> 144:ef7eb2e8f9f7 189 /**
<> 144:ef7eb2e8f9f7 190 * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
<> 144:ef7eb2e8f9f7 191 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 192 * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 193 * the configuration information for the specified GPIO peripheral.
<> 144:ef7eb2e8f9f7 194 * @retval None
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 uint32_t position;
AnnaBridge 165:e614a9f1c9e2 199 uint32_t ioposition = 0x00U;
AnnaBridge 165:e614a9f1c9e2 200 uint32_t iocurrent = 0x00U;
AnnaBridge 165:e614a9f1c9e2 201 uint32_t temp = 0x00U;
AnnaBridge 165:e614a9f1c9e2 202 uint32_t config = 0x00U;
<> 144:ef7eb2e8f9f7 203 __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
AnnaBridge 165:e614a9f1c9e2 204 uint32_t registeroffset = 0U; /* offset used during computation of CNF and MODE bits placement inside CRL or CRH register */
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /* Check the parameters */
<> 144:ef7eb2e8f9f7 207 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 208 assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
<> 144:ef7eb2e8f9f7 209 assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Configure the port pins */
AnnaBridge 165:e614a9f1c9e2 212 for (position = 0U; position < GPIO_NUMBER; position++)
<> 144:ef7eb2e8f9f7 213 {
<> 144:ef7eb2e8f9f7 214 /* Get the IO position */
AnnaBridge 165:e614a9f1c9e2 215 ioposition = (0x01U << position);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Get the current IO position */
<> 144:ef7eb2e8f9f7 218 iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 if (iocurrent == ioposition)
<> 144:ef7eb2e8f9f7 221 {
<> 144:ef7eb2e8f9f7 222 /* Check the Alternate function parameters */
<> 144:ef7eb2e8f9f7 223 assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
<> 144:ef7eb2e8f9f7 226 switch (GPIO_Init->Mode)
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 /* If we are configuring the pin in OUTPUT push-pull mode */
<> 144:ef7eb2e8f9f7 229 case GPIO_MODE_OUTPUT_PP:
<> 144:ef7eb2e8f9f7 230 /* Check the GPIO speed parameter */
<> 144:ef7eb2e8f9f7 231 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 232 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
<> 144:ef7eb2e8f9f7 233 break;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* If we are configuring the pin in OUTPUT open-drain mode */
<> 144:ef7eb2e8f9f7 236 case GPIO_MODE_OUTPUT_OD:
<> 144:ef7eb2e8f9f7 237 /* Check the GPIO speed parameter */
<> 144:ef7eb2e8f9f7 238 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 239 config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
<> 144:ef7eb2e8f9f7 240 break;
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* If we are configuring the pin in ALTERNATE FUNCTION push-pull mode */
<> 144:ef7eb2e8f9f7 243 case GPIO_MODE_AF_PP:
<> 144:ef7eb2e8f9f7 244 /* Check the GPIO speed parameter */
<> 144:ef7eb2e8f9f7 245 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 246 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
<> 144:ef7eb2e8f9f7 247 break;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* If we are configuring the pin in ALTERNATE FUNCTION open-drain mode */
<> 144:ef7eb2e8f9f7 250 case GPIO_MODE_AF_OD:
<> 144:ef7eb2e8f9f7 251 /* Check the GPIO speed parameter */
<> 144:ef7eb2e8f9f7 252 assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
<> 144:ef7eb2e8f9f7 253 config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
<> 144:ef7eb2e8f9f7 254 break;
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* If we are configuring the pin in INPUT (also applicable to EVENT and IT mode) */
<> 144:ef7eb2e8f9f7 257 case GPIO_MODE_INPUT:
<> 144:ef7eb2e8f9f7 258 case GPIO_MODE_IT_RISING:
<> 144:ef7eb2e8f9f7 259 case GPIO_MODE_IT_FALLING:
<> 144:ef7eb2e8f9f7 260 case GPIO_MODE_IT_RISING_FALLING:
<> 144:ef7eb2e8f9f7 261 case GPIO_MODE_EVT_RISING:
<> 144:ef7eb2e8f9f7 262 case GPIO_MODE_EVT_FALLING:
<> 144:ef7eb2e8f9f7 263 case GPIO_MODE_EVT_RISING_FALLING:
<> 144:ef7eb2e8f9f7 264 /* Check the GPIO pull parameter */
<> 144:ef7eb2e8f9f7 265 assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
<> 144:ef7eb2e8f9f7 266 if(GPIO_Init->Pull == GPIO_NOPULL)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
<> 144:ef7eb2e8f9f7 269 }
<> 144:ef7eb2e8f9f7 270 else if(GPIO_Init->Pull == GPIO_PULLUP)
<> 144:ef7eb2e8f9f7 271 {
<> 144:ef7eb2e8f9f7 272 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Set the corresponding ODR bit */
<> 144:ef7eb2e8f9f7 275 GPIOx->BSRR = ioposition;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 else /* GPIO_PULLDOWN */
<> 144:ef7eb2e8f9f7 278 {
<> 144:ef7eb2e8f9f7 279 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /* Reset the corresponding ODR bit */
<> 144:ef7eb2e8f9f7 282 GPIOx->BRR = ioposition;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 break;
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* If we are configuring the pin in INPUT analog mode */
<> 144:ef7eb2e8f9f7 287 case GPIO_MODE_ANALOG:
<> 144:ef7eb2e8f9f7 288 config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
<> 144:ef7eb2e8f9f7 289 break;
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /* Parameters are checked with assert_param */
<> 144:ef7eb2e8f9f7 292 default:
<> 144:ef7eb2e8f9f7 293 break;
<> 144:ef7eb2e8f9f7 294 }
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /* Check if the current bit belongs to first half or last half of the pin count number
<> 144:ef7eb2e8f9f7 297 in order to address CRH or CRL register*/
<> 144:ef7eb2e8f9f7 298 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
AnnaBridge 165:e614a9f1c9e2 299 registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Apply the new configuration of the pin to the register */
<> 144:ef7eb2e8f9f7 302 MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), (config << registeroffset));
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /*--------------------- EXTI Mode Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 305 /* Configure the External Interrupt or event for the current IO */
<> 144:ef7eb2e8f9f7 306 if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* Enable AFIO Clock */
<> 144:ef7eb2e8f9f7 309 __HAL_RCC_AFIO_CLK_ENABLE();
AnnaBridge 165:e614a9f1c9e2 310 temp = AFIO->EXTICR[position >> 2U];
AnnaBridge 165:e614a9f1c9e2 311 CLEAR_BIT(temp, (0x0FU) << (4U * (position & 0x03U)));
AnnaBridge 165:e614a9f1c9e2 312 SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
AnnaBridge 165:e614a9f1c9e2 313 AFIO->EXTICR[position >> 2U] = temp;
<> 144:ef7eb2e8f9f7 314
<> 144:ef7eb2e8f9f7 315
<> 144:ef7eb2e8f9f7 316 /* Configure the interrupt mask */
<> 144:ef7eb2e8f9f7 317 if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 SET_BIT(EXTI->IMR, iocurrent);
<> 144:ef7eb2e8f9f7 320 }
<> 144:ef7eb2e8f9f7 321 else
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 CLEAR_BIT(EXTI->IMR, iocurrent);
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Configure the event mask */
<> 144:ef7eb2e8f9f7 327 if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
<> 144:ef7eb2e8f9f7 328 {
<> 144:ef7eb2e8f9f7 329 SET_BIT(EXTI->EMR, iocurrent);
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 else
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 CLEAR_BIT(EXTI->EMR, iocurrent);
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Enable or disable the rising trigger */
<> 144:ef7eb2e8f9f7 337 if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
<> 144:ef7eb2e8f9f7 338 {
<> 144:ef7eb2e8f9f7 339 SET_BIT(EXTI->RTSR, iocurrent);
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 else
<> 144:ef7eb2e8f9f7 342 {
<> 144:ef7eb2e8f9f7 343 CLEAR_BIT(EXTI->RTSR, iocurrent);
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable or disable the falling trigger */
<> 144:ef7eb2e8f9f7 347 if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
<> 144:ef7eb2e8f9f7 348 {
<> 144:ef7eb2e8f9f7 349 SET_BIT(EXTI->FTSR, iocurrent);
<> 144:ef7eb2e8f9f7 350 }
<> 144:ef7eb2e8f9f7 351 else
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 CLEAR_BIT(EXTI->FTSR, iocurrent);
<> 144:ef7eb2e8f9f7 354 }
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356 }
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 /**
<> 144:ef7eb2e8f9f7 361 * @brief De-initializes the GPIOx peripheral registers to their default reset values.
<> 144:ef7eb2e8f9f7 362 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 363 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 364 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 365 * @retval None
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367 void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 368 {
AnnaBridge 165:e614a9f1c9e2 369 uint32_t position = 0x00U;
AnnaBridge 165:e614a9f1c9e2 370 uint32_t iocurrent = 0x00U;
AnnaBridge 165:e614a9f1c9e2 371 uint32_t tmp = 0x00U;
<> 144:ef7eb2e8f9f7 372 __IO uint32_t *configregister; /* Store the address of CRL or CRH register based on pin number */
AnnaBridge 165:e614a9f1c9e2 373 uint32_t registeroffset = 0U;
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Check the parameters */
<> 144:ef7eb2e8f9f7 376 assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 377 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /* Configure the port pins */
AnnaBridge 165:e614a9f1c9e2 380 while ((GPIO_Pin >> position) != 0U)
<> 144:ef7eb2e8f9f7 381 {
<> 144:ef7eb2e8f9f7 382 /* Get current io position */
AnnaBridge 165:e614a9f1c9e2 383 iocurrent = (GPIO_Pin) & (1U << position);
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 if (iocurrent)
<> 144:ef7eb2e8f9f7 386 {
<> 144:ef7eb2e8f9f7 387 /*------------------------- GPIO Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 388 /* Check if the current bit belongs to first half or last half of the pin count number
<> 144:ef7eb2e8f9f7 389 in order to address CRH or CRL register */
<> 144:ef7eb2e8f9f7 390 configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL : &GPIOx->CRH;
AnnaBridge 165:e614a9f1c9e2 391 registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2U) : ((position - 8U) << 2U);
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* CRL/CRH default value is floating input(0x04) shifted to correct position */
<> 144:ef7eb2e8f9f7 394 MODIFY_REG(*configregister, ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset ), GPIO_CRL_CNF0_0 << registeroffset);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* ODR default value is 0 */
<> 144:ef7eb2e8f9f7 397 CLEAR_BIT(GPIOx->ODR, iocurrent);
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /*------------------------- EXTI Mode Configuration --------------------*/
<> 144:ef7eb2e8f9f7 400 /* Clear the External Interrupt or Event for the current IO */
<> 144:ef7eb2e8f9f7 401
AnnaBridge 165:e614a9f1c9e2 402 tmp = AFIO->EXTICR[position >> 2U];
AnnaBridge 165:e614a9f1c9e2 403 tmp &= 0x0FU << (4U * (position & 0x03U));
AnnaBridge 165:e614a9f1c9e2 404 if(tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))))
<> 144:ef7eb2e8f9f7 405 {
AnnaBridge 165:e614a9f1c9e2 406 tmp = 0x0FU << (4U * (position & 0x03U));
AnnaBridge 165:e614a9f1c9e2 407 CLEAR_BIT(AFIO->EXTICR[position >> 2U], tmp);
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /* Clear EXTI line configuration */
<> 144:ef7eb2e8f9f7 410 CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 411 CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Clear Rising Falling edge configuration */
<> 144:ef7eb2e8f9f7 414 CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 415 CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 position++;
<> 144:ef7eb2e8f9f7 420 }
<> 144:ef7eb2e8f9f7 421 }
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @}
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
AnnaBridge 165:e614a9f1c9e2 428 * @brief GPIO Read and Write
<> 144:ef7eb2e8f9f7 429 *
AnnaBridge 165:e614a9f1c9e2 430 @verbatim
<> 144:ef7eb2e8f9f7 431 ===============================================================================
<> 144:ef7eb2e8f9f7 432 ##### IO operation functions #####
<> 144:ef7eb2e8f9f7 433 ===============================================================================
<> 144:ef7eb2e8f9f7 434 [..]
<> 144:ef7eb2e8f9f7 435 This subsection provides a set of functions allowing to manage the GPIOs.
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 @endverbatim
<> 144:ef7eb2e8f9f7 438 * @{
<> 144:ef7eb2e8f9f7 439 */
AnnaBridge 165:e614a9f1c9e2 440
<> 144:ef7eb2e8f9f7 441 /**
<> 144:ef7eb2e8f9f7 442 * @brief Reads the specified input port pin.
<> 144:ef7eb2e8f9f7 443 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 444 * @param GPIO_Pin: specifies the port bit to read.
<> 144:ef7eb2e8f9f7 445 * This parameter can be GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 446 * @retval The input port pin value.
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 GPIO_PinState bitstatus;
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 456 {
<> 144:ef7eb2e8f9f7 457 bitstatus = GPIO_PIN_SET;
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459 else
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 bitstatus = GPIO_PIN_RESET;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463 return bitstatus;
<> 144:ef7eb2e8f9f7 464 }
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @brief Sets or clears the selected data port bit.
<> 144:ef7eb2e8f9f7 468 *
<> 144:ef7eb2e8f9f7 469 * @note This function uses GPIOx_BSRR register to allow atomic read/modify
<> 144:ef7eb2e8f9f7 470 * accesses. In this way, there is no risk of an IRQ occurring between
<> 144:ef7eb2e8f9f7 471 * the read and the modify access.
<> 144:ef7eb2e8f9f7 472 *
<> 144:ef7eb2e8f9f7 473 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 474 * @param GPIO_Pin: specifies the port bit to be written.
<> 144:ef7eb2e8f9f7 475 * This parameter can be one of GPIO_PIN_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 476 * @param PinState: specifies the value to be written to the selected bit.
<> 144:ef7eb2e8f9f7 477 * This parameter can be one of the GPIO_PinState enum values:
<> 144:ef7eb2e8f9f7 478 * @arg GPIO_BIT_RESET: to clear the port pin
<> 144:ef7eb2e8f9f7 479 * @arg GPIO_BIT_SET: to set the port pin
<> 144:ef7eb2e8f9f7 480 * @retval None
<> 144:ef7eb2e8f9f7 481 */
<> 144:ef7eb2e8f9f7 482 void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 /* Check the parameters */
<> 144:ef7eb2e8f9f7 485 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 486 assert_param(IS_GPIO_PIN_ACTION(PinState));
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 if(PinState != GPIO_PIN_RESET)
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 GPIOx->BSRR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 else
<> 144:ef7eb2e8f9f7 493 {
AnnaBridge 165:e614a9f1c9e2 494 GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
<> 144:ef7eb2e8f9f7 495 }
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Toggles the specified GPIO pin
<> 144:ef7eb2e8f9f7 500 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 501 * @param GPIO_Pin: Specifies the pins to be toggled.
<> 144:ef7eb2e8f9f7 502 * @retval None
<> 144:ef7eb2e8f9f7 503 */
<> 144:ef7eb2e8f9f7 504 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 /* Check the parameters */
<> 144:ef7eb2e8f9f7 507 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 GPIOx->ODR ^= GPIO_Pin;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 /**
<> 144:ef7eb2e8f9f7 513 * @brief Locks GPIO Pins configuration registers.
<> 144:ef7eb2e8f9f7 514 * @note The locking mechanism allows the IO configuration to be frozen. When the LOCK sequence
<> 144:ef7eb2e8f9f7 515 * has been applied on a port bit, it is no longer possible to modify the value of the port bit until
<> 144:ef7eb2e8f9f7 516 * the next reset.
<> 144:ef7eb2e8f9f7 517 * @param GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral
<> 144:ef7eb2e8f9f7 518 * @param GPIO_Pin: specifies the port bit to be locked.
<> 144:ef7eb2e8f9f7 519 * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
<> 144:ef7eb2e8f9f7 520 * @retval None
<> 144:ef7eb2e8f9f7 521 */
<> 144:ef7eb2e8f9f7 522 HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 __IO uint32_t tmp = GPIO_LCKR_LCKK;
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Check the parameters */
<> 144:ef7eb2e8f9f7 527 assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
<> 144:ef7eb2e8f9f7 528 assert_param(IS_GPIO_PIN(GPIO_Pin));
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 /* Apply lock key write sequence */
<> 144:ef7eb2e8f9f7 531 SET_BIT(tmp, GPIO_Pin);
<> 144:ef7eb2e8f9f7 532 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 533 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 534 /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 535 GPIOx->LCKR = GPIO_Pin;
<> 144:ef7eb2e8f9f7 536 /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
<> 144:ef7eb2e8f9f7 537 GPIOx->LCKR = tmp;
<> 144:ef7eb2e8f9f7 538 /* Read LCKK bit*/
<> 144:ef7eb2e8f9f7 539 tmp = GPIOx->LCKR;
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 return HAL_OK;
<> 144:ef7eb2e8f9f7 544 }
<> 144:ef7eb2e8f9f7 545 else
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 }
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 /**
AnnaBridge 165:e614a9f1c9e2 552 * @brief This function handles EXTI interrupt request.
AnnaBridge 165:e614a9f1c9e2 553 * @param GPIO_Pin: Specifies the pins connected EXTI line
<> 144:ef7eb2e8f9f7 554 * @retval None
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 /* EXTI line interrupt detected */
AnnaBridge 165:e614a9f1c9e2 559 if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
AnnaBridge 165:e614a9f1c9e2 560 {
<> 144:ef7eb2e8f9f7 561 __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
<> 144:ef7eb2e8f9f7 562 HAL_GPIO_EXTI_Callback(GPIO_Pin);
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564 }
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /**
AnnaBridge 165:e614a9f1c9e2 567 * @brief EXTI line detection callbacks.
AnnaBridge 165:e614a9f1c9e2 568 * @param GPIO_Pin: Specifies the pins connected EXTI line
<> 144:ef7eb2e8f9f7 569 * @retval None
<> 144:ef7eb2e8f9f7 570 */
<> 144:ef7eb2e8f9f7 571 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
<> 144:ef7eb2e8f9f7 572 {
<> 144:ef7eb2e8f9f7 573 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 574 UNUSED(GPIO_Pin);
AnnaBridge 165:e614a9f1c9e2 575 /* NOTE: This function Should not be modified, when the callback is needed,
AnnaBridge 165:e614a9f1c9e2 576 the HAL_GPIO_EXTI_Callback could be implemented in the user file
AnnaBridge 165:e614a9f1c9e2 577 */
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /**
<> 144:ef7eb2e8f9f7 585 * @}
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #endif /* HAL_GPIO_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 589 /**
<> 144:ef7eb2e8f9f7 590 * @}
<> 144:ef7eb2e8f9f7 591 */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /**
<> 144:ef7eb2e8f9f7 594 * @}
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/