mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_IAR/startup_MKL25Z4.S@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************
<> 144:ef7eb2e8f9f7 2 *
<> 144:ef7eb2e8f9f7 3 * Copyright 2012 IAR Systems. All rights reserved.
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * $Revision: 16 $
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 **************************************************/
<> 144:ef7eb2e8f9f7 8
<> 144:ef7eb2e8f9f7 9 ;
<> 144:ef7eb2e8f9f7 10 ; The modules in this file are included in the libraries, and may be replaced
<> 144:ef7eb2e8f9f7 11 ; by any user-defined modules that define the PUBLIC symbol _program_start or
<> 144:ef7eb2e8f9f7 12 ; a user defined start symbol.
<> 144:ef7eb2e8f9f7 13 ; To override the cstartup defined in the library, simply add your modified
<> 144:ef7eb2e8f9f7 14 ; version to the workbench project.
<> 144:ef7eb2e8f9f7 15 ;
<> 144:ef7eb2e8f9f7 16 ; The vector table is normally located at address 0.
<> 144:ef7eb2e8f9f7 17 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
<> 144:ef7eb2e8f9f7 18 ; The name "__vector_table" has special meaning for C-SPY:
<> 144:ef7eb2e8f9f7 19 ; it is where the SP start value is found, and the NVIC vector
<> 144:ef7eb2e8f9f7 20 ; table register (VTOR) is initialized to this address if != 0.
<> 144:ef7eb2e8f9f7 21 ;
<> 144:ef7eb2e8f9f7 22 ; Cortex-M version
<> 144:ef7eb2e8f9f7 23 ;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 MODULE ?cstartup
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 ;; Forward declaration of sections.
<> 144:ef7eb2e8f9f7 28 SECTION CSTACK:DATA:NOROOT(3)
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 SECTION .intvec:CODE:ROOT(2)
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 EXTERN __iar_program_start
<> 144:ef7eb2e8f9f7 33 EXTERN SystemInit
<> 144:ef7eb2e8f9f7 34 PUBLIC __vector_table
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 DATA
<> 144:ef7eb2e8f9f7 37 __vector_table
<> 144:ef7eb2e8f9f7 38 DCD sfe(CSTACK) ; Top of Stack
<> 144:ef7eb2e8f9f7 39 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 40 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 41 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 42 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 43 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 44 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 45 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 46 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 47 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 48 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 49 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 50 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 51 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 52 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 53 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 54 ; External Interrupts
<> 144:ef7eb2e8f9f7 55 DCD DMA0_IRQHandler ; 0: DMA Channel 0 transfer complete intertrupt
<> 144:ef7eb2e8f9f7 56 DCD DMA1_IRQHandler ; 1: DMA Channel 1 transfer complete intertrupt
<> 144:ef7eb2e8f9f7 57 DCD DMA2_IRQHandler ; 2: DMA Channel 2 transfer complete intertrupt
<> 144:ef7eb2e8f9f7 58 DCD DMA3_IRQHandler ; 3: DMA Channel 3 transfer complete intertrupt
<> 144:ef7eb2e8f9f7 59 DCD 0 ; 4: Reserved DMA Channel 5 transfer complete intertrupt
<> 144:ef7eb2e8f9f7 60 DCD FTFA_IRQHandler ; 5: FTFA
<> 144:ef7eb2e8f9f7 61 DCD LVD_LVW_IRQHandler ; 6: Low-voltage detect, low-voltage warning
<> 144:ef7eb2e8f9f7 62 DCD LLW_IRQHandler ; 7: Low Leakage Wakeup
<> 144:ef7eb2e8f9f7 63 DCD I2C0_IRQHandler ; 8: IIC 0 interrupt
<> 144:ef7eb2e8f9f7 64 DCD I2C1_IRQHandler ; 9: IIC 1 intertrupt
<> 144:ef7eb2e8f9f7 65 DCD SPI0_IRQHandler ;10: SPI0 intertrupt
<> 144:ef7eb2e8f9f7 66 DCD SPI1_IRQHandler ;11: SPI1 intertrupt
<> 144:ef7eb2e8f9f7 67 DCD UART0_IRQHandler ;12: UART 0 status and error intertrupt
<> 144:ef7eb2e8f9f7 68 DCD UART1_IRQHandler ;13: UART 1 status and error intertrupt
<> 144:ef7eb2e8f9f7 69 DCD UART2_IRQHandler ;14: UART 2 status and error intertrupt
<> 144:ef7eb2e8f9f7 70 DCD ADC0_IRQHandler ;15: ADC 0 interrupt
<> 144:ef7eb2e8f9f7 71 DCD CMP0_IRQHandler ;16: CMP 0 interrupt
<> 144:ef7eb2e8f9f7 72 DCD TPM0_IRQHandler ;17: TPM 0 interrupt
<> 144:ef7eb2e8f9f7 73 DCD TPM1_IRQHandler ;18: TPM 1 interrupt
<> 144:ef7eb2e8f9f7 74 DCD TPM2_IRQHandler ;19: TPM 2 interrupt
<> 144:ef7eb2e8f9f7 75 DCD RTC_IRQHandler ;20: RTC Alarm interrupt
<> 144:ef7eb2e8f9f7 76 DCD RTC_Seconds_IRQHandler ;21: RTC Seconds interrupt
<> 144:ef7eb2e8f9f7 77 DCD PIT_IRQHandler ;22: PIT Single interrupt vector for all channels
<> 144:ef7eb2e8f9f7 78 DCD 0 ;23: Reserved
<> 144:ef7eb2e8f9f7 79 DCD USB0_IRQHandler ;24: USB OTG intertrupt
<> 144:ef7eb2e8f9f7 80 DCD DAC0_IRQHandler ;25: UART 0 status intertrupt
<> 144:ef7eb2e8f9f7 81 DCD TSI0_IRQHandler ;26: TSI 0 interrupt
<> 144:ef7eb2e8f9f7 82 DCD MCG_IRQHandler ;27: MCG intertrupt
<> 144:ef7eb2e8f9f7 83 DCD LPTimer_IRQHandler ;28: LPTMR0 intertrupt
<> 144:ef7eb2e8f9f7 84 DCD 0 ;29: Reserved
<> 144:ef7eb2e8f9f7 85 DCD PORTA_IRQHandler ;30: PORT A interrupt
<> 144:ef7eb2e8f9f7 86 DCD PORTD_IRQHandler ;31: PORT D interrupt
<> 144:ef7eb2e8f9f7 87 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 88 ;;Flash Configuration
<> 144:ef7eb2e8f9f7 89 ;;16-byte flash configuration field that stores default protection settings (loaded on reset)
<> 144:ef7eb2e8f9f7 90 ;;and security information that allows the MCU to restrict acces to the FTFL module.
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 BackDoorK0 EQU 0xFF
<> 144:ef7eb2e8f9f7 93 BackDoorK1 EQU 0xFF
<> 144:ef7eb2e8f9f7 94 BackDoorK2 EQU 0xFF
<> 144:ef7eb2e8f9f7 95 BackDoorK3 EQU 0xFF
<> 144:ef7eb2e8f9f7 96 BackDoorK4 EQU 0xFF
<> 144:ef7eb2e8f9f7 97 BackDoorK5 EQU 0xFF
<> 144:ef7eb2e8f9f7 98 BackDoorK6 EQU 0xFF
<> 144:ef7eb2e8f9f7 99 BackDoorK7 EQU 0xFF
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 nFPROT0 EQU 0x00
<> 144:ef7eb2e8f9f7 102 FPROT0 EQU nFPROT0^0xFF
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 nFPROT1 EQU 0x00
<> 144:ef7eb2e8f9f7 105 FPROT1 EQU nFPROT1^0xFF
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 nFPROT2 EQU 0x00
<> 144:ef7eb2e8f9f7 108 FPROT2 EQU nFPROT2^0xFF
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 nFPROT3 EQU 0x00
<> 144:ef7eb2e8f9f7 111 FPROT3 EQU nFPROT3^0xFF
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 FOPT EQU 0xFF
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 FSEC EQU 0xFE
<> 144:ef7eb2e8f9f7 116 SECTION FlashConfig:CONST:REORDER:ROOT(2)
<> 144:ef7eb2e8f9f7 117 Config:
<> 144:ef7eb2e8f9f7 118 DATA
<> 144:ef7eb2e8f9f7 119 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
<> 144:ef7eb2e8f9f7 120 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
<> 144:ef7eb2e8f9f7 121 DCB FPROT0, FPROT1, FPROT2, FPROT3
<> 144:ef7eb2e8f9f7 122 DCB FSEC, FOPT, 0xFF, 0xFF
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
<> 144:ef7eb2e8f9f7 126 ;;
<> 144:ef7eb2e8f9f7 127 ;; Default interrupt handlers.
<> 144:ef7eb2e8f9f7 128 ;;
<> 144:ef7eb2e8f9f7 129 THUMB
<> 144:ef7eb2e8f9f7 130 PUBWEAK Reset_Handler
<> 144:ef7eb2e8f9f7 131 SECTION .text:CODE:NOROOT:REORDER(2)
<> 144:ef7eb2e8f9f7 132 Reset_Handler
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 135 BLX R0
<> 144:ef7eb2e8f9f7 136 LDR R0, =__iar_program_start
<> 144:ef7eb2e8f9f7 137 BX R0
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 PUBWEAK NMI_Handler
<> 144:ef7eb2e8f9f7 140 PUBWEAK HardFault_Handler
<> 144:ef7eb2e8f9f7 141 PUBWEAK SVC_Handler
<> 144:ef7eb2e8f9f7 142 PUBWEAK PendSV_Handler
<> 144:ef7eb2e8f9f7 143 PUBWEAK SysTick_Handler
<> 144:ef7eb2e8f9f7 144 PUBWEAK DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 145 PUBWEAK DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 146 PUBWEAK DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 147 PUBWEAK DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 148 PUBWEAK FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 149 PUBWEAK LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 150 PUBWEAK LLW_IRQHandler
<> 144:ef7eb2e8f9f7 151 PUBWEAK I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 152 PUBWEAK I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 153 PUBWEAK SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 154 PUBWEAK SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 155 PUBWEAK UART0_IRQHandler
<> 144:ef7eb2e8f9f7 156 PUBWEAK UART1_IRQHandler
<> 144:ef7eb2e8f9f7 157 PUBWEAK UART2_IRQHandler
<> 144:ef7eb2e8f9f7 158 PUBWEAK ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 159 PUBWEAK CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 160 PUBWEAK TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 161 PUBWEAK TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 162 PUBWEAK TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 163 PUBWEAK RTC_IRQHandler
<> 144:ef7eb2e8f9f7 164 PUBWEAK RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 165 PUBWEAK PIT_IRQHandler
<> 144:ef7eb2e8f9f7 166 PUBWEAK USB0_IRQHandler
<> 144:ef7eb2e8f9f7 167 PUBWEAK DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 168 PUBWEAK TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 169 PUBWEAK MCG_IRQHandler
<> 144:ef7eb2e8f9f7 170 PUBWEAK LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 171 PUBWEAK PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 172 PUBWEAK PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 SECTION .text:CODE:REORDER:NOROOT(1)
<> 144:ef7eb2e8f9f7 175 THUMB
<> 144:ef7eb2e8f9f7 176 NMI_Handler
<> 144:ef7eb2e8f9f7 177 HardFault_Handler
<> 144:ef7eb2e8f9f7 178 SVC_Handler
<> 144:ef7eb2e8f9f7 179 PendSV_Handler
<> 144:ef7eb2e8f9f7 180 SysTick_Handler
<> 144:ef7eb2e8f9f7 181 DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 182 DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 183 DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 184 DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 185 FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 186 LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 187 LLW_IRQHandler
<> 144:ef7eb2e8f9f7 188 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 189 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 190 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 191 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 192 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 193 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 194 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 195 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 196 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 197 TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 198 TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 199 TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 200 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 201 RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 202 PIT_IRQHandler
<> 144:ef7eb2e8f9f7 203 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 204 DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 205 TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 206 MCG_IRQHandler
<> 144:ef7eb2e8f9f7 207 LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 208 PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 209 PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 210 Default_Handler
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 B Default_Handler
<> 144:ef7eb2e8f9f7 213 END