mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL25Z4.S@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 ;/*****************************************************************************
<> 144:ef7eb2e8f9f7 2 ; * @file: startup_MKL25Z4.s
<> 144:ef7eb2e8f9f7 3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
<> 144:ef7eb2e8f9f7 4 ; * MKL25Z4
<> 144:ef7eb2e8f9f7 5 ; * @version: 1.1
<> 144:ef7eb2e8f9f7 6 ; * @date: 2012-6-21
<> 144:ef7eb2e8f9f7 7 ; *
<> 144:ef7eb2e8f9f7 8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
<> 144:ef7eb2e8f9f7 9 ;*
<> 144:ef7eb2e8f9f7 10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
<> 144:ef7eb2e8f9f7 11 ; *
<> 144:ef7eb2e8f9f7 12 ; *****************************************************************************/
<> 144:ef7eb2e8f9f7 13
<> 144:ef7eb2e8f9f7 14
<> 144:ef7eb2e8f9f7 15 ; <h> Stack Configuration
<> 144:ef7eb2e8f9f7 16 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
<> 144:ef7eb2e8f9f7 17 ; </h>
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 Stack_Size EQU 0x00000400
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 AREA STACK, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 22 EXPORT __initial_sp
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 Stack_Mem SPACE Stack_Size
<> 144:ef7eb2e8f9f7 25 __initial_sp EQU 0x20003000 ; Top of RAM
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 Heap_Size EQU 0x00000000
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 AREA HEAP, NOINIT, READWRITE, ALIGN=3
<> 144:ef7eb2e8f9f7 31 EXPORT __heap_base
<> 144:ef7eb2e8f9f7 32 EXPORT __heap_limit
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 __heap_base
<> 144:ef7eb2e8f9f7 35 Heap_Mem SPACE Heap_Size
<> 144:ef7eb2e8f9f7 36 __heap_limit
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 PRESERVE8
<> 144:ef7eb2e8f9f7 39 THUMB
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 ; Vector Table Mapped to Address 0 at Reset
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 AREA RESET, DATA, READONLY
<> 144:ef7eb2e8f9f7 45 EXPORT __Vectors
<> 144:ef7eb2e8f9f7 46 EXPORT __Vectors_End
<> 144:ef7eb2e8f9f7 47 EXPORT __Vectors_Size
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 __Vectors DCD __initial_sp ; Top of Stack
<> 144:ef7eb2e8f9f7 50 DCD Reset_Handler ; Reset Handler
<> 144:ef7eb2e8f9f7 51 DCD NMI_Handler ; NMI Handler
<> 144:ef7eb2e8f9f7 52 DCD HardFault_Handler ; Hard Fault Handler
<> 144:ef7eb2e8f9f7 53 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 54 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 55 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 56 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 57 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 58 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 59 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 60 DCD SVC_Handler ; SVCall Handler
<> 144:ef7eb2e8f9f7 61 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 62 DCD 0 ; Reserved
<> 144:ef7eb2e8f9f7 63 DCD PendSV_Handler ; PendSV Handler
<> 144:ef7eb2e8f9f7 64 DCD SysTick_Handler ; SysTick Handler
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 ; External Interrupts
<> 144:ef7eb2e8f9f7 67 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
<> 144:ef7eb2e8f9f7 68 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
<> 144:ef7eb2e8f9f7 69 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
<> 144:ef7eb2e8f9f7 70 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
<> 144:ef7eb2e8f9f7 71 DCD Reserved20_IRQHandler ; Reserved interrupt 20
<> 144:ef7eb2e8f9f7 72 DCD FTFA_IRQHandler ; FTFA interrupt
<> 144:ef7eb2e8f9f7 73 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
<> 144:ef7eb2e8f9f7 74 DCD LLW_IRQHandler ; Low Leakage Wakeup
<> 144:ef7eb2e8f9f7 75 DCD I2C0_IRQHandler ; I2C0 interrupt
<> 144:ef7eb2e8f9f7 76 DCD I2C1_IRQHandler ; I2C0 interrupt 25
<> 144:ef7eb2e8f9f7 77 DCD SPI0_IRQHandler ; SPI0 interrupt
<> 144:ef7eb2e8f9f7 78 DCD SPI1_IRQHandler ; SPI1 interrupt
<> 144:ef7eb2e8f9f7 79 DCD UART0_IRQHandler ; UART0 status/error interrupt
<> 144:ef7eb2e8f9f7 80 DCD UART1_IRQHandler ; UART1 status/error interrupt
<> 144:ef7eb2e8f9f7 81 DCD UART2_IRQHandler ; UART2 status/error interrupt
<> 144:ef7eb2e8f9f7 82 DCD ADC0_IRQHandler ; ADC0 interrupt
<> 144:ef7eb2e8f9f7 83 DCD CMP0_IRQHandler ; CMP0 interrupt
<> 144:ef7eb2e8f9f7 84 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 85 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 86 DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
<> 144:ef7eb2e8f9f7 87 DCD RTC_IRQHandler ; RTC interrupt
<> 144:ef7eb2e8f9f7 88 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
<> 144:ef7eb2e8f9f7 89 DCD PIT_IRQHandler ; PIT timer interrupt
<> 144:ef7eb2e8f9f7 90 DCD Reserved39_IRQHandler ; Reserved interrupt 39
<> 144:ef7eb2e8f9f7 91 DCD USB0_IRQHandler ; USB0 interrupt
<> 144:ef7eb2e8f9f7 92 DCD DAC0_IRQHandler ; DAC interrupt
<> 144:ef7eb2e8f9f7 93 DCD TSI0_IRQHandler ; TSI0 interrupt
<> 144:ef7eb2e8f9f7 94 DCD MCG_IRQHandler ; MCG interrupt
<> 144:ef7eb2e8f9f7 95 DCD LPTimer_IRQHandler ; LPTimer interrupt
<> 144:ef7eb2e8f9f7 96 DCD Reserved45_IRQHandler ; Reserved interrupt 45
<> 144:ef7eb2e8f9f7 97 DCD PORTA_IRQHandler ; Port A interrupt
<> 144:ef7eb2e8f9f7 98 DCD PORTD_IRQHandler ; Port D interrupt
<> 144:ef7eb2e8f9f7 99 __Vectors_End
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 __Vectors_Size EQU __Vectors_End - __Vectors
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 ; <h> Flash Configuration
<> 144:ef7eb2e8f9f7 104 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
<> 144:ef7eb2e8f9f7 105 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
<> 144:ef7eb2e8f9f7 106 ; <h> Backdoor Comparison Key
<> 144:ef7eb2e8f9f7 107 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 108 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 109 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 110 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 111 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 112 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 113 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 114 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
<> 144:ef7eb2e8f9f7 115 BackDoorK0 EQU 0xFF
<> 144:ef7eb2e8f9f7 116 BackDoorK1 EQU 0xFF
<> 144:ef7eb2e8f9f7 117 BackDoorK2 EQU 0xFF
<> 144:ef7eb2e8f9f7 118 BackDoorK3 EQU 0xFF
<> 144:ef7eb2e8f9f7 119 BackDoorK4 EQU 0xFF
<> 144:ef7eb2e8f9f7 120 BackDoorK5 EQU 0xFF
<> 144:ef7eb2e8f9f7 121 BackDoorK6 EQU 0xFF
<> 144:ef7eb2e8f9f7 122 BackDoorK7 EQU 0xFF
<> 144:ef7eb2e8f9f7 123 ; </h>
<> 144:ef7eb2e8f9f7 124 ; <h> Program flash protection bytes (FPROT)
<> 144:ef7eb2e8f9f7 125 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
<> 144:ef7eb2e8f9f7 126 ; <i> Each bit protects a 1/32 region of the program flash memory.
<> 144:ef7eb2e8f9f7 127 ; <h> FPROT0
<> 144:ef7eb2e8f9f7 128 ; <i> Program flash protection bytes
<> 144:ef7eb2e8f9f7 129 ; <i> 1/32 - 8/32 region
<> 144:ef7eb2e8f9f7 130 ; <o.0> FPROT0.0
<> 144:ef7eb2e8f9f7 131 ; <o.1> FPROT0.1
<> 144:ef7eb2e8f9f7 132 ; <o.2> FPROT0.2
<> 144:ef7eb2e8f9f7 133 ; <o.3> FPROT0.3
<> 144:ef7eb2e8f9f7 134 ; <o.4> FPROT0.4
<> 144:ef7eb2e8f9f7 135 ; <o.5> FPROT0.5
<> 144:ef7eb2e8f9f7 136 ; <o.6> FPROT0.6
<> 144:ef7eb2e8f9f7 137 ; <o.7> FPROT0.7
<> 144:ef7eb2e8f9f7 138 nFPROT0 EQU 0x00
<> 144:ef7eb2e8f9f7 139 FPROT0 EQU nFPROT0:EOR:0xFF
<> 144:ef7eb2e8f9f7 140 ; </h>
<> 144:ef7eb2e8f9f7 141 ; <h> FPROT1
<> 144:ef7eb2e8f9f7 142 ; <i> Program Flash Region Protect Register 1
<> 144:ef7eb2e8f9f7 143 ; <i> 9/32 - 16/32 region
<> 144:ef7eb2e8f9f7 144 ; <o.0> FPROT1.0
<> 144:ef7eb2e8f9f7 145 ; <o.1> FPROT1.1
<> 144:ef7eb2e8f9f7 146 ; <o.2> FPROT1.2
<> 144:ef7eb2e8f9f7 147 ; <o.3> FPROT1.3
<> 144:ef7eb2e8f9f7 148 ; <o.4> FPROT1.4
<> 144:ef7eb2e8f9f7 149 ; <o.5> FPROT1.5
<> 144:ef7eb2e8f9f7 150 ; <o.6> FPROT1.6
<> 144:ef7eb2e8f9f7 151 ; <o.7> FPROT1.7
<> 144:ef7eb2e8f9f7 152 nFPROT1 EQU 0x00
<> 144:ef7eb2e8f9f7 153 FPROT1 EQU nFPROT1:EOR:0xFF
<> 144:ef7eb2e8f9f7 154 ; </h>
<> 144:ef7eb2e8f9f7 155 ; <h> FPROT2
<> 144:ef7eb2e8f9f7 156 ; <i> Program Flash Region Protect Register 2
<> 144:ef7eb2e8f9f7 157 ; <i> 17/32 - 24/32 region
<> 144:ef7eb2e8f9f7 158 ; <o.0> FPROT2.0
<> 144:ef7eb2e8f9f7 159 ; <o.1> FPROT2.1
<> 144:ef7eb2e8f9f7 160 ; <o.2> FPROT2.2
<> 144:ef7eb2e8f9f7 161 ; <o.3> FPROT2.3
<> 144:ef7eb2e8f9f7 162 ; <o.4> FPROT2.4
<> 144:ef7eb2e8f9f7 163 ; <o.5> FPROT2.5
<> 144:ef7eb2e8f9f7 164 ; <o.6> FPROT2.6
<> 144:ef7eb2e8f9f7 165 ; <o.7> FPROT2.7
<> 144:ef7eb2e8f9f7 166 nFPROT2 EQU 0x00
<> 144:ef7eb2e8f9f7 167 FPROT2 EQU nFPROT2:EOR:0xFF
<> 144:ef7eb2e8f9f7 168 ; </h>
<> 144:ef7eb2e8f9f7 169 ; <h> FPROT3
<> 144:ef7eb2e8f9f7 170 ; <i> Program Flash Region Protect Register 3
<> 144:ef7eb2e8f9f7 171 ; <i> 25/32 - 32/32 region
<> 144:ef7eb2e8f9f7 172 ; <o.0> FPROT3.0
<> 144:ef7eb2e8f9f7 173 ; <o.1> FPROT3.1
<> 144:ef7eb2e8f9f7 174 ; <o.2> FPROT3.2
<> 144:ef7eb2e8f9f7 175 ; <o.3> FPROT3.3
<> 144:ef7eb2e8f9f7 176 ; <o.4> FPROT3.4
<> 144:ef7eb2e8f9f7 177 ; <o.5> FPROT3.5
<> 144:ef7eb2e8f9f7 178 ; <o.6> FPROT3.6
<> 144:ef7eb2e8f9f7 179 ; <o.7> FPROT3.7
<> 144:ef7eb2e8f9f7 180 nFPROT3 EQU 0x00
<> 144:ef7eb2e8f9f7 181 FPROT3 EQU nFPROT3:EOR:0xFF
<> 144:ef7eb2e8f9f7 182 ; </h>
<> 144:ef7eb2e8f9f7 183 ; </h>
<> 144:ef7eb2e8f9f7 184 ; </h>
<> 144:ef7eb2e8f9f7 185 ; <h> Flash nonvolatile option byte (FOPT)
<> 144:ef7eb2e8f9f7 186 ; <i> Allows the user to customize the operation of the MCU at boot time.
<> 144:ef7eb2e8f9f7 187 ; <o.0> LPBOOT0
<> 144:ef7eb2e8f9f7 188 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
<> 144:ef7eb2e8f9f7 189 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
<> 144:ef7eb2e8f9f7 190 ; <o.4> LPBOOT1
<> 144:ef7eb2e8f9f7 191 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
<> 144:ef7eb2e8f9f7 192 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
<> 144:ef7eb2e8f9f7 193 ; <o.2> NMI_DIS
<> 144:ef7eb2e8f9f7 194 ; <0=> NMI interrupts are always blocked
<> 144:ef7eb2e8f9f7 195 ; <1=> NMI pin/interrupts reset default to enabled
<> 144:ef7eb2e8f9f7 196 ; <o.3> RESET_PIN_CFG
<> 144:ef7eb2e8f9f7 197 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
<> 144:ef7eb2e8f9f7 198 ; <1=> RESET pin is dedicated
<> 144:ef7eb2e8f9f7 199 ; <o.3> FAST_INIT
<> 144:ef7eb2e8f9f7 200 ; <0=> Slower initialization
<> 144:ef7eb2e8f9f7 201 ; <1=> Fast Initialization
<> 144:ef7eb2e8f9f7 202 FOPT EQU 0xFF
<> 144:ef7eb2e8f9f7 203 ; </h>
<> 144:ef7eb2e8f9f7 204 ; <h> Flash security byte (FSEC)
<> 144:ef7eb2e8f9f7 205 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
<> 144:ef7eb2e8f9f7 206 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
<> 144:ef7eb2e8f9f7 207 ; <o.0..1> SEC
<> 144:ef7eb2e8f9f7 208 ; <2=> MCU security status is unsecure
<> 144:ef7eb2e8f9f7 209 ; <3=> MCU security status is secure
<> 144:ef7eb2e8f9f7 210 ; <i> Flash Security
<> 144:ef7eb2e8f9f7 211 ; <i> This bits define the security state of the MCU.
<> 144:ef7eb2e8f9f7 212 ; <o.2..3> FSLACC
<> 144:ef7eb2e8f9f7 213 ; <2=> Freescale factory access denied
<> 144:ef7eb2e8f9f7 214 ; <3=> Freescale factory access granted
<> 144:ef7eb2e8f9f7 215 ; <i> Freescale Failure Analysis Access Code
<> 144:ef7eb2e8f9f7 216 ; <i> This bits define the security state of the MCU.
<> 144:ef7eb2e8f9f7 217 ; <o.4..5> MEEN
<> 144:ef7eb2e8f9f7 218 ; <2=> Mass erase is disabled
<> 144:ef7eb2e8f9f7 219 ; <3=> Mass erase is enabled
<> 144:ef7eb2e8f9f7 220 ; <i> Mass Erase Enable Bits
<> 144:ef7eb2e8f9f7 221 ; <i> Enables and disables mass erase capability of the FTFL module
<> 144:ef7eb2e8f9f7 222 ; <o.6..7> KEYEN
<> 144:ef7eb2e8f9f7 223 ; <2=> Backdoor key access enabled
<> 144:ef7eb2e8f9f7 224 ; <3=> Backdoor key access disabled
<> 144:ef7eb2e8f9f7 225 ; <i> Backdoor key Security Enable
<> 144:ef7eb2e8f9f7 226 ; <i> These bits enable and disable backdoor key access to the FTFL module.
<> 144:ef7eb2e8f9f7 227 FSEC EQU 0xFE
<> 144:ef7eb2e8f9f7 228 ; </h>
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 IF :LNOT::DEF:RAM_TARGET
<> 144:ef7eb2e8f9f7 231 AREA |.ARM.__at_0x400|, CODE, READONLY
<> 144:ef7eb2e8f9f7 232 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
<> 144:ef7eb2e8f9f7 233 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
<> 144:ef7eb2e8f9f7 234 DCB FPROT0, FPROT1, FPROT2, FPROT3
<> 144:ef7eb2e8f9f7 235 DCB FSEC, FOPT, 0xFF, 0xFF
<> 144:ef7eb2e8f9f7 236 ENDIF
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 AREA |.text|, CODE, READONLY
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 ; Reset Handler
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 Reset_Handler PROC
<> 144:ef7eb2e8f9f7 244 EXPORT Reset_Handler [WEAK]
<> 144:ef7eb2e8f9f7 245 IMPORT SystemInit
<> 144:ef7eb2e8f9f7 246 IMPORT __main
<> 144:ef7eb2e8f9f7 247 LDR R0, =SystemInit
<> 144:ef7eb2e8f9f7 248 BLX R0
<> 144:ef7eb2e8f9f7 249 LDR R0, =__main
<> 144:ef7eb2e8f9f7 250 BX R0
<> 144:ef7eb2e8f9f7 251 ENDP
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 ; Dummy Exception Handlers (infinite loops which can be modified)
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 NMI_Handler PROC
<> 144:ef7eb2e8f9f7 257 EXPORT NMI_Handler [WEAK]
<> 144:ef7eb2e8f9f7 258 B .
<> 144:ef7eb2e8f9f7 259 ENDP
<> 144:ef7eb2e8f9f7 260 HardFault_Handler\
<> 144:ef7eb2e8f9f7 261 PROC
<> 144:ef7eb2e8f9f7 262 EXPORT HardFault_Handler [WEAK]
<> 144:ef7eb2e8f9f7 263 B .
<> 144:ef7eb2e8f9f7 264 ENDP
<> 144:ef7eb2e8f9f7 265 SVC_Handler PROC
<> 144:ef7eb2e8f9f7 266 EXPORT SVC_Handler [WEAK]
<> 144:ef7eb2e8f9f7 267 B .
<> 144:ef7eb2e8f9f7 268 ENDP
<> 144:ef7eb2e8f9f7 269 PendSV_Handler PROC
<> 144:ef7eb2e8f9f7 270 EXPORT PendSV_Handler [WEAK]
<> 144:ef7eb2e8f9f7 271 B .
<> 144:ef7eb2e8f9f7 272 ENDP
<> 144:ef7eb2e8f9f7 273 SysTick_Handler PROC
<> 144:ef7eb2e8f9f7 274 EXPORT SysTick_Handler [WEAK]
<> 144:ef7eb2e8f9f7 275 B .
<> 144:ef7eb2e8f9f7 276 ENDP
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 Default_Handler PROC
<> 144:ef7eb2e8f9f7 279 EXPORT DMA0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 280 EXPORT DMA1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 281 EXPORT DMA2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 282 EXPORT DMA3_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 283 EXPORT Reserved20_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 284 EXPORT FTFA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 285 EXPORT LVD_LVW_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 286 EXPORT LLW_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 287 EXPORT I2C0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 288 EXPORT I2C1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 289 EXPORT SPI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 290 EXPORT SPI1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 291 EXPORT UART0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 292 EXPORT UART1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 293 EXPORT UART2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 294 EXPORT ADC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 295 EXPORT CMP0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 296 EXPORT TPM0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 297 EXPORT TPM1_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 298 EXPORT TPM2_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 299 EXPORT RTC_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 300 EXPORT RTC_Seconds_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 301 EXPORT PIT_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 302 EXPORT Reserved39_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 303 EXPORT USB0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 304 EXPORT DAC0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 305 EXPORT TSI0_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 306 EXPORT MCG_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 307 EXPORT LPTimer_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 308 EXPORT Reserved45_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 309 EXPORT PORTA_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 310 EXPORT PORTD_IRQHandler [WEAK]
<> 144:ef7eb2e8f9f7 311 EXPORT DefaultISR [WEAK]
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 DMA0_IRQHandler
<> 144:ef7eb2e8f9f7 314 DMA1_IRQHandler
<> 144:ef7eb2e8f9f7 315 DMA2_IRQHandler
<> 144:ef7eb2e8f9f7 316 DMA3_IRQHandler
<> 144:ef7eb2e8f9f7 317 Reserved20_IRQHandler
<> 144:ef7eb2e8f9f7 318 FTFA_IRQHandler
<> 144:ef7eb2e8f9f7 319 LVD_LVW_IRQHandler
<> 144:ef7eb2e8f9f7 320 LLW_IRQHandler
<> 144:ef7eb2e8f9f7 321 I2C0_IRQHandler
<> 144:ef7eb2e8f9f7 322 I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 323 SPI0_IRQHandler
<> 144:ef7eb2e8f9f7 324 SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 325 UART0_IRQHandler
<> 144:ef7eb2e8f9f7 326 UART1_IRQHandler
<> 144:ef7eb2e8f9f7 327 UART2_IRQHandler
<> 144:ef7eb2e8f9f7 328 ADC0_IRQHandler
<> 144:ef7eb2e8f9f7 329 CMP0_IRQHandler
<> 144:ef7eb2e8f9f7 330 TPM0_IRQHandler
<> 144:ef7eb2e8f9f7 331 TPM1_IRQHandler
<> 144:ef7eb2e8f9f7 332 TPM2_IRQHandler
<> 144:ef7eb2e8f9f7 333 RTC_IRQHandler
<> 144:ef7eb2e8f9f7 334 RTC_Seconds_IRQHandler
<> 144:ef7eb2e8f9f7 335 PIT_IRQHandler
<> 144:ef7eb2e8f9f7 336 Reserved39_IRQHandler
<> 144:ef7eb2e8f9f7 337 USB0_IRQHandler
<> 144:ef7eb2e8f9f7 338 DAC0_IRQHandler
<> 144:ef7eb2e8f9f7 339 TSI0_IRQHandler
<> 144:ef7eb2e8f9f7 340 MCG_IRQHandler
<> 144:ef7eb2e8f9f7 341 LPTimer_IRQHandler
<> 144:ef7eb2e8f9f7 342 Reserved45_IRQHandler
<> 144:ef7eb2e8f9f7 343 PORTA_IRQHandler
<> 144:ef7eb2e8f9f7 344 PORTD_IRQHandler
<> 144:ef7eb2e8f9f7 345 DefaultISR
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 B .
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 ENDP
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 ALIGN
<> 144:ef7eb2e8f9f7 353 END