mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/system_clock.c@173:e131a1973e81, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:59:18 2017 +0100
Revision:
173:e131a1973e81
Parent:
170:19eb464bc2be
Child:
174:b96e65c34a4d
This updates the lib to the mbed lib v 151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 170:19eb464bc2be 1 /* mbed Microcontroller Library
Kojto 170:19eb464bc2be 2 * Copyright (c) 2006-2017 ARM Limited
Kojto 170:19eb464bc2be 3 *
Kojto 170:19eb464bc2be 4 * Licensed under the Apache License, Version 2.0 (the "License");
Kojto 170:19eb464bc2be 5 * you may not use this file except in compliance with the License.
Kojto 170:19eb464bc2be 6 * You may obtain a copy of the License at
Kojto 170:19eb464bc2be 7 *
Kojto 170:19eb464bc2be 8 * http://www.apache.org/licenses/LICENSE-2.0
Kojto 170:19eb464bc2be 9 *
Kojto 170:19eb464bc2be 10 * Unless required by applicable law or agreed to in writing, software
Kojto 170:19eb464bc2be 11 * distributed under the License is distributed on an "AS IS" BASIS,
Kojto 170:19eb464bc2be 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Kojto 170:19eb464bc2be 13 * See the License for the specific language governing permissions and
Kojto 170:19eb464bc2be 14 * limitations under the License.
Kojto 170:19eb464bc2be 15 */
Kojto 170:19eb464bc2be 16
Kojto 170:19eb464bc2be 17 /**
Kojto 170:19eb464bc2be 18 * This file configures the system clock as follows:
Kojto 170:19eb464bc2be 19 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
Kojto 170:19eb464bc2be 21 * | (external 24 MHz clock) | (internal 16 MHz)
Kojto 170:19eb464bc2be 22 * | 2- PLL_HSE_XTAL |
Kojto 170:19eb464bc2be 23 * | (external 24 MHz xtal) |
Kojto 170:19eb464bc2be 24 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 25 * SYSCLK(MHz) | 32 | 32
Kojto 170:19eb464bc2be 26 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 27 * AHBCLK (MHz) | 32 | 32
Kojto 170:19eb464bc2be 28 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 29 * APB1CLK (MHz) | 32 | 32
Kojto 170:19eb464bc2be 30 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 31 * APB2CLK (MHz) | 32 | 32
Kojto 170:19eb464bc2be 32 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 33 * USB capable (48 MHz precise clock) | YES | NO
Kojto 170:19eb464bc2be 34 *-----------------------------------------------------------------------------
Kojto 170:19eb464bc2be 35 ******************************************************************************
Kojto 170:19eb464bc2be 36 */
Kojto 170:19eb464bc2be 37
Kojto 170:19eb464bc2be 38 #include "stm32l1xx.h"
Kojto 170:19eb464bc2be 39 #include "stdio.h"
Kojto 170:19eb464bc2be 40
Kojto 170:19eb464bc2be 41 /*!< Uncomment the following line if you need to relocate your vector Table in
Kojto 170:19eb464bc2be 42 Internal SRAM. */
Kojto 170:19eb464bc2be 43 /* #define VECT_TAB_SRAM */
AnnaBridge 173:e131a1973e81 44 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
Kojto 170:19eb464bc2be 45 This value must be a multiple of 0x200. */
Kojto 170:19eb464bc2be 46
Kojto 170:19eb464bc2be 47 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
Kojto 170:19eb464bc2be 48 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
Kojto 170:19eb464bc2be 49 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
Kojto 170:19eb464bc2be 50
Kojto 170:19eb464bc2be 51
Kojto 170:19eb464bc2be 52 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
Kojto 170:19eb464bc2be 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
Kojto 170:19eb464bc2be 54 #endif
Kojto 170:19eb464bc2be 55
Kojto 170:19eb464bc2be 56 uint8_t SetSysClock_PLL_HSI(void);
Kojto 170:19eb464bc2be 57
Kojto 170:19eb464bc2be 58
Kojto 170:19eb464bc2be 59 /**
Kojto 170:19eb464bc2be 60 * @brief Setup the microcontroller system.
Kojto 170:19eb464bc2be 61 * Initialize the Embedded Flash Interface, the PLL and update the
Kojto 170:19eb464bc2be 62 * SystemCoreClock variable.
Kojto 170:19eb464bc2be 63 * @param None
Kojto 170:19eb464bc2be 64 * @retval None
Kojto 170:19eb464bc2be 65 */
Kojto 170:19eb464bc2be 66 void SystemInit (void)
Kojto 170:19eb464bc2be 67 {
Kojto 170:19eb464bc2be 68 /*!< Set MSION bit */
Kojto 170:19eb464bc2be 69 RCC->CR |= (uint32_t)0x00000100;
Kojto 170:19eb464bc2be 70
Kojto 170:19eb464bc2be 71 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
Kojto 170:19eb464bc2be 72 RCC->CFGR &= (uint32_t)0x88FFC00C;
Kojto 170:19eb464bc2be 73
Kojto 170:19eb464bc2be 74 /*!< Reset HSION, HSEON, CSSON and PLLON bits */
Kojto 170:19eb464bc2be 75 RCC->CR &= (uint32_t)0xEEFEFFFE;
Kojto 170:19eb464bc2be 76
Kojto 170:19eb464bc2be 77 /*!< Reset HSEBYP bit */
Kojto 170:19eb464bc2be 78 RCC->CR &= (uint32_t)0xFFFBFFFF;
Kojto 170:19eb464bc2be 79
Kojto 170:19eb464bc2be 80 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
Kojto 170:19eb464bc2be 81 RCC->CFGR &= (uint32_t)0xFF02FFFF;
Kojto 170:19eb464bc2be 82
Kojto 170:19eb464bc2be 83 /*!< Disable all interrupts */
Kojto 170:19eb464bc2be 84 RCC->CIR = 0x00000000;
Kojto 170:19eb464bc2be 85
Kojto 170:19eb464bc2be 86 #ifdef DATA_IN_ExtSRAM
Kojto 170:19eb464bc2be 87 SystemInit_ExtMemCtl();
Kojto 170:19eb464bc2be 88 #endif /* DATA_IN_ExtSRAM */
Kojto 170:19eb464bc2be 89
Kojto 170:19eb464bc2be 90
Kojto 170:19eb464bc2be 91 #if defined(__ICCARM__)
Kojto 170:19eb464bc2be 92 #pragma section=".intvec"
Kojto 170:19eb464bc2be 93 #define FLASH_VTOR_BASE ((uint32_t)__section_begin(".intvec"))
Kojto 170:19eb464bc2be 94 #elif defined(__CC_ARM)
Kojto 170:19eb464bc2be 95 extern uint32_t Load$$LR$$LR_IROM1$$Base[];
Kojto 170:19eb464bc2be 96 #define FLASH_VTOR_BASE ((uint32_t)Load$$LR$$LR_IROM1$$Base)
Kojto 170:19eb464bc2be 97 #elif defined(__GNUC__)
Kojto 170:19eb464bc2be 98 extern uint32_t g_pfnVectors[];
Kojto 170:19eb464bc2be 99 #define FLASH_VTOR_BASE ((uint32_t)g_pfnVectors)
Kojto 170:19eb464bc2be 100 #else
Kojto 170:19eb464bc2be 101 #error "Flash vector address not set for this toolchain"
Kojto 170:19eb464bc2be 102 #endif
Kojto 170:19eb464bc2be 103
Kojto 170:19eb464bc2be 104 #ifdef VECT_TAB_SRAM
Kojto 170:19eb464bc2be 105 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
Kojto 170:19eb464bc2be 106 #else
Kojto 170:19eb464bc2be 107 SCB->VTOR = FLASH_VTOR_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
Kojto 170:19eb464bc2be 108 #endif
Kojto 170:19eb464bc2be 109
Kojto 170:19eb464bc2be 110 }
Kojto 170:19eb464bc2be 111
Kojto 170:19eb464bc2be 112 /**
Kojto 170:19eb464bc2be 113 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
Kojto 170:19eb464bc2be 114 * AHB/APBx prescalers and Flash settings
Kojto 170:19eb464bc2be 115 * @note This function should be called only once the RCC clock configuration
Kojto 170:19eb464bc2be 116 * is reset to the default reset state (done in SystemInit() function).
Kojto 170:19eb464bc2be 117 * @param None
Kojto 170:19eb464bc2be 118 * @retval None
Kojto 170:19eb464bc2be 119 */
Kojto 170:19eb464bc2be 120 void SetSysClock(void)
Kojto 170:19eb464bc2be 121 {
Kojto 170:19eb464bc2be 122 /* 1- Try to start with HSE and external clock */
Kojto 170:19eb464bc2be 123 #if USE_PLL_HSE_EXTC != 0
Kojto 170:19eb464bc2be 124 if (SetSysClock_PLL_HSE(1) == 0)
Kojto 170:19eb464bc2be 125 #endif
Kojto 170:19eb464bc2be 126 {
Kojto 170:19eb464bc2be 127 /* 2- If fail try to start with HSE and external xtal */
Kojto 170:19eb464bc2be 128 #if USE_PLL_HSE_XTAL != 0
Kojto 170:19eb464bc2be 129 if (SetSysClock_PLL_HSE(0) == 0)
Kojto 170:19eb464bc2be 130 #endif
Kojto 170:19eb464bc2be 131 {
Kojto 170:19eb464bc2be 132 /* 3- If fail start with HSI clock */
Kojto 170:19eb464bc2be 133 if (SetSysClock_PLL_HSI() == 0) {
Kojto 170:19eb464bc2be 134 while(1) {
Kojto 170:19eb464bc2be 135 // [TODO] Put something here to tell the user that a problem occured...
Kojto 170:19eb464bc2be 136 }
Kojto 170:19eb464bc2be 137 }
Kojto 170:19eb464bc2be 138 }
Kojto 170:19eb464bc2be 139 }
Kojto 170:19eb464bc2be 140
Kojto 170:19eb464bc2be 141 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 142 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
Kojto 170:19eb464bc2be 143 }
Kojto 170:19eb464bc2be 144
Kojto 170:19eb464bc2be 145 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
Kojto 170:19eb464bc2be 146 /******************************************************************************/
Kojto 170:19eb464bc2be 147 /* PLL (clocked by HSE) used as System clock source */
Kojto 170:19eb464bc2be 148 /******************************************************************************/
Kojto 170:19eb464bc2be 149 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
Kojto 170:19eb464bc2be 150 {
Kojto 170:19eb464bc2be 151 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 152 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 153
Kojto 170:19eb464bc2be 154 /* Used to gain time after DeepSleep in case HSI is used */
Kojto 170:19eb464bc2be 155 if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) {
Kojto 170:19eb464bc2be 156 return 0;
Kojto 170:19eb464bc2be 157 }
Kojto 170:19eb464bc2be 158
Kojto 170:19eb464bc2be 159 /* The voltage scaling allows optimizing the power consumption when the device is
Kojto 170:19eb464bc2be 160 clocked below the maximum system frequency, to update the voltage scaling value
Kojto 170:19eb464bc2be 161 regarding system frequency refer to product datasheet. */
Kojto 170:19eb464bc2be 162 __PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 163 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 170:19eb464bc2be 164
Kojto 170:19eb464bc2be 165 /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
Kojto 170:19eb464bc2be 166 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
Kojto 170:19eb464bc2be 167 if (bypass == 0) {
Kojto 170:19eb464bc2be 168 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 24 MHz xtal on OSC_IN/OSC_OUT */
Kojto 170:19eb464bc2be 169 } else {
Kojto 170:19eb464bc2be 170 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 24 MHz clock on OSC_IN */
Kojto 170:19eb464bc2be 171 }
Kojto 170:19eb464bc2be 172 RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
Kojto 170:19eb464bc2be 173 // SYSCLK = 32 MHz ((24 MHz * 4) / 3)
Kojto 170:19eb464bc2be 174 // USBCLK = 48 MHz ((24 MHz * 4) / 2) --> USB OK
Kojto 170:19eb464bc2be 175 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 176 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
Kojto 170:19eb464bc2be 177 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
Kojto 170:19eb464bc2be 178 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
Kojto 170:19eb464bc2be 179
Kojto 170:19eb464bc2be 180 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 181 return 0; // FAIL
Kojto 170:19eb464bc2be 182 }
Kojto 170:19eb464bc2be 183
Kojto 170:19eb464bc2be 184 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 185 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 186 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
Kojto 170:19eb464bc2be 187 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 188 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 189 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 190 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Kojto 170:19eb464bc2be 191 return 0; // FAIL
Kojto 170:19eb464bc2be 192 }
Kojto 170:19eb464bc2be 193
Kojto 170:19eb464bc2be 194 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 195 //if (bypass == 0)
Kojto 170:19eb464bc2be 196 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
Kojto 170:19eb464bc2be 197 //else
Kojto 170:19eb464bc2be 198 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
Kojto 170:19eb464bc2be 199
Kojto 170:19eb464bc2be 200 return 1; // OK
Kojto 170:19eb464bc2be 201 }
Kojto 170:19eb464bc2be 202 #endif
Kojto 170:19eb464bc2be 203
Kojto 170:19eb464bc2be 204 /******************************************************************************/
Kojto 170:19eb464bc2be 205 /* PLL (clocked by HSI) used as System clock source */
Kojto 170:19eb464bc2be 206 /******************************************************************************/
Kojto 170:19eb464bc2be 207 uint8_t SetSysClock_PLL_HSI(void)
Kojto 170:19eb464bc2be 208 {
Kojto 170:19eb464bc2be 209 RCC_ClkInitTypeDef RCC_ClkInitStruct;
Kojto 170:19eb464bc2be 210 RCC_OscInitTypeDef RCC_OscInitStruct;
Kojto 170:19eb464bc2be 211
Kojto 170:19eb464bc2be 212 /* The voltage scaling allows optimizing the power consumption when the device is
Kojto 170:19eb464bc2be 213 clocked below the maximum system frequency, to update the voltage scaling value
Kojto 170:19eb464bc2be 214 regarding system frequency refer to product datasheet. */
Kojto 170:19eb464bc2be 215 __PWR_CLK_ENABLE();
Kojto 170:19eb464bc2be 216 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
Kojto 170:19eb464bc2be 217
Kojto 170:19eb464bc2be 218 /* Enable HSI oscillator and activate PLL with HSI as source */
Kojto 170:19eb464bc2be 219 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
Kojto 170:19eb464bc2be 220 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
Kojto 170:19eb464bc2be 221 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Kojto 170:19eb464bc2be 222 // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
Kojto 170:19eb464bc2be 223 // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
Kojto 170:19eb464bc2be 224 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
Kojto 170:19eb464bc2be 225 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
Kojto 170:19eb464bc2be 226 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
Kojto 170:19eb464bc2be 227 RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
Kojto 170:19eb464bc2be 228 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Kojto 170:19eb464bc2be 229 return 0; // FAIL
Kojto 170:19eb464bc2be 230 }
Kojto 170:19eb464bc2be 231
Kojto 170:19eb464bc2be 232 /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
Kojto 170:19eb464bc2be 233 while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
Kojto 170:19eb464bc2be 234
Kojto 170:19eb464bc2be 235 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
Kojto 170:19eb464bc2be 236 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Kojto 170:19eb464bc2be 237 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
Kojto 170:19eb464bc2be 238 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 239 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 240 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
Kojto 170:19eb464bc2be 241 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
Kojto 170:19eb464bc2be 242 return 0; // FAIL
Kojto 170:19eb464bc2be 243 }
Kojto 170:19eb464bc2be 244
Kojto 170:19eb464bc2be 245 /* Output clock on MCO1 pin(PA8) for debugging purpose */
Kojto 170:19eb464bc2be 246 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
Kojto 170:19eb464bc2be 247
Kojto 170:19eb464bc2be 248 return 1; // OK
Kojto 170:19eb464bc2be 249 }
Kojto 170:19eb464bc2be 250
Kojto 170:19eb464bc2be 251 /******************************************************************************/
Kojto 170:19eb464bc2be 252 /* Hard Fault Handler */
Kojto 170:19eb464bc2be 253 /******************************************************************************/
Kojto 170:19eb464bc2be 254 void HardFault_Handler(void)
Kojto 170:19eb464bc2be 255 {
AnnaBridge 173:e131a1973e81 256 #if !defined(NDEBUG) || NDEBUG == 0
Kojto 170:19eb464bc2be 257 printf("Hard Fault\n");
AnnaBridge 173:e131a1973e81 258 #endif
Kojto 170:19eb464bc2be 259 NVIC_SystemReset();
Kojto 170:19eb464bc2be 260 }
Kojto 170:19eb464bc2be 261