mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c@173:e131a1973e81, 2017-09-15 (annotated)

Committer:
AnnaBridge
Date:
Fri Sep 15 14:59:18 2017 +0100
Revision:
173:e131a1973e81
Parent:
168:9672193075cf
Child:
175:af195413fb11
This updates the lib to the mbed lib v 151

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 168:9672193075cf 1 /* mbed Microcontroller Library
AnnaBridge 168:9672193075cf 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 168:9672193075cf 3 *
AnnaBridge 168:9672193075cf 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 168:9672193075cf 5 * you may not use this file except in compliance with the License.
AnnaBridge 168:9672193075cf 6 * You may obtain a copy of the License at
AnnaBridge 168:9672193075cf 7 *
AnnaBridge 168:9672193075cf 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 168:9672193075cf 9 *
AnnaBridge 168:9672193075cf 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 168:9672193075cf 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 168:9672193075cf 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 168:9672193075cf 13 * See the License for the specific language governing permissions and
AnnaBridge 168:9672193075cf 14 * limitations under the License.
AnnaBridge 168:9672193075cf 15 */
AnnaBridge 168:9672193075cf 16
AnnaBridge 168:9672193075cf 17 /**
AnnaBridge 168:9672193075cf 18 * This file configures the system clock as follows:
AnnaBridge 168:9672193075cf 19 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 20 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
AnnaBridge 168:9672193075cf 21 * | (external 8 MHz clock) | (internal 16 MHz)
AnnaBridge 168:9672193075cf 22 * | 2- PLL_HSE_XTAL |
AnnaBridge 168:9672193075cf 23 * | (external 8 MHz xtal) |
AnnaBridge 168:9672193075cf 24 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 25 * SYSCLK(MHz) | 100 | 100
AnnaBridge 168:9672193075cf 26 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 27 * AHBCLK (MHz) | 100 | 100
AnnaBridge 168:9672193075cf 28 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 29 * APB1CLK (MHz) | 50 | 50
AnnaBridge 168:9672193075cf 30 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 31 * APB2CLK (MHz) | 100 | 100
AnnaBridge 168:9672193075cf 32 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 33 * USB capable (48 MHz precise clock) | NO | NO
AnnaBridge 168:9672193075cf 34 *-----------------------------------------------------------------------------
AnnaBridge 168:9672193075cf 35 **/
AnnaBridge 168:9672193075cf 36
AnnaBridge 168:9672193075cf 37 #include "stm32f4xx.h"
AnnaBridge 168:9672193075cf 38
AnnaBridge 168:9672193075cf 39 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 168:9672193075cf 40 Internal SRAM. */
AnnaBridge 168:9672193075cf 41 /* #define VECT_TAB_SRAM */
AnnaBridge 168:9672193075cf 42 #ifndef VECT_TAB_OFFSET
AnnaBridge 168:9672193075cf 43 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 168:9672193075cf 44 This value must be a multiple of 0x200. */
AnnaBridge 168:9672193075cf 45 #endif
AnnaBridge 168:9672193075cf 46
AnnaBridge 168:9672193075cf 47
AnnaBridge 168:9672193075cf 48 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
AnnaBridge 168:9672193075cf 49 #define USE_PLL_HSE_EXTC (0) /* Use external clock */
AnnaBridge 168:9672193075cf 50 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
AnnaBridge 168:9672193075cf 51
AnnaBridge 168:9672193075cf 52 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 168:9672193075cf 53 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 168:9672193075cf 54 #endif
AnnaBridge 168:9672193075cf 55
AnnaBridge 168:9672193075cf 56 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 168:9672193075cf 57
AnnaBridge 168:9672193075cf 58 /**
AnnaBridge 168:9672193075cf 59 * @brief Setup the microcontroller system
AnnaBridge 168:9672193075cf 60 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 168:9672193075cf 61 * configuration.
AnnaBridge 168:9672193075cf 62 * @param None
AnnaBridge 168:9672193075cf 63 * @retval None
AnnaBridge 168:9672193075cf 64 */
AnnaBridge 168:9672193075cf 65 void SystemInit(void)
AnnaBridge 168:9672193075cf 66 {
AnnaBridge 168:9672193075cf 67 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 168:9672193075cf 68 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 168:9672193075cf 69 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
AnnaBridge 168:9672193075cf 70 #endif
AnnaBridge 168:9672193075cf 71 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 168:9672193075cf 72 /* Set HSION bit */
AnnaBridge 168:9672193075cf 73 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 168:9672193075cf 74
AnnaBridge 168:9672193075cf 75 /* Reset CFGR register */
AnnaBridge 168:9672193075cf 76 RCC->CFGR = 0x00000000;
AnnaBridge 168:9672193075cf 77
AnnaBridge 168:9672193075cf 78 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 168:9672193075cf 79 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 168:9672193075cf 80
AnnaBridge 168:9672193075cf 81 /* Reset PLLCFGR register */
AnnaBridge 168:9672193075cf 82 RCC->PLLCFGR = 0x24003010;
AnnaBridge 168:9672193075cf 83
AnnaBridge 168:9672193075cf 84 /* Reset HSEBYP bit */
AnnaBridge 168:9672193075cf 85 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 168:9672193075cf 86
AnnaBridge 168:9672193075cf 87 /* Disable all interrupts */
AnnaBridge 168:9672193075cf 88 RCC->CIR = 0x00000000;
AnnaBridge 168:9672193075cf 89
AnnaBridge 168:9672193075cf 90 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 168:9672193075cf 91 SystemInit_ExtMemCtl();
AnnaBridge 168:9672193075cf 92 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 168:9672193075cf 93
AnnaBridge 168:9672193075cf 94 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 168:9672193075cf 95 #ifdef VECT_TAB_SRAM
AnnaBridge 168:9672193075cf 96 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 168:9672193075cf 97 #else
AnnaBridge 168:9672193075cf 98 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 168:9672193075cf 99 #endif
AnnaBridge 168:9672193075cf 100
AnnaBridge 168:9672193075cf 101 }
AnnaBridge 168:9672193075cf 102
AnnaBridge 168:9672193075cf 103 /**
AnnaBridge 168:9672193075cf 104 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 168:9672193075cf 105 * AHB/APBx prescalers and Flash settings
AnnaBridge 168:9672193075cf 106 * @note This function should be called only once the RCC clock configuration
AnnaBridge 168:9672193075cf 107 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 168:9672193075cf 108 * @param None
AnnaBridge 168:9672193075cf 109 * @retval None
AnnaBridge 168:9672193075cf 110 */
AnnaBridge 168:9672193075cf 111 void SetSysClock(void)
AnnaBridge 168:9672193075cf 112 {
AnnaBridge 168:9672193075cf 113 /* 1- Try to start with HSE and external clock */
AnnaBridge 168:9672193075cf 114 #if USE_PLL_HSE_EXTC != 0
AnnaBridge 168:9672193075cf 115 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 168:9672193075cf 116 #endif
AnnaBridge 168:9672193075cf 117 {
AnnaBridge 168:9672193075cf 118 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 168:9672193075cf 119 #if USE_PLL_HSE_XTAL != 0
AnnaBridge 168:9672193075cf 120 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 168:9672193075cf 121 #endif
AnnaBridge 168:9672193075cf 122 {
AnnaBridge 168:9672193075cf 123 /* 3- If fail start with HSI clock */
AnnaBridge 168:9672193075cf 124 if (SetSysClock_PLL_HSI() == 0) {
AnnaBridge 168:9672193075cf 125 while(1) {
AnnaBridge 168:9672193075cf 126 // [TODO] Put something here to tell the user that a problem occured...
AnnaBridge 168:9672193075cf 127 }
AnnaBridge 168:9672193075cf 128 }
AnnaBridge 168:9672193075cf 129 }
AnnaBridge 168:9672193075cf 130 }
AnnaBridge 168:9672193075cf 131
AnnaBridge 168:9672193075cf 132 /* Output clock on MCO2 pin(PC9) for debugging purpose */
AnnaBridge 168:9672193075cf 133 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
AnnaBridge 168:9672193075cf 134 }
AnnaBridge 168:9672193075cf 135
AnnaBridge 168:9672193075cf 136 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
AnnaBridge 168:9672193075cf 137 /******************************************************************************/
AnnaBridge 168:9672193075cf 138 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 168:9672193075cf 139 /******************************************************************************/
AnnaBridge 168:9672193075cf 140 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 168:9672193075cf 141 {
AnnaBridge 168:9672193075cf 142 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 143 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 144
AnnaBridge 168:9672193075cf 145 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 146 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 147 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 148 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 149 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 168:9672193075cf 150
AnnaBridge 168:9672193075cf 151 /* Enable HSE oscillator and activate PLL with HSE as source */
AnnaBridge 168:9672193075cf 152 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 153 if (bypass == 0) {
AnnaBridge 168:9672193075cf 154 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
AnnaBridge 168:9672193075cf 155 } else {
AnnaBridge 168:9672193075cf 156 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
AnnaBridge 168:9672193075cf 157 }
AnnaBridge 168:9672193075cf 158 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 159 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 168:9672193075cf 160 //RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (8 MHz / 8)
AnnaBridge 168:9672193075cf 161 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
AnnaBridge 168:9672193075cf 162 RCC_OscInitStruct.PLL.PLLM = 13; // VCO input clock = 2 MHz (8 MHz / 4)
AnnaBridge 168:9672193075cf 163 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 400 MHz (2 MHz * 200)
AnnaBridge 168:9672193075cf 164 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
AnnaBridge 168:9672193075cf 165 RCC_OscInitStruct.PLL.PLLQ = 8; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
AnnaBridge 168:9672193075cf 166 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 167 return 0; // FAIL
AnnaBridge 168:9672193075cf 168 }
AnnaBridge 168:9672193075cf 169
AnnaBridge 168:9672193075cf 170 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 171 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 172 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
AnnaBridge 168:9672193075cf 173 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
AnnaBridge 168:9672193075cf 174 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
AnnaBridge 168:9672193075cf 175 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
AnnaBridge 168:9672193075cf 176 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 177 return 0; // FAIL
AnnaBridge 168:9672193075cf 178 }
AnnaBridge 168:9672193075cf 179
AnnaBridge 168:9672193075cf 180 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 181
AnnaBridge 168:9672193075cf 182 //if (bypass == 0)
AnnaBridge 168:9672193075cf 183 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
AnnaBridge 168:9672193075cf 184 //else
AnnaBridge 168:9672193075cf 185 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
AnnaBridge 168:9672193075cf 186
AnnaBridge 168:9672193075cf 187 return 1; // OK
AnnaBridge 168:9672193075cf 188 }
AnnaBridge 168:9672193075cf 189 #endif
AnnaBridge 168:9672193075cf 190
AnnaBridge 168:9672193075cf 191 /******************************************************************************/
AnnaBridge 168:9672193075cf 192 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 168:9672193075cf 193 /******************************************************************************/
AnnaBridge 168:9672193075cf 194 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 168:9672193075cf 195 {
AnnaBridge 168:9672193075cf 196 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 168:9672193075cf 197 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 168:9672193075cf 198
AnnaBridge 168:9672193075cf 199 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 168:9672193075cf 200 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 168:9672193075cf 201 regarding system frequency refer to product datasheet. */
AnnaBridge 168:9672193075cf 202 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 168:9672193075cf 203 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 168:9672193075cf 204
AnnaBridge 168:9672193075cf 205 /* Enable HSI oscillator and activate PLL with HSI as source */
AnnaBridge 168:9672193075cf 206 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 168:9672193075cf 207 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 168:9672193075cf 208 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 168:9672193075cf 209 RCC_OscInitStruct.HSICalibrationValue = 16;
AnnaBridge 168:9672193075cf 210 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 168:9672193075cf 211 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 168:9672193075cf 212 //RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
AnnaBridge 168:9672193075cf 213 //RCC_OscInitStruct.PLL.PLLN = 400; // VCO output clock = 400 MHz (1 MHz * 400)
AnnaBridge 168:9672193075cf 214 RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
AnnaBridge 168:9672193075cf 215 RCC_OscInitStruct.PLL.PLLN = 200; // VCO output clock = 400 MHz (2 MHz * 200)
AnnaBridge 168:9672193075cf 216 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 100 MHz (400 MHz / 4)
AnnaBridge 168:9672193075cf 217 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 44.44 MHz (400 MHz / 9) --> Not good for USB
AnnaBridge 168:9672193075cf 218 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 168:9672193075cf 219 return 0; // FAIL
AnnaBridge 168:9672193075cf 220 }
AnnaBridge 168:9672193075cf 221
AnnaBridge 168:9672193075cf 222 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 168:9672193075cf 223 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 168:9672193075cf 224 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 100 MHz
AnnaBridge 168:9672193075cf 225 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 100 MHz
AnnaBridge 168:9672193075cf 226 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 50 MHz
AnnaBridge 168:9672193075cf 227 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 100 MHz
AnnaBridge 168:9672193075cf 228 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
AnnaBridge 168:9672193075cf 229 return 0; // FAIL
AnnaBridge 168:9672193075cf 230 }
AnnaBridge 168:9672193075cf 231
AnnaBridge 168:9672193075cf 232 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 168:9672193075cf 233 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 168:9672193075cf 234
AnnaBridge 168:9672193075cf 235 return 1; // OK
AnnaBridge 168:9672193075cf 236 }
AnnaBridge 168:9672193075cf 237
AnnaBridge 168:9672193075cf 238 /******************************************************************************/
AnnaBridge 168:9672193075cf 239 /* Hard Fault Handler */
AnnaBridge 168:9672193075cf 240 /******************************************************************************/
AnnaBridge 168:9672193075cf 241 void HardFault_Handler(void)
AnnaBridge 168:9672193075cf 242 {
AnnaBridge 173:e131a1973e81 243 #if !defined(NDEBUG) || NDEBUG == 0
AnnaBridge 168:9672193075cf 244 printf("Hard Fault\n");
AnnaBridge 173:e131a1973e81 245 #endif
AnnaBridge 168:9672193075cf 246 NVIC_SystemReset();
AnnaBridge 168:9672193075cf 247 }