mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

cmsis/TARGET_CORTEX_M/mpu_armv7.h@188:bcfe06ba3d64, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:46:34 2018 +0000
Revision:
188:bcfe06ba3d64
Parent:
186:707f6e361f3e 
mbed-dev library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /******************************************************************************
Anna Bridge 180:96ed750bd169 2 * @file mpu_armv7.h
Anna Bridge 186:707f6e361f3e 3 * @brief CMSIS MPU API for Armv7-M MPU
AnnaBridge 188:bcfe06ba3d64 4 * @version V5.0.5
AnnaBridge 188:bcfe06ba3d64 5 * @date 06. September 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 186:707f6e361f3e 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 186:707f6e361f3e 25 #if defined ( __ICCARM__ )
Anna Bridge 186:707f6e361f3e 26 #pragma system_include /* treat file as system include file for MISRA check */
Anna Bridge 186:707f6e361f3e 27 #elif defined (__clang__)
Anna Bridge 186:707f6e361f3e 28 #pragma clang system_header /* treat file as system include file */
Anna Bridge 186:707f6e361f3e 29 #endif
Anna Bridge 186:707f6e361f3e 30
Anna Bridge 180:96ed750bd169 31 #ifndef ARM_MPU_ARMV7_H
Anna Bridge 180:96ed750bd169 32 #define ARM_MPU_ARMV7_H
Anna Bridge 180:96ed750bd169 33
AnnaBridge 188:bcfe06ba3d64 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
AnnaBridge 188:bcfe06ba3d64 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
AnnaBridge 188:bcfe06ba3d64 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
AnnaBridge 188:bcfe06ba3d64 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
AnnaBridge 188:bcfe06ba3d64 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
AnnaBridge 188:bcfe06ba3d64 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
AnnaBridge 188:bcfe06ba3d64 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
AnnaBridge 188:bcfe06ba3d64 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
AnnaBridge 188:bcfe06ba3d64 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
AnnaBridge 188:bcfe06ba3d64 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
AnnaBridge 188:bcfe06ba3d64 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
AnnaBridge 188:bcfe06ba3d64 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
AnnaBridge 188:bcfe06ba3d64 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
AnnaBridge 188:bcfe06ba3d64 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
AnnaBridge 188:bcfe06ba3d64 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
AnnaBridge 188:bcfe06ba3d64 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
AnnaBridge 188:bcfe06ba3d64 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
AnnaBridge 188:bcfe06ba3d64 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
AnnaBridge 188:bcfe06ba3d64 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
AnnaBridge 188:bcfe06ba3d64 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
AnnaBridge 188:bcfe06ba3d64 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
AnnaBridge 188:bcfe06ba3d64 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
AnnaBridge 188:bcfe06ba3d64 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
AnnaBridge 188:bcfe06ba3d64 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
AnnaBridge 188:bcfe06ba3d64 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
AnnaBridge 188:bcfe06ba3d64 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
AnnaBridge 188:bcfe06ba3d64 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
AnnaBridge 188:bcfe06ba3d64 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
Anna Bridge 180:96ed750bd169 62
AnnaBridge 188:bcfe06ba3d64 63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
AnnaBridge 188:bcfe06ba3d64 64 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
AnnaBridge 188:bcfe06ba3d64 65 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
AnnaBridge 188:bcfe06ba3d64 66 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
AnnaBridge 188:bcfe06ba3d64 67 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
AnnaBridge 188:bcfe06ba3d64 68 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
Anna Bridge 180:96ed750bd169 69
Anna Bridge 180:96ed750bd169 70 /** MPU Region Base Address Register Value
Anna Bridge 180:96ed750bd169 71 *
Anna Bridge 180:96ed750bd169 72 * \param Region The region to be configured, number 0 to 15.
Anna Bridge 180:96ed750bd169 73 * \param BaseAddress The base address for the region.
Anna Bridge 180:96ed750bd169 74 */
Anna Bridge 180:96ed750bd169 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
Anna Bridge 180:96ed750bd169 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
Anna Bridge 180:96ed750bd169 77 ((Region) & MPU_RBAR_REGION_Msk) | \
Anna Bridge 180:96ed750bd169 78 (MPU_RBAR_VALID_Msk))
Anna Bridge 180:96ed750bd169 79
Anna Bridge 180:96ed750bd169 80 /**
AnnaBridge 188:bcfe06ba3d64 81 * MPU Memory Access Attributes
AnnaBridge 188:bcfe06ba3d64 82 *
AnnaBridge 188:bcfe06ba3d64 83 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
AnnaBridge 188:bcfe06ba3d64 84 * \param IsShareable Region is shareable between multiple bus masters.
AnnaBridge 188:bcfe06ba3d64 85 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
AnnaBridge 188:bcfe06ba3d64 86 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
AnnaBridge 188:bcfe06ba3d64 87 */
AnnaBridge 188:bcfe06ba3d64 88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
AnnaBridge 188:bcfe06ba3d64 89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
AnnaBridge 188:bcfe06ba3d64 90 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
AnnaBridge 188:bcfe06ba3d64 91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
AnnaBridge 188:bcfe06ba3d64 92 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
AnnaBridge 188:bcfe06ba3d64 93
AnnaBridge 188:bcfe06ba3d64 94 /**
AnnaBridge 188:bcfe06ba3d64 95 * MPU Region Attribute and Size Register Value
AnnaBridge 188:bcfe06ba3d64 96 *
AnnaBridge 188:bcfe06ba3d64 97 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
AnnaBridge 188:bcfe06ba3d64 98 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
AnnaBridge 188:bcfe06ba3d64 99 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
AnnaBridge 188:bcfe06ba3d64 100 * \param SubRegionDisable Sub-region disable field.
AnnaBridge 188:bcfe06ba3d64 101 * \param Size Region size of the region to be configured, for example 4K, 8K.
AnnaBridge 188:bcfe06ba3d64 102 */
AnnaBridge 188:bcfe06ba3d64 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
AnnaBridge 188:bcfe06ba3d64 104 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
AnnaBridge 188:bcfe06ba3d64 105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
AnnaBridge 188:bcfe06ba3d64 106 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
AnnaBridge 188:bcfe06ba3d64 107 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
AnnaBridge 188:bcfe06ba3d64 108 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
AnnaBridge 188:bcfe06ba3d64 109 (((MPU_RASR_ENABLE_Msk))))
AnnaBridge 188:bcfe06ba3d64 110
AnnaBridge 188:bcfe06ba3d64 111 /**
Anna Bridge 186:707f6e361f3e 112 * MPU Region Attribute and Size Register Value
Anna Bridge 180:96ed750bd169 113 *
Anna Bridge 180:96ed750bd169 114 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
Anna Bridge 180:96ed750bd169 115 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
Anna Bridge 180:96ed750bd169 116 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
Anna Bridge 180:96ed750bd169 117 * \param IsShareable Region is shareable between multiple bus masters.
Anna Bridge 180:96ed750bd169 118 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
Anna Bridge 180:96ed750bd169 119 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
Anna Bridge 180:96ed750bd169 120 * \param SubRegionDisable Sub-region disable field.
Anna Bridge 180:96ed750bd169 121 * \param Size Region size of the region to be configured, for example 4K, 8K.
Anna Bridge 180:96ed750bd169 122 */
Anna Bridge 180:96ed750bd169 123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
AnnaBridge 188:bcfe06ba3d64 124 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
AnnaBridge 188:bcfe06ba3d64 125
AnnaBridge 188:bcfe06ba3d64 126 /**
AnnaBridge 188:bcfe06ba3d64 127 * MPU Memory Access Attribute for strongly ordered memory.
AnnaBridge 188:bcfe06ba3d64 128 * - TEX: 000b
AnnaBridge 188:bcfe06ba3d64 129 * - Shareable
AnnaBridge 188:bcfe06ba3d64 130 * - Non-cacheable
AnnaBridge 188:bcfe06ba3d64 131 * - Non-bufferable
AnnaBridge 188:bcfe06ba3d64 132 */
AnnaBridge 188:bcfe06ba3d64 133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
AnnaBridge 188:bcfe06ba3d64 134
AnnaBridge 188:bcfe06ba3d64 135 /**
AnnaBridge 188:bcfe06ba3d64 136 * MPU Memory Access Attribute for device memory.
AnnaBridge 188:bcfe06ba3d64 137 * - TEX: 000b (if non-shareable) or 010b (if shareable)
AnnaBridge 188:bcfe06ba3d64 138 * - Shareable or non-shareable
AnnaBridge 188:bcfe06ba3d64 139 * - Non-cacheable
AnnaBridge 188:bcfe06ba3d64 140 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
AnnaBridge 188:bcfe06ba3d64 141 *
AnnaBridge 188:bcfe06ba3d64 142 * \param IsShareable Configures the device memory as shareable or non-shareable.
AnnaBridge 188:bcfe06ba3d64 143 */
AnnaBridge 188:bcfe06ba3d64 144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
AnnaBridge 188:bcfe06ba3d64 145
AnnaBridge 188:bcfe06ba3d64 146 /**
AnnaBridge 188:bcfe06ba3d64 147 * MPU Memory Access Attribute for normal memory.
AnnaBridge 188:bcfe06ba3d64 148 * - TEX: 1BBb (reflecting outer cacheability rules)
AnnaBridge 188:bcfe06ba3d64 149 * - Shareable or non-shareable
AnnaBridge 188:bcfe06ba3d64 150 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
AnnaBridge 188:bcfe06ba3d64 151 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
AnnaBridge 188:bcfe06ba3d64 152 *
AnnaBridge 188:bcfe06ba3d64 153 * \param OuterCp Configures the outer cache policy.
AnnaBridge 188:bcfe06ba3d64 154 * \param InnerCp Configures the inner cache policy.
AnnaBridge 188:bcfe06ba3d64 155 * \param IsShareable Configures the memory as shareable or non-shareable.
AnnaBridge 188:bcfe06ba3d64 156 */
AnnaBridge 188:bcfe06ba3d64 157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
AnnaBridge 188:bcfe06ba3d64 158
AnnaBridge 188:bcfe06ba3d64 159 /**
AnnaBridge 188:bcfe06ba3d64 160 * MPU Memory Access Attribute non-cacheable policy.
AnnaBridge 188:bcfe06ba3d64 161 */
AnnaBridge 188:bcfe06ba3d64 162 #define ARM_MPU_CACHEP_NOCACHE 0U
AnnaBridge 188:bcfe06ba3d64 163
AnnaBridge 188:bcfe06ba3d64 164 /**
AnnaBridge 188:bcfe06ba3d64 165 * MPU Memory Access Attribute write-back, write and read allocate policy.
AnnaBridge 188:bcfe06ba3d64 166 */
AnnaBridge 188:bcfe06ba3d64 167 #define ARM_MPU_CACHEP_WB_WRA 1U
AnnaBridge 188:bcfe06ba3d64 168
AnnaBridge 188:bcfe06ba3d64 169 /**
AnnaBridge 188:bcfe06ba3d64 170 * MPU Memory Access Attribute write-through, no write allocate policy.
AnnaBridge 188:bcfe06ba3d64 171 */
AnnaBridge 188:bcfe06ba3d64 172 #define ARM_MPU_CACHEP_WT_NWA 2U
AnnaBridge 188:bcfe06ba3d64 173
AnnaBridge 188:bcfe06ba3d64 174 /**
AnnaBridge 188:bcfe06ba3d64 175 * MPU Memory Access Attribute write-back, no write allocate policy.
AnnaBridge 188:bcfe06ba3d64 176 */
AnnaBridge 188:bcfe06ba3d64 177 #define ARM_MPU_CACHEP_WB_NWA 3U
Anna Bridge 180:96ed750bd169 178
Anna Bridge 180:96ed750bd169 179
Anna Bridge 180:96ed750bd169 180 /**
Anna Bridge 180:96ed750bd169 181 * Struct for a single MPU Region
Anna Bridge 180:96ed750bd169 182 */
Anna Bridge 186:707f6e361f3e 183 typedef struct {
Anna Bridge 180:96ed750bd169 184 uint32_t RBAR; //!< The region base address register value (RBAR)
Anna Bridge 180:96ed750bd169 185 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
Anna Bridge 180:96ed750bd169 186 } ARM_MPU_Region_t;
Anna Bridge 180:96ed750bd169 187
Anna Bridge 180:96ed750bd169 188 /** Enable the MPU.
Anna Bridge 180:96ed750bd169 189 * \param MPU_Control Default access permissions for unconfigured regions.
Anna Bridge 180:96ed750bd169 190 */
Anna Bridge 180:96ed750bd169 191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
Anna Bridge 180:96ed750bd169 192 {
Anna Bridge 180:96ed750bd169 193 __DSB();
Anna Bridge 180:96ed750bd169 194 __ISB();
Anna Bridge 180:96ed750bd169 195 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 196 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 197 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 198 #endif
Anna Bridge 180:96ed750bd169 199 }
Anna Bridge 180:96ed750bd169 200
Anna Bridge 180:96ed750bd169 201 /** Disable the MPU.
Anna Bridge 180:96ed750bd169 202 */
Anna Bridge 180:96ed750bd169 203 __STATIC_INLINE void ARM_MPU_Disable(void)
Anna Bridge 180:96ed750bd169 204 {
Anna Bridge 180:96ed750bd169 205 __DSB();
Anna Bridge 180:96ed750bd169 206 __ISB();
Anna Bridge 180:96ed750bd169 207 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
Anna Bridge 180:96ed750bd169 208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
Anna Bridge 180:96ed750bd169 209 #endif
Anna Bridge 180:96ed750bd169 210 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
Anna Bridge 180:96ed750bd169 211 }
Anna Bridge 180:96ed750bd169 212
Anna Bridge 180:96ed750bd169 213 /** Clear and disable the given MPU region.
Anna Bridge 180:96ed750bd169 214 * \param rnr Region number to be cleared.
Anna Bridge 180:96ed750bd169 215 */
Anna Bridge 180:96ed750bd169 216 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
Anna Bridge 180:96ed750bd169 217 {
Anna Bridge 180:96ed750bd169 218 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 219 MPU->RASR = 0U;
Anna Bridge 180:96ed750bd169 220 }
Anna Bridge 180:96ed750bd169 221
Anna Bridge 180:96ed750bd169 222 /** Configure an MPU region.
Anna Bridge 180:96ed750bd169 223 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 224 * \param rsar Value for RSAR register.
Anna Bridge 180:96ed750bd169 225 */
Anna Bridge 180:96ed750bd169 226 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
Anna Bridge 180:96ed750bd169 227 {
Anna Bridge 180:96ed750bd169 228 MPU->RBAR = rbar;
Anna Bridge 180:96ed750bd169 229 MPU->RASR = rasr;
Anna Bridge 180:96ed750bd169 230 }
Anna Bridge 180:96ed750bd169 231
Anna Bridge 180:96ed750bd169 232 /** Configure the given MPU region.
Anna Bridge 180:96ed750bd169 233 * \param rnr Region number to be configured.
Anna Bridge 180:96ed750bd169 234 * \param rbar Value for RBAR register.
Anna Bridge 180:96ed750bd169 235 * \param rsar Value for RSAR register.
Anna Bridge 180:96ed750bd169 236 */
Anna Bridge 180:96ed750bd169 237 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
Anna Bridge 180:96ed750bd169 238 {
Anna Bridge 180:96ed750bd169 239 MPU->RNR = rnr;
Anna Bridge 180:96ed750bd169 240 MPU->RBAR = rbar;
Anna Bridge 180:96ed750bd169 241 MPU->RASR = rasr;
Anna Bridge 180:96ed750bd169 242 }
Anna Bridge 180:96ed750bd169 243
Anna Bridge 180:96ed750bd169 244 /** Memcopy with strictly ordered memory access, e.g. for register targets.
Anna Bridge 180:96ed750bd169 245 * \param dst Destination data is copied to.
Anna Bridge 180:96ed750bd169 246 * \param src Source data is copied from.
Anna Bridge 180:96ed750bd169 247 * \param len Amount of data words to be copied.
Anna Bridge 180:96ed750bd169 248 */
Anna Bridge 180:96ed750bd169 249 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
Anna Bridge 180:96ed750bd169 250 {
Anna Bridge 180:96ed750bd169 251 uint32_t i;
Anna Bridge 180:96ed750bd169 252 for (i = 0U; i < len; ++i)
Anna Bridge 180:96ed750bd169 253 {
Anna Bridge 180:96ed750bd169 254 dst[i] = src[i];
Anna Bridge 180:96ed750bd169 255 }
Anna Bridge 180:96ed750bd169 256 }
Anna Bridge 180:96ed750bd169 257
Anna Bridge 180:96ed750bd169 258 /** Load the given number of MPU regions from a table.
Anna Bridge 180:96ed750bd169 259 * \param table Pointer to the MPU configuration table.
Anna Bridge 180:96ed750bd169 260 * \param cnt Amount of regions to be configured.
Anna Bridge 180:96ed750bd169 261 */
Anna Bridge 180:96ed750bd169 262 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
Anna Bridge 180:96ed750bd169 263 {
Anna Bridge 186:707f6e361f3e 264 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
Anna Bridge 186:707f6e361f3e 265 while (cnt > MPU_TYPE_RALIASES) {
Anna Bridge 180:96ed750bd169 266 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
Anna Bridge 186:707f6e361f3e 267 table += MPU_TYPE_RALIASES;
Anna Bridge 186:707f6e361f3e 268 cnt -= MPU_TYPE_RALIASES;
Anna Bridge 180:96ed750bd169 269 }
Anna Bridge 186:707f6e361f3e 270 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
Anna Bridge 180:96ed750bd169 271 }
Anna Bridge 180:96ed750bd169 272
Anna Bridge 180:96ed750bd169 273 #endif