mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h@158:b23ee177fd68, 2017-02-14 (annotated)

Committer:
Kojto
Date:
Tue Feb 14 14:44:10 2017 +0000
Revision:
158:b23ee177fd68
Parent:
targets/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F769NI/device/stm32f769xx.h@157:ff67d9f36b67
Child:
161:2cc1468da177
This updates the lib to the mbed lib v136

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 147:30b64687e01f 1 /**
<> 147:30b64687e01f 2 ******************************************************************************
<> 147:30b64687e01f 3 * @file stm32f769xx.h
<> 147:30b64687e01f 4 * @author MCD Application Team
<> 157:ff67d9f36b67 5 * @version V1.1.2
<> 157:ff67d9f36b67 6 * @date 23-September-2016
<> 147:30b64687e01f 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
<> 147:30b64687e01f 8 *
<> 147:30b64687e01f 9 * This file contains:
<> 147:30b64687e01f 10 * - Data structures and the address mapping for all peripherals
<> 147:30b64687e01f 11 * - Peripheral's registers declarations and bits definition
<> 147:30b64687e01f 12 * - Macros to access peripheral’s registers hardware
<> 147:30b64687e01f 13 *
<> 147:30b64687e01f 14 ******************************************************************************
<> 147:30b64687e01f 15 * @attention
<> 147:30b64687e01f 16 *
<> 147:30b64687e01f 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 147:30b64687e01f 18 *
<> 147:30b64687e01f 19 * Redistribution and use in source and binary forms, with or without modification,
<> 147:30b64687e01f 20 * are permitted provided that the following conditions are met:
<> 147:30b64687e01f 21 * 1. Redistributions of source code must retain the above copyright notice,
<> 147:30b64687e01f 22 * this list of conditions and the following disclaimer.
<> 147:30b64687e01f 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 147:30b64687e01f 24 * this list of conditions and the following disclaimer in the documentation
<> 147:30b64687e01f 25 * and/or other materials provided with the distribution.
<> 147:30b64687e01f 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 147:30b64687e01f 27 * may be used to endorse or promote products derived from this software
<> 147:30b64687e01f 28 * without specific prior written permission.
<> 147:30b64687e01f 29 *
<> 147:30b64687e01f 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 147:30b64687e01f 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 147:30b64687e01f 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 147:30b64687e01f 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 147:30b64687e01f 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 147:30b64687e01f 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 147:30b64687e01f 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 147:30b64687e01f 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 147:30b64687e01f 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 147:30b64687e01f 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 147:30b64687e01f 40 *
<> 147:30b64687e01f 41 ******************************************************************************
<> 147:30b64687e01f 42 */
<> 147:30b64687e01f 43
<> 147:30b64687e01f 44 /** @addtogroup CMSIS_Device
<> 147:30b64687e01f 45 * @{
<> 147:30b64687e01f 46 */
<> 147:30b64687e01f 47
<> 147:30b64687e01f 48 /** @addtogroup stm32f769xx
<> 147:30b64687e01f 49 * @{
<> 147:30b64687e01f 50 */
<> 147:30b64687e01f 51
<> 147:30b64687e01f 52 #ifndef __STM32F769xx_H
<> 147:30b64687e01f 53 #define __STM32F769xx_H
<> 147:30b64687e01f 54
<> 147:30b64687e01f 55 #ifdef __cplusplus
<> 147:30b64687e01f 56 extern "C" {
<> 147:30b64687e01f 57 #endif /* __cplusplus */
<> 147:30b64687e01f 58
<> 147:30b64687e01f 59 /** @addtogroup Configuration_section_for_CMSIS
<> 147:30b64687e01f 60 * @{
<> 147:30b64687e01f 61 */
<> 147:30b64687e01f 62
<> 147:30b64687e01f 63 /**
<> 147:30b64687e01f 64 * @brief STM32F7xx Interrupt Number Definition, according to the selected device
<> 147:30b64687e01f 65 * in @ref Library_configuration_section
<> 147:30b64687e01f 66 */
<> 147:30b64687e01f 67 typedef enum
<> 147:30b64687e01f 68 {
<> 147:30b64687e01f 69 /****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/
<> 147:30b64687e01f 70 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 147:30b64687e01f 71 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */
<> 147:30b64687e01f 72 BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */
<> 147:30b64687e01f 73 UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */
<> 147:30b64687e01f 74 SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */
<> 147:30b64687e01f 75 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */
<> 147:30b64687e01f 76 PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */
<> 147:30b64687e01f 77 SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */
<> 147:30b64687e01f 78 /****** STM32 specific Interrupt Numbers **********************************************************************/
<> 147:30b64687e01f 79 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
<> 147:30b64687e01f 80 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
<> 147:30b64687e01f 81 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
<> 147:30b64687e01f 82 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
<> 147:30b64687e01f 83 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
<> 147:30b64687e01f 84 RCC_IRQn = 5, /*!< RCC global Interrupt */
<> 147:30b64687e01f 85 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
<> 147:30b64687e01f 86 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
<> 147:30b64687e01f 87 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
<> 147:30b64687e01f 88 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
<> 147:30b64687e01f 89 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
<> 147:30b64687e01f 90 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
<> 147:30b64687e01f 91 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
<> 147:30b64687e01f 92 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
<> 147:30b64687e01f 93 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
<> 147:30b64687e01f 94 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
<> 147:30b64687e01f 95 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
<> 147:30b64687e01f 96 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
<> 147:30b64687e01f 97 ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */
<> 147:30b64687e01f 98 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
<> 147:30b64687e01f 99 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
<> 147:30b64687e01f 100 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
<> 147:30b64687e01f 101 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
<> 147:30b64687e01f 102 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
<> 147:30b64687e01f 103 TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */
<> 147:30b64687e01f 104 TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */
<> 147:30b64687e01f 105 TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
<> 147:30b64687e01f 106 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
<> 147:30b64687e01f 107 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
<> 147:30b64687e01f 108 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
<> 147:30b64687e01f 109 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
<> 147:30b64687e01f 110 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
<> 147:30b64687e01f 111 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
<> 147:30b64687e01f 112 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
<> 147:30b64687e01f 113 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
<> 147:30b64687e01f 114 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
<> 147:30b64687e01f 115 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
<> 147:30b64687e01f 116 USART1_IRQn = 37, /*!< USART1 global Interrupt */
<> 147:30b64687e01f 117 USART2_IRQn = 38, /*!< USART2 global Interrupt */
<> 147:30b64687e01f 118 USART3_IRQn = 39, /*!< USART3 global Interrupt */
<> 147:30b64687e01f 119 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
<> 147:30b64687e01f 120 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
<> 147:30b64687e01f 121 OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */
<> 147:30b64687e01f 122 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
<> 147:30b64687e01f 123 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
<> 147:30b64687e01f 124 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
<> 147:30b64687e01f 125 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
<> 147:30b64687e01f 126 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
<> 147:30b64687e01f 127 FMC_IRQn = 48, /*!< FMC global Interrupt */
<> 147:30b64687e01f 128 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
<> 147:30b64687e01f 129 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
<> 147:30b64687e01f 130 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
<> 147:30b64687e01f 131 UART4_IRQn = 52, /*!< UART4 global Interrupt */
<> 147:30b64687e01f 132 UART5_IRQn = 53, /*!< UART5 global Interrupt */
<> 147:30b64687e01f 133 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
<> 147:30b64687e01f 134 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
<> 147:30b64687e01f 135 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
<> 147:30b64687e01f 136 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
<> 147:30b64687e01f 137 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
<> 147:30b64687e01f 138 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
<> 147:30b64687e01f 139 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
<> 147:30b64687e01f 140 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
<> 147:30b64687e01f 141 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
<> 147:30b64687e01f 142 CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */
<> 147:30b64687e01f 143 CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */
<> 147:30b64687e01f 144 CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */
<> 147:30b64687e01f 145 CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */
<> 147:30b64687e01f 146 OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */
<> 147:30b64687e01f 147 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
<> 147:30b64687e01f 148 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
<> 147:30b64687e01f 149 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
<> 147:30b64687e01f 150 USART6_IRQn = 71, /*!< USART6 global interrupt */
<> 147:30b64687e01f 151 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
<> 147:30b64687e01f 152 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
<> 147:30b64687e01f 153 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
<> 147:30b64687e01f 154 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
<> 147:30b64687e01f 155 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
<> 147:30b64687e01f 156 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
<> 147:30b64687e01f 157 DCMI_IRQn = 78, /*!< DCMI global interrupt */
<> 147:30b64687e01f 158 RNG_IRQn = 80, /*!< RNG global interrupt */
<> 147:30b64687e01f 159 FPU_IRQn = 81, /*!< FPU global interrupt */
<> 147:30b64687e01f 160 UART7_IRQn = 82, /*!< UART7 global interrupt */
<> 147:30b64687e01f 161 UART8_IRQn = 83, /*!< UART8 global interrupt */
<> 147:30b64687e01f 162 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
<> 147:30b64687e01f 163 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
<> 147:30b64687e01f 164 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
<> 147:30b64687e01f 165 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
<> 147:30b64687e01f 166 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
<> 147:30b64687e01f 167 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
<> 147:30b64687e01f 168 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
<> 147:30b64687e01f 169 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
<> 147:30b64687e01f 170 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
<> 147:30b64687e01f 171 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
<> 147:30b64687e01f 172 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
<> 147:30b64687e01f 173 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
<> 147:30b64687e01f 174 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
<> 147:30b64687e01f 175 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
<> 147:30b64687e01f 176 DSI_IRQn = 98, /*!< DSI global Interrupt */
<> 147:30b64687e01f 177 DFSDM1_FLT0_IRQn = 99, /*!< DFSDM1 Filter 0 global Interrupt */
<> 147:30b64687e01f 178 DFSDM1_FLT1_IRQn = 100, /*!< DFSDM1 Filter 1 global Interrupt */
<> 147:30b64687e01f 179 DFSDM1_FLT2_IRQn = 101, /*!< DFSDM1 Filter 2 global Interrupt */
<> 147:30b64687e01f 180 DFSDM1_FLT3_IRQn = 102, /*!< DFSDM1 Filter 3 global Interrupt */
<> 147:30b64687e01f 181 SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */
<> 147:30b64687e01f 182 CAN3_TX_IRQn = 104, /*!< CAN3 TX Interrupt */
<> 147:30b64687e01f 183 CAN3_RX0_IRQn = 105, /*!< CAN3 RX0 Interrupt */
<> 147:30b64687e01f 184 CAN3_RX1_IRQn = 106, /*!< CAN3 RX1 Interrupt */
<> 147:30b64687e01f 185 CAN3_SCE_IRQn = 107, /*!< CAN3 SCE Interrupt */
<> 147:30b64687e01f 186 JPEG_IRQn = 108, /*!< JPEG global Interrupt */
<> 147:30b64687e01f 187 MDIOS_IRQn = 109 /*!< MDIO Slave global Interrupt */
<> 147:30b64687e01f 188 } IRQn_Type;
<> 147:30b64687e01f 189
<> 147:30b64687e01f 190 /**
<> 147:30b64687e01f 191 * @}
<> 147:30b64687e01f 192 */
<> 147:30b64687e01f 193
<> 147:30b64687e01f 194 /**
<> 147:30b64687e01f 195 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
<> 147:30b64687e01f 196 */
<> 147:30b64687e01f 197 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
<> 147:30b64687e01f 198 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
<> 147:30b64687e01f 199 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
<> 147:30b64687e01f 200 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 147:30b64687e01f 201 #define __FPU_PRESENT 1 /*!< FPU present */
<> 147:30b64687e01f 202 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
<> 147:30b64687e01f 203 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
<> 147:30b64687e01f 204 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
<> 147:30b64687e01f 205
<> 147:30b64687e01f 206
<> 147:30b64687e01f 207 #include "system_stm32f7xx.h"
<> 147:30b64687e01f 208 #include <stdint.h>
<> 147:30b64687e01f 209
<> 147:30b64687e01f 210 /** @addtogroup Peripheral_registers_structures
<> 147:30b64687e01f 211 * @{
<> 147:30b64687e01f 212 */
<> 147:30b64687e01f 213
<> 147:30b64687e01f 214 /**
<> 147:30b64687e01f 215 * @brief Analog to Digital Converter
<> 147:30b64687e01f 216 */
<> 147:30b64687e01f 217
<> 147:30b64687e01f 218 typedef struct
<> 147:30b64687e01f 219 {
<> 147:30b64687e01f 220 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
<> 147:30b64687e01f 221 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
<> 147:30b64687e01f 222 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
<> 147:30b64687e01f 223 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
<> 147:30b64687e01f 224 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
<> 147:30b64687e01f 225 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
<> 147:30b64687e01f 226 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
<> 147:30b64687e01f 227 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
<> 147:30b64687e01f 228 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
<> 147:30b64687e01f 229 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */
<> 147:30b64687e01f 230 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */
<> 147:30b64687e01f 231 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */
<> 147:30b64687e01f 232 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */
<> 147:30b64687e01f 233 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */
<> 147:30b64687e01f 234 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/
<> 147:30b64687e01f 235 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */
<> 147:30b64687e01f 236 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */
<> 147:30b64687e01f 237 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */
<> 147:30b64687e01f 238 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */
<> 147:30b64687e01f 239 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */
<> 147:30b64687e01f 240 } ADC_TypeDef;
<> 147:30b64687e01f 241
<> 147:30b64687e01f 242 typedef struct
<> 147:30b64687e01f 243 {
<> 147:30b64687e01f 244 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */
<> 147:30b64687e01f 245 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
<> 147:30b64687e01f 246 __IO uint32_t CDR; /*!< ADC common regular data register for dual
<> 147:30b64687e01f 247 AND triple modes, Address offset: ADC1 base address + 0x308 */
<> 147:30b64687e01f 248 } ADC_Common_TypeDef;
<> 147:30b64687e01f 249
<> 147:30b64687e01f 250
<> 147:30b64687e01f 251 /**
<> 147:30b64687e01f 252 * @brief Controller Area Network TxMailBox
<> 147:30b64687e01f 253 */
<> 147:30b64687e01f 254
<> 147:30b64687e01f 255 typedef struct
<> 147:30b64687e01f 256 {
<> 147:30b64687e01f 257 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
<> 147:30b64687e01f 258 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
<> 147:30b64687e01f 259 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
<> 147:30b64687e01f 260 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
<> 147:30b64687e01f 261 } CAN_TxMailBox_TypeDef;
<> 147:30b64687e01f 262
<> 147:30b64687e01f 263 /**
<> 147:30b64687e01f 264 * @brief Controller Area Network FIFOMailBox
<> 147:30b64687e01f 265 */
<> 147:30b64687e01f 266
<> 147:30b64687e01f 267 typedef struct
<> 147:30b64687e01f 268 {
<> 147:30b64687e01f 269 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
<> 147:30b64687e01f 270 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
<> 147:30b64687e01f 271 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
<> 147:30b64687e01f 272 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
<> 147:30b64687e01f 273 } CAN_FIFOMailBox_TypeDef;
<> 147:30b64687e01f 274
<> 147:30b64687e01f 275 /**
<> 147:30b64687e01f 276 * @brief Controller Area Network FilterRegister
<> 147:30b64687e01f 277 */
<> 147:30b64687e01f 278
<> 147:30b64687e01f 279 typedef struct
<> 147:30b64687e01f 280 {
<> 147:30b64687e01f 281 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
<> 147:30b64687e01f 282 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
<> 147:30b64687e01f 283 } CAN_FilterRegister_TypeDef;
<> 147:30b64687e01f 284
<> 147:30b64687e01f 285 /**
<> 147:30b64687e01f 286 * @brief Controller Area Network
<> 147:30b64687e01f 287 */
<> 147:30b64687e01f 288
<> 147:30b64687e01f 289 typedef struct
<> 147:30b64687e01f 290 {
<> 147:30b64687e01f 291 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
<> 147:30b64687e01f 292 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
<> 147:30b64687e01f 293 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
<> 147:30b64687e01f 294 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
<> 147:30b64687e01f 295 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
<> 147:30b64687e01f 296 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
<> 147:30b64687e01f 297 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
<> 147:30b64687e01f 298 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
<> 147:30b64687e01f 299 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
<> 147:30b64687e01f 300 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
<> 147:30b64687e01f 301 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
<> 147:30b64687e01f 302 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
<> 147:30b64687e01f 303 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
<> 147:30b64687e01f 304 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
<> 147:30b64687e01f 305 uint32_t RESERVED2; /*!< Reserved, 0x208 */
<> 147:30b64687e01f 306 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
<> 147:30b64687e01f 307 uint32_t RESERVED3; /*!< Reserved, 0x210 */
<> 147:30b64687e01f 308 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
<> 147:30b64687e01f 309 uint32_t RESERVED4; /*!< Reserved, 0x218 */
<> 147:30b64687e01f 310 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
<> 147:30b64687e01f 311 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
<> 147:30b64687e01f 312 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
<> 147:30b64687e01f 313 } CAN_TypeDef;
<> 147:30b64687e01f 314
<> 147:30b64687e01f 315 /**
<> 147:30b64687e01f 316 * @brief HDMI-CEC
<> 147:30b64687e01f 317 */
<> 147:30b64687e01f 318
<> 147:30b64687e01f 319 typedef struct
<> 147:30b64687e01f 320 {
<> 147:30b64687e01f 321 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
<> 147:30b64687e01f 322 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
<> 147:30b64687e01f 323 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
<> 147:30b64687e01f 324 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
<> 147:30b64687e01f 325 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
<> 147:30b64687e01f 326 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
<> 147:30b64687e01f 327 }CEC_TypeDef;
<> 147:30b64687e01f 328
<> 147:30b64687e01f 329 /**
<> 147:30b64687e01f 330 * @brief CRC calculation unit
<> 147:30b64687e01f 331 */
<> 147:30b64687e01f 332
<> 147:30b64687e01f 333 typedef struct
<> 147:30b64687e01f 334 {
<> 147:30b64687e01f 335 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
<> 147:30b64687e01f 336 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
<> 147:30b64687e01f 337 uint8_t RESERVED0; /*!< Reserved, 0x05 */
<> 147:30b64687e01f 338 uint16_t RESERVED1; /*!< Reserved, 0x06 */
<> 147:30b64687e01f 339 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
<> 147:30b64687e01f 340 uint32_t RESERVED2; /*!< Reserved, 0x0C */
<> 147:30b64687e01f 341 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
<> 147:30b64687e01f 342 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
<> 147:30b64687e01f 343 } CRC_TypeDef;
<> 147:30b64687e01f 344
<> 147:30b64687e01f 345 /**
<> 147:30b64687e01f 346 * @brief Digital to Analog Converter
<> 147:30b64687e01f 347 */
<> 147:30b64687e01f 348
<> 147:30b64687e01f 349 typedef struct
<> 147:30b64687e01f 350 {
<> 147:30b64687e01f 351 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
<> 147:30b64687e01f 352 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
<> 147:30b64687e01f 353 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
<> 147:30b64687e01f 354 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
<> 147:30b64687e01f 355 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
<> 147:30b64687e01f 356 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
<> 147:30b64687e01f 357 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
<> 147:30b64687e01f 358 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
<> 147:30b64687e01f 359 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
<> 147:30b64687e01f 360 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
<> 147:30b64687e01f 361 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
<> 147:30b64687e01f 362 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
<> 147:30b64687e01f 363 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
<> 147:30b64687e01f 364 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
<> 147:30b64687e01f 365 } DAC_TypeDef;
<> 147:30b64687e01f 366
<> 147:30b64687e01f 367 /**
<> 147:30b64687e01f 368 * @brief DFSDM module registers
<> 147:30b64687e01f 369 */
<> 147:30b64687e01f 370 typedef struct
<> 147:30b64687e01f 371 {
<> 147:30b64687e01f 372 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
<> 147:30b64687e01f 373 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
<> 147:30b64687e01f 374 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
<> 147:30b64687e01f 375 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
<> 147:30b64687e01f 376 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
<> 147:30b64687e01f 377 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
<> 147:30b64687e01f 378 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
<> 147:30b64687e01f 379 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
<> 147:30b64687e01f 380 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
<> 147:30b64687e01f 381 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
<> 147:30b64687e01f 382 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
<> 147:30b64687e01f 383 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
<> 147:30b64687e01f 384 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
<> 147:30b64687e01f 385 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
<> 147:30b64687e01f 386 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
<> 147:30b64687e01f 387 } DFSDM_Filter_TypeDef;
<> 147:30b64687e01f 388
<> 147:30b64687e01f 389 /**
<> 147:30b64687e01f 390 * @brief DFSDM channel configuration registers
<> 147:30b64687e01f 391 */
<> 147:30b64687e01f 392 typedef struct
<> 147:30b64687e01f 393 {
<> 147:30b64687e01f 394 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
<> 147:30b64687e01f 395 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
<> 147:30b64687e01f 396 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
<> 147:30b64687e01f 397 short circuit detector register, Address offset: 0x08 */
<> 147:30b64687e01f 398 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
<> 147:30b64687e01f 399 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
<> 147:30b64687e01f 400 } DFSDM_Channel_TypeDef;
<> 147:30b64687e01f 401
<> 147:30b64687e01f 402 /**
<> 147:30b64687e01f 403 * @brief Debug MCU
<> 147:30b64687e01f 404 */
<> 147:30b64687e01f 405
<> 147:30b64687e01f 406 typedef struct
<> 147:30b64687e01f 407 {
<> 147:30b64687e01f 408 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
<> 147:30b64687e01f 409 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 410 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
<> 147:30b64687e01f 411 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
<> 147:30b64687e01f 412 }DBGMCU_TypeDef;
<> 147:30b64687e01f 413
<> 147:30b64687e01f 414 /**
<> 147:30b64687e01f 415 * @brief DCMI
<> 147:30b64687e01f 416 */
<> 147:30b64687e01f 417
<> 147:30b64687e01f 418 typedef struct
<> 147:30b64687e01f 419 {
<> 147:30b64687e01f 420 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 421 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
<> 147:30b64687e01f 422 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
<> 147:30b64687e01f 423 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
<> 147:30b64687e01f 424 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
<> 147:30b64687e01f 425 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
<> 147:30b64687e01f 426 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
<> 147:30b64687e01f 427 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
<> 147:30b64687e01f 428 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
<> 147:30b64687e01f 429 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
<> 147:30b64687e01f 430 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
<> 147:30b64687e01f 431 } DCMI_TypeDef;
<> 147:30b64687e01f 432
<> 147:30b64687e01f 433 /**
<> 147:30b64687e01f 434 * @brief DMA Controller
<> 147:30b64687e01f 435 */
<> 147:30b64687e01f 436
<> 147:30b64687e01f 437 typedef struct
<> 147:30b64687e01f 438 {
<> 147:30b64687e01f 439 __IO uint32_t CR; /*!< DMA stream x configuration register */
<> 147:30b64687e01f 440 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
<> 147:30b64687e01f 441 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
<> 147:30b64687e01f 442 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
<> 147:30b64687e01f 443 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
<> 147:30b64687e01f 444 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
<> 147:30b64687e01f 445 } DMA_Stream_TypeDef;
<> 147:30b64687e01f 446
<> 147:30b64687e01f 447 typedef struct
<> 147:30b64687e01f 448 {
<> 147:30b64687e01f 449 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
<> 147:30b64687e01f 450 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
<> 147:30b64687e01f 451 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
<> 147:30b64687e01f 452 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
<> 147:30b64687e01f 453 } DMA_TypeDef;
<> 147:30b64687e01f 454
<> 147:30b64687e01f 455 /**
<> 147:30b64687e01f 456 * @brief DMA2D Controller
<> 147:30b64687e01f 457 */
<> 147:30b64687e01f 458
<> 147:30b64687e01f 459 typedef struct
<> 147:30b64687e01f 460 {
<> 147:30b64687e01f 461 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
<> 147:30b64687e01f 462 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
<> 147:30b64687e01f 463 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
<> 147:30b64687e01f 464 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
<> 147:30b64687e01f 465 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
<> 147:30b64687e01f 466 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
<> 147:30b64687e01f 467 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
<> 147:30b64687e01f 468 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
<> 147:30b64687e01f 469 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
<> 147:30b64687e01f 470 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
<> 147:30b64687e01f 471 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
<> 147:30b64687e01f 472 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
<> 147:30b64687e01f 473 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
<> 147:30b64687e01f 474 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
<> 147:30b64687e01f 475 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
<> 147:30b64687e01f 476 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
<> 147:30b64687e01f 477 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
<> 147:30b64687e01f 478 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
<> 147:30b64687e01f 479 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
<> 147:30b64687e01f 480 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
<> 147:30b64687e01f 481 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
<> 147:30b64687e01f 482 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
<> 147:30b64687e01f 483 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
<> 147:30b64687e01f 484 } DMA2D_TypeDef;
<> 147:30b64687e01f 485
<> 147:30b64687e01f 486
<> 147:30b64687e01f 487 /**
<> 147:30b64687e01f 488 * @brief Ethernet MAC
<> 147:30b64687e01f 489 */
<> 147:30b64687e01f 490
<> 147:30b64687e01f 491 typedef struct
<> 147:30b64687e01f 492 {
<> 147:30b64687e01f 493 __IO uint32_t MACCR;
<> 147:30b64687e01f 494 __IO uint32_t MACFFR;
<> 147:30b64687e01f 495 __IO uint32_t MACHTHR;
<> 147:30b64687e01f 496 __IO uint32_t MACHTLR;
<> 147:30b64687e01f 497 __IO uint32_t MACMIIAR;
<> 147:30b64687e01f 498 __IO uint32_t MACMIIDR;
<> 147:30b64687e01f 499 __IO uint32_t MACFCR;
<> 147:30b64687e01f 500 __IO uint32_t MACVLANTR; /* 8 */
<> 147:30b64687e01f 501 uint32_t RESERVED0[2];
<> 147:30b64687e01f 502 __IO uint32_t MACRWUFFR; /* 11 */
<> 147:30b64687e01f 503 __IO uint32_t MACPMTCSR;
<> 147:30b64687e01f 504 uint32_t RESERVED1[2];
<> 147:30b64687e01f 505 __IO uint32_t MACSR; /* 15 */
<> 147:30b64687e01f 506 __IO uint32_t MACIMR;
<> 147:30b64687e01f 507 __IO uint32_t MACA0HR;
<> 147:30b64687e01f 508 __IO uint32_t MACA0LR;
<> 147:30b64687e01f 509 __IO uint32_t MACA1HR;
<> 147:30b64687e01f 510 __IO uint32_t MACA1LR;
<> 147:30b64687e01f 511 __IO uint32_t MACA2HR;
<> 147:30b64687e01f 512 __IO uint32_t MACA2LR;
<> 147:30b64687e01f 513 __IO uint32_t MACA3HR;
<> 147:30b64687e01f 514 __IO uint32_t MACA3LR; /* 24 */
<> 147:30b64687e01f 515 uint32_t RESERVED2[40];
<> 147:30b64687e01f 516 __IO uint32_t MMCCR; /* 65 */
<> 147:30b64687e01f 517 __IO uint32_t MMCRIR;
<> 147:30b64687e01f 518 __IO uint32_t MMCTIR;
<> 147:30b64687e01f 519 __IO uint32_t MMCRIMR;
<> 147:30b64687e01f 520 __IO uint32_t MMCTIMR; /* 69 */
<> 147:30b64687e01f 521 uint32_t RESERVED3[14];
<> 147:30b64687e01f 522 __IO uint32_t MMCTGFSCCR; /* 84 */
<> 147:30b64687e01f 523 __IO uint32_t MMCTGFMSCCR;
<> 147:30b64687e01f 524 uint32_t RESERVED4[5];
<> 147:30b64687e01f 525 __IO uint32_t MMCTGFCR;
<> 147:30b64687e01f 526 uint32_t RESERVED5[10];
<> 147:30b64687e01f 527 __IO uint32_t MMCRFCECR;
<> 147:30b64687e01f 528 __IO uint32_t MMCRFAECR;
<> 147:30b64687e01f 529 uint32_t RESERVED6[10];
<> 147:30b64687e01f 530 __IO uint32_t MMCRGUFCR;
<> 147:30b64687e01f 531 uint32_t RESERVED7[334];
<> 147:30b64687e01f 532 __IO uint32_t PTPTSCR;
<> 147:30b64687e01f 533 __IO uint32_t PTPSSIR;
<> 147:30b64687e01f 534 __IO uint32_t PTPTSHR;
<> 147:30b64687e01f 535 __IO uint32_t PTPTSLR;
<> 147:30b64687e01f 536 __IO uint32_t PTPTSHUR;
<> 147:30b64687e01f 537 __IO uint32_t PTPTSLUR;
<> 147:30b64687e01f 538 __IO uint32_t PTPTSAR;
<> 147:30b64687e01f 539 __IO uint32_t PTPTTHR;
<> 147:30b64687e01f 540 __IO uint32_t PTPTTLR;
<> 147:30b64687e01f 541 __IO uint32_t RESERVED8;
<> 147:30b64687e01f 542 __IO uint32_t PTPTSSR;
<> 147:30b64687e01f 543 uint32_t RESERVED9[565];
<> 147:30b64687e01f 544 __IO uint32_t DMABMR;
<> 147:30b64687e01f 545 __IO uint32_t DMATPDR;
<> 147:30b64687e01f 546 __IO uint32_t DMARPDR;
<> 147:30b64687e01f 547 __IO uint32_t DMARDLAR;
<> 147:30b64687e01f 548 __IO uint32_t DMATDLAR;
<> 147:30b64687e01f 549 __IO uint32_t DMASR;
<> 147:30b64687e01f 550 __IO uint32_t DMAOMR;
<> 147:30b64687e01f 551 __IO uint32_t DMAIER;
<> 147:30b64687e01f 552 __IO uint32_t DMAMFBOCR;
<> 147:30b64687e01f 553 __IO uint32_t DMARSWTR;
<> 147:30b64687e01f 554 uint32_t RESERVED10[8];
<> 147:30b64687e01f 555 __IO uint32_t DMACHTDR;
<> 147:30b64687e01f 556 __IO uint32_t DMACHRDR;
<> 147:30b64687e01f 557 __IO uint32_t DMACHTBAR;
<> 147:30b64687e01f 558 __IO uint32_t DMACHRBAR;
<> 147:30b64687e01f 559 } ETH_TypeDef;
<> 147:30b64687e01f 560
<> 147:30b64687e01f 561 /**
<> 147:30b64687e01f 562 * @brief External Interrupt/Event Controller
<> 147:30b64687e01f 563 */
<> 147:30b64687e01f 564
<> 147:30b64687e01f 565 typedef struct
<> 147:30b64687e01f 566 {
<> 147:30b64687e01f 567 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
<> 147:30b64687e01f 568 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
<> 147:30b64687e01f 569 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
<> 147:30b64687e01f 570 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
<> 147:30b64687e01f 571 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
<> 147:30b64687e01f 572 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
<> 147:30b64687e01f 573 } EXTI_TypeDef;
<> 147:30b64687e01f 574
<> 147:30b64687e01f 575 /**
<> 147:30b64687e01f 576 * @brief FLASH Registers
<> 147:30b64687e01f 577 */
<> 147:30b64687e01f 578
<> 147:30b64687e01f 579 typedef struct
<> 147:30b64687e01f 580 {
<> 147:30b64687e01f 581 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
<> 147:30b64687e01f 582 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
<> 147:30b64687e01f 583 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
<> 147:30b64687e01f 584 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
<> 147:30b64687e01f 585 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
<> 147:30b64687e01f 586 __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */
<> 147:30b64687e01f 587 __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */
<> 147:30b64687e01f 588 } FLASH_TypeDef;
<> 147:30b64687e01f 589
<> 147:30b64687e01f 590
<> 147:30b64687e01f 591
<> 147:30b64687e01f 592 /**
<> 147:30b64687e01f 593 * @brief Flexible Memory Controller
<> 147:30b64687e01f 594 */
<> 147:30b64687e01f 595
<> 147:30b64687e01f 596 typedef struct
<> 147:30b64687e01f 597 {
<> 147:30b64687e01f 598 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
<> 147:30b64687e01f 599 } FMC_Bank1_TypeDef;
<> 147:30b64687e01f 600
<> 147:30b64687e01f 601 /**
<> 147:30b64687e01f 602 * @brief Flexible Memory Controller Bank1E
<> 147:30b64687e01f 603 */
<> 147:30b64687e01f 604
<> 147:30b64687e01f 605 typedef struct
<> 147:30b64687e01f 606 {
<> 147:30b64687e01f 607 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
<> 147:30b64687e01f 608 } FMC_Bank1E_TypeDef;
<> 147:30b64687e01f 609
<> 147:30b64687e01f 610 /**
<> 147:30b64687e01f 611 * @brief Flexible Memory Controller Bank3
<> 147:30b64687e01f 612 */
<> 147:30b64687e01f 613
<> 147:30b64687e01f 614 typedef struct
<> 147:30b64687e01f 615 {
<> 147:30b64687e01f 616 __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
<> 147:30b64687e01f 617 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
<> 147:30b64687e01f 618 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
<> 147:30b64687e01f 619 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
<> 147:30b64687e01f 620 uint32_t RESERVED0; /*!< Reserved, 0x90 */
<> 147:30b64687e01f 621 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
<> 147:30b64687e01f 622 } FMC_Bank3_TypeDef;
<> 147:30b64687e01f 623
<> 147:30b64687e01f 624 /**
<> 147:30b64687e01f 625 * @brief Flexible Memory Controller Bank5_6
<> 147:30b64687e01f 626 */
<> 147:30b64687e01f 627
<> 147:30b64687e01f 628 typedef struct
<> 147:30b64687e01f 629 {
<> 147:30b64687e01f 630 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
<> 147:30b64687e01f 631 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
<> 147:30b64687e01f 632 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
<> 147:30b64687e01f 633 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
<> 147:30b64687e01f 634 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
<> 147:30b64687e01f 635 } FMC_Bank5_6_TypeDef;
<> 147:30b64687e01f 636
<> 147:30b64687e01f 637
<> 147:30b64687e01f 638 /**
<> 147:30b64687e01f 639 * @brief General Purpose I/O
<> 147:30b64687e01f 640 */
<> 147:30b64687e01f 641
<> 147:30b64687e01f 642 typedef struct
<> 147:30b64687e01f 643 {
<> 147:30b64687e01f 644 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
<> 147:30b64687e01f 645 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
<> 147:30b64687e01f 646 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
<> 147:30b64687e01f 647 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
<> 147:30b64687e01f 648 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
<> 147:30b64687e01f 649 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
<> 147:30b64687e01f 650 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
<> 147:30b64687e01f 651 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
<> 147:30b64687e01f 652 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
<> 147:30b64687e01f 653 } GPIO_TypeDef;
<> 147:30b64687e01f 654
<> 147:30b64687e01f 655 /**
<> 147:30b64687e01f 656 * @brief System configuration controller
<> 147:30b64687e01f 657 */
<> 147:30b64687e01f 658
<> 147:30b64687e01f 659 typedef struct
<> 147:30b64687e01f 660 {
<> 147:30b64687e01f 661 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
<> 147:30b64687e01f 662 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 663 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
<> 147:30b64687e01f 664 uint32_t RESERVED; /*!< Reserved, 0x18 */
<> 147:30b64687e01f 665 __IO uint32_t CBR; /*!< SYSCFG Class B register, Address offset: 0x1C */
<> 147:30b64687e01f 666 __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */
<> 147:30b64687e01f 667 } SYSCFG_TypeDef;
<> 147:30b64687e01f 668
<> 147:30b64687e01f 669 /**
<> 147:30b64687e01f 670 * @brief Inter-integrated Circuit Interface
<> 147:30b64687e01f 671 */
<> 147:30b64687e01f 672
<> 147:30b64687e01f 673 typedef struct
<> 147:30b64687e01f 674 {
<> 147:30b64687e01f 675 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 676 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 677 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
<> 147:30b64687e01f 678 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
<> 147:30b64687e01f 679 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
<> 147:30b64687e01f 680 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
<> 147:30b64687e01f 681 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
<> 147:30b64687e01f 682 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
<> 147:30b64687e01f 683 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
<> 147:30b64687e01f 684 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
<> 147:30b64687e01f 685 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
<> 147:30b64687e01f 686 } I2C_TypeDef;
<> 147:30b64687e01f 687
<> 147:30b64687e01f 688 /**
<> 147:30b64687e01f 689 * @brief Independent WATCHDOG
<> 147:30b64687e01f 690 */
<> 147:30b64687e01f 691
<> 147:30b64687e01f 692 typedef struct
<> 147:30b64687e01f 693 {
<> 147:30b64687e01f 694 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
<> 147:30b64687e01f 695 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
<> 147:30b64687e01f 696 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
<> 147:30b64687e01f 697 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
<> 147:30b64687e01f 698 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
<> 147:30b64687e01f 699 } IWDG_TypeDef;
<> 147:30b64687e01f 700
<> 147:30b64687e01f 701
<> 147:30b64687e01f 702 /**
<> 147:30b64687e01f 703 * @brief LCD-TFT Display Controller
<> 147:30b64687e01f 704 */
<> 147:30b64687e01f 705
<> 147:30b64687e01f 706 typedef struct
<> 147:30b64687e01f 707 {
<> 147:30b64687e01f 708 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
<> 147:30b64687e01f 709 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
<> 147:30b64687e01f 710 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
<> 147:30b64687e01f 711 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
<> 147:30b64687e01f 712 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
<> 147:30b64687e01f 713 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
<> 147:30b64687e01f 714 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
<> 147:30b64687e01f 715 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
<> 147:30b64687e01f 716 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
<> 147:30b64687e01f 717 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
<> 147:30b64687e01f 718 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
<> 147:30b64687e01f 719 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
<> 147:30b64687e01f 720 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
<> 147:30b64687e01f 721 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
<> 147:30b64687e01f 722 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
<> 147:30b64687e01f 723 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
<> 147:30b64687e01f 724 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
<> 147:30b64687e01f 725 } LTDC_TypeDef;
<> 147:30b64687e01f 726
<> 147:30b64687e01f 727 /**
<> 147:30b64687e01f 728 * @brief LCD-TFT Display layer x Controller
<> 147:30b64687e01f 729 */
<> 147:30b64687e01f 730
<> 147:30b64687e01f 731 typedef struct
<> 147:30b64687e01f 732 {
<> 147:30b64687e01f 733 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
<> 147:30b64687e01f 734 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
<> 147:30b64687e01f 735 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
<> 147:30b64687e01f 736 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
<> 147:30b64687e01f 737 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
<> 147:30b64687e01f 738 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
<> 147:30b64687e01f 739 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
<> 147:30b64687e01f 740 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
<> 147:30b64687e01f 741 uint32_t RESERVED0[2]; /*!< Reserved */
<> 147:30b64687e01f 742 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
<> 147:30b64687e01f 743 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
<> 147:30b64687e01f 744 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
<> 147:30b64687e01f 745 uint32_t RESERVED1[3]; /*!< Reserved */
<> 147:30b64687e01f 746 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
<> 147:30b64687e01f 747
<> 147:30b64687e01f 748 } LTDC_Layer_TypeDef;
<> 147:30b64687e01f 749
<> 147:30b64687e01f 750 /**
<> 147:30b64687e01f 751 * @brief Power Control
<> 147:30b64687e01f 752 */
<> 147:30b64687e01f 753
<> 147:30b64687e01f 754 typedef struct
<> 147:30b64687e01f 755 {
<> 147:30b64687e01f 756 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 757 __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */
<> 147:30b64687e01f 758 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
<> 147:30b64687e01f 759 __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */
<> 147:30b64687e01f 760 } PWR_TypeDef;
<> 147:30b64687e01f 761
<> 147:30b64687e01f 762
<> 147:30b64687e01f 763 /**
<> 147:30b64687e01f 764 * @brief Reset and Clock Control
<> 147:30b64687e01f 765 */
<> 147:30b64687e01f 766
<> 147:30b64687e01f 767 typedef struct
<> 147:30b64687e01f 768 {
<> 147:30b64687e01f 769 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
<> 147:30b64687e01f 770 __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 771 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
<> 147:30b64687e01f 772 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */
<> 147:30b64687e01f 773 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */
<> 147:30b64687e01f 774 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */
<> 147:30b64687e01f 775 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */
<> 147:30b64687e01f 776 uint32_t RESERVED0; /*!< Reserved, 0x1C */
<> 147:30b64687e01f 777 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */
<> 147:30b64687e01f 778 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
<> 147:30b64687e01f 779 uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */
<> 147:30b64687e01f 780 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */
<> 147:30b64687e01f 781 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */
<> 147:30b64687e01f 782 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */
<> 147:30b64687e01f 783 uint32_t RESERVED2; /*!< Reserved, 0x3C */
<> 147:30b64687e01f 784 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */
<> 147:30b64687e01f 785 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */
<> 147:30b64687e01f 786 uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */
<> 147:30b64687e01f 787 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
<> 147:30b64687e01f 788 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
<> 147:30b64687e01f 789 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
<> 147:30b64687e01f 790 uint32_t RESERVED4; /*!< Reserved, 0x5C */
<> 147:30b64687e01f 791 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
<> 147:30b64687e01f 792 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
<> 147:30b64687e01f 793 uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */
<> 147:30b64687e01f 794 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */
<> 147:30b64687e01f 795 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
<> 147:30b64687e01f 796 uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */
<> 147:30b64687e01f 797 __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */
<> 147:30b64687e01f 798 __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */
<> 147:30b64687e01f 799 __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */
<> 147:30b64687e01f 800 __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */
<> 147:30b64687e01f 801 __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */
<> 147:30b64687e01f 802
<> 147:30b64687e01f 803 } RCC_TypeDef;
<> 147:30b64687e01f 804
<> 147:30b64687e01f 805 /**
<> 147:30b64687e01f 806 * @brief Real-Time Clock
<> 147:30b64687e01f 807 */
<> 147:30b64687e01f 808
<> 147:30b64687e01f 809 typedef struct
<> 147:30b64687e01f 810 {
<> 147:30b64687e01f 811 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
<> 147:30b64687e01f 812 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
<> 147:30b64687e01f 813 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
<> 147:30b64687e01f 814 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
<> 147:30b64687e01f 815 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
<> 147:30b64687e01f 816 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
<> 147:30b64687e01f 817 uint32_t reserved; /*!< Reserved */
<> 147:30b64687e01f 818 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
<> 147:30b64687e01f 819 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
<> 147:30b64687e01f 820 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
<> 147:30b64687e01f 821 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
<> 147:30b64687e01f 822 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
<> 147:30b64687e01f 823 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
<> 147:30b64687e01f 824 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
<> 147:30b64687e01f 825 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
<> 147:30b64687e01f 826 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
<> 147:30b64687e01f 827 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
<> 147:30b64687e01f 828 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
<> 147:30b64687e01f 829 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
<> 147:30b64687e01f 830 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
<> 147:30b64687e01f 831 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
<> 147:30b64687e01f 832 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
<> 147:30b64687e01f 833 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
<> 147:30b64687e01f 834 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
<> 147:30b64687e01f 835 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
<> 147:30b64687e01f 836 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
<> 147:30b64687e01f 837 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
<> 147:30b64687e01f 838 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
<> 147:30b64687e01f 839 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
<> 147:30b64687e01f 840 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
<> 147:30b64687e01f 841 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
<> 147:30b64687e01f 842 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
<> 147:30b64687e01f 843 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
<> 147:30b64687e01f 844 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
<> 147:30b64687e01f 845 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
<> 147:30b64687e01f 846 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
<> 147:30b64687e01f 847 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
<> 147:30b64687e01f 848 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
<> 147:30b64687e01f 849 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
<> 147:30b64687e01f 850 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
<> 147:30b64687e01f 851 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
<> 147:30b64687e01f 852 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
<> 147:30b64687e01f 853 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
<> 147:30b64687e01f 854 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
<> 147:30b64687e01f 855 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
<> 147:30b64687e01f 856 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
<> 147:30b64687e01f 857 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
<> 147:30b64687e01f 858 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
<> 147:30b64687e01f 859 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
<> 147:30b64687e01f 860 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
<> 147:30b64687e01f 861 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
<> 147:30b64687e01f 862 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
<> 147:30b64687e01f 863 } RTC_TypeDef;
<> 147:30b64687e01f 864
<> 147:30b64687e01f 865
<> 147:30b64687e01f 866 /**
<> 147:30b64687e01f 867 * @brief Serial Audio Interface
<> 147:30b64687e01f 868 */
<> 147:30b64687e01f 869
<> 147:30b64687e01f 870 typedef struct
<> 147:30b64687e01f 871 {
<> 147:30b64687e01f 872 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
<> 147:30b64687e01f 873 } SAI_TypeDef;
<> 147:30b64687e01f 874
<> 147:30b64687e01f 875 typedef struct
<> 147:30b64687e01f 876 {
<> 147:30b64687e01f 877 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
<> 147:30b64687e01f 878 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
<> 147:30b64687e01f 879 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
<> 147:30b64687e01f 880 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
<> 147:30b64687e01f 881 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
<> 147:30b64687e01f 882 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
<> 147:30b64687e01f 883 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
<> 147:30b64687e01f 884 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
<> 147:30b64687e01f 885 } SAI_Block_TypeDef;
<> 147:30b64687e01f 886
<> 147:30b64687e01f 887 /**
<> 147:30b64687e01f 888 * @brief SPDIF-RX Interface
<> 147:30b64687e01f 889 */
<> 147:30b64687e01f 890
<> 147:30b64687e01f 891 typedef struct
<> 147:30b64687e01f 892 {
<> 147:30b64687e01f 893 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
<> 147:30b64687e01f 894 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
<> 147:30b64687e01f 895 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
<> 147:30b64687e01f 896 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
<> 147:30b64687e01f 897 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
<> 147:30b64687e01f 898 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
<> 147:30b64687e01f 899 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
<> 147:30b64687e01f 900 } SPDIFRX_TypeDef;
<> 147:30b64687e01f 901
<> 147:30b64687e01f 902 /**
<> 147:30b64687e01f 903 * @brief SD host Interface
<> 147:30b64687e01f 904 */
<> 147:30b64687e01f 905
<> 147:30b64687e01f 906 typedef struct
<> 147:30b64687e01f 907 {
<> 147:30b64687e01f 908 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
<> 147:30b64687e01f 909 __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */
<> 147:30b64687e01f 910 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
<> 147:30b64687e01f 911 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
<> 147:30b64687e01f 912 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
<> 147:30b64687e01f 913 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
<> 147:30b64687e01f 914 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
<> 147:30b64687e01f 915 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
<> 147:30b64687e01f 916 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
<> 147:30b64687e01f 917 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
<> 147:30b64687e01f 918 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
<> 147:30b64687e01f 919 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
<> 147:30b64687e01f 920 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
<> 147:30b64687e01f 921 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
<> 147:30b64687e01f 922 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
<> 147:30b64687e01f 923 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
<> 147:30b64687e01f 924 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
<> 147:30b64687e01f 925 __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
<> 147:30b64687e01f 926 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
<> 147:30b64687e01f 927 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
<> 147:30b64687e01f 928 } SDMMC_TypeDef;
<> 147:30b64687e01f 929
<> 147:30b64687e01f 930 /**
<> 147:30b64687e01f 931 * @brief Serial Peripheral Interface
<> 147:30b64687e01f 932 */
<> 147:30b64687e01f 933
<> 147:30b64687e01f 934 typedef struct
<> 147:30b64687e01f 935 {
<> 147:30b64687e01f 936 __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
<> 147:30b64687e01f 937 __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 938 __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */
<> 147:30b64687e01f 939 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
<> 147:30b64687e01f 940 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
<> 147:30b64687e01f 941 __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
<> 147:30b64687e01f 942 __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
<> 147:30b64687e01f 943 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
<> 147:30b64687e01f 944 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
<> 147:30b64687e01f 945 } SPI_TypeDef;
<> 147:30b64687e01f 946
<> 147:30b64687e01f 947 /**
<> 147:30b64687e01f 948 * @brief QUAD Serial Peripheral Interface
<> 147:30b64687e01f 949 */
<> 147:30b64687e01f 950
<> 147:30b64687e01f 951 typedef struct
<> 147:30b64687e01f 952 {
<> 147:30b64687e01f 953 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
<> 147:30b64687e01f 954 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 955 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
<> 147:30b64687e01f 956 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
<> 147:30b64687e01f 957 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
<> 147:30b64687e01f 958 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
<> 147:30b64687e01f 959 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
<> 147:30b64687e01f 960 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
<> 147:30b64687e01f 961 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
<> 147:30b64687e01f 962 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
<> 147:30b64687e01f 963 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
<> 147:30b64687e01f 964 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
<> 147:30b64687e01f 965 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
<> 147:30b64687e01f 966 } QUADSPI_TypeDef;
<> 147:30b64687e01f 967
<> 147:30b64687e01f 968 /**
<> 147:30b64687e01f 969 * @brief TIM
<> 147:30b64687e01f 970 */
<> 147:30b64687e01f 971
<> 147:30b64687e01f 972 typedef struct
<> 147:30b64687e01f 973 {
<> 147:30b64687e01f 974 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 975 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 976 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
<> 147:30b64687e01f 977 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
<> 147:30b64687e01f 978 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
<> 147:30b64687e01f 979 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
<> 147:30b64687e01f 980 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
<> 147:30b64687e01f 981 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
<> 147:30b64687e01f 982 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
<> 147:30b64687e01f 983 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
<> 147:30b64687e01f 984 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
<> 147:30b64687e01f 985 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
<> 147:30b64687e01f 986 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
<> 147:30b64687e01f 987 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
<> 147:30b64687e01f 988 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
<> 147:30b64687e01f 989 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
<> 147:30b64687e01f 990 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
<> 147:30b64687e01f 991 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
<> 147:30b64687e01f 992 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
<> 147:30b64687e01f 993 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
<> 147:30b64687e01f 994 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
<> 147:30b64687e01f 995 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
<> 147:30b64687e01f 996 __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */
<> 147:30b64687e01f 997 __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */
<> 147:30b64687e01f 998 __IO uint32_t AF1; /*!< TIM Alternate function option register 1, Address offset: 0x60 */
<> 147:30b64687e01f 999 __IO uint32_t AF2; /*!< TIM Alternate function option register 2, Address offset: 0x64 */
<> 147:30b64687e01f 1000
<> 147:30b64687e01f 1001 } TIM_TypeDef;
<> 147:30b64687e01f 1002
<> 147:30b64687e01f 1003 /**
<> 147:30b64687e01f 1004 * @brief LPTIMIMER
<> 147:30b64687e01f 1005 */
<> 147:30b64687e01f 1006 typedef struct
<> 147:30b64687e01f 1007 {
<> 147:30b64687e01f 1008 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
<> 147:30b64687e01f 1009 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
<> 147:30b64687e01f 1010 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
<> 147:30b64687e01f 1011 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
<> 147:30b64687e01f 1012 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
<> 147:30b64687e01f 1013 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
<> 147:30b64687e01f 1014 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
<> 147:30b64687e01f 1015 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
<> 147:30b64687e01f 1016 } LPTIM_TypeDef;
<> 147:30b64687e01f 1017
<> 147:30b64687e01f 1018
<> 147:30b64687e01f 1019 /**
<> 147:30b64687e01f 1020 * @brief Universal Synchronous Asynchronous Receiver Transmitter
<> 147:30b64687e01f 1021 */
<> 147:30b64687e01f 1022
<> 147:30b64687e01f 1023 typedef struct
<> 147:30b64687e01f 1024 {
<> 147:30b64687e01f 1025 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
<> 147:30b64687e01f 1026 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
<> 147:30b64687e01f 1027 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
<> 147:30b64687e01f 1028 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
<> 147:30b64687e01f 1029 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
<> 147:30b64687e01f 1030 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
<> 147:30b64687e01f 1031 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
<> 147:30b64687e01f 1032 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
<> 147:30b64687e01f 1033 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
<> 147:30b64687e01f 1034 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
<> 147:30b64687e01f 1035 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
<> 147:30b64687e01f 1036 } USART_TypeDef;
<> 147:30b64687e01f 1037
<> 147:30b64687e01f 1038
<> 147:30b64687e01f 1039 /**
<> 147:30b64687e01f 1040 * @brief Window WATCHDOG
<> 147:30b64687e01f 1041 */
<> 147:30b64687e01f 1042
<> 147:30b64687e01f 1043 typedef struct
<> 147:30b64687e01f 1044 {
<> 147:30b64687e01f 1045 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
<> 147:30b64687e01f 1046 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
<> 147:30b64687e01f 1047 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
<> 147:30b64687e01f 1048 } WWDG_TypeDef;
<> 147:30b64687e01f 1049
<> 147:30b64687e01f 1050
<> 147:30b64687e01f 1051 /**
<> 147:30b64687e01f 1052 * @brief RNG
<> 147:30b64687e01f 1053 */
<> 147:30b64687e01f 1054
<> 147:30b64687e01f 1055 typedef struct
<> 147:30b64687e01f 1056 {
<> 147:30b64687e01f 1057 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
<> 147:30b64687e01f 1058 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
<> 147:30b64687e01f 1059 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
<> 147:30b64687e01f 1060 } RNG_TypeDef;
<> 147:30b64687e01f 1061
<> 147:30b64687e01f 1062 /**
<> 147:30b64687e01f 1063 * @}
<> 147:30b64687e01f 1064 */
<> 147:30b64687e01f 1065
<> 147:30b64687e01f 1066 /**
<> 147:30b64687e01f 1067 * @brief USB_OTG_Core_Registers
<> 147:30b64687e01f 1068 */
<> 147:30b64687e01f 1069 typedef struct
<> 147:30b64687e01f 1070 {
<> 147:30b64687e01f 1071 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
<> 147:30b64687e01f 1072 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
<> 147:30b64687e01f 1073 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
<> 147:30b64687e01f 1074 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
<> 147:30b64687e01f 1075 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
<> 147:30b64687e01f 1076 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
<> 147:30b64687e01f 1077 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
<> 147:30b64687e01f 1078 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
<> 147:30b64687e01f 1079 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
<> 147:30b64687e01f 1080 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
<> 147:30b64687e01f 1081 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
<> 147:30b64687e01f 1082 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
<> 147:30b64687e01f 1083 uint32_t Reserved30[2]; /*!< Reserved 030h */
<> 147:30b64687e01f 1084 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
<> 147:30b64687e01f 1085 __IO uint32_t CID; /*!< User ID Register 03Ch */
<> 147:30b64687e01f 1086 uint32_t Reserved5[3]; /*!< Reserved 040h-048h */
<> 147:30b64687e01f 1087 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
<> 147:30b64687e01f 1088 uint32_t Reserved6; /*!< Reserved 050h */
<> 147:30b64687e01f 1089 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
<> 147:30b64687e01f 1090 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
<> 147:30b64687e01f 1091 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
<> 147:30b64687e01f 1092 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
<> 147:30b64687e01f 1093 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
<> 147:30b64687e01f 1094 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
<> 147:30b64687e01f 1095 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
<> 147:30b64687e01f 1096 } USB_OTG_GlobalTypeDef;
<> 147:30b64687e01f 1097
<> 147:30b64687e01f 1098
<> 147:30b64687e01f 1099 /**
<> 147:30b64687e01f 1100 * @brief USB_OTG_device_Registers
<> 147:30b64687e01f 1101 */
<> 147:30b64687e01f 1102 typedef struct
<> 147:30b64687e01f 1103 {
<> 147:30b64687e01f 1104 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
<> 147:30b64687e01f 1105 __IO uint32_t DCTL; /*!< dev Control Register 804h */
<> 147:30b64687e01f 1106 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
<> 147:30b64687e01f 1107 uint32_t Reserved0C; /*!< Reserved 80Ch */
<> 147:30b64687e01f 1108 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
<> 147:30b64687e01f 1109 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
<> 147:30b64687e01f 1110 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
<> 147:30b64687e01f 1111 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
<> 147:30b64687e01f 1112 uint32_t Reserved20; /*!< Reserved 820h */
<> 147:30b64687e01f 1113 uint32_t Reserved9; /*!< Reserved 824h */
<> 147:30b64687e01f 1114 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
<> 147:30b64687e01f 1115 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
<> 147:30b64687e01f 1116 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
<> 147:30b64687e01f 1117 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
<> 147:30b64687e01f 1118 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
<> 147:30b64687e01f 1119 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
<> 147:30b64687e01f 1120 uint32_t Reserved40; /*!< dedicated EP mask 840h */
<> 147:30b64687e01f 1121 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
<> 147:30b64687e01f 1122 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
<> 147:30b64687e01f 1123 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
<> 147:30b64687e01f 1124 } USB_OTG_DeviceTypeDef;
<> 147:30b64687e01f 1125
<> 147:30b64687e01f 1126
<> 147:30b64687e01f 1127 /**
<> 147:30b64687e01f 1128 * @brief USB_OTG_IN_Endpoint-Specific_Register
<> 147:30b64687e01f 1129 */
<> 147:30b64687e01f 1130 typedef struct
<> 147:30b64687e01f 1131 {
<> 147:30b64687e01f 1132 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
<> 147:30b64687e01f 1133 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
<> 147:30b64687e01f 1134 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
<> 147:30b64687e01f 1135 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
<> 147:30b64687e01f 1136 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
<> 147:30b64687e01f 1137 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
<> 147:30b64687e01f 1138 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
<> 147:30b64687e01f 1139 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
<> 147:30b64687e01f 1140 } USB_OTG_INEndpointTypeDef;
<> 147:30b64687e01f 1141
<> 147:30b64687e01f 1142
<> 147:30b64687e01f 1143 /**
<> 147:30b64687e01f 1144 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
<> 147:30b64687e01f 1145 */
<> 147:30b64687e01f 1146 typedef struct
<> 147:30b64687e01f 1147 {
<> 147:30b64687e01f 1148 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
<> 147:30b64687e01f 1149 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
<> 147:30b64687e01f 1150 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
<> 147:30b64687e01f 1151 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
<> 147:30b64687e01f 1152 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
<> 147:30b64687e01f 1153 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
<> 147:30b64687e01f 1154 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
<> 147:30b64687e01f 1155 } USB_OTG_OUTEndpointTypeDef;
<> 147:30b64687e01f 1156
<> 147:30b64687e01f 1157
<> 147:30b64687e01f 1158 /**
<> 147:30b64687e01f 1159 * @brief USB_OTG_Host_Mode_Register_Structures
<> 147:30b64687e01f 1160 */
<> 147:30b64687e01f 1161 typedef struct
<> 147:30b64687e01f 1162 {
<> 147:30b64687e01f 1163 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
<> 147:30b64687e01f 1164 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
<> 147:30b64687e01f 1165 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
<> 147:30b64687e01f 1166 uint32_t Reserved40C; /*!< Reserved 40Ch */
<> 147:30b64687e01f 1167 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
<> 147:30b64687e01f 1168 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
<> 147:30b64687e01f 1169 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
<> 147:30b64687e01f 1170 } USB_OTG_HostTypeDef;
<> 147:30b64687e01f 1171
<> 147:30b64687e01f 1172 /**
<> 147:30b64687e01f 1173 * @brief USB_OTG_Host_Channel_Specific_Registers
<> 147:30b64687e01f 1174 */
<> 147:30b64687e01f 1175 typedef struct
<> 147:30b64687e01f 1176 {
<> 147:30b64687e01f 1177 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
<> 147:30b64687e01f 1178 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
<> 147:30b64687e01f 1179 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
<> 147:30b64687e01f 1180 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
<> 147:30b64687e01f 1181 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
<> 147:30b64687e01f 1182 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
<> 147:30b64687e01f 1183 uint32_t Reserved[2]; /*!< Reserved */
<> 147:30b64687e01f 1184 } USB_OTG_HostChannelTypeDef;
<> 147:30b64687e01f 1185 /**
<> 147:30b64687e01f 1186 * @}
<> 147:30b64687e01f 1187 */
<> 147:30b64687e01f 1188
<> 147:30b64687e01f 1189 /**
<> 147:30b64687e01f 1190 * @brief JPEG Codec
<> 147:30b64687e01f 1191 */
<> 147:30b64687e01f 1192 typedef struct
<> 147:30b64687e01f 1193 {
<> 147:30b64687e01f 1194 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
<> 147:30b64687e01f 1195 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
<> 147:30b64687e01f 1196 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
<> 147:30b64687e01f 1197 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
<> 147:30b64687e01f 1198 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
<> 147:30b64687e01f 1199 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
<> 147:30b64687e01f 1200 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
<> 147:30b64687e01f 1201 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
<> 147:30b64687e01f 1202 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
<> 147:30b64687e01f 1203 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
<> 147:30b64687e01f 1204 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
<> 147:30b64687e01f 1205 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
<> 147:30b64687e01f 1206 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
<> 147:30b64687e01f 1207 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
<> 147:30b64687e01f 1208 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
<> 147:30b64687e01f 1209 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
<> 147:30b64687e01f 1210 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
<> 147:30b64687e01f 1211 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
<> 147:30b64687e01f 1212 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
<> 147:30b64687e01f 1213 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
<> 147:30b64687e01f 1214 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
<> 147:30b64687e01f 1215 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
<> 147:30b64687e01f 1216 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
<> 147:30b64687e01f 1217 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
<> 147:30b64687e01f 1218 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
<> 147:30b64687e01f 1219 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encoder, AC Huffman table 0, Address offset: 500h-65Ch */
<> 147:30b64687e01f 1220 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encoder, AC Huffman table 1, Address offset: 660h-7BCh */
<> 147:30b64687e01f 1221 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encoder, DC Huffman table 0, Address offset: 7C0h-7DCh */
<> 147:30b64687e01f 1222 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encoder, DC Huffman table 1, Address offset: 7E0h-7FCh */
<> 147:30b64687e01f 1223
<> 147:30b64687e01f 1224 } JPEG_TypeDef;
<> 147:30b64687e01f 1225
<> 147:30b64687e01f 1226 /**
<> 147:30b64687e01f 1227 * @brief MDIOS
<> 147:30b64687e01f 1228 */
<> 147:30b64687e01f 1229
<> 147:30b64687e01f 1230 typedef struct
<> 147:30b64687e01f 1231 {
<> 147:30b64687e01f 1232 __IO uint32_t CR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 00h */
<> 147:30b64687e01f 1233 __IO uint32_t WRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 04h */
<> 147:30b64687e01f 1234 __IO uint32_t CWRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 08h */
<> 147:30b64687e01f 1235 __IO uint32_t RDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 0Ch */
<> 147:30b64687e01f 1236 __IO uint32_t CRDFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 10h */
<> 147:30b64687e01f 1237 __IO uint32_t SR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 14h */
<> 147:30b64687e01f 1238 __IO uint32_t CLRFR; /*!< MDIOS Configuration Register (MDIOS_CR), Address offset: 18h */
<> 147:30b64687e01f 1239 uint32_t RESERVED0[57]; /* Reserved Address offset: 1Ch */
<> 147:30b64687e01f 1240 __IO uint32_t DINR0; /*!< MDIOS Input Data Register (MDIOS_DINR0), Address offset: 100h */
<> 147:30b64687e01f 1241 __IO uint32_t DINR1; /*!< MDIOS Input Data Register (MDIOS_DINR1), Address offset: 104h */
<> 147:30b64687e01f 1242 __IO uint32_t DINR2; /*!< MDIOS Input Data Register (MDIOS_DINR2), Address offset: 108h */
<> 147:30b64687e01f 1243 __IO uint32_t DINR3; /*!< MDIOS Input Data Register (MDIOS_DINR3), Address offset: 10Ch */
<> 147:30b64687e01f 1244 __IO uint32_t DINR4; /*!< MDIOS Input Data Register (MDIOS_DINR4), Address offset: 110h */
<> 147:30b64687e01f 1245 __IO uint32_t DINR5; /*!< MDIOS Input Data Register (MDIOS_DINR5), Address offset: 114h */
<> 147:30b64687e01f 1246 __IO uint32_t DINR6; /*!< MDIOS Input Data Register (MDIOS_DINR6), Address offset: 118h */
<> 147:30b64687e01f 1247 __IO uint32_t DINR7; /*!< MDIOS Input Data Register (MDIOS_DINR7), Address offset: 11Ch */
<> 147:30b64687e01f 1248 __IO uint32_t DINR8; /*!< MDIOS Input Data Register (MDIOS_DINR8), Address offset: 120h */
<> 147:30b64687e01f 1249 __IO uint32_t DINR9; /*!< MDIOS Input Data Register (MDIOS_DINR9), Address offset: 124h */
<> 147:30b64687e01f 1250 __IO uint32_t DINR10; /*!< MDIOS Input Data Register (MDIOS_DINR10), Address offset: 128h */
<> 147:30b64687e01f 1251 __IO uint32_t DINR11; /*!< MDIOS Input Data Register (MDIOS_DINR11), Address offset: 12Ch */
<> 147:30b64687e01f 1252 __IO uint32_t DINR12; /*!< MDIOS Input Data Register (MDIOS_DINR12), Address offset: 130h */
<> 147:30b64687e01f 1253 __IO uint32_t DINR13; /*!< MDIOS Input Data Register (MDIOS_DINR13), Address offset: 134h */
<> 147:30b64687e01f 1254 __IO uint32_t DINR14; /*!< MDIOS Input Data Register (MDIOS_DINR14), Address offset: 138h */
<> 147:30b64687e01f 1255 __IO uint32_t DINR15; /*!< MDIOS Input Data Register (MDIOS_DINR15), Address offset: 13Ch */
<> 147:30b64687e01f 1256 __IO uint32_t DINR16; /*!< MDIOS Input Data Register (MDIOS_DINR16), Address offset: 140h */
<> 147:30b64687e01f 1257 __IO uint32_t DINR17; /*!< MDIOS Input Data Register (MDIOS_DINR17), Address offset: 144h */
<> 147:30b64687e01f 1258 __IO uint32_t DINR18; /*!< MDIOS Input Data Register (MDIOS_DINR18), Address offset: 148h */
<> 147:30b64687e01f 1259 __IO uint32_t DINR19; /*!< MDIOS Input Data Register (MDIOS_DINR19), Address offset: 14Ch */
<> 147:30b64687e01f 1260 __IO uint32_t DINR20; /*!< MDIOS Input Data Register (MDIOS_DINR20), Address offset: 150h */
<> 147:30b64687e01f 1261 __IO uint32_t DINR21; /*!< MDIOS Input Data Register (MDIOS_DINR21), Address offset: 154h */
<> 147:30b64687e01f 1262 __IO uint32_t DINR22; /*!< MDIOS Input Data Register (MDIOS_DINR22), Address offset: 158h */
<> 147:30b64687e01f 1263 __IO uint32_t DINR23; /*!< MDIOS Input Data Register (MDIOS_DINR23), Address offset: 15Ch */
<> 147:30b64687e01f 1264 __IO uint32_t DINR24; /*!< MDIOS Input Data Register (MDIOS_DINR24), Address offset: 160h */
<> 147:30b64687e01f 1265 __IO uint32_t DINR25; /*!< MDIOS Input Data Register (MDIOS_DINR25), Address offset: 164h */
<> 147:30b64687e01f 1266 __IO uint32_t DINR26; /*!< MDIOS Input Data Register (MDIOS_DINR26), Address offset: 168h */
<> 147:30b64687e01f 1267 __IO uint32_t DINR27; /*!< MDIOS Input Data Register (MDIOS_DINR27), Address offset: 16Ch */
<> 147:30b64687e01f 1268 __IO uint32_t DINR28; /*!< MDIOS Input Data Register (MDIOS_DINR28), Address offset: 170h */
<> 147:30b64687e01f 1269 __IO uint32_t DINR29; /*!< MDIOS Input Data Register (MDIOS_DINR29), Address offset: 174h */
<> 147:30b64687e01f 1270 __IO uint32_t DINR30; /*!< MDIOS Input Data Register (MDIOS_DINR30), Address offset: 178h */
<> 147:30b64687e01f 1271 __IO uint32_t DINR31; /*!< MDIOS Input Data Register (MDIOS_DINR31), Address offset: 17Ch */
<> 147:30b64687e01f 1272 __IO uint32_t DOUTR0; /*!< MDIOS Output Data Register (MDIOS_DOUTR0), Address offset: 180h */
<> 147:30b64687e01f 1273 __IO uint32_t DOUTR1; /*!< MDIOS Output Data Register (MDIOS_DOUTR1), Address offset: 184h */
<> 147:30b64687e01f 1274 __IO uint32_t DOUTR2; /*!< MDIOS Output Data Register (MDIOS_DOUTR2), Address offset: 188h */
<> 147:30b64687e01f 1275 __IO uint32_t DOUTR3; /*!< MDIOS Output Data Register (MDIOS_DOUTR3), Address offset: 18Ch */
<> 147:30b64687e01f 1276 __IO uint32_t DOUTR4; /*!< MDIOS Output Data Register (MDIOS_DOUTR4), Address offset: 190h */
<> 147:30b64687e01f 1277 __IO uint32_t DOUTR5; /*!< MDIOS Output Data Register (MDIOS_DOUTR5), Address offset: 194h */
<> 147:30b64687e01f 1278 __IO uint32_t DOUTR6; /*!< MDIOS Output Data Register (MDIOS_DOUTR6), Address offset: 198h */
<> 147:30b64687e01f 1279 __IO uint32_t DOUTR7; /*!< MDIOS Output Data Register (MDIOS_DOUTR7), Address offset: 19Ch */
<> 147:30b64687e01f 1280 __IO uint32_t DOUTR8; /*!< MDIOS Output Data Register (MDIOS_DOUTR8), Address offset: 1A0h */
<> 147:30b64687e01f 1281 __IO uint32_t DOUTR9; /*!< MDIOS Output Data Register (MDIOS_DOUTR9), Address offset: 1A4h */
<> 147:30b64687e01f 1282 __IO uint32_t DOUTR10; /*!< MDIOS Output Data Register (MDIOS_DOUTR10), Address offset: 1A8h */
<> 147:30b64687e01f 1283 __IO uint32_t DOUTR11; /*!< MDIOS Output Data Register (MDIOS_DOUTR11), Address offset: 1ACh */
<> 147:30b64687e01f 1284 __IO uint32_t DOUTR12; /*!< MDIOS Output Data Register (MDIOS_DOUTR12), Address offset: 1B0h */
<> 147:30b64687e01f 1285 __IO uint32_t DOUTR13; /*!< MDIOS Output Data Register (MDIOS_DOUTR13), Address offset: 1B4h */
<> 147:30b64687e01f 1286 __IO uint32_t DOUTR14; /*!< MDIOS Output Data Register (MDIOS_DOUTR14), Address offset: 1B8h */
<> 147:30b64687e01f 1287 __IO uint32_t DOUTR15; /*!< MDIOS Output Data Register (MDIOS_DOUTR15), Address offset: 1BCh */
<> 147:30b64687e01f 1288 __IO uint32_t DOUTR16; /*!< MDIOS Output Data Register (MDIOS_DOUTR16), Address offset: 1C0h */
<> 147:30b64687e01f 1289 __IO uint32_t DOUTR17; /*!< MDIOS Output Data Register (MDIOS_DOUTR17), Address offset: 1C4h */
<> 147:30b64687e01f 1290 __IO uint32_t DOUTR18; /*!< MDIOS Output Data Register (MDIOS_DOUTR18), Address offset: 1C8h */
<> 147:30b64687e01f 1291 __IO uint32_t DOUTR19; /*!< MDIOS Output Data Register (MDIOS_DOUTR19), Address offset: 1CCh */
<> 147:30b64687e01f 1292 __IO uint32_t DOUTR20; /*!< MDIOS Output Data Register (MDIOS_DOUTR20), Address offset: 1D0h */
<> 147:30b64687e01f 1293 __IO uint32_t DOUTR21; /*!< MDIOS Output Data Register (MDIOS_DOUTR21), Address offset: 1D4h */
<> 147:30b64687e01f 1294 __IO uint32_t DOUTR22; /*!< MDIOS Output Data Register (MDIOS_DOUTR22), Address offset: 1D8h */
<> 147:30b64687e01f 1295 __IO uint32_t DOUTR23; /*!< MDIOS Output Data Register (MDIOS_DOUTR23), Address offset: 1DCh */
<> 147:30b64687e01f 1296 __IO uint32_t DOUTR24; /*!< MDIOS Output Data Register (MDIOS_DOUTR24), Address offset: 1E0h */
<> 147:30b64687e01f 1297 __IO uint32_t DOUTR25; /*!< MDIOS Output Data Register (MDIOS_DOUTR25), Address offset: 1E4h */
<> 147:30b64687e01f 1298 __IO uint32_t DOUTR26; /*!< MDIOS Output Data Register (MDIOS_DOUTR26), Address offset: 1E8h */
<> 147:30b64687e01f 1299 __IO uint32_t DOUTR27; /*!< MDIOS Output Data Register (MDIOS_DOUTR27), Address offset: 1ECh */
<> 147:30b64687e01f 1300 __IO uint32_t DOUTR28; /*!< MDIOS Output Data Register (MDIOS_DOUTR28), Address offset: 1F0h */
<> 147:30b64687e01f 1301 __IO uint32_t DOUTR29; /*!< MDIOS Output Data Register (MDIOS_DOUTR29), Address offset: 1F4h */
<> 147:30b64687e01f 1302 __IO uint32_t DOUTR30; /*!< MDIOS Output Data Register (MDIOS_DOUTR30), Address offset: 1F8h */
<> 147:30b64687e01f 1303 __IO uint32_t DOUTR31; /*!< MDIOS Output Data Register (MDIOS_DOUTR31), Address offset: 1FCh */
<> 147:30b64687e01f 1304 } MDIOS_TypeDef;
<> 147:30b64687e01f 1305
<> 147:30b64687e01f 1306 /**
<> 147:30b64687e01f 1307 * @brief DSI Controller
<> 147:30b64687e01f 1308 */
<> 147:30b64687e01f 1309
<> 147:30b64687e01f 1310 typedef struct
<> 147:30b64687e01f 1311 {
<> 147:30b64687e01f 1312 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
<> 147:30b64687e01f 1313 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
<> 147:30b64687e01f 1314 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
<> 147:30b64687e01f 1315 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
<> 147:30b64687e01f 1316 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
<> 147:30b64687e01f 1317 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
<> 147:30b64687e01f 1318 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
<> 147:30b64687e01f 1319 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
<> 147:30b64687e01f 1320 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
<> 147:30b64687e01f 1321 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
<> 147:30b64687e01f 1322 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
<> 147:30b64687e01f 1323 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
<> 147:30b64687e01f 1324 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
<> 147:30b64687e01f 1325 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
<> 147:30b64687e01f 1326 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
<> 147:30b64687e01f 1327 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
<> 147:30b64687e01f 1328 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
<> 147:30b64687e01f 1329 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
<> 147:30b64687e01f 1330 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
<> 147:30b64687e01f 1331 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
<> 147:30b64687e01f 1332 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
<> 147:30b64687e01f 1333 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
<> 147:30b64687e01f 1334 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
<> 147:30b64687e01f 1335 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
<> 147:30b64687e01f 1336 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
<> 147:30b64687e01f 1337 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
<> 147:30b64687e01f 1338 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
<> 147:30b64687e01f 1339 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
<> 147:30b64687e01f 1340 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
<> 147:30b64687e01f 1341 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
<> 147:30b64687e01f 1342 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
<> 147:30b64687e01f 1343 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
<> 147:30b64687e01f 1344 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
<> 147:30b64687e01f 1345 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
<> 147:30b64687e01f 1346 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
<> 147:30b64687e01f 1347 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
<> 147:30b64687e01f 1348 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
<> 147:30b64687e01f 1349 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
<> 147:30b64687e01f 1350 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
<> 147:30b64687e01f 1351 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
<> 147:30b64687e01f 1352 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
<> 147:30b64687e01f 1353 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
<> 147:30b64687e01f 1354 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
<> 147:30b64687e01f 1355 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
<> 147:30b64687e01f 1356 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
<> 147:30b64687e01f 1357 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
<> 147:30b64687e01f 1358 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
<> 147:30b64687e01f 1359 uint32_t RESERVED5; /*!< Reserved, 0x114 */
<> 147:30b64687e01f 1360 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
<> 147:30b64687e01f 1361 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
<> 147:30b64687e01f 1362 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
<> 147:30b64687e01f 1363 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
<> 147:30b64687e01f 1364 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
<> 147:30b64687e01f 1365 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
<> 147:30b64687e01f 1366 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
<> 147:30b64687e01f 1367 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
<> 147:30b64687e01f 1368 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
<> 147:30b64687e01f 1369 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
<> 147:30b64687e01f 1370 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
<> 147:30b64687e01f 1371 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
<> 147:30b64687e01f 1372 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
<> 147:30b64687e01f 1373 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
<> 147:30b64687e01f 1374 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
<> 147:30b64687e01f 1375 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
<> 147:30b64687e01f 1376 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
<> 147:30b64687e01f 1377 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
<> 147:30b64687e01f 1378 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
<> 147:30b64687e01f 1379 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
<> 147:30b64687e01f 1380 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
<> 147:30b64687e01f 1381 uint32_t RESERVED9; /*!< Reserved, 0x414 */
<> 147:30b64687e01f 1382 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
<> 147:30b64687e01f 1383 uint32_t RESERVED10; /*!< Reserved, 0x42C */
<> 147:30b64687e01f 1384 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
<> 147:30b64687e01f 1385 } DSI_TypeDef;
<> 147:30b64687e01f 1386
<> 147:30b64687e01f 1387 /** @addtogroup Peripheral_memory_map
<> 147:30b64687e01f 1388 * @{
<> 147:30b64687e01f 1389 */
<> 147:30b64687e01f 1390 #define RAMITCM_BASE 0x00000000U /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */
<> 147:30b64687e01f 1391 #define FLASHITCM_BASE 0x00200000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over ITCM */
<> 147:30b64687e01f 1392 #define FLASHAXI_BASE 0x08000000U /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
<> 147:30b64687e01f 1393 #define RAMDTCM_BASE 0x20000000U /*!< Base address of : 128KB system data RAM accessible over DTCM */
<> 147:30b64687e01f 1394 #define PERIPH_BASE 0x40000000U /*!< Base address of : AHB/ABP Peripherals */
<> 147:30b64687e01f 1395 #define BKPSRAM_BASE 0x40024000U /*!< Base address of : Backup SRAM(4 KB) */
<> 147:30b64687e01f 1396 #define QSPI_BASE 0x90000000U /*!< Base address of : QSPI memories accessible over AXI */
<> 147:30b64687e01f 1397 #define FMC_R_BASE 0xA0000000U /*!< Base address of : FMC Control registers */
<> 147:30b64687e01f 1398 #define QSPI_R_BASE 0xA0001000U /*!< Base address of : QSPI Control registers */
<> 147:30b64687e01f 1399 #define SRAM1_BASE 0x20020000U /*!< Base address of : 368KB RAM1 accessible over AXI/AHB */
<> 147:30b64687e01f 1400 #define SRAM2_BASE 0x2007C000U /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */
<> 147:30b64687e01f 1401 #define FLASH_END 0x081FFFFFU /*!< FLASH end address */
<> 147:30b64687e01f 1402
<> 147:30b64687e01f 1403 /* Legacy define */
<> 147:30b64687e01f 1404 #define FLASH_BASE FLASHAXI_BASE
<> 147:30b64687e01f 1405
<> 147:30b64687e01f 1406 /*!< Peripheral memory map */
<> 147:30b64687e01f 1407 #define APB1PERIPH_BASE PERIPH_BASE
<> 147:30b64687e01f 1408 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
<> 147:30b64687e01f 1409 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
<> 147:30b64687e01f 1410 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
<> 147:30b64687e01f 1411
<> 147:30b64687e01f 1412 /*!< APB1 peripherals */
<> 147:30b64687e01f 1413 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
<> 147:30b64687e01f 1414 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
<> 147:30b64687e01f 1415 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
<> 147:30b64687e01f 1416 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
<> 147:30b64687e01f 1417 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
<> 147:30b64687e01f 1418 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
<> 147:30b64687e01f 1419 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
<> 147:30b64687e01f 1420 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
<> 147:30b64687e01f 1421 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
<> 147:30b64687e01f 1422 #define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
<> 147:30b64687e01f 1423 #define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
<> 147:30b64687e01f 1424 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
<> 147:30b64687e01f 1425 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
<> 147:30b64687e01f 1426 #define CAN3_BASE (APB1PERIPH_BASE + 0x3400U)
<> 147:30b64687e01f 1427 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
<> 147:30b64687e01f 1428 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
<> 147:30b64687e01f 1429 #define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
<> 147:30b64687e01f 1430 #define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
<> 147:30b64687e01f 1431 #define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
<> 147:30b64687e01f 1432 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
<> 147:30b64687e01f 1433 #define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
<> 147:30b64687e01f 1434 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
<> 147:30b64687e01f 1435 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
<> 147:30b64687e01f 1436 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
<> 147:30b64687e01f 1437 #define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
<> 147:30b64687e01f 1438 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
<> 147:30b64687e01f 1439 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
<> 147:30b64687e01f 1440 #define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
<> 147:30b64687e01f 1441 #define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
<> 147:30b64687e01f 1442 #define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
<> 147:30b64687e01f 1443 #define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
<> 147:30b64687e01f 1444 #define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
<> 147:30b64687e01f 1445
<> 147:30b64687e01f 1446 /*!< APB2 peripherals */
<> 147:30b64687e01f 1447 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
<> 147:30b64687e01f 1448 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
<> 147:30b64687e01f 1449 #define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
<> 147:30b64687e01f 1450 #define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
<> 147:30b64687e01f 1451 #define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00U)
<> 147:30b64687e01f 1452 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
<> 147:30b64687e01f 1453 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
<> 147:30b64687e01f 1454 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
<> 147:30b64687e01f 1455 #define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
<> 147:30b64687e01f 1456 #define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
<> 147:30b64687e01f 1457 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
<> 147:30b64687e01f 1458 #define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
<> 147:30b64687e01f 1459 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
<> 147:30b64687e01f 1460 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
<> 147:30b64687e01f 1461 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
<> 147:30b64687e01f 1462 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
<> 147:30b64687e01f 1463 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
<> 147:30b64687e01f 1464 #define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
<> 147:30b64687e01f 1465 #define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
<> 147:30b64687e01f 1466 #define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
<> 147:30b64687e01f 1467 #define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
<> 147:30b64687e01f 1468 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
<> 147:30b64687e01f 1469 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
<> 147:30b64687e01f 1470 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
<> 147:30b64687e01f 1471 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
<> 147:30b64687e01f 1472 #define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
<> 147:30b64687e01f 1473 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
<> 147:30b64687e01f 1474 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
<> 147:30b64687e01f 1475 #define DSI_BASE (APB2PERIPH_BASE + 0x6C00U)
<> 147:30b64687e01f 1476 #define DFSDM1_BASE (APB2PERIPH_BASE + 0x7400U)
<> 147:30b64687e01f 1477 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00U)
<> 147:30b64687e01f 1478 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20U)
<> 147:30b64687e01f 1479 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40U)
<> 147:30b64687e01f 1480 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60U)
<> 147:30b64687e01f 1481 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80U)
<> 147:30b64687e01f 1482 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0U)
<> 147:30b64687e01f 1483 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0U)
<> 147:30b64687e01f 1484 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0U)
<> 147:30b64687e01f 1485 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100U)
<> 147:30b64687e01f 1486 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180U)
<> 147:30b64687e01f 1487 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200U)
<> 147:30b64687e01f 1488 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280U)
<> 147:30b64687e01f 1489 #define MDIOS_BASE (APB2PERIPH_BASE + 0x7800U)
<> 147:30b64687e01f 1490 /*!< AHB1 peripherals */
<> 147:30b64687e01f 1491 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
<> 147:30b64687e01f 1492 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
<> 147:30b64687e01f 1493 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
<> 147:30b64687e01f 1494 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
<> 147:30b64687e01f 1495 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
<> 147:30b64687e01f 1496 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
<> 147:30b64687e01f 1497 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
<> 147:30b64687e01f 1498 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
<> 147:30b64687e01f 1499 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
<> 147:30b64687e01f 1500 #define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
<> 147:30b64687e01f 1501 #define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
<> 147:30b64687e01f 1502 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
<> 147:30b64687e01f 1503 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
<> 147:30b64687e01f 1504 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
<> 147:30b64687e01f 1505 #define UID_BASE 0x1FF0F420U /*!< Unique device ID register base address */
<> 147:30b64687e01f 1506 #define FLASHSIZE_BASE 0x1FF0F442U /*!< FLASH Size register base address */
<> 147:30b64687e01f 1507 #define PACKAGESIZE_BASE 0x1FFF7BF0U /*!< Package size register base address */
<> 147:30b64687e01f 1508 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
<> 147:30b64687e01f 1509 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
<> 147:30b64687e01f 1510 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
<> 147:30b64687e01f 1511 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
<> 147:30b64687e01f 1512 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
<> 147:30b64687e01f 1513 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
<> 147:30b64687e01f 1514 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
<> 147:30b64687e01f 1515 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
<> 147:30b64687e01f 1516 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
<> 147:30b64687e01f 1517 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
<> 147:30b64687e01f 1518 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
<> 147:30b64687e01f 1519 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
<> 147:30b64687e01f 1520 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
<> 147:30b64687e01f 1521 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
<> 147:30b64687e01f 1522 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
<> 147:30b64687e01f 1523 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
<> 147:30b64687e01f 1524 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
<> 147:30b64687e01f 1525 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
<> 147:30b64687e01f 1526 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
<> 147:30b64687e01f 1527 #define ETH_MAC_BASE (ETH_BASE)
<> 147:30b64687e01f 1528 #define ETH_MMC_BASE (ETH_BASE + 0x0100U)
<> 147:30b64687e01f 1529 #define ETH_PTP_BASE (ETH_BASE + 0x0700U)
<> 147:30b64687e01f 1530 #define ETH_DMA_BASE (ETH_BASE + 0x1000U)
<> 147:30b64687e01f 1531 #define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
<> 147:30b64687e01f 1532 /*!< AHB2 peripherals */
<> 147:30b64687e01f 1533 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
<> 147:30b64687e01f 1534 #define JPEG_BASE (AHB2PERIPH_BASE + 0x51000U)
<> 147:30b64687e01f 1535 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
<> 147:30b64687e01f 1536 /*!< FMC Bankx registers base address */
<> 147:30b64687e01f 1537 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
<> 147:30b64687e01f 1538 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
<> 147:30b64687e01f 1539 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
<> 147:30b64687e01f 1540 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
<> 147:30b64687e01f 1541
<> 147:30b64687e01f 1542 /* Debug MCU registers base address */
<> 147:30b64687e01f 1543 #define DBGMCU_BASE 0xE0042000U
<> 147:30b64687e01f 1544
<> 147:30b64687e01f 1545 /*!< USB registers base address */
<> 147:30b64687e01f 1546 #define USB_OTG_HS_PERIPH_BASE 0x40040000U
<> 147:30b64687e01f 1547 #define USB_OTG_FS_PERIPH_BASE 0x50000000U
<> 147:30b64687e01f 1548
<> 147:30b64687e01f 1549 #define USB_OTG_GLOBAL_BASE 0x000U
<> 147:30b64687e01f 1550 #define USB_OTG_DEVICE_BASE 0x800U
<> 147:30b64687e01f 1551 #define USB_OTG_IN_ENDPOINT_BASE 0x900U
<> 147:30b64687e01f 1552 #define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
<> 147:30b64687e01f 1553 #define USB_OTG_EP_REG_SIZE 0x20U
<> 147:30b64687e01f 1554 #define USB_OTG_HOST_BASE 0x400U
<> 147:30b64687e01f 1555 #define USB_OTG_HOST_PORT_BASE 0x440U
<> 147:30b64687e01f 1556 #define USB_OTG_HOST_CHANNEL_BASE 0x500U
<> 147:30b64687e01f 1557 #define USB_OTG_HOST_CHANNEL_SIZE 0x20U
<> 147:30b64687e01f 1558 #define USB_OTG_PCGCCTL_BASE 0xE00U
<> 147:30b64687e01f 1559 #define USB_OTG_FIFO_BASE 0x1000U
<> 147:30b64687e01f 1560 #define USB_OTG_FIFO_SIZE 0x1000U
<> 147:30b64687e01f 1561
<> 147:30b64687e01f 1562 /**
<> 147:30b64687e01f 1563 * @}
<> 147:30b64687e01f 1564 */
<> 147:30b64687e01f 1565
<> 147:30b64687e01f 1566 /** @addtogroup Peripheral_declaration
<> 147:30b64687e01f 1567 * @{
<> 147:30b64687e01f 1568 */
<> 147:30b64687e01f 1569 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
<> 147:30b64687e01f 1570 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
<> 147:30b64687e01f 1571 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
<> 147:30b64687e01f 1572 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
<> 147:30b64687e01f 1573 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
<> 147:30b64687e01f 1574 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
<> 147:30b64687e01f 1575 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
<> 147:30b64687e01f 1576 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
<> 147:30b64687e01f 1577 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
<> 147:30b64687e01f 1578 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
<> 147:30b64687e01f 1579 #define RTC ((RTC_TypeDef *) RTC_BASE)
<> 147:30b64687e01f 1580 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
<> 147:30b64687e01f 1581 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
<> 147:30b64687e01f 1582 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
<> 147:30b64687e01f 1583 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
<> 157:ff67d9f36b67 1584 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
<> 147:30b64687e01f 1585 #define USART2 ((USART_TypeDef *) USART2_BASE)
<> 147:30b64687e01f 1586 #define USART3 ((USART_TypeDef *) USART3_BASE)
<> 147:30b64687e01f 1587 #define UART4 ((USART_TypeDef *) UART4_BASE)
<> 147:30b64687e01f 1588 #define UART5 ((USART_TypeDef *) UART5_BASE)
<> 147:30b64687e01f 1589 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
<> 147:30b64687e01f 1590 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
<> 147:30b64687e01f 1591 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
<> 147:30b64687e01f 1592 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
<> 147:30b64687e01f 1593 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
<> 147:30b64687e01f 1594 #define CAN2 ((CAN_TypeDef *) CAN2_BASE)
<> 147:30b64687e01f 1595 #define CEC ((CEC_TypeDef *) CEC_BASE)
<> 147:30b64687e01f 1596 #define PWR ((PWR_TypeDef *) PWR_BASE)
<> 147:30b64687e01f 1597 #define DAC ((DAC_TypeDef *) DAC_BASE)
<> 147:30b64687e01f 1598 #define UART7 ((USART_TypeDef *) UART7_BASE)
<> 147:30b64687e01f 1599 #define UART8 ((USART_TypeDef *) UART8_BASE)
<> 147:30b64687e01f 1600 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
<> 147:30b64687e01f 1601 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
<> 147:30b64687e01f 1602 #define USART1 ((USART_TypeDef *) USART1_BASE)
<> 147:30b64687e01f 1603 #define USART6 ((USART_TypeDef *) USART6_BASE)
<> 147:30b64687e01f 1604 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
<> 147:30b64687e01f 1605 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
<> 147:30b64687e01f 1606 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
<> 147:30b64687e01f 1607 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
<> 147:30b64687e01f 1608 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
<> 147:30b64687e01f 1609 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
<> 147:30b64687e01f 1610 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
<> 147:30b64687e01f 1611 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
<> 147:30b64687e01f 1612 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
<> 147:30b64687e01f 1613 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
<> 147:30b64687e01f 1614 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
<> 147:30b64687e01f 1615 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
<> 147:30b64687e01f 1616 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
<> 147:30b64687e01f 1617 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
<> 147:30b64687e01f 1618 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
<> 147:30b64687e01f 1619 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
<> 147:30b64687e01f 1620 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
<> 147:30b64687e01f 1621 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
<> 147:30b64687e01f 1622 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
<> 147:30b64687e01f 1623 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
<> 147:30b64687e01f 1624 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
<> 147:30b64687e01f 1625 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
<> 147:30b64687e01f 1626 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
<> 147:30b64687e01f 1627 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
<> 147:30b64687e01f 1628 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
<> 147:30b64687e01f 1629 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
<> 147:30b64687e01f 1630 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
<> 147:30b64687e01f 1631 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
<> 147:30b64687e01f 1632 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
<> 147:30b64687e01f 1633 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
<> 147:30b64687e01f 1634 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
<> 147:30b64687e01f 1635 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
<> 147:30b64687e01f 1636 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
<> 147:30b64687e01f 1637 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
<> 147:30b64687e01f 1638 #define CRC ((CRC_TypeDef *) CRC_BASE)
<> 147:30b64687e01f 1639 #define RCC ((RCC_TypeDef *) RCC_BASE)
<> 147:30b64687e01f 1640 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
<> 147:30b64687e01f 1641 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
<> 147:30b64687e01f 1642 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
<> 147:30b64687e01f 1643 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
<> 147:30b64687e01f 1644 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
<> 147:30b64687e01f 1645 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
<> 147:30b64687e01f 1646 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
<> 147:30b64687e01f 1647 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
<> 147:30b64687e01f 1648 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
<> 147:30b64687e01f 1649 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
<> 147:30b64687e01f 1650 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
<> 147:30b64687e01f 1651 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
<> 147:30b64687e01f 1652 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
<> 147:30b64687e01f 1653 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
<> 147:30b64687e01f 1654 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
<> 147:30b64687e01f 1655 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
<> 147:30b64687e01f 1656 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
<> 147:30b64687e01f 1657 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
<> 147:30b64687e01f 1658 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
<> 147:30b64687e01f 1659 #define ETH ((ETH_TypeDef *) ETH_BASE)
<> 147:30b64687e01f 1660 #define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
<> 147:30b64687e01f 1661 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
<> 147:30b64687e01f 1662 #define RNG ((RNG_TypeDef *) RNG_BASE)
<> 147:30b64687e01f 1663 #define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
<> 147:30b64687e01f 1664 #define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
<> 147:30b64687e01f 1665 #define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
<> 147:30b64687e01f 1666 #define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
<> 147:30b64687e01f 1667 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
<> 147:30b64687e01f 1668 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
<> 147:30b64687e01f 1669 #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
<> 147:30b64687e01f 1670 #define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
<> 147:30b64687e01f 1671 #define CAN3 ((CAN_TypeDef *) CAN3_BASE)
<> 147:30b64687e01f 1672 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
<> 147:30b64687e01f 1673 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
<> 147:30b64687e01f 1674 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
<> 147:30b64687e01f 1675 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
<> 147:30b64687e01f 1676 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
<> 147:30b64687e01f 1677 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
<> 147:30b64687e01f 1678 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
<> 147:30b64687e01f 1679 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
<> 147:30b64687e01f 1680 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
<> 147:30b64687e01f 1681 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
<> 147:30b64687e01f 1682 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
<> 147:30b64687e01f 1683 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
<> 147:30b64687e01f 1684 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
<> 147:30b64687e01f 1685 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
<> 147:30b64687e01f 1686 #define JPEG ((JPEG_TypeDef *) JPEG_BASE)
<> 147:30b64687e01f 1687 #define DSI ((DSI_TypeDef *)DSI_BASE)
<> 147:30b64687e01f 1688
<> 147:30b64687e01f 1689 /**
<> 147:30b64687e01f 1690 * @}
<> 147:30b64687e01f 1691 */
<> 147:30b64687e01f 1692
<> 147:30b64687e01f 1693 /** @addtogroup Exported_constants
<> 147:30b64687e01f 1694 * @{
<> 147:30b64687e01f 1695 */
<> 147:30b64687e01f 1696
<> 147:30b64687e01f 1697 /** @addtogroup Peripheral_Registers_Bits_Definition
<> 147:30b64687e01f 1698 * @{
<> 147:30b64687e01f 1699 */
<> 147:30b64687e01f 1700
<> 147:30b64687e01f 1701 /******************************************************************************/
<> 147:30b64687e01f 1702 /* Peripheral Registers_Bits_Definition */
<> 147:30b64687e01f 1703 /******************************************************************************/
<> 147:30b64687e01f 1704
<> 147:30b64687e01f 1705 /******************************************************************************/
<> 147:30b64687e01f 1706 /* */
<> 147:30b64687e01f 1707 /* Analog to Digital Converter */
<> 147:30b64687e01f 1708 /* */
<> 147:30b64687e01f 1709 /******************************************************************************/
<> 147:30b64687e01f 1710 /******************** Bit definition for ADC_SR register ********************/
<> 147:30b64687e01f 1711 #define ADC_SR_AWD 0x00000001U /*!<Analog watchdog flag */
<> 147:30b64687e01f 1712 #define ADC_SR_EOC 0x00000002U /*!<End of conversion */
<> 147:30b64687e01f 1713 #define ADC_SR_JEOC 0x00000004U /*!<Injected channel end of conversion */
<> 147:30b64687e01f 1714 #define ADC_SR_JSTRT 0x00000008U /*!<Injected channel Start flag */
<> 147:30b64687e01f 1715 #define ADC_SR_STRT 0x00000010U /*!<Regular channel Start flag */
<> 147:30b64687e01f 1716 #define ADC_SR_OVR 0x00000020U /*!<Overrun flag */
<> 147:30b64687e01f 1717
<> 147:30b64687e01f 1718 /******************* Bit definition for ADC_CR1 register ********************/
<> 147:30b64687e01f 1719 #define ADC_CR1_AWDCH 0x0000001FU /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
<> 147:30b64687e01f 1720 #define ADC_CR1_AWDCH_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1721 #define ADC_CR1_AWDCH_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1722 #define ADC_CR1_AWDCH_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1723 #define ADC_CR1_AWDCH_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 1724 #define ADC_CR1_AWDCH_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 1725 #define ADC_CR1_EOCIE 0x00000020U /*!<Interrupt enable for EOC */
<> 147:30b64687e01f 1726 #define ADC_CR1_AWDIE 0x00000040U /*!<AAnalog Watchdog interrupt enable */
<> 147:30b64687e01f 1727 #define ADC_CR1_JEOCIE 0x00000080U /*!<Interrupt enable for injected channels */
<> 147:30b64687e01f 1728 #define ADC_CR1_SCAN 0x00000100U /*!<Scan mode */
<> 147:30b64687e01f 1729 #define ADC_CR1_AWDSGL 0x00000200U /*!<Enable the watchdog on a single channel in scan mode */
<> 147:30b64687e01f 1730 #define ADC_CR1_JAUTO 0x00000400U /*!<Automatic injected group conversion */
<> 147:30b64687e01f 1731 #define ADC_CR1_DISCEN 0x00000800U /*!<Discontinuous mode on regular channels */
<> 147:30b64687e01f 1732 #define ADC_CR1_JDISCEN 0x00001000U /*!<Discontinuous mode on injected channels */
<> 147:30b64687e01f 1733 #define ADC_CR1_DISCNUM 0x0000E000U /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
<> 147:30b64687e01f 1734 #define ADC_CR1_DISCNUM_0 0x00002000U /*!<Bit 0 */
<> 147:30b64687e01f 1735 #define ADC_CR1_DISCNUM_1 0x00004000U /*!<Bit 1 */
<> 147:30b64687e01f 1736 #define ADC_CR1_DISCNUM_2 0x00008000U /*!<Bit 2 */
<> 147:30b64687e01f 1737 #define ADC_CR1_JAWDEN 0x00400000U /*!<Analog watchdog enable on injected channels */
<> 147:30b64687e01f 1738 #define ADC_CR1_AWDEN 0x00800000U /*!<Analog watchdog enable on regular channels */
<> 147:30b64687e01f 1739 #define ADC_CR1_RES 0x03000000U /*!<RES[2:0] bits (Resolution) */
<> 147:30b64687e01f 1740 #define ADC_CR1_RES_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 1741 #define ADC_CR1_RES_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 1742 #define ADC_CR1_OVRIE 0x04000000U /*!<overrun interrupt enable */
<> 147:30b64687e01f 1743
<> 147:30b64687e01f 1744 /******************* Bit definition for ADC_CR2 register ********************/
<> 147:30b64687e01f 1745 #define ADC_CR2_ADON 0x00000001U /*!<A/D Converter ON / OFF */
<> 147:30b64687e01f 1746 #define ADC_CR2_CONT 0x00000002U /*!<Continuous Conversion */
<> 147:30b64687e01f 1747 #define ADC_CR2_DMA 0x00000100U /*!<Direct Memory access mode */
<> 147:30b64687e01f 1748 #define ADC_CR2_DDS 0x00000200U /*!<DMA disable selection (Single ADC) */
<> 147:30b64687e01f 1749 #define ADC_CR2_EOCS 0x00000400U /*!<End of conversion selection */
<> 147:30b64687e01f 1750 #define ADC_CR2_ALIGN 0x00000800U /*!<Data Alignment */
<> 147:30b64687e01f 1751 #define ADC_CR2_JEXTSEL 0x000F0000U /*!<JEXTSEL[3:0] bits (External event select for injected group) */
<> 147:30b64687e01f 1752 #define ADC_CR2_JEXTSEL_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 1753 #define ADC_CR2_JEXTSEL_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 1754 #define ADC_CR2_JEXTSEL_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 1755 #define ADC_CR2_JEXTSEL_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 1756 #define ADC_CR2_JEXTEN 0x00300000U /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
<> 147:30b64687e01f 1757 #define ADC_CR2_JEXTEN_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 1758 #define ADC_CR2_JEXTEN_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 1759 #define ADC_CR2_JSWSTART 0x00400000U /*!<Start Conversion of injected channels */
<> 147:30b64687e01f 1760 #define ADC_CR2_EXTSEL 0x0F000000U /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
<> 147:30b64687e01f 1761 #define ADC_CR2_EXTSEL_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 1762 #define ADC_CR2_EXTSEL_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 1763 #define ADC_CR2_EXTSEL_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 1764 #define ADC_CR2_EXTSEL_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 1765 #define ADC_CR2_EXTEN 0x30000000U /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
<> 147:30b64687e01f 1766 #define ADC_CR2_EXTEN_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 1767 #define ADC_CR2_EXTEN_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 1768 #define ADC_CR2_SWSTART 0x40000000U /*!<Start Conversion of regular channels */
<> 147:30b64687e01f 1769
<> 147:30b64687e01f 1770 /****************** Bit definition for ADC_SMPR1 register *******************/
<> 147:30b64687e01f 1771 #define ADC_SMPR1_SMP10 0x00000007U /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
<> 147:30b64687e01f 1772 #define ADC_SMPR1_SMP10_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1773 #define ADC_SMPR1_SMP10_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1774 #define ADC_SMPR1_SMP10_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1775 #define ADC_SMPR1_SMP11 0x00000038U /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
<> 147:30b64687e01f 1776 #define ADC_SMPR1_SMP11_0 0x00000008U /*!<Bit 0 */
<> 147:30b64687e01f 1777 #define ADC_SMPR1_SMP11_1 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 1778 #define ADC_SMPR1_SMP11_2 0x00000020U /*!<Bit 2 */
<> 147:30b64687e01f 1779 #define ADC_SMPR1_SMP12 0x000001C0U /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
<> 147:30b64687e01f 1780 #define ADC_SMPR1_SMP12_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 1781 #define ADC_SMPR1_SMP12_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 1782 #define ADC_SMPR1_SMP12_2 0x00000100U /*!<Bit 2 */
<> 147:30b64687e01f 1783 #define ADC_SMPR1_SMP13 0x00000E00U /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
<> 147:30b64687e01f 1784 #define ADC_SMPR1_SMP13_0 0x00000200U /*!<Bit 0 */
<> 147:30b64687e01f 1785 #define ADC_SMPR1_SMP13_1 0x00000400U /*!<Bit 1 */
<> 147:30b64687e01f 1786 #define ADC_SMPR1_SMP13_2 0x00000800U /*!<Bit 2 */
<> 147:30b64687e01f 1787 #define ADC_SMPR1_SMP14 0x00007000U /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
<> 147:30b64687e01f 1788 #define ADC_SMPR1_SMP14_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 1789 #define ADC_SMPR1_SMP14_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 1790 #define ADC_SMPR1_SMP14_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 1791 #define ADC_SMPR1_SMP15 0x00038000U /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
<> 147:30b64687e01f 1792 #define ADC_SMPR1_SMP15_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1793 #define ADC_SMPR1_SMP15_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1794 #define ADC_SMPR1_SMP15_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1795 #define ADC_SMPR1_SMP16 0x001C0000U /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
<> 147:30b64687e01f 1796 #define ADC_SMPR1_SMP16_0 0x00040000U /*!<Bit 0 */
<> 147:30b64687e01f 1797 #define ADC_SMPR1_SMP16_1 0x00080000U /*!<Bit 1 */
<> 147:30b64687e01f 1798 #define ADC_SMPR1_SMP16_2 0x00100000U /*!<Bit 2 */
<> 147:30b64687e01f 1799 #define ADC_SMPR1_SMP17 0x00E00000U /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
<> 147:30b64687e01f 1800 #define ADC_SMPR1_SMP17_0 0x00200000U /*!<Bit 0 */
<> 147:30b64687e01f 1801 #define ADC_SMPR1_SMP17_1 0x00400000U /*!<Bit 1 */
<> 147:30b64687e01f 1802 #define ADC_SMPR1_SMP17_2 0x00800000U /*!<Bit 2 */
<> 147:30b64687e01f 1803 #define ADC_SMPR1_SMP18 0x07000000U /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
<> 147:30b64687e01f 1804 #define ADC_SMPR1_SMP18_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 1805 #define ADC_SMPR1_SMP18_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 1806 #define ADC_SMPR1_SMP18_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 1807
<> 147:30b64687e01f 1808 /****************** Bit definition for ADC_SMPR2 register *******************/
<> 147:30b64687e01f 1809 #define ADC_SMPR2_SMP0 0x00000007U /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
<> 147:30b64687e01f 1810 #define ADC_SMPR2_SMP0_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1811 #define ADC_SMPR2_SMP0_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1812 #define ADC_SMPR2_SMP0_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1813 #define ADC_SMPR2_SMP1 0x00000038U /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
<> 147:30b64687e01f 1814 #define ADC_SMPR2_SMP1_0 0x00000008U /*!<Bit 0 */
<> 147:30b64687e01f 1815 #define ADC_SMPR2_SMP1_1 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 1816 #define ADC_SMPR2_SMP1_2 0x00000020U /*!<Bit 2 */
<> 147:30b64687e01f 1817 #define ADC_SMPR2_SMP2 0x000001C0U /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
<> 147:30b64687e01f 1818 #define ADC_SMPR2_SMP2_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 1819 #define ADC_SMPR2_SMP2_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 1820 #define ADC_SMPR2_SMP2_2 0x00000100U /*!<Bit 2 */
<> 147:30b64687e01f 1821 #define ADC_SMPR2_SMP3 0x00000E00U /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
<> 147:30b64687e01f 1822 #define ADC_SMPR2_SMP3_0 0x00000200U /*!<Bit 0 */
<> 147:30b64687e01f 1823 #define ADC_SMPR2_SMP3_1 0x00000400U /*!<Bit 1 */
<> 147:30b64687e01f 1824 #define ADC_SMPR2_SMP3_2 0x00000800U /*!<Bit 2 */
<> 147:30b64687e01f 1825 #define ADC_SMPR2_SMP4 0x00007000U /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
<> 147:30b64687e01f 1826 #define ADC_SMPR2_SMP4_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 1827 #define ADC_SMPR2_SMP4_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 1828 #define ADC_SMPR2_SMP4_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 1829 #define ADC_SMPR2_SMP5 0x00038000U /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
<> 147:30b64687e01f 1830 #define ADC_SMPR2_SMP5_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1831 #define ADC_SMPR2_SMP5_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1832 #define ADC_SMPR2_SMP5_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1833 #define ADC_SMPR2_SMP6 0x001C0000U /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
<> 147:30b64687e01f 1834 #define ADC_SMPR2_SMP6_0 0x00040000U /*!<Bit 0 */
<> 147:30b64687e01f 1835 #define ADC_SMPR2_SMP6_1 0x00080000U /*!<Bit 1 */
<> 147:30b64687e01f 1836 #define ADC_SMPR2_SMP6_2 0x00100000U /*!<Bit 2 */
<> 147:30b64687e01f 1837 #define ADC_SMPR2_SMP7 0x00E00000U /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
<> 147:30b64687e01f 1838 #define ADC_SMPR2_SMP7_0 0x00200000U /*!<Bit 0 */
<> 147:30b64687e01f 1839 #define ADC_SMPR2_SMP7_1 0x00400000U /*!<Bit 1 */
<> 147:30b64687e01f 1840 #define ADC_SMPR2_SMP7_2 0x00800000U /*!<Bit 2 */
<> 147:30b64687e01f 1841 #define ADC_SMPR2_SMP8 0x07000000U /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
<> 147:30b64687e01f 1842 #define ADC_SMPR2_SMP8_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 1843 #define ADC_SMPR2_SMP8_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 1844 #define ADC_SMPR2_SMP8_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 1845 #define ADC_SMPR2_SMP9 0x38000000U /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
<> 147:30b64687e01f 1846 #define ADC_SMPR2_SMP9_0 0x08000000U /*!<Bit 0 */
<> 147:30b64687e01f 1847 #define ADC_SMPR2_SMP9_1 0x10000000U /*!<Bit 1 */
<> 147:30b64687e01f 1848 #define ADC_SMPR2_SMP9_2 0x20000000U /*!<Bit 2 */
<> 147:30b64687e01f 1849
<> 147:30b64687e01f 1850 /****************** Bit definition for ADC_JOFR1 register *******************/
<> 147:30b64687e01f 1851 #define ADC_JOFR1_JOFFSET1 0x0FFFU /*!<Data offset for injected channel 1 */
<> 147:30b64687e01f 1852
<> 147:30b64687e01f 1853 /****************** Bit definition for ADC_JOFR2 register *******************/
<> 147:30b64687e01f 1854 #define ADC_JOFR2_JOFFSET2 0x0FFFU /*!<Data offset for injected channel 2 */
<> 147:30b64687e01f 1855
<> 147:30b64687e01f 1856 /****************** Bit definition for ADC_JOFR3 register *******************/
<> 147:30b64687e01f 1857 #define ADC_JOFR3_JOFFSET3 0x0FFFU /*!<Data offset for injected channel 3 */
<> 147:30b64687e01f 1858
<> 147:30b64687e01f 1859 /****************** Bit definition for ADC_JOFR4 register *******************/
<> 147:30b64687e01f 1860 #define ADC_JOFR4_JOFFSET4 0x0FFFU /*!<Data offset for injected channel 4 */
<> 147:30b64687e01f 1861
<> 147:30b64687e01f 1862 /******************* Bit definition for ADC_HTR register ********************/
<> 147:30b64687e01f 1863 #define ADC_HTR_HT 0x0FFFU /*!<Analog watchdog high threshold */
<> 147:30b64687e01f 1864
<> 147:30b64687e01f 1865 /******************* Bit definition for ADC_LTR register ********************/
<> 147:30b64687e01f 1866 #define ADC_LTR_LT 0x0FFFU /*!<Analog watchdog low threshold */
<> 147:30b64687e01f 1867
<> 147:30b64687e01f 1868 /******************* Bit definition for ADC_SQR1 register *******************/
<> 147:30b64687e01f 1869 #define ADC_SQR1_SQ13 0x0000001FU /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
<> 147:30b64687e01f 1870 #define ADC_SQR1_SQ13_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1871 #define ADC_SQR1_SQ13_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1872 #define ADC_SQR1_SQ13_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1873 #define ADC_SQR1_SQ13_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 1874 #define ADC_SQR1_SQ13_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 1875 #define ADC_SQR1_SQ14 0x000003E0U /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
<> 147:30b64687e01f 1876 #define ADC_SQR1_SQ14_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 1877 #define ADC_SQR1_SQ14_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 1878 #define ADC_SQR1_SQ14_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 1879 #define ADC_SQR1_SQ14_3 0x00000100U /*!<Bit 3 */
<> 147:30b64687e01f 1880 #define ADC_SQR1_SQ14_4 0x00000200U /*!<Bit 4 */
<> 147:30b64687e01f 1881 #define ADC_SQR1_SQ15 0x00007C00U /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
<> 147:30b64687e01f 1882 #define ADC_SQR1_SQ15_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 1883 #define ADC_SQR1_SQ15_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 1884 #define ADC_SQR1_SQ15_2 0x00001000U /*!<Bit 2 */
<> 147:30b64687e01f 1885 #define ADC_SQR1_SQ15_3 0x00002000U /*!<Bit 3 */
<> 147:30b64687e01f 1886 #define ADC_SQR1_SQ15_4 0x00004000U /*!<Bit 4 */
<> 147:30b64687e01f 1887 #define ADC_SQR1_SQ16 0x000F8000U /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
<> 147:30b64687e01f 1888 #define ADC_SQR1_SQ16_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1889 #define ADC_SQR1_SQ16_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1890 #define ADC_SQR1_SQ16_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1891 #define ADC_SQR1_SQ16_3 0x00040000U /*!<Bit 3 */
<> 147:30b64687e01f 1892 #define ADC_SQR1_SQ16_4 0x00080000U /*!<Bit 4 */
<> 147:30b64687e01f 1893 #define ADC_SQR1_L 0x00F00000U /*!<L[3:0] bits (Regular channel sequence length) */
<> 147:30b64687e01f 1894 #define ADC_SQR1_L_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 1895 #define ADC_SQR1_L_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 1896 #define ADC_SQR1_L_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 1897 #define ADC_SQR1_L_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 1898
<> 147:30b64687e01f 1899 /******************* Bit definition for ADC_SQR2 register *******************/
<> 147:30b64687e01f 1900 #define ADC_SQR2_SQ7 0x0000001FU /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
<> 147:30b64687e01f 1901 #define ADC_SQR2_SQ7_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1902 #define ADC_SQR2_SQ7_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1903 #define ADC_SQR2_SQ7_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1904 #define ADC_SQR2_SQ7_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 1905 #define ADC_SQR2_SQ7_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 1906 #define ADC_SQR2_SQ8 0x000003E0U /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
<> 147:30b64687e01f 1907 #define ADC_SQR2_SQ8_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 1908 #define ADC_SQR2_SQ8_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 1909 #define ADC_SQR2_SQ8_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 1910 #define ADC_SQR2_SQ8_3 0x00000100U /*!<Bit 3 */
<> 147:30b64687e01f 1911 #define ADC_SQR2_SQ8_4 0x00000200U /*!<Bit 4 */
<> 147:30b64687e01f 1912 #define ADC_SQR2_SQ9 0x00007C00U /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
<> 147:30b64687e01f 1913 #define ADC_SQR2_SQ9_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 1914 #define ADC_SQR2_SQ9_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 1915 #define ADC_SQR2_SQ9_2 0x00001000U /*!<Bit 2 */
<> 147:30b64687e01f 1916 #define ADC_SQR2_SQ9_3 0x00002000U /*!<Bit 3 */
<> 147:30b64687e01f 1917 #define ADC_SQR2_SQ9_4 0x00004000U /*!<Bit 4 */
<> 147:30b64687e01f 1918 #define ADC_SQR2_SQ10 0x000F8000U /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
<> 147:30b64687e01f 1919 #define ADC_SQR2_SQ10_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1920 #define ADC_SQR2_SQ10_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1921 #define ADC_SQR2_SQ10_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1922 #define ADC_SQR2_SQ10_3 0x00040000U /*!<Bit 3 */
<> 147:30b64687e01f 1923 #define ADC_SQR2_SQ10_4 0x00080000U /*!<Bit 4 */
<> 147:30b64687e01f 1924 #define ADC_SQR2_SQ11 0x01F00000U /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
<> 147:30b64687e01f 1925 #define ADC_SQR2_SQ11_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 1926 #define ADC_SQR2_SQ11_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 1927 #define ADC_SQR2_SQ11_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 1928 #define ADC_SQR2_SQ11_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 1929 #define ADC_SQR2_SQ11_4 0x01000000U /*!<Bit 4 */
<> 147:30b64687e01f 1930 #define ADC_SQR2_SQ12 0x3E000000U /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
<> 147:30b64687e01f 1931 #define ADC_SQR2_SQ12_0 0x02000000U /*!<Bit 0 */
<> 147:30b64687e01f 1932 #define ADC_SQR2_SQ12_1 0x04000000U /*!<Bit 1 */
<> 147:30b64687e01f 1933 #define ADC_SQR2_SQ12_2 0x08000000U /*!<Bit 2 */
<> 147:30b64687e01f 1934 #define ADC_SQR2_SQ12_3 0x10000000U /*!<Bit 3 */
<> 147:30b64687e01f 1935 #define ADC_SQR2_SQ12_4 0x20000000U /*!<Bit 4 */
<> 147:30b64687e01f 1936
<> 147:30b64687e01f 1937 /******************* Bit definition for ADC_SQR3 register *******************/
<> 147:30b64687e01f 1938 #define ADC_SQR3_SQ1 0x0000001FU /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
<> 147:30b64687e01f 1939 #define ADC_SQR3_SQ1_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1940 #define ADC_SQR3_SQ1_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1941 #define ADC_SQR3_SQ1_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1942 #define ADC_SQR3_SQ1_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 1943 #define ADC_SQR3_SQ1_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 1944 #define ADC_SQR3_SQ2 0x000003E0U /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
<> 147:30b64687e01f 1945 #define ADC_SQR3_SQ2_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 1946 #define ADC_SQR3_SQ2_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 1947 #define ADC_SQR3_SQ2_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 1948 #define ADC_SQR3_SQ2_3 0x00000100U /*!<Bit 3 */
<> 147:30b64687e01f 1949 #define ADC_SQR3_SQ2_4 0x00000200U /*!<Bit 4 */
<> 147:30b64687e01f 1950 #define ADC_SQR3_SQ3 0x00007C00U /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
<> 147:30b64687e01f 1951 #define ADC_SQR3_SQ3_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 1952 #define ADC_SQR3_SQ3_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 1953 #define ADC_SQR3_SQ3_2 0x00001000U /*!<Bit 2 */
<> 147:30b64687e01f 1954 #define ADC_SQR3_SQ3_3 0x00002000U /*!<Bit 3 */
<> 147:30b64687e01f 1955 #define ADC_SQR3_SQ3_4 0x00004000U /*!<Bit 4 */
<> 147:30b64687e01f 1956 #define ADC_SQR3_SQ4 0x000F8000U /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
<> 147:30b64687e01f 1957 #define ADC_SQR3_SQ4_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1958 #define ADC_SQR3_SQ4_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1959 #define ADC_SQR3_SQ4_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1960 #define ADC_SQR3_SQ4_3 0x00040000U /*!<Bit 3 */
<> 147:30b64687e01f 1961 #define ADC_SQR3_SQ4_4 0x00080000U /*!<Bit 4 */
<> 147:30b64687e01f 1962 #define ADC_SQR3_SQ5 0x01F00000U /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
<> 147:30b64687e01f 1963 #define ADC_SQR3_SQ5_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 1964 #define ADC_SQR3_SQ5_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 1965 #define ADC_SQR3_SQ5_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 1966 #define ADC_SQR3_SQ5_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 1967 #define ADC_SQR3_SQ5_4 0x01000000U /*!<Bit 4 */
<> 147:30b64687e01f 1968 #define ADC_SQR3_SQ6 0x3E000000U /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
<> 147:30b64687e01f 1969 #define ADC_SQR3_SQ6_0 0x02000000U /*!<Bit 0 */
<> 147:30b64687e01f 1970 #define ADC_SQR3_SQ6_1 0x04000000U /*!<Bit 1 */
<> 147:30b64687e01f 1971 #define ADC_SQR3_SQ6_2 0x08000000U /*!<Bit 2 */
<> 147:30b64687e01f 1972 #define ADC_SQR3_SQ6_3 0x10000000U /*!<Bit 3 */
<> 147:30b64687e01f 1973 #define ADC_SQR3_SQ6_4 0x20000000U /*!<Bit 4 */
<> 147:30b64687e01f 1974
<> 147:30b64687e01f 1975 /******************* Bit definition for ADC_JSQR register *******************/
<> 147:30b64687e01f 1976 #define ADC_JSQR_JSQ1 0x0000001FU /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
<> 147:30b64687e01f 1977 #define ADC_JSQR_JSQ1_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 1978 #define ADC_JSQR_JSQ1_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 1979 #define ADC_JSQR_JSQ1_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 1980 #define ADC_JSQR_JSQ1_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 1981 #define ADC_JSQR_JSQ1_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 1982 #define ADC_JSQR_JSQ2 0x000003E0U /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
<> 147:30b64687e01f 1983 #define ADC_JSQR_JSQ2_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 1984 #define ADC_JSQR_JSQ2_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 1985 #define ADC_JSQR_JSQ2_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 1986 #define ADC_JSQR_JSQ2_3 0x00000100U /*!<Bit 3 */
<> 147:30b64687e01f 1987 #define ADC_JSQR_JSQ2_4 0x00000200U /*!<Bit 4 */
<> 147:30b64687e01f 1988 #define ADC_JSQR_JSQ3 0x00007C00U /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
<> 147:30b64687e01f 1989 #define ADC_JSQR_JSQ3_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 1990 #define ADC_JSQR_JSQ3_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 1991 #define ADC_JSQR_JSQ3_2 0x00001000U /*!<Bit 2 */
<> 147:30b64687e01f 1992 #define ADC_JSQR_JSQ3_3 0x00002000U /*!<Bit 3 */
<> 147:30b64687e01f 1993 #define ADC_JSQR_JSQ3_4 0x00004000U /*!<Bit 4 */
<> 147:30b64687e01f 1994 #define ADC_JSQR_JSQ4 0x000F8000U /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
<> 147:30b64687e01f 1995 #define ADC_JSQR_JSQ4_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 1996 #define ADC_JSQR_JSQ4_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 1997 #define ADC_JSQR_JSQ4_2 0x00020000U /*!<Bit 2 */
<> 147:30b64687e01f 1998 #define ADC_JSQR_JSQ4_3 0x00040000U /*!<Bit 3 */
<> 147:30b64687e01f 1999 #define ADC_JSQR_JSQ4_4 0x00080000U /*!<Bit 4 */
<> 147:30b64687e01f 2000 #define ADC_JSQR_JL 0x00300000U /*!<JL[1:0] bits (Injected Sequence length) */
<> 147:30b64687e01f 2001 #define ADC_JSQR_JL_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 2002 #define ADC_JSQR_JL_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 2003
<> 147:30b64687e01f 2004 /******************* Bit definition for ADC_JDR1 register *******************/
<> 147:30b64687e01f 2005 #define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 147:30b64687e01f 2006
<> 147:30b64687e01f 2007 /******************* Bit definition for ADC_JDR2 register *******************/
<> 147:30b64687e01f 2008 #define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 147:30b64687e01f 2009
<> 147:30b64687e01f 2010 /******************* Bit definition for ADC_JDR3 register *******************/
<> 147:30b64687e01f 2011 #define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 147:30b64687e01f 2012
<> 147:30b64687e01f 2013 /******************* Bit definition for ADC_JDR4 register *******************/
<> 147:30b64687e01f 2014 #define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */
<> 147:30b64687e01f 2015
<> 147:30b64687e01f 2016 /******************** Bit definition for ADC_DR register ********************/
<> 147:30b64687e01f 2017 #define ADC_DR_DATA 0x0000FFFFU /*!<Regular data */
<> 147:30b64687e01f 2018 #define ADC_DR_ADC2DATA 0xFFFF0000U /*!<ADC2 data */
<> 147:30b64687e01f 2019
<> 147:30b64687e01f 2020 /******************* Bit definition for ADC_CSR register ********************/
<> 147:30b64687e01f 2021 #define ADC_CSR_AWD1 0x00000001U /*!<ADC1 Analog watchdog flag */
<> 147:30b64687e01f 2022 #define ADC_CSR_EOC1 0x00000002U /*!<ADC1 End of conversion */
<> 147:30b64687e01f 2023 #define ADC_CSR_JEOC1 0x00000004U /*!<ADC1 Injected channel end of conversion */
<> 147:30b64687e01f 2024 #define ADC_CSR_JSTRT1 0x00000008U /*!<ADC1 Injected channel Start flag */
<> 147:30b64687e01f 2025 #define ADC_CSR_STRT1 0x00000010U /*!<ADC1 Regular channel Start flag */
<> 147:30b64687e01f 2026 #define ADC_CSR_OVR1 0x00000020U /*!<ADC1 Overrun flag */
<> 147:30b64687e01f 2027 #define ADC_CSR_AWD2 0x00000100U /*!<ADC2 Analog watchdog flag */
<> 147:30b64687e01f 2028 #define ADC_CSR_EOC2 0x00000200U /*!<ADC2 End of conversion */
<> 147:30b64687e01f 2029 #define ADC_CSR_JEOC2 0x00000400U /*!<ADC2 Injected channel end of conversion */
<> 147:30b64687e01f 2030 #define ADC_CSR_JSTRT2 0x00000800U /*!<ADC2 Injected channel Start flag */
<> 147:30b64687e01f 2031 #define ADC_CSR_STRT2 0x00001000U /*!<ADC2 Regular channel Start flag */
<> 147:30b64687e01f 2032 #define ADC_CSR_OVR2 0x00002000U /*!<ADC2 Overrun flag */
<> 147:30b64687e01f 2033 #define ADC_CSR_AWD3 0x00010000U /*!<ADC3 Analog watchdog flag */
<> 147:30b64687e01f 2034 #define ADC_CSR_EOC3 0x00020000U /*!<ADC3 End of conversion */
<> 147:30b64687e01f 2035 #define ADC_CSR_JEOC3 0x00040000U /*!<ADC3 Injected channel end of conversion */
<> 147:30b64687e01f 2036 #define ADC_CSR_JSTRT3 0x00080000U /*!<ADC3 Injected channel Start flag */
<> 147:30b64687e01f 2037 #define ADC_CSR_STRT3 0x00100000U /*!<ADC3 Regular channel Start flag */
<> 147:30b64687e01f 2038 #define ADC_CSR_OVR3 0x00200000U /*!<ADC3 Overrun flag */
<> 147:30b64687e01f 2039
<> 147:30b64687e01f 2040 /* Legacy defines */
<> 147:30b64687e01f 2041 #define ADC_CSR_DOVR1 ADC_CSR_OVR1
<> 147:30b64687e01f 2042 #define ADC_CSR_DOVR2 ADC_CSR_OVR2
<> 147:30b64687e01f 2043 #define ADC_CSR_DOVR3 ADC_CSR_OVR3
<> 147:30b64687e01f 2044
<> 147:30b64687e01f 2045
<> 147:30b64687e01f 2046 /******************* Bit definition for ADC_CCR register ********************/
<> 147:30b64687e01f 2047 #define ADC_CCR_MULTI 0x0000001FU /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
<> 147:30b64687e01f 2048 #define ADC_CCR_MULTI_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 2049 #define ADC_CCR_MULTI_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 2050 #define ADC_CCR_MULTI_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 2051 #define ADC_CCR_MULTI_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 2052 #define ADC_CCR_MULTI_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 2053 #define ADC_CCR_DELAY 0x00000F00U /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
<> 147:30b64687e01f 2054 #define ADC_CCR_DELAY_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 2055 #define ADC_CCR_DELAY_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 2056 #define ADC_CCR_DELAY_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 2057 #define ADC_CCR_DELAY_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 2058 #define ADC_CCR_DDS 0x00002000U /*!<DMA disable selection (Multi-ADC mode) */
<> 147:30b64687e01f 2059 #define ADC_CCR_DMA 0x0000C000U /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
<> 147:30b64687e01f 2060 #define ADC_CCR_DMA_0 0x00004000U /*!<Bit 0 */
<> 147:30b64687e01f 2061 #define ADC_CCR_DMA_1 0x00008000U /*!<Bit 1 */
<> 147:30b64687e01f 2062 #define ADC_CCR_ADCPRE 0x00030000U /*!<ADCPRE[1:0] bits (ADC prescaler) */
<> 147:30b64687e01f 2063 #define ADC_CCR_ADCPRE_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 2064 #define ADC_CCR_ADCPRE_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 2065 #define ADC_CCR_VBATE 0x00400000U /*!<VBAT Enable */
<> 147:30b64687e01f 2066 #define ADC_CCR_TSVREFE 0x00800000U /*!<Temperature Sensor and VREFINT Enable */
<> 147:30b64687e01f 2067
<> 147:30b64687e01f 2068 /******************* Bit definition for ADC_CDR register ********************/
<> 147:30b64687e01f 2069 #define ADC_CDR_DATA1 0x0000FFFFU /*!<1st data of a pair of regular conversions */
<> 147:30b64687e01f 2070 #define ADC_CDR_DATA2 0xFFFF0000U /*!<2nd data of a pair of regular conversions */
<> 147:30b64687e01f 2071
<> 147:30b64687e01f 2072 /******************************************************************************/
<> 147:30b64687e01f 2073 /* */
<> 147:30b64687e01f 2074 /* Controller Area Network */
<> 147:30b64687e01f 2075 /* */
<> 147:30b64687e01f 2076 /******************************************************************************/
<> 147:30b64687e01f 2077 /*!<CAN control and status registers */
<> 147:30b64687e01f 2078 /******************* Bit definition for CAN_MCR register ********************/
<> 147:30b64687e01f 2079 #define CAN_MCR_INRQ 0x00000001U /*!<Initialization Request */
<> 147:30b64687e01f 2080 #define CAN_MCR_SLEEP 0x00000002U /*!<Sleep Mode Request */
<> 147:30b64687e01f 2081 #define CAN_MCR_TXFP 0x00000004U /*!<Transmit FIFO Priority */
<> 147:30b64687e01f 2082 #define CAN_MCR_RFLM 0x00000008U /*!<Receive FIFO Locked Mode */
<> 147:30b64687e01f 2083 #define CAN_MCR_NART 0x00000010U /*!<No Automatic Retransmission */
<> 147:30b64687e01f 2084 #define CAN_MCR_AWUM 0x00000020U /*!<Automatic Wakeup Mode */
<> 147:30b64687e01f 2085 #define CAN_MCR_ABOM 0x00000040U /*!<Automatic Bus-Off Management */
<> 147:30b64687e01f 2086 #define CAN_MCR_TTCM 0x00000080U /*!<Time Triggered Communication Mode */
<> 147:30b64687e01f 2087 #define CAN_MCR_RESET 0x00008000U /*!<bxCAN software master reset */
<> 147:30b64687e01f 2088
<> 147:30b64687e01f 2089 /******************* Bit definition for CAN_MSR register ********************/
<> 147:30b64687e01f 2090 #define CAN_MSR_INAK 0x00000001U /*!<Initialization Acknowledge */
<> 147:30b64687e01f 2091 #define CAN_MSR_SLAK 0x00000002U /*!<Sleep Acknowledge */
<> 147:30b64687e01f 2092 #define CAN_MSR_ERRI 0x00000004U /*!<Error Interrupt */
<> 147:30b64687e01f 2093 #define CAN_MSR_WKUI 0x00000008U /*!<Wakeup Interrupt */
<> 147:30b64687e01f 2094 #define CAN_MSR_SLAKI 0x00000010U /*!<Sleep Acknowledge Interrupt */
<> 147:30b64687e01f 2095 #define CAN_MSR_TXM 0x00000100U /*!<Transmit Mode */
<> 147:30b64687e01f 2096 #define CAN_MSR_RXM 0x00000200U /*!<Receive Mode */
<> 147:30b64687e01f 2097 #define CAN_MSR_SAMP 0x00000400U /*!<Last Sample Point */
<> 147:30b64687e01f 2098 #define CAN_MSR_RX 0x00000800U /*!<CAN Rx Signal */
<> 147:30b64687e01f 2099
<> 147:30b64687e01f 2100 /******************* Bit definition for CAN_TSR register ********************/
<> 147:30b64687e01f 2101 #define CAN_TSR_RQCP0 0x00000001U /*!<Request Completed Mailbox0 */
<> 147:30b64687e01f 2102 #define CAN_TSR_TXOK0 0x00000002U /*!<Transmission OK of Mailbox0 */
<> 147:30b64687e01f 2103 #define CAN_TSR_ALST0 0x00000004U /*!<Arbitration Lost for Mailbox0 */
<> 147:30b64687e01f 2104 #define CAN_TSR_TERR0 0x00000008U /*!<Transmission Error of Mailbox0 */
<> 147:30b64687e01f 2105 #define CAN_TSR_ABRQ0 0x00000080U /*!<Abort Request for Mailbox0 */
<> 147:30b64687e01f 2106 #define CAN_TSR_RQCP1 0x00000100U /*!<Request Completed Mailbox1 */
<> 147:30b64687e01f 2107 #define CAN_TSR_TXOK1 0x00000200U /*!<Transmission OK of Mailbox1 */
<> 147:30b64687e01f 2108 #define CAN_TSR_ALST1 0x00000400U /*!<Arbitration Lost for Mailbox1 */
<> 147:30b64687e01f 2109 #define CAN_TSR_TERR1 0x00000800U /*!<Transmission Error of Mailbox1 */
<> 147:30b64687e01f 2110 #define CAN_TSR_ABRQ1 0x00008000U /*!<Abort Request for Mailbox 1 */
<> 147:30b64687e01f 2111 #define CAN_TSR_RQCP2 0x00010000U /*!<Request Completed Mailbox2 */
<> 147:30b64687e01f 2112 #define CAN_TSR_TXOK2 0x00020000U /*!<Transmission OK of Mailbox 2 */
<> 147:30b64687e01f 2113 #define CAN_TSR_ALST2 0x00040000U /*!<Arbitration Lost for mailbox 2 */
<> 147:30b64687e01f 2114 #define CAN_TSR_TERR2 0x00080000U /*!<Transmission Error of Mailbox 2 */
<> 147:30b64687e01f 2115 #define CAN_TSR_ABRQ2 0x00800000U /*!<Abort Request for Mailbox 2 */
<> 147:30b64687e01f 2116 #define CAN_TSR_CODE 0x03000000U /*!<Mailbox Code */
<> 147:30b64687e01f 2117
<> 147:30b64687e01f 2118 #define CAN_TSR_TME 0x1C000000U /*!<TME[2:0] bits */
<> 147:30b64687e01f 2119 #define CAN_TSR_TME0 0x04000000U /*!<Transmit Mailbox 0 Empty */
<> 147:30b64687e01f 2120 #define CAN_TSR_TME1 0x08000000U /*!<Transmit Mailbox 1 Empty */
<> 147:30b64687e01f 2121 #define CAN_TSR_TME2 0x10000000U /*!<Transmit Mailbox 2 Empty */
<> 147:30b64687e01f 2122
<> 147:30b64687e01f 2123 #define CAN_TSR_LOW 0xE0000000U /*!<LOW[2:0] bits */
<> 147:30b64687e01f 2124 #define CAN_TSR_LOW0 0x20000000U /*!<Lowest Priority Flag for Mailbox 0 */
<> 147:30b64687e01f 2125 #define CAN_TSR_LOW1 0x40000000U /*!<Lowest Priority Flag for Mailbox 1 */
<> 147:30b64687e01f 2126 #define CAN_TSR_LOW2 0x80000000U /*!<Lowest Priority Flag for Mailbox 2 */
<> 147:30b64687e01f 2127
<> 147:30b64687e01f 2128 /******************* Bit definition for CAN_RF0R register *******************/
<> 147:30b64687e01f 2129 #define CAN_RF0R_FMP0 0x00000003U /*!<FIFO 0 Message Pending */
<> 147:30b64687e01f 2130 #define CAN_RF0R_FULL0 0x00000008U /*!<FIFO 0 Full */
<> 147:30b64687e01f 2131 #define CAN_RF0R_FOVR0 0x00000010U /*!<FIFO 0 Overrun */
<> 147:30b64687e01f 2132 #define CAN_RF0R_RFOM0 0x00000020U /*!<Release FIFO 0 Output Mailbox */
<> 147:30b64687e01f 2133
<> 147:30b64687e01f 2134 /******************* Bit definition for CAN_RF1R register *******************/
<> 147:30b64687e01f 2135 #define CAN_RF1R_FMP1 0x00000003U /*!<FIFO 1 Message Pending */
<> 147:30b64687e01f 2136 #define CAN_RF1R_FULL1 0x00000008U /*!<FIFO 1 Full */
<> 147:30b64687e01f 2137 #define CAN_RF1R_FOVR1 0x00000010U /*!<FIFO 1 Overrun */
<> 147:30b64687e01f 2138 #define CAN_RF1R_RFOM1 0x00000020U /*!<Release FIFO 1 Output Mailbox */
<> 147:30b64687e01f 2139
<> 147:30b64687e01f 2140 /******************** Bit definition for CAN_IER register *******************/
<> 147:30b64687e01f 2141 #define CAN_IER_TMEIE 0x00000001U /*!<Transmit Mailbox Empty Interrupt Enable */
<> 147:30b64687e01f 2142 #define CAN_IER_FMPIE0 0x00000002U /*!<FIFO Message Pending Interrupt Enable */
<> 147:30b64687e01f 2143 #define CAN_IER_FFIE0 0x00000004U /*!<FIFO Full Interrupt Enable */
<> 147:30b64687e01f 2144 #define CAN_IER_FOVIE0 0x00000008U /*!<FIFO Overrun Interrupt Enable */
<> 147:30b64687e01f 2145 #define CAN_IER_FMPIE1 0x00000010U /*!<FIFO Message Pending Interrupt Enable */
<> 147:30b64687e01f 2146 #define CAN_IER_FFIE1 0x00000020U /*!<FIFO Full Interrupt Enable */
<> 147:30b64687e01f 2147 #define CAN_IER_FOVIE1 0x00000040U /*!<FIFO Overrun Interrupt Enable */
<> 147:30b64687e01f 2148 #define CAN_IER_EWGIE 0x00000100U /*!<Error Warning Interrupt Enable */
<> 147:30b64687e01f 2149 #define CAN_IER_EPVIE 0x00000200U /*!<Error Passive Interrupt Enable */
<> 147:30b64687e01f 2150 #define CAN_IER_BOFIE 0x00000400U /*!<Bus-Off Interrupt Enable */
<> 147:30b64687e01f 2151 #define CAN_IER_LECIE 0x00000800U /*!<Last Error Code Interrupt Enable */
<> 147:30b64687e01f 2152 #define CAN_IER_ERRIE 0x00008000U /*!<Error Interrupt Enable */
<> 147:30b64687e01f 2153 #define CAN_IER_WKUIE 0x00010000U /*!<Wakeup Interrupt Enable */
<> 147:30b64687e01f 2154 #define CAN_IER_SLKIE 0x00020000U /*!<Sleep Interrupt Enable */
<> 147:30b64687e01f 2155
<> 147:30b64687e01f 2156 /******************** Bit definition for CAN_ESR register *******************/
<> 147:30b64687e01f 2157 #define CAN_ESR_EWGF 0x00000001U /*!<Error Warning Flag */
<> 147:30b64687e01f 2158 #define CAN_ESR_EPVF 0x00000002U /*!<Error Passive Flag */
<> 147:30b64687e01f 2159 #define CAN_ESR_BOFF 0x00000004U /*!<Bus-Off Flag */
<> 147:30b64687e01f 2160
<> 147:30b64687e01f 2161 #define CAN_ESR_LEC 0x00000070U /*!<LEC[2:0] bits (Last Error Code) */
<> 147:30b64687e01f 2162 #define CAN_ESR_LEC_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 2163 #define CAN_ESR_LEC_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 2164 #define CAN_ESR_LEC_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 2165
<> 147:30b64687e01f 2166 #define CAN_ESR_TEC 0x00FF0000U /*!<Least significant byte of the 9-bit Transmit Error Counter */
<> 147:30b64687e01f 2167 #define CAN_ESR_REC 0xFF000000U /*!<Receive Error Counter */
<> 147:30b64687e01f 2168
<> 147:30b64687e01f 2169 /******************* Bit definition for CAN_BTR register ********************/
<> 147:30b64687e01f 2170 #define CAN_BTR_BRP 0x000003FFU /*!<Baud Rate Prescaler */
<> 147:30b64687e01f 2171 #define CAN_BTR_TS1 0x000F0000U /*!<Time Segment 1 */
<> 147:30b64687e01f 2172 #define CAN_BTR_TS1_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 2173 #define CAN_BTR_TS1_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 2174 #define CAN_BTR_TS1_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 2175 #define CAN_BTR_TS1_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 2176 #define CAN_BTR_TS2 0x00700000U /*!<Time Segment 2 */
<> 147:30b64687e01f 2177 #define CAN_BTR_TS2_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 2178 #define CAN_BTR_TS2_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 2179 #define CAN_BTR_TS2_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 2180 #define CAN_BTR_SJW 0x03000000U /*!<Resynchronization Jump Width */
<> 147:30b64687e01f 2181 #define CAN_BTR_SJW_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 2182 #define CAN_BTR_SJW_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 2183 #define CAN_BTR_LBKM 0x40000000U /*!<Loop Back Mode (Debug) */
<> 147:30b64687e01f 2184 #define CAN_BTR_SILM 0x80000000U /*!<Silent Mode */
<> 147:30b64687e01f 2185
<> 147:30b64687e01f 2186 /*!<Mailbox registers */
<> 147:30b64687e01f 2187 /****************** Bit definition for CAN_TI0R register ********************/
<> 147:30b64687e01f 2188 #define CAN_TI0R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 2189 #define CAN_TI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 147:30b64687e01f 2190 #define CAN_TI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 147:30b64687e01f 2191 #define CAN_TI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 147:30b64687e01f 2192 #define CAN_TI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 2193
<> 147:30b64687e01f 2194 /****************** Bit definition for CAN_TDT0R register *******************/
<> 147:30b64687e01f 2195 #define CAN_TDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 147:30b64687e01f 2196 #define CAN_TDT0R_TGT 0x00000100U /*!<Transmit Global Time */
<> 147:30b64687e01f 2197 #define CAN_TDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 147:30b64687e01f 2198
<> 147:30b64687e01f 2199 /****************** Bit definition for CAN_TDL0R register *******************/
<> 147:30b64687e01f 2200 #define CAN_TDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 147:30b64687e01f 2201 #define CAN_TDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 147:30b64687e01f 2202 #define CAN_TDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 147:30b64687e01f 2203 #define CAN_TDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 147:30b64687e01f 2204
<> 147:30b64687e01f 2205 /****************** Bit definition for CAN_TDH0R register *******************/
<> 147:30b64687e01f 2206 #define CAN_TDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 147:30b64687e01f 2207 #define CAN_TDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 147:30b64687e01f 2208 #define CAN_TDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 147:30b64687e01f 2209 #define CAN_TDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 147:30b64687e01f 2210
<> 147:30b64687e01f 2211 /******************* Bit definition for CAN_TI1R register *******************/
<> 147:30b64687e01f 2212 #define CAN_TI1R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 2213 #define CAN_TI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 147:30b64687e01f 2214 #define CAN_TI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 147:30b64687e01f 2215 #define CAN_TI1R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 147:30b64687e01f 2216 #define CAN_TI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 2217
<> 147:30b64687e01f 2218 /******************* Bit definition for CAN_TDT1R register ******************/
<> 147:30b64687e01f 2219 #define CAN_TDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 147:30b64687e01f 2220 #define CAN_TDT1R_TGT 0x00000100U /*!<Transmit Global Time */
<> 147:30b64687e01f 2221 #define CAN_TDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 147:30b64687e01f 2222
<> 147:30b64687e01f 2223 /******************* Bit definition for CAN_TDL1R register ******************/
<> 147:30b64687e01f 2224 #define CAN_TDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 147:30b64687e01f 2225 #define CAN_TDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 147:30b64687e01f 2226 #define CAN_TDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 147:30b64687e01f 2227 #define CAN_TDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 147:30b64687e01f 2228
<> 147:30b64687e01f 2229 /******************* Bit definition for CAN_TDH1R register ******************/
<> 147:30b64687e01f 2230 #define CAN_TDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 147:30b64687e01f 2231 #define CAN_TDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 147:30b64687e01f 2232 #define CAN_TDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 147:30b64687e01f 2233 #define CAN_TDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 147:30b64687e01f 2234
<> 147:30b64687e01f 2235 /******************* Bit definition for CAN_TI2R register *******************/
<> 147:30b64687e01f 2236 #define CAN_TI2R_TXRQ 0x00000001U /*!<Transmit Mailbox Request */
<> 147:30b64687e01f 2237 #define CAN_TI2R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 147:30b64687e01f 2238 #define CAN_TI2R_IDE 0x00000004U /*!<Identifier Extension */
<> 147:30b64687e01f 2239 #define CAN_TI2R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 147:30b64687e01f 2240 #define CAN_TI2R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 2241
<> 147:30b64687e01f 2242 /******************* Bit definition for CAN_TDT2R register ******************/
<> 147:30b64687e01f 2243 #define CAN_TDT2R_DLC 0x0000000FU /*!<Data Length Code */
<> 147:30b64687e01f 2244 #define CAN_TDT2R_TGT 0x00000100U /*!<Transmit Global Time */
<> 147:30b64687e01f 2245 #define CAN_TDT2R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 147:30b64687e01f 2246
<> 147:30b64687e01f 2247 /******************* Bit definition for CAN_TDL2R register ******************/
<> 147:30b64687e01f 2248 #define CAN_TDL2R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 147:30b64687e01f 2249 #define CAN_TDL2R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 147:30b64687e01f 2250 #define CAN_TDL2R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 147:30b64687e01f 2251 #define CAN_TDL2R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 147:30b64687e01f 2252
<> 147:30b64687e01f 2253 /******************* Bit definition for CAN_TDH2R register ******************/
<> 147:30b64687e01f 2254 #define CAN_TDH2R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 147:30b64687e01f 2255 #define CAN_TDH2R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 147:30b64687e01f 2256 #define CAN_TDH2R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 147:30b64687e01f 2257 #define CAN_TDH2R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 147:30b64687e01f 2258
<> 147:30b64687e01f 2259 /******************* Bit definition for CAN_RI0R register *******************/
<> 147:30b64687e01f 2260 #define CAN_RI0R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 147:30b64687e01f 2261 #define CAN_RI0R_IDE 0x00000004U /*!<Identifier Extension */
<> 147:30b64687e01f 2262 #define CAN_RI0R_EXID 0x001FFFF8U /*!<Extended Identifier */
<> 147:30b64687e01f 2263 #define CAN_RI0R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 2264
<> 147:30b64687e01f 2265 /******************* Bit definition for CAN_RDT0R register ******************/
<> 147:30b64687e01f 2266 #define CAN_RDT0R_DLC 0x0000000FU /*!<Data Length Code */
<> 147:30b64687e01f 2267 #define CAN_RDT0R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 147:30b64687e01f 2268 #define CAN_RDT0R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 147:30b64687e01f 2269
<> 147:30b64687e01f 2270 /******************* Bit definition for CAN_RDL0R register ******************/
<> 147:30b64687e01f 2271 #define CAN_RDL0R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 147:30b64687e01f 2272 #define CAN_RDL0R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 147:30b64687e01f 2273 #define CAN_RDL0R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 147:30b64687e01f 2274 #define CAN_RDL0R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 147:30b64687e01f 2275
<> 147:30b64687e01f 2276 /******************* Bit definition for CAN_RDH0R register ******************/
<> 147:30b64687e01f 2277 #define CAN_RDH0R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 147:30b64687e01f 2278 #define CAN_RDH0R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 147:30b64687e01f 2279 #define CAN_RDH0R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 147:30b64687e01f 2280 #define CAN_RDH0R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 147:30b64687e01f 2281
<> 147:30b64687e01f 2282 /******************* Bit definition for CAN_RI1R register *******************/
<> 147:30b64687e01f 2283 #define CAN_RI1R_RTR 0x00000002U /*!<Remote Transmission Request */
<> 147:30b64687e01f 2284 #define CAN_RI1R_IDE 0x00000004U /*!<Identifier Extension */
<> 147:30b64687e01f 2285 #define CAN_RI1R_EXID 0x001FFFF8U /*!<Extended identifier */
<> 147:30b64687e01f 2286 #define CAN_RI1R_STID 0xFFE00000U /*!<Standard Identifier or Extended Identifier */
<> 147:30b64687e01f 2287
<> 147:30b64687e01f 2288 /******************* Bit definition for CAN_RDT1R register ******************/
<> 147:30b64687e01f 2289 #define CAN_RDT1R_DLC 0x0000000FU /*!<Data Length Code */
<> 147:30b64687e01f 2290 #define CAN_RDT1R_FMI 0x0000FF00U /*!<Filter Match Index */
<> 147:30b64687e01f 2291 #define CAN_RDT1R_TIME 0xFFFF0000U /*!<Message Time Stamp */
<> 147:30b64687e01f 2292
<> 147:30b64687e01f 2293 /******************* Bit definition for CAN_RDL1R register ******************/
<> 147:30b64687e01f 2294 #define CAN_RDL1R_DATA0 0x000000FFU /*!<Data byte 0 */
<> 147:30b64687e01f 2295 #define CAN_RDL1R_DATA1 0x0000FF00U /*!<Data byte 1 */
<> 147:30b64687e01f 2296 #define CAN_RDL1R_DATA2 0x00FF0000U /*!<Data byte 2 */
<> 147:30b64687e01f 2297 #define CAN_RDL1R_DATA3 0xFF000000U /*!<Data byte 3 */
<> 147:30b64687e01f 2298
<> 147:30b64687e01f 2299 /******************* Bit definition for CAN_RDH1R register ******************/
<> 147:30b64687e01f 2300 #define CAN_RDH1R_DATA4 0x000000FFU /*!<Data byte 4 */
<> 147:30b64687e01f 2301 #define CAN_RDH1R_DATA5 0x0000FF00U /*!<Data byte 5 */
<> 147:30b64687e01f 2302 #define CAN_RDH1R_DATA6 0x00FF0000U /*!<Data byte 6 */
<> 147:30b64687e01f 2303 #define CAN_RDH1R_DATA7 0xFF000000U /*!<Data byte 7 */
<> 147:30b64687e01f 2304
<> 147:30b64687e01f 2305 /*!<CAN filter registers */
<> 147:30b64687e01f 2306 /******************* Bit definition for CAN_FMR register ********************/
<> 147:30b64687e01f 2307 #define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */
<> 147:30b64687e01f 2308 #define CAN_FMR_CAN2SB 0x00003F00U /*!<CAN2 start bank */
<> 147:30b64687e01f 2309
<> 147:30b64687e01f 2310 /******************* Bit definition for CAN_FM1R register *******************/
<> 147:30b64687e01f 2311 #define CAN_FM1R_FBM 0x3FFFU /*!<Filter Mode */
<> 147:30b64687e01f 2312 #define CAN_FM1R_FBM0 0x0001U /*!<Filter Init Mode bit 0 */
<> 147:30b64687e01f 2313 #define CAN_FM1R_FBM1 0x0002U /*!<Filter Init Mode bit 1 */
<> 147:30b64687e01f 2314 #define CAN_FM1R_FBM2 0x0004U /*!<Filter Init Mode bit 2 */
<> 147:30b64687e01f 2315 #define CAN_FM1R_FBM3 0x0008U /*!<Filter Init Mode bit 3 */
<> 147:30b64687e01f 2316 #define CAN_FM1R_FBM4 0x0010U /*!<Filter Init Mode bit 4 */
<> 147:30b64687e01f 2317 #define CAN_FM1R_FBM5 0x0020U /*!<Filter Init Mode bit 5 */
<> 147:30b64687e01f 2318 #define CAN_FM1R_FBM6 0x0040U /*!<Filter Init Mode bit 6 */
<> 147:30b64687e01f 2319 #define CAN_FM1R_FBM7 0x0080U /*!<Filter Init Mode bit 7 */
<> 147:30b64687e01f 2320 #define CAN_FM1R_FBM8 0x0100U /*!<Filter Init Mode bit 8 */
<> 147:30b64687e01f 2321 #define CAN_FM1R_FBM9 0x0200U /*!<Filter Init Mode bit 9 */
<> 147:30b64687e01f 2322 #define CAN_FM1R_FBM10 0x0400U /*!<Filter Init Mode bit 10 */
<> 147:30b64687e01f 2323 #define CAN_FM1R_FBM11 0x0800U /*!<Filter Init Mode bit 11 */
<> 147:30b64687e01f 2324 #define CAN_FM1R_FBM12 0x1000U /*!<Filter Init Mode bit 12 */
<> 147:30b64687e01f 2325 #define CAN_FM1R_FBM13 0x2000U /*!<Filter Init Mode bit 13 */
<> 147:30b64687e01f 2326
<> 147:30b64687e01f 2327 /******************* Bit definition for CAN_FS1R register *******************/
<> 147:30b64687e01f 2328 #define CAN_FS1R_FSC 0x00003FFFU /*!<Filter Scale Configuration */
<> 147:30b64687e01f 2329 #define CAN_FS1R_FSC0 0x00000001U /*!<Filter Scale Configuration bit 0 */
<> 147:30b64687e01f 2330 #define CAN_FS1R_FSC1 0x00000002U /*!<Filter Scale Configuration bit 1 */
<> 147:30b64687e01f 2331 #define CAN_FS1R_FSC2 0x00000004U /*!<Filter Scale Configuration bit 2 */
<> 147:30b64687e01f 2332 #define CAN_FS1R_FSC3 0x00000008U /*!<Filter Scale Configuration bit 3 */
<> 147:30b64687e01f 2333 #define CAN_FS1R_FSC4 0x00000010U /*!<Filter Scale Configuration bit 4 */
<> 147:30b64687e01f 2334 #define CAN_FS1R_FSC5 0x00000020U /*!<Filter Scale Configuration bit 5 */
<> 147:30b64687e01f 2335 #define CAN_FS1R_FSC6 0x00000040U /*!<Filter Scale Configuration bit 6 */
<> 147:30b64687e01f 2336 #define CAN_FS1R_FSC7 0x00000080U /*!<Filter Scale Configuration bit 7 */
<> 147:30b64687e01f 2337 #define CAN_FS1R_FSC8 0x00000100U /*!<Filter Scale Configuration bit 8 */
<> 147:30b64687e01f 2338 #define CAN_FS1R_FSC9 0x00000200U /*!<Filter Scale Configuration bit 9 */
<> 147:30b64687e01f 2339 #define CAN_FS1R_FSC10 0x00000400U /*!<Filter Scale Configuration bit 10 */
<> 147:30b64687e01f 2340 #define CAN_FS1R_FSC11 0x00000800U /*!<Filter Scale Configuration bit 11 */
<> 147:30b64687e01f 2341 #define CAN_FS1R_FSC12 0x00001000U /*!<Filter Scale Configuration bit 12 */
<> 147:30b64687e01f 2342 #define CAN_FS1R_FSC13 0x00002000U /*!<Filter Scale Configuration bit 13 */
<> 147:30b64687e01f 2343
<> 147:30b64687e01f 2344 /****************** Bit definition for CAN_FFA1R register *******************/
<> 147:30b64687e01f 2345 #define CAN_FFA1R_FFA 0x00003FFFU /*!<Filter FIFO Assignment */
<> 147:30b64687e01f 2346 #define CAN_FFA1R_FFA0 0x00000001U /*!<Filter FIFO Assignment for Filter 0 */
<> 147:30b64687e01f 2347 #define CAN_FFA1R_FFA1 0x00000002U /*!<Filter FIFO Assignment for Filter 1 */
<> 147:30b64687e01f 2348 #define CAN_FFA1R_FFA2 0x00000004U /*!<Filter FIFO Assignment for Filter 2 */
<> 147:30b64687e01f 2349 #define CAN_FFA1R_FFA3 0x00000008U /*!<Filter FIFO Assignment for Filter 3 */
<> 147:30b64687e01f 2350 #define CAN_FFA1R_FFA4 0x00000010U /*!<Filter FIFO Assignment for Filter 4 */
<> 147:30b64687e01f 2351 #define CAN_FFA1R_FFA5 0x00000020U /*!<Filter FIFO Assignment for Filter 5 */
<> 147:30b64687e01f 2352 #define CAN_FFA1R_FFA6 0x00000040U /*!<Filter FIFO Assignment for Filter 6 */
<> 147:30b64687e01f 2353 #define CAN_FFA1R_FFA7 0x00000080U /*!<Filter FIFO Assignment for Filter 7 */
<> 147:30b64687e01f 2354 #define CAN_FFA1R_FFA8 0x00000100U /*!<Filter FIFO Assignment for Filter 8 */
<> 147:30b64687e01f 2355 #define CAN_FFA1R_FFA9 0x00000200U /*!<Filter FIFO Assignment for Filter 9 */
<> 147:30b64687e01f 2356 #define CAN_FFA1R_FFA10 0x00000400U /*!<Filter FIFO Assignment for Filter 10 */
<> 147:30b64687e01f 2357 #define CAN_FFA1R_FFA11 0x00000800U /*!<Filter FIFO Assignment for Filter 11 */
<> 147:30b64687e01f 2358 #define CAN_FFA1R_FFA12 0x00001000U /*!<Filter FIFO Assignment for Filter 12 */
<> 147:30b64687e01f 2359 #define CAN_FFA1R_FFA13 0x00002000U /*!<Filter FIFO Assignment for Filter 13 */
<> 147:30b64687e01f 2360
<> 147:30b64687e01f 2361 /******************* Bit definition for CAN_FA1R register *******************/
<> 147:30b64687e01f 2362 #define CAN_FA1R_FACT 0x00003FFFU /*!<Filter Active */
<> 147:30b64687e01f 2363 #define CAN_FA1R_FACT0 0x00000001U /*!<Filter 0 Active */
<> 147:30b64687e01f 2364 #define CAN_FA1R_FACT1 0x00000002U /*!<Filter 1 Active */
<> 147:30b64687e01f 2365 #define CAN_FA1R_FACT2 0x00000004U /*!<Filter 2 Active */
<> 147:30b64687e01f 2366 #define CAN_FA1R_FACT3 0x00000008U /*!<Filter 3 Active */
<> 147:30b64687e01f 2367 #define CAN_FA1R_FACT4 0x00000010U /*!<Filter 4 Active */
<> 147:30b64687e01f 2368 #define CAN_FA1R_FACT5 0x00000020U /*!<Filter 5 Active */
<> 147:30b64687e01f 2369 #define CAN_FA1R_FACT6 0x00000040U /*!<Filter 6 Active */
<> 147:30b64687e01f 2370 #define CAN_FA1R_FACT7 0x00000080U /*!<Filter 7 Active */
<> 147:30b64687e01f 2371 #define CAN_FA1R_FACT8 0x00000100U /*!<Filter 8 Active */
<> 147:30b64687e01f 2372 #define CAN_FA1R_FACT9 0x00000200U /*!<Filter 9 Active */
<> 147:30b64687e01f 2373 #define CAN_FA1R_FACT10 0x00000400U /*!<Filter 10 Active */
<> 147:30b64687e01f 2374 #define CAN_FA1R_FACT11 0x00000800U /*!<Filter 11 Active */
<> 147:30b64687e01f 2375 #define CAN_FA1R_FACT12 0x00001000U /*!<Filter 12 Active */
<> 147:30b64687e01f 2376 #define CAN_FA1R_FACT13 0x00002000U /*!<Filter 13 Active */
<> 147:30b64687e01f 2377
<> 147:30b64687e01f 2378 /******************* Bit definition for CAN_F0R1 register *******************/
<> 147:30b64687e01f 2379 #define CAN_F0R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2380 #define CAN_F0R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2381 #define CAN_F0R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2382 #define CAN_F0R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2383 #define CAN_F0R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2384 #define CAN_F0R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2385 #define CAN_F0R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2386 #define CAN_F0R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2387 #define CAN_F0R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2388 #define CAN_F0R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2389 #define CAN_F0R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2390 #define CAN_F0R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2391 #define CAN_F0R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2392 #define CAN_F0R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2393 #define CAN_F0R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2394 #define CAN_F0R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2395 #define CAN_F0R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2396 #define CAN_F0R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2397 #define CAN_F0R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2398 #define CAN_F0R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2399 #define CAN_F0R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2400 #define CAN_F0R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2401 #define CAN_F0R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2402 #define CAN_F0R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2403 #define CAN_F0R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2404 #define CAN_F0R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2405 #define CAN_F0R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2406 #define CAN_F0R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2407 #define CAN_F0R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2408 #define CAN_F0R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2409 #define CAN_F0R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2410 #define CAN_F0R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2411
<> 147:30b64687e01f 2412 /******************* Bit definition for CAN_F1R1 register *******************/
<> 147:30b64687e01f 2413 #define CAN_F1R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2414 #define CAN_F1R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2415 #define CAN_F1R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2416 #define CAN_F1R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2417 #define CAN_F1R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2418 #define CAN_F1R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2419 #define CAN_F1R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2420 #define CAN_F1R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2421 #define CAN_F1R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2422 #define CAN_F1R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2423 #define CAN_F1R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2424 #define CAN_F1R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2425 #define CAN_F1R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2426 #define CAN_F1R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2427 #define CAN_F1R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2428 #define CAN_F1R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2429 #define CAN_F1R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2430 #define CAN_F1R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2431 #define CAN_F1R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2432 #define CAN_F1R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2433 #define CAN_F1R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2434 #define CAN_F1R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2435 #define CAN_F1R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2436 #define CAN_F1R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2437 #define CAN_F1R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2438 #define CAN_F1R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2439 #define CAN_F1R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2440 #define CAN_F1R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2441 #define CAN_F1R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2442 #define CAN_F1R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2443 #define CAN_F1R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2444 #define CAN_F1R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2445
<> 147:30b64687e01f 2446 /******************* Bit definition for CAN_F2R1 register *******************/
<> 147:30b64687e01f 2447 #define CAN_F2R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2448 #define CAN_F2R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2449 #define CAN_F2R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2450 #define CAN_F2R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2451 #define CAN_F2R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2452 #define CAN_F2R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2453 #define CAN_F2R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2454 #define CAN_F2R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2455 #define CAN_F2R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2456 #define CAN_F2R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2457 #define CAN_F2R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2458 #define CAN_F2R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2459 #define CAN_F2R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2460 #define CAN_F2R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2461 #define CAN_F2R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2462 #define CAN_F2R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2463 #define CAN_F2R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2464 #define CAN_F2R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2465 #define CAN_F2R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2466 #define CAN_F2R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2467 #define CAN_F2R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2468 #define CAN_F2R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2469 #define CAN_F2R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2470 #define CAN_F2R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2471 #define CAN_F2R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2472 #define CAN_F2R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2473 #define CAN_F2R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2474 #define CAN_F2R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2475 #define CAN_F2R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2476 #define CAN_F2R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2477 #define CAN_F2R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2478 #define CAN_F2R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2479
<> 147:30b64687e01f 2480 /******************* Bit definition for CAN_F3R1 register *******************/
<> 147:30b64687e01f 2481 #define CAN_F3R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2482 #define CAN_F3R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2483 #define CAN_F3R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2484 #define CAN_F3R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2485 #define CAN_F3R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2486 #define CAN_F3R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2487 #define CAN_F3R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2488 #define CAN_F3R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2489 #define CAN_F3R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2490 #define CAN_F3R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2491 #define CAN_F3R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2492 #define CAN_F3R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2493 #define CAN_F3R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2494 #define CAN_F3R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2495 #define CAN_F3R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2496 #define CAN_F3R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2497 #define CAN_F3R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2498 #define CAN_F3R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2499 #define CAN_F3R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2500 #define CAN_F3R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2501 #define CAN_F3R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2502 #define CAN_F3R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2503 #define CAN_F3R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2504 #define CAN_F3R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2505 #define CAN_F3R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2506 #define CAN_F3R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2507 #define CAN_F3R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2508 #define CAN_F3R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2509 #define CAN_F3R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2510 #define CAN_F3R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2511 #define CAN_F3R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2512 #define CAN_F3R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2513
<> 147:30b64687e01f 2514 /******************* Bit definition for CAN_F4R1 register *******************/
<> 147:30b64687e01f 2515 #define CAN_F4R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2516 #define CAN_F4R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2517 #define CAN_F4R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2518 #define CAN_F4R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2519 #define CAN_F4R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2520 #define CAN_F4R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2521 #define CAN_F4R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2522 #define CAN_F4R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2523 #define CAN_F4R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2524 #define CAN_F4R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2525 #define CAN_F4R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2526 #define CAN_F4R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2527 #define CAN_F4R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2528 #define CAN_F4R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2529 #define CAN_F4R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2530 #define CAN_F4R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2531 #define CAN_F4R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2532 #define CAN_F4R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2533 #define CAN_F4R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2534 #define CAN_F4R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2535 #define CAN_F4R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2536 #define CAN_F4R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2537 #define CAN_F4R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2538 #define CAN_F4R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2539 #define CAN_F4R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2540 #define CAN_F4R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2541 #define CAN_F4R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2542 #define CAN_F4R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2543 #define CAN_F4R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2544 #define CAN_F4R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2545 #define CAN_F4R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2546 #define CAN_F4R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2547
<> 147:30b64687e01f 2548 /******************* Bit definition for CAN_F5R1 register *******************/
<> 147:30b64687e01f 2549 #define CAN_F5R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2550 #define CAN_F5R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2551 #define CAN_F5R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2552 #define CAN_F5R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2553 #define CAN_F5R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2554 #define CAN_F5R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2555 #define CAN_F5R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2556 #define CAN_F5R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2557 #define CAN_F5R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2558 #define CAN_F5R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2559 #define CAN_F5R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2560 #define CAN_F5R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2561 #define CAN_F5R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2562 #define CAN_F5R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2563 #define CAN_F5R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2564 #define CAN_F5R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2565 #define CAN_F5R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2566 #define CAN_F5R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2567 #define CAN_F5R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2568 #define CAN_F5R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2569 #define CAN_F5R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2570 #define CAN_F5R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2571 #define CAN_F5R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2572 #define CAN_F5R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2573 #define CAN_F5R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2574 #define CAN_F5R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2575 #define CAN_F5R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2576 #define CAN_F5R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2577 #define CAN_F5R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2578 #define CAN_F5R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2579 #define CAN_F5R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2580 #define CAN_F5R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2581
<> 147:30b64687e01f 2582 /******************* Bit definition for CAN_F6R1 register *******************/
<> 147:30b64687e01f 2583 #define CAN_F6R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2584 #define CAN_F6R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2585 #define CAN_F6R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2586 #define CAN_F6R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2587 #define CAN_F6R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2588 #define CAN_F6R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2589 #define CAN_F6R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2590 #define CAN_F6R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2591 #define CAN_F6R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2592 #define CAN_F6R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2593 #define CAN_F6R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2594 #define CAN_F6R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2595 #define CAN_F6R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2596 #define CAN_F6R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2597 #define CAN_F6R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2598 #define CAN_F6R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2599 #define CAN_F6R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2600 #define CAN_F6R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2601 #define CAN_F6R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2602 #define CAN_F6R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2603 #define CAN_F6R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2604 #define CAN_F6R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2605 #define CAN_F6R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2606 #define CAN_F6R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2607 #define CAN_F6R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2608 #define CAN_F6R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2609 #define CAN_F6R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2610 #define CAN_F6R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2611 #define CAN_F6R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2612 #define CAN_F6R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2613 #define CAN_F6R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2614 #define CAN_F6R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2615
<> 147:30b64687e01f 2616 /******************* Bit definition for CAN_F7R1 register *******************/
<> 147:30b64687e01f 2617 #define CAN_F7R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2618 #define CAN_F7R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2619 #define CAN_F7R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2620 #define CAN_F7R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2621 #define CAN_F7R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2622 #define CAN_F7R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2623 #define CAN_F7R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2624 #define CAN_F7R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2625 #define CAN_F7R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2626 #define CAN_F7R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2627 #define CAN_F7R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2628 #define CAN_F7R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2629 #define CAN_F7R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2630 #define CAN_F7R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2631 #define CAN_F7R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2632 #define CAN_F7R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2633 #define CAN_F7R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2634 #define CAN_F7R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2635 #define CAN_F7R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2636 #define CAN_F7R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2637 #define CAN_F7R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2638 #define CAN_F7R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2639 #define CAN_F7R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2640 #define CAN_F7R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2641 #define CAN_F7R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2642 #define CAN_F7R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2643 #define CAN_F7R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2644 #define CAN_F7R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2645 #define CAN_F7R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2646 #define CAN_F7R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2647 #define CAN_F7R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2648 #define CAN_F7R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2649
<> 147:30b64687e01f 2650 /******************* Bit definition for CAN_F8R1 register *******************/
<> 147:30b64687e01f 2651 #define CAN_F8R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2652 #define CAN_F8R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2653 #define CAN_F8R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2654 #define CAN_F8R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2655 #define CAN_F8R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2656 #define CAN_F8R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2657 #define CAN_F8R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2658 #define CAN_F8R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2659 #define CAN_F8R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2660 #define CAN_F8R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2661 #define CAN_F8R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2662 #define CAN_F8R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2663 #define CAN_F8R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2664 #define CAN_F8R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2665 #define CAN_F8R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2666 #define CAN_F8R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2667 #define CAN_F8R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2668 #define CAN_F8R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2669 #define CAN_F8R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2670 #define CAN_F8R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2671 #define CAN_F8R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2672 #define CAN_F8R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2673 #define CAN_F8R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2674 #define CAN_F8R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2675 #define CAN_F8R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2676 #define CAN_F8R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2677 #define CAN_F8R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2678 #define CAN_F8R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2679 #define CAN_F8R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2680 #define CAN_F8R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2681 #define CAN_F8R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2682 #define CAN_F8R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2683
<> 147:30b64687e01f 2684 /******************* Bit definition for CAN_F9R1 register *******************/
<> 147:30b64687e01f 2685 #define CAN_F9R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2686 #define CAN_F9R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2687 #define CAN_F9R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2688 #define CAN_F9R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2689 #define CAN_F9R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2690 #define CAN_F9R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2691 #define CAN_F9R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2692 #define CAN_F9R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2693 #define CAN_F9R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2694 #define CAN_F9R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2695 #define CAN_F9R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2696 #define CAN_F9R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2697 #define CAN_F9R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2698 #define CAN_F9R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2699 #define CAN_F9R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2700 #define CAN_F9R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2701 #define CAN_F9R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2702 #define CAN_F9R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2703 #define CAN_F9R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2704 #define CAN_F9R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2705 #define CAN_F9R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2706 #define CAN_F9R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2707 #define CAN_F9R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2708 #define CAN_F9R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2709 #define CAN_F9R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2710 #define CAN_F9R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2711 #define CAN_F9R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2712 #define CAN_F9R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2713 #define CAN_F9R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2714 #define CAN_F9R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2715 #define CAN_F9R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2716 #define CAN_F9R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2717
<> 147:30b64687e01f 2718 /******************* Bit definition for CAN_F10R1 register ******************/
<> 147:30b64687e01f 2719 #define CAN_F10R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2720 #define CAN_F10R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2721 #define CAN_F10R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2722 #define CAN_F10R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2723 #define CAN_F10R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2724 #define CAN_F10R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2725 #define CAN_F10R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2726 #define CAN_F10R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2727 #define CAN_F10R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2728 #define CAN_F10R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2729 #define CAN_F10R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2730 #define CAN_F10R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2731 #define CAN_F10R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2732 #define CAN_F10R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2733 #define CAN_F10R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2734 #define CAN_F10R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2735 #define CAN_F10R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2736 #define CAN_F10R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2737 #define CAN_F10R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2738 #define CAN_F10R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2739 #define CAN_F10R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2740 #define CAN_F10R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2741 #define CAN_F10R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2742 #define CAN_F10R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2743 #define CAN_F10R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2744 #define CAN_F10R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2745 #define CAN_F10R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2746 #define CAN_F10R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2747 #define CAN_F10R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2748 #define CAN_F10R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2749 #define CAN_F10R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2750 #define CAN_F10R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2751
<> 147:30b64687e01f 2752 /******************* Bit definition for CAN_F11R1 register ******************/
<> 147:30b64687e01f 2753 #define CAN_F11R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2754 #define CAN_F11R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2755 #define CAN_F11R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2756 #define CAN_F11R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2757 #define CAN_F11R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2758 #define CAN_F11R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2759 #define CAN_F11R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2760 #define CAN_F11R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2761 #define CAN_F11R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2762 #define CAN_F11R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2763 #define CAN_F11R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2764 #define CAN_F11R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2765 #define CAN_F11R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2766 #define CAN_F11R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2767 #define CAN_F11R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2768 #define CAN_F11R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2769 #define CAN_F11R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2770 #define CAN_F11R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2771 #define CAN_F11R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2772 #define CAN_F11R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2773 #define CAN_F11R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2774 #define CAN_F11R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2775 #define CAN_F11R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2776 #define CAN_F11R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2777 #define CAN_F11R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2778 #define CAN_F11R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2779 #define CAN_F11R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2780 #define CAN_F11R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2781 #define CAN_F11R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2782 #define CAN_F11R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2783 #define CAN_F11R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2784 #define CAN_F11R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2785
<> 147:30b64687e01f 2786 /******************* Bit definition for CAN_F12R1 register ******************/
<> 147:30b64687e01f 2787 #define CAN_F12R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2788 #define CAN_F12R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2789 #define CAN_F12R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2790 #define CAN_F12R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2791 #define CAN_F12R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2792 #define CAN_F12R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2793 #define CAN_F12R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2794 #define CAN_F12R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2795 #define CAN_F12R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2796 #define CAN_F12R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2797 #define CAN_F12R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2798 #define CAN_F12R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2799 #define CAN_F12R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2800 #define CAN_F12R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2801 #define CAN_F12R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2802 #define CAN_F12R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2803 #define CAN_F12R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2804 #define CAN_F12R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2805 #define CAN_F12R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2806 #define CAN_F12R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2807 #define CAN_F12R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2808 #define CAN_F12R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2809 #define CAN_F12R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2810 #define CAN_F12R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2811 #define CAN_F12R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2812 #define CAN_F12R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2813 #define CAN_F12R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2814 #define CAN_F12R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2815 #define CAN_F12R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2816 #define CAN_F12R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2817 #define CAN_F12R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2818 #define CAN_F12R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2819
<> 147:30b64687e01f 2820 /******************* Bit definition for CAN_F13R1 register ******************/
<> 147:30b64687e01f 2821 #define CAN_F13R1_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2822 #define CAN_F13R1_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2823 #define CAN_F13R1_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2824 #define CAN_F13R1_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2825 #define CAN_F13R1_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2826 #define CAN_F13R1_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2827 #define CAN_F13R1_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2828 #define CAN_F13R1_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2829 #define CAN_F13R1_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2830 #define CAN_F13R1_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2831 #define CAN_F13R1_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2832 #define CAN_F13R1_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2833 #define CAN_F13R1_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2834 #define CAN_F13R1_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2835 #define CAN_F13R1_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2836 #define CAN_F13R1_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2837 #define CAN_F13R1_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2838 #define CAN_F13R1_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2839 #define CAN_F13R1_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2840 #define CAN_F13R1_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2841 #define CAN_F13R1_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2842 #define CAN_F13R1_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2843 #define CAN_F13R1_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2844 #define CAN_F13R1_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2845 #define CAN_F13R1_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2846 #define CAN_F13R1_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2847 #define CAN_F13R1_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2848 #define CAN_F13R1_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2849 #define CAN_F13R1_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2850 #define CAN_F13R1_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2851 #define CAN_F13R1_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2852 #define CAN_F13R1_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2853
<> 147:30b64687e01f 2854 /******************* Bit definition for CAN_F0R2 register *******************/
<> 147:30b64687e01f 2855 #define CAN_F0R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2856 #define CAN_F0R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2857 #define CAN_F0R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2858 #define CAN_F0R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2859 #define CAN_F0R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2860 #define CAN_F0R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2861 #define CAN_F0R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2862 #define CAN_F0R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2863 #define CAN_F0R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2864 #define CAN_F0R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2865 #define CAN_F0R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2866 #define CAN_F0R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2867 #define CAN_F0R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2868 #define CAN_F0R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2869 #define CAN_F0R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2870 #define CAN_F0R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2871 #define CAN_F0R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2872 #define CAN_F0R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2873 #define CAN_F0R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2874 #define CAN_F0R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2875 #define CAN_F0R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2876 #define CAN_F0R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2877 #define CAN_F0R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2878 #define CAN_F0R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2879 #define CAN_F0R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2880 #define CAN_F0R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2881 #define CAN_F0R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2882 #define CAN_F0R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2883 #define CAN_F0R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2884 #define CAN_F0R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2885 #define CAN_F0R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2886 #define CAN_F0R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2887
<> 147:30b64687e01f 2888 /******************* Bit definition for CAN_F1R2 register *******************/
<> 147:30b64687e01f 2889 #define CAN_F1R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2890 #define CAN_F1R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2891 #define CAN_F1R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2892 #define CAN_F1R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2893 #define CAN_F1R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2894 #define CAN_F1R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2895 #define CAN_F1R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2896 #define CAN_F1R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2897 #define CAN_F1R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2898 #define CAN_F1R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2899 #define CAN_F1R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2900 #define CAN_F1R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2901 #define CAN_F1R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2902 #define CAN_F1R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2903 #define CAN_F1R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2904 #define CAN_F1R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2905 #define CAN_F1R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2906 #define CAN_F1R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2907 #define CAN_F1R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2908 #define CAN_F1R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2909 #define CAN_F1R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2910 #define CAN_F1R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2911 #define CAN_F1R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2912 #define CAN_F1R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2913 #define CAN_F1R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2914 #define CAN_F1R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2915 #define CAN_F1R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2916 #define CAN_F1R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2917 #define CAN_F1R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2918 #define CAN_F1R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2919 #define CAN_F1R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2920 #define CAN_F1R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2921
<> 147:30b64687e01f 2922 /******************* Bit definition for CAN_F2R2 register *******************/
<> 147:30b64687e01f 2923 #define CAN_F2R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2924 #define CAN_F2R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2925 #define CAN_F2R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2926 #define CAN_F2R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2927 #define CAN_F2R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2928 #define CAN_F2R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2929 #define CAN_F2R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2930 #define CAN_F2R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2931 #define CAN_F2R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2932 #define CAN_F2R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2933 #define CAN_F2R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2934 #define CAN_F2R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2935 #define CAN_F2R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2936 #define CAN_F2R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2937 #define CAN_F2R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2938 #define CAN_F2R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2939 #define CAN_F2R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2940 #define CAN_F2R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2941 #define CAN_F2R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2942 #define CAN_F2R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2943 #define CAN_F2R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2944 #define CAN_F2R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2945 #define CAN_F2R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2946 #define CAN_F2R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2947 #define CAN_F2R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2948 #define CAN_F2R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2949 #define CAN_F2R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2950 #define CAN_F2R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2951 #define CAN_F2R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2952 #define CAN_F2R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2953 #define CAN_F2R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2954 #define CAN_F2R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2955
<> 147:30b64687e01f 2956 /******************* Bit definition for CAN_F3R2 register *******************/
<> 147:30b64687e01f 2957 #define CAN_F3R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2958 #define CAN_F3R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2959 #define CAN_F3R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2960 #define CAN_F3R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2961 #define CAN_F3R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2962 #define CAN_F3R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2963 #define CAN_F3R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2964 #define CAN_F3R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2965 #define CAN_F3R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 2966 #define CAN_F3R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 2967 #define CAN_F3R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 2968 #define CAN_F3R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 2969 #define CAN_F3R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 2970 #define CAN_F3R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 2971 #define CAN_F3R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 2972 #define CAN_F3R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 2973 #define CAN_F3R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 2974 #define CAN_F3R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 2975 #define CAN_F3R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 2976 #define CAN_F3R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 2977 #define CAN_F3R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 2978 #define CAN_F3R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 2979 #define CAN_F3R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 2980 #define CAN_F3R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 2981 #define CAN_F3R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 2982 #define CAN_F3R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 2983 #define CAN_F3R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 2984 #define CAN_F3R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 2985 #define CAN_F3R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 2986 #define CAN_F3R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 2987 #define CAN_F3R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 2988 #define CAN_F3R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 2989
<> 147:30b64687e01f 2990 /******************* Bit definition for CAN_F4R2 register *******************/
<> 147:30b64687e01f 2991 #define CAN_F4R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 2992 #define CAN_F4R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 2993 #define CAN_F4R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 2994 #define CAN_F4R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 2995 #define CAN_F4R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 2996 #define CAN_F4R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 2997 #define CAN_F4R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 2998 #define CAN_F4R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 2999 #define CAN_F4R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3000 #define CAN_F4R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3001 #define CAN_F4R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3002 #define CAN_F4R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3003 #define CAN_F4R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3004 #define CAN_F4R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3005 #define CAN_F4R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3006 #define CAN_F4R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3007 #define CAN_F4R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3008 #define CAN_F4R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3009 #define CAN_F4R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3010 #define CAN_F4R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3011 #define CAN_F4R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3012 #define CAN_F4R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3013 #define CAN_F4R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3014 #define CAN_F4R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3015 #define CAN_F4R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3016 #define CAN_F4R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3017 #define CAN_F4R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3018 #define CAN_F4R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3019 #define CAN_F4R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3020 #define CAN_F4R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3021 #define CAN_F4R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3022 #define CAN_F4R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3023
<> 147:30b64687e01f 3024 /******************* Bit definition for CAN_F5R2 register *******************/
<> 147:30b64687e01f 3025 #define CAN_F5R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3026 #define CAN_F5R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3027 #define CAN_F5R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3028 #define CAN_F5R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3029 #define CAN_F5R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3030 #define CAN_F5R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3031 #define CAN_F5R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3032 #define CAN_F5R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3033 #define CAN_F5R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3034 #define CAN_F5R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3035 #define CAN_F5R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3036 #define CAN_F5R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3037 #define CAN_F5R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3038 #define CAN_F5R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3039 #define CAN_F5R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3040 #define CAN_F5R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3041 #define CAN_F5R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3042 #define CAN_F5R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3043 #define CAN_F5R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3044 #define CAN_F5R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3045 #define CAN_F5R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3046 #define CAN_F5R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3047 #define CAN_F5R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3048 #define CAN_F5R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3049 #define CAN_F5R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3050 #define CAN_F5R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3051 #define CAN_F5R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3052 #define CAN_F5R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3053 #define CAN_F5R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3054 #define CAN_F5R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3055 #define CAN_F5R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3056 #define CAN_F5R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3057
<> 147:30b64687e01f 3058 /******************* Bit definition for CAN_F6R2 register *******************/
<> 147:30b64687e01f 3059 #define CAN_F6R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3060 #define CAN_F6R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3061 #define CAN_F6R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3062 #define CAN_F6R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3063 #define CAN_F6R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3064 #define CAN_F6R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3065 #define CAN_F6R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3066 #define CAN_F6R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3067 #define CAN_F6R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3068 #define CAN_F6R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3069 #define CAN_F6R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3070 #define CAN_F6R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3071 #define CAN_F6R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3072 #define CAN_F6R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3073 #define CAN_F6R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3074 #define CAN_F6R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3075 #define CAN_F6R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3076 #define CAN_F6R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3077 #define CAN_F6R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3078 #define CAN_F6R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3079 #define CAN_F6R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3080 #define CAN_F6R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3081 #define CAN_F6R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3082 #define CAN_F6R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3083 #define CAN_F6R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3084 #define CAN_F6R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3085 #define CAN_F6R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3086 #define CAN_F6R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3087 #define CAN_F6R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3088 #define CAN_F6R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3089 #define CAN_F6R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3090 #define CAN_F6R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3091
<> 147:30b64687e01f 3092 /******************* Bit definition for CAN_F7R2 register *******************/
<> 147:30b64687e01f 3093 #define CAN_F7R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3094 #define CAN_F7R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3095 #define CAN_F7R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3096 #define CAN_F7R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3097 #define CAN_F7R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3098 #define CAN_F7R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3099 #define CAN_F7R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3100 #define CAN_F7R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3101 #define CAN_F7R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3102 #define CAN_F7R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3103 #define CAN_F7R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3104 #define CAN_F7R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3105 #define CAN_F7R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3106 #define CAN_F7R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3107 #define CAN_F7R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3108 #define CAN_F7R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3109 #define CAN_F7R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3110 #define CAN_F7R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3111 #define CAN_F7R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3112 #define CAN_F7R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3113 #define CAN_F7R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3114 #define CAN_F7R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3115 #define CAN_F7R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3116 #define CAN_F7R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3117 #define CAN_F7R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3118 #define CAN_F7R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3119 #define CAN_F7R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3120 #define CAN_F7R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3121 #define CAN_F7R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3122 #define CAN_F7R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3123 #define CAN_F7R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3124 #define CAN_F7R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3125
<> 147:30b64687e01f 3126 /******************* Bit definition for CAN_F8R2 register *******************/
<> 147:30b64687e01f 3127 #define CAN_F8R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3128 #define CAN_F8R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3129 #define CAN_F8R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3130 #define CAN_F8R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3131 #define CAN_F8R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3132 #define CAN_F8R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3133 #define CAN_F8R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3134 #define CAN_F8R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3135 #define CAN_F8R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3136 #define CAN_F8R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3137 #define CAN_F8R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3138 #define CAN_F8R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3139 #define CAN_F8R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3140 #define CAN_F8R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3141 #define CAN_F8R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3142 #define CAN_F8R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3143 #define CAN_F8R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3144 #define CAN_F8R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3145 #define CAN_F8R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3146 #define CAN_F8R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3147 #define CAN_F8R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3148 #define CAN_F8R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3149 #define CAN_F8R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3150 #define CAN_F8R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3151 #define CAN_F8R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3152 #define CAN_F8R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3153 #define CAN_F8R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3154 #define CAN_F8R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3155 #define CAN_F8R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3156 #define CAN_F8R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3157 #define CAN_F8R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3158 #define CAN_F8R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3159
<> 147:30b64687e01f 3160 /******************* Bit definition for CAN_F9R2 register *******************/
<> 147:30b64687e01f 3161 #define CAN_F9R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3162 #define CAN_F9R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3163 #define CAN_F9R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3164 #define CAN_F9R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3165 #define CAN_F9R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3166 #define CAN_F9R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3167 #define CAN_F9R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3168 #define CAN_F9R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3169 #define CAN_F9R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3170 #define CAN_F9R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3171 #define CAN_F9R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3172 #define CAN_F9R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3173 #define CAN_F9R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3174 #define CAN_F9R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3175 #define CAN_F9R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3176 #define CAN_F9R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3177 #define CAN_F9R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3178 #define CAN_F9R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3179 #define CAN_F9R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3180 #define CAN_F9R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3181 #define CAN_F9R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3182 #define CAN_F9R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3183 #define CAN_F9R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3184 #define CAN_F9R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3185 #define CAN_F9R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3186 #define CAN_F9R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3187 #define CAN_F9R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3188 #define CAN_F9R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3189 #define CAN_F9R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3190 #define CAN_F9R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3191 #define CAN_F9R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3192 #define CAN_F9R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3193
<> 147:30b64687e01f 3194 /******************* Bit definition for CAN_F10R2 register ******************/
<> 147:30b64687e01f 3195 #define CAN_F10R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3196 #define CAN_F10R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3197 #define CAN_F10R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3198 #define CAN_F10R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3199 #define CAN_F10R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3200 #define CAN_F10R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3201 #define CAN_F10R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3202 #define CAN_F10R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3203 #define CAN_F10R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3204 #define CAN_F10R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3205 #define CAN_F10R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3206 #define CAN_F10R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3207 #define CAN_F10R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3208 #define CAN_F10R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3209 #define CAN_F10R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3210 #define CAN_F10R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3211 #define CAN_F10R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3212 #define CAN_F10R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3213 #define CAN_F10R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3214 #define CAN_F10R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3215 #define CAN_F10R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3216 #define CAN_F10R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3217 #define CAN_F10R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3218 #define CAN_F10R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3219 #define CAN_F10R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3220 #define CAN_F10R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3221 #define CAN_F10R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3222 #define CAN_F10R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3223 #define CAN_F10R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3224 #define CAN_F10R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3225 #define CAN_F10R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3226 #define CAN_F10R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3227
<> 147:30b64687e01f 3228 /******************* Bit definition for CAN_F11R2 register ******************/
<> 147:30b64687e01f 3229 #define CAN_F11R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3230 #define CAN_F11R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3231 #define CAN_F11R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3232 #define CAN_F11R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3233 #define CAN_F11R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3234 #define CAN_F11R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3235 #define CAN_F11R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3236 #define CAN_F11R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3237 #define CAN_F11R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3238 #define CAN_F11R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3239 #define CAN_F11R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3240 #define CAN_F11R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3241 #define CAN_F11R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3242 #define CAN_F11R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3243 #define CAN_F11R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3244 #define CAN_F11R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3245 #define CAN_F11R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3246 #define CAN_F11R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3247 #define CAN_F11R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3248 #define CAN_F11R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3249 #define CAN_F11R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3250 #define CAN_F11R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3251 #define CAN_F11R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3252 #define CAN_F11R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3253 #define CAN_F11R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3254 #define CAN_F11R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3255 #define CAN_F11R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3256 #define CAN_F11R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3257 #define CAN_F11R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3258 #define CAN_F11R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3259 #define CAN_F11R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3260 #define CAN_F11R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3261
<> 147:30b64687e01f 3262 /******************* Bit definition for CAN_F12R2 register ******************/
<> 147:30b64687e01f 3263 #define CAN_F12R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3264 #define CAN_F12R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3265 #define CAN_F12R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3266 #define CAN_F12R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3267 #define CAN_F12R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3268 #define CAN_F12R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3269 #define CAN_F12R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3270 #define CAN_F12R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3271 #define CAN_F12R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3272 #define CAN_F12R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3273 #define CAN_F12R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3274 #define CAN_F12R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3275 #define CAN_F12R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3276 #define CAN_F12R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3277 #define CAN_F12R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3278 #define CAN_F12R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3279 #define CAN_F12R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3280 #define CAN_F12R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3281 #define CAN_F12R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3282 #define CAN_F12R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3283 #define CAN_F12R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3284 #define CAN_F12R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3285 #define CAN_F12R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3286 #define CAN_F12R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3287 #define CAN_F12R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3288 #define CAN_F12R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3289 #define CAN_F12R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3290 #define CAN_F12R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3291 #define CAN_F12R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3292 #define CAN_F12R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3293 #define CAN_F12R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3294 #define CAN_F12R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3295
<> 147:30b64687e01f 3296 /******************* Bit definition for CAN_F13R2 register ******************/
<> 147:30b64687e01f 3297 #define CAN_F13R2_FB0 0x00000001U /*!<Filter bit 0 */
<> 147:30b64687e01f 3298 #define CAN_F13R2_FB1 0x00000002U /*!<Filter bit 1 */
<> 147:30b64687e01f 3299 #define CAN_F13R2_FB2 0x00000004U /*!<Filter bit 2 */
<> 147:30b64687e01f 3300 #define CAN_F13R2_FB3 0x00000008U /*!<Filter bit 3 */
<> 147:30b64687e01f 3301 #define CAN_F13R2_FB4 0x00000010U /*!<Filter bit 4 */
<> 147:30b64687e01f 3302 #define CAN_F13R2_FB5 0x00000020U /*!<Filter bit 5 */
<> 147:30b64687e01f 3303 #define CAN_F13R2_FB6 0x00000040U /*!<Filter bit 6 */
<> 147:30b64687e01f 3304 #define CAN_F13R2_FB7 0x00000080U /*!<Filter bit 7 */
<> 147:30b64687e01f 3305 #define CAN_F13R2_FB8 0x00000100U /*!<Filter bit 8 */
<> 147:30b64687e01f 3306 #define CAN_F13R2_FB9 0x00000200U /*!<Filter bit 9 */
<> 147:30b64687e01f 3307 #define CAN_F13R2_FB10 0x00000400U /*!<Filter bit 10 */
<> 147:30b64687e01f 3308 #define CAN_F13R2_FB11 0x00000800U /*!<Filter bit 11 */
<> 147:30b64687e01f 3309 #define CAN_F13R2_FB12 0x00001000U /*!<Filter bit 12 */
<> 147:30b64687e01f 3310 #define CAN_F13R2_FB13 0x00002000U /*!<Filter bit 13 */
<> 147:30b64687e01f 3311 #define CAN_F13R2_FB14 0x00004000U /*!<Filter bit 14 */
<> 147:30b64687e01f 3312 #define CAN_F13R2_FB15 0x00008000U /*!<Filter bit 15 */
<> 147:30b64687e01f 3313 #define CAN_F13R2_FB16 0x00010000U /*!<Filter bit 16 */
<> 147:30b64687e01f 3314 #define CAN_F13R2_FB17 0x00020000U /*!<Filter bit 17 */
<> 147:30b64687e01f 3315 #define CAN_F13R2_FB18 0x00040000U /*!<Filter bit 18 */
<> 147:30b64687e01f 3316 #define CAN_F13R2_FB19 0x00080000U /*!<Filter bit 19 */
<> 147:30b64687e01f 3317 #define CAN_F13R2_FB20 0x00100000U /*!<Filter bit 20 */
<> 147:30b64687e01f 3318 #define CAN_F13R2_FB21 0x00200000U /*!<Filter bit 21 */
<> 147:30b64687e01f 3319 #define CAN_F13R2_FB22 0x00400000U /*!<Filter bit 22 */
<> 147:30b64687e01f 3320 #define CAN_F13R2_FB23 0x00800000U /*!<Filter bit 23 */
<> 147:30b64687e01f 3321 #define CAN_F13R2_FB24 0x01000000U /*!<Filter bit 24 */
<> 147:30b64687e01f 3322 #define CAN_F13R2_FB25 0x02000000U /*!<Filter bit 25 */
<> 147:30b64687e01f 3323 #define CAN_F13R2_FB26 0x04000000U /*!<Filter bit 26 */
<> 147:30b64687e01f 3324 #define CAN_F13R2_FB27 0x08000000U /*!<Filter bit 27 */
<> 147:30b64687e01f 3325 #define CAN_F13R2_FB28 0x10000000U /*!<Filter bit 28 */
<> 147:30b64687e01f 3326 #define CAN_F13R2_FB29 0x20000000U /*!<Filter bit 29 */
<> 147:30b64687e01f 3327 #define CAN_F13R2_FB30 0x40000000U /*!<Filter bit 30 */
<> 147:30b64687e01f 3328 #define CAN_F13R2_FB31 0x80000000U /*!<Filter bit 31 */
<> 147:30b64687e01f 3329
<> 147:30b64687e01f 3330 /******************************************************************************/
<> 147:30b64687e01f 3331 /* */
<> 147:30b64687e01f 3332 /* HDMI-CEC (CEC) */
<> 147:30b64687e01f 3333 /* */
<> 147:30b64687e01f 3334 /******************************************************************************/
<> 147:30b64687e01f 3335
<> 147:30b64687e01f 3336 /******************* Bit definition for CEC_CR register *********************/
<> 147:30b64687e01f 3337 #define CEC_CR_CECEN 0x00000001U /*!< CEC Enable */
<> 147:30b64687e01f 3338 #define CEC_CR_TXSOM 0x00000002U /*!< CEC Tx Start Of Message */
<> 147:30b64687e01f 3339 #define CEC_CR_TXEOM 0x00000004U /*!< CEC Tx End Of Message */
<> 147:30b64687e01f 3340
<> 147:30b64687e01f 3341 /******************* Bit definition for CEC_CFGR register *******************/
<> 147:30b64687e01f 3342 #define CEC_CFGR_SFT 0x00000007U /*!< CEC Signal Free Time */
<> 147:30b64687e01f 3343 #define CEC_CFGR_RXTOL 0x00000008U /*!< CEC Tolerance */
<> 147:30b64687e01f 3344 #define CEC_CFGR_BRESTP 0x00000010U /*!< CEC Rx Stop */
<> 147:30b64687e01f 3345 #define CEC_CFGR_BREGEN 0x00000020U /*!< CEC Bit Rising Error generation */
<> 147:30b64687e01f 3346 #define CEC_CFGR_LBPEGEN 0x00000040U /*!< CEC Long Period Error generation */
<> 147:30b64687e01f 3347 #define CEC_CFGR_BRDNOGEN 0x00000080U /*!< CEC Broadcast no Error generation */
<> 147:30b64687e01f 3348 #define CEC_CFGR_SFTOPT 0x00000100U /*!< CEC Signal Free Time optional */
<> 147:30b64687e01f 3349 #define CEC_CFGR_OAR 0x7FFF0000U /*!< CEC Own Address */
<> 147:30b64687e01f 3350 #define CEC_CFGR_LSTN 0x80000000U /*!< CEC Listen mode */
<> 147:30b64687e01f 3351
<> 147:30b64687e01f 3352 /******************* Bit definition for CEC_TXDR register *******************/
<> 147:30b64687e01f 3353 #define CEC_TXDR_TXD 0x000000FFU /*!< CEC Tx Data */
<> 147:30b64687e01f 3354
<> 147:30b64687e01f 3355 /******************* Bit definition for CEC_RXDR register *******************/
<> 147:30b64687e01f 3356 #define CEC_TXDR_RXD 0x000000FFU /*!< CEC Rx Data */
<> 147:30b64687e01f 3357
<> 147:30b64687e01f 3358 /******************* Bit definition for CEC_ISR register ********************/
<> 147:30b64687e01f 3359 #define CEC_ISR_RXBR 0x00000001U /*!< CEC Rx-Byte Received */
<> 147:30b64687e01f 3360 #define CEC_ISR_RXEND 0x00000002U /*!< CEC End Of Reception */
<> 147:30b64687e01f 3361 #define CEC_ISR_RXOVR 0x00000004U /*!< CEC Rx-Overrun */
<> 147:30b64687e01f 3362 #define CEC_ISR_BRE 0x00000008U /*!< CEC Rx Bit Rising Error */
<> 147:30b64687e01f 3363 #define CEC_ISR_SBPE 0x00000010U /*!< CEC Rx Short Bit period Error */
<> 147:30b64687e01f 3364 #define CEC_ISR_LBPE 0x00000020U /*!< CEC Rx Long Bit period Error */
<> 147:30b64687e01f 3365 #define CEC_ISR_RXACKE 0x00000040U /*!< CEC Rx Missing Acknowledge */
<> 147:30b64687e01f 3366 #define CEC_ISR_ARBLST 0x00000080U /*!< CEC Arbitration Lost */
<> 147:30b64687e01f 3367 #define CEC_ISR_TXBR 0x00000100U /*!< CEC Tx Byte Request */
<> 147:30b64687e01f 3368 #define CEC_ISR_TXEND 0x00000200U /*!< CEC End of Transmission */
<> 147:30b64687e01f 3369 #define CEC_ISR_TXUDR 0x00000400U /*!< CEC Tx-Buffer Underrun */
<> 147:30b64687e01f 3370 #define CEC_ISR_TXERR 0x00000800U /*!< CEC Tx-Error */
<> 147:30b64687e01f 3371 #define CEC_ISR_TXACKE 0x00001000U /*!< CEC Tx Missing Acknowledge */
<> 147:30b64687e01f 3372
<> 147:30b64687e01f 3373 /******************* Bit definition for CEC_IER register ********************/
<> 147:30b64687e01f 3374 #define CEC_IER_RXBRIE 0x00000001U /*!< CEC Rx-Byte Received IT Enable */
<> 147:30b64687e01f 3375 #define CEC_IER_RXENDIE 0x00000002U /*!< CEC End Of Reception IT Enable */
<> 147:30b64687e01f 3376 #define CEC_IER_RXOVRIE 0x00000004U /*!< CEC Rx-Overrun IT Enable */
<> 147:30b64687e01f 3377 #define CEC_IER_BREIE 0x00000008U /*!< CEC Rx Bit Rising Error IT Enable */
<> 147:30b64687e01f 3378 #define CEC_IER_SBPEIE 0x00000010U /*!< CEC Rx Short Bit period Error IT Enable*/
<> 147:30b64687e01f 3379 #define CEC_IER_LBPEIE 0x00000020U /*!< CEC Rx Long Bit period Error IT Enable */
<> 147:30b64687e01f 3380 #define CEC_IER_RXACKEIE 0x00000040U /*!< CEC Rx Missing Acknowledge IT Enable */
<> 147:30b64687e01f 3381 #define CEC_IER_ARBLSTIE 0x00000080U /*!< CEC Arbitration Lost IT Enable */
<> 147:30b64687e01f 3382 #define CEC_IER_TXBRIE 0x00000100U /*!< CEC Tx Byte Request IT Enable */
<> 147:30b64687e01f 3383 #define CEC_IER_TXENDIE 0x00000200U /*!< CEC End of Transmission IT Enable */
<> 147:30b64687e01f 3384 #define CEC_IER_TXUDRIE 0x00000400U /*!< CEC Tx-Buffer Underrun IT Enable */
<> 147:30b64687e01f 3385 #define CEC_IER_TXERRIE 0x00000800U /*!< CEC Tx-Error IT Enable */
<> 147:30b64687e01f 3386 #define CEC_IER_TXACKEIE 0x00001000U /*!< CEC Tx Missing Acknowledge IT Enable */
<> 147:30b64687e01f 3387
<> 147:30b64687e01f 3388 /******************************************************************************/
<> 147:30b64687e01f 3389 /* */
<> 147:30b64687e01f 3390 /* CRC calculation unit */
<> 147:30b64687e01f 3391 /* */
<> 147:30b64687e01f 3392 /******************************************************************************/
<> 147:30b64687e01f 3393 /******************* Bit definition for CRC_DR register *********************/
<> 147:30b64687e01f 3394 #define CRC_DR_DR 0xFFFFFFFFU /*!< Data register bits */
<> 147:30b64687e01f 3395
<> 147:30b64687e01f 3396 /******************* Bit definition for CRC_IDR register ********************/
<> 147:30b64687e01f 3397 #define CRC_IDR_IDR 0x000000FFU /*!< General-purpose 8-bit data register bits */
<> 147:30b64687e01f 3398
<> 147:30b64687e01f 3399 /******************** Bit definition for CRC_CR register ********************/
<> 147:30b64687e01f 3400 #define CRC_CR_RESET 0x00000001U /*!< RESET the CRC computation unit bit */
<> 147:30b64687e01f 3401 #define CRC_CR_POLYSIZE 0x00000018U /*!< Polynomial size bits */
<> 147:30b64687e01f 3402 #define CRC_CR_POLYSIZE_0 0x00000008U /*!< Polynomial size bit 0 */
<> 147:30b64687e01f 3403 #define CRC_CR_POLYSIZE_1 0x00000010U /*!< Polynomial size bit 1 */
<> 147:30b64687e01f 3404 #define CRC_CR_REV_IN 0x00000060U /*!< REV_IN Reverse Input Data bits */
<> 147:30b64687e01f 3405 #define CRC_CR_REV_IN_0 0x00000020U /*!< Bit 0 */
<> 147:30b64687e01f 3406 #define CRC_CR_REV_IN_1 0x00000040U /*!< Bit 1 */
<> 147:30b64687e01f 3407 #define CRC_CR_REV_OUT 0x00000080U /*!< REV_OUT Reverse Output Data bits */
<> 147:30b64687e01f 3408
<> 147:30b64687e01f 3409 /******************* Bit definition for CRC_INIT register *******************/
<> 147:30b64687e01f 3410 #define CRC_INIT_INIT 0xFFFFFFFFU /*!< Initial CRC value bits */
<> 147:30b64687e01f 3411
<> 147:30b64687e01f 3412 /******************* Bit definition for CRC_POL register ********************/
<> 147:30b64687e01f 3413 #define CRC_POL_POL 0xFFFFFFFFU /*!< Coefficients of the polynomial */
<> 147:30b64687e01f 3414
<> 147:30b64687e01f 3415
<> 147:30b64687e01f 3416 /******************************************************************************/
<> 147:30b64687e01f 3417 /* */
<> 147:30b64687e01f 3418 /* Digital to Analog Converter */
<> 147:30b64687e01f 3419 /* */
<> 147:30b64687e01f 3420 /******************************************************************************/
<> 147:30b64687e01f 3421 /******************** Bit definition for DAC_CR register ********************/
<> 147:30b64687e01f 3422 #define DAC_CR_EN1 0x00000001U /*!<DAC channel1 enable */
<> 147:30b64687e01f 3423 #define DAC_CR_BOFF1 0x00000002U /*!<DAC channel1 output buffer disable */
<> 147:30b64687e01f 3424 #define DAC_CR_TEN1 0x00000004U /*!<DAC channel1 Trigger enable */
<> 147:30b64687e01f 3425 #define DAC_CR_TSEL1 0x00000038U /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
<> 147:30b64687e01f 3426 #define DAC_CR_TSEL1_0 0x00000008U /*!<Bit 0 */
<> 147:30b64687e01f 3427 #define DAC_CR_TSEL1_1 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 3428 #define DAC_CR_TSEL1_2 0x00000020U /*!<Bit 2 */
<> 147:30b64687e01f 3429 #define DAC_CR_WAVE1 0x000000C0U /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */
<> 147:30b64687e01f 3430 #define DAC_CR_WAVE1_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 3431 #define DAC_CR_WAVE1_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 3432 #define DAC_CR_MAMP1 0x00000F00U /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
<> 147:30b64687e01f 3433 #define DAC_CR_MAMP1_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 3434 #define DAC_CR_MAMP1_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 3435 #define DAC_CR_MAMP1_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 3436 #define DAC_CR_MAMP1_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 3437 #define DAC_CR_DMAEN1 0x00001000U /*!<DAC channel1 DMA enable */
<> 147:30b64687e01f 3438 #define DAC_CR_DMAUDRIE1 0x00002000U /*!<DAC channel1 DMA underrun interrupt enable */
<> 147:30b64687e01f 3439 #define DAC_CR_EN2 0x00010000U /*!<DAC channel2 enable */
<> 147:30b64687e01f 3440 #define DAC_CR_BOFF2 0x00020000U /*!<DAC channel2 output buffer disable */
<> 147:30b64687e01f 3441 #define DAC_CR_TEN2 0x00040000U /*!<DAC channel2 Trigger enable */
<> 147:30b64687e01f 3442 #define DAC_CR_TSEL2 0x00380000U /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
<> 147:30b64687e01f 3443 #define DAC_CR_TSEL2_0 0x00080000U /*!<Bit 0 */
<> 147:30b64687e01f 3444 #define DAC_CR_TSEL2_1 0x00100000U /*!<Bit 1 */
<> 147:30b64687e01f 3445 #define DAC_CR_TSEL2_2 0x00200000U /*!<Bit 2 */
<> 147:30b64687e01f 3446 #define DAC_CR_WAVE2 0x00C00000U /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
<> 147:30b64687e01f 3447 #define DAC_CR_WAVE2_0 0x00400000U /*!<Bit 0 */
<> 147:30b64687e01f 3448 #define DAC_CR_WAVE2_1 0x00800000U /*!<Bit 1 */
<> 147:30b64687e01f 3449 #define DAC_CR_MAMP2 0x0F000000U /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
<> 147:30b64687e01f 3450 #define DAC_CR_MAMP2_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 3451 #define DAC_CR_MAMP2_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 3452 #define DAC_CR_MAMP2_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 3453 #define DAC_CR_MAMP2_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 3454 #define DAC_CR_DMAEN2 0x10000000U /*!<DAC channel2 DMA enable */
<> 147:30b64687e01f 3455 #define DAC_CR_DMAUDRIE2 0x20000000U /*!<DAC channel2 DMA underrun interrupt enable */
<> 147:30b64687e01f 3456
<> 147:30b64687e01f 3457 /***************** Bit definition for DAC_SWTRIGR register ******************/
<> 147:30b64687e01f 3458 #define DAC_SWTRIGR_SWTRIG1 0x01U /*!<DAC channel1 software trigger */
<> 147:30b64687e01f 3459 #define DAC_SWTRIGR_SWTRIG2 0x02U /*!<DAC channel2 software trigger */
<> 147:30b64687e01f 3460
<> 147:30b64687e01f 3461 /***************** Bit definition for DAC_DHR12R1 register ******************/
<> 147:30b64687e01f 3462 #define DAC_DHR12R1_DACC1DHR 0x0FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 147:30b64687e01f 3463
<> 147:30b64687e01f 3464 /***************** Bit definition for DAC_DHR12L1 register ******************/
<> 147:30b64687e01f 3465 #define DAC_DHR12L1_DACC1DHR 0xFFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 147:30b64687e01f 3466
<> 147:30b64687e01f 3467 /****************** Bit definition for DAC_DHR8R1 register ******************/
<> 147:30b64687e01f 3468 #define DAC_DHR8R1_DACC1DHR 0xFFU /*!<DAC channel1 8-bit Right aligned data */
<> 147:30b64687e01f 3469
<> 147:30b64687e01f 3470 /***************** Bit definition for DAC_DHR12R2 register ******************/
<> 147:30b64687e01f 3471 #define DAC_DHR12R2_DACC2DHR 0x0FFFU /*!<DAC channel2 12-bit Right aligned data */
<> 147:30b64687e01f 3472
<> 147:30b64687e01f 3473 /***************** Bit definition for DAC_DHR12L2 register ******************/
<> 147:30b64687e01f 3474 #define DAC_DHR12L2_DACC2DHR 0xFFF0U /*!<DAC channel2 12-bit Left aligned data */
<> 147:30b64687e01f 3475
<> 147:30b64687e01f 3476 /****************** Bit definition for DAC_DHR8R2 register ******************/
<> 147:30b64687e01f 3477 #define DAC_DHR8R2_DACC2DHR 0xFFU /*!<DAC channel2 8-bit Right aligned data */
<> 147:30b64687e01f 3478
<> 147:30b64687e01f 3479 /***************** Bit definition for DAC_DHR12RD register ******************/
<> 147:30b64687e01f 3480 #define DAC_DHR12RD_DACC1DHR 0x00000FFFU /*!<DAC channel1 12-bit Right aligned data */
<> 147:30b64687e01f 3481 #define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /*!<DAC channel2 12-bit Right aligned data */
<> 147:30b64687e01f 3482
<> 147:30b64687e01f 3483 /***************** Bit definition for DAC_DHR12LD register ******************/
<> 147:30b64687e01f 3484 #define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /*!<DAC channel1 12-bit Left aligned data */
<> 147:30b64687e01f 3485 #define DAC_DHR12LD_DACC2DHR 0xFFF00000U /*!<DAC channel2 12-bit Left aligned data */
<> 147:30b64687e01f 3486
<> 147:30b64687e01f 3487 /****************** Bit definition for DAC_DHR8RD register ******************/
<> 147:30b64687e01f 3488 #define DAC_DHR8RD_DACC1DHR 0x00FFU /*!<DAC channel1 8-bit Right aligned data */
<> 147:30b64687e01f 3489 #define DAC_DHR8RD_DACC2DHR 0xFF00U /*!<DAC channel2 8-bit Right aligned data */
<> 147:30b64687e01f 3490
<> 147:30b64687e01f 3491 /******************* Bit definition for DAC_DOR1 register *******************/
<> 147:30b64687e01f 3492 #define DAC_DOR1_DACC1DOR 0x0FFFU /*!<DAC channel1 data output */
<> 147:30b64687e01f 3493
<> 147:30b64687e01f 3494 /******************* Bit definition for DAC_DOR2 register *******************/
<> 147:30b64687e01f 3495 #define DAC_DOR2_DACC2DOR 0x0FFFU /*!<DAC channel2 data output */
<> 147:30b64687e01f 3496
<> 147:30b64687e01f 3497 /******************** Bit definition for DAC_SR register ********************/
<> 147:30b64687e01f 3498 #define DAC_SR_DMAUDR1 0x00002000U /*!<DAC channel1 DMA underrun flag */
<> 147:30b64687e01f 3499 #define DAC_SR_DMAUDR2 0x20000000U /*!<DAC channel2 DMA underrun flag */
<> 147:30b64687e01f 3500
<> 147:30b64687e01f 3501 /******************************************************************************/
<> 147:30b64687e01f 3502 /* */
<> 147:30b64687e01f 3503 /* Digital Filter for Sigma Delta Modulators */
<> 147:30b64687e01f 3504 /* */
<> 147:30b64687e01f 3505 /******************************************************************************/
<> 147:30b64687e01f 3506
<> 147:30b64687e01f 3507 /**************** DFSDM channel configuration registers ********************/
<> 147:30b64687e01f 3508
<> 147:30b64687e01f 3509 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
<> 147:30b64687e01f 3510 #define DFSDM_CHCFGR1_DFSDMEN 0x80000000U /*!< Global enable for DFSDM interface */
<> 147:30b64687e01f 3511 #define DFSDM_CHCFGR1_CKOUTSRC 0x40000000U /*!< Output serial clock source selection */
<> 147:30b64687e01f 3512 #define DFSDM_CHCFGR1_CKOUTDIV 0x00FF0000U /*!< CKOUTDIV[7:0] output serial clock divider */
<> 147:30b64687e01f 3513 #define DFSDM_CHCFGR1_DATPACK 0x0000C000U /*!< DATPACK[1:0] Data packing mode */
<> 147:30b64687e01f 3514 #define DFSDM_CHCFGR1_DATPACK_1 0x00008000U /*!< Data packing mode, Bit 1 */
<> 147:30b64687e01f 3515 #define DFSDM_CHCFGR1_DATPACK_0 0x00004000U /*!< Data packing mode, Bit 0 */
<> 147:30b64687e01f 3516 #define DFSDM_CHCFGR1_DATMPX 0x00003000U /*!< DATMPX[1:0] Input data multiplexer for channel y */
<> 147:30b64687e01f 3517 #define DFSDM_CHCFGR1_DATMPX_1 0x00002000U /*!< Input data multiplexer for channel y, Bit 1 */
<> 147:30b64687e01f 3518 #define DFSDM_CHCFGR1_DATMPX_0 0x00001000U /*!< Input data multiplexer for channel y, Bit 0 */
<> 147:30b64687e01f 3519 #define DFSDM_CHCFGR1_CHINSEL 0x00000100U /*!< Serial inputs selection for channel y */
<> 147:30b64687e01f 3520 #define DFSDM_CHCFGR1_CHEN 0x00000080U /*!< Channel y enable */
<> 147:30b64687e01f 3521 #define DFSDM_CHCFGR1_CKABEN 0x00000040U /*!< Clock absence detector enable on channel y */
<> 147:30b64687e01f 3522 #define DFSDM_CHCFGR1_SCDEN 0x00000020U /*!< Short circuit detector enable on channel y */
<> 147:30b64687e01f 3523 #define DFSDM_CHCFGR1_SPICKSEL 0x0000000CU /*!< SPICKSEL[1:0] SPI clock select for channel y */
<> 147:30b64687e01f 3524 #define DFSDM_CHCFGR1_SPICKSEL_1 0x00000008U /*!< SPI clock select for channel y, Bit 1 */
<> 147:30b64687e01f 3525 #define DFSDM_CHCFGR1_SPICKSEL_0 0x00000004U /*!< SPI clock select for channel y, Bit 0 */
<> 147:30b64687e01f 3526 #define DFSDM_CHCFGR1_SITP 0x00000003U /*!< SITP[1:0] Serial interface type for channel y */
<> 147:30b64687e01f 3527 #define DFSDM_CHCFGR1_SITP_1 0x00000002U /*!< Serial interface type for channel y, Bit 1 */
<> 147:30b64687e01f 3528 #define DFSDM_CHCFGR1_SITP_0 0x00000001U /*!< Serial interface type for channel y, Bit 0 */
<> 147:30b64687e01f 3529
<> 147:30b64687e01f 3530 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
<> 147:30b64687e01f 3531 #define DFSDM_CHCFGR2_OFFSET 0xFFFFFF00U /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
<> 147:30b64687e01f 3532 #define DFSDM_CHCFGR2_DTRBS 0x000000F8U /*!< DTRBS[4:0] Data right bit-shift for channel y */
<> 147:30b64687e01f 3533
<> 147:30b64687e01f 3534 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
<> 147:30b64687e01f 3535 #define DFSDM_CHAWSCDR_AWFORD 0x00C00000U /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
<> 147:30b64687e01f 3536 #define DFSDM_CHAWSCDR_AWFORD_1 0x00800000U /*!< Analog watchdog Sinc filter order on channel y, Bit 1 */
<> 147:30b64687e01f 3537 #define DFSDM_CHAWSCDR_AWFORD_0 0x00400000U /*!< Analog watchdog Sinc filter order on channel y, Bit 0 */
<> 147:30b64687e01f 3538 #define DFSDM_CHAWSCDR_AWFOSR 0x001F0000U /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
<> 147:30b64687e01f 3539 #define DFSDM_CHAWSCDR_BKSCD 0x0000F000U /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
<> 147:30b64687e01f 3540 #define DFSDM_CHAWSCDR_SCDT 0x000000FFU /*!< SCDT[7:0] Short circuit detector threshold for channel y */
<> 147:30b64687e01f 3541
<> 147:30b64687e01f 3542 /**************** Bit definition for DFSDM_CHWDATR register *******************/
<> 147:30b64687e01f 3543 #define DFSDM_CHWDATR_WDATA 0x0000FFFFU /*!< WDATA[15:0] Input channel y watchdog data */
<> 147:30b64687e01f 3544
<> 147:30b64687e01f 3545 /**************** Bit definition for DFSDM_CHDATINR register *****************/
<> 147:30b64687e01f 3546 #define DFSDM_CHDATINR_INDAT0 0x0000FFFFU /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
<> 147:30b64687e01f 3547 #define DFSDM_CHDATINR_INDAT1 0xFFFF0000U /*!< INDAT0[15:0] Input data for channel y */
<> 147:30b64687e01f 3548
<> 147:30b64687e01f 3549 /************************ DFSDM module registers ****************************/
<> 147:30b64687e01f 3550
<> 147:30b64687e01f 3551 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
<> 147:30b64687e01f 3552 #define DFSDM_FLTCR1_AWFSEL 0x40000000U /*!< Analog watchdog fast mode select */
<> 147:30b64687e01f 3553 #define DFSDM_FLTCR1_FAST 0x20000000U /*!< Fast conversion mode selection */
<> 147:30b64687e01f 3554 #define DFSDM_FLTCR1_RCH 0x07000000U /*!< RCH[2:0] Regular channel selection */
<> 147:30b64687e01f 3555 #define DFSDM_FLTCR1_RDMAEN 0x00200000U /*!< DMA channel enabled to read data for the regular conversion */
<> 147:30b64687e01f 3556 #define DFSDM_FLTCR1_RSYNC 0x00080000U /*!< Launch regular conversion synchronously with DFSDMx */
<> 147:30b64687e01f 3557 #define DFSDM_FLTCR1_RCONT 0x00040000U /*!< Continuous mode selection for regular conversions */
<> 147:30b64687e01f 3558 #define DFSDM_FLTCR1_RSWSTART 0x00020000U /*!< Software start of a conversion on the regular channel */
<> 147:30b64687e01f 3559 #define DFSDM_FLTCR1_JEXTEN 0x00006000U /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
<> 147:30b64687e01f 3560 #define DFSDM_FLTCR1_JEXTEN_1 0x00004000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 1 */
<> 147:30b64687e01f 3561 #define DFSDM_FLTCR1_JEXTEN_0 0x00002000U /*!< Trigger enable and trigger edge selection for injected conversions, Bit 0 */
<> 147:30b64687e01f 3562 #define DFSDM_FLTCR1_JEXTSEL 0x00001F00U /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
<> 147:30b64687e01f 3563 #define DFSDM_FLTCR1_JEXTSEL_0 0x00000100U /*!< Trigger signal selection for launching injected conversions, Bit 0 */
<> 147:30b64687e01f 3564 #define DFSDM_FLTCR1_JEXTSEL_1 0x00000200U /*!< Trigger signal selection for launching injected conversions, Bit 1 */
<> 147:30b64687e01f 3565 #define DFSDM_FLTCR1_JEXTSEL_2 0x00000400U /*!< Trigger signal selection for launching injected conversions, Bit 2 */
<> 147:30b64687e01f 3566 #define DFSDM_FLTCR1_JEXTSEL_3 0x00000800U /*!< Trigger signal selection for launching injected conversions, Bit 3 */
<> 147:30b64687e01f 3567 #define DFSDM_FLTCR1_JEXTSEL_4 0x00001000U /*!< Trigger signal selection for launching injected conversions, Bit 4 */
<> 147:30b64687e01f 3568 #define DFSDM_FLTCR1_JDMAEN 0x00000020U /*!< DMA channel enabled to read data for the injected channel group */
<> 147:30b64687e01f 3569 #define DFSDM_FLTCR1_JSCAN 0x00000010U /*!< Scanning conversion in continuous mode selection for injected conversions */
<> 147:30b64687e01f 3570 #define DFSDM_FLTCR1_JSYNC 0x00000008U /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
<> 147:30b64687e01f 3571 #define DFSDM_FLTCR1_JSWSTART 0x00000002U /*!< Start the conversion of the injected group of channels */
<> 147:30b64687e01f 3572 #define DFSDM_FLTCR1_DFEN 0x00000001U /*!< DFSDM enable */
<> 147:30b64687e01f 3573
<> 147:30b64687e01f 3574 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
<> 147:30b64687e01f 3575 #define DFSDM_FLTCR2_AWDCH 0x00FF0000U /*!< AWDCH[7:0] Analog watchdog channel selection */
<> 147:30b64687e01f 3576 #define DFSDM_FLTCR2_EXCH 0x0000FF00U /*!< EXCH[7:0] Extreme detector channel selection */
<> 147:30b64687e01f 3577 #define DFSDM_FLTCR2_CKABIE 0x00000040U /*!< Clock absence interrupt enable */
<> 147:30b64687e01f 3578 #define DFSDM_FLTCR2_SCDIE 0x00000020U /*!< Short circuit detector interrupt enable */
<> 147:30b64687e01f 3579 #define DFSDM_FLTCR2_AWDIE 0x00000010U /*!< Analog watchdog interrupt enable */
<> 147:30b64687e01f 3580 #define DFSDM_FLTCR2_ROVRIE 0x00000008U /*!< Regular data overrun interrupt enable */
<> 147:30b64687e01f 3581 #define DFSDM_FLTCR2_JOVRIE 0x00000004U /*!< Injected data overrun interrupt enable */
<> 147:30b64687e01f 3582 #define DFSDM_FLTCR2_REOCIE 0x00000002U /*!< Regular end of conversion interrupt enable */
<> 147:30b64687e01f 3583 #define DFSDM_FLTCR2_JEOCIE 0x00000001U /*!< Injected end of conversion interrupt enable */
<> 147:30b64687e01f 3584
<> 147:30b64687e01f 3585 /******************** Bit definition for DFSDM_FLTISR register *******************/
<> 147:30b64687e01f 3586 #define DFSDM_FLTISR_SCDF 0xFF000000U /*!< SCDF[7:0] Short circuit detector flag */
<> 147:30b64687e01f 3587 #define DFSDM_FLTISR_CKABF 0x00FF0000U /*!< CKABF[7:0] Clock absence flag */
<> 147:30b64687e01f 3588 #define DFSDM_FLTISR_RCIP 0x00004000U /*!< Regular conversion in progress status */
<> 147:30b64687e01f 3589 #define DFSDM_FLTISR_JCIP 0x00002000U /*!< Injected conversion in progress status */
<> 147:30b64687e01f 3590 #define DFSDM_FLTISR_AWDF 0x00000010U /*!< Analog watchdog */
<> 147:30b64687e01f 3591 #define DFSDM_FLTISR_ROVRF 0x00000008U /*!< Regular conversion overrun flag */
<> 147:30b64687e01f 3592 #define DFSDM_FLTISR_JOVRF 0x00000004U /*!< Injected conversion overrun flag */
<> 147:30b64687e01f 3593 #define DFSDM_FLTISR_REOCF 0x00000002U /*!< End of regular conversion flag */
<> 147:30b64687e01f 3594 #define DFSDM_FLTISR_JEOCF 0x00000001U /*!< End of injected conversion flag */
<> 147:30b64687e01f 3595
<> 147:30b64687e01f 3596 /******************** Bit definition for DFSDM_FLTICR register *******************/
<> 147:30b64687e01f 3597 #define DFSDM_FLTICR_CLRSCSDF 0xFF000000U /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
<> 147:30b64687e01f 3598 #define DFSDM_FLTICR_CLRCKABF 0x00FF0000U /*!< CLRCKABF[7:0] Clear the clock absence flag */
<> 147:30b64687e01f 3599 #define DFSDM_FLTICR_CLRROVRF 0x00000008U /*!< Clear the regular conversion overrun flag */
<> 147:30b64687e01f 3600 #define DFSDM_FLTICR_CLRJOVRF 0x00000004U /*!< Clear the injected conversion overrun flag */
<> 147:30b64687e01f 3601
<> 147:30b64687e01f 3602 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
<> 147:30b64687e01f 3603 #define DFSDM_FLTJCHGR_JCHG 0x000000FFU /*!< JCHG[7:0] Injected channel group selection */
<> 147:30b64687e01f 3604
<> 147:30b64687e01f 3605 /******************** Bit definition for DFSDM_FLTFCR register *******************/
<> 147:30b64687e01f 3606 #define DFSDM_FLTFCR_FORD 0xE0000000U /*!< FORD[2:0] Sinc filter order */
<> 147:30b64687e01f 3607 #define DFSDM_FLTFCR_FORD_2 0x80000000U /*!< Sinc filter order, Bit 2 */
<> 147:30b64687e01f 3608 #define DFSDM_FLTFCR_FORD_1 0x40000000U /*!< Sinc filter order, Bit 1 */
<> 147:30b64687e01f 3609 #define DFSDM_FLTFCR_FORD_0 0x20000000U /*!< Sinc filter order, Bit 0 */
<> 147:30b64687e01f 3610 #define DFSDM_FLTFCR_FOSR 0x03FF0000U /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
<> 147:30b64687e01f 3611 #define DFSDM_FLTFCR_IOSR 0x000000FFU /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
<> 147:30b64687e01f 3612
<> 147:30b64687e01f 3613 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
<> 147:30b64687e01f 3614 #define DFSDM_FLTJDATAR_JDATA 0xFFFFFF00U /*!< JDATA[23:0] Injected group conversion data */
<> 147:30b64687e01f 3615 #define DFSDM_FLTJDATAR_JDATACH 0x00000007U /*!< JDATACH[2:0] Injected channel most recently converted */
<> 147:30b64687e01f 3616
<> 147:30b64687e01f 3617 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
<> 147:30b64687e01f 3618 #define DFSDM_FLTRDATAR_RDATA 0xFFFFFF00U /*!< RDATA[23:0] Regular channel conversion data */
<> 147:30b64687e01f 3619 #define DFSDM_FLTRDATAR_RPEND 0x00000010U /*!< RPEND Regular channel pending data */
<> 147:30b64687e01f 3620 #define DFSDM_FLTRDATAR_RDATACH 0x00000007U /*!< RDATACH[2:0] Regular channel most recently converted */
<> 147:30b64687e01f 3621
<> 147:30b64687e01f 3622 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
<> 147:30b64687e01f 3623 #define DFSDM_FLTAWHTR_AWHT 0xFFFFFF00U /*!< AWHT[23:0] Analog watchdog high threshold */
<> 147:30b64687e01f 3624 #define DFSDM_FLTAWHTR_BKAWH 0x0000000FU /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
<> 147:30b64687e01f 3625
<> 147:30b64687e01f 3626 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
<> 147:30b64687e01f 3627 #define DFSDM_FLTAWLTR_AWLT 0xFFFFFF00U /*!< AWLT[23:0] Analog watchdog low threshold */
<> 147:30b64687e01f 3628 #define DFSDM_FLTAWLTR_BKAWL 0x0000000FU /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
<> 147:30b64687e01f 3629
<> 147:30b64687e01f 3630 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
<> 147:30b64687e01f 3631 #define DFSDM_FLTAWSR_AWHTF 0x0000FF00U /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
<> 147:30b64687e01f 3632 #define DFSDM_FLTAWSR_AWLTF 0x000000FFU /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
<> 147:30b64687e01f 3633
<> 147:30b64687e01f 3634 /****************** Bit definition for DFSDM_FLTAWCFR register *****************/
<> 147:30b64687e01f 3635 #define DFSDM_FLTAWCFR_CLRAWHTF 0x0000FF00U /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
<> 147:30b64687e01f 3636 #define DFSDM_FLTAWCFR_CLRAWLTF 0x000000FFU /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
<> 147:30b64687e01f 3637
<> 147:30b64687e01f 3638 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
<> 147:30b64687e01f 3639 #define DFSDM_FLTEXMAX_EXMAX 0xFFFFFF00U /*!< EXMAX[23:0] Extreme detector maximum value */
<> 147:30b64687e01f 3640 #define DFSDM_FLTEXMAX_EXMAXCH 0x00000007U /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
<> 147:30b64687e01f 3641
<> 147:30b64687e01f 3642 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
<> 147:30b64687e01f 3643 #define DFSDM_FLTEXMIN_EXMIN 0xFFFFFF00U /*!< EXMIN[23:0] Extreme detector minimum value */
<> 147:30b64687e01f 3644 #define DFSDM_FLTEXMIN_EXMINCH 0x00000007U /*!< EXMINCH[2:0] Extreme detector minimum data channel */
<> 147:30b64687e01f 3645
<> 147:30b64687e01f 3646 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
<> 147:30b64687e01f 3647 #define DFSDM_FLTCNVTIMR_CNVCNT 0xFFFFFFF0U /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
<> 147:30b64687e01f 3648
<> 147:30b64687e01f 3649 /******************************************************************************/
<> 147:30b64687e01f 3650 /* */
<> 147:30b64687e01f 3651 /* Debug MCU */
<> 147:30b64687e01f 3652 /* */
<> 147:30b64687e01f 3653 /******************************************************************************/
<> 147:30b64687e01f 3654
<> 147:30b64687e01f 3655 /******************************************************************************/
<> 147:30b64687e01f 3656 /* */
<> 147:30b64687e01f 3657 /* DCMI */
<> 147:30b64687e01f 3658 /* */
<> 147:30b64687e01f 3659 /******************************************************************************/
<> 147:30b64687e01f 3660 /******************** Bits definition for DCMI_CR register ******************/
<> 147:30b64687e01f 3661 #define DCMI_CR_CAPTURE 0x00000001U
<> 147:30b64687e01f 3662 #define DCMI_CR_CM 0x00000002U
<> 147:30b64687e01f 3663 #define DCMI_CR_CROP 0x00000004U
<> 147:30b64687e01f 3664 #define DCMI_CR_JPEG 0x00000008U
<> 147:30b64687e01f 3665 #define DCMI_CR_ESS 0x00000010U
<> 147:30b64687e01f 3666 #define DCMI_CR_PCKPOL 0x00000020U
<> 147:30b64687e01f 3667 #define DCMI_CR_HSPOL 0x00000040U
<> 147:30b64687e01f 3668 #define DCMI_CR_VSPOL 0x00000080U
<> 147:30b64687e01f 3669 #define DCMI_CR_FCRC_0 0x00000100U
<> 147:30b64687e01f 3670 #define DCMI_CR_FCRC_1 0x00000200U
<> 147:30b64687e01f 3671 #define DCMI_CR_EDM_0 0x00000400U
<> 147:30b64687e01f 3672 #define DCMI_CR_EDM_1 0x00000800U
<> 147:30b64687e01f 3673 #define DCMI_CR_CRE 0x00001000U
<> 147:30b64687e01f 3674 #define DCMI_CR_ENABLE 0x00004000U
<> 147:30b64687e01f 3675 #define DCMI_CR_BSM 0x00030000U
<> 147:30b64687e01f 3676 #define DCMI_CR_BSM_0 0x00010000U
<> 147:30b64687e01f 3677 #define DCMI_CR_BSM_1 0x00020000U
<> 147:30b64687e01f 3678 #define DCMI_CR_OEBS 0x00040000U
<> 147:30b64687e01f 3679 #define DCMI_CR_LSM 0x00080000U
<> 147:30b64687e01f 3680 #define DCMI_CR_OELS 0x00100000U
<> 147:30b64687e01f 3681
<> 147:30b64687e01f 3682 /******************** Bits definition for DCMI_SR register ******************/
<> 147:30b64687e01f 3683 #define DCMI_SR_HSYNC 0x00000001U
<> 147:30b64687e01f 3684 #define DCMI_SR_VSYNC 0x00000002U
<> 147:30b64687e01f 3685 #define DCMI_SR_FNE 0x00000004U
<> 147:30b64687e01f 3686
<> 147:30b64687e01f 3687 /******************** Bits definition for DCMI_RIS register ****************/
<> 147:30b64687e01f 3688 #define DCMI_RIS_FRAME_RIS 0x00000001U
<> 147:30b64687e01f 3689 #define DCMI_RIS_OVR_RIS 0x00000002U
<> 147:30b64687e01f 3690 #define DCMI_RIS_ERR_RIS 0x00000004U
<> 147:30b64687e01f 3691 #define DCMI_RIS_VSYNC_RIS 0x00000008U
<> 147:30b64687e01f 3692 #define DCMI_RIS_LINE_RIS 0x00000010U
<> 147:30b64687e01f 3693
<> 147:30b64687e01f 3694 /* Legacy defines */
<> 147:30b64687e01f 3695 #define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
<> 147:30b64687e01f 3696 #define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
<> 147:30b64687e01f 3697 #define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
<> 147:30b64687e01f 3698 #define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
<> 147:30b64687e01f 3699 #define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
<> 147:30b64687e01f 3700
<> 147:30b64687e01f 3701 /******************** Bits definition for DCMI_IER register *****************/
<> 147:30b64687e01f 3702 #define DCMI_IER_FRAME_IE 0x00000001U
<> 147:30b64687e01f 3703 #define DCMI_IER_OVR_IE 0x00000002U
<> 147:30b64687e01f 3704 #define DCMI_IER_ERR_IE 0x00000004U
<> 147:30b64687e01f 3705 #define DCMI_IER_VSYNC_IE 0x00000008U
<> 147:30b64687e01f 3706 #define DCMI_IER_LINE_IE 0x00000010U
<> 147:30b64687e01f 3707
<> 147:30b64687e01f 3708
<> 147:30b64687e01f 3709 /******************** Bits definition for DCMI_MIS register *****************/
<> 147:30b64687e01f 3710 #define DCMI_MIS_FRAME_MIS 0x00000001U
<> 147:30b64687e01f 3711 #define DCMI_MIS_OVR_MIS 0x00000002U
<> 147:30b64687e01f 3712 #define DCMI_MIS_ERR_MIS 0x00000004U
<> 147:30b64687e01f 3713 #define DCMI_MIS_VSYNC_MIS 0x00000008U
<> 147:30b64687e01f 3714 #define DCMI_MIS_LINE_MIS 0x00000010U
<> 147:30b64687e01f 3715
<> 147:30b64687e01f 3716
<> 147:30b64687e01f 3717 /******************** Bits definition for DCMI_ICR register *****************/
<> 147:30b64687e01f 3718 #define DCMI_ICR_FRAME_ISC 0x00000001U
<> 147:30b64687e01f 3719 #define DCMI_ICR_OVR_ISC 0x00000002U
<> 147:30b64687e01f 3720 #define DCMI_ICR_ERR_ISC 0x00000004U
<> 147:30b64687e01f 3721 #define DCMI_ICR_VSYNC_ISC 0x00000008U
<> 147:30b64687e01f 3722 #define DCMI_ICR_LINE_ISC 0x00000010U
<> 147:30b64687e01f 3723
<> 147:30b64687e01f 3724
<> 147:30b64687e01f 3725 /******************** Bits definition for DCMI_ESCR register ******************/
<> 147:30b64687e01f 3726 #define DCMI_ESCR_FSC 0x000000FFU
<> 147:30b64687e01f 3727 #define DCMI_ESCR_LSC 0x0000FF00U
<> 147:30b64687e01f 3728 #define DCMI_ESCR_LEC 0x00FF0000U
<> 147:30b64687e01f 3729 #define DCMI_ESCR_FEC 0xFF000000U
<> 147:30b64687e01f 3730
<> 147:30b64687e01f 3731 /******************** Bits definition for DCMI_ESUR register ******************/
<> 147:30b64687e01f 3732 #define DCMI_ESUR_FSU 0x000000FFU
<> 147:30b64687e01f 3733 #define DCMI_ESUR_LSU 0x0000FF00U
<> 147:30b64687e01f 3734 #define DCMI_ESUR_LEU 0x00FF0000U
<> 147:30b64687e01f 3735 #define DCMI_ESUR_FEU 0xFF000000U
<> 147:30b64687e01f 3736
<> 147:30b64687e01f 3737 /******************** Bits definition for DCMI_CWSTRT register ******************/
<> 147:30b64687e01f 3738 #define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
<> 147:30b64687e01f 3739 #define DCMI_CWSTRT_VST 0x1FFF0000U
<> 147:30b64687e01f 3740
<> 147:30b64687e01f 3741 /******************** Bits definition for DCMI_CWSIZE register ******************/
<> 147:30b64687e01f 3742 #define DCMI_CWSIZE_CAPCNT 0x00003FFFU
<> 147:30b64687e01f 3743 #define DCMI_CWSIZE_VLINE 0x3FFF0000U
<> 147:30b64687e01f 3744
<> 147:30b64687e01f 3745 /******************** Bits definition for DCMI_DR register ******************/
<> 147:30b64687e01f 3746 #define DCMI_DR_BYTE0 0x000000FFU
<> 147:30b64687e01f 3747 #define DCMI_DR_BYTE1 0x0000FF00U
<> 147:30b64687e01f 3748 #define DCMI_DR_BYTE2 0x00FF0000U
<> 147:30b64687e01f 3749 #define DCMI_DR_BYTE3 0xFF000000U
<> 147:30b64687e01f 3750
<> 147:30b64687e01f 3751 /******************************************************************************/
<> 147:30b64687e01f 3752 /* */
<> 147:30b64687e01f 3753 /* DMA Controller */
<> 147:30b64687e01f 3754 /* */
<> 147:30b64687e01f 3755 /******************************************************************************/
<> 147:30b64687e01f 3756 /******************** Bits definition for DMA_SxCR register *****************/
<> 147:30b64687e01f 3757 #define DMA_SxCR_CHSEL 0x1E000000U
<> 147:30b64687e01f 3758 #define DMA_SxCR_CHSEL_0 0x02000000U
<> 147:30b64687e01f 3759 #define DMA_SxCR_CHSEL_1 0x04000000U
<> 147:30b64687e01f 3760 #define DMA_SxCR_CHSEL_2 0x08000000U
<> 147:30b64687e01f 3761 #define DMA_SxCR_CHSEL_3 0x10000000U
<> 147:30b64687e01f 3762 #define DMA_SxCR_MBURST 0x01800000U
<> 147:30b64687e01f 3763 #define DMA_SxCR_MBURST_0 0x00800000U
<> 147:30b64687e01f 3764 #define DMA_SxCR_MBURST_1 0x01000000U
<> 147:30b64687e01f 3765 #define DMA_SxCR_PBURST 0x00600000U
<> 147:30b64687e01f 3766 #define DMA_SxCR_PBURST_0 0x00200000U
<> 147:30b64687e01f 3767 #define DMA_SxCR_PBURST_1 0x00400000U
<> 147:30b64687e01f 3768 #define DMA_SxCR_CT 0x00080000U
<> 147:30b64687e01f 3769 #define DMA_SxCR_DBM 0x00040000U
<> 147:30b64687e01f 3770 #define DMA_SxCR_PL 0x00030000U
<> 147:30b64687e01f 3771 #define DMA_SxCR_PL_0 0x00010000U
<> 147:30b64687e01f 3772 #define DMA_SxCR_PL_1 0x00020000U
<> 147:30b64687e01f 3773 #define DMA_SxCR_PINCOS 0x00008000U
<> 147:30b64687e01f 3774 #define DMA_SxCR_MSIZE 0x00006000U
<> 147:30b64687e01f 3775 #define DMA_SxCR_MSIZE_0 0x00002000U
<> 147:30b64687e01f 3776 #define DMA_SxCR_MSIZE_1 0x00004000U
<> 147:30b64687e01f 3777 #define DMA_SxCR_PSIZE 0x00001800U
<> 147:30b64687e01f 3778 #define DMA_SxCR_PSIZE_0 0x00000800U
<> 147:30b64687e01f 3779 #define DMA_SxCR_PSIZE_1 0x00001000U
<> 147:30b64687e01f 3780 #define DMA_SxCR_MINC 0x00000400U
<> 147:30b64687e01f 3781 #define DMA_SxCR_PINC 0x00000200U
<> 147:30b64687e01f 3782 #define DMA_SxCR_CIRC 0x00000100U
<> 147:30b64687e01f 3783 #define DMA_SxCR_DIR 0x000000C0U
<> 147:30b64687e01f 3784 #define DMA_SxCR_DIR_0 0x00000040U
<> 147:30b64687e01f 3785 #define DMA_SxCR_DIR_1 0x00000080U
<> 147:30b64687e01f 3786 #define DMA_SxCR_PFCTRL 0x00000020U
<> 147:30b64687e01f 3787 #define DMA_SxCR_TCIE 0x00000010U
<> 147:30b64687e01f 3788 #define DMA_SxCR_HTIE 0x00000008U
<> 147:30b64687e01f 3789 #define DMA_SxCR_TEIE 0x00000004U
<> 147:30b64687e01f 3790 #define DMA_SxCR_DMEIE 0x00000002U
<> 147:30b64687e01f 3791 #define DMA_SxCR_EN 0x00000001U
<> 147:30b64687e01f 3792
<> 147:30b64687e01f 3793 /******************** Bits definition for DMA_SxCNDTR register **************/
<> 147:30b64687e01f 3794 #define DMA_SxNDT 0x0000FFFFU
<> 147:30b64687e01f 3795 #define DMA_SxNDT_0 0x00000001U
<> 147:30b64687e01f 3796 #define DMA_SxNDT_1 0x00000002U
<> 147:30b64687e01f 3797 #define DMA_SxNDT_2 0x00000004U
<> 147:30b64687e01f 3798 #define DMA_SxNDT_3 0x00000008U
<> 147:30b64687e01f 3799 #define DMA_SxNDT_4 0x00000010U
<> 147:30b64687e01f 3800 #define DMA_SxNDT_5 0x00000020U
<> 147:30b64687e01f 3801 #define DMA_SxNDT_6 0x00000040U
<> 147:30b64687e01f 3802 #define DMA_SxNDT_7 0x00000080U
<> 147:30b64687e01f 3803 #define DMA_SxNDT_8 0x00000100U
<> 147:30b64687e01f 3804 #define DMA_SxNDT_9 0x00000200U
<> 147:30b64687e01f 3805 #define DMA_SxNDT_10 0x00000400U
<> 147:30b64687e01f 3806 #define DMA_SxNDT_11 0x00000800U
<> 147:30b64687e01f 3807 #define DMA_SxNDT_12 0x00001000U
<> 147:30b64687e01f 3808 #define DMA_SxNDT_13 0x00002000U
<> 147:30b64687e01f 3809 #define DMA_SxNDT_14 0x00004000U
<> 147:30b64687e01f 3810 #define DMA_SxNDT_15 0x00008000U
<> 147:30b64687e01f 3811
<> 147:30b64687e01f 3812 /******************** Bits definition for DMA_SxFCR register ****************/
<> 147:30b64687e01f 3813 #define DMA_SxFCR_FEIE 0x00000080U
<> 147:30b64687e01f 3814 #define DMA_SxFCR_FS 0x00000038U
<> 147:30b64687e01f 3815 #define DMA_SxFCR_FS_0 0x00000008U
<> 147:30b64687e01f 3816 #define DMA_SxFCR_FS_1 0x00000010U
<> 147:30b64687e01f 3817 #define DMA_SxFCR_FS_2 0x00000020U
<> 147:30b64687e01f 3818 #define DMA_SxFCR_DMDIS 0x00000004U
<> 147:30b64687e01f 3819 #define DMA_SxFCR_FTH 0x00000003U
<> 147:30b64687e01f 3820 #define DMA_SxFCR_FTH_0 0x00000001U
<> 147:30b64687e01f 3821 #define DMA_SxFCR_FTH_1 0x00000002U
<> 147:30b64687e01f 3822
<> 147:30b64687e01f 3823 /******************** Bits definition for DMA_LISR register *****************/
<> 147:30b64687e01f 3824 #define DMA_LISR_TCIF3 0x08000000U
<> 147:30b64687e01f 3825 #define DMA_LISR_HTIF3 0x04000000U
<> 147:30b64687e01f 3826 #define DMA_LISR_TEIF3 0x02000000U
<> 147:30b64687e01f 3827 #define DMA_LISR_DMEIF3 0x01000000U
<> 147:30b64687e01f 3828 #define DMA_LISR_FEIF3 0x00400000U
<> 147:30b64687e01f 3829 #define DMA_LISR_TCIF2 0x00200000U
<> 147:30b64687e01f 3830 #define DMA_LISR_HTIF2 0x00100000U
<> 147:30b64687e01f 3831 #define DMA_LISR_TEIF2 0x00080000U
<> 147:30b64687e01f 3832 #define DMA_LISR_DMEIF2 0x00040000U
<> 147:30b64687e01f 3833 #define DMA_LISR_FEIF2 0x00010000U
<> 147:30b64687e01f 3834 #define DMA_LISR_TCIF1 0x00000800U
<> 147:30b64687e01f 3835 #define DMA_LISR_HTIF1 0x00000400U
<> 147:30b64687e01f 3836 #define DMA_LISR_TEIF1 0x00000200U
<> 147:30b64687e01f 3837 #define DMA_LISR_DMEIF1 0x00000100U
<> 147:30b64687e01f 3838 #define DMA_LISR_FEIF1 0x00000040U
<> 147:30b64687e01f 3839 #define DMA_LISR_TCIF0 0x00000020U
<> 147:30b64687e01f 3840 #define DMA_LISR_HTIF0 0x00000010U
<> 147:30b64687e01f 3841 #define DMA_LISR_TEIF0 0x00000008U
<> 147:30b64687e01f 3842 #define DMA_LISR_DMEIF0 0x00000004U
<> 147:30b64687e01f 3843 #define DMA_LISR_FEIF0 0x00000001U
<> 147:30b64687e01f 3844
<> 147:30b64687e01f 3845 /******************** Bits definition for DMA_HISR register *****************/
<> 147:30b64687e01f 3846 #define DMA_HISR_TCIF7 0x08000000U
<> 147:30b64687e01f 3847 #define DMA_HISR_HTIF7 0x04000000U
<> 147:30b64687e01f 3848 #define DMA_HISR_TEIF7 0x02000000U
<> 147:30b64687e01f 3849 #define DMA_HISR_DMEIF7 0x01000000U
<> 147:30b64687e01f 3850 #define DMA_HISR_FEIF7 0x00400000U
<> 147:30b64687e01f 3851 #define DMA_HISR_TCIF6 0x00200000U
<> 147:30b64687e01f 3852 #define DMA_HISR_HTIF6 0x00100000U
<> 147:30b64687e01f 3853 #define DMA_HISR_TEIF6 0x00080000U
<> 147:30b64687e01f 3854 #define DMA_HISR_DMEIF6 0x00040000U
<> 147:30b64687e01f 3855 #define DMA_HISR_FEIF6 0x00010000U
<> 147:30b64687e01f 3856 #define DMA_HISR_TCIF5 0x00000800U
<> 147:30b64687e01f 3857 #define DMA_HISR_HTIF5 0x00000400U
<> 147:30b64687e01f 3858 #define DMA_HISR_TEIF5 0x00000200U
<> 147:30b64687e01f 3859 #define DMA_HISR_DMEIF5 0x00000100U
<> 147:30b64687e01f 3860 #define DMA_HISR_FEIF5 0x00000040U
<> 147:30b64687e01f 3861 #define DMA_HISR_TCIF4 0x00000020U
<> 147:30b64687e01f 3862 #define DMA_HISR_HTIF4 0x00000010U
<> 147:30b64687e01f 3863 #define DMA_HISR_TEIF4 0x00000008U
<> 147:30b64687e01f 3864 #define DMA_HISR_DMEIF4 0x00000004U
<> 147:30b64687e01f 3865 #define DMA_HISR_FEIF4 0x00000001U
<> 147:30b64687e01f 3866
<> 147:30b64687e01f 3867 /******************** Bits definition for DMA_LIFCR register ****************/
<> 147:30b64687e01f 3868 #define DMA_LIFCR_CTCIF3 0x08000000U
<> 147:30b64687e01f 3869 #define DMA_LIFCR_CHTIF3 0x04000000U
<> 147:30b64687e01f 3870 #define DMA_LIFCR_CTEIF3 0x02000000U
<> 147:30b64687e01f 3871 #define DMA_LIFCR_CDMEIF3 0x01000000U
<> 147:30b64687e01f 3872 #define DMA_LIFCR_CFEIF3 0x00400000U
<> 147:30b64687e01f 3873 #define DMA_LIFCR_CTCIF2 0x00200000U
<> 147:30b64687e01f 3874 #define DMA_LIFCR_CHTIF2 0x00100000U
<> 147:30b64687e01f 3875 #define DMA_LIFCR_CTEIF2 0x00080000U
<> 147:30b64687e01f 3876 #define DMA_LIFCR_CDMEIF2 0x00040000U
<> 147:30b64687e01f 3877 #define DMA_LIFCR_CFEIF2 0x00010000U
<> 147:30b64687e01f 3878 #define DMA_LIFCR_CTCIF1 0x00000800U
<> 147:30b64687e01f 3879 #define DMA_LIFCR_CHTIF1 0x00000400U
<> 147:30b64687e01f 3880 #define DMA_LIFCR_CTEIF1 0x00000200U
<> 147:30b64687e01f 3881 #define DMA_LIFCR_CDMEIF1 0x00000100U
<> 147:30b64687e01f 3882 #define DMA_LIFCR_CFEIF1 0x00000040U
<> 147:30b64687e01f 3883 #define DMA_LIFCR_CTCIF0 0x00000020U
<> 147:30b64687e01f 3884 #define DMA_LIFCR_CHTIF0 0x00000010U
<> 147:30b64687e01f 3885 #define DMA_LIFCR_CTEIF0 0x00000008U
<> 147:30b64687e01f 3886 #define DMA_LIFCR_CDMEIF0 0x00000004U
<> 147:30b64687e01f 3887 #define DMA_LIFCR_CFEIF0 0x00000001U
<> 147:30b64687e01f 3888
<> 147:30b64687e01f 3889 /******************** Bits definition for DMA_HIFCR register ****************/
<> 147:30b64687e01f 3890 #define DMA_HIFCR_CTCIF7 0x08000000U
<> 147:30b64687e01f 3891 #define DMA_HIFCR_CHTIF7 0x04000000U
<> 147:30b64687e01f 3892 #define DMA_HIFCR_CTEIF7 0x02000000U
<> 147:30b64687e01f 3893 #define DMA_HIFCR_CDMEIF7 0x01000000U
<> 147:30b64687e01f 3894 #define DMA_HIFCR_CFEIF7 0x00400000U
<> 147:30b64687e01f 3895 #define DMA_HIFCR_CTCIF6 0x00200000U
<> 147:30b64687e01f 3896 #define DMA_HIFCR_CHTIF6 0x00100000U
<> 147:30b64687e01f 3897 #define DMA_HIFCR_CTEIF6 0x00080000U
<> 147:30b64687e01f 3898 #define DMA_HIFCR_CDMEIF6 0x00040000U
<> 147:30b64687e01f 3899 #define DMA_HIFCR_CFEIF6 0x00010000U
<> 147:30b64687e01f 3900 #define DMA_HIFCR_CTCIF5 0x00000800U
<> 147:30b64687e01f 3901 #define DMA_HIFCR_CHTIF5 0x00000400U
<> 147:30b64687e01f 3902 #define DMA_HIFCR_CTEIF5 0x00000200U
<> 147:30b64687e01f 3903 #define DMA_HIFCR_CDMEIF5 0x00000100U
<> 147:30b64687e01f 3904 #define DMA_HIFCR_CFEIF5 0x00000040U
<> 147:30b64687e01f 3905 #define DMA_HIFCR_CTCIF4 0x00000020U
<> 147:30b64687e01f 3906 #define DMA_HIFCR_CHTIF4 0x00000010U
<> 147:30b64687e01f 3907 #define DMA_HIFCR_CTEIF4 0x00000008U
<> 147:30b64687e01f 3908 #define DMA_HIFCR_CDMEIF4 0x00000004U
<> 147:30b64687e01f 3909 #define DMA_HIFCR_CFEIF4 0x00000001U
<> 147:30b64687e01f 3910
<> 147:30b64687e01f 3911 /******************************************************************************/
<> 147:30b64687e01f 3912 /* */
<> 147:30b64687e01f 3913 /* AHB Master DMA2D Controller (DMA2D) */
<> 147:30b64687e01f 3914 /* */
<> 147:30b64687e01f 3915 /******************************************************************************/
<> 147:30b64687e01f 3916
<> 147:30b64687e01f 3917 /******************** Bit definition for DMA2D_CR register ******************/
<> 147:30b64687e01f 3918
<> 147:30b64687e01f 3919 #define DMA2D_CR_START 0x00000001U /*!< Start transfer */
<> 147:30b64687e01f 3920 #define DMA2D_CR_SUSP 0x00000002U /*!< Suspend transfer */
<> 147:30b64687e01f 3921 #define DMA2D_CR_ABORT 0x00000004U /*!< Abort transfer */
<> 147:30b64687e01f 3922 #define DMA2D_CR_TEIE 0x00000100U /*!< Transfer Error Interrupt Enable */
<> 147:30b64687e01f 3923 #define DMA2D_CR_TCIE 0x00000200U /*!< Transfer Complete Interrupt Enable */
<> 147:30b64687e01f 3924 #define DMA2D_CR_TWIE 0x00000400U /*!< Transfer Watermark Interrupt Enable */
<> 147:30b64687e01f 3925 #define DMA2D_CR_CAEIE 0x00000800U /*!< CLUT Access Error Interrupt Enable */
<> 147:30b64687e01f 3926 #define DMA2D_CR_CTCIE 0x00001000U /*!< CLUT Transfer Complete Interrupt Enable */
<> 147:30b64687e01f 3927 #define DMA2D_CR_CEIE 0x00002000U /*!< Configuration Error Interrupt Enable */
<> 147:30b64687e01f 3928 #define DMA2D_CR_MODE 0x00030000U /*!< DMA2D Mode[1:0] */
<> 147:30b64687e01f 3929 #define DMA2D_CR_MODE_0 0x00010000U /*!< DMA2D Mode bit 0 */
<> 147:30b64687e01f 3930 #define DMA2D_CR_MODE_1 0x00020000U /*!< DMA2D Mode bit 1 */
<> 147:30b64687e01f 3931
<> 147:30b64687e01f 3932 /******************** Bit definition for DMA2D_ISR register *****************/
<> 147:30b64687e01f 3933
<> 147:30b64687e01f 3934 #define DMA2D_ISR_TEIF 0x00000001U /*!< Transfer Error Interrupt Flag */
<> 147:30b64687e01f 3935 #define DMA2D_ISR_TCIF 0x00000002U /*!< Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3936 #define DMA2D_ISR_TWIF 0x00000004U /*!< Transfer Watermark Interrupt Flag */
<> 147:30b64687e01f 3937 #define DMA2D_ISR_CAEIF 0x00000008U /*!< CLUT Access Error Interrupt Flag */
<> 147:30b64687e01f 3938 #define DMA2D_ISR_CTCIF 0x00000010U /*!< CLUT Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3939 #define DMA2D_ISR_CEIF 0x00000020U /*!< Configuration Error Interrupt Flag */
<> 147:30b64687e01f 3940
<> 147:30b64687e01f 3941 /******************** Bit definition for DMA2D_IFCR register ****************/
<> 147:30b64687e01f 3942
<> 147:30b64687e01f 3943 #define DMA2D_IFCR_CTEIF 0x00000001U /*!< Clears Transfer Error Interrupt Flag */
<> 147:30b64687e01f 3944 #define DMA2D_IFCR_CTCIF 0x00000002U /*!< Clears Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3945 #define DMA2D_IFCR_CTWIF 0x00000004U /*!< Clears Transfer Watermark Interrupt Flag */
<> 147:30b64687e01f 3946 #define DMA2D_IFCR_CAECIF 0x00000008U /*!< Clears CLUT Access Error Interrupt Flag */
<> 147:30b64687e01f 3947 #define DMA2D_IFCR_CCTCIF 0x00000010U /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3948 #define DMA2D_IFCR_CCEIF 0x00000020U /*!< Clears Configuration Error Interrupt Flag */
<> 147:30b64687e01f 3949
<> 147:30b64687e01f 3950 /* Legacy defines */
<> 147:30b64687e01f 3951 #define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /*!< Clears Transfer Error Interrupt Flag */
<> 147:30b64687e01f 3952 #define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /*!< Clears Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3953 #define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /*!< Clears Transfer Watermark Interrupt Flag */
<> 147:30b64687e01f 3954 #define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /*!< Clears CLUT Access Error Interrupt Flag */
<> 147:30b64687e01f 3955 #define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /*!< Clears CLUT Transfer Complete Interrupt Flag */
<> 147:30b64687e01f 3956 #define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /*!< Clears Configuration Error Interrupt Flag */
<> 147:30b64687e01f 3957
<> 147:30b64687e01f 3958 /******************** Bit definition for DMA2D_FGMAR register ***************/
<> 147:30b64687e01f 3959
<> 147:30b64687e01f 3960 #define DMA2D_FGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
<> 147:30b64687e01f 3961
<> 147:30b64687e01f 3962 /******************** Bit definition for DMA2D_FGOR register ****************/
<> 147:30b64687e01f 3963
<> 147:30b64687e01f 3964 #define DMA2D_FGOR_LO 0x00003FFFU /*!< Line Offset */
<> 147:30b64687e01f 3965
<> 147:30b64687e01f 3966 /******************** Bit definition for DMA2D_BGMAR register ***************/
<> 147:30b64687e01f 3967
<> 147:30b64687e01f 3968 #define DMA2D_BGMAR_MA 0xFFFFFFFFU /*!< Memory Address */
<> 147:30b64687e01f 3969
<> 147:30b64687e01f 3970 /******************** Bit definition for DMA2D_BGOR register ****************/
<> 147:30b64687e01f 3971
<> 147:30b64687e01f 3972 #define DMA2D_BGOR_LO 0x00003FFFU /*!< Line Offset */
<> 147:30b64687e01f 3973
<> 147:30b64687e01f 3974 /******************** Bit definition for DMA2D_FGPFCCR register *************/
<> 147:30b64687e01f 3975
<> 147:30b64687e01f 3976 #define DMA2D_FGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
<> 147:30b64687e01f 3977 #define DMA2D_FGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
<> 147:30b64687e01f 3978 #define DMA2D_FGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
<> 147:30b64687e01f 3979 #define DMA2D_FGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
<> 147:30b64687e01f 3980 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
<> 147:30b64687e01f 3981 #define DMA2D_FGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
<> 147:30b64687e01f 3982 #define DMA2D_FGPFCCR_START 0x00000020U /*!< Start */
<> 147:30b64687e01f 3983 #define DMA2D_FGPFCCR_CS 0x0000FF00U /*!< CLUT size */
<> 147:30b64687e01f 3984 #define DMA2D_FGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
<> 147:30b64687e01f 3985 #define DMA2D_FGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
<> 147:30b64687e01f 3986 #define DMA2D_FGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
<> 147:30b64687e01f 3987 #define DMA2D_FGPFCCR_AI 0x00100000U /*!< Foreground Input Alpha Inverted */
<> 147:30b64687e01f 3988 #define DMA2D_FGPFCCR_RBS 0x00200000U /*!< Foreground Input Red Blue Swap */
<> 147:30b64687e01f 3989 #define DMA2D_FGPFCCR_ALPHA 0xFF000000U /*!< Alpha value */
<> 147:30b64687e01f 3990
<> 147:30b64687e01f 3991 /******************** Bit definition for DMA2D_FGCOLR register **************/
<> 147:30b64687e01f 3992
<> 147:30b64687e01f 3993 #define DMA2D_FGCOLR_BLUE 0x000000FFU /*!< Blue Value */
<> 147:30b64687e01f 3994 #define DMA2D_FGCOLR_GREEN 0x0000FF00U /*!< Green Value */
<> 147:30b64687e01f 3995 #define DMA2D_FGCOLR_RED 0x00FF0000U /*!< Red Value */
<> 147:30b64687e01f 3996
<> 147:30b64687e01f 3997 /******************** Bit definition for DMA2D_BGPFCCR register *************/
<> 147:30b64687e01f 3998
<> 147:30b64687e01f 3999 #define DMA2D_BGPFCCR_CM 0x0000000FU /*!< Input color mode CM[3:0] */
<> 147:30b64687e01f 4000 #define DMA2D_BGPFCCR_CM_0 0x00000001U /*!< Input color mode CM bit 0 */
<> 147:30b64687e01f 4001 #define DMA2D_BGPFCCR_CM_1 0x00000002U /*!< Input color mode CM bit 1 */
<> 147:30b64687e01f 4002 #define DMA2D_BGPFCCR_CM_2 0x00000004U /*!< Input color mode CM bit 2 */
<> 147:30b64687e01f 4003 #define DMA2D_FGPFCCR_CM_3 0x00000008U /*!< Input color mode CM bit 3 */
<> 147:30b64687e01f 4004 #define DMA2D_BGPFCCR_CCM 0x00000010U /*!< CLUT Color mode */
<> 147:30b64687e01f 4005 #define DMA2D_BGPFCCR_START 0x00000020U /*!< Start */
<> 147:30b64687e01f 4006 #define DMA2D_BGPFCCR_CS 0x0000FF00U /*!< CLUT size */
<> 147:30b64687e01f 4007 #define DMA2D_BGPFCCR_AM 0x00030000U /*!< Alpha mode AM[1:0] */
<> 147:30b64687e01f 4008 #define DMA2D_BGPFCCR_AM_0 0x00010000U /*!< Alpha mode AM bit 0 */
<> 147:30b64687e01f 4009 #define DMA2D_BGPFCCR_AM_1 0x00020000U /*!< Alpha mode AM bit 1 */
<> 147:30b64687e01f 4010 #define DMA2D_BGPFCCR_AI 0x00100000U /*!< background Input Alpha Inverted */
<> 147:30b64687e01f 4011 #define DMA2D_BGPFCCR_RBS 0x00200000U /*!< Background Input Red Blue Swap */
<> 147:30b64687e01f 4012 #define DMA2D_BGPFCCR_ALPHA 0xFF000000U /*!< background Input Alpha value */
<> 147:30b64687e01f 4013
<> 147:30b64687e01f 4014 /******************** Bit definition for DMA2D_BGCOLR register **************/
<> 147:30b64687e01f 4015
<> 147:30b64687e01f 4016 #define DMA2D_BGCOLR_BLUE 0x000000FFU /*!< Blue Value */
<> 147:30b64687e01f 4017 #define DMA2D_BGCOLR_GREEN 0x0000FF00U /*!< Green Value */
<> 147:30b64687e01f 4018 #define DMA2D_BGCOLR_RED 0x00FF0000U /*!< Red Value */
<> 147:30b64687e01f 4019
<> 147:30b64687e01f 4020 /******************** Bit definition for DMA2D_FGCMAR register **************/
<> 147:30b64687e01f 4021
<> 147:30b64687e01f 4022 #define DMA2D_FGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
<> 147:30b64687e01f 4023
<> 147:30b64687e01f 4024 /******************** Bit definition for DMA2D_BGCMAR register **************/
<> 147:30b64687e01f 4025
<> 147:30b64687e01f 4026 #define DMA2D_BGCMAR_MA 0xFFFFFFFFU /*!< Memory Address */
<> 147:30b64687e01f 4027
<> 147:30b64687e01f 4028 /******************** Bit definition for DMA2D_OPFCCR register **************/
<> 147:30b64687e01f 4029
<> 147:30b64687e01f 4030 #define DMA2D_OPFCCR_CM 0x00000007U /*!< Color mode CM[2:0] */
<> 147:30b64687e01f 4031 #define DMA2D_OPFCCR_CM_0 0x00000001U /*!< Color mode CM bit 0 */
<> 147:30b64687e01f 4032 #define DMA2D_OPFCCR_CM_1 0x00000002U /*!< Color mode CM bit 1 */
<> 147:30b64687e01f 4033 #define DMA2D_OPFCCR_CM_2 0x00000004U /*!< Color mode CM bit 2 */
<> 147:30b64687e01f 4034 #define DMA2D_OPFCCR_AI 0x00100000U /*!< Output Alpha Inverted */
<> 147:30b64687e01f 4035 #define DMA2D_OPFCCR_RBS 0x00200000U /*!< Output Red Blue Swap */
<> 147:30b64687e01f 4036
<> 147:30b64687e01f 4037 /******************** Bit definition for DMA2D_OCOLR register ***************/
<> 147:30b64687e01f 4038
<> 147:30b64687e01f 4039 /*!<Mode_ARGB8888/RGB888 */
<> 147:30b64687e01f 4040
<> 147:30b64687e01f 4041 #define DMA2D_OCOLR_BLUE_1 0x000000FFU /*!< BLUE Value */
<> 147:30b64687e01f 4042 #define DMA2D_OCOLR_GREEN_1 0x0000FF00U /*!< GREEN Value */
<> 147:30b64687e01f 4043 #define DMA2D_OCOLR_RED_1 0x00FF0000U /*!< Red Value */
<> 147:30b64687e01f 4044 #define DMA2D_OCOLR_ALPHA_1 0xFF000000U /*!< Alpha Channel Value */
<> 147:30b64687e01f 4045
<> 147:30b64687e01f 4046 /*!<Mode_RGB565 */
<> 147:30b64687e01f 4047 #define DMA2D_OCOLR_BLUE_2 0x0000001FU /*!< BLUE Value */
<> 147:30b64687e01f 4048 #define DMA2D_OCOLR_GREEN_2 0x000007E0U /*!< GREEN Value */
<> 147:30b64687e01f 4049 #define DMA2D_OCOLR_RED_2 0x0000F800U /*!< Red Value */
<> 147:30b64687e01f 4050
<> 147:30b64687e01f 4051 /*!<Mode_ARGB1555 */
<> 147:30b64687e01f 4052 #define DMA2D_OCOLR_BLUE_3 0x0000001FU /*!< BLUE Value */
<> 147:30b64687e01f 4053 #define DMA2D_OCOLR_GREEN_3 0x000003E0U /*!< GREEN Value */
<> 147:30b64687e01f 4054 #define DMA2D_OCOLR_RED_3 0x00007C00U /*!< Red Value */
<> 147:30b64687e01f 4055 #define DMA2D_OCOLR_ALPHA_3 0x00008000U /*!< Alpha Channel Value */
<> 147:30b64687e01f 4056
<> 147:30b64687e01f 4057 /*!<Mode_ARGB4444 */
<> 147:30b64687e01f 4058 #define DMA2D_OCOLR_BLUE_4 0x0000000FU /*!< BLUE Value */
<> 147:30b64687e01f 4059 #define DMA2D_OCOLR_GREEN_4 0x000000F0U /*!< GREEN Value */
<> 147:30b64687e01f 4060 #define DMA2D_OCOLR_RED_4 0x00000F00U /*!< Red Value */
<> 147:30b64687e01f 4061 #define DMA2D_OCOLR_ALPHA_4 0x0000F000U /*!< Alpha Channel Value */
<> 147:30b64687e01f 4062
<> 147:30b64687e01f 4063 /******************** Bit definition for DMA2D_OMAR register ****************/
<> 147:30b64687e01f 4064
<> 147:30b64687e01f 4065 #define DMA2D_OMAR_MA 0xFFFFFFFFU /*!< Memory Address */
<> 147:30b64687e01f 4066
<> 147:30b64687e01f 4067 /******************** Bit definition for DMA2D_OOR register *****************/
<> 147:30b64687e01f 4068
<> 147:30b64687e01f 4069 #define DMA2D_OOR_LO 0x00003FFFU /*!< Line Offset */
<> 147:30b64687e01f 4070
<> 147:30b64687e01f 4071 /******************** Bit definition for DMA2D_NLR register *****************/
<> 147:30b64687e01f 4072
<> 147:30b64687e01f 4073 #define DMA2D_NLR_NL 0x0000FFFFU /*!< Number of Lines */
<> 147:30b64687e01f 4074 #define DMA2D_NLR_PL 0x3FFF0000U /*!< Pixel per Lines */
<> 147:30b64687e01f 4075
<> 147:30b64687e01f 4076 /******************** Bit definition for DMA2D_LWR register *****************/
<> 147:30b64687e01f 4077
<> 147:30b64687e01f 4078 #define DMA2D_LWR_LW 0x0000FFFFU /*!< Line Watermark */
<> 147:30b64687e01f 4079
<> 147:30b64687e01f 4080 /******************** Bit definition for DMA2D_AMTCR register ***************/
<> 147:30b64687e01f 4081
<> 147:30b64687e01f 4082 #define DMA2D_AMTCR_EN 0x00000001U /*!< Enable */
<> 147:30b64687e01f 4083 #define DMA2D_AMTCR_DT 0x0000FF00U /*!< Dead Time */
<> 147:30b64687e01f 4084
<> 147:30b64687e01f 4085
<> 147:30b64687e01f 4086 /******************** Bit definition for DMA2D_FGCLUT register **************/
<> 147:30b64687e01f 4087
<> 147:30b64687e01f 4088 /******************** Bit definition for DMA2D_BGCLUT register **************/
<> 147:30b64687e01f 4089
<> 147:30b64687e01f 4090 /******************************************************************************/
<> 147:30b64687e01f 4091 /* */
<> 147:30b64687e01f 4092 /* External Interrupt/Event Controller */
<> 147:30b64687e01f 4093 /* */
<> 147:30b64687e01f 4094 /******************************************************************************/
<> 147:30b64687e01f 4095 /******************* Bit definition for EXTI_IMR register *******************/
<> 147:30b64687e01f 4096 #define EXTI_IMR_MR0 0x00000001U /*!< Interrupt Mask on line 0 */
<> 147:30b64687e01f 4097 #define EXTI_IMR_MR1 0x00000002U /*!< Interrupt Mask on line 1 */
<> 147:30b64687e01f 4098 #define EXTI_IMR_MR2 0x00000004U /*!< Interrupt Mask on line 2 */
<> 147:30b64687e01f 4099 #define EXTI_IMR_MR3 0x00000008U /*!< Interrupt Mask on line 3 */
<> 147:30b64687e01f 4100 #define EXTI_IMR_MR4 0x00000010U /*!< Interrupt Mask on line 4 */
<> 147:30b64687e01f 4101 #define EXTI_IMR_MR5 0x00000020U /*!< Interrupt Mask on line 5 */
<> 147:30b64687e01f 4102 #define EXTI_IMR_MR6 0x00000040U /*!< Interrupt Mask on line 6 */
<> 147:30b64687e01f 4103 #define EXTI_IMR_MR7 0x00000080U /*!< Interrupt Mask on line 7 */
<> 147:30b64687e01f 4104 #define EXTI_IMR_MR8 0x00000100U /*!< Interrupt Mask on line 8 */
<> 147:30b64687e01f 4105 #define EXTI_IMR_MR9 0x00000200U /*!< Interrupt Mask on line 9 */
<> 147:30b64687e01f 4106 #define EXTI_IMR_MR10 0x00000400U /*!< Interrupt Mask on line 10 */
<> 147:30b64687e01f 4107 #define EXTI_IMR_MR11 0x00000800U /*!< Interrupt Mask on line 11 */
<> 147:30b64687e01f 4108 #define EXTI_IMR_MR12 0x00001000U /*!< Interrupt Mask on line 12 */
<> 147:30b64687e01f 4109 #define EXTI_IMR_MR13 0x00002000U /*!< Interrupt Mask on line 13 */
<> 147:30b64687e01f 4110 #define EXTI_IMR_MR14 0x00004000U /*!< Interrupt Mask on line 14 */
<> 147:30b64687e01f 4111 #define EXTI_IMR_MR15 0x00008000U /*!< Interrupt Mask on line 15 */
<> 147:30b64687e01f 4112 #define EXTI_IMR_MR16 0x00010000U /*!< Interrupt Mask on line 16 */
<> 147:30b64687e01f 4113 #define EXTI_IMR_MR17 0x00020000U /*!< Interrupt Mask on line 17 */
<> 147:30b64687e01f 4114 #define EXTI_IMR_MR18 0x00040000U /*!< Interrupt Mask on line 18 */
<> 147:30b64687e01f 4115 #define EXTI_IMR_MR19 0x00080000U /*!< Interrupt Mask on line 19 */
<> 147:30b64687e01f 4116 #define EXTI_IMR_MR20 0x00100000U /*!< Interrupt Mask on line 20 */
<> 147:30b64687e01f 4117 #define EXTI_IMR_MR21 0x00200000U /*!< Interrupt Mask on line 21 */
<> 147:30b64687e01f 4118 #define EXTI_IMR_MR22 0x00400000U /*!< Interrupt Mask on line 22 */
<> 147:30b64687e01f 4119 #define EXTI_IMR_MR23 0x00800000U /*!< Interrupt Mask on line 23 */
<> 147:30b64687e01f 4120 #define EXTI_IMR_MR24 0x01000000U /*!< Interrupt Mask on line 24 */
<> 147:30b64687e01f 4121
<> 147:30b64687e01f 4122 /* Reference Defines */
<> 147:30b64687e01f 4123 #define EXTI_IMR_IM0 EXTI_IMR_MR0
<> 147:30b64687e01f 4124 #define EXTI_IMR_IM1 EXTI_IMR_MR1
<> 147:30b64687e01f 4125 #define EXTI_IMR_IM2 EXTI_IMR_MR2
<> 147:30b64687e01f 4126 #define EXTI_IMR_IM3 EXTI_IMR_MR3
<> 147:30b64687e01f 4127 #define EXTI_IMR_IM4 EXTI_IMR_MR4
<> 147:30b64687e01f 4128 #define EXTI_IMR_IM5 EXTI_IMR_MR5
<> 147:30b64687e01f 4129 #define EXTI_IMR_IM6 EXTI_IMR_MR6
<> 147:30b64687e01f 4130 #define EXTI_IMR_IM7 EXTI_IMR_MR7
<> 147:30b64687e01f 4131 #define EXTI_IMR_IM8 EXTI_IMR_MR8
<> 147:30b64687e01f 4132 #define EXTI_IMR_IM9 EXTI_IMR_MR9
<> 147:30b64687e01f 4133 #define EXTI_IMR_IM10 EXTI_IMR_MR10
<> 147:30b64687e01f 4134 #define EXTI_IMR_IM11 EXTI_IMR_MR11
<> 147:30b64687e01f 4135 #define EXTI_IMR_IM12 EXTI_IMR_MR12
<> 147:30b64687e01f 4136 #define EXTI_IMR_IM13 EXTI_IMR_MR13
<> 147:30b64687e01f 4137 #define EXTI_IMR_IM14 EXTI_IMR_MR14
<> 147:30b64687e01f 4138 #define EXTI_IMR_IM15 EXTI_IMR_MR15
<> 147:30b64687e01f 4139 #define EXTI_IMR_IM16 EXTI_IMR_MR16
<> 147:30b64687e01f 4140 #define EXTI_IMR_IM17 EXTI_IMR_MR17
<> 147:30b64687e01f 4141 #define EXTI_IMR_IM18 EXTI_IMR_MR18
<> 147:30b64687e01f 4142 #define EXTI_IMR_IM19 EXTI_IMR_MR19
<> 147:30b64687e01f 4143 #define EXTI_IMR_IM20 EXTI_IMR_MR20
<> 147:30b64687e01f 4144 #define EXTI_IMR_IM21 EXTI_IMR_MR21
<> 147:30b64687e01f 4145 #define EXTI_IMR_IM22 EXTI_IMR_MR22
<> 147:30b64687e01f 4146 #define EXTI_IMR_IM23 EXTI_IMR_MR23
<> 147:30b64687e01f 4147 #define EXTI_IMR_IM24 EXTI_IMR_MR24
<> 147:30b64687e01f 4148
<> 147:30b64687e01f 4149 #define EXTI_IMR_IM 0x01FFFFFFU /*!< Interrupt Mask All */
<> 147:30b64687e01f 4150
<> 147:30b64687e01f 4151 /******************* Bit definition for EXTI_EMR register *******************/
<> 147:30b64687e01f 4152 #define EXTI_EMR_MR0 0x00000001U /*!< Event Mask on line 0 */
<> 147:30b64687e01f 4153 #define EXTI_EMR_MR1 0x00000002U /*!< Event Mask on line 1 */
<> 147:30b64687e01f 4154 #define EXTI_EMR_MR2 0x00000004U /*!< Event Mask on line 2 */
<> 147:30b64687e01f 4155 #define EXTI_EMR_MR3 0x00000008U /*!< Event Mask on line 3 */
<> 147:30b64687e01f 4156 #define EXTI_EMR_MR4 0x00000010U /*!< Event Mask on line 4 */
<> 147:30b64687e01f 4157 #define EXTI_EMR_MR5 0x00000020U /*!< Event Mask on line 5 */
<> 147:30b64687e01f 4158 #define EXTI_EMR_MR6 0x00000040U /*!< Event Mask on line 6 */
<> 147:30b64687e01f 4159 #define EXTI_EMR_MR7 0x00000080U /*!< Event Mask on line 7 */
<> 147:30b64687e01f 4160 #define EXTI_EMR_MR8 0x00000100U /*!< Event Mask on line 8 */
<> 147:30b64687e01f 4161 #define EXTI_EMR_MR9 0x00000200U /*!< Event Mask on line 9 */
<> 147:30b64687e01f 4162 #define EXTI_EMR_MR10 0x00000400U /*!< Event Mask on line 10 */
<> 147:30b64687e01f 4163 #define EXTI_EMR_MR11 0x00000800U /*!< Event Mask on line 11 */
<> 147:30b64687e01f 4164 #define EXTI_EMR_MR12 0x00001000U /*!< Event Mask on line 12 */
<> 147:30b64687e01f 4165 #define EXTI_EMR_MR13 0x00002000U /*!< Event Mask on line 13 */
<> 147:30b64687e01f 4166 #define EXTI_EMR_MR14 0x00004000U /*!< Event Mask on line 14 */
<> 147:30b64687e01f 4167 #define EXTI_EMR_MR15 0x00008000U /*!< Event Mask on line 15 */
<> 147:30b64687e01f 4168 #define EXTI_EMR_MR16 0x00010000U /*!< Event Mask on line 16 */
<> 147:30b64687e01f 4169 #define EXTI_EMR_MR17 0x00020000U /*!< Event Mask on line 17 */
<> 147:30b64687e01f 4170 #define EXTI_EMR_MR18 0x00040000U /*!< Event Mask on line 18 */
<> 147:30b64687e01f 4171 #define EXTI_EMR_MR19 0x00080000U /*!< Event Mask on line 19 */
<> 147:30b64687e01f 4172 #define EXTI_EMR_MR20 0x00100000U /*!< Event Mask on line 20 */
<> 147:30b64687e01f 4173 #define EXTI_EMR_MR21 0x00200000U /*!< Event Mask on line 21 */
<> 147:30b64687e01f 4174 #define EXTI_EMR_MR22 0x00400000U /*!< Event Mask on line 22 */
<> 147:30b64687e01f 4175 #define EXTI_EMR_MR23 0x00800000U /*!< Event Mask on line 23 */
<> 147:30b64687e01f 4176 #define EXTI_EMR_MR24 0x01000000U /*!< Event Mask on line 24 */
<> 147:30b64687e01f 4177
<> 147:30b64687e01f 4178 /* Reference Defines */
<> 147:30b64687e01f 4179 #define EXTI_EMR_EM0 EXTI_EMR_MR0
<> 147:30b64687e01f 4180 #define EXTI_EMR_EM1 EXTI_EMR_MR1
<> 147:30b64687e01f 4181 #define EXTI_EMR_EM2 EXTI_EMR_MR2
<> 147:30b64687e01f 4182 #define EXTI_EMR_EM3 EXTI_EMR_MR3
<> 147:30b64687e01f 4183 #define EXTI_EMR_EM4 EXTI_EMR_MR4
<> 147:30b64687e01f 4184 #define EXTI_EMR_EM5 EXTI_EMR_MR5
<> 147:30b64687e01f 4185 #define EXTI_EMR_EM6 EXTI_EMR_MR6
<> 147:30b64687e01f 4186 #define EXTI_EMR_EM7 EXTI_EMR_MR7
<> 147:30b64687e01f 4187 #define EXTI_EMR_EM8 EXTI_EMR_MR8
<> 147:30b64687e01f 4188 #define EXTI_EMR_EM9 EXTI_EMR_MR9
<> 147:30b64687e01f 4189 #define EXTI_EMR_EM10 EXTI_EMR_MR10
<> 147:30b64687e01f 4190 #define EXTI_EMR_EM11 EXTI_EMR_MR11
<> 147:30b64687e01f 4191 #define EXTI_EMR_EM12 EXTI_EMR_MR12
<> 147:30b64687e01f 4192 #define EXTI_EMR_EM13 EXTI_EMR_MR13
<> 147:30b64687e01f 4193 #define EXTI_EMR_EM14 EXTI_EMR_MR14
<> 147:30b64687e01f 4194 #define EXTI_EMR_EM15 EXTI_EMR_MR15
<> 147:30b64687e01f 4195 #define EXTI_EMR_EM16 EXTI_EMR_MR16
<> 147:30b64687e01f 4196 #define EXTI_EMR_EM17 EXTI_EMR_MR17
<> 147:30b64687e01f 4197 #define EXTI_EMR_EM18 EXTI_EMR_MR18
<> 147:30b64687e01f 4198 #define EXTI_EMR_EM19 EXTI_EMR_MR19
<> 147:30b64687e01f 4199 #define EXTI_EMR_EM20 EXTI_EMR_MR20
<> 147:30b64687e01f 4200 #define EXTI_EMR_EM21 EXTI_EMR_MR21
<> 147:30b64687e01f 4201 #define EXTI_EMR_EM22 EXTI_EMR_MR22
<> 147:30b64687e01f 4202 #define EXTI_EMR_EM23 EXTI_EMR_MR23
<> 147:30b64687e01f 4203 #define EXTI_EMR_EM24 EXTI_EMR_MR24
<> 147:30b64687e01f 4204
<> 147:30b64687e01f 4205
<> 147:30b64687e01f 4206 /****************** Bit definition for EXTI_RTSR register *******************/
<> 147:30b64687e01f 4207 #define EXTI_RTSR_TR0 0x00000001U /*!< Rising trigger event configuration bit of line 0 */
<> 147:30b64687e01f 4208 #define EXTI_RTSR_TR1 0x00000002U /*!< Rising trigger event configuration bit of line 1 */
<> 147:30b64687e01f 4209 #define EXTI_RTSR_TR2 0x00000004U /*!< Rising trigger event configuration bit of line 2 */
<> 147:30b64687e01f 4210 #define EXTI_RTSR_TR3 0x00000008U /*!< Rising trigger event configuration bit of line 3 */
<> 147:30b64687e01f 4211 #define EXTI_RTSR_TR4 0x00000010U /*!< Rising trigger event configuration bit of line 4 */
<> 147:30b64687e01f 4212 #define EXTI_RTSR_TR5 0x00000020U /*!< Rising trigger event configuration bit of line 5 */
<> 147:30b64687e01f 4213 #define EXTI_RTSR_TR6 0x00000040U /*!< Rising trigger event configuration bit of line 6 */
<> 147:30b64687e01f 4214 #define EXTI_RTSR_TR7 0x00000080U /*!< Rising trigger event configuration bit of line 7 */
<> 147:30b64687e01f 4215 #define EXTI_RTSR_TR8 0x00000100U /*!< Rising trigger event configuration bit of line 8 */
<> 147:30b64687e01f 4216 #define EXTI_RTSR_TR9 0x00000200U /*!< Rising trigger event configuration bit of line 9 */
<> 147:30b64687e01f 4217 #define EXTI_RTSR_TR10 0x00000400U /*!< Rising trigger event configuration bit of line 10 */
<> 147:30b64687e01f 4218 #define EXTI_RTSR_TR11 0x00000800U /*!< Rising trigger event configuration bit of line 11 */
<> 147:30b64687e01f 4219 #define EXTI_RTSR_TR12 0x00001000U /*!< Rising trigger event configuration bit of line 12 */
<> 147:30b64687e01f 4220 #define EXTI_RTSR_TR13 0x00002000U /*!< Rising trigger event configuration bit of line 13 */
<> 147:30b64687e01f 4221 #define EXTI_RTSR_TR14 0x00004000U /*!< Rising trigger event configuration bit of line 14 */
<> 147:30b64687e01f 4222 #define EXTI_RTSR_TR15 0x00008000U /*!< Rising trigger event configuration bit of line 15 */
<> 147:30b64687e01f 4223 #define EXTI_RTSR_TR16 0x00010000U /*!< Rising trigger event configuration bit of line 16 */
<> 147:30b64687e01f 4224 #define EXTI_RTSR_TR17 0x00020000U /*!< Rising trigger event configuration bit of line 17 */
<> 147:30b64687e01f 4225 #define EXTI_RTSR_TR18 0x00040000U /*!< Rising trigger event configuration bit of line 18 */
<> 147:30b64687e01f 4226 #define EXTI_RTSR_TR19 0x00080000U /*!< Rising trigger event configuration bit of line 19 */
<> 147:30b64687e01f 4227 #define EXTI_RTSR_TR20 0x00100000U /*!< Rising trigger event configuration bit of line 20 */
<> 147:30b64687e01f 4228 #define EXTI_RTSR_TR21 0x00200000U /*!< Rising trigger event configuration bit of line 21 */
<> 147:30b64687e01f 4229 #define EXTI_RTSR_TR22 0x00400000U /*!< Rising trigger event configuration bit of line 22 */
<> 147:30b64687e01f 4230 #define EXTI_RTSR_TR23 0x00800000U /*!< Rising trigger event configuration bit of line 23 */
<> 147:30b64687e01f 4231 #define EXTI_RTSR_TR24 0x01000000U /*!< Rising trigger event configuration bit of line 24 */
<> 147:30b64687e01f 4232
<> 147:30b64687e01f 4233 /****************** Bit definition for EXTI_FTSR register *******************/
<> 147:30b64687e01f 4234 #define EXTI_FTSR_TR0 0x00000001U /*!< Falling trigger event configuration bit of line 0 */
<> 147:30b64687e01f 4235 #define EXTI_FTSR_TR1 0x00000002U /*!< Falling trigger event configuration bit of line 1 */
<> 147:30b64687e01f 4236 #define EXTI_FTSR_TR2 0x00000004U /*!< Falling trigger event configuration bit of line 2 */
<> 147:30b64687e01f 4237 #define EXTI_FTSR_TR3 0x00000008U /*!< Falling trigger event configuration bit of line 3 */
<> 147:30b64687e01f 4238 #define EXTI_FTSR_TR4 0x00000010U /*!< Falling trigger event configuration bit of line 4 */
<> 147:30b64687e01f 4239 #define EXTI_FTSR_TR5 0x00000020U /*!< Falling trigger event configuration bit of line 5 */
<> 147:30b64687e01f 4240 #define EXTI_FTSR_TR6 0x00000040U /*!< Falling trigger event configuration bit of line 6 */
<> 147:30b64687e01f 4241 #define EXTI_FTSR_TR7 0x00000080U /*!< Falling trigger event configuration bit of line 7 */
<> 147:30b64687e01f 4242 #define EXTI_FTSR_TR8 0x00000100U /*!< Falling trigger event configuration bit of line 8 */
<> 147:30b64687e01f 4243 #define EXTI_FTSR_TR9 0x00000200U /*!< Falling trigger event configuration bit of line 9 */
<> 147:30b64687e01f 4244 #define EXTI_FTSR_TR10 0x00000400U /*!< Falling trigger event configuration bit of line 10 */
<> 147:30b64687e01f 4245 #define EXTI_FTSR_TR11 0x00000800U /*!< Falling trigger event configuration bit of line 11 */
<> 147:30b64687e01f 4246 #define EXTI_FTSR_TR12 0x00001000U /*!< Falling trigger event configuration bit of line 12 */
<> 147:30b64687e01f 4247 #define EXTI_FTSR_TR13 0x00002000U /*!< Falling trigger event configuration bit of line 13 */
<> 147:30b64687e01f 4248 #define EXTI_FTSR_TR14 0x00004000U /*!< Falling trigger event configuration bit of line 14 */
<> 147:30b64687e01f 4249 #define EXTI_FTSR_TR15 0x00008000U /*!< Falling trigger event configuration bit of line 15 */
<> 147:30b64687e01f 4250 #define EXTI_FTSR_TR16 0x00010000U /*!< Falling trigger event configuration bit of line 16 */
<> 147:30b64687e01f 4251 #define EXTI_FTSR_TR17 0x00020000U /*!< Falling trigger event configuration bit of line 17 */
<> 147:30b64687e01f 4252 #define EXTI_FTSR_TR18 0x00040000U /*!< Falling trigger event configuration bit of line 18 */
<> 147:30b64687e01f 4253 #define EXTI_FTSR_TR19 0x00080000U /*!< Falling trigger event configuration bit of line 19 */
<> 147:30b64687e01f 4254 #define EXTI_FTSR_TR20 0x00100000U /*!< Falling trigger event configuration bit of line 20 */
<> 147:30b64687e01f 4255 #define EXTI_FTSR_TR21 0x00200000U /*!< Falling trigger event configuration bit of line 21 */
<> 147:30b64687e01f 4256 #define EXTI_FTSR_TR22 0x00400000U /*!< Falling trigger event configuration bit of line 22 */
<> 147:30b64687e01f 4257 #define EXTI_FTSR_TR23 0x00800000U /*!< Falling trigger event configuration bit of line 23 */
<> 147:30b64687e01f 4258 #define EXTI_FTSR_TR24 0x01000000U /*!< Falling trigger event configuration bit of line 24 */
<> 147:30b64687e01f 4259
<> 147:30b64687e01f 4260 /****************** Bit definition for EXTI_SWIER register ******************/
<> 147:30b64687e01f 4261 #define EXTI_SWIER_SWIER0 0x00000001U /*!< Software Interrupt on line 0 */
<> 147:30b64687e01f 4262 #define EXTI_SWIER_SWIER1 0x00000002U /*!< Software Interrupt on line 1 */
<> 147:30b64687e01f 4263 #define EXTI_SWIER_SWIER2 0x00000004U /*!< Software Interrupt on line 2 */
<> 147:30b64687e01f 4264 #define EXTI_SWIER_SWIER3 0x00000008U /*!< Software Interrupt on line 3 */
<> 147:30b64687e01f 4265 #define EXTI_SWIER_SWIER4 0x00000010U /*!< Software Interrupt on line 4 */
<> 147:30b64687e01f 4266 #define EXTI_SWIER_SWIER5 0x00000020U /*!< Software Interrupt on line 5 */
<> 147:30b64687e01f 4267 #define EXTI_SWIER_SWIER6 0x00000040U /*!< Software Interrupt on line 6 */
<> 147:30b64687e01f 4268 #define EXTI_SWIER_SWIER7 0x00000080U /*!< Software Interrupt on line 7 */
<> 147:30b64687e01f 4269 #define EXTI_SWIER_SWIER8 0x00000100U /*!< Software Interrupt on line 8 */
<> 147:30b64687e01f 4270 #define EXTI_SWIER_SWIER9 0x00000200U /*!< Software Interrupt on line 9 */
<> 147:30b64687e01f 4271 #define EXTI_SWIER_SWIER10 0x00000400U /*!< Software Interrupt on line 10 */
<> 147:30b64687e01f 4272 #define EXTI_SWIER_SWIER11 0x00000800U /*!< Software Interrupt on line 11 */
<> 147:30b64687e01f 4273 #define EXTI_SWIER_SWIER12 0x00001000U /*!< Software Interrupt on line 12 */
<> 147:30b64687e01f 4274 #define EXTI_SWIER_SWIER13 0x00002000U /*!< Software Interrupt on line 13 */
<> 147:30b64687e01f 4275 #define EXTI_SWIER_SWIER14 0x00004000U /*!< Software Interrupt on line 14 */
<> 147:30b64687e01f 4276 #define EXTI_SWIER_SWIER15 0x00008000U /*!< Software Interrupt on line 15 */
<> 147:30b64687e01f 4277 #define EXTI_SWIER_SWIER16 0x00010000U /*!< Software Interrupt on line 16 */
<> 147:30b64687e01f 4278 #define EXTI_SWIER_SWIER17 0x00020000U /*!< Software Interrupt on line 17 */
<> 147:30b64687e01f 4279 #define EXTI_SWIER_SWIER18 0x00040000U /*!< Software Interrupt on line 18 */
<> 147:30b64687e01f 4280 #define EXTI_SWIER_SWIER19 0x00080000U /*!< Software Interrupt on line 19 */
<> 147:30b64687e01f 4281 #define EXTI_SWIER_SWIER20 0x00100000U /*!< Software Interrupt on line 20 */
<> 147:30b64687e01f 4282 #define EXTI_SWIER_SWIER21 0x00200000U /*!< Software Interrupt on line 21 */
<> 147:30b64687e01f 4283 #define EXTI_SWIER_SWIER22 0x00400000U /*!< Software Interrupt on line 22 */
<> 147:30b64687e01f 4284 #define EXTI_SWIER_SWIER23 0x00800000U /*!< Software Interrupt on line 23 */
<> 147:30b64687e01f 4285 #define EXTI_SWIER_SWIER24 0x01000000U /*!< Software Interrupt on line 24 */
<> 147:30b64687e01f 4286
<> 147:30b64687e01f 4287 /******************* Bit definition for EXTI_PR register ********************/
<> 147:30b64687e01f 4288 #define EXTI_PR_PR0 0x00000001U /*!< Pending bit for line 0 */
<> 147:30b64687e01f 4289 #define EXTI_PR_PR1 0x00000002U /*!< Pending bit for line 1 */
<> 147:30b64687e01f 4290 #define EXTI_PR_PR2 0x00000004U /*!< Pending bit for line 2 */
<> 147:30b64687e01f 4291 #define EXTI_PR_PR3 0x00000008U /*!< Pending bit for line 3 */
<> 147:30b64687e01f 4292 #define EXTI_PR_PR4 0x00000010U /*!< Pending bit for line 4 */
<> 147:30b64687e01f 4293 #define EXTI_PR_PR5 0x00000020U /*!< Pending bit for line 5 */
<> 147:30b64687e01f 4294 #define EXTI_PR_PR6 0x00000040U /*!< Pending bit for line 6 */
<> 147:30b64687e01f 4295 #define EXTI_PR_PR7 0x00000080U /*!< Pending bit for line 7 */
<> 147:30b64687e01f 4296 #define EXTI_PR_PR8 0x00000100U /*!< Pending bit for line 8 */
<> 147:30b64687e01f 4297 #define EXTI_PR_PR9 0x00000200U /*!< Pending bit for line 9 */
<> 147:30b64687e01f 4298 #define EXTI_PR_PR10 0x00000400U /*!< Pending bit for line 10 */
<> 147:30b64687e01f 4299 #define EXTI_PR_PR11 0x00000800U /*!< Pending bit for line 11 */
<> 147:30b64687e01f 4300 #define EXTI_PR_PR12 0x00001000U /*!< Pending bit for line 12 */
<> 147:30b64687e01f 4301 #define EXTI_PR_PR13 0x00002000U /*!< Pending bit for line 13 */
<> 147:30b64687e01f 4302 #define EXTI_PR_PR14 0x00004000U /*!< Pending bit for line 14 */
<> 147:30b64687e01f 4303 #define EXTI_PR_PR15 0x00008000U /*!< Pending bit for line 15 */
<> 147:30b64687e01f 4304 #define EXTI_PR_PR16 0x00010000U /*!< Pending bit for line 16 */
<> 147:30b64687e01f 4305 #define EXTI_PR_PR17 0x00020000U /*!< Pending bit for line 17 */
<> 147:30b64687e01f 4306 #define EXTI_PR_PR18 0x00040000U /*!< Pending bit for line 18 */
<> 147:30b64687e01f 4307 #define EXTI_PR_PR19 0x00080000U /*!< Pending bit for line 19 */
<> 147:30b64687e01f 4308 #define EXTI_PR_PR20 0x00100000U /*!< Pending bit for line 20 */
<> 147:30b64687e01f 4309 #define EXTI_PR_PR21 0x00200000U /*!< Pending bit for line 21 */
<> 147:30b64687e01f 4310 #define EXTI_PR_PR22 0x00400000U /*!< Pending bit for line 22 */
<> 147:30b64687e01f 4311 #define EXTI_PR_PR23 0x00800000U /*!< Pending bit for line 23 */
<> 147:30b64687e01f 4312 #define EXTI_PR_PR24 0x01000000U /*!< Pending bit for line 24 */
<> 147:30b64687e01f 4313
<> 147:30b64687e01f 4314 /******************************************************************************/
<> 147:30b64687e01f 4315 /* */
<> 147:30b64687e01f 4316 /* FLASH */
<> 147:30b64687e01f 4317 /* */
<> 147:30b64687e01f 4318 /******************************************************************************/
<> 147:30b64687e01f 4319 /*
<> 147:30b64687e01f 4320 * @brief FLASH Total Sectors Number
<> 147:30b64687e01f 4321 */
<> 147:30b64687e01f 4322 #define FLASH_SECTOR_TOTAL 24
<> 147:30b64687e01f 4323
<> 147:30b64687e01f 4324 /******************* Bits definition for FLASH_ACR register *****************/
<> 147:30b64687e01f 4325 #define FLASH_ACR_LATENCY 0x0000000FU
<> 147:30b64687e01f 4326 #define FLASH_ACR_LATENCY_0WS 0x00000000U
<> 147:30b64687e01f 4327 #define FLASH_ACR_LATENCY_1WS 0x00000001U
<> 147:30b64687e01f 4328 #define FLASH_ACR_LATENCY_2WS 0x00000002U
<> 147:30b64687e01f 4329 #define FLASH_ACR_LATENCY_3WS 0x00000003U
<> 147:30b64687e01f 4330 #define FLASH_ACR_LATENCY_4WS 0x00000004U
<> 147:30b64687e01f 4331 #define FLASH_ACR_LATENCY_5WS 0x00000005U
<> 147:30b64687e01f 4332 #define FLASH_ACR_LATENCY_6WS 0x00000006U
<> 147:30b64687e01f 4333 #define FLASH_ACR_LATENCY_7WS 0x00000007U
<> 147:30b64687e01f 4334 #define FLASH_ACR_LATENCY_8WS 0x00000008U
<> 147:30b64687e01f 4335 #define FLASH_ACR_LATENCY_9WS 0x00000009U
<> 147:30b64687e01f 4336 #define FLASH_ACR_LATENCY_10WS 0x0000000AU
<> 147:30b64687e01f 4337 #define FLASH_ACR_LATENCY_11WS 0x0000000BU
<> 147:30b64687e01f 4338 #define FLASH_ACR_LATENCY_12WS 0x0000000CU
<> 147:30b64687e01f 4339 #define FLASH_ACR_LATENCY_13WS 0x0000000DU
<> 147:30b64687e01f 4340 #define FLASH_ACR_LATENCY_14WS 0x0000000EU
<> 147:30b64687e01f 4341 #define FLASH_ACR_LATENCY_15WS 0x0000000FU
<> 147:30b64687e01f 4342 #define FLASH_ACR_PRFTEN 0x00000100U
<> 147:30b64687e01f 4343 #define FLASH_ACR_ARTEN 0x00000200U
<> 147:30b64687e01f 4344 #define FLASH_ACR_ARTRST 0x00000800U
<> 147:30b64687e01f 4345
<> 147:30b64687e01f 4346 /******************* Bits definition for FLASH_SR register ******************/
<> 147:30b64687e01f 4347 #define FLASH_SR_EOP 0x00000001U
<> 147:30b64687e01f 4348 #define FLASH_SR_OPERR 0x00000002U
<> 147:30b64687e01f 4349 #define FLASH_SR_WRPERR 0x00000010U
<> 147:30b64687e01f 4350 #define FLASH_SR_PGAERR 0x00000020U
<> 147:30b64687e01f 4351 #define FLASH_SR_PGPERR 0x00000040U
<> 147:30b64687e01f 4352 #define FLASH_SR_ERSERR 0x00000080U
<> 147:30b64687e01f 4353 #define FLASH_SR_BSY 0x00010000U
<> 147:30b64687e01f 4354
<> 147:30b64687e01f 4355 /******************* Bits definition for FLASH_CR register ******************/
<> 147:30b64687e01f 4356 #define FLASH_CR_PG 0x00000001U
<> 147:30b64687e01f 4357 #define FLASH_CR_SER 0x00000002U
<> 147:30b64687e01f 4358 #define FLASH_CR_MER 0x00000004U
<> 147:30b64687e01f 4359 #define FLASH_CR_MER1 FLASH_CR_MER
<> 147:30b64687e01f 4360 #define FLASH_CR_SNB 0x000000F8U
<> 147:30b64687e01f 4361 #define FLASH_CR_SNB_0 0x00000008U
<> 147:30b64687e01f 4362 #define FLASH_CR_SNB_1 0x00000010U
<> 147:30b64687e01f 4363 #define FLASH_CR_SNB_2 0x00000020U
<> 147:30b64687e01f 4364 #define FLASH_CR_SNB_3 0x00000040U
<> 147:30b64687e01f 4365 #define FLASH_CR_SNB_4 0x00000080U
<> 147:30b64687e01f 4366 #define FLASH_CR_PSIZE 0x00000300U
<> 147:30b64687e01f 4367 #define FLASH_CR_PSIZE_0 0x00000100U
<> 147:30b64687e01f 4368 #define FLASH_CR_PSIZE_1 0x00000200U
<> 147:30b64687e01f 4369 #define FLASH_CR_MER2 0x00008000U
<> 147:30b64687e01f 4370 #define FLASH_CR_STRT 0x00010000U
<> 147:30b64687e01f 4371 #define FLASH_CR_EOPIE 0x01000000U
<> 147:30b64687e01f 4372 #define FLASH_CR_ERRIE 0x02000000U
<> 147:30b64687e01f 4373 #define FLASH_CR_LOCK 0x80000000U
<> 147:30b64687e01f 4374
<> 147:30b64687e01f 4375 /******************* Bits definition for FLASH_OPTCR register ***************/
<> 147:30b64687e01f 4376 #define FLASH_OPTCR_OPTLOCK 0x00000001U
<> 147:30b64687e01f 4377 #define FLASH_OPTCR_OPTSTRT 0x00000002U
<> 147:30b64687e01f 4378 #define FLASH_OPTCR_BOR_LEV 0x0000000CU
<> 147:30b64687e01f 4379 #define FLASH_OPTCR_BOR_LEV_0 0x00000004U
<> 147:30b64687e01f 4380 #define FLASH_OPTCR_BOR_LEV_1 0x00000008U
<> 147:30b64687e01f 4381 #define FLASH_OPTCR_WWDG_SW 0x00000010U
<> 147:30b64687e01f 4382 #define FLASH_OPTCR_IWDG_SW 0x00000020U
<> 147:30b64687e01f 4383 #define FLASH_OPTCR_nRST_STOP 0x00000040U
<> 147:30b64687e01f 4384 #define FLASH_OPTCR_nRST_STDBY 0x00000080U
<> 147:30b64687e01f 4385 #define FLASH_OPTCR_RDP 0x0000FF00U
<> 147:30b64687e01f 4386 #define FLASH_OPTCR_RDP_0 0x00000100U
<> 147:30b64687e01f 4387 #define FLASH_OPTCR_RDP_1 0x00000200U
<> 147:30b64687e01f 4388 #define FLASH_OPTCR_RDP_2 0x00000400U
<> 147:30b64687e01f 4389 #define FLASH_OPTCR_RDP_3 0x00000800U
<> 147:30b64687e01f 4390 #define FLASH_OPTCR_RDP_4 0x00001000U
<> 147:30b64687e01f 4391 #define FLASH_OPTCR_RDP_5 0x00002000U
<> 147:30b64687e01f 4392 #define FLASH_OPTCR_RDP_6 0x00004000U
<> 147:30b64687e01f 4393 #define FLASH_OPTCR_RDP_7 0x00008000U
<> 147:30b64687e01f 4394 #define FLASH_OPTCR_nWRP 0x0FFF0000U
<> 147:30b64687e01f 4395 #define FLASH_OPTCR_nWRP_0 0x00010000U
<> 147:30b64687e01f 4396 #define FLASH_OPTCR_nWRP_1 0x00020000U
<> 147:30b64687e01f 4397 #define FLASH_OPTCR_nWRP_2 0x00040000U
<> 147:30b64687e01f 4398 #define FLASH_OPTCR_nWRP_3 0x00080000U
<> 147:30b64687e01f 4399 #define FLASH_OPTCR_nWRP_4 0x00100000U
<> 147:30b64687e01f 4400 #define FLASH_OPTCR_nWRP_5 0x00200000U
<> 147:30b64687e01f 4401 #define FLASH_OPTCR_nWRP_6 0x00400000U
<> 147:30b64687e01f 4402 #define FLASH_OPTCR_nWRP_7 0x00800000U
<> 147:30b64687e01f 4403 #define FLASH_OPTCR_nWRP_8 0x01000000U
<> 147:30b64687e01f 4404 #define FLASH_OPTCR_nWRP_9 0x02000000U
<> 147:30b64687e01f 4405 #define FLASH_OPTCR_nWRP_10 0x04000000U
<> 147:30b64687e01f 4406 #define FLASH_OPTCR_nWRP_11 0x08000000U
<> 147:30b64687e01f 4407 #define FLASH_OPTCR_nDBOOT 0x10000000U
<> 147:30b64687e01f 4408 #define FLASH_OPTCR_nDBANK 0x20000000U
<> 147:30b64687e01f 4409 #define FLASH_OPTCR_IWDG_STDBY 0x40000000U
<> 147:30b64687e01f 4410 #define FLASH_OPTCR_IWDG_STOP 0x80000000U
<> 147:30b64687e01f 4411
<> 147:30b64687e01f 4412 /******************* Bits definition for FLASH_OPTCR1 register ***************/
<> 147:30b64687e01f 4413 #define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
<> 147:30b64687e01f 4414 #define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
<> 147:30b64687e01f 4415
<> 157:ff67d9f36b67 4416
<> 147:30b64687e01f 4417 /******************************************************************************/
<> 147:30b64687e01f 4418 /* */
<> 147:30b64687e01f 4419 /* Flexible Memory Controller */
<> 147:30b64687e01f 4420 /* */
<> 147:30b64687e01f 4421 /******************************************************************************/
<> 147:30b64687e01f 4422 /****************** Bit definition for FMC_BCR1 register *******************/
<> 147:30b64687e01f 4423 #define FMC_BCR1_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 147:30b64687e01f 4424 #define FMC_BCR1_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 4425 #define FMC_BCR1_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 4426 #define FMC_BCR1_MTYP_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4427 #define FMC_BCR1_MTYP_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4428 #define FMC_BCR1_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 4429 #define FMC_BCR1_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4430 #define FMC_BCR1_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4431 #define FMC_BCR1_FACCEN 0x00000040U /*!<Flash access enable */
<> 147:30b64687e01f 4432 #define FMC_BCR1_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 147:30b64687e01f 4433 #define FMC_BCR1_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 147:30b64687e01f 4434 #define FMC_BCR1_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 147:30b64687e01f 4435 #define FMC_BCR1_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 147:30b64687e01f 4436 #define FMC_BCR1_WREN 0x00001000U /*!<Write enable bit */
<> 147:30b64687e01f 4437 #define FMC_BCR1_WAITEN 0x00002000U /*!<Wait enable bit */
<> 147:30b64687e01f 4438 #define FMC_BCR1_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 147:30b64687e01f 4439 #define FMC_BCR1_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 147:30b64687e01f 4440 #define FMC_BCR1_CPSIZE 0x00070000U /*!<CRAM page size */
<> 147:30b64687e01f 4441 #define FMC_BCR1_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4442 #define FMC_BCR1_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4443 #define FMC_BCR1_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4444 #define FMC_BCR1_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 147:30b64687e01f 4445 #define FMC_BCR1_CCLKEN 0x00100000U /*!<Continous clock enable */
<> 147:30b64687e01f 4446 #define FMC_BCR1_WFDIS 0x00200000U /*!<Write FIFO Disable */
<> 147:30b64687e01f 4447
<> 147:30b64687e01f 4448 /****************** Bit definition for FMC_BCR2 register *******************/
<> 147:30b64687e01f 4449 #define FMC_BCR2_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 147:30b64687e01f 4450 #define FMC_BCR2_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 4451 #define FMC_BCR2_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 4452 #define FMC_BCR2_MTYP_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4453 #define FMC_BCR2_MTYP_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4454 #define FMC_BCR2_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 4455 #define FMC_BCR2_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4456 #define FMC_BCR2_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4457 #define FMC_BCR2_FACCEN 0x00000040U /*!<Flash access enable */
<> 147:30b64687e01f 4458 #define FMC_BCR2_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 147:30b64687e01f 4459 #define FMC_BCR2_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 147:30b64687e01f 4460 #define FMC_BCR2_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 147:30b64687e01f 4461 #define FMC_BCR2_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 147:30b64687e01f 4462 #define FMC_BCR2_WREN 0x00001000U /*!<Write enable bit */
<> 147:30b64687e01f 4463 #define FMC_BCR2_WAITEN 0x00002000U /*!<Wait enable bit */
<> 147:30b64687e01f 4464 #define FMC_BCR2_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 147:30b64687e01f 4465 #define FMC_BCR2_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 147:30b64687e01f 4466 #define FMC_BCR2_CPSIZE 0x00070000U /*!<CRAM page size */
<> 147:30b64687e01f 4467 #define FMC_BCR2_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4468 #define FMC_BCR2_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4469 #define FMC_BCR2_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4470 #define FMC_BCR2_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 147:30b64687e01f 4471
<> 147:30b64687e01f 4472 /****************** Bit definition for FMC_BCR3 register *******************/
<> 147:30b64687e01f 4473 #define FMC_BCR3_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 147:30b64687e01f 4474 #define FMC_BCR3_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 4475 #define FMC_BCR3_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 4476 #define FMC_BCR3_MTYP_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4477 #define FMC_BCR3_MTYP_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4478 #define FMC_BCR3_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 4479 #define FMC_BCR3_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4480 #define FMC_BCR3_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4481 #define FMC_BCR3_FACCEN 0x00000040U /*!<Flash access enable */
<> 147:30b64687e01f 4482 #define FMC_BCR3_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 147:30b64687e01f 4483 #define FMC_BCR3_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 147:30b64687e01f 4484 #define FMC_BCR3_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 147:30b64687e01f 4485 #define FMC_BCR3_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 147:30b64687e01f 4486 #define FMC_BCR3_WREN 0x00001000U /*!<Write enable bit */
<> 147:30b64687e01f 4487 #define FMC_BCR3_WAITEN 0x00002000U /*!<Wait enable bit */
<> 147:30b64687e01f 4488 #define FMC_BCR3_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 147:30b64687e01f 4489 #define FMC_BCR3_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 147:30b64687e01f 4490 #define FMC_BCR3_CPSIZE 0x00070000U /*!<CRAM page size */
<> 147:30b64687e01f 4491 #define FMC_BCR3_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4492 #define FMC_BCR3_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4493 #define FMC_BCR3_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4494 #define FMC_BCR3_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 147:30b64687e01f 4495
<> 147:30b64687e01f 4496 /****************** Bit definition for FMC_BCR4 register *******************/
<> 147:30b64687e01f 4497 #define FMC_BCR4_MBKEN 0x00000001U /*!<Memory bank enable bit */
<> 147:30b64687e01f 4498 #define FMC_BCR4_MUXEN 0x00000002U /*!<Address/data multiplexing enable bit */
<> 147:30b64687e01f 4499 #define FMC_BCR4_MTYP 0x0000000CU /*!<MTYP[1:0] bits (Memory type) */
<> 147:30b64687e01f 4500 #define FMC_BCR4_MTYP_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4501 #define FMC_BCR4_MTYP_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4502 #define FMC_BCR4_MWID 0x00000030U /*!<MWID[1:0] bits (Memory data bus width) */
<> 147:30b64687e01f 4503 #define FMC_BCR4_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4504 #define FMC_BCR4_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4505 #define FMC_BCR4_FACCEN 0x00000040U /*!<Flash access enable */
<> 147:30b64687e01f 4506 #define FMC_BCR4_BURSTEN 0x00000100U /*!<Burst enable bit */
<> 147:30b64687e01f 4507 #define FMC_BCR4_WAITPOL 0x00000200U /*!<Wait signal polarity bit */
<> 147:30b64687e01f 4508 #define FMC_BCR4_WRAPMOD 0x00000400U /*!<Wrapped burst mode support */
<> 147:30b64687e01f 4509 #define FMC_BCR4_WAITCFG 0x00000800U /*!<Wait timing configuration */
<> 147:30b64687e01f 4510 #define FMC_BCR4_WREN 0x00001000U /*!<Write enable bit */
<> 147:30b64687e01f 4511 #define FMC_BCR4_WAITEN 0x00002000U /*!<Wait enable bit */
<> 147:30b64687e01f 4512 #define FMC_BCR4_EXTMOD 0x00004000U /*!<Extended mode enable */
<> 147:30b64687e01f 4513 #define FMC_BCR4_ASYNCWAIT 0x00008000U /*!<Asynchronous wait */
<> 147:30b64687e01f 4514 #define FMC_BCR4_CPSIZE 0x00070000U /*!<CRAM page size */
<> 147:30b64687e01f 4515 #define FMC_BCR4_CPSIZE_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4516 #define FMC_BCR4_CPSIZE_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4517 #define FMC_BCR4_CPSIZE_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4518 #define FMC_BCR4_CBURSTRW 0x00080000U /*!<Write burst enable */
<> 147:30b64687e01f 4519
<> 147:30b64687e01f 4520 /****************** Bit definition for FMC_BTR1 register ******************/
<> 147:30b64687e01f 4521 #define FMC_BTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4522 #define FMC_BTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4523 #define FMC_BTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4524 #define FMC_BTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4525 #define FMC_BTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4526 #define FMC_BTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4527 #define FMC_BTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4528 #define FMC_BTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4529 #define FMC_BTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4530 #define FMC_BTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4531 #define FMC_BTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4532 #define FMC_BTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4533 #define FMC_BTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4534 #define FMC_BTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4535 #define FMC_BTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4536 #define FMC_BTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4537 #define FMC_BTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4538 #define FMC_BTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4539 #define FMC_BTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4540 #define FMC_BTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4541 #define FMC_BTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4542 #define FMC_BTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4543 #define FMC_BTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4544 #define FMC_BTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4545 #define FMC_BTR1_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 4546 #define FMC_BTR1_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 4547 #define FMC_BTR1_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 4548 #define FMC_BTR1_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 4549 #define FMC_BTR1_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 4550 #define FMC_BTR1_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 4551 #define FMC_BTR1_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4552 #define FMC_BTR1_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4553 #define FMC_BTR1_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4554 #define FMC_BTR1_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4555 #define FMC_BTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4556 #define FMC_BTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4557 #define FMC_BTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4558
<> 147:30b64687e01f 4559 /****************** Bit definition for FMC_BTR2 register *******************/
<> 147:30b64687e01f 4560 #define FMC_BTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4561 #define FMC_BTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4562 #define FMC_BTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4563 #define FMC_BTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4564 #define FMC_BTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4565 #define FMC_BTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4566 #define FMC_BTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4567 #define FMC_BTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4568 #define FMC_BTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4569 #define FMC_BTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4570 #define FMC_BTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4571 #define FMC_BTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4572 #define FMC_BTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4573 #define FMC_BTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4574 #define FMC_BTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4575 #define FMC_BTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4576 #define FMC_BTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4577 #define FMC_BTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4578 #define FMC_BTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4579 #define FMC_BTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4580 #define FMC_BTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4581 #define FMC_BTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4582 #define FMC_BTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4583 #define FMC_BTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4584 #define FMC_BTR2_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 4585 #define FMC_BTR2_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 4586 #define FMC_BTR2_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 4587 #define FMC_BTR2_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 4588 #define FMC_BTR2_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 4589 #define FMC_BTR2_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 4590 #define FMC_BTR2_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4591 #define FMC_BTR2_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4592 #define FMC_BTR2_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4593 #define FMC_BTR2_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4594 #define FMC_BTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4595 #define FMC_BTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4596 #define FMC_BTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4597
<> 147:30b64687e01f 4598 /******************* Bit definition for FMC_BTR3 register *******************/
<> 147:30b64687e01f 4599 #define FMC_BTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4600 #define FMC_BTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4601 #define FMC_BTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4602 #define FMC_BTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4603 #define FMC_BTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4604 #define FMC_BTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4605 #define FMC_BTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4606 #define FMC_BTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4607 #define FMC_BTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4608 #define FMC_BTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4609 #define FMC_BTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4610 #define FMC_BTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4611 #define FMC_BTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4612 #define FMC_BTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4613 #define FMC_BTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4614 #define FMC_BTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4615 #define FMC_BTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4616 #define FMC_BTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4617 #define FMC_BTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4618 #define FMC_BTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4619 #define FMC_BTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4620 #define FMC_BTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4621 #define FMC_BTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4622 #define FMC_BTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4623 #define FMC_BTR3_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 4624 #define FMC_BTR3_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 4625 #define FMC_BTR3_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 4626 #define FMC_BTR3_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 4627 #define FMC_BTR3_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 4628 #define FMC_BTR3_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 4629 #define FMC_BTR3_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4630 #define FMC_BTR3_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4631 #define FMC_BTR3_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4632 #define FMC_BTR3_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4633 #define FMC_BTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4634 #define FMC_BTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4635 #define FMC_BTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4636
<> 147:30b64687e01f 4637 /****************** Bit definition for FMC_BTR4 register *******************/
<> 147:30b64687e01f 4638 #define FMC_BTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4639 #define FMC_BTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4640 #define FMC_BTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4641 #define FMC_BTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4642 #define FMC_BTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4643 #define FMC_BTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4644 #define FMC_BTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4645 #define FMC_BTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4646 #define FMC_BTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4647 #define FMC_BTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4648 #define FMC_BTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4649 #define FMC_BTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4650 #define FMC_BTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4651 #define FMC_BTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4652 #define FMC_BTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4653 #define FMC_BTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4654 #define FMC_BTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4655 #define FMC_BTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4656 #define FMC_BTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4657 #define FMC_BTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4658 #define FMC_BTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4659 #define FMC_BTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4660 #define FMC_BTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4661 #define FMC_BTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4662 #define FMC_BTR4_CLKDIV 0x00F00000U /*!<CLKDIV[3:0] bits (Clock divide ratio) */
<> 147:30b64687e01f 4663 #define FMC_BTR4_CLKDIV_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 4664 #define FMC_BTR4_CLKDIV_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 4665 #define FMC_BTR4_CLKDIV_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 4666 #define FMC_BTR4_CLKDIV_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 4667 #define FMC_BTR4_DATLAT 0x0F000000U /*!<DATLA[3:0] bits (Data latency) */
<> 147:30b64687e01f 4668 #define FMC_BTR4_DATLAT_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4669 #define FMC_BTR4_DATLAT_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4670 #define FMC_BTR4_DATLAT_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4671 #define FMC_BTR4_DATLAT_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4672 #define FMC_BTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4673 #define FMC_BTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4674 #define FMC_BTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4675
<> 147:30b64687e01f 4676 /****************** Bit definition for FMC_BWTR1 register ******************/
<> 147:30b64687e01f 4677 #define FMC_BWTR1_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4678 #define FMC_BWTR1_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4679 #define FMC_BWTR1_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4680 #define FMC_BWTR1_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4681 #define FMC_BWTR1_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4682 #define FMC_BWTR1_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4683 #define FMC_BWTR1_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4684 #define FMC_BWTR1_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4685 #define FMC_BWTR1_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4686 #define FMC_BWTR1_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4687 #define FMC_BWTR1_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4688 #define FMC_BWTR1_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4689 #define FMC_BWTR1_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4690 #define FMC_BWTR1_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4691 #define FMC_BWTR1_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4692 #define FMC_BWTR1_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4693 #define FMC_BWTR1_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4694 #define FMC_BWTR1_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4695 #define FMC_BWTR1_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4696 #define FMC_BWTR1_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4697 #define FMC_BWTR1_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4698 #define FMC_BWTR1_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4699 #define FMC_BWTR1_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4700 #define FMC_BWTR1_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4701 #define FMC_BWTR1_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4702 #define FMC_BWTR1_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4703 #define FMC_BWTR1_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4704
<> 147:30b64687e01f 4705 /****************** Bit definition for FMC_BWTR2 register ******************/
<> 147:30b64687e01f 4706 #define FMC_BWTR2_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4707 #define FMC_BWTR2_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4708 #define FMC_BWTR2_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4709 #define FMC_BWTR2_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4710 #define FMC_BWTR2_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4711 #define FMC_BWTR2_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4712 #define FMC_BWTR2_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4713 #define FMC_BWTR2_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4714 #define FMC_BWTR2_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4715 #define FMC_BWTR2_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4716 #define FMC_BWTR2_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4717 #define FMC_BWTR2_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4718 #define FMC_BWTR2_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4719 #define FMC_BWTR2_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4720 #define FMC_BWTR2_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4721 #define FMC_BWTR2_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4722 #define FMC_BWTR2_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4723 #define FMC_BWTR2_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4724 #define FMC_BWTR2_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4725 #define FMC_BWTR2_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4726 #define FMC_BWTR2_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4727 #define FMC_BWTR2_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4728 #define FMC_BWTR2_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4729 #define FMC_BWTR2_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4730 #define FMC_BWTR2_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4731 #define FMC_BWTR2_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4732 #define FMC_BWTR2_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4733
<> 147:30b64687e01f 4734 /****************** Bit definition for FMC_BWTR3 register ******************/
<> 147:30b64687e01f 4735 #define FMC_BWTR3_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4736 #define FMC_BWTR3_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4737 #define FMC_BWTR3_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4738 #define FMC_BWTR3_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4739 #define FMC_BWTR3_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4740 #define FMC_BWTR3_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4741 #define FMC_BWTR3_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4742 #define FMC_BWTR3_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4743 #define FMC_BWTR3_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4744 #define FMC_BWTR3_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4745 #define FMC_BWTR3_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4746 #define FMC_BWTR3_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4747 #define FMC_BWTR3_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4748 #define FMC_BWTR3_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4749 #define FMC_BWTR3_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4750 #define FMC_BWTR3_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4751 #define FMC_BWTR3_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4752 #define FMC_BWTR3_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4753 #define FMC_BWTR3_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4754 #define FMC_BWTR3_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4755 #define FMC_BWTR3_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4756 #define FMC_BWTR3_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4757 #define FMC_BWTR3_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4758 #define FMC_BWTR3_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4759 #define FMC_BWTR3_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4760 #define FMC_BWTR3_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4761 #define FMC_BWTR3_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4762
<> 147:30b64687e01f 4763 /****************** Bit definition for FMC_BWTR4 register ******************/
<> 147:30b64687e01f 4764 #define FMC_BWTR4_ADDSET 0x0000000FU /*!<ADDSET[3:0] bits (Address setup phase duration) */
<> 147:30b64687e01f 4765 #define FMC_BWTR4_ADDSET_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4766 #define FMC_BWTR4_ADDSET_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4767 #define FMC_BWTR4_ADDSET_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4768 #define FMC_BWTR4_ADDSET_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4769 #define FMC_BWTR4_ADDHLD 0x000000F0U /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
<> 147:30b64687e01f 4770 #define FMC_BWTR4_ADDHLD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4771 #define FMC_BWTR4_ADDHLD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4772 #define FMC_BWTR4_ADDHLD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4773 #define FMC_BWTR4_ADDHLD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4774 #define FMC_BWTR4_DATAST 0x0000FF00U /*!<DATAST [3:0] bits (Data-phase duration) */
<> 147:30b64687e01f 4775 #define FMC_BWTR4_DATAST_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4776 #define FMC_BWTR4_DATAST_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4777 #define FMC_BWTR4_DATAST_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4778 #define FMC_BWTR4_DATAST_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4779 #define FMC_BWTR4_DATAST_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4780 #define FMC_BWTR4_DATAST_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4781 #define FMC_BWTR4_DATAST_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4782 #define FMC_BWTR4_DATAST_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4783 #define FMC_BWTR4_BUSTURN 0x000F0000U /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
<> 147:30b64687e01f 4784 #define FMC_BWTR4_BUSTURN_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4785 #define FMC_BWTR4_BUSTURN_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4786 #define FMC_BWTR4_BUSTURN_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4787 #define FMC_BWTR4_BUSTURN_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4788 #define FMC_BWTR4_ACCMOD 0x30000000U /*!<ACCMOD[1:0] bits (Access mode) */
<> 147:30b64687e01f 4789 #define FMC_BWTR4_ACCMOD_0 0x10000000U /*!<Bit 0 */
<> 147:30b64687e01f 4790 #define FMC_BWTR4_ACCMOD_1 0x20000000U /*!<Bit 1 */
<> 147:30b64687e01f 4791
<> 147:30b64687e01f 4792 /****************** Bit definition for FMC_PCR register *******************/
<> 147:30b64687e01f 4793 #define FMC_PCR_PWAITEN 0x00000002U /*!<Wait feature enable bit */
<> 147:30b64687e01f 4794 #define FMC_PCR_PBKEN 0x00000004U /*!<PC Card/NAND Flash memory bank enable bit */
<> 147:30b64687e01f 4795 #define FMC_PCR_PTYP 0x00000008U /*!<Memory type */
<> 147:30b64687e01f 4796 #define FMC_PCR_PWID 0x00000030U /*!<PWID[1:0] bits (NAND Flash databus width) */
<> 147:30b64687e01f 4797 #define FMC_PCR_PWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4798 #define FMC_PCR_PWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4799 #define FMC_PCR_ECCEN 0x00000040U /*!<ECC computation logic enable bit */
<> 147:30b64687e01f 4800 #define FMC_PCR_TCLR 0x00001E00U /*!<TCLR[3:0] bits (CLE to RE delay) */
<> 147:30b64687e01f 4801 #define FMC_PCR_TCLR_0 0x00000200U /*!<Bit 0 */
<> 147:30b64687e01f 4802 #define FMC_PCR_TCLR_1 0x00000400U /*!<Bit 1 */
<> 147:30b64687e01f 4803 #define FMC_PCR_TCLR_2 0x00000800U /*!<Bit 2 */
<> 147:30b64687e01f 4804 #define FMC_PCR_TCLR_3 0x00001000U /*!<Bit 3 */
<> 147:30b64687e01f 4805 #define FMC_PCR_TAR 0x0001E000U /*!<TAR[3:0] bits (ALE to RE delay) */
<> 147:30b64687e01f 4806 #define FMC_PCR_TAR_0 0x00002000U /*!<Bit 0 */
<> 147:30b64687e01f 4807 #define FMC_PCR_TAR_1 0x00004000U /*!<Bit 1 */
<> 147:30b64687e01f 4808 #define FMC_PCR_TAR_2 0x00008000U /*!<Bit 2 */
<> 147:30b64687e01f 4809 #define FMC_PCR_TAR_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 4810 #define FMC_PCR_ECCPS 0x000E0000U /*!<ECCPS[2:0] bits (ECC page size) */
<> 147:30b64687e01f 4811 #define FMC_PCR_ECCPS_0 0x00020000U /*!<Bit 0 */
<> 147:30b64687e01f 4812 #define FMC_PCR_ECCPS_1 0x00040000U /*!<Bit 1 */
<> 147:30b64687e01f 4813 #define FMC_PCR_ECCPS_2 0x00080000U /*!<Bit 2 */
<> 147:30b64687e01f 4814
<> 147:30b64687e01f 4815 /******************* Bit definition for FMC_SR register *******************/
<> 147:30b64687e01f 4816 #define FMC_SR_IRS 0x01U /*!<Interrupt Rising Edge status */
<> 147:30b64687e01f 4817 #define FMC_SR_ILS 0x02U /*!<Interrupt Level status */
<> 147:30b64687e01f 4818 #define FMC_SR_IFS 0x04U /*!<Interrupt Falling Edge status */
<> 147:30b64687e01f 4819 #define FMC_SR_IREN 0x08U /*!<Interrupt Rising Edge detection Enable bit */
<> 147:30b64687e01f 4820 #define FMC_SR_ILEN 0x10U /*!<Interrupt Level detection Enable bit */
<> 147:30b64687e01f 4821 #define FMC_SR_IFEN 0x20U /*!<Interrupt Falling Edge detection Enable bit */
<> 147:30b64687e01f 4822 #define FMC_SR_FEMPT 0x40U /*!<FIFO empty */
<> 147:30b64687e01f 4823
<> 147:30b64687e01f 4824 /****************** Bit definition for FMC_PMEM register ******************/
<> 147:30b64687e01f 4825 #define FMC_PMEM_MEMSET3 0x000000FFU /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
<> 147:30b64687e01f 4826 #define FMC_PMEM_MEMSET3_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4827 #define FMC_PMEM_MEMSET3_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4828 #define FMC_PMEM_MEMSET3_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4829 #define FMC_PMEM_MEMSET3_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4830 #define FMC_PMEM_MEMSET3_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 4831 #define FMC_PMEM_MEMSET3_5 0x00000020U /*!<Bit 5 */
<> 147:30b64687e01f 4832 #define FMC_PMEM_MEMSET3_6 0x00000040U /*!<Bit 6 */
<> 147:30b64687e01f 4833 #define FMC_PMEM_MEMSET3_7 0x00000080U /*!<Bit 7 */
<> 147:30b64687e01f 4834 #define FMC_PMEM_MEMWAIT3 0x0000FF00U /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
<> 147:30b64687e01f 4835 #define FMC_PMEM_MEMWAIT3_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4836 #define FMC_PMEM_MEMWAIT3_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4837 #define FMC_PMEM_MEMWAIT3_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4838 #define FMC_PMEM_MEMWAIT3_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4839 #define FMC_PMEM_MEMWAIT3_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4840 #define FMC_PMEM_MEMWAIT3_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4841 #define FMC_PMEM_MEMWAIT3_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4842 #define FMC_PMEM_MEMWAIT3_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4843 #define FMC_PMEM_MEMHOLD3 0x00FF0000U /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
<> 147:30b64687e01f 4844 #define FMC_PMEM_MEMHOLD3_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4845 #define FMC_PMEM_MEMHOLD3_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4846 #define FMC_PMEM_MEMHOLD3_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4847 #define FMC_PMEM_MEMHOLD3_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4848 #define FMC_PMEM_MEMHOLD3_4 0x00100000U /*!<Bit 4 */
<> 147:30b64687e01f 4849 #define FMC_PMEM_MEMHOLD3_5 0x00200000U /*!<Bit 5 */
<> 147:30b64687e01f 4850 #define FMC_PMEM_MEMHOLD3_6 0x00400000U /*!<Bit 6 */
<> 147:30b64687e01f 4851 #define FMC_PMEM_MEMHOLD3_7 0x00800000U /*!<Bit 7 */
<> 147:30b64687e01f 4852 #define FMC_PMEM_MEMHIZ3 0xFF000000U /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
<> 147:30b64687e01f 4853 #define FMC_PMEM_MEMHIZ3_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4854 #define FMC_PMEM_MEMHIZ3_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4855 #define FMC_PMEM_MEMHIZ3_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4856 #define FMC_PMEM_MEMHIZ3_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4857 #define FMC_PMEM_MEMHIZ3_4 0x10000000U /*!<Bit 4 */
<> 147:30b64687e01f 4858 #define FMC_PMEM_MEMHIZ3_5 0x20000000U /*!<Bit 5 */
<> 147:30b64687e01f 4859 #define FMC_PMEM_MEMHIZ3_6 0x40000000U /*!<Bit 6 */
<> 147:30b64687e01f 4860 #define FMC_PMEM_MEMHIZ3_7 0x80000000U /*!<Bit 7 */
<> 147:30b64687e01f 4861
<> 147:30b64687e01f 4862 /****************** Bit definition for FMC_PATT register ******************/
<> 147:30b64687e01f 4863 #define FMC_PATT_ATTSET3 0x000000FFU /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
<> 147:30b64687e01f 4864 #define FMC_PATT_ATTSET3_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4865 #define FMC_PATT_ATTSET3_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4866 #define FMC_PATT_ATTSET3_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4867 #define FMC_PATT_ATTSET3_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4868 #define FMC_PATT_ATTSET3_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 4869 #define FMC_PATT_ATTSET3_5 0x00000020U /*!<Bit 5 */
<> 147:30b64687e01f 4870 #define FMC_PATT_ATTSET3_6 0x00000040U /*!<Bit 6 */
<> 147:30b64687e01f 4871 #define FMC_PATT_ATTSET3_7 0x00000080U /*!<Bit 7 */
<> 147:30b64687e01f 4872 #define FMC_PATT_ATTWAIT3 0x0000FF00U /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
<> 147:30b64687e01f 4873 #define FMC_PATT_ATTWAIT3_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4874 #define FMC_PATT_ATTWAIT3_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4875 #define FMC_PATT_ATTWAIT3_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4876 #define FMC_PATT_ATTWAIT3_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4877 #define FMC_PATT_ATTWAIT3_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 4878 #define FMC_PATT_ATTWAIT3_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 4879 #define FMC_PATT_ATTWAIT3_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 4880 #define FMC_PATT_ATTWAIT3_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 4881 #define FMC_PATT_ATTHOLD3 0x00FF0000U /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
<> 147:30b64687e01f 4882 #define FMC_PATT_ATTHOLD3_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4883 #define FMC_PATT_ATTHOLD3_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4884 #define FMC_PATT_ATTHOLD3_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4885 #define FMC_PATT_ATTHOLD3_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 4886 #define FMC_PATT_ATTHOLD3_4 0x00100000U /*!<Bit 4 */
<> 147:30b64687e01f 4887 #define FMC_PATT_ATTHOLD3_5 0x00200000U /*!<Bit 5 */
<> 147:30b64687e01f 4888 #define FMC_PATT_ATTHOLD3_6 0x00400000U /*!<Bit 6 */
<> 147:30b64687e01f 4889 #define FMC_PATT_ATTHOLD3_7 0x00800000U /*!<Bit 7 */
<> 147:30b64687e01f 4890 #define FMC_PATT_ATTHIZ3 0xFF000000U /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
<> 147:30b64687e01f 4891 #define FMC_PATT_ATTHIZ3_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4892 #define FMC_PATT_ATTHIZ3_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4893 #define FMC_PATT_ATTHIZ3_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4894 #define FMC_PATT_ATTHIZ3_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 4895 #define FMC_PATT_ATTHIZ3_4 0x10000000U /*!<Bit 4 */
<> 147:30b64687e01f 4896 #define FMC_PATT_ATTHIZ3_5 0x20000000U /*!<Bit 5 */
<> 147:30b64687e01f 4897 #define FMC_PATT_ATTHIZ3_6 0x40000000U /*!<Bit 6 */
<> 147:30b64687e01f 4898 #define FMC_PATT_ATTHIZ3_7 0x80000000U /*!<Bit 7 */
<> 147:30b64687e01f 4899
<> 147:30b64687e01f 4900 /****************** Bit definition for FMC_ECCR register ******************/
<> 147:30b64687e01f 4901 #define FMC_ECCR_ECC3 0xFFFFFFFFU /*!<ECC result */
<> 147:30b64687e01f 4902
<> 147:30b64687e01f 4903 /****************** Bit definition for FMC_SDCR1 register ******************/
<> 147:30b64687e01f 4904 #define FMC_SDCR1_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
<> 147:30b64687e01f 4905 #define FMC_SDCR1_NC_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4906 #define FMC_SDCR1_NC_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4907 #define FMC_SDCR1_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
<> 147:30b64687e01f 4908 #define FMC_SDCR1_NR_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4909 #define FMC_SDCR1_NR_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4910 #define FMC_SDCR1_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
<> 147:30b64687e01f 4911 #define FMC_SDCR1_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4912 #define FMC_SDCR1_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4913 #define FMC_SDCR1_NB 0x00000040U /*!<Number of internal bank */
<> 147:30b64687e01f 4914 #define FMC_SDCR1_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
<> 147:30b64687e01f 4915 #define FMC_SDCR1_CAS_0 0x00000080U /*!<Bit 0 */
<> 147:30b64687e01f 4916 #define FMC_SDCR1_CAS_1 0x00000100U /*!<Bit 1 */
<> 147:30b64687e01f 4917 #define FMC_SDCR1_WP 0x00000200U /*!<Write protection */
<> 147:30b64687e01f 4918 #define FMC_SDCR1_SDCLK 0x00000C00U /*!<SDRAM clock configuration */
<> 147:30b64687e01f 4919 #define FMC_SDCR1_SDCLK_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 4920 #define FMC_SDCR1_SDCLK_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 4921 #define FMC_SDCR1_RBURST 0x00001000U /*!<Read burst */
<> 147:30b64687e01f 4922 #define FMC_SDCR1_RPIPE 0x00006000U /*!<Write protection */
<> 147:30b64687e01f 4923 #define FMC_SDCR1_RPIPE_0 0x00002000U /*!<Bit 0 */
<> 147:30b64687e01f 4924 #define FMC_SDCR1_RPIPE_1 0x00004000U /*!<Bit 1 */
<> 147:30b64687e01f 4925
<> 147:30b64687e01f 4926 /****************** Bit definition for FMC_SDCR2 register ******************/
<> 147:30b64687e01f 4927 #define FMC_SDCR2_NC 0x00000003U /*!<NC[1:0] bits (Number of column bits) */
<> 147:30b64687e01f 4928 #define FMC_SDCR2_NC_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4929 #define FMC_SDCR2_NC_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4930 #define FMC_SDCR2_NR 0x0000000CU /*!<NR[1:0] bits (Number of row bits) */
<> 147:30b64687e01f 4931 #define FMC_SDCR2_NR_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 4932 #define FMC_SDCR2_NR_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 4933 #define FMC_SDCR2_MWID 0x00000030U /*!<NR[1:0] bits (Number of row bits) */
<> 147:30b64687e01f 4934 #define FMC_SDCR2_MWID_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4935 #define FMC_SDCR2_MWID_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4936 #define FMC_SDCR2_NB 0x00000040U /*!<Number of internal bank */
<> 147:30b64687e01f 4937 #define FMC_SDCR2_CAS 0x00000180U /*!<CAS[1:0] bits (CAS latency) */
<> 147:30b64687e01f 4938 #define FMC_SDCR2_CAS_0 0x00000080U /*!<Bit 0 */
<> 147:30b64687e01f 4939 #define FMC_SDCR2_CAS_1 0x00000100U /*!<Bit 1 */
<> 147:30b64687e01f 4940 #define FMC_SDCR2_WP 0x00000200U /*!<Write protection */
<> 147:30b64687e01f 4941 #define FMC_SDCR2_SDCLK 0x00000C00U /*!<SDCLK[1:0] (SDRAM clock configuration) */
<> 147:30b64687e01f 4942 #define FMC_SDCR2_SDCLK_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 4943 #define FMC_SDCR2_SDCLK_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 4944 #define FMC_SDCR2_RBURST 0x00001000U /*!<Read burst */
<> 147:30b64687e01f 4945 #define FMC_SDCR2_RPIPE 0x00006000U /*!<RPIPE[1:0](Read pipe) */
<> 147:30b64687e01f 4946 #define FMC_SDCR2_RPIPE_0 0x00002000U /*!<Bit 0 */
<> 147:30b64687e01f 4947 #define FMC_SDCR2_RPIPE_1 0x00004000U /*!<Bit 1 */
<> 147:30b64687e01f 4948
<> 147:30b64687e01f 4949 /****************** Bit definition for FMC_SDTR1 register ******************/
<> 147:30b64687e01f 4950 #define FMC_SDTR1_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
<> 147:30b64687e01f 4951 #define FMC_SDTR1_TMRD_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4952 #define FMC_SDTR1_TMRD_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4953 #define FMC_SDTR1_TMRD_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4954 #define FMC_SDTR1_TMRD_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4955 #define FMC_SDTR1_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
<> 147:30b64687e01f 4956 #define FMC_SDTR1_TXSR_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4957 #define FMC_SDTR1_TXSR_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4958 #define FMC_SDTR1_TXSR_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4959 #define FMC_SDTR1_TXSR_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4960 #define FMC_SDTR1_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
<> 147:30b64687e01f 4961 #define FMC_SDTR1_TRAS_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4962 #define FMC_SDTR1_TRAS_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4963 #define FMC_SDTR1_TRAS_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4964 #define FMC_SDTR1_TRAS_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4965 #define FMC_SDTR1_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
<> 147:30b64687e01f 4966 #define FMC_SDTR1_TRC_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 4967 #define FMC_SDTR1_TRC_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 4968 #define FMC_SDTR1_TRC_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 4969 #define FMC_SDTR1_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
<> 147:30b64687e01f 4970 #define FMC_SDTR1_TWR_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 4971 #define FMC_SDTR1_TWR_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 4972 #define FMC_SDTR1_TWR_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 4973 #define FMC_SDTR1_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
<> 147:30b64687e01f 4974 #define FMC_SDTR1_TRP_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 4975 #define FMC_SDTR1_TRP_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 4976 #define FMC_SDTR1_TRP_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 4977 #define FMC_SDTR1_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
<> 147:30b64687e01f 4978 #define FMC_SDTR1_TRCD_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 4979 #define FMC_SDTR1_TRCD_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 4980 #define FMC_SDTR1_TRCD_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 4981
<> 147:30b64687e01f 4982 /****************** Bit definition for FMC_SDTR2 register ******************/
<> 147:30b64687e01f 4983 #define FMC_SDTR2_TMRD 0x0000000FU /*!<TMRD[3:0] bits (Load mode register to active) */
<> 147:30b64687e01f 4984 #define FMC_SDTR2_TMRD_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 4985 #define FMC_SDTR2_TMRD_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 4986 #define FMC_SDTR2_TMRD_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 4987 #define FMC_SDTR2_TMRD_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 4988 #define FMC_SDTR2_TXSR 0x000000F0U /*!<TXSR[3:0] bits (Exit self refresh) */
<> 147:30b64687e01f 4989 #define FMC_SDTR2_TXSR_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 4990 #define FMC_SDTR2_TXSR_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 4991 #define FMC_SDTR2_TXSR_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 4992 #define FMC_SDTR2_TXSR_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 4993 #define FMC_SDTR2_TRAS 0x00000F00U /*!<TRAS[3:0] bits (Self refresh time) */
<> 147:30b64687e01f 4994 #define FMC_SDTR2_TRAS_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 4995 #define FMC_SDTR2_TRAS_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 4996 #define FMC_SDTR2_TRAS_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 4997 #define FMC_SDTR2_TRAS_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 4998 #define FMC_SDTR2_TRC 0x0000F000U /*!<TRC[2:0] bits (Row cycle delay) */
<> 147:30b64687e01f 4999 #define FMC_SDTR2_TRC_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 5000 #define FMC_SDTR2_TRC_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 5001 #define FMC_SDTR2_TRC_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 5002 #define FMC_SDTR2_TWR 0x000F0000U /*!<TRC[2:0] bits (Write recovery delay) */
<> 147:30b64687e01f 5003 #define FMC_SDTR2_TWR_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 5004 #define FMC_SDTR2_TWR_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 5005 #define FMC_SDTR2_TWR_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 5006 #define FMC_SDTR2_TRP 0x00F00000U /*!<TRP[2:0] bits (Row precharge delay) */
<> 147:30b64687e01f 5007 #define FMC_SDTR2_TRP_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 5008 #define FMC_SDTR2_TRP_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 5009 #define FMC_SDTR2_TRP_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 5010 #define FMC_SDTR2_TRCD 0x0F000000U /*!<TRP[2:0] bits (Row to column delay) */
<> 147:30b64687e01f 5011 #define FMC_SDTR2_TRCD_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 5012 #define FMC_SDTR2_TRCD_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 5013 #define FMC_SDTR2_TRCD_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 5014
<> 147:30b64687e01f 5015 /****************** Bit definition for FMC_SDCMR register ******************/
<> 147:30b64687e01f 5016 #define FMC_SDCMR_MODE 0x00000007U /*!<MODE[2:0] bits (Command mode) */
<> 147:30b64687e01f 5017 #define FMC_SDCMR_MODE_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 5018 #define FMC_SDCMR_MODE_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 5019 #define FMC_SDCMR_MODE_2 0x00000003U /*!<Bit 2 */
<> 147:30b64687e01f 5020 #define FMC_SDCMR_CTB2 0x00000008U /*!<Command target 2 */
<> 147:30b64687e01f 5021 #define FMC_SDCMR_CTB1 0x00000010U /*!<Command target 1 */
<> 147:30b64687e01f 5022 #define FMC_SDCMR_NRFS 0x000001E0U /*!<NRFS[3:0] bits (Number of auto-refresh) */
<> 147:30b64687e01f 5023 #define FMC_SDCMR_NRFS_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 5024 #define FMC_SDCMR_NRFS_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 5025 #define FMC_SDCMR_NRFS_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 5026 #define FMC_SDCMR_NRFS_3 0x00000100U /*!<Bit 3 */
<> 147:30b64687e01f 5027 #define FMC_SDCMR_MRD 0x003FFE00U /*!<MRD[12:0] bits (Mode register definition) */
<> 147:30b64687e01f 5028
<> 147:30b64687e01f 5029 /****************** Bit definition for FMC_SDRTR register ******************/
<> 147:30b64687e01f 5030 #define FMC_SDRTR_CRE 0x00000001U /*!<Clear refresh error flag */
<> 147:30b64687e01f 5031 #define FMC_SDRTR_COUNT 0x00003FFEU /*!<COUNT[12:0] bits (Refresh timer count) */
<> 147:30b64687e01f 5032 #define FMC_SDRTR_REIE 0x00004000U /*!<RES interupt enable */
<> 147:30b64687e01f 5033
<> 147:30b64687e01f 5034 /****************** Bit definition for FMC_SDSR register ******************/
<> 147:30b64687e01f 5035 #define FMC_SDSR_RE 0x00000001U /*!<Refresh error flag */
<> 147:30b64687e01f 5036 #define FMC_SDSR_MODES1 0x00000006U /*!<MODES1[1:0]bits (Status mode for bank 1) */
<> 147:30b64687e01f 5037 #define FMC_SDSR_MODES1_0 0x00000002U /*!<Bit 0 */
<> 147:30b64687e01f 5038 #define FMC_SDSR_MODES1_1 0x00000004U /*!<Bit 1 */
<> 147:30b64687e01f 5039 #define FMC_SDSR_MODES2 0x00000018U /*!<MODES2[1:0]bits (Status mode for bank 2) */
<> 147:30b64687e01f 5040 #define FMC_SDSR_MODES2_0 0x00000008U /*!<Bit 0 */
<> 147:30b64687e01f 5041 #define FMC_SDSR_MODES2_1 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 5042 #define FMC_SDSR_BUSY 0x00000020U /*!<Busy status */
<> 147:30b64687e01f 5043
<> 147:30b64687e01f 5044 /******************************************************************************/
<> 147:30b64687e01f 5045 /* */
<> 147:30b64687e01f 5046 /* General Purpose I/O */
<> 147:30b64687e01f 5047 /* */
<> 147:30b64687e01f 5048 /******************************************************************************/
<> 147:30b64687e01f 5049 /****************** Bits definition for GPIO_MODER register *****************/
<> 147:30b64687e01f 5050 #define GPIO_MODER_MODER0 0x00000003U
<> 147:30b64687e01f 5051 #define GPIO_MODER_MODER0_0 0x00000001U
<> 147:30b64687e01f 5052 #define GPIO_MODER_MODER0_1 0x00000002U
<> 147:30b64687e01f 5053 #define GPIO_MODER_MODER1 0x0000000CU
<> 147:30b64687e01f 5054 #define GPIO_MODER_MODER1_0 0x00000004U
<> 147:30b64687e01f 5055 #define GPIO_MODER_MODER1_1 0x00000008U
<> 147:30b64687e01f 5056 #define GPIO_MODER_MODER2 0x00000030U
<> 147:30b64687e01f 5057 #define GPIO_MODER_MODER2_0 0x00000010U
<> 147:30b64687e01f 5058 #define GPIO_MODER_MODER2_1 0x00000020U
<> 147:30b64687e01f 5059 #define GPIO_MODER_MODER3 0x000000C0U
<> 147:30b64687e01f 5060 #define GPIO_MODER_MODER3_0 0x00000040U
<> 147:30b64687e01f 5061 #define GPIO_MODER_MODER3_1 0x00000080U
<> 147:30b64687e01f 5062 #define GPIO_MODER_MODER4 0x00000300U
<> 147:30b64687e01f 5063 #define GPIO_MODER_MODER4_0 0x00000100U
<> 147:30b64687e01f 5064 #define GPIO_MODER_MODER4_1 0x00000200U
<> 147:30b64687e01f 5065 #define GPIO_MODER_MODER5 0x00000C00U
<> 147:30b64687e01f 5066 #define GPIO_MODER_MODER5_0 0x00000400U
<> 147:30b64687e01f 5067 #define GPIO_MODER_MODER5_1 0x00000800U
<> 147:30b64687e01f 5068 #define GPIO_MODER_MODER6 0x00003000U
<> 147:30b64687e01f 5069 #define GPIO_MODER_MODER6_0 0x00001000U
<> 147:30b64687e01f 5070 #define GPIO_MODER_MODER6_1 0x00002000U
<> 147:30b64687e01f 5071 #define GPIO_MODER_MODER7 0x0000C000U
<> 147:30b64687e01f 5072 #define GPIO_MODER_MODER7_0 0x00004000U
<> 147:30b64687e01f 5073 #define GPIO_MODER_MODER7_1 0x00008000U
<> 147:30b64687e01f 5074 #define GPIO_MODER_MODER8 0x00030000U
<> 147:30b64687e01f 5075 #define GPIO_MODER_MODER8_0 0x00010000U
<> 147:30b64687e01f 5076 #define GPIO_MODER_MODER8_1 0x00020000U
<> 147:30b64687e01f 5077 #define GPIO_MODER_MODER9 0x000C0000U
<> 147:30b64687e01f 5078 #define GPIO_MODER_MODER9_0 0x00040000U
<> 147:30b64687e01f 5079 #define GPIO_MODER_MODER9_1 0x00080000U
<> 147:30b64687e01f 5080 #define GPIO_MODER_MODER10 0x00300000U
<> 147:30b64687e01f 5081 #define GPIO_MODER_MODER10_0 0x00100000U
<> 147:30b64687e01f 5082 #define GPIO_MODER_MODER10_1 0x00200000U
<> 147:30b64687e01f 5083 #define GPIO_MODER_MODER11 0x00C00000U
<> 147:30b64687e01f 5084 #define GPIO_MODER_MODER11_0 0x00400000U
<> 147:30b64687e01f 5085 #define GPIO_MODER_MODER11_1 0x00800000U
<> 147:30b64687e01f 5086 #define GPIO_MODER_MODER12 0x03000000U
<> 147:30b64687e01f 5087 #define GPIO_MODER_MODER12_0 0x01000000U
<> 147:30b64687e01f 5088 #define GPIO_MODER_MODER12_1 0x02000000U
<> 147:30b64687e01f 5089 #define GPIO_MODER_MODER13 0x0C000000U
<> 147:30b64687e01f 5090 #define GPIO_MODER_MODER13_0 0x04000000U
<> 147:30b64687e01f 5091 #define GPIO_MODER_MODER13_1 0x08000000U
<> 147:30b64687e01f 5092 #define GPIO_MODER_MODER14 0x30000000U
<> 147:30b64687e01f 5093 #define GPIO_MODER_MODER14_0 0x10000000U
<> 147:30b64687e01f 5094 #define GPIO_MODER_MODER14_1 0x20000000U
<> 147:30b64687e01f 5095 #define GPIO_MODER_MODER15 0xC0000000U
<> 147:30b64687e01f 5096 #define GPIO_MODER_MODER15_0 0x40000000U
<> 147:30b64687e01f 5097 #define GPIO_MODER_MODER15_1 0x80000000U
<> 147:30b64687e01f 5098
<> 147:30b64687e01f 5099 /****************** Bits definition for GPIO_OTYPER register ****************/
<> 147:30b64687e01f 5100 #define GPIO_OTYPER_OT_0 0x00000001U
<> 147:30b64687e01f 5101 #define GPIO_OTYPER_OT_1 0x00000002U
<> 147:30b64687e01f 5102 #define GPIO_OTYPER_OT_2 0x00000004U
<> 147:30b64687e01f 5103 #define GPIO_OTYPER_OT_3 0x00000008U
<> 147:30b64687e01f 5104 #define GPIO_OTYPER_OT_4 0x00000010U
<> 147:30b64687e01f 5105 #define GPIO_OTYPER_OT_5 0x00000020U
<> 147:30b64687e01f 5106 #define GPIO_OTYPER_OT_6 0x00000040U
<> 147:30b64687e01f 5107 #define GPIO_OTYPER_OT_7 0x00000080U
<> 147:30b64687e01f 5108 #define GPIO_OTYPER_OT_8 0x00000100U
<> 147:30b64687e01f 5109 #define GPIO_OTYPER_OT_9 0x00000200U
<> 147:30b64687e01f 5110 #define GPIO_OTYPER_OT_10 0x00000400U
<> 147:30b64687e01f 5111 #define GPIO_OTYPER_OT_11 0x00000800U
<> 147:30b64687e01f 5112 #define GPIO_OTYPER_OT_12 0x00001000U
<> 147:30b64687e01f 5113 #define GPIO_OTYPER_OT_13 0x00002000U
<> 147:30b64687e01f 5114 #define GPIO_OTYPER_OT_14 0x00004000U
<> 147:30b64687e01f 5115 #define GPIO_OTYPER_OT_15 0x00008000U
<> 147:30b64687e01f 5116
<> 147:30b64687e01f 5117 /****************** Bits definition for GPIO_OSPEEDR register ***************/
<> 147:30b64687e01f 5118 #define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
<> 147:30b64687e01f 5119 #define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
<> 147:30b64687e01f 5120 #define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
<> 147:30b64687e01f 5121 #define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
<> 147:30b64687e01f 5122 #define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
<> 147:30b64687e01f 5123 #define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
<> 147:30b64687e01f 5124 #define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
<> 147:30b64687e01f 5125 #define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
<> 147:30b64687e01f 5126 #define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
<> 147:30b64687e01f 5127 #define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
<> 147:30b64687e01f 5128 #define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
<> 147:30b64687e01f 5129 #define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
<> 147:30b64687e01f 5130 #define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
<> 147:30b64687e01f 5131 #define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
<> 147:30b64687e01f 5132 #define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
<> 147:30b64687e01f 5133 #define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
<> 147:30b64687e01f 5134 #define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
<> 147:30b64687e01f 5135 #define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
<> 147:30b64687e01f 5136 #define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
<> 147:30b64687e01f 5137 #define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
<> 147:30b64687e01f 5138 #define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
<> 147:30b64687e01f 5139 #define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
<> 147:30b64687e01f 5140 #define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
<> 147:30b64687e01f 5141 #define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
<> 147:30b64687e01f 5142 #define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
<> 147:30b64687e01f 5143 #define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
<> 147:30b64687e01f 5144 #define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
<> 147:30b64687e01f 5145 #define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
<> 147:30b64687e01f 5146 #define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
<> 147:30b64687e01f 5147 #define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
<> 147:30b64687e01f 5148 #define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
<> 147:30b64687e01f 5149 #define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
<> 147:30b64687e01f 5150 #define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
<> 147:30b64687e01f 5151 #define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
<> 147:30b64687e01f 5152 #define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
<> 147:30b64687e01f 5153 #define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
<> 147:30b64687e01f 5154 #define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
<> 147:30b64687e01f 5155 #define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
<> 147:30b64687e01f 5156 #define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
<> 147:30b64687e01f 5157 #define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
<> 147:30b64687e01f 5158 #define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
<> 147:30b64687e01f 5159 #define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
<> 147:30b64687e01f 5160 #define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
<> 147:30b64687e01f 5161 #define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
<> 147:30b64687e01f 5162 #define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
<> 147:30b64687e01f 5163 #define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
<> 147:30b64687e01f 5164 #define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
<> 147:30b64687e01f 5165 #define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
<> 147:30b64687e01f 5166
<> 147:30b64687e01f 5167 /****************** Bits definition for GPIO_PUPDR register *****************/
<> 147:30b64687e01f 5168 #define GPIO_PUPDR_PUPDR0 0x00000003U
<> 147:30b64687e01f 5169 #define GPIO_PUPDR_PUPDR0_0 0x00000001U
<> 147:30b64687e01f 5170 #define GPIO_PUPDR_PUPDR0_1 0x00000002U
<> 147:30b64687e01f 5171 #define GPIO_PUPDR_PUPDR1 0x0000000CU
<> 147:30b64687e01f 5172 #define GPIO_PUPDR_PUPDR1_0 0x00000004U
<> 147:30b64687e01f 5173 #define GPIO_PUPDR_PUPDR1_1 0x00000008U
<> 147:30b64687e01f 5174 #define GPIO_PUPDR_PUPDR2 0x00000030U
<> 147:30b64687e01f 5175 #define GPIO_PUPDR_PUPDR2_0 0x00000010U
<> 147:30b64687e01f 5176 #define GPIO_PUPDR_PUPDR2_1 0x00000020U
<> 147:30b64687e01f 5177 #define GPIO_PUPDR_PUPDR3 0x000000C0U
<> 147:30b64687e01f 5178 #define GPIO_PUPDR_PUPDR3_0 0x00000040U
<> 147:30b64687e01f 5179 #define GPIO_PUPDR_PUPDR3_1 0x00000080U
<> 147:30b64687e01f 5180 #define GPIO_PUPDR_PUPDR4 0x00000300U
<> 147:30b64687e01f 5181 #define GPIO_PUPDR_PUPDR4_0 0x00000100U
<> 147:30b64687e01f 5182 #define GPIO_PUPDR_PUPDR4_1 0x00000200U
<> 147:30b64687e01f 5183 #define GPIO_PUPDR_PUPDR5 0x00000C00U
<> 147:30b64687e01f 5184 #define GPIO_PUPDR_PUPDR5_0 0x00000400U
<> 147:30b64687e01f 5185 #define GPIO_PUPDR_PUPDR5_1 0x00000800U
<> 147:30b64687e01f 5186 #define GPIO_PUPDR_PUPDR6 0x00003000U
<> 147:30b64687e01f 5187 #define GPIO_PUPDR_PUPDR6_0 0x00001000U
<> 147:30b64687e01f 5188 #define GPIO_PUPDR_PUPDR6_1 0x00002000U
<> 147:30b64687e01f 5189 #define GPIO_PUPDR_PUPDR7 0x0000C000U
<> 147:30b64687e01f 5190 #define GPIO_PUPDR_PUPDR7_0 0x00004000U
<> 147:30b64687e01f 5191 #define GPIO_PUPDR_PUPDR7_1 0x00008000U
<> 147:30b64687e01f 5192 #define GPIO_PUPDR_PUPDR8 0x00030000U
<> 147:30b64687e01f 5193 #define GPIO_PUPDR_PUPDR8_0 0x00010000U
<> 147:30b64687e01f 5194 #define GPIO_PUPDR_PUPDR8_1 0x00020000U
<> 147:30b64687e01f 5195 #define GPIO_PUPDR_PUPDR9 0x000C0000U
<> 147:30b64687e01f 5196 #define GPIO_PUPDR_PUPDR9_0 0x00040000U
<> 147:30b64687e01f 5197 #define GPIO_PUPDR_PUPDR9_1 0x00080000U
<> 147:30b64687e01f 5198 #define GPIO_PUPDR_PUPDR10 0x00300000U
<> 147:30b64687e01f 5199 #define GPIO_PUPDR_PUPDR10_0 0x00100000U
<> 147:30b64687e01f 5200 #define GPIO_PUPDR_PUPDR10_1 0x00200000U
<> 147:30b64687e01f 5201 #define GPIO_PUPDR_PUPDR11 0x00C00000U
<> 147:30b64687e01f 5202 #define GPIO_PUPDR_PUPDR11_0 0x00400000U
<> 147:30b64687e01f 5203 #define GPIO_PUPDR_PUPDR11_1 0x00800000U
<> 147:30b64687e01f 5204 #define GPIO_PUPDR_PUPDR12 0x03000000U
<> 147:30b64687e01f 5205 #define GPIO_PUPDR_PUPDR12_0 0x01000000U
<> 147:30b64687e01f 5206 #define GPIO_PUPDR_PUPDR12_1 0x02000000U
<> 147:30b64687e01f 5207 #define GPIO_PUPDR_PUPDR13 0x0C000000U
<> 147:30b64687e01f 5208 #define GPIO_PUPDR_PUPDR13_0 0x04000000U
<> 147:30b64687e01f 5209 #define GPIO_PUPDR_PUPDR13_1 0x08000000U
<> 147:30b64687e01f 5210 #define GPIO_PUPDR_PUPDR14 0x30000000U
<> 147:30b64687e01f 5211 #define GPIO_PUPDR_PUPDR14_0 0x10000000U
<> 147:30b64687e01f 5212 #define GPIO_PUPDR_PUPDR14_1 0x20000000U
<> 147:30b64687e01f 5213 #define GPIO_PUPDR_PUPDR15 0xC0000000U
<> 147:30b64687e01f 5214 #define GPIO_PUPDR_PUPDR15_0 0x40000000U
<> 147:30b64687e01f 5215 #define GPIO_PUPDR_PUPDR15_1 0x80000000U
<> 147:30b64687e01f 5216
<> 147:30b64687e01f 5217 /****************** Bits definition for GPIO_IDR register *******************/
<> 147:30b64687e01f 5218 #define GPIO_IDR_IDR_0 0x00000001U
<> 147:30b64687e01f 5219 #define GPIO_IDR_IDR_1 0x00000002U
<> 147:30b64687e01f 5220 #define GPIO_IDR_IDR_2 0x00000004U
<> 147:30b64687e01f 5221 #define GPIO_IDR_IDR_3 0x00000008U
<> 147:30b64687e01f 5222 #define GPIO_IDR_IDR_4 0x00000010U
<> 147:30b64687e01f 5223 #define GPIO_IDR_IDR_5 0x00000020U
<> 147:30b64687e01f 5224 #define GPIO_IDR_IDR_6 0x00000040U
<> 147:30b64687e01f 5225 #define GPIO_IDR_IDR_7 0x00000080U
<> 147:30b64687e01f 5226 #define GPIO_IDR_IDR_8 0x00000100U
<> 147:30b64687e01f 5227 #define GPIO_IDR_IDR_9 0x00000200U
<> 147:30b64687e01f 5228 #define GPIO_IDR_IDR_10 0x00000400U
<> 147:30b64687e01f 5229 #define GPIO_IDR_IDR_11 0x00000800U
<> 147:30b64687e01f 5230 #define GPIO_IDR_IDR_12 0x00001000U
<> 147:30b64687e01f 5231 #define GPIO_IDR_IDR_13 0x00002000U
<> 147:30b64687e01f 5232 #define GPIO_IDR_IDR_14 0x00004000U
<> 147:30b64687e01f 5233 #define GPIO_IDR_IDR_15 0x00008000U
<> 147:30b64687e01f 5234
<> 147:30b64687e01f 5235 /****************** Bits definition for GPIO_ODR register *******************/
<> 147:30b64687e01f 5236 #define GPIO_ODR_ODR_0 0x00000001U
<> 147:30b64687e01f 5237 #define GPIO_ODR_ODR_1 0x00000002U
<> 147:30b64687e01f 5238 #define GPIO_ODR_ODR_2 0x00000004U
<> 147:30b64687e01f 5239 #define GPIO_ODR_ODR_3 0x00000008U
<> 147:30b64687e01f 5240 #define GPIO_ODR_ODR_4 0x00000010U
<> 147:30b64687e01f 5241 #define GPIO_ODR_ODR_5 0x00000020U
<> 147:30b64687e01f 5242 #define GPIO_ODR_ODR_6 0x00000040U
<> 147:30b64687e01f 5243 #define GPIO_ODR_ODR_7 0x00000080U
<> 147:30b64687e01f 5244 #define GPIO_ODR_ODR_8 0x00000100U
<> 147:30b64687e01f 5245 #define GPIO_ODR_ODR_9 0x00000200U
<> 147:30b64687e01f 5246 #define GPIO_ODR_ODR_10 0x00000400U
<> 147:30b64687e01f 5247 #define GPIO_ODR_ODR_11 0x00000800U
<> 147:30b64687e01f 5248 #define GPIO_ODR_ODR_12 0x00001000U
<> 147:30b64687e01f 5249 #define GPIO_ODR_ODR_13 0x00002000U
<> 147:30b64687e01f 5250 #define GPIO_ODR_ODR_14 0x00004000U
<> 147:30b64687e01f 5251 #define GPIO_ODR_ODR_15 0x00008000U
<> 147:30b64687e01f 5252
<> 147:30b64687e01f 5253 /****************** Bits definition for GPIO_BSRR register ******************/
<> 147:30b64687e01f 5254 #define GPIO_BSRR_BS_0 0x00000001U
<> 147:30b64687e01f 5255 #define GPIO_BSRR_BS_1 0x00000002U
<> 147:30b64687e01f 5256 #define GPIO_BSRR_BS_2 0x00000004U
<> 147:30b64687e01f 5257 #define GPIO_BSRR_BS_3 0x00000008U
<> 147:30b64687e01f 5258 #define GPIO_BSRR_BS_4 0x00000010U
<> 147:30b64687e01f 5259 #define GPIO_BSRR_BS_5 0x00000020U
<> 147:30b64687e01f 5260 #define GPIO_BSRR_BS_6 0x00000040U
<> 147:30b64687e01f 5261 #define GPIO_BSRR_BS_7 0x00000080U
<> 147:30b64687e01f 5262 #define GPIO_BSRR_BS_8 0x00000100U
<> 147:30b64687e01f 5263 #define GPIO_BSRR_BS_9 0x00000200U
<> 147:30b64687e01f 5264 #define GPIO_BSRR_BS_10 0x00000400U
<> 147:30b64687e01f 5265 #define GPIO_BSRR_BS_11 0x00000800U
<> 147:30b64687e01f 5266 #define GPIO_BSRR_BS_12 0x00001000U
<> 147:30b64687e01f 5267 #define GPIO_BSRR_BS_13 0x00002000U
<> 147:30b64687e01f 5268 #define GPIO_BSRR_BS_14 0x00004000U
<> 147:30b64687e01f 5269 #define GPIO_BSRR_BS_15 0x00008000U
<> 147:30b64687e01f 5270 #define GPIO_BSRR_BR_0 0x00010000U
<> 147:30b64687e01f 5271 #define GPIO_BSRR_BR_1 0x00020000U
<> 147:30b64687e01f 5272 #define GPIO_BSRR_BR_2 0x00040000U
<> 147:30b64687e01f 5273 #define GPIO_BSRR_BR_3 0x00080000U
<> 147:30b64687e01f 5274 #define GPIO_BSRR_BR_4 0x00100000U
<> 147:30b64687e01f 5275 #define GPIO_BSRR_BR_5 0x00200000U
<> 147:30b64687e01f 5276 #define GPIO_BSRR_BR_6 0x00400000U
<> 147:30b64687e01f 5277 #define GPIO_BSRR_BR_7 0x00800000U
<> 147:30b64687e01f 5278 #define GPIO_BSRR_BR_8 0x01000000U
<> 147:30b64687e01f 5279 #define GPIO_BSRR_BR_9 0x02000000U
<> 147:30b64687e01f 5280 #define GPIO_BSRR_BR_10 0x04000000U
<> 147:30b64687e01f 5281 #define GPIO_BSRR_BR_11 0x08000000U
<> 147:30b64687e01f 5282 #define GPIO_BSRR_BR_12 0x10000000U
<> 147:30b64687e01f 5283 #define GPIO_BSRR_BR_13 0x20000000U
<> 147:30b64687e01f 5284 #define GPIO_BSRR_BR_14 0x40000000U
<> 147:30b64687e01f 5285 #define GPIO_BSRR_BR_15 0x80000000U
<> 147:30b64687e01f 5286
<> 147:30b64687e01f 5287 /****************** Bit definition for GPIO_LCKR register *********************/
<> 147:30b64687e01f 5288 #define GPIO_LCKR_LCK0 0x00000001U
<> 147:30b64687e01f 5289 #define GPIO_LCKR_LCK1 0x00000002U
<> 147:30b64687e01f 5290 #define GPIO_LCKR_LCK2 0x00000004U
<> 147:30b64687e01f 5291 #define GPIO_LCKR_LCK3 0x00000008U
<> 147:30b64687e01f 5292 #define GPIO_LCKR_LCK4 0x00000010U
<> 147:30b64687e01f 5293 #define GPIO_LCKR_LCK5 0x00000020U
<> 147:30b64687e01f 5294 #define GPIO_LCKR_LCK6 0x00000040U
<> 147:30b64687e01f 5295 #define GPIO_LCKR_LCK7 0x00000080U
<> 147:30b64687e01f 5296 #define GPIO_LCKR_LCK8 0x00000100U
<> 147:30b64687e01f 5297 #define GPIO_LCKR_LCK9 0x00000200U
<> 147:30b64687e01f 5298 #define GPIO_LCKR_LCK10 0x00000400U
<> 147:30b64687e01f 5299 #define GPIO_LCKR_LCK11 0x00000800U
<> 147:30b64687e01f 5300 #define GPIO_LCKR_LCK12 0x00001000U
<> 147:30b64687e01f 5301 #define GPIO_LCKR_LCK13 0x00002000U
<> 147:30b64687e01f 5302 #define GPIO_LCKR_LCK14 0x00004000U
<> 147:30b64687e01f 5303 #define GPIO_LCKR_LCK15 0x00008000U
<> 147:30b64687e01f 5304 #define GPIO_LCKR_LCKK 0x00010000U
<> 147:30b64687e01f 5305
<> 147:30b64687e01f 5306
<> 147:30b64687e01f 5307 /******************************************************************************/
<> 147:30b64687e01f 5308 /* */
<> 147:30b64687e01f 5309 /* Inter-integrated Circuit Interface (I2C) */
<> 147:30b64687e01f 5310 /* */
<> 147:30b64687e01f 5311 /******************************************************************************/
<> 147:30b64687e01f 5312 /******************* Bit definition for I2C_CR1 register *******************/
<> 147:30b64687e01f 5313 #define I2C_CR1_PE 0x00000001U /*!< Peripheral enable */
<> 147:30b64687e01f 5314 #define I2C_CR1_TXIE 0x00000002U /*!< TX interrupt enable */
<> 147:30b64687e01f 5315 #define I2C_CR1_RXIE 0x00000004U /*!< RX interrupt enable */
<> 147:30b64687e01f 5316 #define I2C_CR1_ADDRIE 0x00000008U /*!< Address match interrupt enable */
<> 147:30b64687e01f 5317 #define I2C_CR1_NACKIE 0x00000010U /*!< NACK received interrupt enable */
<> 147:30b64687e01f 5318 #define I2C_CR1_STOPIE 0x00000020U /*!< STOP detection interrupt enable */
<> 147:30b64687e01f 5319 #define I2C_CR1_TCIE 0x00000040U /*!< Transfer complete interrupt enable */
<> 147:30b64687e01f 5320 #define I2C_CR1_ERRIE 0x00000080U /*!< Errors interrupt enable */
<> 147:30b64687e01f 5321 #define I2C_CR1_DNF 0x00000F00U /*!< Digital noise filter */
<> 147:30b64687e01f 5322 #define I2C_CR1_ANFOFF 0x00001000U /*!< Analog noise filter OFF */
<> 147:30b64687e01f 5323 #define I2C_CR1_TXDMAEN 0x00004000U /*!< DMA transmission requests enable */
<> 147:30b64687e01f 5324 #define I2C_CR1_RXDMAEN 0x00008000U /*!< DMA reception requests enable */
<> 147:30b64687e01f 5325 #define I2C_CR1_SBC 0x00010000U /*!< Slave byte control */
<> 147:30b64687e01f 5326 #define I2C_CR1_NOSTRETCH 0x00020000U /*!< Clock stretching disable */
<> 147:30b64687e01f 5327 #define I2C_CR1_GCEN 0x00080000U /*!< General call enable */
<> 147:30b64687e01f 5328 #define I2C_CR1_SMBHEN 0x00100000U /*!< SMBus host address enable */
<> 147:30b64687e01f 5329 #define I2C_CR1_SMBDEN 0x00200000U /*!< SMBus device default address enable */
<> 147:30b64687e01f 5330 #define I2C_CR1_ALERTEN 0x00400000U /*!< SMBus alert enable */
<> 147:30b64687e01f 5331 #define I2C_CR1_PECEN 0x00800000U /*!< PEC enable */
<> 147:30b64687e01f 5332
<> 147:30b64687e01f 5333
<> 147:30b64687e01f 5334 /****************** Bit definition for I2C_CR2 register ********************/
<> 147:30b64687e01f 5335 #define I2C_CR2_SADD 0x000003FFU /*!< Slave address (master mode) */
<> 147:30b64687e01f 5336 #define I2C_CR2_RD_WRN 0x00000400U /*!< Transfer direction (master mode) */
<> 147:30b64687e01f 5337 #define I2C_CR2_ADD10 0x00000800U /*!< 10-bit addressing mode (master mode) */
<> 147:30b64687e01f 5338 #define I2C_CR2_HEAD10R 0x00001000U /*!< 10-bit address header only read direction (master mode) */
<> 147:30b64687e01f 5339 #define I2C_CR2_START 0x00002000U /*!< START generation */
<> 147:30b64687e01f 5340 #define I2C_CR2_STOP 0x00004000U /*!< STOP generation (master mode) */
<> 147:30b64687e01f 5341 #define I2C_CR2_NACK 0x00008000U /*!< NACK generation (slave mode) */
<> 147:30b64687e01f 5342 #define I2C_CR2_NBYTES 0x00FF0000U /*!< Number of bytes */
<> 147:30b64687e01f 5343 #define I2C_CR2_RELOAD 0x01000000U /*!< NBYTES reload mode */
<> 147:30b64687e01f 5344 #define I2C_CR2_AUTOEND 0x02000000U /*!< Automatic end mode (master mode) */
<> 147:30b64687e01f 5345 #define I2C_CR2_PECBYTE 0x04000000U /*!< Packet error checking byte */
<> 147:30b64687e01f 5346
<> 147:30b64687e01f 5347 /******************* Bit definition for I2C_OAR1 register ******************/
<> 147:30b64687e01f 5348 #define I2C_OAR1_OA1 0x000003FFU /*!< Interface own address 1 */
<> 147:30b64687e01f 5349 #define I2C_OAR1_OA1MODE 0x00000400U /*!< Own address 1 10-bit mode */
<> 147:30b64687e01f 5350 #define I2C_OAR1_OA1EN 0x00008000U /*!< Own address 1 enable */
<> 147:30b64687e01f 5351
<> 147:30b64687e01f 5352 /******************* Bit definition for I2C_OAR2 register ******************/
<> 147:30b64687e01f 5353 #define I2C_OAR2_OA2 0x000000FEU /*!< Interface own address 2 */
<> 147:30b64687e01f 5354 #define I2C_OAR2_OA2MSK 0x00000700U /*!< Own address 2 masks */
<> 147:30b64687e01f 5355 #define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */
<> 147:30b64687e01f 5356 #define I2C_OAR2_OA2MASK01 0x00000100U /*!< OA2[1] is masked, Only OA2[7:2] are compared */
<> 147:30b64687e01f 5357 #define I2C_OAR2_OA2MASK02 0x00000200U /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
<> 147:30b64687e01f 5358 #define I2C_OAR2_OA2MASK03 0x00000300U /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
<> 147:30b64687e01f 5359 #define I2C_OAR2_OA2MASK04 0x00000400U /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
<> 147:30b64687e01f 5360 #define I2C_OAR2_OA2MASK05 0x00000500U /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
<> 147:30b64687e01f 5361 #define I2C_OAR2_OA2MASK06 0x00000600U /*!< OA2[6:1] is masked, Only OA2[7] are compared */
<> 147:30b64687e01f 5362 #define I2C_OAR2_OA2MASK07 0x00000700U /*!< OA2[7:1] is masked, No comparison is done */
<> 147:30b64687e01f 5363 #define I2C_OAR2_OA2EN 0x00008000U /*!< Own address 2 enable */
<> 147:30b64687e01f 5364
<> 147:30b64687e01f 5365 /******************* Bit definition for I2C_TIMINGR register *******************/
<> 147:30b64687e01f 5366 #define I2C_TIMINGR_SCLL 0x000000FFU /*!< SCL low period (master mode) */
<> 147:30b64687e01f 5367 #define I2C_TIMINGR_SCLH 0x0000FF00U /*!< SCL high period (master mode) */
<> 147:30b64687e01f 5368 #define I2C_TIMINGR_SDADEL 0x000F0000U /*!< Data hold time */
<> 147:30b64687e01f 5369 #define I2C_TIMINGR_SCLDEL 0x00F00000U /*!< Data setup time */
<> 147:30b64687e01f 5370 #define I2C_TIMINGR_PRESC 0xF0000000U /*!< Timings prescaler */
<> 147:30b64687e01f 5371
<> 147:30b64687e01f 5372 /******************* Bit definition for I2C_TIMEOUTR register *******************/
<> 147:30b64687e01f 5373 #define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /*!< Bus timeout A */
<> 147:30b64687e01f 5374 #define I2C_TIMEOUTR_TIDLE 0x00001000U /*!< Idle clock timeout detection */
<> 147:30b64687e01f 5375 #define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /*!< Clock timeout enable */
<> 147:30b64687e01f 5376 #define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /*!< Bus timeout B */
<> 147:30b64687e01f 5377 #define I2C_TIMEOUTR_TEXTEN 0x80000000U /*!< Extended clock timeout enable */
<> 147:30b64687e01f 5378
<> 147:30b64687e01f 5379 /****************** Bit definition for I2C_ISR register *********************/
<> 147:30b64687e01f 5380 #define I2C_ISR_TXE 0x00000001U /*!< Transmit data register empty */
<> 147:30b64687e01f 5381 #define I2C_ISR_TXIS 0x00000002U /*!< Transmit interrupt status */
<> 147:30b64687e01f 5382 #define I2C_ISR_RXNE 0x00000004U /*!< Receive data register not empty */
<> 147:30b64687e01f 5383 #define I2C_ISR_ADDR 0x00000008U /*!< Address matched (slave mode) */
<> 147:30b64687e01f 5384 #define I2C_ISR_NACKF 0x00000010U /*!< NACK received flag */
<> 147:30b64687e01f 5385 #define I2C_ISR_STOPF 0x00000020U /*!< STOP detection flag */
<> 147:30b64687e01f 5386 #define I2C_ISR_TC 0x00000040U /*!< Transfer complete (master mode) */
<> 147:30b64687e01f 5387 #define I2C_ISR_TCR 0x00000080U /*!< Transfer complete reload */
<> 147:30b64687e01f 5388 #define I2C_ISR_BERR 0x00000100U /*!< Bus error */
<> 147:30b64687e01f 5389 #define I2C_ISR_ARLO 0x00000200U /*!< Arbitration lost */
<> 147:30b64687e01f 5390 #define I2C_ISR_OVR 0x00000400U /*!< Overrun/Underrun */
<> 147:30b64687e01f 5391 #define I2C_ISR_PECERR 0x00000800U /*!< PEC error in reception */
<> 147:30b64687e01f 5392 #define I2C_ISR_TIMEOUT 0x00001000U /*!< Timeout or Tlow detection flag */
<> 147:30b64687e01f 5393 #define I2C_ISR_ALERT 0x00002000U /*!< SMBus alert */
<> 147:30b64687e01f 5394 #define I2C_ISR_BUSY 0x00008000U /*!< Bus busy */
<> 147:30b64687e01f 5395 #define I2C_ISR_DIR 0x00010000U /*!< Transfer direction (slave mode) */
<> 147:30b64687e01f 5396 #define I2C_ISR_ADDCODE 0x00FE0000U /*!< Address match code (slave mode) */
<> 147:30b64687e01f 5397
<> 147:30b64687e01f 5398 /****************** Bit definition for I2C_ICR register *********************/
<> 147:30b64687e01f 5399 #define I2C_ICR_ADDRCF 0x00000008U /*!< Address matched clear flag */
<> 147:30b64687e01f 5400 #define I2C_ICR_NACKCF 0x00000010U /*!< NACK clear flag */
<> 147:30b64687e01f 5401 #define I2C_ICR_STOPCF 0x00000020U /*!< STOP detection clear flag */
<> 147:30b64687e01f 5402 #define I2C_ICR_BERRCF 0x00000100U /*!< Bus error clear flag */
<> 147:30b64687e01f 5403 #define I2C_ICR_ARLOCF 0x00000200U /*!< Arbitration lost clear flag */
<> 147:30b64687e01f 5404 #define I2C_ICR_OVRCF 0x00000400U /*!< Overrun/Underrun clear flag */
<> 147:30b64687e01f 5405 #define I2C_ICR_PECCF 0x00000800U /*!< PAC error clear flag */
<> 147:30b64687e01f 5406 #define I2C_ICR_TIMOUTCF 0x00001000U /*!< Timeout clear flag */
<> 147:30b64687e01f 5407 #define I2C_ICR_ALERTCF 0x00002000U /*!< Alert clear flag */
<> 147:30b64687e01f 5408
<> 147:30b64687e01f 5409 /****************** Bit definition for I2C_PECR register *********************/
<> 147:30b64687e01f 5410 #define I2C_PECR_PEC 0x000000FFU /*!< PEC register */
<> 147:30b64687e01f 5411
<> 147:30b64687e01f 5412 /****************** Bit definition for I2C_RXDR register *********************/
<> 147:30b64687e01f 5413 #define I2C_RXDR_RXDATA 0x000000FFU /*!< 8-bit receive data */
<> 147:30b64687e01f 5414
<> 147:30b64687e01f 5415 /****************** Bit definition for I2C_TXDR register *********************/
<> 147:30b64687e01f 5416 #define I2C_TXDR_TXDATA 0x000000FFU /*!< 8-bit transmit data */
<> 147:30b64687e01f 5417
<> 147:30b64687e01f 5418
<> 147:30b64687e01f 5419 /******************************************************************************/
<> 147:30b64687e01f 5420 /* */
<> 147:30b64687e01f 5421 /* Independent WATCHDOG */
<> 147:30b64687e01f 5422 /* */
<> 147:30b64687e01f 5423 /******************************************************************************/
<> 147:30b64687e01f 5424 /******************* Bit definition for IWDG_KR register ********************/
<> 147:30b64687e01f 5425 #define IWDG_KR_KEY 0xFFFFU /*!<Key value (write only, read 0000h) */
<> 147:30b64687e01f 5426
<> 147:30b64687e01f 5427 /******************* Bit definition for IWDG_PR register ********************/
<> 147:30b64687e01f 5428 #define IWDG_PR_PR 0x07U /*!<PR[2:0] (Prescaler divider) */
<> 147:30b64687e01f 5429 #define IWDG_PR_PR_0 0x01U /*!<Bit 0 */
<> 147:30b64687e01f 5430 #define IWDG_PR_PR_1 0x02U /*!<Bit 1 */
<> 147:30b64687e01f 5431 #define IWDG_PR_PR_2 0x04U /*!<Bit 2 */
<> 147:30b64687e01f 5432
<> 147:30b64687e01f 5433 /******************* Bit definition for IWDG_RLR register *******************/
<> 147:30b64687e01f 5434 #define IWDG_RLR_RL 0x0FFFU /*!<Watchdog counter reload value */
<> 147:30b64687e01f 5435
<> 147:30b64687e01f 5436 /******************* Bit definition for IWDG_SR register ********************/
<> 147:30b64687e01f 5437 #define IWDG_SR_PVU 0x01U /*!< Watchdog prescaler value update */
<> 147:30b64687e01f 5438 #define IWDG_SR_RVU 0x02U /*!< Watchdog counter reload value update */
<> 147:30b64687e01f 5439 #define IWDG_SR_WVU 0x04U /*!< Watchdog counter window value update */
<> 147:30b64687e01f 5440
<> 147:30b64687e01f 5441 /******************* Bit definition for IWDG_KR register ********************/
<> 147:30b64687e01f 5442 #define IWDG_WINR_WIN 0x0FFFU /*!< Watchdog counter window value */
<> 147:30b64687e01f 5443
<> 147:30b64687e01f 5444 /******************************************************************************/
<> 147:30b64687e01f 5445 /* */
<> 147:30b64687e01f 5446 /* LCD-TFT Display Controller (LTDC) */
<> 147:30b64687e01f 5447 /* */
<> 147:30b64687e01f 5448 /******************************************************************************/
<> 147:30b64687e01f 5449
<> 147:30b64687e01f 5450 /******************** Bit definition for LTDC_SSCR register *****************/
<> 147:30b64687e01f 5451
<> 147:30b64687e01f 5452 #define LTDC_SSCR_VSH 0x000007FFU /*!< Vertical Synchronization Height */
<> 147:30b64687e01f 5453 #define LTDC_SSCR_HSW 0x0FFF0000U /*!< Horizontal Synchronization Width */
<> 147:30b64687e01f 5454
<> 147:30b64687e01f 5455 /******************** Bit definition for LTDC_BPCR register *****************/
<> 147:30b64687e01f 5456
<> 147:30b64687e01f 5457 #define LTDC_BPCR_AVBP 0x000007FFU /*!< Accumulated Vertical Back Porch */
<> 147:30b64687e01f 5458 #define LTDC_BPCR_AHBP 0x0FFF0000U /*!< Accumulated Horizontal Back Porch */
<> 147:30b64687e01f 5459
<> 147:30b64687e01f 5460 /******************** Bit definition for LTDC_AWCR register *****************/
<> 147:30b64687e01f 5461
<> 147:30b64687e01f 5462 #define LTDC_AWCR_AAH 0x000007FFU /*!< Accumulated Active heigh */
<> 147:30b64687e01f 5463 #define LTDC_AWCR_AAW 0x0FFF0000U /*!< Accumulated Active Width */
<> 147:30b64687e01f 5464
<> 147:30b64687e01f 5465 /******************** Bit definition for LTDC_TWCR register *****************/
<> 147:30b64687e01f 5466
<> 147:30b64687e01f 5467 #define LTDC_TWCR_TOTALH 0x000007FFU /*!< Total Heigh */
<> 147:30b64687e01f 5468 #define LTDC_TWCR_TOTALW 0x0FFF0000U /*!< Total Width */
<> 147:30b64687e01f 5469
<> 147:30b64687e01f 5470 /******************** Bit definition for LTDC_GCR register ******************/
<> 147:30b64687e01f 5471
<> 147:30b64687e01f 5472 #define LTDC_GCR_LTDCEN 0x00000001U /*!< LCD-TFT controller enable bit */
<> 147:30b64687e01f 5473 #define LTDC_GCR_DBW 0x00000070U /*!< Dither Blue Width */
<> 147:30b64687e01f 5474 #define LTDC_GCR_DGW 0x00000700U /*!< Dither Green Width */
<> 147:30b64687e01f 5475 #define LTDC_GCR_DRW 0x00007000U /*!< Dither Red Width */
<> 147:30b64687e01f 5476 #define LTDC_GCR_DEN 0x00010000U /*!< Dither Enable */
<> 147:30b64687e01f 5477 #define LTDC_GCR_PCPOL 0x10000000U /*!< Pixel Clock Polarity */
<> 147:30b64687e01f 5478 #define LTDC_GCR_DEPOL 0x20000000U /*!< Data Enable Polarity */
<> 147:30b64687e01f 5479 #define LTDC_GCR_VSPOL 0x40000000U /*!< Vertical Synchronization Polarity */
<> 147:30b64687e01f 5480 #define LTDC_GCR_HSPOL 0x80000000U /*!< Horizontal Synchronization Polarity */
<> 147:30b64687e01f 5481
<> 147:30b64687e01f 5482
<> 147:30b64687e01f 5483 /******************** Bit definition for LTDC_SRCR register *****************/
<> 147:30b64687e01f 5484
<> 147:30b64687e01f 5485 #define LTDC_SRCR_IMR 0x00000001U /*!< Immediate Reload */
<> 147:30b64687e01f 5486 #define LTDC_SRCR_VBR 0x00000002U /*!< Vertical Blanking Reload */
<> 147:30b64687e01f 5487
<> 147:30b64687e01f 5488 /******************** Bit definition for LTDC_BCCR register *****************/
<> 147:30b64687e01f 5489
<> 147:30b64687e01f 5490 #define LTDC_BCCR_BCBLUE 0x000000FFU /*!< Background Blue value */
<> 147:30b64687e01f 5491 #define LTDC_BCCR_BCGREEN 0x0000FF00U /*!< Background Green value */
<> 147:30b64687e01f 5492 #define LTDC_BCCR_BCRED 0x00FF0000U /*!< Background Red value */
<> 147:30b64687e01f 5493
<> 147:30b64687e01f 5494 /******************** Bit definition for LTDC_IER register ******************/
<> 147:30b64687e01f 5495
<> 147:30b64687e01f 5496 #define LTDC_IER_LIE 0x00000001U /*!< Line Interrupt Enable */
<> 147:30b64687e01f 5497 #define LTDC_IER_FUIE 0x00000002U /*!< FIFO Underrun Interrupt Enable */
<> 147:30b64687e01f 5498 #define LTDC_IER_TERRIE 0x00000004U /*!< Transfer Error Interrupt Enable */
<> 147:30b64687e01f 5499 #define LTDC_IER_RRIE 0x00000008U /*!< Register Reload interrupt enable */
<> 147:30b64687e01f 5500
<> 147:30b64687e01f 5501 /******************** Bit definition for LTDC_ISR register ******************/
<> 147:30b64687e01f 5502
<> 147:30b64687e01f 5503 #define LTDC_ISR_LIF 0x00000001U /*!< Line Interrupt Flag */
<> 147:30b64687e01f 5504 #define LTDC_ISR_FUIF 0x00000002U /*!< FIFO Underrun Interrupt Flag */
<> 147:30b64687e01f 5505 #define LTDC_ISR_TERRIF 0x00000004U /*!< Transfer Error Interrupt Flag */
<> 147:30b64687e01f 5506 #define LTDC_ISR_RRIF 0x00000008U /*!< Register Reload interrupt Flag */
<> 147:30b64687e01f 5507
<> 147:30b64687e01f 5508 /******************** Bit definition for LTDC_ICR register ******************/
<> 147:30b64687e01f 5509
<> 147:30b64687e01f 5510 #define LTDC_ICR_CLIF 0x00000001U /*!< Clears the Line Interrupt Flag */
<> 147:30b64687e01f 5511 #define LTDC_ICR_CFUIF 0x00000002U /*!< Clears the FIFO Underrun Interrupt Flag */
<> 147:30b64687e01f 5512 #define LTDC_ICR_CTERRIF 0x00000004U /*!< Clears the Transfer Error Interrupt Flag */
<> 147:30b64687e01f 5513 #define LTDC_ICR_CRRIF 0x00000008U /*!< Clears Register Reload interrupt Flag */
<> 147:30b64687e01f 5514
<> 147:30b64687e01f 5515 /******************** Bit definition for LTDC_LIPCR register ****************/
<> 147:30b64687e01f 5516
<> 147:30b64687e01f 5517 #define LTDC_LIPCR_LIPOS 0x000007FFU /*!< Line Interrupt Position */
<> 147:30b64687e01f 5518
<> 147:30b64687e01f 5519 /******************** Bit definition for LTDC_CPSR register *****************/
<> 147:30b64687e01f 5520
<> 147:30b64687e01f 5521 #define LTDC_CPSR_CYPOS 0x0000FFFFU /*!< Current Y Position */
<> 147:30b64687e01f 5522 #define LTDC_CPSR_CXPOS 0xFFFF0000U /*!< Current X Position */
<> 147:30b64687e01f 5523
<> 147:30b64687e01f 5524 /******************** Bit definition for LTDC_CDSR register *****************/
<> 147:30b64687e01f 5525
<> 147:30b64687e01f 5526 #define LTDC_CDSR_VDES 0x00000001U /*!< Vertical Data Enable Status */
<> 147:30b64687e01f 5527 #define LTDC_CDSR_HDES 0x00000002U /*!< Horizontal Data Enable Status */
<> 147:30b64687e01f 5528 #define LTDC_CDSR_VSYNCS 0x00000004U /*!< Vertical Synchronization Status */
<> 147:30b64687e01f 5529 #define LTDC_CDSR_HSYNCS 0x00000008U /*!< Horizontal Synchronization Status */
<> 147:30b64687e01f 5530
<> 147:30b64687e01f 5531 /******************** Bit definition for LTDC_LxCR register *****************/
<> 147:30b64687e01f 5532
<> 147:30b64687e01f 5533 #define LTDC_LxCR_LEN 0x00000001U /*!< Layer Enable */
<> 147:30b64687e01f 5534 #define LTDC_LxCR_COLKEN 0x00000002U /*!< Color Keying Enable */
<> 147:30b64687e01f 5535 #define LTDC_LxCR_CLUTEN 0x00000010U /*!< Color Lockup Table Enable */
<> 147:30b64687e01f 5536
<> 147:30b64687e01f 5537 /******************** Bit definition for LTDC_LxWHPCR register **************/
<> 147:30b64687e01f 5538
<> 147:30b64687e01f 5539 #define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /*!< Window Horizontal Start Position */
<> 147:30b64687e01f 5540 #define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /*!< Window Horizontal Stop Position */
<> 147:30b64687e01f 5541
<> 147:30b64687e01f 5542 /******************** Bit definition for LTDC_LxWVPCR register **************/
<> 147:30b64687e01f 5543
<> 147:30b64687e01f 5544 #define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /*!< Window Vertical Start Position */
<> 147:30b64687e01f 5545 #define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /*!< Window Vertical Stop Position */
<> 147:30b64687e01f 5546
<> 147:30b64687e01f 5547 /******************** Bit definition for LTDC_LxCKCR register ***************/
<> 147:30b64687e01f 5548
<> 147:30b64687e01f 5549 #define LTDC_LxCKCR_CKBLUE 0x000000FFU /*!< Color Key Blue value */
<> 147:30b64687e01f 5550 #define LTDC_LxCKCR_CKGREEN 0x0000FF00U /*!< Color Key Green value */
<> 147:30b64687e01f 5551 #define LTDC_LxCKCR_CKRED 0x00FF0000U /*!< Color Key Red value */
<> 147:30b64687e01f 5552
<> 147:30b64687e01f 5553 /******************** Bit definition for LTDC_LxPFCR register ***************/
<> 147:30b64687e01f 5554
<> 147:30b64687e01f 5555 #define LTDC_LxPFCR_PF 0x00000007U /*!< Pixel Format */
<> 147:30b64687e01f 5556
<> 147:30b64687e01f 5557 /******************** Bit definition for LTDC_LxCACR register ***************/
<> 147:30b64687e01f 5558
<> 147:30b64687e01f 5559 #define LTDC_LxCACR_CONSTA 0x000000FFU /*!< Constant Alpha */
<> 147:30b64687e01f 5560
<> 147:30b64687e01f 5561 /******************** Bit definition for LTDC_LxDCCR register ***************/
<> 147:30b64687e01f 5562
<> 147:30b64687e01f 5563 #define LTDC_LxDCCR_DCBLUE 0x000000FFU /*!< Default Color Blue */
<> 147:30b64687e01f 5564 #define LTDC_LxDCCR_DCGREEN 0x0000FF00U /*!< Default Color Green */
<> 147:30b64687e01f 5565 #define LTDC_LxDCCR_DCRED 0x00FF0000U /*!< Default Color Red */
<> 147:30b64687e01f 5566 #define LTDC_LxDCCR_DCALPHA 0xFF000000U /*!< Default Color Alpha */
<> 147:30b64687e01f 5567
<> 147:30b64687e01f 5568 /******************** Bit definition for LTDC_LxBFCR register ***************/
<> 147:30b64687e01f 5569
<> 147:30b64687e01f 5570 #define LTDC_LxBFCR_BF2 0x00000007U /*!< Blending Factor 2 */
<> 147:30b64687e01f 5571 #define LTDC_LxBFCR_BF1 0x00000700U /*!< Blending Factor 1 */
<> 147:30b64687e01f 5572
<> 147:30b64687e01f 5573 /******************** Bit definition for LTDC_LxCFBAR register **************/
<> 147:30b64687e01f 5574
<> 147:30b64687e01f 5575 #define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /*!< Color Frame Buffer Start Address */
<> 147:30b64687e01f 5576
<> 147:30b64687e01f 5577 /******************** Bit definition for LTDC_LxCFBLR register **************/
<> 147:30b64687e01f 5578
<> 147:30b64687e01f 5579 #define LTDC_LxCFBLR_CFBLL 0x00001FFFU /*!< Color Frame Buffer Line Length */
<> 147:30b64687e01f 5580 #define LTDC_LxCFBLR_CFBP 0x1FFF0000U /*!< Color Frame Buffer Pitch in bytes */
<> 147:30b64687e01f 5581
<> 147:30b64687e01f 5582 /******************** Bit definition for LTDC_LxCFBLNR register *************/
<> 147:30b64687e01f 5583
<> 147:30b64687e01f 5584 #define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /*!< Frame Buffer Line Number */
<> 147:30b64687e01f 5585
<> 147:30b64687e01f 5586 /******************** Bit definition for LTDC_LxCLUTWR register *************/
<> 147:30b64687e01f 5587
<> 147:30b64687e01f 5588 #define LTDC_LxCLUTWR_BLUE 0x000000FFU /*!< Blue value */
<> 147:30b64687e01f 5589 #define LTDC_LxCLUTWR_GREEN 0x0000FF00U /*!< Green value */
<> 147:30b64687e01f 5590 #define LTDC_LxCLUTWR_RED 0x00FF0000U /*!< Red value */
<> 147:30b64687e01f 5591 #define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /*!< CLUT address */
<> 147:30b64687e01f 5592
<> 147:30b64687e01f 5593 /******************************************************************************/
<> 147:30b64687e01f 5594 /* */
<> 147:30b64687e01f 5595 /* Power Control */
<> 147:30b64687e01f 5596 /* */
<> 147:30b64687e01f 5597 /******************************************************************************/
<> 147:30b64687e01f 5598 /******************** Bit definition for PWR_CR1 register ********************/
<> 147:30b64687e01f 5599 #define PWR_CR1_LPDS 0x00000001U /*!< Low-Power Deepsleep */
<> 147:30b64687e01f 5600 #define PWR_CR1_PDDS 0x00000002U /*!< Power Down Deepsleep */
<> 147:30b64687e01f 5601 #define PWR_CR1_CSBF 0x00000008U /*!< Clear Standby Flag */
<> 147:30b64687e01f 5602 #define PWR_CR1_PVDE 0x00000010U /*!< Power Voltage Detector Enable */
<> 147:30b64687e01f 5603 #define PWR_CR1_PLS 0x000000E0U /*!< PLS[2:0] bits (PVD Level Selection) */
<> 147:30b64687e01f 5604 #define PWR_CR1_PLS_0 0x00000020U /*!< Bit 0 */
<> 147:30b64687e01f 5605 #define PWR_CR1_PLS_1 0x00000040U /*!< Bit 1 */
<> 147:30b64687e01f 5606 #define PWR_CR1_PLS_2 0x00000080U /*!< Bit 2 */
<> 147:30b64687e01f 5607
<> 147:30b64687e01f 5608 /*!< PVD level configuration */
<> 147:30b64687e01f 5609 #define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */
<> 147:30b64687e01f 5610 #define PWR_CR1_PLS_LEV1 0x00000020U /*!< PVD level 1 */
<> 147:30b64687e01f 5611 #define PWR_CR1_PLS_LEV2 0x00000040U /*!< PVD level 2 */
<> 147:30b64687e01f 5612 #define PWR_CR1_PLS_LEV3 0x00000060U /*!< PVD level 3 */
<> 147:30b64687e01f 5613 #define PWR_CR1_PLS_LEV4 0x00000080U /*!< PVD level 4 */
<> 147:30b64687e01f 5614 #define PWR_CR1_PLS_LEV5 0x000000A0U /*!< PVD level 5 */
<> 147:30b64687e01f 5615 #define PWR_CR1_PLS_LEV6 0x000000C0U /*!< PVD level 6 */
<> 147:30b64687e01f 5616 #define PWR_CR1_PLS_LEV7 0x000000E0U /*!< PVD level 7 */
<> 147:30b64687e01f 5617 #define PWR_CR1_DBP 0x00000100U /*!< Disable Backup Domain write protection */
<> 147:30b64687e01f 5618 #define PWR_CR1_FPDS 0x00000200U /*!< Flash power down in Stop mode */
<> 147:30b64687e01f 5619 #define PWR_CR1_LPUDS 0x00000400U /*!< Low-power regulator in deepsleep under-drive mode */
<> 147:30b64687e01f 5620 #define PWR_CR1_MRUDS 0x00000800U /*!< Main regulator in deepsleep under-drive mode */
<> 147:30b64687e01f 5621 #define PWR_CR1_ADCDC1 0x00002000U /*!< Refer to AN4073 on how to use this bit */
<> 147:30b64687e01f 5622 #define PWR_CR1_VOS 0x0000C000U /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
<> 147:30b64687e01f 5623 #define PWR_CR1_VOS_0 0x00004000U /*!< Bit 0 */
<> 147:30b64687e01f 5624 #define PWR_CR1_VOS_1 0x00008000U /*!< Bit 1 */
<> 147:30b64687e01f 5625 #define PWR_CR1_ODEN 0x00010000U /*!< Over Drive enable */
<> 147:30b64687e01f 5626 #define PWR_CR1_ODSWEN 0x00020000U /*!< Over Drive switch enabled */
<> 147:30b64687e01f 5627 #define PWR_CR1_UDEN 0x000C0000U /*!< Under Drive enable in stop mode */
<> 147:30b64687e01f 5628 #define PWR_CR1_UDEN_0 0x00040000U /*!< Bit 0 */
<> 147:30b64687e01f 5629 #define PWR_CR1_UDEN_1 0x00080000U /*!< Bit 1 */
<> 147:30b64687e01f 5630
<> 147:30b64687e01f 5631 /******************* Bit definition for PWR_CSR1 register ********************/
<> 147:30b64687e01f 5632 #define PWR_CSR1_WUIF 0x00000001U /*!< Wake up internal Flag */
<> 147:30b64687e01f 5633 #define PWR_CSR1_SBF 0x00000002U /*!< Standby Flag */
<> 147:30b64687e01f 5634 #define PWR_CSR1_PVDO 0x00000004U /*!< PVD Output */
<> 147:30b64687e01f 5635 #define PWR_CSR1_BRR 0x00000008U /*!< Backup regulator ready */
<> 147:30b64687e01f 5636 #define PWR_CSR1_EIWUP 0x00000100U /*!< Enable internal wakeup */
<> 147:30b64687e01f 5637 #define PWR_CSR1_BRE 0x00000200U /*!< Backup regulator enable */
<> 147:30b64687e01f 5638 #define PWR_CSR1_VOSRDY 0x00004000U /*!< Regulator voltage scaling output selection ready */
<> 147:30b64687e01f 5639 #define PWR_CSR1_ODRDY 0x00010000U /*!< Over Drive generator ready */
<> 147:30b64687e01f 5640 #define PWR_CSR1_ODSWRDY 0x00020000U /*!< Over Drive Switch ready */
<> 147:30b64687e01f 5641 #define PWR_CSR1_UDRDY 0x000C0000U /*!< Under Drive ready */
<> 147:30b64687e01f 5642
<> 147:30b64687e01f 5643
<> 147:30b64687e01f 5644 /******************** Bit definition for PWR_CR2 register ********************/
<> 147:30b64687e01f 5645 #define PWR_CR2_CWUPF1 0x00000001U /*!< Clear Wakeup Pin Flag for PA0 */
<> 147:30b64687e01f 5646 #define PWR_CR2_CWUPF2 0x00000002U /*!< Clear Wakeup Pin Flag for PA2 */
<> 147:30b64687e01f 5647 #define PWR_CR2_CWUPF3 0x00000004U /*!< Clear Wakeup Pin Flag for PC1 */
<> 147:30b64687e01f 5648 #define PWR_CR2_CWUPF4 0x00000008U /*!< Clear Wakeup Pin Flag for PC13 */
<> 147:30b64687e01f 5649 #define PWR_CR2_CWUPF5 0x00000010U /*!< Clear Wakeup Pin Flag for PI8 */
<> 147:30b64687e01f 5650 #define PWR_CR2_CWUPF6 0x00000020U /*!< Clear Wakeup Pin Flag for PI11 */
<> 147:30b64687e01f 5651 #define PWR_CR2_WUPP1 0x00000100U /*!< Wakeup Pin Polarity bit for PA0 */
<> 147:30b64687e01f 5652 #define PWR_CR2_WUPP2 0x00000200U /*!< Wakeup Pin Polarity bit for PA2 */
<> 147:30b64687e01f 5653 #define PWR_CR2_WUPP3 0x00000400U /*!< Wakeup Pin Polarity bit for PC1 */
<> 147:30b64687e01f 5654 #define PWR_CR2_WUPP4 0x00000800U /*!< Wakeup Pin Polarity bit for PC13 */
<> 147:30b64687e01f 5655 #define PWR_CR2_WUPP5 0x00001000U /*!< Wakeup Pin Polarity bit for PI8 */
<> 147:30b64687e01f 5656 #define PWR_CR2_WUPP6 0x00002000U /*!< Wakeup Pin Polarity bit for PI11 */
<> 147:30b64687e01f 5657
<> 147:30b64687e01f 5658 /******************* Bit definition for PWR_CSR2 register ********************/
<> 147:30b64687e01f 5659 #define PWR_CSR2_WUPF1 0x00000001U /*!< Wakeup Pin Flag for PA0 */
<> 147:30b64687e01f 5660 #define PWR_CSR2_WUPF2 0x00000002U /*!< Wakeup Pin Flag for PA2 */
<> 147:30b64687e01f 5661 #define PWR_CSR2_WUPF3 0x00000004U /*!< Wakeup Pin Flag for PC1 */
<> 147:30b64687e01f 5662 #define PWR_CSR2_WUPF4 0x00000008U /*!< Wakeup Pin Flag for PC13 */
<> 147:30b64687e01f 5663 #define PWR_CSR2_WUPF5 0x00000010U /*!< Wakeup Pin Flag for PI8 */
<> 147:30b64687e01f 5664 #define PWR_CSR2_WUPF6 0x00000020U /*!< Wakeup Pin Flag for PI11 */
<> 147:30b64687e01f 5665 #define PWR_CSR2_EWUP1 0x00000100U /*!< Enable Wakeup Pin PA0 */
<> 147:30b64687e01f 5666 #define PWR_CSR2_EWUP2 0x00000200U /*!< Enable Wakeup Pin PA2 */
<> 147:30b64687e01f 5667 #define PWR_CSR2_EWUP3 0x00000400U /*!< Enable Wakeup Pin PC1 */
<> 147:30b64687e01f 5668 #define PWR_CSR2_EWUP4 0x00000800U /*!< Enable Wakeup Pin PC13 */
<> 147:30b64687e01f 5669 #define PWR_CSR2_EWUP5 0x00001000U /*!< Enable Wakeup Pin PI8 */
<> 147:30b64687e01f 5670 #define PWR_CSR2_EWUP6 0x00002000U /*!< Enable Wakeup Pin PI11 */
<> 147:30b64687e01f 5671
<> 147:30b64687e01f 5672 /******************************************************************************/
<> 147:30b64687e01f 5673 /* */
<> 147:30b64687e01f 5674 /* QUADSPI */
<> 147:30b64687e01f 5675 /* */
<> 147:30b64687e01f 5676 /******************************************************************************/
<> 147:30b64687e01f 5677 /***************** Bit definition for QUADSPI_CR register *******************/
<> 147:30b64687e01f 5678 #define QUADSPI_CR_EN 0x00000001U /*!< Enable */
<> 147:30b64687e01f 5679 #define QUADSPI_CR_ABORT 0x00000002U /*!< Abort request */
<> 147:30b64687e01f 5680 #define QUADSPI_CR_DMAEN 0x00000004U /*!< DMA Enable */
<> 147:30b64687e01f 5681 #define QUADSPI_CR_TCEN 0x00000008U /*!< Timeout Counter Enable */
<> 147:30b64687e01f 5682 #define QUADSPI_CR_SSHIFT 0x00000010U /*!< Sample Shift */
<> 147:30b64687e01f 5683 #define QUADSPI_CR_DFM 0x00000040U /*!< Dual Flash Mode */
<> 147:30b64687e01f 5684 #define QUADSPI_CR_FSEL 0x00000080U /*!< Flash Select */
<> 147:30b64687e01f 5685 #define QUADSPI_CR_FTHRES 0x00001F00U /*!< FTHRES[4:0] FIFO Level */
<> 147:30b64687e01f 5686 #define QUADSPI_CR_FTHRES_0 0x00000100U /*!< Bit 0 */
<> 147:30b64687e01f 5687 #define QUADSPI_CR_FTHRES_1 0x00000200U /*!< Bit 1 */
<> 147:30b64687e01f 5688 #define QUADSPI_CR_FTHRES_2 0x00000400U /*!< Bit 2 */
<> 147:30b64687e01f 5689 #define QUADSPI_CR_FTHRES_3 0x00000800U /*!< Bit 3 */
<> 147:30b64687e01f 5690 #define QUADSPI_CR_FTHRES_4 0x00001000U /*!< Bit 4 */
<> 147:30b64687e01f 5691 #define QUADSPI_CR_TEIE 0x00010000U /*!< Transfer Error Interrupt Enable */
<> 147:30b64687e01f 5692 #define QUADSPI_CR_TCIE 0x00020000U /*!< Transfer Complete Interrupt Enable */
<> 147:30b64687e01f 5693 #define QUADSPI_CR_FTIE 0x00040000U /*!< FIFO Threshold Interrupt Enable */
<> 147:30b64687e01f 5694 #define QUADSPI_CR_SMIE 0x00080000U /*!< Status Match Interrupt Enable */
<> 147:30b64687e01f 5695 #define QUADSPI_CR_TOIE 0x00100000U /*!< TimeOut Interrupt Enable */
<> 147:30b64687e01f 5696 #define QUADSPI_CR_APMS 0x00400000U /*!< Bit 1 */
<> 147:30b64687e01f 5697 #define QUADSPI_CR_PMM 0x00800000U /*!< Polling Match Mode */
<> 147:30b64687e01f 5698 #define QUADSPI_CR_PRESCALER 0xFF000000U /*!< PRESCALER[7:0] Clock prescaler */
<> 147:30b64687e01f 5699 #define QUADSPI_CR_PRESCALER_0 0x01000000U /*!< Bit 0 */
<> 147:30b64687e01f 5700 #define QUADSPI_CR_PRESCALER_1 0x02000000U /*!< Bit 1 */
<> 147:30b64687e01f 5701 #define QUADSPI_CR_PRESCALER_2 0x04000000U /*!< Bit 2 */
<> 147:30b64687e01f 5702 #define QUADSPI_CR_PRESCALER_3 0x08000000U /*!< Bit 3 */
<> 147:30b64687e01f 5703 #define QUADSPI_CR_PRESCALER_4 0x10000000U /*!< Bit 4 */
<> 147:30b64687e01f 5704 #define QUADSPI_CR_PRESCALER_5 0x20000000U /*!< Bit 5 */
<> 147:30b64687e01f 5705 #define QUADSPI_CR_PRESCALER_6 0x40000000U /*!< Bit 6 */
<> 147:30b64687e01f 5706 #define QUADSPI_CR_PRESCALER_7 0x80000000U /*!< Bit 7 */
<> 147:30b64687e01f 5707
<> 147:30b64687e01f 5708 /***************** Bit definition for QUADSPI_DCR register ******************/
<> 147:30b64687e01f 5709 #define QUADSPI_DCR_CKMODE 0x00000001U /*!< Mode 0 / Mode 3 */
<> 147:30b64687e01f 5710 #define QUADSPI_DCR_CSHT 0x00000700U /*!< CSHT[2:0]: ChipSelect High Time */
<> 147:30b64687e01f 5711 #define QUADSPI_DCR_CSHT_0 0x00000100U /*!< Bit 0 */
<> 147:30b64687e01f 5712 #define QUADSPI_DCR_CSHT_1 0x00000200U /*!< Bit 1 */
<> 147:30b64687e01f 5713 #define QUADSPI_DCR_CSHT_2 0x00000400U /*!< Bit 2 */
<> 147:30b64687e01f 5714 #define QUADSPI_DCR_FSIZE 0x001F0000U /*!< FSIZE[4:0]: Flash Size */
<> 147:30b64687e01f 5715 #define QUADSPI_DCR_FSIZE_0 0x00010000U /*!< Bit 0 */
<> 147:30b64687e01f 5716 #define QUADSPI_DCR_FSIZE_1 0x00020000U /*!< Bit 1 */
<> 147:30b64687e01f 5717 #define QUADSPI_DCR_FSIZE_2 0x00040000U /*!< Bit 2 */
<> 147:30b64687e01f 5718 #define QUADSPI_DCR_FSIZE_3 0x00080000U /*!< Bit 3 */
<> 147:30b64687e01f 5719 #define QUADSPI_DCR_FSIZE_4 0x00100000U /*!< Bit 4 */
<> 147:30b64687e01f 5720
<> 147:30b64687e01f 5721 /****************** Bit definition for QUADSPI_SR register *******************/
<> 147:30b64687e01f 5722 #define QUADSPI_SR_TEF 0x00000001U /*!< Transfer Error Flag */
<> 147:30b64687e01f 5723 #define QUADSPI_SR_TCF 0x00000002U /*!< Transfer Complete Flag */
<> 147:30b64687e01f 5724 #define QUADSPI_SR_FTF 0x00000004U /*!< FIFO Threshlod Flag */
<> 147:30b64687e01f 5725 #define QUADSPI_SR_SMF 0x00000008U /*!< Status Match Flag */
<> 147:30b64687e01f 5726 #define QUADSPI_SR_TOF 0x00000010U /*!< Timeout Flag */
<> 147:30b64687e01f 5727 #define QUADSPI_SR_BUSY 0x00000020U /*!< Busy */
<> 147:30b64687e01f 5728 #define QUADSPI_SR_FLEVEL 0x00001F00U /*!< FIFO Threshlod Flag */
<> 147:30b64687e01f 5729 #define QUADSPI_SR_FLEVEL_0 0x00000100U /*!< Bit 0 */
<> 147:30b64687e01f 5730 #define QUADSPI_SR_FLEVEL_1 0x00000200U /*!< Bit 1 */
<> 147:30b64687e01f 5731 #define QUADSPI_SR_FLEVEL_2 0x00000400U /*!< Bit 2 */
<> 147:30b64687e01f 5732 #define QUADSPI_SR_FLEVEL_3 0x00000800U /*!< Bit 3 */
<> 147:30b64687e01f 5733 #define QUADSPI_SR_FLEVEL_4 0x00001000U /*!< Bit 4 */
<> 147:30b64687e01f 5734
<> 147:30b64687e01f 5735 /****************** Bit definition for QUADSPI_FCR register ******************/
<> 147:30b64687e01f 5736 #define QUADSPI_FCR_CTEF 0x00000001U /*!< Clear Transfer Error Flag */
<> 147:30b64687e01f 5737 #define QUADSPI_FCR_CTCF 0x00000002U /*!< Clear Transfer Complete Flag */
<> 147:30b64687e01f 5738 #define QUADSPI_FCR_CSMF 0x00000008U /*!< Clear Status Match Flag */
<> 147:30b64687e01f 5739 #define QUADSPI_FCR_CTOF 0x00000010U /*!< Clear Timeout Flag */
<> 147:30b64687e01f 5740
<> 147:30b64687e01f 5741 /****************** Bit definition for QUADSPI_DLR register ******************/
<> 147:30b64687e01f 5742 #define QUADSPI_DLR_DL 0xFFFFFFFFU /*!< DL[31:0]: Data Length */
<> 147:30b64687e01f 5743
<> 147:30b64687e01f 5744 /****************** Bit definition for QUADSPI_CCR register ******************/
<> 147:30b64687e01f 5745 #define QUADSPI_CCR_INSTRUCTION 0x000000FFU /*!< INSTRUCTION[7:0]: Instruction */
<> 147:30b64687e01f 5746 #define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /*!< Bit 0 */
<> 147:30b64687e01f 5747 #define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /*!< Bit 1 */
<> 147:30b64687e01f 5748 #define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /*!< Bit 2 */
<> 147:30b64687e01f 5749 #define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /*!< Bit 3 */
<> 147:30b64687e01f 5750 #define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /*!< Bit 4 */
<> 147:30b64687e01f 5751 #define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /*!< Bit 5 */
<> 147:30b64687e01f 5752 #define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /*!< Bit 6 */
<> 147:30b64687e01f 5753 #define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /*!< Bit 7 */
<> 147:30b64687e01f 5754 #define QUADSPI_CCR_IMODE 0x00000300U /*!< IMODE[1:0]: Instruction Mode */
<> 147:30b64687e01f 5755 #define QUADSPI_CCR_IMODE_0 0x00000100U /*!< Bit 0 */
<> 147:30b64687e01f 5756 #define QUADSPI_CCR_IMODE_1 0x00000200U /*!< Bit 1 */
<> 147:30b64687e01f 5757 #define QUADSPI_CCR_ADMODE 0x00000C00U /*!< ADMODE[1:0]: Address Mode */
<> 147:30b64687e01f 5758 #define QUADSPI_CCR_ADMODE_0 0x00000400U /*!< Bit 0 */
<> 147:30b64687e01f 5759 #define QUADSPI_CCR_ADMODE_1 0x00000800U /*!< Bit 1 */
<> 147:30b64687e01f 5760 #define QUADSPI_CCR_ADSIZE 0x00003000U /*!< ADSIZE[1:0]: Address Size */
<> 147:30b64687e01f 5761 #define QUADSPI_CCR_ADSIZE_0 0x00001000U /*!< Bit 0 */
<> 147:30b64687e01f 5762 #define QUADSPI_CCR_ADSIZE_1 0x00002000U /*!< Bit 1 */
<> 147:30b64687e01f 5763 #define QUADSPI_CCR_ABMODE 0x0000C000U /*!< ABMODE[1:0]: Alternate Bytes Mode */
<> 147:30b64687e01f 5764 #define QUADSPI_CCR_ABMODE_0 0x00004000U /*!< Bit 0 */
<> 147:30b64687e01f 5765 #define QUADSPI_CCR_ABMODE_1 0x00008000U /*!< Bit 1 */
<> 147:30b64687e01f 5766 #define QUADSPI_CCR_ABSIZE 0x00030000U /*!< ABSIZE[1:0]: Instruction Mode */
<> 147:30b64687e01f 5767 #define QUADSPI_CCR_ABSIZE_0 0x00010000U /*!< Bit 0 */
<> 147:30b64687e01f 5768 #define QUADSPI_CCR_ABSIZE_1 0x00020000U /*!< Bit 1 */
<> 147:30b64687e01f 5769 #define QUADSPI_CCR_DCYC 0x007C0000U /*!< DCYC[4:0]: Dummy Cycles */
<> 147:30b64687e01f 5770 #define QUADSPI_CCR_DCYC_0 0x00040000U /*!< Bit 0 */
<> 147:30b64687e01f 5771 #define QUADSPI_CCR_DCYC_1 0x00080000U /*!< Bit 1 */
<> 147:30b64687e01f 5772 #define QUADSPI_CCR_DCYC_2 0x00100000U /*!< Bit 2 */
<> 147:30b64687e01f 5773 #define QUADSPI_CCR_DCYC_3 0x00200000U /*!< Bit 3 */
<> 147:30b64687e01f 5774 #define QUADSPI_CCR_DCYC_4 0x00400000U /*!< Bit 4 */
<> 147:30b64687e01f 5775 #define QUADSPI_CCR_DMODE 0x03000000U /*!< DMODE[1:0]: Data Mode */
<> 147:30b64687e01f 5776 #define QUADSPI_CCR_DMODE_0 0x01000000U /*!< Bit 0 */
<> 147:30b64687e01f 5777 #define QUADSPI_CCR_DMODE_1 0x02000000U /*!< Bit 1 */
<> 147:30b64687e01f 5778 #define QUADSPI_CCR_FMODE 0x0C000000U /*!< FMODE[1:0]: Functional Mode */
<> 147:30b64687e01f 5779 #define QUADSPI_CCR_FMODE_0 0x04000000U /*!< Bit 0 */
<> 147:30b64687e01f 5780 #define QUADSPI_CCR_FMODE_1 0x08000000U /*!< Bit 1 */
<> 147:30b64687e01f 5781 #define QUADSPI_CCR_SIOO 0x10000000U /*!< SIOO: Send Instruction Only Once Mode */
<> 147:30b64687e01f 5782 #define QUADSPI_CCR_DHHC 0x40000000U /*!< DHHC: Delay Half Hclk Cycle */
<> 147:30b64687e01f 5783 #define QUADSPI_CCR_DDRM 0x80000000U /*!< DDRM: Double Data Rate Mode */
<> 147:30b64687e01f 5784 /****************** Bit definition for QUADSPI_AR register *******************/
<> 147:30b64687e01f 5785 #define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /*!< ADDRESS[31:0]: Address */
<> 147:30b64687e01f 5786
<> 147:30b64687e01f 5787 /****************** Bit definition for QUADSPI_ABR register ******************/
<> 147:30b64687e01f 5788 #define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /*!< ALTERNATE[31:0]: Alternate Bytes */
<> 147:30b64687e01f 5789
<> 147:30b64687e01f 5790 /****************** Bit definition for QUADSPI_DR register *******************/
<> 147:30b64687e01f 5791 #define QUADSPI_DR_DATA 0xFFFFFFFFU /*!< DATA[31:0]: Data */
<> 147:30b64687e01f 5792
<> 147:30b64687e01f 5793 /****************** Bit definition for QUADSPI_PSMKR register ****************/
<> 147:30b64687e01f 5794 #define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /*!< MASK[31:0]: Status Mask */
<> 147:30b64687e01f 5795
<> 147:30b64687e01f 5796 /****************** Bit definition for QUADSPI_PSMAR register ****************/
<> 147:30b64687e01f 5797 #define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /*!< MATCH[31:0]: Status Match */
<> 147:30b64687e01f 5798
<> 147:30b64687e01f 5799 /****************** Bit definition for QUADSPI_PIR register *****************/
<> 147:30b64687e01f 5800 #define QUADSPI_PIR_INTERVAL 0x0000FFFFU /*!< INTERVAL[15:0]: Polling Interval */
<> 147:30b64687e01f 5801
<> 147:30b64687e01f 5802 /****************** Bit definition for QUADSPI_LPTR register *****************/
<> 147:30b64687e01f 5803 #define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /*!< TIMEOUT[15:0]: Timeout period */
<> 147:30b64687e01f 5804
<> 147:30b64687e01f 5805 /******************************************************************************/
<> 147:30b64687e01f 5806 /* */
<> 147:30b64687e01f 5807 /* Reset and Clock Control */
<> 147:30b64687e01f 5808 /* */
<> 147:30b64687e01f 5809 /******************************************************************************/
<> 147:30b64687e01f 5810 /******************** Bit definition for RCC_CR register ********************/
<> 147:30b64687e01f 5811 #define RCC_CR_HSION 0x00000001U
<> 147:30b64687e01f 5812 #define RCC_CR_HSIRDY 0x00000002U
<> 147:30b64687e01f 5813 #define RCC_CR_HSITRIM 0x000000F8U
<> 147:30b64687e01f 5814 #define RCC_CR_HSITRIM_0 0x00000008U /*!<Bit 0 */
<> 147:30b64687e01f 5815 #define RCC_CR_HSITRIM_1 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 5816 #define RCC_CR_HSITRIM_2 0x00000020U /*!<Bit 2 */
<> 147:30b64687e01f 5817 #define RCC_CR_HSITRIM_3 0x00000040U /*!<Bit 3 */
<> 147:30b64687e01f 5818 #define RCC_CR_HSITRIM_4 0x00000080U /*!<Bit 4 */
<> 147:30b64687e01f 5819 #define RCC_CR_HSICAL 0x0000FF00U
<> 147:30b64687e01f 5820 #define RCC_CR_HSICAL_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 5821 #define RCC_CR_HSICAL_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 5822 #define RCC_CR_HSICAL_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 5823 #define RCC_CR_HSICAL_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 5824 #define RCC_CR_HSICAL_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 5825 #define RCC_CR_HSICAL_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 5826 #define RCC_CR_HSICAL_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 5827 #define RCC_CR_HSICAL_7 0x00008000U /*!<Bit 7 */
<> 147:30b64687e01f 5828 #define RCC_CR_HSEON 0x00010000U
<> 147:30b64687e01f 5829 #define RCC_CR_HSERDY 0x00020000U
<> 147:30b64687e01f 5830 #define RCC_CR_HSEBYP 0x00040000U
<> 147:30b64687e01f 5831 #define RCC_CR_CSSON 0x00080000U
<> 147:30b64687e01f 5832 #define RCC_CR_PLLON 0x01000000U
<> 147:30b64687e01f 5833 #define RCC_CR_PLLRDY 0x02000000U
<> 147:30b64687e01f 5834 #define RCC_CR_PLLI2SON 0x04000000U
<> 147:30b64687e01f 5835 #define RCC_CR_PLLI2SRDY 0x08000000U
<> 147:30b64687e01f 5836 #define RCC_CR_PLLSAION 0x10000000U
<> 147:30b64687e01f 5837 #define RCC_CR_PLLSAIRDY 0x20000000U
<> 147:30b64687e01f 5838
<> 147:30b64687e01f 5839 /******************** Bit definition for RCC_PLLCFGR register ***************/
<> 147:30b64687e01f 5840 #define RCC_PLLCFGR_PLLM 0x0000003FU
<> 147:30b64687e01f 5841 #define RCC_PLLCFGR_PLLM_0 0x00000001U
<> 147:30b64687e01f 5842 #define RCC_PLLCFGR_PLLM_1 0x00000002U
<> 147:30b64687e01f 5843 #define RCC_PLLCFGR_PLLM_2 0x00000004U
<> 147:30b64687e01f 5844 #define RCC_PLLCFGR_PLLM_3 0x00000008U
<> 147:30b64687e01f 5845 #define RCC_PLLCFGR_PLLM_4 0x00000010U
<> 147:30b64687e01f 5846 #define RCC_PLLCFGR_PLLM_5 0x00000020U
<> 147:30b64687e01f 5847 #define RCC_PLLCFGR_PLLN 0x00007FC0U
<> 147:30b64687e01f 5848 #define RCC_PLLCFGR_PLLN_0 0x00000040U
<> 147:30b64687e01f 5849 #define RCC_PLLCFGR_PLLN_1 0x00000080U
<> 147:30b64687e01f 5850 #define RCC_PLLCFGR_PLLN_2 0x00000100U
<> 147:30b64687e01f 5851 #define RCC_PLLCFGR_PLLN_3 0x00000200U
<> 147:30b64687e01f 5852 #define RCC_PLLCFGR_PLLN_4 0x00000400U
<> 147:30b64687e01f 5853 #define RCC_PLLCFGR_PLLN_5 0x00000800U
<> 147:30b64687e01f 5854 #define RCC_PLLCFGR_PLLN_6 0x00001000U
<> 147:30b64687e01f 5855 #define RCC_PLLCFGR_PLLN_7 0x00002000U
<> 147:30b64687e01f 5856 #define RCC_PLLCFGR_PLLN_8 0x00004000U
<> 147:30b64687e01f 5857 #define RCC_PLLCFGR_PLLP 0x00030000U
<> 147:30b64687e01f 5858 #define RCC_PLLCFGR_PLLP_0 0x00010000U
<> 147:30b64687e01f 5859 #define RCC_PLLCFGR_PLLP_1 0x00020000U
<> 147:30b64687e01f 5860 #define RCC_PLLCFGR_PLLSRC 0x00400000U
<> 147:30b64687e01f 5861 #define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
<> 147:30b64687e01f 5862 #define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
<> 147:30b64687e01f 5863 #define RCC_PLLCFGR_PLLQ 0x0F000000U
<> 147:30b64687e01f 5864 #define RCC_PLLCFGR_PLLQ_0 0x01000000U
<> 147:30b64687e01f 5865 #define RCC_PLLCFGR_PLLQ_1 0x02000000U
<> 147:30b64687e01f 5866 #define RCC_PLLCFGR_PLLQ_2 0x04000000U
<> 147:30b64687e01f 5867 #define RCC_PLLCFGR_PLLQ_3 0x08000000U
<> 147:30b64687e01f 5868
<> 147:30b64687e01f 5869 #define RCC_PLLCFGR_PLLR 0x70000000U
<> 147:30b64687e01f 5870 #define RCC_PLLCFGR_PLLR_0 0x10000000U
<> 147:30b64687e01f 5871 #define RCC_PLLCFGR_PLLR_1 0x20000000U
<> 147:30b64687e01f 5872 #define RCC_PLLCFGR_PLLR_2 0x40000000U
<> 147:30b64687e01f 5873
<> 147:30b64687e01f 5874 /******************** Bit definition for RCC_CFGR register ******************/
<> 147:30b64687e01f 5875 /*!< SW configuration */
<> 147:30b64687e01f 5876 #define RCC_CFGR_SW 0x00000003U /*!< SW[1:0] bits (System clock Switch) */
<> 147:30b64687e01f 5877 #define RCC_CFGR_SW_0 0x00000001U /*!< Bit 0 */
<> 147:30b64687e01f 5878 #define RCC_CFGR_SW_1 0x00000002U /*!< Bit 1 */
<> 147:30b64687e01f 5879 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
<> 147:30b64687e01f 5880 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
<> 147:30b64687e01f 5881 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
<> 147:30b64687e01f 5882
<> 147:30b64687e01f 5883 /*!< SWS configuration */
<> 147:30b64687e01f 5884 #define RCC_CFGR_SWS 0x0000000CU /*!< SWS[1:0] bits (System Clock Switch Status) */
<> 147:30b64687e01f 5885 #define RCC_CFGR_SWS_0 0x00000004U /*!< Bit 0 */
<> 147:30b64687e01f 5886 #define RCC_CFGR_SWS_1 0x00000008U /*!< Bit 1 */
<> 147:30b64687e01f 5887 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
<> 147:30b64687e01f 5888 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
<> 147:30b64687e01f 5889 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
<> 147:30b64687e01f 5890
<> 147:30b64687e01f 5891 /*!< HPRE configuration */
<> 147:30b64687e01f 5892 #define RCC_CFGR_HPRE 0x000000F0U /*!< HPRE[3:0] bits (AHB prescaler) */
<> 147:30b64687e01f 5893 #define RCC_CFGR_HPRE_0 0x00000010U /*!< Bit 0 */
<> 147:30b64687e01f 5894 #define RCC_CFGR_HPRE_1 0x00000020U /*!< Bit 1 */
<> 147:30b64687e01f 5895 #define RCC_CFGR_HPRE_2 0x00000040U /*!< Bit 2 */
<> 147:30b64687e01f 5896 #define RCC_CFGR_HPRE_3 0x00000080U /*!< Bit 3 */
<> 147:30b64687e01f 5897
<> 147:30b64687e01f 5898 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
<> 147:30b64687e01f 5899 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
<> 147:30b64687e01f 5900 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
<> 147:30b64687e01f 5901 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
<> 147:30b64687e01f 5902 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
<> 147:30b64687e01f 5903 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
<> 147:30b64687e01f 5904 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
<> 147:30b64687e01f 5905 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
<> 147:30b64687e01f 5906 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
<> 147:30b64687e01f 5907
<> 147:30b64687e01f 5908 /*!< PPRE1 configuration */
<> 147:30b64687e01f 5909 #define RCC_CFGR_PPRE1 0x00001C00U /*!< PRE1[2:0] bits (APB1 prescaler) */
<> 147:30b64687e01f 5910 #define RCC_CFGR_PPRE1_0 0x00000400U /*!< Bit 0 */
<> 147:30b64687e01f 5911 #define RCC_CFGR_PPRE1_1 0x00000800U /*!< Bit 1 */
<> 147:30b64687e01f 5912 #define RCC_CFGR_PPRE1_2 0x00001000U /*!< Bit 2 */
<> 147:30b64687e01f 5913
<> 147:30b64687e01f 5914 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
<> 147:30b64687e01f 5915 #define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */
<> 147:30b64687e01f 5916 #define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */
<> 147:30b64687e01f 5917 #define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */
<> 147:30b64687e01f 5918 #define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */
<> 147:30b64687e01f 5919
<> 147:30b64687e01f 5920 /*!< PPRE2 configuration */
<> 147:30b64687e01f 5921 #define RCC_CFGR_PPRE2 0x0000E000U /*!< PRE2[2:0] bits (APB2 prescaler) */
<> 147:30b64687e01f 5922 #define RCC_CFGR_PPRE2_0 0x00002000U /*!< Bit 0 */
<> 147:30b64687e01f 5923 #define RCC_CFGR_PPRE2_1 0x00004000U /*!< Bit 1 */
<> 147:30b64687e01f 5924 #define RCC_CFGR_PPRE2_2 0x00008000U /*!< Bit 2 */
<> 147:30b64687e01f 5925
<> 147:30b64687e01f 5926 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
<> 147:30b64687e01f 5927 #define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */
<> 147:30b64687e01f 5928 #define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */
<> 147:30b64687e01f 5929 #define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */
<> 147:30b64687e01f 5930 #define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */
<> 147:30b64687e01f 5931
<> 147:30b64687e01f 5932 /*!< RTCPRE configuration */
<> 147:30b64687e01f 5933 #define RCC_CFGR_RTCPRE 0x001F0000U
<> 147:30b64687e01f 5934 #define RCC_CFGR_RTCPRE_0 0x00010000U
<> 147:30b64687e01f 5935 #define RCC_CFGR_RTCPRE_1 0x00020000U
<> 147:30b64687e01f 5936 #define RCC_CFGR_RTCPRE_2 0x00040000U
<> 147:30b64687e01f 5937 #define RCC_CFGR_RTCPRE_3 0x00080000U
<> 147:30b64687e01f 5938 #define RCC_CFGR_RTCPRE_4 0x00100000U
<> 147:30b64687e01f 5939
<> 147:30b64687e01f 5940 /*!< MCO1 configuration */
<> 147:30b64687e01f 5941 #define RCC_CFGR_MCO1 0x00600000U
<> 147:30b64687e01f 5942 #define RCC_CFGR_MCO1_0 0x00200000U
<> 147:30b64687e01f 5943 #define RCC_CFGR_MCO1_1 0x00400000U
<> 147:30b64687e01f 5944
<> 147:30b64687e01f 5945 #define RCC_CFGR_I2SSRC 0x00800000U
<> 147:30b64687e01f 5946
<> 147:30b64687e01f 5947 #define RCC_CFGR_MCO1PRE 0x07000000U
<> 147:30b64687e01f 5948 #define RCC_CFGR_MCO1PRE_0 0x01000000U
<> 147:30b64687e01f 5949 #define RCC_CFGR_MCO1PRE_1 0x02000000U
<> 147:30b64687e01f 5950 #define RCC_CFGR_MCO1PRE_2 0x04000000U
<> 147:30b64687e01f 5951
<> 147:30b64687e01f 5952 #define RCC_CFGR_MCO2PRE 0x38000000U
<> 147:30b64687e01f 5953 #define RCC_CFGR_MCO2PRE_0 0x08000000U
<> 147:30b64687e01f 5954 #define RCC_CFGR_MCO2PRE_1 0x10000000U
<> 147:30b64687e01f 5955 #define RCC_CFGR_MCO2PRE_2 0x20000000U
<> 147:30b64687e01f 5956
<> 147:30b64687e01f 5957 #define RCC_CFGR_MCO2 0xC0000000U
<> 147:30b64687e01f 5958 #define RCC_CFGR_MCO2_0 0x40000000U
<> 147:30b64687e01f 5959 #define RCC_CFGR_MCO2_1 0x80000000U
<> 147:30b64687e01f 5960
<> 147:30b64687e01f 5961 /******************** Bit definition for RCC_CIR register *******************/
<> 147:30b64687e01f 5962 #define RCC_CIR_LSIRDYF 0x00000001U
<> 147:30b64687e01f 5963 #define RCC_CIR_LSERDYF 0x00000002U
<> 147:30b64687e01f 5964 #define RCC_CIR_HSIRDYF 0x00000004U
<> 147:30b64687e01f 5965 #define RCC_CIR_HSERDYF 0x00000008U
<> 147:30b64687e01f 5966 #define RCC_CIR_PLLRDYF 0x00000010U
<> 147:30b64687e01f 5967 #define RCC_CIR_PLLI2SRDYF 0x00000020U
<> 147:30b64687e01f 5968 #define RCC_CIR_PLLSAIRDYF 0x00000040U
<> 147:30b64687e01f 5969 #define RCC_CIR_CSSF 0x00000080U
<> 147:30b64687e01f 5970 #define RCC_CIR_LSIRDYIE 0x00000100U
<> 147:30b64687e01f 5971 #define RCC_CIR_LSERDYIE 0x00000200U
<> 147:30b64687e01f 5972 #define RCC_CIR_HSIRDYIE 0x00000400U
<> 147:30b64687e01f 5973 #define RCC_CIR_HSERDYIE 0x00000800U
<> 147:30b64687e01f 5974 #define RCC_CIR_PLLRDYIE 0x00001000U
<> 147:30b64687e01f 5975 #define RCC_CIR_PLLI2SRDYIE 0x00002000U
<> 147:30b64687e01f 5976 #define RCC_CIR_PLLSAIRDYIE 0x00004000U
<> 147:30b64687e01f 5977 #define RCC_CIR_LSIRDYC 0x00010000U
<> 147:30b64687e01f 5978 #define RCC_CIR_LSERDYC 0x00020000U
<> 147:30b64687e01f 5979 #define RCC_CIR_HSIRDYC 0x00040000U
<> 147:30b64687e01f 5980 #define RCC_CIR_HSERDYC 0x00080000U
<> 147:30b64687e01f 5981 #define RCC_CIR_PLLRDYC 0x00100000U
<> 147:30b64687e01f 5982 #define RCC_CIR_PLLI2SRDYC 0x00200000U
<> 147:30b64687e01f 5983 #define RCC_CIR_PLLSAIRDYC 0x00400000U
<> 147:30b64687e01f 5984 #define RCC_CIR_CSSC 0x00800000U
<> 147:30b64687e01f 5985
<> 147:30b64687e01f 5986 /******************** Bit definition for RCC_AHB1RSTR register **************/
<> 147:30b64687e01f 5987 #define RCC_AHB1RSTR_GPIOARST 0x00000001U
<> 147:30b64687e01f 5988 #define RCC_AHB1RSTR_GPIOBRST 0x00000002U
<> 147:30b64687e01f 5989 #define RCC_AHB1RSTR_GPIOCRST 0x00000004U
<> 147:30b64687e01f 5990 #define RCC_AHB1RSTR_GPIODRST 0x00000008U
<> 147:30b64687e01f 5991 #define RCC_AHB1RSTR_GPIOERST 0x00000010U
<> 147:30b64687e01f 5992 #define RCC_AHB1RSTR_GPIOFRST 0x00000020U
<> 147:30b64687e01f 5993 #define RCC_AHB1RSTR_GPIOGRST 0x00000040U
<> 147:30b64687e01f 5994 #define RCC_AHB1RSTR_GPIOHRST 0x00000080U
<> 147:30b64687e01f 5995 #define RCC_AHB1RSTR_GPIOIRST 0x00000100U
<> 147:30b64687e01f 5996 #define RCC_AHB1RSTR_GPIOJRST 0x00000200U
<> 147:30b64687e01f 5997 #define RCC_AHB1RSTR_GPIOKRST 0x00000400U
<> 147:30b64687e01f 5998 #define RCC_AHB1RSTR_CRCRST 0x00001000U
<> 147:30b64687e01f 5999 #define RCC_AHB1RSTR_DMA1RST 0x00200000U
<> 147:30b64687e01f 6000 #define RCC_AHB1RSTR_DMA2RST 0x00400000U
<> 147:30b64687e01f 6001 #define RCC_AHB1RSTR_DMA2DRST 0x00800000U
<> 147:30b64687e01f 6002 #define RCC_AHB1RSTR_ETHMACRST 0x02000000U
<> 147:30b64687e01f 6003 #define RCC_AHB1RSTR_OTGHRST 0x20000000U
<> 147:30b64687e01f 6004
<> 147:30b64687e01f 6005 /******************** Bit definition for RCC_AHB2RSTR register **************/
<> 147:30b64687e01f 6006 #define RCC_AHB2RSTR_DCMIRST 0x00000001U
<> 147:30b64687e01f 6007 #define RCC_AHB2RSTR_JPEGRST 0x00000002U
<> 147:30b64687e01f 6008 #define RCC_AHB2RSTR_RNGRST 0x00000040U
<> 147:30b64687e01f 6009 #define RCC_AHB2RSTR_OTGFSRST 0x00000080U
<> 147:30b64687e01f 6010
<> 147:30b64687e01f 6011 /******************** Bit definition for RCC_AHB3RSTR register **************/
<> 147:30b64687e01f 6012
<> 147:30b64687e01f 6013 #define RCC_AHB3RSTR_FMCRST 0x00000001U
<> 147:30b64687e01f 6014 #define RCC_AHB3RSTR_QSPIRST 0x00000002U
<> 147:30b64687e01f 6015
<> 147:30b64687e01f 6016 /******************** Bit definition for RCC_APB1RSTR register **************/
<> 147:30b64687e01f 6017 #define RCC_APB1RSTR_TIM2RST 0x00000001U
<> 147:30b64687e01f 6018 #define RCC_APB1RSTR_TIM3RST 0x00000002U
<> 147:30b64687e01f 6019 #define RCC_APB1RSTR_TIM4RST 0x00000004U
<> 147:30b64687e01f 6020 #define RCC_APB1RSTR_TIM5RST 0x00000008U
<> 147:30b64687e01f 6021 #define RCC_APB1RSTR_TIM6RST 0x00000010U
<> 147:30b64687e01f 6022 #define RCC_APB1RSTR_TIM7RST 0x00000020U
<> 147:30b64687e01f 6023 #define RCC_APB1RSTR_TIM12RST 0x00000040U
<> 147:30b64687e01f 6024 #define RCC_APB1RSTR_TIM13RST 0x00000080U
<> 147:30b64687e01f 6025 #define RCC_APB1RSTR_TIM14RST 0x00000100U
<> 147:30b64687e01f 6026 #define RCC_APB1RSTR_LPTIM1RST 0x00000200U
<> 147:30b64687e01f 6027 #define RCC_APB1RSTR_WWDGRST 0x00000800U
<> 147:30b64687e01f 6028 #define RCC_APB1RSTR_CAN3RST 0x00002000U
<> 147:30b64687e01f 6029 #define RCC_APB1RSTR_SPI2RST 0x00004000U
<> 147:30b64687e01f 6030 #define RCC_APB1RSTR_SPI3RST 0x00008000U
<> 147:30b64687e01f 6031 #define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
<> 147:30b64687e01f 6032 #define RCC_APB1RSTR_USART2RST 0x00020000U
<> 147:30b64687e01f 6033 #define RCC_APB1RSTR_USART3RST 0x00040000U
<> 147:30b64687e01f 6034 #define RCC_APB1RSTR_UART4RST 0x00080000U
<> 147:30b64687e01f 6035 #define RCC_APB1RSTR_UART5RST 0x00100000U
<> 147:30b64687e01f 6036 #define RCC_APB1RSTR_I2C1RST 0x00200000U
<> 147:30b64687e01f 6037 #define RCC_APB1RSTR_I2C2RST 0x00400000U
<> 147:30b64687e01f 6038 #define RCC_APB1RSTR_I2C3RST 0x00800000U
<> 147:30b64687e01f 6039 #define RCC_APB1RSTR_I2C4RST 0x01000000U
<> 147:30b64687e01f 6040 #define RCC_APB1RSTR_CAN1RST 0x02000000U
<> 147:30b64687e01f 6041 #define RCC_APB1RSTR_CAN2RST 0x04000000U
<> 147:30b64687e01f 6042 #define RCC_APB1RSTR_CECRST 0x08000000U
<> 147:30b64687e01f 6043 #define RCC_APB1RSTR_PWRRST 0x10000000U
<> 147:30b64687e01f 6044 #define RCC_APB1RSTR_DACRST 0x20000000U
<> 147:30b64687e01f 6045 #define RCC_APB1RSTR_UART7RST 0x40000000U
<> 147:30b64687e01f 6046 #define RCC_APB1RSTR_UART8RST 0x80000000U
<> 147:30b64687e01f 6047
<> 147:30b64687e01f 6048 /******************** Bit definition for RCC_APB2RSTR register **************/
<> 147:30b64687e01f 6049 #define RCC_APB2RSTR_TIM1RST 0x00000001U
<> 147:30b64687e01f 6050 #define RCC_APB2RSTR_TIM8RST 0x00000002U
<> 147:30b64687e01f 6051 #define RCC_APB2RSTR_USART1RST 0x00000010U
<> 147:30b64687e01f 6052 #define RCC_APB2RSTR_USART6RST 0x00000020U
<> 147:30b64687e01f 6053 #define RCC_APB2RSTR_SDMMC2RST 0x00000080U
<> 147:30b64687e01f 6054 #define RCC_APB2RSTR_ADCRST 0x00000100U
<> 147:30b64687e01f 6055 #define RCC_APB2RSTR_SDMMC1RST 0x00000800U
<> 147:30b64687e01f 6056 #define RCC_APB2RSTR_SPI1RST 0x00001000U
<> 147:30b64687e01f 6057 #define RCC_APB2RSTR_SPI4RST 0x00002000U
<> 147:30b64687e01f 6058 #define RCC_APB2RSTR_SYSCFGRST 0x00004000U
<> 147:30b64687e01f 6059 #define RCC_APB2RSTR_TIM9RST 0x00010000U
<> 147:30b64687e01f 6060 #define RCC_APB2RSTR_TIM10RST 0x00020000U
<> 147:30b64687e01f 6061 #define RCC_APB2RSTR_TIM11RST 0x00040000U
<> 147:30b64687e01f 6062 #define RCC_APB2RSTR_SPI5RST 0x00100000U
<> 147:30b64687e01f 6063 #define RCC_APB2RSTR_SPI6RST 0x00200000U
<> 147:30b64687e01f 6064 #define RCC_APB2RSTR_SAI1RST 0x00400000U
<> 147:30b64687e01f 6065 #define RCC_APB2RSTR_SAI2RST 0x00800000U
<> 147:30b64687e01f 6066 #define RCC_APB2RSTR_LTDCRST 0x04000000U
<> 147:30b64687e01f 6067 #define RCC_APB2RSTR_DSIRST 0x08000000U
<> 147:30b64687e01f 6068 #define RCC_APB2RSTR_DFSDM1RST 0x20000000U
<> 147:30b64687e01f 6069 #define RCC_APB2RSTR_MDIORST 0x40000000U
<> 147:30b64687e01f 6070
<> 147:30b64687e01f 6071 /******************** Bit definition for RCC_AHB1ENR register ***************/
<> 147:30b64687e01f 6072 #define RCC_AHB1ENR_GPIOAEN 0x00000001U
<> 147:30b64687e01f 6073 #define RCC_AHB1ENR_GPIOBEN 0x00000002U
<> 147:30b64687e01f 6074 #define RCC_AHB1ENR_GPIOCEN 0x00000004U
<> 147:30b64687e01f 6075 #define RCC_AHB1ENR_GPIODEN 0x00000008U
<> 147:30b64687e01f 6076 #define RCC_AHB1ENR_GPIOEEN 0x00000010U
<> 147:30b64687e01f 6077 #define RCC_AHB1ENR_GPIOFEN 0x00000020U
<> 147:30b64687e01f 6078 #define RCC_AHB1ENR_GPIOGEN 0x00000040U
<> 147:30b64687e01f 6079 #define RCC_AHB1ENR_GPIOHEN 0x00000080U
<> 147:30b64687e01f 6080 #define RCC_AHB1ENR_GPIOIEN 0x00000100U
<> 147:30b64687e01f 6081 #define RCC_AHB1ENR_GPIOJEN 0x00000200U
<> 147:30b64687e01f 6082 #define RCC_AHB1ENR_GPIOKEN 0x00000400U
<> 147:30b64687e01f 6083 #define RCC_AHB1ENR_CRCEN 0x00001000U
<> 147:30b64687e01f 6084 #define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
<> 147:30b64687e01f 6085 #define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
<> 147:30b64687e01f 6086 #define RCC_AHB1ENR_DMA1EN 0x00200000U
<> 147:30b64687e01f 6087 #define RCC_AHB1ENR_DMA2EN 0x00400000U
<> 147:30b64687e01f 6088 #define RCC_AHB1ENR_DMA2DEN 0x00800000U
<> 147:30b64687e01f 6089 #define RCC_AHB1ENR_ETHMACEN 0x02000000U
<> 147:30b64687e01f 6090 #define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
<> 147:30b64687e01f 6091 #define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
<> 147:30b64687e01f 6092 #define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
<> 147:30b64687e01f 6093 #define RCC_AHB1ENR_OTGHSEN 0x20000000U
<> 147:30b64687e01f 6094 #define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
<> 147:30b64687e01f 6095
<> 147:30b64687e01f 6096 /******************** Bit definition for RCC_AHB2ENR register ***************/
<> 147:30b64687e01f 6097 #define RCC_AHB2ENR_DCMIEN 0x00000001U
<> 147:30b64687e01f 6098 #define RCC_AHB2ENR_JPEGEN 0x00000002U
<> 147:30b64687e01f 6099 #define RCC_AHB2ENR_RNGEN 0x00000040U
<> 147:30b64687e01f 6100 #define RCC_AHB2ENR_OTGFSEN 0x00000080U
<> 147:30b64687e01f 6101
<> 147:30b64687e01f 6102 /******************** Bit definition for RCC_AHB3ENR register ***************/
<> 147:30b64687e01f 6103 #define RCC_AHB3ENR_FMCEN 0x00000001U
<> 147:30b64687e01f 6104 #define RCC_AHB3ENR_QSPIEN 0x00000002U
<> 147:30b64687e01f 6105
<> 147:30b64687e01f 6106 /******************** Bit definition for RCC_APB1ENR register ***************/
<> 147:30b64687e01f 6107 #define RCC_APB1ENR_TIM2EN 0x00000001U
<> 147:30b64687e01f 6108 #define RCC_APB1ENR_TIM3EN 0x00000002U
<> 147:30b64687e01f 6109 #define RCC_APB1ENR_TIM4EN 0x00000004U
<> 147:30b64687e01f 6110 #define RCC_APB1ENR_TIM5EN 0x00000008U
<> 147:30b64687e01f 6111 #define RCC_APB1ENR_TIM6EN 0x00000010U
<> 147:30b64687e01f 6112 #define RCC_APB1ENR_TIM7EN 0x00000020U
<> 147:30b64687e01f 6113 #define RCC_APB1ENR_TIM12EN 0x00000040U
<> 147:30b64687e01f 6114 #define RCC_APB1ENR_TIM13EN 0x00000080U
<> 147:30b64687e01f 6115 #define RCC_APB1ENR_TIM14EN 0x00000100U
<> 147:30b64687e01f 6116 #define RCC_APB1ENR_LPTIM1EN 0x00000200U
<> 147:30b64687e01f 6117 #define RCC_APB1ENR_RTCEN 0x00000400U
<> 147:30b64687e01f 6118 #define RCC_APB1ENR_WWDGEN 0x00000800U
<> 147:30b64687e01f 6119 #define RCC_APB1ENR_CAN3EN 0x00002000U
<> 147:30b64687e01f 6120 #define RCC_APB1ENR_SPI2EN 0x00004000U
<> 147:30b64687e01f 6121 #define RCC_APB1ENR_SPI3EN 0x00008000U
<> 147:30b64687e01f 6122 #define RCC_APB1ENR_SPDIFRXEN 0x00010000U
<> 147:30b64687e01f 6123 #define RCC_APB1ENR_USART2EN 0x00020000U
<> 147:30b64687e01f 6124 #define RCC_APB1ENR_USART3EN 0x00040000U
<> 147:30b64687e01f 6125 #define RCC_APB1ENR_UART4EN 0x00080000U
<> 147:30b64687e01f 6126 #define RCC_APB1ENR_UART5EN 0x00100000U
<> 147:30b64687e01f 6127 #define RCC_APB1ENR_I2C1EN 0x00200000U
<> 147:30b64687e01f 6128 #define RCC_APB1ENR_I2C2EN 0x00400000U
<> 147:30b64687e01f 6129 #define RCC_APB1ENR_I2C3EN 0x00800000U
<> 147:30b64687e01f 6130 #define RCC_APB1ENR_I2C4EN 0x01000000U
<> 147:30b64687e01f 6131 #define RCC_APB1ENR_CAN1EN 0x02000000U
<> 147:30b64687e01f 6132 #define RCC_APB1ENR_CAN2EN 0x04000000U
<> 147:30b64687e01f 6133 #define RCC_APB1ENR_CECEN 0x08000000U
<> 147:30b64687e01f 6134 #define RCC_APB1ENR_PWREN 0x10000000U
<> 147:30b64687e01f 6135 #define RCC_APB1ENR_DACEN 0x20000000U
<> 147:30b64687e01f 6136 #define RCC_APB1ENR_UART7EN 0x40000000U
<> 147:30b64687e01f 6137 #define RCC_APB1ENR_UART8EN 0x80000000U
<> 147:30b64687e01f 6138
<> 147:30b64687e01f 6139 /******************** Bit definition for RCC_APB2ENR register ***************/
<> 147:30b64687e01f 6140 #define RCC_APB2ENR_TIM1EN 0x00000001U
<> 147:30b64687e01f 6141 #define RCC_APB2ENR_TIM8EN 0x00000002U
<> 147:30b64687e01f 6142 #define RCC_APB2ENR_USART1EN 0x00000010U
<> 147:30b64687e01f 6143 #define RCC_APB2ENR_USART6EN 0x00000020U
<> 147:30b64687e01f 6144 #define RCC_APB2ENR_SDMMC2EN 0x00000080U
<> 147:30b64687e01f 6145 #define RCC_APB2ENR_ADC1EN 0x00000100U
<> 147:30b64687e01f 6146 #define RCC_APB2ENR_ADC2EN 0x00000200U
<> 147:30b64687e01f 6147 #define RCC_APB2ENR_ADC3EN 0x00000400U
<> 147:30b64687e01f 6148 #define RCC_APB2ENR_SDMMC1EN 0x00000800U
<> 147:30b64687e01f 6149 #define RCC_APB2ENR_SPI1EN 0x00001000U
<> 147:30b64687e01f 6150 #define RCC_APB2ENR_SPI4EN 0x00002000U
<> 147:30b64687e01f 6151 #define RCC_APB2ENR_SYSCFGEN 0x00004000U
<> 147:30b64687e01f 6152 #define RCC_APB2ENR_TIM9EN 0x00010000U
<> 147:30b64687e01f 6153 #define RCC_APB2ENR_TIM10EN 0x00020000U
<> 147:30b64687e01f 6154 #define RCC_APB2ENR_TIM11EN 0x00040000U
<> 147:30b64687e01f 6155 #define RCC_APB2ENR_SPI5EN 0x00100000U
<> 147:30b64687e01f 6156 #define RCC_APB2ENR_SPI6EN 0x00200000U
<> 147:30b64687e01f 6157 #define RCC_APB2ENR_SAI1EN 0x00400000U
<> 147:30b64687e01f 6158 #define RCC_APB2ENR_SAI2EN 0x00800000U
<> 147:30b64687e01f 6159 #define RCC_APB2ENR_LTDCEN 0x04000000U
<> 147:30b64687e01f 6160 #define RCC_APB2ENR_DSIEN 0x08000000U
<> 147:30b64687e01f 6161 #define RCC_APB2ENR_DFSDM1EN 0x20000000U
<> 147:30b64687e01f 6162 #define RCC_APB2ENR_MDIOEN 0x40000000U
<> 147:30b64687e01f 6163
<> 147:30b64687e01f 6164 /******************** Bit definition for RCC_AHB1LPENR register *************/
<> 147:30b64687e01f 6165 #define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
<> 147:30b64687e01f 6166 #define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
<> 147:30b64687e01f 6167 #define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
<> 147:30b64687e01f 6168 #define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
<> 147:30b64687e01f 6169 #define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
<> 147:30b64687e01f 6170 #define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
<> 147:30b64687e01f 6171 #define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
<> 147:30b64687e01f 6172 #define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
<> 147:30b64687e01f 6173 #define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
<> 147:30b64687e01f 6174 #define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
<> 147:30b64687e01f 6175 #define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
<> 147:30b64687e01f 6176 #define RCC_AHB1LPENR_CRCLPEN 0x00001000U
<> 147:30b64687e01f 6177 #define RCC_AHB1LPENR_AXILPEN 0x00002000U
<> 147:30b64687e01f 6178 #define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
<> 147:30b64687e01f 6179 #define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
<> 147:30b64687e01f 6180 #define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
<> 147:30b64687e01f 6181 #define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
<> 147:30b64687e01f 6182 #define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
<> 147:30b64687e01f 6183 #define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
<> 147:30b64687e01f 6184 #define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
<> 147:30b64687e01f 6185 #define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
<> 147:30b64687e01f 6186 #define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
<> 147:30b64687e01f 6187 #define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
<> 147:30b64687e01f 6188 #define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
<> 147:30b64687e01f 6189 #define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
<> 147:30b64687e01f 6190 #define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
<> 147:30b64687e01f 6191 #define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
<> 147:30b64687e01f 6192
<> 147:30b64687e01f 6193 /******************** Bit definition for RCC_AHB2LPENR register *************/
<> 147:30b64687e01f 6194 #define RCC_AHB2LPENR_DCMILPEN 0x00000001U
<> 147:30b64687e01f 6195 #define RCC_AHB2LPENR_JPEGLPEN 0x00000002U
<> 147:30b64687e01f 6196 #define RCC_AHB2LPENR_RNGLPEN 0x00000040U
<> 147:30b64687e01f 6197 #define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
<> 147:30b64687e01f 6198
<> 147:30b64687e01f 6199 /******************** Bit definition for RCC_AHB3LPENR register *************/
<> 147:30b64687e01f 6200 #define RCC_AHB3LPENR_FMCLPEN 0x00000001U
<> 147:30b64687e01f 6201 #define RCC_AHB3LPENR_QSPILPEN 0x00000002U
<> 147:30b64687e01f 6202 /******************** Bit definition for RCC_APB1LPENR register *************/
<> 147:30b64687e01f 6203 #define RCC_APB1LPENR_TIM2LPEN 0x00000001U
<> 147:30b64687e01f 6204 #define RCC_APB1LPENR_TIM3LPEN 0x00000002U
<> 147:30b64687e01f 6205 #define RCC_APB1LPENR_TIM4LPEN 0x00000004U
<> 147:30b64687e01f 6206 #define RCC_APB1LPENR_TIM5LPEN 0x00000008U
<> 147:30b64687e01f 6207 #define RCC_APB1LPENR_TIM6LPEN 0x00000010U
<> 147:30b64687e01f 6208 #define RCC_APB1LPENR_TIM7LPEN 0x00000020U
<> 147:30b64687e01f 6209 #define RCC_APB1LPENR_TIM12LPEN 0x00000040U
<> 147:30b64687e01f 6210 #define RCC_APB1LPENR_TIM13LPEN 0x00000080U
<> 147:30b64687e01f 6211 #define RCC_APB1LPENR_TIM14LPEN 0x00000100U
<> 147:30b64687e01f 6212 #define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
<> 147:30b64687e01f 6213 #define RCC_APB1LPENR_RTCLPEN 0x00000400U
<> 147:30b64687e01f 6214 #define RCC_APB1LPENR_WWDGLPEN 0x00000800U
<> 147:30b64687e01f 6215 #define RCC_APB1LPENR_CAN3LPEN 0x00002000U
<> 147:30b64687e01f 6216 #define RCC_APB1LPENR_SPI2LPEN 0x00004000U
<> 147:30b64687e01f 6217 #define RCC_APB1LPENR_SPI3LPEN 0x00008000U
<> 147:30b64687e01f 6218 #define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
<> 147:30b64687e01f 6219 #define RCC_APB1LPENR_USART2LPEN 0x00020000U
<> 147:30b64687e01f 6220 #define RCC_APB1LPENR_USART3LPEN 0x00040000U
<> 147:30b64687e01f 6221 #define RCC_APB1LPENR_UART4LPEN 0x00080000U
<> 147:30b64687e01f 6222 #define RCC_APB1LPENR_UART5LPEN 0x00100000U
<> 147:30b64687e01f 6223 #define RCC_APB1LPENR_I2C1LPEN 0x00200000U
<> 147:30b64687e01f 6224 #define RCC_APB1LPENR_I2C2LPEN 0x00400000U
<> 147:30b64687e01f 6225 #define RCC_APB1LPENR_I2C3LPEN 0x00800000U
<> 147:30b64687e01f 6226 #define RCC_APB1LPENR_I2C4LPEN 0x01000000U
<> 147:30b64687e01f 6227 #define RCC_APB1LPENR_CAN1LPEN 0x02000000U
<> 147:30b64687e01f 6228 #define RCC_APB1LPENR_CAN2LPEN 0x04000000U
<> 147:30b64687e01f 6229 #define RCC_APB1LPENR_CECLPEN 0x08000000U
<> 147:30b64687e01f 6230 #define RCC_APB1LPENR_PWRLPEN 0x10000000U
<> 147:30b64687e01f 6231 #define RCC_APB1LPENR_DACLPEN 0x20000000U
<> 147:30b64687e01f 6232 #define RCC_APB1LPENR_UART7LPEN 0x40000000U
<> 147:30b64687e01f 6233 #define RCC_APB1LPENR_UART8LPEN 0x80000000U
<> 147:30b64687e01f 6234
<> 147:30b64687e01f 6235 /******************** Bit definition for RCC_APB2LPENR register *************/
<> 147:30b64687e01f 6236 #define RCC_APB2LPENR_TIM1LPEN 0x00000001U
<> 147:30b64687e01f 6237 #define RCC_APB2LPENR_TIM8LPEN 0x00000002U
<> 147:30b64687e01f 6238 #define RCC_APB2LPENR_USART1LPEN 0x00000010U
<> 147:30b64687e01f 6239 #define RCC_APB2LPENR_USART6LPEN 0x00000020U
<> 147:30b64687e01f 6240 #define RCC_APB2LPENR_SDMMC2LPEN 0x00000080U
<> 147:30b64687e01f 6241 #define RCC_APB2LPENR_ADC1LPEN 0x00000100U
<> 147:30b64687e01f 6242 #define RCC_APB2LPENR_ADC2LPEN 0x00000200U
<> 147:30b64687e01f 6243 #define RCC_APB2LPENR_ADC3LPEN 0x00000400U
<> 147:30b64687e01f 6244 #define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
<> 147:30b64687e01f 6245 #define RCC_APB2LPENR_SPI1LPEN 0x00001000U
<> 147:30b64687e01f 6246 #define RCC_APB2LPENR_SPI4LPEN 0x00002000U
<> 147:30b64687e01f 6247 #define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
<> 147:30b64687e01f 6248 #define RCC_APB2LPENR_TIM9LPEN 0x00010000U
<> 147:30b64687e01f 6249 #define RCC_APB2LPENR_TIM10LPEN 0x00020000U
<> 147:30b64687e01f 6250 #define RCC_APB2LPENR_TIM11LPEN 0x00040000U
<> 147:30b64687e01f 6251 #define RCC_APB2LPENR_SPI5LPEN 0x00100000U
<> 147:30b64687e01f 6252 #define RCC_APB2LPENR_SPI6LPEN 0x00200000U
<> 147:30b64687e01f 6253 #define RCC_APB2LPENR_SAI1LPEN 0x00400000U
<> 147:30b64687e01f 6254 #define RCC_APB2LPENR_SAI2LPEN 0x00800000U
<> 147:30b64687e01f 6255 #define RCC_APB2LPENR_LTDCLPEN 0x04000000U
<> 147:30b64687e01f 6256 #define RCC_APB2LPENR_DSILPEN 0x08000000U
<> 147:30b64687e01f 6257 #define RCC_APB2LPENR_DFSDM1LPEN 0x20000000U
<> 147:30b64687e01f 6258 #define RCC_APB2LPENR_MDIOLPEN 0x40000000U
<> 147:30b64687e01f 6259
<> 147:30b64687e01f 6260 /******************** Bit definition for RCC_BDCR register ******************/
<> 147:30b64687e01f 6261 #define RCC_BDCR_LSEON 0x00000001U
<> 147:30b64687e01f 6262 #define RCC_BDCR_LSERDY 0x00000002U
<> 147:30b64687e01f 6263 #define RCC_BDCR_LSEBYP 0x00000004U
<> 147:30b64687e01f 6264 #define RCC_BDCR_LSEDRV 0x00000018U
<> 147:30b64687e01f 6265 #define RCC_BDCR_LSEDRV_0 0x00000008U
<> 147:30b64687e01f 6266 #define RCC_BDCR_LSEDRV_1 0x00000010U
<> 147:30b64687e01f 6267 #define RCC_BDCR_RTCSEL 0x00000300U
<> 147:30b64687e01f 6268 #define RCC_BDCR_RTCSEL_0 0x00000100U
<> 147:30b64687e01f 6269 #define RCC_BDCR_RTCSEL_1 0x00000200U
<> 147:30b64687e01f 6270 #define RCC_BDCR_RTCEN 0x00008000U
<> 147:30b64687e01f 6271 #define RCC_BDCR_BDRST 0x00010000U
<> 147:30b64687e01f 6272
<> 147:30b64687e01f 6273 /******************** Bit definition for RCC_CSR register *******************/
<> 147:30b64687e01f 6274 #define RCC_CSR_LSION 0x00000001U
<> 147:30b64687e01f 6275 #define RCC_CSR_LSIRDY 0x00000002U
<> 147:30b64687e01f 6276 #define RCC_CSR_RMVF 0x01000000U
<> 147:30b64687e01f 6277 #define RCC_CSR_BORRSTF 0x02000000U
<> 147:30b64687e01f 6278 #define RCC_CSR_PINRSTF 0x04000000U
<> 147:30b64687e01f 6279 #define RCC_CSR_PORRSTF 0x08000000U
<> 147:30b64687e01f 6280 #define RCC_CSR_SFTRSTF 0x10000000U
<> 147:30b64687e01f 6281 #define RCC_CSR_IWDGRSTF 0x20000000U
<> 147:30b64687e01f 6282 #define RCC_CSR_WWDGRSTF 0x40000000U
<> 147:30b64687e01f 6283 #define RCC_CSR_LPWRRSTF 0x80000000U
<> 147:30b64687e01f 6284
<> 147:30b64687e01f 6285 /******************** Bit definition for RCC_SSCGR register *****************/
<> 147:30b64687e01f 6286 #define RCC_SSCGR_MODPER 0x00001FFFU
<> 147:30b64687e01f 6287 #define RCC_SSCGR_INCSTEP 0x0FFFE000U
<> 147:30b64687e01f 6288 #define RCC_SSCGR_SPREADSEL 0x40000000U
<> 147:30b64687e01f 6289 #define RCC_SSCGR_SSCGEN 0x80000000U
<> 147:30b64687e01f 6290
<> 147:30b64687e01f 6291 /******************** Bit definition for RCC_PLLI2SCFGR register ************/
<> 147:30b64687e01f 6292 #define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
<> 147:30b64687e01f 6293 #define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
<> 147:30b64687e01f 6294 #define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
<> 147:30b64687e01f 6295 #define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
<> 147:30b64687e01f 6296 #define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
<> 147:30b64687e01f 6297 #define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
<> 147:30b64687e01f 6298 #define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
<> 147:30b64687e01f 6299 #define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
<> 147:30b64687e01f 6300 #define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
<> 147:30b64687e01f 6301 #define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
<> 147:30b64687e01f 6302 #define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
<> 147:30b64687e01f 6303 #define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
<> 147:30b64687e01f 6304 #define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
<> 147:30b64687e01f 6305 #define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
<> 147:30b64687e01f 6306 #define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
<> 147:30b64687e01f 6307 #define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
<> 147:30b64687e01f 6308 #define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
<> 147:30b64687e01f 6309 #define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
<> 147:30b64687e01f 6310 #define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
<> 147:30b64687e01f 6311 #define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
<> 147:30b64687e01f 6312 #define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
<> 147:30b64687e01f 6313 #define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
<> 147:30b64687e01f 6314
<> 147:30b64687e01f 6315 /******************** Bit definition for RCC_PLLSAICFGR register ************/
<> 147:30b64687e01f 6316 #define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
<> 147:30b64687e01f 6317 #define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
<> 147:30b64687e01f 6318 #define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
<> 147:30b64687e01f 6319 #define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
<> 147:30b64687e01f 6320 #define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
<> 147:30b64687e01f 6321 #define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
<> 147:30b64687e01f 6322 #define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
<> 147:30b64687e01f 6323 #define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
<> 147:30b64687e01f 6324 #define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
<> 147:30b64687e01f 6325 #define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
<> 147:30b64687e01f 6326 #define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
<> 147:30b64687e01f 6327 #define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
<> 147:30b64687e01f 6328 #define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
<> 147:30b64687e01f 6329 #define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
<> 147:30b64687e01f 6330 #define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
<> 147:30b64687e01f 6331 #define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
<> 147:30b64687e01f 6332 #define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
<> 147:30b64687e01f 6333 #define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
<> 147:30b64687e01f 6334 #define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
<> 147:30b64687e01f 6335 #define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
<> 147:30b64687e01f 6336 #define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
<> 147:30b64687e01f 6337 #define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
<> 147:30b64687e01f 6338
<> 147:30b64687e01f 6339 /******************** Bit definition for RCC_DCKCFGR1 register ***************/
<> 147:30b64687e01f 6340 #define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
<> 147:30b64687e01f 6341 #define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
<> 147:30b64687e01f 6342 #define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
<> 147:30b64687e01f 6343 #define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
<> 147:30b64687e01f 6344 #define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
<> 147:30b64687e01f 6345 #define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
<> 147:30b64687e01f 6346
<> 147:30b64687e01f 6347 #define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
<> 147:30b64687e01f 6348 #define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
<> 147:30b64687e01f 6349 #define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
<> 147:30b64687e01f 6350 #define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
<> 147:30b64687e01f 6351 #define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
<> 147:30b64687e01f 6352 #define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
<> 147:30b64687e01f 6353
<> 147:30b64687e01f 6354 #define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
<> 147:30b64687e01f 6355 #define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
<> 147:30b64687e01f 6356 #define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
<> 147:30b64687e01f 6357
<> 147:30b64687e01f 6358 #define RCC_DCKCFGR1_SAI1SEL 0x00300000U
<> 147:30b64687e01f 6359 #define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
<> 147:30b64687e01f 6360 #define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
<> 147:30b64687e01f 6361
<> 147:30b64687e01f 6362 #define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
<> 147:30b64687e01f 6363 #define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
<> 147:30b64687e01f 6364 #define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
<> 147:30b64687e01f 6365
<> 147:30b64687e01f 6366 #define RCC_DCKCFGR1_TIMPRE 0x01000000U
<> 147:30b64687e01f 6367 #define RCC_DCKCFGR1_DFSDM1SEL 0x02000000U
<> 147:30b64687e01f 6368 #define RCC_DCKCFGR1_ADFSDM1SEL 0x04000000U
<> 147:30b64687e01f 6369
<> 147:30b64687e01f 6370 /******************** Bit definition for RCC_DCKCFGR2 register ***************/
<> 147:30b64687e01f 6371 #define RCC_DCKCFGR2_USART1SEL 0x00000003U
<> 147:30b64687e01f 6372 #define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
<> 147:30b64687e01f 6373 #define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
<> 147:30b64687e01f 6374 #define RCC_DCKCFGR2_USART2SEL 0x0000000CU
<> 147:30b64687e01f 6375 #define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
<> 147:30b64687e01f 6376 #define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
<> 147:30b64687e01f 6377 #define RCC_DCKCFGR2_USART3SEL 0x00000030U
<> 147:30b64687e01f 6378 #define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
<> 147:30b64687e01f 6379 #define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
<> 147:30b64687e01f 6380 #define RCC_DCKCFGR2_UART4SEL 0x000000C0U
<> 147:30b64687e01f 6381 #define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
<> 147:30b64687e01f 6382 #define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
<> 147:30b64687e01f 6383 #define RCC_DCKCFGR2_UART5SEL 0x00000300U
<> 147:30b64687e01f 6384 #define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
<> 147:30b64687e01f 6385 #define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
<> 147:30b64687e01f 6386 #define RCC_DCKCFGR2_USART6SEL 0x00000C00U
<> 147:30b64687e01f 6387 #define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
<> 147:30b64687e01f 6388 #define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
<> 147:30b64687e01f 6389 #define RCC_DCKCFGR2_UART7SEL 0x00003000U
<> 147:30b64687e01f 6390 #define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
<> 147:30b64687e01f 6391 #define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
<> 147:30b64687e01f 6392 #define RCC_DCKCFGR2_UART8SEL 0x0000C000U
<> 147:30b64687e01f 6393 #define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
<> 147:30b64687e01f 6394 #define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
<> 147:30b64687e01f 6395 #define RCC_DCKCFGR2_I2C1SEL 0x00030000U
<> 147:30b64687e01f 6396 #define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
<> 147:30b64687e01f 6397 #define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
<> 147:30b64687e01f 6398 #define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
<> 147:30b64687e01f 6399 #define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
<> 147:30b64687e01f 6400 #define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
<> 147:30b64687e01f 6401 #define RCC_DCKCFGR2_I2C3SEL 0x00300000U
<> 147:30b64687e01f 6402 #define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
<> 147:30b64687e01f 6403 #define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
<> 147:30b64687e01f 6404 #define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
<> 147:30b64687e01f 6405 #define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
<> 147:30b64687e01f 6406 #define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
<> 147:30b64687e01f 6407 #define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
<> 147:30b64687e01f 6408 #define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
<> 147:30b64687e01f 6409 #define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
<> 147:30b64687e01f 6410 #define RCC_DCKCFGR2_CECSEL 0x04000000U
<> 147:30b64687e01f 6411 #define RCC_DCKCFGR2_CK48MSEL 0x08000000U
<> 147:30b64687e01f 6412 #define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
<> 147:30b64687e01f 6413 #define RCC_DCKCFGR2_SDMMC2SEL 0x20000000U
<> 147:30b64687e01f 6414 #define RCC_DCKCFGR2_DSISEL 0x40000000U
<> 147:30b64687e01f 6415
<> 147:30b64687e01f 6416 /******************************************************************************/
<> 147:30b64687e01f 6417 /* */
<> 147:30b64687e01f 6418 /* RNG */
<> 147:30b64687e01f 6419 /* */
<> 147:30b64687e01f 6420 /******************************************************************************/
<> 147:30b64687e01f 6421 /******************** Bits definition for RNG_CR register *******************/
<> 147:30b64687e01f 6422 #define RNG_CR_RNGEN 0x00000004U
<> 147:30b64687e01f 6423 #define RNG_CR_IE 0x00000008U
<> 147:30b64687e01f 6424
<> 147:30b64687e01f 6425 /******************** Bits definition for RNG_SR register *******************/
<> 147:30b64687e01f 6426 #define RNG_SR_DRDY 0x00000001U
<> 147:30b64687e01f 6427 #define RNG_SR_CECS 0x00000002U
<> 147:30b64687e01f 6428 #define RNG_SR_SECS 0x00000004U
<> 147:30b64687e01f 6429 #define RNG_SR_CEIS 0x00000020U
<> 147:30b64687e01f 6430 #define RNG_SR_SEIS 0x00000040U
<> 147:30b64687e01f 6431
<> 147:30b64687e01f 6432 /******************************************************************************/
<> 147:30b64687e01f 6433 /* */
<> 147:30b64687e01f 6434 /* Real-Time Clock (RTC) */
<> 147:30b64687e01f 6435 /* */
<> 147:30b64687e01f 6436 /******************************************************************************/
<> 147:30b64687e01f 6437 /******************** Bits definition for RTC_TR register *******************/
<> 147:30b64687e01f 6438 #define RTC_TR_PM 0x00400000U
<> 147:30b64687e01f 6439 #define RTC_TR_HT 0x00300000U
<> 147:30b64687e01f 6440 #define RTC_TR_HT_0 0x00100000U
<> 147:30b64687e01f 6441 #define RTC_TR_HT_1 0x00200000U
<> 147:30b64687e01f 6442 #define RTC_TR_HU 0x000F0000U
<> 147:30b64687e01f 6443 #define RTC_TR_HU_0 0x00010000U
<> 147:30b64687e01f 6444 #define RTC_TR_HU_1 0x00020000U
<> 147:30b64687e01f 6445 #define RTC_TR_HU_2 0x00040000U
<> 147:30b64687e01f 6446 #define RTC_TR_HU_3 0x00080000U
<> 147:30b64687e01f 6447 #define RTC_TR_MNT 0x00007000U
<> 147:30b64687e01f 6448 #define RTC_TR_MNT_0 0x00001000U
<> 147:30b64687e01f 6449 #define RTC_TR_MNT_1 0x00002000U
<> 147:30b64687e01f 6450 #define RTC_TR_MNT_2 0x00004000U
<> 147:30b64687e01f 6451 #define RTC_TR_MNU 0x00000F00U
<> 147:30b64687e01f 6452 #define RTC_TR_MNU_0 0x00000100U
<> 147:30b64687e01f 6453 #define RTC_TR_MNU_1 0x00000200U
<> 147:30b64687e01f 6454 #define RTC_TR_MNU_2 0x00000400U
<> 147:30b64687e01f 6455 #define RTC_TR_MNU_3 0x00000800U
<> 147:30b64687e01f 6456 #define RTC_TR_ST 0x00000070U
<> 147:30b64687e01f 6457 #define RTC_TR_ST_0 0x00000010U
<> 147:30b64687e01f 6458 #define RTC_TR_ST_1 0x00000020U
<> 147:30b64687e01f 6459 #define RTC_TR_ST_2 0x00000040U
<> 147:30b64687e01f 6460 #define RTC_TR_SU 0x0000000FU
<> 147:30b64687e01f 6461 #define RTC_TR_SU_0 0x00000001U
<> 147:30b64687e01f 6462 #define RTC_TR_SU_1 0x00000002U
<> 147:30b64687e01f 6463 #define RTC_TR_SU_2 0x00000004U
<> 147:30b64687e01f 6464 #define RTC_TR_SU_3 0x00000008U
<> 147:30b64687e01f 6465
<> 147:30b64687e01f 6466 /******************** Bits definition for RTC_DR register *******************/
<> 147:30b64687e01f 6467 #define RTC_DR_YT 0x00F00000U
<> 147:30b64687e01f 6468 #define RTC_DR_YT_0 0x00100000U
<> 147:30b64687e01f 6469 #define RTC_DR_YT_1 0x00200000U
<> 147:30b64687e01f 6470 #define RTC_DR_YT_2 0x00400000U
<> 147:30b64687e01f 6471 #define RTC_DR_YT_3 0x00800000U
<> 147:30b64687e01f 6472 #define RTC_DR_YU 0x000F0000U
<> 147:30b64687e01f 6473 #define RTC_DR_YU_0 0x00010000U
<> 147:30b64687e01f 6474 #define RTC_DR_YU_1 0x00020000U
<> 147:30b64687e01f 6475 #define RTC_DR_YU_2 0x00040000U
<> 147:30b64687e01f 6476 #define RTC_DR_YU_3 0x00080000U
<> 147:30b64687e01f 6477 #define RTC_DR_WDU 0x0000E000U
<> 147:30b64687e01f 6478 #define RTC_DR_WDU_0 0x00002000U
<> 147:30b64687e01f 6479 #define RTC_DR_WDU_1 0x00004000U
<> 147:30b64687e01f 6480 #define RTC_DR_WDU_2 0x00008000U
<> 147:30b64687e01f 6481 #define RTC_DR_MT 0x00001000U
<> 147:30b64687e01f 6482 #define RTC_DR_MU 0x00000F00U
<> 147:30b64687e01f 6483 #define RTC_DR_MU_0 0x00000100U
<> 147:30b64687e01f 6484 #define RTC_DR_MU_1 0x00000200U
<> 147:30b64687e01f 6485 #define RTC_DR_MU_2 0x00000400U
<> 147:30b64687e01f 6486 #define RTC_DR_MU_3 0x00000800U
<> 147:30b64687e01f 6487 #define RTC_DR_DT 0x00000030U
<> 147:30b64687e01f 6488 #define RTC_DR_DT_0 0x00000010U
<> 147:30b64687e01f 6489 #define RTC_DR_DT_1 0x00000020U
<> 147:30b64687e01f 6490 #define RTC_DR_DU 0x0000000FU
<> 147:30b64687e01f 6491 #define RTC_DR_DU_0 0x00000001U
<> 147:30b64687e01f 6492 #define RTC_DR_DU_1 0x00000002U
<> 147:30b64687e01f 6493 #define RTC_DR_DU_2 0x00000004U
<> 147:30b64687e01f 6494 #define RTC_DR_DU_3 0x00000008U
<> 147:30b64687e01f 6495
<> 147:30b64687e01f 6496 /******************** Bits definition for RTC_CR register *******************/
<> 147:30b64687e01f 6497 #define RTC_CR_ITSE 0x01000000U
<> 147:30b64687e01f 6498 #define RTC_CR_COE 0x00800000U
<> 147:30b64687e01f 6499 #define RTC_CR_OSEL 0x00600000U
<> 147:30b64687e01f 6500 #define RTC_CR_OSEL_0 0x00200000U
<> 147:30b64687e01f 6501 #define RTC_CR_OSEL_1 0x00400000U
<> 147:30b64687e01f 6502 #define RTC_CR_POL 0x00100000U
<> 147:30b64687e01f 6503 #define RTC_CR_COSEL 0x00080000U
<> 157:ff67d9f36b67 6504 #define RTC_CR_BKP 0x00040000U
<> 147:30b64687e01f 6505 #define RTC_CR_SUB1H 0x00020000U
<> 147:30b64687e01f 6506 #define RTC_CR_ADD1H 0x00010000U
<> 147:30b64687e01f 6507 #define RTC_CR_TSIE 0x00008000U
<> 147:30b64687e01f 6508 #define RTC_CR_WUTIE 0x00004000U
<> 147:30b64687e01f 6509 #define RTC_CR_ALRBIE 0x00002000U
<> 147:30b64687e01f 6510 #define RTC_CR_ALRAIE 0x00001000U
<> 147:30b64687e01f 6511 #define RTC_CR_TSE 0x00000800U
<> 147:30b64687e01f 6512 #define RTC_CR_WUTE 0x00000400U
<> 147:30b64687e01f 6513 #define RTC_CR_ALRBE 0x00000200U
<> 147:30b64687e01f 6514 #define RTC_CR_ALRAE 0x00000100U
<> 147:30b64687e01f 6515 #define RTC_CR_FMT 0x00000040U
<> 147:30b64687e01f 6516 #define RTC_CR_BYPSHAD 0x00000020U
<> 147:30b64687e01f 6517 #define RTC_CR_REFCKON 0x00000010U
<> 147:30b64687e01f 6518 #define RTC_CR_TSEDGE 0x00000008U
<> 147:30b64687e01f 6519 #define RTC_CR_WUCKSEL 0x00000007U
<> 147:30b64687e01f 6520 #define RTC_CR_WUCKSEL_0 0x00000001U
<> 147:30b64687e01f 6521 #define RTC_CR_WUCKSEL_1 0x00000002U
<> 147:30b64687e01f 6522 #define RTC_CR_WUCKSEL_2 0x00000004U
<> 147:30b64687e01f 6523
<> 157:ff67d9f36b67 6524 /* Legacy define */
<> 157:ff67d9f36b67 6525 #define RTC_CR_BCK RTC_CR_BKP
<> 157:ff67d9f36b67 6526
<> 147:30b64687e01f 6527 /******************** Bits definition for RTC_ISR register ******************/
<> 147:30b64687e01f 6528 #define RTC_ISR_ITSF 0x00020000U
<> 147:30b64687e01f 6529 #define RTC_ISR_RECALPF 0x00010000U
<> 147:30b64687e01f 6530 #define RTC_ISR_TAMP3F 0x00008000U
<> 147:30b64687e01f 6531 #define RTC_ISR_TAMP2F 0x00004000U
<> 147:30b64687e01f 6532 #define RTC_ISR_TAMP1F 0x00002000U
<> 147:30b64687e01f 6533 #define RTC_ISR_TSOVF 0x00001000U
<> 147:30b64687e01f 6534 #define RTC_ISR_TSF 0x00000800U
<> 147:30b64687e01f 6535 #define RTC_ISR_WUTF 0x00000400U
<> 147:30b64687e01f 6536 #define RTC_ISR_ALRBF 0x00000200U
<> 147:30b64687e01f 6537 #define RTC_ISR_ALRAF 0x00000100U
<> 147:30b64687e01f 6538 #define RTC_ISR_INIT 0x00000080U
<> 147:30b64687e01f 6539 #define RTC_ISR_INITF 0x00000040U
<> 147:30b64687e01f 6540 #define RTC_ISR_RSF 0x00000020U
<> 147:30b64687e01f 6541 #define RTC_ISR_INITS 0x00000010U
<> 147:30b64687e01f 6542 #define RTC_ISR_SHPF 0x00000008U
<> 147:30b64687e01f 6543 #define RTC_ISR_WUTWF 0x00000004U
<> 147:30b64687e01f 6544 #define RTC_ISR_ALRBWF 0x00000002U
<> 147:30b64687e01f 6545 #define RTC_ISR_ALRAWF 0x00000001U
<> 147:30b64687e01f 6546
<> 147:30b64687e01f 6547 /******************** Bits definition for RTC_PRER register *****************/
<> 147:30b64687e01f 6548 #define RTC_PRER_PREDIV_A 0x007F0000U
<> 147:30b64687e01f 6549 #define RTC_PRER_PREDIV_S 0x00007FFFU
<> 147:30b64687e01f 6550
<> 147:30b64687e01f 6551 /******************** Bits definition for RTC_WUTR register *****************/
<> 147:30b64687e01f 6552 #define RTC_WUTR_WUT 0x0000FFFFU
<> 147:30b64687e01f 6553
<> 147:30b64687e01f 6554 /******************** Bits definition for RTC_ALRMAR register ***************/
<> 147:30b64687e01f 6555 #define RTC_ALRMAR_MSK4 0x80000000U
<> 147:30b64687e01f 6556 #define RTC_ALRMAR_WDSEL 0x40000000U
<> 147:30b64687e01f 6557 #define RTC_ALRMAR_DT 0x30000000U
<> 147:30b64687e01f 6558 #define RTC_ALRMAR_DT_0 0x10000000U
<> 147:30b64687e01f 6559 #define RTC_ALRMAR_DT_1 0x20000000U
<> 147:30b64687e01f 6560 #define RTC_ALRMAR_DU 0x0F000000U
<> 147:30b64687e01f 6561 #define RTC_ALRMAR_DU_0 0x01000000U
<> 147:30b64687e01f 6562 #define RTC_ALRMAR_DU_1 0x02000000U
<> 147:30b64687e01f 6563 #define RTC_ALRMAR_DU_2 0x04000000U
<> 147:30b64687e01f 6564 #define RTC_ALRMAR_DU_3 0x08000000U
<> 147:30b64687e01f 6565 #define RTC_ALRMAR_MSK3 0x00800000U
<> 147:30b64687e01f 6566 #define RTC_ALRMAR_PM 0x00400000U
<> 147:30b64687e01f 6567 #define RTC_ALRMAR_HT 0x00300000U
<> 147:30b64687e01f 6568 #define RTC_ALRMAR_HT_0 0x00100000U
<> 147:30b64687e01f 6569 #define RTC_ALRMAR_HT_1 0x00200000U
<> 147:30b64687e01f 6570 #define RTC_ALRMAR_HU 0x000F0000U
<> 147:30b64687e01f 6571 #define RTC_ALRMAR_HU_0 0x00010000U
<> 147:30b64687e01f 6572 #define RTC_ALRMAR_HU_1 0x00020000U
<> 147:30b64687e01f 6573 #define RTC_ALRMAR_HU_2 0x00040000U
<> 147:30b64687e01f 6574 #define RTC_ALRMAR_HU_3 0x00080000U
<> 147:30b64687e01f 6575 #define RTC_ALRMAR_MSK2 0x00008000U
<> 147:30b64687e01f 6576 #define RTC_ALRMAR_MNT 0x00007000U
<> 147:30b64687e01f 6577 #define RTC_ALRMAR_MNT_0 0x00001000U
<> 147:30b64687e01f 6578 #define RTC_ALRMAR_MNT_1 0x00002000U
<> 147:30b64687e01f 6579 #define RTC_ALRMAR_MNT_2 0x00004000U
<> 147:30b64687e01f 6580 #define RTC_ALRMAR_MNU 0x00000F00U
<> 147:30b64687e01f 6581 #define RTC_ALRMAR_MNU_0 0x00000100U
<> 147:30b64687e01f 6582 #define RTC_ALRMAR_MNU_1 0x00000200U
<> 147:30b64687e01f 6583 #define RTC_ALRMAR_MNU_2 0x00000400U
<> 147:30b64687e01f 6584 #define RTC_ALRMAR_MNU_3 0x00000800U
<> 147:30b64687e01f 6585 #define RTC_ALRMAR_MSK1 0x00000080U
<> 147:30b64687e01f 6586 #define RTC_ALRMAR_ST 0x00000070U
<> 147:30b64687e01f 6587 #define RTC_ALRMAR_ST_0 0x00000010U
<> 147:30b64687e01f 6588 #define RTC_ALRMAR_ST_1 0x00000020U
<> 147:30b64687e01f 6589 #define RTC_ALRMAR_ST_2 0x00000040U
<> 147:30b64687e01f 6590 #define RTC_ALRMAR_SU 0x0000000FU
<> 147:30b64687e01f 6591 #define RTC_ALRMAR_SU_0 0x00000001U
<> 147:30b64687e01f 6592 #define RTC_ALRMAR_SU_1 0x00000002U
<> 147:30b64687e01f 6593 #define RTC_ALRMAR_SU_2 0x00000004U
<> 147:30b64687e01f 6594 #define RTC_ALRMAR_SU_3 0x00000008U
<> 147:30b64687e01f 6595
<> 147:30b64687e01f 6596 /******************** Bits definition for RTC_ALRMBR register ***************/
<> 147:30b64687e01f 6597 #define RTC_ALRMBR_MSK4 0x80000000U
<> 147:30b64687e01f 6598 #define RTC_ALRMBR_WDSEL 0x40000000U
<> 147:30b64687e01f 6599 #define RTC_ALRMBR_DT 0x30000000U
<> 147:30b64687e01f 6600 #define RTC_ALRMBR_DT_0 0x10000000U
<> 147:30b64687e01f 6601 #define RTC_ALRMBR_DT_1 0x20000000U
<> 147:30b64687e01f 6602 #define RTC_ALRMBR_DU 0x0F000000U
<> 147:30b64687e01f 6603 #define RTC_ALRMBR_DU_0 0x01000000U
<> 147:30b64687e01f 6604 #define RTC_ALRMBR_DU_1 0x02000000U
<> 147:30b64687e01f 6605 #define RTC_ALRMBR_DU_2 0x04000000U
<> 147:30b64687e01f 6606 #define RTC_ALRMBR_DU_3 0x08000000U
<> 147:30b64687e01f 6607 #define RTC_ALRMBR_MSK3 0x00800000U
<> 147:30b64687e01f 6608 #define RTC_ALRMBR_PM 0x00400000U
<> 147:30b64687e01f 6609 #define RTC_ALRMBR_HT 0x00300000U
<> 147:30b64687e01f 6610 #define RTC_ALRMBR_HT_0 0x00100000U
<> 147:30b64687e01f 6611 #define RTC_ALRMBR_HT_1 0x00200000U
<> 147:30b64687e01f 6612 #define RTC_ALRMBR_HU 0x000F0000U
<> 147:30b64687e01f 6613 #define RTC_ALRMBR_HU_0 0x00010000U
<> 147:30b64687e01f 6614 #define RTC_ALRMBR_HU_1 0x00020000U
<> 147:30b64687e01f 6615 #define RTC_ALRMBR_HU_2 0x00040000U
<> 147:30b64687e01f 6616 #define RTC_ALRMBR_HU_3 0x00080000U
<> 147:30b64687e01f 6617 #define RTC_ALRMBR_MSK2 0x00008000U
<> 147:30b64687e01f 6618 #define RTC_ALRMBR_MNT 0x00007000U
<> 147:30b64687e01f 6619 #define RTC_ALRMBR_MNT_0 0x00001000U
<> 147:30b64687e01f 6620 #define RTC_ALRMBR_MNT_1 0x00002000U
<> 147:30b64687e01f 6621 #define RTC_ALRMBR_MNT_2 0x00004000U
<> 147:30b64687e01f 6622 #define RTC_ALRMBR_MNU 0x00000F00U
<> 147:30b64687e01f 6623 #define RTC_ALRMBR_MNU_0 0x00000100U
<> 147:30b64687e01f 6624 #define RTC_ALRMBR_MNU_1 0x00000200U
<> 147:30b64687e01f 6625 #define RTC_ALRMBR_MNU_2 0x00000400U
<> 147:30b64687e01f 6626 #define RTC_ALRMBR_MNU_3 0x00000800U
<> 147:30b64687e01f 6627 #define RTC_ALRMBR_MSK1 0x00000080U
<> 147:30b64687e01f 6628 #define RTC_ALRMBR_ST 0x00000070U
<> 147:30b64687e01f 6629 #define RTC_ALRMBR_ST_0 0x00000010U
<> 147:30b64687e01f 6630 #define RTC_ALRMBR_ST_1 0x00000020U
<> 147:30b64687e01f 6631 #define RTC_ALRMBR_ST_2 0x00000040U
<> 147:30b64687e01f 6632 #define RTC_ALRMBR_SU 0x0000000FU
<> 147:30b64687e01f 6633 #define RTC_ALRMBR_SU_0 0x00000001U
<> 147:30b64687e01f 6634 #define RTC_ALRMBR_SU_1 0x00000002U
<> 147:30b64687e01f 6635 #define RTC_ALRMBR_SU_2 0x00000004U
<> 147:30b64687e01f 6636 #define RTC_ALRMBR_SU_3 0x00000008U
<> 147:30b64687e01f 6637
<> 147:30b64687e01f 6638 /******************** Bits definition for RTC_WPR register ******************/
<> 147:30b64687e01f 6639 #define RTC_WPR_KEY 0x000000FFU
<> 147:30b64687e01f 6640
<> 147:30b64687e01f 6641 /******************** Bits definition for RTC_SSR register ******************/
<> 147:30b64687e01f 6642 #define RTC_SSR_SS 0x0000FFFFU
<> 147:30b64687e01f 6643
<> 147:30b64687e01f 6644 /******************** Bits definition for RTC_SHIFTR register ***************/
<> 147:30b64687e01f 6645 #define RTC_SHIFTR_SUBFS 0x00007FFFU
<> 147:30b64687e01f 6646 #define RTC_SHIFTR_ADD1S 0x80000000U
<> 147:30b64687e01f 6647
<> 147:30b64687e01f 6648 /******************** Bits definition for RTC_TSTR register *****************/
<> 147:30b64687e01f 6649 #define RTC_TSTR_PM 0x00400000U
<> 147:30b64687e01f 6650 #define RTC_TSTR_HT 0x00300000U
<> 147:30b64687e01f 6651 #define RTC_TSTR_HT_0 0x00100000U
<> 147:30b64687e01f 6652 #define RTC_TSTR_HT_1 0x00200000U
<> 147:30b64687e01f 6653 #define RTC_TSTR_HU 0x000F0000U
<> 147:30b64687e01f 6654 #define RTC_TSTR_HU_0 0x00010000U
<> 147:30b64687e01f 6655 #define RTC_TSTR_HU_1 0x00020000U
<> 147:30b64687e01f 6656 #define RTC_TSTR_HU_2 0x00040000U
<> 147:30b64687e01f 6657 #define RTC_TSTR_HU_3 0x00080000U
<> 147:30b64687e01f 6658 #define RTC_TSTR_MNT 0x00007000U
<> 147:30b64687e01f 6659 #define RTC_TSTR_MNT_0 0x00001000U
<> 147:30b64687e01f 6660 #define RTC_TSTR_MNT_1 0x00002000U
<> 147:30b64687e01f 6661 #define RTC_TSTR_MNT_2 0x00004000U
<> 147:30b64687e01f 6662 #define RTC_TSTR_MNU 0x00000F00U
<> 147:30b64687e01f 6663 #define RTC_TSTR_MNU_0 0x00000100U
<> 147:30b64687e01f 6664 #define RTC_TSTR_MNU_1 0x00000200U
<> 147:30b64687e01f 6665 #define RTC_TSTR_MNU_2 0x00000400U
<> 147:30b64687e01f 6666 #define RTC_TSTR_MNU_3 0x00000800U
<> 147:30b64687e01f 6667 #define RTC_TSTR_ST 0x00000070U
<> 147:30b64687e01f 6668 #define RTC_TSTR_ST_0 0x00000010U
<> 147:30b64687e01f 6669 #define RTC_TSTR_ST_1 0x00000020U
<> 147:30b64687e01f 6670 #define RTC_TSTR_ST_2 0x00000040U
<> 147:30b64687e01f 6671 #define RTC_TSTR_SU 0x0000000FU
<> 147:30b64687e01f 6672 #define RTC_TSTR_SU_0 0x00000001U
<> 147:30b64687e01f 6673 #define RTC_TSTR_SU_1 0x00000002U
<> 147:30b64687e01f 6674 #define RTC_TSTR_SU_2 0x00000004U
<> 147:30b64687e01f 6675 #define RTC_TSTR_SU_3 0x00000008U
<> 147:30b64687e01f 6676
<> 147:30b64687e01f 6677 /******************** Bits definition for RTC_TSDR register *****************/
<> 147:30b64687e01f 6678 #define RTC_TSDR_WDU 0x0000E000U
<> 147:30b64687e01f 6679 #define RTC_TSDR_WDU_0 0x00002000U
<> 147:30b64687e01f 6680 #define RTC_TSDR_WDU_1 0x00004000U
<> 147:30b64687e01f 6681 #define RTC_TSDR_WDU_2 0x00008000U
<> 147:30b64687e01f 6682 #define RTC_TSDR_MT 0x00001000U
<> 147:30b64687e01f 6683 #define RTC_TSDR_MU 0x00000F00U
<> 147:30b64687e01f 6684 #define RTC_TSDR_MU_0 0x00000100U
<> 147:30b64687e01f 6685 #define RTC_TSDR_MU_1 0x00000200U
<> 147:30b64687e01f 6686 #define RTC_TSDR_MU_2 0x00000400U
<> 147:30b64687e01f 6687 #define RTC_TSDR_MU_3 0x00000800U
<> 147:30b64687e01f 6688 #define RTC_TSDR_DT 0x00000030U
<> 147:30b64687e01f 6689 #define RTC_TSDR_DT_0 0x00000010U
<> 147:30b64687e01f 6690 #define RTC_TSDR_DT_1 0x00000020U
<> 147:30b64687e01f 6691 #define RTC_TSDR_DU 0x0000000FU
<> 147:30b64687e01f 6692 #define RTC_TSDR_DU_0 0x00000001U
<> 147:30b64687e01f 6693 #define RTC_TSDR_DU_1 0x00000002U
<> 147:30b64687e01f 6694 #define RTC_TSDR_DU_2 0x00000004U
<> 147:30b64687e01f 6695 #define RTC_TSDR_DU_3 0x00000008U
<> 147:30b64687e01f 6696
<> 147:30b64687e01f 6697 /******************** Bits definition for RTC_TSSSR register ****************/
<> 147:30b64687e01f 6698 #define RTC_TSSSR_SS 0x0000FFFFU
<> 147:30b64687e01f 6699
<> 147:30b64687e01f 6700 /******************** Bits definition for RTC_CAL register *****************/
<> 147:30b64687e01f 6701 #define RTC_CALR_CALP 0x00008000U
<> 147:30b64687e01f 6702 #define RTC_CALR_CALW8 0x00004000U
<> 147:30b64687e01f 6703 #define RTC_CALR_CALW16 0x00002000U
<> 147:30b64687e01f 6704 #define RTC_CALR_CALM 0x000001FFU
<> 147:30b64687e01f 6705 #define RTC_CALR_CALM_0 0x00000001U
<> 147:30b64687e01f 6706 #define RTC_CALR_CALM_1 0x00000002U
<> 147:30b64687e01f 6707 #define RTC_CALR_CALM_2 0x00000004U
<> 147:30b64687e01f 6708 #define RTC_CALR_CALM_3 0x00000008U
<> 147:30b64687e01f 6709 #define RTC_CALR_CALM_4 0x00000010U
<> 147:30b64687e01f 6710 #define RTC_CALR_CALM_5 0x00000020U
<> 147:30b64687e01f 6711 #define RTC_CALR_CALM_6 0x00000040U
<> 147:30b64687e01f 6712 #define RTC_CALR_CALM_7 0x00000080U
<> 147:30b64687e01f 6713 #define RTC_CALR_CALM_8 0x00000100U
<> 147:30b64687e01f 6714
<> 147:30b64687e01f 6715 /******************** Bits definition for RTC_TAMPCR register ****************/
<> 147:30b64687e01f 6716 #define RTC_TAMPCR_TAMP3MF 0x01000000U
<> 147:30b64687e01f 6717 #define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
<> 147:30b64687e01f 6718 #define RTC_TAMPCR_TAMP3IE 0x00400000U
<> 147:30b64687e01f 6719 #define RTC_TAMPCR_TAMP2MF 0x00200000U
<> 147:30b64687e01f 6720 #define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
<> 147:30b64687e01f 6721 #define RTC_TAMPCR_TAMP2IE 0x00080000U
<> 147:30b64687e01f 6722 #define RTC_TAMPCR_TAMP1MF 0x00040000U
<> 147:30b64687e01f 6723 #define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
<> 147:30b64687e01f 6724 #define RTC_TAMPCR_TAMP1IE 0x00010000U
<> 147:30b64687e01f 6725 #define RTC_TAMPCR_TAMPPUDIS 0x00008000U
<> 147:30b64687e01f 6726 #define RTC_TAMPCR_TAMPPRCH 0x00006000U
<> 147:30b64687e01f 6727 #define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
<> 147:30b64687e01f 6728 #define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
<> 147:30b64687e01f 6729 #define RTC_TAMPCR_TAMPFLT 0x00001800U
<> 147:30b64687e01f 6730 #define RTC_TAMPCR_TAMPFLT_0 0x00000800U
<> 147:30b64687e01f 6731 #define RTC_TAMPCR_TAMPFLT_1 0x00001000U
<> 147:30b64687e01f 6732 #define RTC_TAMPCR_TAMPFREQ 0x00000700U
<> 147:30b64687e01f 6733 #define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
<> 147:30b64687e01f 6734 #define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
<> 147:30b64687e01f 6735 #define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
<> 147:30b64687e01f 6736 #define RTC_TAMPCR_TAMPTS 0x00000080U
<> 147:30b64687e01f 6737 #define RTC_TAMPCR_TAMP3TRG 0x00000040U
<> 147:30b64687e01f 6738 #define RTC_TAMPCR_TAMP3E 0x00000020U
<> 147:30b64687e01f 6739 #define RTC_TAMPCR_TAMP2TRG 0x00000010U
<> 147:30b64687e01f 6740 #define RTC_TAMPCR_TAMP2E 0x00000008U
<> 147:30b64687e01f 6741 #define RTC_TAMPCR_TAMPIE 0x00000004U
<> 147:30b64687e01f 6742 #define RTC_TAMPCR_TAMP1TRG 0x00000002U
<> 147:30b64687e01f 6743 #define RTC_TAMPCR_TAMP1E 0x00000001U
<> 147:30b64687e01f 6744
<> 147:30b64687e01f 6745
<> 147:30b64687e01f 6746 /******************** Bits definition for RTC_ALRMASSR register *************/
<> 147:30b64687e01f 6747 #define RTC_ALRMASSR_MASKSS 0x0F000000U
<> 147:30b64687e01f 6748 #define RTC_ALRMASSR_MASKSS_0 0x01000000U
<> 147:30b64687e01f 6749 #define RTC_ALRMASSR_MASKSS_1 0x02000000U
<> 147:30b64687e01f 6750 #define RTC_ALRMASSR_MASKSS_2 0x04000000U
<> 147:30b64687e01f 6751 #define RTC_ALRMASSR_MASKSS_3 0x08000000U
<> 147:30b64687e01f 6752 #define RTC_ALRMASSR_SS 0x00007FFFU
<> 147:30b64687e01f 6753
<> 147:30b64687e01f 6754 /******************** Bits definition for RTC_ALRMBSSR register *************/
<> 147:30b64687e01f 6755 #define RTC_ALRMBSSR_MASKSS 0x0F000000U
<> 147:30b64687e01f 6756 #define RTC_ALRMBSSR_MASKSS_0 0x01000000U
<> 147:30b64687e01f 6757 #define RTC_ALRMBSSR_MASKSS_1 0x02000000U
<> 147:30b64687e01f 6758 #define RTC_ALRMBSSR_MASKSS_2 0x04000000U
<> 147:30b64687e01f 6759 #define RTC_ALRMBSSR_MASKSS_3 0x08000000U
<> 147:30b64687e01f 6760 #define RTC_ALRMBSSR_SS 0x00007FFFU
<> 147:30b64687e01f 6761
<> 147:30b64687e01f 6762 /******************** Bits definition for RTC_OR register ****************/
<> 147:30b64687e01f 6763 #define RTC_OR_TSINSEL 0x00000006U
<> 147:30b64687e01f 6764 #define RTC_OR_TSINSEL_0 0x00000002U
<> 147:30b64687e01f 6765 #define RTC_OR_TSINSEL_1 0x00000004U
<> 147:30b64687e01f 6766 #define RTC_OR_ALARMTYPE 0x00000008U
<> 147:30b64687e01f 6767
<> 147:30b64687e01f 6768 /******************** Bits definition for RTC_BKP0R register ****************/
<> 147:30b64687e01f 6769 #define RTC_BKP0R 0xFFFFFFFFU
<> 147:30b64687e01f 6770
<> 147:30b64687e01f 6771 /******************** Bits definition for RTC_BKP1R register ****************/
<> 147:30b64687e01f 6772 #define RTC_BKP1R 0xFFFFFFFFU
<> 147:30b64687e01f 6773
<> 147:30b64687e01f 6774 /******************** Bits definition for RTC_BKP2R register ****************/
<> 147:30b64687e01f 6775 #define RTC_BKP2R 0xFFFFFFFFU
<> 147:30b64687e01f 6776
<> 147:30b64687e01f 6777 /******************** Bits definition for RTC_BKP3R register ****************/
<> 147:30b64687e01f 6778 #define RTC_BKP3R 0xFFFFFFFFU
<> 147:30b64687e01f 6779
<> 147:30b64687e01f 6780 /******************** Bits definition for RTC_BKP4R register ****************/
<> 147:30b64687e01f 6781 #define RTC_BKP4R 0xFFFFFFFFU
<> 147:30b64687e01f 6782
<> 147:30b64687e01f 6783 /******************** Bits definition for RTC_BKP5R register ****************/
<> 147:30b64687e01f 6784 #define RTC_BKP5R 0xFFFFFFFFU
<> 147:30b64687e01f 6785
<> 147:30b64687e01f 6786 /******************** Bits definition for RTC_BKP6R register ****************/
<> 147:30b64687e01f 6787 #define RTC_BKP6R 0xFFFFFFFFU
<> 147:30b64687e01f 6788
<> 147:30b64687e01f 6789 /******************** Bits definition for RTC_BKP7R register ****************/
<> 147:30b64687e01f 6790 #define RTC_BKP7R 0xFFFFFFFFU
<> 147:30b64687e01f 6791
<> 147:30b64687e01f 6792 /******************** Bits definition for RTC_BKP8R register ****************/
<> 147:30b64687e01f 6793 #define RTC_BKP8R 0xFFFFFFFFU
<> 147:30b64687e01f 6794
<> 147:30b64687e01f 6795 /******************** Bits definition for RTC_BKP9R register ****************/
<> 147:30b64687e01f 6796 #define RTC_BKP9R 0xFFFFFFFFU
<> 147:30b64687e01f 6797
<> 147:30b64687e01f 6798 /******************** Bits definition for RTC_BKP10R register ***************/
<> 147:30b64687e01f 6799 #define RTC_BKP10R 0xFFFFFFFFU
<> 147:30b64687e01f 6800
<> 147:30b64687e01f 6801 /******************** Bits definition for RTC_BKP11R register ***************/
<> 147:30b64687e01f 6802 #define RTC_BKP11R 0xFFFFFFFFU
<> 147:30b64687e01f 6803
<> 147:30b64687e01f 6804 /******************** Bits definition for RTC_BKP12R register ***************/
<> 147:30b64687e01f 6805 #define RTC_BKP12R 0xFFFFFFFFU
<> 147:30b64687e01f 6806
<> 147:30b64687e01f 6807 /******************** Bits definition for RTC_BKP13R register ***************/
<> 147:30b64687e01f 6808 #define RTC_BKP13R 0xFFFFFFFFU
<> 147:30b64687e01f 6809
<> 147:30b64687e01f 6810 /******************** Bits definition for RTC_BKP14R register ***************/
<> 147:30b64687e01f 6811 #define RTC_BKP14R 0xFFFFFFFFU
<> 147:30b64687e01f 6812
<> 147:30b64687e01f 6813 /******************** Bits definition for RTC_BKP15R register ***************/
<> 147:30b64687e01f 6814 #define RTC_BKP15R 0xFFFFFFFFU
<> 147:30b64687e01f 6815
<> 147:30b64687e01f 6816 /******************** Bits definition for RTC_BKP16R register ***************/
<> 147:30b64687e01f 6817 #define RTC_BKP16R 0xFFFFFFFFU
<> 147:30b64687e01f 6818
<> 147:30b64687e01f 6819 /******************** Bits definition for RTC_BKP17R register ***************/
<> 147:30b64687e01f 6820 #define RTC_BKP17R 0xFFFFFFFFU
<> 147:30b64687e01f 6821
<> 147:30b64687e01f 6822 /******************** Bits definition for RTC_BKP18R register ***************/
<> 147:30b64687e01f 6823 #define RTC_BKP18R 0xFFFFFFFFU
<> 147:30b64687e01f 6824
<> 147:30b64687e01f 6825 /******************** Bits definition for RTC_BKP19R register ***************/
<> 147:30b64687e01f 6826 #define RTC_BKP19R 0xFFFFFFFFU
<> 147:30b64687e01f 6827
<> 147:30b64687e01f 6828 /******************** Bits definition for RTC_BKP20R register ***************/
<> 147:30b64687e01f 6829 #define RTC_BKP20R 0xFFFFFFFFU
<> 147:30b64687e01f 6830
<> 147:30b64687e01f 6831 /******************** Bits definition for RTC_BKP21R register ***************/
<> 147:30b64687e01f 6832 #define RTC_BKP21R 0xFFFFFFFFU
<> 147:30b64687e01f 6833
<> 147:30b64687e01f 6834 /******************** Bits definition for RTC_BKP22R register ***************/
<> 147:30b64687e01f 6835 #define RTC_BKP22R 0xFFFFFFFFU
<> 147:30b64687e01f 6836
<> 147:30b64687e01f 6837 /******************** Bits definition for RTC_BKP23R register ***************/
<> 147:30b64687e01f 6838 #define RTC_BKP23R 0xFFFFFFFFU
<> 147:30b64687e01f 6839
<> 147:30b64687e01f 6840 /******************** Bits definition for RTC_BKP24R register ***************/
<> 147:30b64687e01f 6841 #define RTC_BKP24R 0xFFFFFFFFU
<> 147:30b64687e01f 6842
<> 147:30b64687e01f 6843 /******************** Bits definition for RTC_BKP25R register ***************/
<> 147:30b64687e01f 6844 #define RTC_BKP25R 0xFFFFFFFFU
<> 147:30b64687e01f 6845
<> 147:30b64687e01f 6846 /******************** Bits definition for RTC_BKP26R register ***************/
<> 147:30b64687e01f 6847 #define RTC_BKP26R 0xFFFFFFFFU
<> 147:30b64687e01f 6848
<> 147:30b64687e01f 6849 /******************** Bits definition for RTC_BKP27R register ***************/
<> 147:30b64687e01f 6850 #define RTC_BKP27R 0xFFFFFFFFU
<> 147:30b64687e01f 6851
<> 147:30b64687e01f 6852 /******************** Bits definition for RTC_BKP28R register ***************/
<> 147:30b64687e01f 6853 #define RTC_BKP28R 0xFFFFFFFFU
<> 147:30b64687e01f 6854
<> 147:30b64687e01f 6855 /******************** Bits definition for RTC_BKP29R register ***************/
<> 147:30b64687e01f 6856 #define RTC_BKP29R 0xFFFFFFFFU
<> 147:30b64687e01f 6857
<> 147:30b64687e01f 6858 /******************** Bits definition for RTC_BKP30R register ***************/
<> 147:30b64687e01f 6859 #define RTC_BKP30R 0xFFFFFFFFU
<> 147:30b64687e01f 6860
<> 147:30b64687e01f 6861 /******************** Bits definition for RTC_BKP31R register ***************/
<> 147:30b64687e01f 6862 #define RTC_BKP31R 0xFFFFFFFFU
<> 147:30b64687e01f 6863
<> 147:30b64687e01f 6864 /******************** Number of backup registers ******************************/
<> 147:30b64687e01f 6865 #define RTC_BKP_NUMBER 0x00000020U
<> 147:30b64687e01f 6866
<> 147:30b64687e01f 6867
<> 147:30b64687e01f 6868 /******************************************************************************/
<> 147:30b64687e01f 6869 /* */
<> 147:30b64687e01f 6870 /* Serial Audio Interface */
<> 147:30b64687e01f 6871 /* */
<> 147:30b64687e01f 6872 /******************************************************************************/
<> 147:30b64687e01f 6873 /******************** Bit definition for SAI_GCR register *******************/
<> 147:30b64687e01f 6874 #define SAI_GCR_SYNCIN 0x00000003U /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
<> 147:30b64687e01f 6875 #define SAI_GCR_SYNCIN_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 6876 #define SAI_GCR_SYNCIN_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 6877
<> 147:30b64687e01f 6878 #define SAI_GCR_SYNCOUT 0x00000030U /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
<> 147:30b64687e01f 6879 #define SAI_GCR_SYNCOUT_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 6880 #define SAI_GCR_SYNCOUT_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 6881
<> 147:30b64687e01f 6882 /******************* Bit definition for SAI_xCR1 register *******************/
<> 147:30b64687e01f 6883 #define SAI_xCR1_MODE 0x00000003U /*!<MODE[1:0] bits (Audio Block Mode) */
<> 147:30b64687e01f 6884 #define SAI_xCR1_MODE_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 6885 #define SAI_xCR1_MODE_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 6886
<> 147:30b64687e01f 6887 #define SAI_xCR1_PRTCFG 0x0000000CU /*!<PRTCFG[1:0] bits (Protocol Configuration) */
<> 147:30b64687e01f 6888 #define SAI_xCR1_PRTCFG_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 6889 #define SAI_xCR1_PRTCFG_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 6890
<> 147:30b64687e01f 6891 #define SAI_xCR1_DS 0x000000E0U /*!<DS[1:0] bits (Data Size) */
<> 147:30b64687e01f 6892 #define SAI_xCR1_DS_0 0x00000020U /*!<Bit 0 */
<> 147:30b64687e01f 6893 #define SAI_xCR1_DS_1 0x00000040U /*!<Bit 1 */
<> 147:30b64687e01f 6894 #define SAI_xCR1_DS_2 0x00000080U /*!<Bit 2 */
<> 147:30b64687e01f 6895
<> 147:30b64687e01f 6896 #define SAI_xCR1_LSBFIRST 0x00000100U /*!<LSB First Configuration */
<> 147:30b64687e01f 6897 #define SAI_xCR1_CKSTR 0x00000200U /*!<ClocK STRobing edge */
<> 147:30b64687e01f 6898
<> 147:30b64687e01f 6899 #define SAI_xCR1_SYNCEN 0x00000C00U /*!<SYNCEN[1:0](SYNChronization ENable) */
<> 147:30b64687e01f 6900 #define SAI_xCR1_SYNCEN_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 6901 #define SAI_xCR1_SYNCEN_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 6902
<> 147:30b64687e01f 6903 #define SAI_xCR1_MONO 0x00001000U /*!<Mono mode */
<> 147:30b64687e01f 6904 #define SAI_xCR1_OUTDRIV 0x00002000U /*!<Output Drive */
<> 147:30b64687e01f 6905 #define SAI_xCR1_SAIEN 0x00010000U /*!<Audio Block enable */
<> 147:30b64687e01f 6906 #define SAI_xCR1_DMAEN 0x00020000U /*!<DMA enable */
<> 147:30b64687e01f 6907 #define SAI_xCR1_NODIV 0x00080000U /*!<No Divider Configuration */
<> 147:30b64687e01f 6908
<> 147:30b64687e01f 6909 #define SAI_xCR1_MCKDIV 0x00F00000U /*!<MCKDIV[3:0] (Master ClocK Divider) */
<> 147:30b64687e01f 6910 #define SAI_xCR1_MCKDIV_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 6911 #define SAI_xCR1_MCKDIV_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 6912 #define SAI_xCR1_MCKDIV_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 6913 #define SAI_xCR1_MCKDIV_3 0x00800000U /*!<Bit 3 */
<> 147:30b64687e01f 6914
<> 147:30b64687e01f 6915 /******************* Bit definition for SAI_xCR2 register *******************/
<> 147:30b64687e01f 6916 #define SAI_xCR2_FTH 0x00000007U /*!<FTH[2:0](Fifo THreshold) */
<> 147:30b64687e01f 6917 #define SAI_xCR2_FTH_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 6918 #define SAI_xCR2_FTH_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 6919 #define SAI_xCR2_FTH_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 6920
<> 147:30b64687e01f 6921 #define SAI_xCR2_FFLUSH 0x00000008U /*!<Fifo FLUSH */
<> 147:30b64687e01f 6922 #define SAI_xCR2_TRIS 0x00000010U /*!<TRIState Management on data line */
<> 147:30b64687e01f 6923 #define SAI_xCR2_MUTE 0x00000020U /*!<Mute mode */
<> 147:30b64687e01f 6924 #define SAI_xCR2_MUTEVAL 0x00000040U /*!<Muate value */
<> 147:30b64687e01f 6925
<> 147:30b64687e01f 6926 #define SAI_xCR2_MUTECNT 0x00001F80U /*!<MUTECNT[5:0] (MUTE counter) */
<> 147:30b64687e01f 6927 #define SAI_xCR2_MUTECNT_0 0x00000080U /*!<Bit 0 */
<> 147:30b64687e01f 6928 #define SAI_xCR2_MUTECNT_1 0x00000100U /*!<Bit 1 */
<> 147:30b64687e01f 6929 #define SAI_xCR2_MUTECNT_2 0x00000200U /*!<Bit 2 */
<> 147:30b64687e01f 6930 #define SAI_xCR2_MUTECNT_3 0x00000400U /*!<Bit 3 */
<> 147:30b64687e01f 6931 #define SAI_xCR2_MUTECNT_4 0x00000800U /*!<Bit 4 */
<> 147:30b64687e01f 6932 #define SAI_xCR2_MUTECNT_5 0x00001000U /*!<Bit 5 */
<> 147:30b64687e01f 6933
<> 147:30b64687e01f 6934 #define SAI_xCR2_CPL 0x00002000U /*!< Complement Bit */
<> 147:30b64687e01f 6935
<> 147:30b64687e01f 6936 #define SAI_xCR2_COMP 0x0000C000U /*!<COMP[1:0] (Companding mode) */
<> 147:30b64687e01f 6937 #define SAI_xCR2_COMP_0 0x00004000U /*!<Bit 0 */
<> 147:30b64687e01f 6938 #define SAI_xCR2_COMP_1 0x00008000U /*!<Bit 1 */
<> 147:30b64687e01f 6939
<> 147:30b64687e01f 6940 /****************** Bit definition for SAI_xFRCR register *******************/
<> 147:30b64687e01f 6941 #define SAI_xFRCR_FRL 0x000000FFU /*!<FRL[1:0](Frame length) */
<> 147:30b64687e01f 6942 #define SAI_xFRCR_FRL_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 6943 #define SAI_xFRCR_FRL_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 6944 #define SAI_xFRCR_FRL_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 6945 #define SAI_xFRCR_FRL_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 6946 #define SAI_xFRCR_FRL_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 6947 #define SAI_xFRCR_FRL_5 0x00000020U /*!<Bit 5 */
<> 147:30b64687e01f 6948 #define SAI_xFRCR_FRL_6 0x00000040U /*!<Bit 6 */
<> 147:30b64687e01f 6949 #define SAI_xFRCR_FRL_7 0x00000080U /*!<Bit 7 */
<> 147:30b64687e01f 6950
<> 147:30b64687e01f 6951 #define SAI_xFRCR_FSALL 0x00007F00U /*!<FRL[1:0] (Frame synchronization active level length) */
<> 147:30b64687e01f 6952 #define SAI_xFRCR_FSALL_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 6953 #define SAI_xFRCR_FSALL_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 6954 #define SAI_xFRCR_FSALL_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 6955 #define SAI_xFRCR_FSALL_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 6956 #define SAI_xFRCR_FSALL_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 6957 #define SAI_xFRCR_FSALL_5 0x00002000U /*!<Bit 5 */
<> 147:30b64687e01f 6958 #define SAI_xFRCR_FSALL_6 0x00004000U /*!<Bit 6 */
<> 147:30b64687e01f 6959
<> 147:30b64687e01f 6960 #define SAI_xFRCR_FSDEF 0x00010000U /*!<Frame Synchronization Definition */
<> 147:30b64687e01f 6961 #define SAI_xFRCR_FSPOL 0x00020000U /*!<Frame Synchronization POLarity */
<> 147:30b64687e01f 6962 #define SAI_xFRCR_FSOFF 0x00040000U /*!<Frame Synchronization OFFset */
<> 147:30b64687e01f 6963
<> 147:30b64687e01f 6964 /* Legacy define */
<> 147:30b64687e01f 6965 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
<> 147:30b64687e01f 6966
<> 147:30b64687e01f 6967 /****************** Bit definition for SAI_xSLOTR register *******************/
<> 147:30b64687e01f 6968 #define SAI_xSLOTR_FBOFF 0x0000001FU /*!<FRL[4:0](First Bit Offset) */
<> 147:30b64687e01f 6969 #define SAI_xSLOTR_FBOFF_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 6970 #define SAI_xSLOTR_FBOFF_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 6971 #define SAI_xSLOTR_FBOFF_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 6972 #define SAI_xSLOTR_FBOFF_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 6973 #define SAI_xSLOTR_FBOFF_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 6974
<> 147:30b64687e01f 6975 #define SAI_xSLOTR_SLOTSZ 0x000000C0U /*!<SLOTSZ[1:0] (Slot size) */
<> 147:30b64687e01f 6976 #define SAI_xSLOTR_SLOTSZ_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 6977 #define SAI_xSLOTR_SLOTSZ_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 6978
<> 147:30b64687e01f 6979 #define SAI_xSLOTR_NBSLOT 0x00000F00U /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
<> 147:30b64687e01f 6980 #define SAI_xSLOTR_NBSLOT_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 6981 #define SAI_xSLOTR_NBSLOT_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 6982 #define SAI_xSLOTR_NBSLOT_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 6983 #define SAI_xSLOTR_NBSLOT_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 6984
<> 147:30b64687e01f 6985 #define SAI_xSLOTR_SLOTEN 0xFFFF0000U /*!<SLOTEN[15:0] (Slot Enable) */
<> 147:30b64687e01f 6986
<> 147:30b64687e01f 6987 /******************* Bit definition for SAI_xIMR register *******************/
<> 147:30b64687e01f 6988 #define SAI_xIMR_OVRUDRIE 0x00000001U /*!<Overrun underrun interrupt enable */
<> 147:30b64687e01f 6989 #define SAI_xIMR_MUTEDETIE 0x00000002U /*!<Mute detection interrupt enable */
<> 147:30b64687e01f 6990 #define SAI_xIMR_WCKCFGIE 0x00000004U /*!<Wrong Clock Configuration interrupt enable */
<> 147:30b64687e01f 6991 #define SAI_xIMR_FREQIE 0x00000008U /*!<FIFO request interrupt enable */
<> 147:30b64687e01f 6992 #define SAI_xIMR_CNRDYIE 0x00000010U /*!<Codec not ready interrupt enable */
<> 147:30b64687e01f 6993 #define SAI_xIMR_AFSDETIE 0x00000020U /*!<Anticipated frame synchronization detection interrupt enable */
<> 147:30b64687e01f 6994 #define SAI_xIMR_LFSDETIE 0x00000040U /*!<Late frame synchronization detection interrupt enable */
<> 147:30b64687e01f 6995
<> 147:30b64687e01f 6996 /******************** Bit definition for SAI_xSR register *******************/
<> 147:30b64687e01f 6997 #define SAI_xSR_OVRUDR 0x00000001U /*!<Overrun underrun */
<> 147:30b64687e01f 6998 #define SAI_xSR_MUTEDET 0x00000002U /*!<Mute detection */
<> 147:30b64687e01f 6999 #define SAI_xSR_WCKCFG 0x00000004U /*!<Wrong Clock Configuration */
<> 147:30b64687e01f 7000 #define SAI_xSR_FREQ 0x00000008U /*!<FIFO request */
<> 147:30b64687e01f 7001 #define SAI_xSR_CNRDY 0x00000010U /*!<Codec not ready */
<> 147:30b64687e01f 7002 #define SAI_xSR_AFSDET 0x00000020U /*!<Anticipated frame synchronization detection */
<> 147:30b64687e01f 7003 #define SAI_xSR_LFSDET 0x00000040U /*!<Late frame synchronization detection */
<> 147:30b64687e01f 7004
<> 147:30b64687e01f 7005 #define SAI_xSR_FLVL 0x00070000U /*!<FLVL[2:0] (FIFO Level Threshold) */
<> 147:30b64687e01f 7006 #define SAI_xSR_FLVL_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 7007 #define SAI_xSR_FLVL_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 7008 #define SAI_xSR_FLVL_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 7009
<> 147:30b64687e01f 7010 /****************** Bit definition for SAI_xCLRFR register ******************/
<> 147:30b64687e01f 7011 #define SAI_xCLRFR_COVRUDR 0x00000001U /*!<Clear Overrun underrun */
<> 147:30b64687e01f 7012 #define SAI_xCLRFR_CMUTEDET 0x00000002U /*!<Clear Mute detection */
<> 147:30b64687e01f 7013 #define SAI_xCLRFR_CWCKCFG 0x00000004U /*!<Clear Wrong Clock Configuration */
<> 147:30b64687e01f 7014 #define SAI_xCLRFR_CFREQ 0x00000008U /*!<Clear FIFO request */
<> 147:30b64687e01f 7015 #define SAI_xCLRFR_CCNRDY 0x00000010U /*!<Clear Codec not ready */
<> 147:30b64687e01f 7016 #define SAI_xCLRFR_CAFSDET 0x00000020U /*!<Clear Anticipated frame synchronization detection */
<> 147:30b64687e01f 7017 #define SAI_xCLRFR_CLFSDET 0x00000040U /*!<Clear Late frame synchronization detection */
<> 147:30b64687e01f 7018
<> 147:30b64687e01f 7019 /****************** Bit definition for SAI_xDR register *********************/
<> 147:30b64687e01f 7020 #define SAI_xDR_DATA 0xFFFFFFFFU
<> 147:30b64687e01f 7021
<> 147:30b64687e01f 7022 /******************************************************************************/
<> 147:30b64687e01f 7023 /* */
<> 147:30b64687e01f 7024 /* SPDIF-RX Interface */
<> 147:30b64687e01f 7025 /* */
<> 147:30b64687e01f 7026 /******************************************************************************/
<> 147:30b64687e01f 7027 /******************** Bit definition for SPDIF_CR register *******************/
<> 147:30b64687e01f 7028 #define SPDIFRX_CR_SPDIFEN 0x00000003U /*!<Peripheral Block Enable */
<> 147:30b64687e01f 7029 #define SPDIFRX_CR_RXDMAEN 0x00000004U /*!<Receiver DMA Enable for data flow */
<> 147:30b64687e01f 7030 #define SPDIFRX_CR_RXSTEO 0x00000008U /*!<Stereo Mode */
<> 147:30b64687e01f 7031 #define SPDIFRX_CR_DRFMT 0x00000030U /*!<RX Data format */
<> 147:30b64687e01f 7032 #define SPDIFRX_CR_PMSK 0x00000040U /*!<Mask Parity error bit */
<> 147:30b64687e01f 7033 #define SPDIFRX_CR_VMSK 0x00000080U /*!<Mask of Validity bit */
<> 147:30b64687e01f 7034 #define SPDIFRX_CR_CUMSK 0x00000100U /*!<Mask of channel status and user bits */
<> 147:30b64687e01f 7035 #define SPDIFRX_CR_PTMSK 0x00000200U /*!<Mask of Preamble Type bits */
<> 147:30b64687e01f 7036 #define SPDIFRX_CR_CBDMAEN 0x00000400U /*!<Control Buffer DMA ENable for control flow */
<> 147:30b64687e01f 7037 #define SPDIFRX_CR_CHSEL 0x00000800U /*!<Channel Selection */
<> 147:30b64687e01f 7038 #define SPDIFRX_CR_NBTR 0x00003000U /*!<Maximum allowed re-tries during synchronization phase */
<> 147:30b64687e01f 7039 #define SPDIFRX_CR_WFA 0x00004000U /*!<Wait For Activity */
<> 147:30b64687e01f 7040 #define SPDIFRX_CR_INSEL 0x00070000U /*!<SPDIF input selection */
<> 147:30b64687e01f 7041
<> 147:30b64687e01f 7042 /******************* Bit definition for SPDIFRX_IMR register *******************/
<> 147:30b64687e01f 7043 #define SPDIFRX_IMR_RXNEIE 0x00000001U /*!<RXNE interrupt enable */
<> 147:30b64687e01f 7044 #define SPDIFRX_IMR_CSRNEIE 0x00000002U /*!<Control Buffer Ready Interrupt Enable */
<> 147:30b64687e01f 7045 #define SPDIFRX_IMR_PERRIE 0x00000004U /*!<Parity error interrupt enable */
<> 147:30b64687e01f 7046 #define SPDIFRX_IMR_OVRIE 0x00000008U /*!<Overrun error Interrupt Enable */
<> 147:30b64687e01f 7047 #define SPDIFRX_IMR_SBLKIE 0x00000010U /*!<Synchronization Block Detected Interrupt Enable */
<> 147:30b64687e01f 7048 #define SPDIFRX_IMR_SYNCDIE 0x00000020U /*!<Synchronization Done */
<> 147:30b64687e01f 7049 #define SPDIFRX_IMR_IFEIE 0x00000040U /*!<Serial Interface Error Interrupt Enable */
<> 147:30b64687e01f 7050
<> 147:30b64687e01f 7051 /******************* Bit definition for SPDIFRX_SR register *******************/
<> 147:30b64687e01f 7052 #define SPDIFRX_SR_RXNE 0x00000001U /*!<Read data register not empty */
<> 147:30b64687e01f 7053 #define SPDIFRX_SR_CSRNE 0x00000002U /*!<The Control Buffer register is not empty */
<> 147:30b64687e01f 7054 #define SPDIFRX_SR_PERR 0x00000004U /*!<Parity error */
<> 147:30b64687e01f 7055 #define SPDIFRX_SR_OVR 0x00000008U /*!<Overrun error */
<> 147:30b64687e01f 7056 #define SPDIFRX_SR_SBD 0x00000010U /*!<Synchronization Block Detected */
<> 147:30b64687e01f 7057 #define SPDIFRX_SR_SYNCD 0x00000020U /*!<Synchronization Done */
<> 147:30b64687e01f 7058 #define SPDIFRX_SR_FERR 0x00000040U /*!<Framing error */
<> 147:30b64687e01f 7059 #define SPDIFRX_SR_SERR 0x00000080U /*!<Synchronization error */
<> 147:30b64687e01f 7060 #define SPDIFRX_SR_TERR 0x00000100U /*!<Time-out error */
<> 147:30b64687e01f 7061 #define SPDIFRX_SR_WIDTH5 0x7FFF0000U /*!<Duration of 5 symbols counted with spdif_clk */
<> 147:30b64687e01f 7062
<> 147:30b64687e01f 7063 /******************* Bit definition for SPDIFRX_IFCR register *******************/
<> 147:30b64687e01f 7064 #define SPDIFRX_IFCR_PERRCF 0x00000004U /*!<Clears the Parity error flag */
<> 147:30b64687e01f 7065 #define SPDIFRX_IFCR_OVRCF 0x00000008U /*!<Clears the Overrun error flag */
<> 147:30b64687e01f 7066 #define SPDIFRX_IFCR_SBDCF 0x00000010U /*!<Clears the Synchronization Block Detected flag */
<> 147:30b64687e01f 7067 #define SPDIFRX_IFCR_SYNCDCF 0x00000020U /*!<Clears the Synchronization Done flag */
<> 147:30b64687e01f 7068
<> 147:30b64687e01f 7069 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
<> 147:30b64687e01f 7070 #define SPDIFRX_DR0_DR 0x00FFFFFFU /*!<Data value */
<> 147:30b64687e01f 7071 #define SPDIFRX_DR0_PE 0x01000000U /*!<Parity Error bit */
<> 147:30b64687e01f 7072 #define SPDIFRX_DR0_V 0x02000000U /*!<Validity bit */
<> 147:30b64687e01f 7073 #define SPDIFRX_DR0_U 0x04000000U /*!<User bit */
<> 147:30b64687e01f 7074 #define SPDIFRX_DR0_C 0x08000000U /*!<Channel Status bit */
<> 147:30b64687e01f 7075 #define SPDIFRX_DR0_PT 0x30000000U /*!<Preamble Type */
<> 147:30b64687e01f 7076
<> 147:30b64687e01f 7077 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
<> 147:30b64687e01f 7078 #define SPDIFRX_DR1_DR 0xFFFFFF00U /*!<Data value */
<> 147:30b64687e01f 7079 #define SPDIFRX_DR1_PT 0x00000030U /*!<Preamble Type */
<> 147:30b64687e01f 7080 #define SPDIFRX_DR1_C 0x00000008U /*!<Channel Status bit */
<> 147:30b64687e01f 7081 #define SPDIFRX_DR1_U 0x00000004U /*!<User bit */
<> 147:30b64687e01f 7082 #define SPDIFRX_DR1_V 0x00000002U /*!<Validity bit */
<> 147:30b64687e01f 7083 #define SPDIFRX_DR1_PE 0x00000001U /*!<Parity Error bit */
<> 147:30b64687e01f 7084
<> 147:30b64687e01f 7085 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
<> 147:30b64687e01f 7086 #define SPDIFRX_DR1_DRNL1 0xFFFF0000U /*!<Data value Channel B */
<> 147:30b64687e01f 7087 #define SPDIFRX_DR1_DRNL2 0x0000FFFFU /*!<Data value Channel A */
<> 147:30b64687e01f 7088
<> 147:30b64687e01f 7089 /******************* Bit definition for SPDIFRX_CSR register *******************/
<> 147:30b64687e01f 7090 #define SPDIFRX_CSR_USR 0x0000FFFFU /*!<User data information */
<> 147:30b64687e01f 7091 #define SPDIFRX_CSR_CS 0x00FF0000U /*!<Channel A status information */
<> 147:30b64687e01f 7092 #define SPDIFRX_CSR_SOB 0x01000000U /*!<Start Of Block */
<> 147:30b64687e01f 7093
<> 147:30b64687e01f 7094 /******************* Bit definition for SPDIFRX_DIR register *******************/
<> 147:30b64687e01f 7095 #define SPDIFRX_DIR_THI 0x000013FFU /*!<Threshold LOW */
<> 147:30b64687e01f 7096 #define SPDIFRX_DIR_TLO 0x1FFF0000U /*!<Threshold HIGH */
<> 147:30b64687e01f 7097
<> 147:30b64687e01f 7098 /******************************************************************************/
<> 147:30b64687e01f 7099 /* */
<> 147:30b64687e01f 7100 /* SD host Interface */
<> 147:30b64687e01f 7101 /* */
<> 147:30b64687e01f 7102 /******************************************************************************/
<> 147:30b64687e01f 7103 /****************** Bit definition for SDMMC_POWER register ******************/
<> 147:30b64687e01f 7104 #define SDMMC_POWER_PWRCTRL 0x03U /*!<PWRCTRL[1:0] bits (Power supply control bits) */
<> 147:30b64687e01f 7105 #define SDMMC_POWER_PWRCTRL_0 0x01U /*!<Bit 0 */
<> 147:30b64687e01f 7106 #define SDMMC_POWER_PWRCTRL_1 0x02U /*!<Bit 1 */
<> 147:30b64687e01f 7107
<> 147:30b64687e01f 7108 /****************** Bit definition for SDMMC_CLKCR register ******************/
<> 147:30b64687e01f 7109 #define SDMMC_CLKCR_CLKDIV 0x00FFU /*!<Clock divide factor */
<> 147:30b64687e01f 7110 #define SDMMC_CLKCR_CLKEN 0x0100U /*!<Clock enable bit */
<> 147:30b64687e01f 7111 #define SDMMC_CLKCR_PWRSAV 0x0200U /*!<Power saving configuration bit */
<> 147:30b64687e01f 7112 #define SDMMC_CLKCR_BYPASS 0x0400U /*!<Clock divider bypass enable bit */
<> 147:30b64687e01f 7113
<> 147:30b64687e01f 7114 #define SDMMC_CLKCR_WIDBUS 0x1800U /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
<> 147:30b64687e01f 7115 #define SDMMC_CLKCR_WIDBUS_0 0x0800U /*!<Bit 0 */
<> 147:30b64687e01f 7116 #define SDMMC_CLKCR_WIDBUS_1 0x1000U /*!<Bit 1 */
<> 147:30b64687e01f 7117
<> 147:30b64687e01f 7118 #define SDMMC_CLKCR_NEGEDGE 0x2000U /*!<SDMMC_CK dephasing selection bit */
<> 147:30b64687e01f 7119 #define SDMMC_CLKCR_HWFC_EN 0x4000U /*!<HW Flow Control enable */
<> 147:30b64687e01f 7120
<> 147:30b64687e01f 7121 /******************* Bit definition for SDMMC_ARG register *******************/
<> 147:30b64687e01f 7122 #define SDMMC_ARG_CMDARG 0xFFFFFFFFU /*!<Command argument */
<> 147:30b64687e01f 7123
<> 147:30b64687e01f 7124 /******************* Bit definition for SDMMC_CMD register *******************/
<> 147:30b64687e01f 7125 #define SDMMC_CMD_CMDINDEX 0x003FU /*!<Command Index */
<> 147:30b64687e01f 7126
<> 147:30b64687e01f 7127 #define SDMMC_CMD_WAITRESP 0x00C0U /*!<WAITRESP[1:0] bits (Wait for response bits) */
<> 147:30b64687e01f 7128 #define SDMMC_CMD_WAITRESP_0 0x0040U /*!< Bit 0 */
<> 147:30b64687e01f 7129 #define SDMMC_CMD_WAITRESP_1 0x0080U /*!< Bit 1 */
<> 147:30b64687e01f 7130
<> 147:30b64687e01f 7131 #define SDMMC_CMD_WAITINT 0x0100U /*!<CPSM Waits for Interrupt Request */
<> 147:30b64687e01f 7132 #define SDMMC_CMD_WAITPEND 0x0200U /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
<> 147:30b64687e01f 7133 #define SDMMC_CMD_CPSMEN 0x0400U /*!<Command path state machine (CPSM) Enable bit */
<> 147:30b64687e01f 7134 #define SDMMC_CMD_SDIOSUSPEND 0x0800U /*!<SD I/O suspend command */
<> 147:30b64687e01f 7135
<> 147:30b64687e01f 7136 /***************** Bit definition for SDMMC_RESPCMD register *****************/
<> 147:30b64687e01f 7137 #define SDMMC_RESPCMD_RESPCMD 0x3FU /*!<Response command index */
<> 147:30b64687e01f 7138
<> 147:30b64687e01f 7139 /****************** Bit definition for SDMMC_RESP0 register ******************/
<> 147:30b64687e01f 7140 #define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /*!<Card Status */
<> 147:30b64687e01f 7141
<> 147:30b64687e01f 7142 /****************** Bit definition for SDMMC_RESP1 register ******************/
<> 147:30b64687e01f 7143 #define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /*!<Card Status */
<> 147:30b64687e01f 7144
<> 147:30b64687e01f 7145 /****************** Bit definition for SDMMC_RESP2 register ******************/
<> 147:30b64687e01f 7146 #define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /*!<Card Status */
<> 147:30b64687e01f 7147
<> 147:30b64687e01f 7148 /****************** Bit definition for SDMMC_RESP3 register ******************/
<> 147:30b64687e01f 7149 #define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /*!<Card Status */
<> 147:30b64687e01f 7150
<> 147:30b64687e01f 7151 /****************** Bit definition for SDMMC_RESP4 register ******************/
<> 147:30b64687e01f 7152 #define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /*!<Card Status */
<> 147:30b64687e01f 7153
<> 147:30b64687e01f 7154 /****************** Bit definition for SDMMC_DTIMER register *****************/
<> 147:30b64687e01f 7155 #define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /*!<Data timeout period. */
<> 147:30b64687e01f 7156
<> 147:30b64687e01f 7157 /****************** Bit definition for SDMMC_DLEN register *******************/
<> 147:30b64687e01f 7158 #define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /*!<Data length value */
<> 147:30b64687e01f 7159
<> 147:30b64687e01f 7160 /****************** Bit definition for SDMMC_DCTRL register ******************/
<> 147:30b64687e01f 7161 #define SDMMC_DCTRL_DTEN 0x0001U /*!<Data transfer enabled bit */
<> 147:30b64687e01f 7162 #define SDMMC_DCTRL_DTDIR 0x0002U /*!<Data transfer direction selection */
<> 147:30b64687e01f 7163 #define SDMMC_DCTRL_DTMODE 0x0004U /*!<Data transfer mode selection */
<> 147:30b64687e01f 7164 #define SDMMC_DCTRL_DMAEN 0x0008U /*!<DMA enabled bit */
<> 147:30b64687e01f 7165
<> 147:30b64687e01f 7166 #define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /*!<DBLOCKSIZE[3:0] bits (Data block size) */
<> 147:30b64687e01f 7167 #define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /*!<Bit 0 */
<> 147:30b64687e01f 7168 #define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /*!<Bit 1 */
<> 147:30b64687e01f 7169 #define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /*!<Bit 2 */
<> 147:30b64687e01f 7170 #define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /*!<Bit 3 */
<> 147:30b64687e01f 7171
<> 147:30b64687e01f 7172 #define SDMMC_DCTRL_RWSTART 0x0100U /*!<Read wait start */
<> 147:30b64687e01f 7173 #define SDMMC_DCTRL_RWSTOP 0x0200U /*!<Read wait stop */
<> 147:30b64687e01f 7174 #define SDMMC_DCTRL_RWMOD 0x0400U /*!<Read wait mode */
<> 147:30b64687e01f 7175 #define SDMMC_DCTRL_SDIOEN 0x0800U /*!<SD I/O enable functions */
<> 147:30b64687e01f 7176
<> 147:30b64687e01f 7177 /****************** Bit definition for SDMMC_DCOUNT register *****************/
<> 147:30b64687e01f 7178 #define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /*!<Data count value */
<> 147:30b64687e01f 7179
<> 147:30b64687e01f 7180 /****************** Bit definition for SDMMC_STA registe ********************/
<> 147:30b64687e01f 7181 #define SDMMC_STA_CCRCFAIL 0x00000001U /*!<Command response received (CRC check failed) */
<> 147:30b64687e01f 7182 #define SDMMC_STA_DCRCFAIL 0x00000002U /*!<Data block sent/received (CRC check failed) */
<> 147:30b64687e01f 7183 #define SDMMC_STA_CTIMEOUT 0x00000004U /*!<Command response timeout */
<> 147:30b64687e01f 7184 #define SDMMC_STA_DTIMEOUT 0x00000008U /*!<Data timeout */
<> 147:30b64687e01f 7185 #define SDMMC_STA_TXUNDERR 0x00000010U /*!<Transmit FIFO underrun error */
<> 147:30b64687e01f 7186 #define SDMMC_STA_RXOVERR 0x00000020U /*!<Received FIFO overrun error */
<> 147:30b64687e01f 7187 #define SDMMC_STA_CMDREND 0x00000040U /*!<Command response received (CRC check passed) */
<> 147:30b64687e01f 7188 #define SDMMC_STA_CMDSENT 0x00000080U /*!<Command sent (no response required) */
<> 147:30b64687e01f 7189 #define SDMMC_STA_DATAEND 0x00000100U /*!<Data end (data counter, SDIDCOUNT, is zero) */
<> 147:30b64687e01f 7190 #define SDMMC_STA_DBCKEND 0x00000400U /*!<Data block sent/received (CRC check passed) */
<> 147:30b64687e01f 7191 #define SDMMC_STA_CMDACT 0x00000800U /*!<Command transfer in progress */
<> 147:30b64687e01f 7192 #define SDMMC_STA_TXACT 0x00001000U /*!<Data transmit in progress */
<> 147:30b64687e01f 7193 #define SDMMC_STA_RXACT 0x00002000U /*!<Data receive in progress */
<> 147:30b64687e01f 7194 #define SDMMC_STA_TXFIFOHE 0x00004000U /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
<> 147:30b64687e01f 7195 #define SDMMC_STA_RXFIFOHF 0x00008000U /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
<> 147:30b64687e01f 7196 #define SDMMC_STA_TXFIFOF 0x00010000U /*!<Transmit FIFO full */
<> 147:30b64687e01f 7197 #define SDMMC_STA_RXFIFOF 0x00020000U /*!<Receive FIFO full */
<> 147:30b64687e01f 7198 #define SDMMC_STA_TXFIFOE 0x00040000U /*!<Transmit FIFO empty */
<> 147:30b64687e01f 7199 #define SDMMC_STA_RXFIFOE 0x00080000U /*!<Receive FIFO empty */
<> 147:30b64687e01f 7200 #define SDMMC_STA_TXDAVL 0x00100000U /*!<Data available in transmit FIFO */
<> 147:30b64687e01f 7201 #define SDMMC_STA_RXDAVL 0x00200000U /*!<Data available in receive FIFO */
<> 147:30b64687e01f 7202 #define SDMMC_STA_SDIOIT 0x00400000U /*!<SDMMC interrupt received */
<> 147:30b64687e01f 7203
<> 147:30b64687e01f 7204 /******************* Bit definition for SDMMC_ICR register *******************/
<> 147:30b64687e01f 7205 #define SDMMC_ICR_CCRCFAILC 0x00000001U /*!<CCRCFAIL flag clear bit */
<> 147:30b64687e01f 7206 #define SDMMC_ICR_DCRCFAILC 0x00000002U /*!<DCRCFAIL flag clear bit */
<> 147:30b64687e01f 7207 #define SDMMC_ICR_CTIMEOUTC 0x00000004U /*!<CTIMEOUT flag clear bit */
<> 147:30b64687e01f 7208 #define SDMMC_ICR_DTIMEOUTC 0x00000008U /*!<DTIMEOUT flag clear bit */
<> 147:30b64687e01f 7209 #define SDMMC_ICR_TXUNDERRC 0x00000010U /*!<TXUNDERR flag clear bit */
<> 147:30b64687e01f 7210 #define SDMMC_ICR_RXOVERRC 0x00000020U /*!<RXOVERR flag clear bit */
<> 147:30b64687e01f 7211 #define SDMMC_ICR_CMDRENDC 0x00000040U /*!<CMDREND flag clear bit */
<> 147:30b64687e01f 7212 #define SDMMC_ICR_CMDSENTC 0x00000080U /*!<CMDSENT flag clear bit */
<> 147:30b64687e01f 7213 #define SDMMC_ICR_DATAENDC 0x00000100U /*!<DATAEND flag clear bit */
<> 147:30b64687e01f 7214 #define SDMMC_ICR_DBCKENDC 0x00000400U /*!<DBCKEND flag clear bit */
<> 147:30b64687e01f 7215 #define SDMMC_ICR_SDIOITC 0x00400000U /*!<SDMMCIT flag clear bit */
<> 147:30b64687e01f 7216
<> 147:30b64687e01f 7217 /****************** Bit definition for SDMMC_MASK register *******************/
<> 147:30b64687e01f 7218 #define SDMMC_MASK_CCRCFAILIE 0x00000001U /*!<Command CRC Fail Interrupt Enable */
<> 147:30b64687e01f 7219 #define SDMMC_MASK_DCRCFAILIE 0x00000002U /*!<Data CRC Fail Interrupt Enable */
<> 147:30b64687e01f 7220 #define SDMMC_MASK_CTIMEOUTIE 0x00000004U /*!<Command TimeOut Interrupt Enable */
<> 147:30b64687e01f 7221 #define SDMMC_MASK_DTIMEOUTIE 0x00000008U /*!<Data TimeOut Interrupt Enable */
<> 147:30b64687e01f 7222 #define SDMMC_MASK_TXUNDERRIE 0x00000010U /*!<Tx FIFO UnderRun Error Interrupt Enable */
<> 147:30b64687e01f 7223 #define SDMMC_MASK_RXOVERRIE 0x00000020U /*!<Rx FIFO OverRun Error Interrupt Enable */
<> 147:30b64687e01f 7224 #define SDMMC_MASK_CMDRENDIE 0x00000040U /*!<Command Response Received Interrupt Enable */
<> 147:30b64687e01f 7225 #define SDMMC_MASK_CMDSENTIE 0x00000080U /*!<Command Sent Interrupt Enable */
<> 147:30b64687e01f 7226 #define SDMMC_MASK_DATAENDIE 0x00000100U /*!<Data End Interrupt Enable */
<> 147:30b64687e01f 7227 #define SDMMC_MASK_DBCKENDIE 0x00000400U /*!<Data Block End Interrupt Enable */
<> 147:30b64687e01f 7228 #define SDMMC_MASK_CMDACTIE 0x00000800U /*!<CCommand Acting Interrupt Enable */
<> 147:30b64687e01f 7229 #define SDMMC_MASK_TXACTIE 0x00001000U /*!<Data Transmit Acting Interrupt Enable */
<> 147:30b64687e01f 7230 #define SDMMC_MASK_RXACTIE 0x00002000U /*!<Data receive acting interrupt enabled */
<> 147:30b64687e01f 7231 #define SDMMC_MASK_TXFIFOHEIE 0x00004000U /*!<Tx FIFO Half Empty interrupt Enable */
<> 147:30b64687e01f 7232 #define SDMMC_MASK_RXFIFOHFIE 0x00008000U /*!<Rx FIFO Half Full interrupt Enable */
<> 147:30b64687e01f 7233 #define SDMMC_MASK_TXFIFOFIE 0x00010000U /*!<Tx FIFO Full interrupt Enable */
<> 147:30b64687e01f 7234 #define SDMMC_MASK_RXFIFOFIE 0x00020000U /*!<Rx FIFO Full interrupt Enable */
<> 147:30b64687e01f 7235 #define SDMMC_MASK_TXFIFOEIE 0x00040000U /*!<Tx FIFO Empty interrupt Enable */
<> 147:30b64687e01f 7236 #define SDMMC_MASK_RXFIFOEIE 0x00080000U /*!<Rx FIFO Empty interrupt Enable */
<> 147:30b64687e01f 7237 #define SDMMC_MASK_TXDAVLIE 0x00100000U /*!<Data available in Tx FIFO interrupt Enable */
<> 147:30b64687e01f 7238 #define SDMMC_MASK_RXDAVLIE 0x00200000U /*!<Data available in Rx FIFO interrupt Enable */
<> 147:30b64687e01f 7239 #define SDMMC_MASK_SDIOITIE 0x00400000U /*!<SDMMC Mode Interrupt Received interrupt Enable */
<> 147:30b64687e01f 7240
<> 147:30b64687e01f 7241 /***************** Bit definition for SDMMC_FIFOCNT register *****************/
<> 147:30b64687e01f 7242 #define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /*!<Remaining number of words to be written to or read from the FIFO */
<> 147:30b64687e01f 7243
<> 147:30b64687e01f 7244 /****************** Bit definition for SDMMC_FIFO register *******************/
<> 147:30b64687e01f 7245 #define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /*!<Receive and transmit FIFO data */
<> 147:30b64687e01f 7246
<> 147:30b64687e01f 7247 /******************************************************************************/
<> 147:30b64687e01f 7248 /* */
<> 147:30b64687e01f 7249 /* Serial Peripheral Interface (SPI) */
<> 147:30b64687e01f 7250 /* */
<> 147:30b64687e01f 7251 /******************************************************************************/
<> 147:30b64687e01f 7252 /******************* Bit definition for SPI_CR1 register ********************/
<> 147:30b64687e01f 7253 #define SPI_CR1_CPHA 0x00000001U /*!< Clock Phase */
<> 147:30b64687e01f 7254 #define SPI_CR1_CPOL 0x00000002U /*!< Clock Polarity */
<> 147:30b64687e01f 7255 #define SPI_CR1_MSTR 0x00000004U /*!< Master Selection */
<> 147:30b64687e01f 7256 #define SPI_CR1_BR 0x00000038U /*!< BR[2:0] bits (Baud Rate Control) */
<> 147:30b64687e01f 7257 #define SPI_CR1_BR_0 0x00000008U /*!< Bit 0 */
<> 147:30b64687e01f 7258 #define SPI_CR1_BR_1 0x00000010U /*!< Bit 1 */
<> 147:30b64687e01f 7259 #define SPI_CR1_BR_2 0x00000020U /*!< Bit 2 */
<> 147:30b64687e01f 7260 #define SPI_CR1_SPE 0x00000040U /*!< SPI Enable */
<> 147:30b64687e01f 7261 #define SPI_CR1_LSBFIRST 0x00000080U /*!< Frame Format */
<> 147:30b64687e01f 7262 #define SPI_CR1_SSI 0x00000100U /*!< Internal slave select */
<> 147:30b64687e01f 7263 #define SPI_CR1_SSM 0x00000200U /*!< Software slave management */
<> 147:30b64687e01f 7264 #define SPI_CR1_RXONLY 0x00000400U /*!< Receive only */
<> 147:30b64687e01f 7265 #define SPI_CR1_CRCL 0x00000800U /*!< CRC Length */
<> 147:30b64687e01f 7266 #define SPI_CR1_CRCNEXT 0x00001000U /*!< Transmit CRC next */
<> 147:30b64687e01f 7267 #define SPI_CR1_CRCEN 0x00002000U /*!< Hardware CRC calculation enable */
<> 147:30b64687e01f 7268 #define SPI_CR1_BIDIOE 0x00004000U /*!< Output enable in bidirectional mode */
<> 147:30b64687e01f 7269 #define SPI_CR1_BIDIMODE 0x00008000U /*!< Bidirectional data mode enable */
<> 147:30b64687e01f 7270
<> 147:30b64687e01f 7271 /******************* Bit definition for SPI_CR2 register ********************/
<> 147:30b64687e01f 7272 #define SPI_CR2_RXDMAEN 0x00000001U /*!< Rx Buffer DMA Enable */
<> 147:30b64687e01f 7273 #define SPI_CR2_TXDMAEN 0x00000002U /*!< Tx Buffer DMA Enable */
<> 147:30b64687e01f 7274 #define SPI_CR2_SSOE 0x00000004U /*!< SS Output Enable */
<> 147:30b64687e01f 7275 #define SPI_CR2_NSSP 0x00000008U /*!< NSS pulse management Enable */
<> 147:30b64687e01f 7276 #define SPI_CR2_FRF 0x00000010U /*!< Frame Format Enable */
<> 147:30b64687e01f 7277 #define SPI_CR2_ERRIE 0x00000020U /*!< Error Interrupt Enable */
<> 147:30b64687e01f 7278 #define SPI_CR2_RXNEIE 0x00000040U /*!< RX buffer Not Empty Interrupt Enable */
<> 147:30b64687e01f 7279 #define SPI_CR2_TXEIE 0x00000080U /*!< Tx buffer Empty Interrupt Enable */
<> 147:30b64687e01f 7280 #define SPI_CR2_DS 0x00000F00U /*!< DS[3:0] Data Size */
<> 147:30b64687e01f 7281 #define SPI_CR2_DS_0 0x00000100U /*!< Bit 0 */
<> 147:30b64687e01f 7282 #define SPI_CR2_DS_1 0x00000200U /*!< Bit 1 */
<> 147:30b64687e01f 7283 #define SPI_CR2_DS_2 0x00000400U /*!< Bit 2 */
<> 147:30b64687e01f 7284 #define SPI_CR2_DS_3 0x00000800U /*!< Bit 3 */
<> 147:30b64687e01f 7285 #define SPI_CR2_FRXTH 0x00001000U /*!< FIFO reception Threshold */
<> 147:30b64687e01f 7286 #define SPI_CR2_LDMARX 0x00002000U /*!< Last DMA transfer for reception */
<> 147:30b64687e01f 7287 #define SPI_CR2_LDMATX 0x00004000U /*!< Last DMA transfer for transmission */
<> 147:30b64687e01f 7288
<> 147:30b64687e01f 7289 /******************** Bit definition for SPI_SR register ********************/
<> 147:30b64687e01f 7290 #define SPI_SR_RXNE 0x00000001U /*!< Receive buffer Not Empty */
<> 147:30b64687e01f 7291 #define SPI_SR_TXE 0x00000002U /*!< Transmit buffer Empty */
<> 147:30b64687e01f 7292 #define SPI_SR_CHSIDE 0x00000004U /*!< Channel side */
<> 147:30b64687e01f 7293 #define SPI_SR_UDR 0x00000008U /*!< Underrun flag */
<> 147:30b64687e01f 7294 #define SPI_SR_CRCERR 0x00000010U /*!< CRC Error flag */
<> 147:30b64687e01f 7295 #define SPI_SR_MODF 0x00000020U /*!< Mode fault */
<> 147:30b64687e01f 7296 #define SPI_SR_OVR 0x00000040U /*!< Overrun flag */
<> 147:30b64687e01f 7297 #define SPI_SR_BSY 0x00000080U /*!< Busy flag */
<> 147:30b64687e01f 7298 #define SPI_SR_FRE 0x00000100U /*!< TI frame format error */
<> 147:30b64687e01f 7299 #define SPI_SR_FRLVL 0x00000600U /*!< FIFO Reception Level */
<> 147:30b64687e01f 7300 #define SPI_SR_FRLVL_0 0x00000200U /*!< Bit 0 */
<> 147:30b64687e01f 7301 #define SPI_SR_FRLVL_1 0x00000400U /*!< Bit 1 */
<> 147:30b64687e01f 7302 #define SPI_SR_FTLVL 0x00001800U /*!< FIFO Transmission Level */
<> 147:30b64687e01f 7303 #define SPI_SR_FTLVL_0 0x00000800U /*!< Bit 0 */
<> 147:30b64687e01f 7304 #define SPI_SR_FTLVL_1 0x00001000U /*!< Bit 1 */
<> 147:30b64687e01f 7305
<> 147:30b64687e01f 7306 /******************** Bit definition for SPI_DR register ********************/
<> 147:30b64687e01f 7307 #define SPI_DR_DR 0xFFFFU /*!< Data Register */
<> 147:30b64687e01f 7308
<> 147:30b64687e01f 7309 /******************* Bit definition for SPI_CRCPR register ******************/
<> 147:30b64687e01f 7310 #define SPI_CRCPR_CRCPOLY 0xFFFFU /*!< CRC polynomial register */
<> 147:30b64687e01f 7311
<> 147:30b64687e01f 7312 /****************** Bit definition for SPI_RXCRCR register ******************/
<> 147:30b64687e01f 7313 #define SPI_RXCRCR_RXCRC 0xFFFFU /*!< Rx CRC Register */
<> 147:30b64687e01f 7314
<> 147:30b64687e01f 7315 /****************** Bit definition for SPI_TXCRCR register ******************/
<> 147:30b64687e01f 7316 #define SPI_TXCRCR_TXCRC 0xFFFFU /*!< Tx CRC Register */
<> 147:30b64687e01f 7317
<> 147:30b64687e01f 7318 /****************** Bit definition for SPI_I2SCFGR register *****************/
<> 147:30b64687e01f 7319 #define SPI_I2SCFGR_CHLEN 0x00000001U /*!<Channel length (number of bits per audio channel) */
<> 147:30b64687e01f 7320 #define SPI_I2SCFGR_DATLEN 0x00000006U /*!<DATLEN[1:0] bits (Data length to be transferred) */
<> 147:30b64687e01f 7321 #define SPI_I2SCFGR_DATLEN_0 0x00000002U /*!<Bit 0 */
<> 147:30b64687e01f 7322 #define SPI_I2SCFGR_DATLEN_1 0x00000004U /*!<Bit 1 */
<> 147:30b64687e01f 7323 #define SPI_I2SCFGR_CKPOL 0x00000008U /*!<steady state clock polarity */
<> 147:30b64687e01f 7324 #define SPI_I2SCFGR_I2SSTD 0x00000030U /*!<I2SSTD[1:0] bits (I2S standard selection) */
<> 147:30b64687e01f 7325 #define SPI_I2SCFGR_I2SSTD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 7326 #define SPI_I2SCFGR_I2SSTD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 7327 #define SPI_I2SCFGR_PCMSYNC 0x00000080U /*!<PCM frame synchronization */
<> 147:30b64687e01f 7328 #define SPI_I2SCFGR_I2SCFG 0x00000300U /*!<I2SCFG[1:0] bits (I2S configuration mode) */
<> 147:30b64687e01f 7329 #define SPI_I2SCFGR_I2SCFG_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 7330 #define SPI_I2SCFGR_I2SCFG_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 7331 #define SPI_I2SCFGR_I2SE 0x00000400U /*!<I2S Enable */
<> 147:30b64687e01f 7332 #define SPI_I2SCFGR_I2SMOD 0x00000800U /*!<I2S mode selection */
<> 147:30b64687e01f 7333 #define SPI_I2SCFGR_ASTRTEN 0x00001000U /*!<Asynchronous start enable */
<> 147:30b64687e01f 7334
<> 147:30b64687e01f 7335 /****************** Bit definition for SPI_I2SPR register *******************/
<> 147:30b64687e01f 7336 #define SPI_I2SPR_I2SDIV 0x00FFU /*!<I2S Linear prescaler */
<> 147:30b64687e01f 7337 #define SPI_I2SPR_ODD 0x0100U /*!<Odd factor for the prescaler */
<> 147:30b64687e01f 7338 #define SPI_I2SPR_MCKOE 0x0200U /*!<Master Clock Output Enable */
<> 147:30b64687e01f 7339
<> 147:30b64687e01f 7340
<> 147:30b64687e01f 7341 /******************************************************************************/
<> 147:30b64687e01f 7342 /* */
<> 147:30b64687e01f 7343 /* SYSCFG */
<> 147:30b64687e01f 7344 /* */
<> 147:30b64687e01f 7345 /******************************************************************************/
<> 147:30b64687e01f 7346 /****************** Bit definition for SYSCFG_MEMRMP register ***************/
<> 147:30b64687e01f 7347 #define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /*!< Boot information after Reset */
<> 147:30b64687e01f 7348
<> 147:30b64687e01f 7349 #define SYSCFG_MEMRMP_SWP_FB 0x00000100U /*!< User Flash Bank swap */
<> 147:30b64687e01f 7350
<> 147:30b64687e01f 7351 #define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /*!< FMC Memory Mapping swapping */
<> 147:30b64687e01f 7352 #define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
<> 147:30b64687e01f 7353 #define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
<> 147:30b64687e01f 7354
<> 147:30b64687e01f 7355 /****************** Bit definition for SYSCFG_PMC register ******************/
<> 147:30b64687e01f 7356 #define SYSCFG_PMC_I2C1_FMP 0x00000001U /*!< I2C1_FMP I2C1 Fast Mode + Enable */
<> 147:30b64687e01f 7357 #define SYSCFG_PMC_I2C2_FMP 0x00000002U /*!< I2C2_FMP I2C2 Fast Mode + Enable */
<> 147:30b64687e01f 7358 #define SYSCFG_PMC_I2C3_FMP 0x00000004U /*!< I2C3_FMP I2C3 Fast Mode + Enable */
<> 147:30b64687e01f 7359 #define SYSCFG_PMC_I2C4_FMP 0x00000008U /*!< I2C4_FMP I2C4 Fast Mode + Enable */
<> 147:30b64687e01f 7360 #define SYSCFG_PMC_I2C_PB6_FMP 0x00000010U /*!< PB6_FMP Fast Mode + Enable */
<> 147:30b64687e01f 7361 #define SYSCFG_PMC_I2C_PB7_FMP 0x00000020U /*!< PB7_FMP Fast Mode + Enable */
<> 147:30b64687e01f 7362 #define SYSCFG_PMC_I2C_PB8_FMP 0x00000040U /*!< PB8_FMP Fast Mode + Enable */
<> 147:30b64687e01f 7363 #define SYSCFG_PMC_I2C_PB9_FMP 0x00000080U /*!< PB9_FMP Fast Mode + Enable */
<> 147:30b64687e01f 7364
<> 147:30b64687e01f 7365 #define SYSCFG_PMC_ADCxDC2 0x00070000U /*!< Refer to AN4073 on how to use this bit */
<> 147:30b64687e01f 7366 #define SYSCFG_PMC_ADC1DC2 0x00010000U /*!< Refer to AN4073 on how to use this bit */
<> 147:30b64687e01f 7367 #define SYSCFG_PMC_ADC2DC2 0x00020000U /*!< Refer to AN4073 on how to use this bit */
<> 147:30b64687e01f 7368 #define SYSCFG_PMC_ADC3DC2 0x00040000U /*!< Refer to AN4073 on how to use this bit */
<> 147:30b64687e01f 7369
<> 147:30b64687e01f 7370 #define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /*!<Ethernet PHY interface selection */
<> 147:30b64687e01f 7371
<> 147:30b64687e01f 7372 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
<> 147:30b64687e01f 7373 #define SYSCFG_EXTICR1_EXTI0 0x000FU /*!<EXTI 0 configuration */
<> 147:30b64687e01f 7374 #define SYSCFG_EXTICR1_EXTI1 0x00F0U /*!<EXTI 1 configuration */
<> 147:30b64687e01f 7375 #define SYSCFG_EXTICR1_EXTI2 0x0F00U /*!<EXTI 2 configuration */
<> 147:30b64687e01f 7376 #define SYSCFG_EXTICR1_EXTI3 0xF000U /*!<EXTI 3 configuration */
<> 147:30b64687e01f 7377 /**
<> 147:30b64687e01f 7378 * @brief EXTI0 configuration
<> 147:30b64687e01f 7379 */
<> 147:30b64687e01f 7380 #define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */
<> 147:30b64687e01f 7381 #define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */
<> 147:30b64687e01f 7382 #define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */
<> 147:30b64687e01f 7383 #define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */
<> 147:30b64687e01f 7384 #define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */
<> 147:30b64687e01f 7385 #define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */
<> 147:30b64687e01f 7386 #define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */
<> 147:30b64687e01f 7387 #define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */
<> 147:30b64687e01f 7388 #define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */
<> 147:30b64687e01f 7389 #define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */
<> 147:30b64687e01f 7390 #define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */
<> 147:30b64687e01f 7391
<> 147:30b64687e01f 7392 /**
<> 147:30b64687e01f 7393 * @brief EXTI1 configuration
<> 147:30b64687e01f 7394 */
<> 147:30b64687e01f 7395 #define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */
<> 147:30b64687e01f 7396 #define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */
<> 147:30b64687e01f 7397 #define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */
<> 147:30b64687e01f 7398 #define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */
<> 147:30b64687e01f 7399 #define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */
<> 147:30b64687e01f 7400 #define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */
<> 147:30b64687e01f 7401 #define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */
<> 147:30b64687e01f 7402 #define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */
<> 147:30b64687e01f 7403 #define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */
<> 147:30b64687e01f 7404 #define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */
<> 147:30b64687e01f 7405 #define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */
<> 147:30b64687e01f 7406
<> 147:30b64687e01f 7407 /**
<> 147:30b64687e01f 7408 * @brief EXTI2 configuration
<> 147:30b64687e01f 7409 */
<> 147:30b64687e01f 7410 #define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */
<> 147:30b64687e01f 7411 #define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */
<> 147:30b64687e01f 7412 #define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */
<> 147:30b64687e01f 7413 #define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */
<> 147:30b64687e01f 7414 #define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */
<> 147:30b64687e01f 7415 #define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */
<> 147:30b64687e01f 7416 #define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */
<> 147:30b64687e01f 7417 #define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */
<> 147:30b64687e01f 7418 #define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */
<> 147:30b64687e01f 7419 #define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */
<> 147:30b64687e01f 7420 #define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */
<> 147:30b64687e01f 7421
<> 147:30b64687e01f 7422 /**
<> 147:30b64687e01f 7423 * @brief EXTI3 configuration
<> 147:30b64687e01f 7424 */
<> 147:30b64687e01f 7425 #define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */
<> 147:30b64687e01f 7426 #define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */
<> 147:30b64687e01f 7427 #define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */
<> 147:30b64687e01f 7428 #define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */
<> 147:30b64687e01f 7429 #define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */
<> 147:30b64687e01f 7430 #define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */
<> 147:30b64687e01f 7431 #define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */
<> 147:30b64687e01f 7432 #define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */
<> 147:30b64687e01f 7433 #define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */
<> 147:30b64687e01f 7434 #define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */
<> 147:30b64687e01f 7435 #define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */
<> 147:30b64687e01f 7436
<> 147:30b64687e01f 7437 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
<> 147:30b64687e01f 7438 #define SYSCFG_EXTICR2_EXTI4 0x000FU /*!<EXTI 4 configuration */
<> 147:30b64687e01f 7439 #define SYSCFG_EXTICR2_EXTI5 0x00F0U /*!<EXTI 5 configuration */
<> 147:30b64687e01f 7440 #define SYSCFG_EXTICR2_EXTI6 0x0F00U /*!<EXTI 6 configuration */
<> 147:30b64687e01f 7441 #define SYSCFG_EXTICR2_EXTI7 0xF000U /*!<EXTI 7 configuration */
<> 147:30b64687e01f 7442 /**
<> 147:30b64687e01f 7443 * @brief EXTI4 configuration
<> 147:30b64687e01f 7444 */
<> 147:30b64687e01f 7445 #define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */
<> 147:30b64687e01f 7446 #define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */
<> 147:30b64687e01f 7447 #define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */
<> 147:30b64687e01f 7448 #define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */
<> 147:30b64687e01f 7449 #define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */
<> 147:30b64687e01f 7450 #define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */
<> 147:30b64687e01f 7451 #define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */
<> 147:30b64687e01f 7452 #define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */
<> 147:30b64687e01f 7453 #define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */
<> 147:30b64687e01f 7454 #define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */
<> 147:30b64687e01f 7455 #define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */
<> 147:30b64687e01f 7456
<> 147:30b64687e01f 7457 /**
<> 147:30b64687e01f 7458 * @brief EXTI5 configuration
<> 147:30b64687e01f 7459 */
<> 147:30b64687e01f 7460 #define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */
<> 147:30b64687e01f 7461 #define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */
<> 147:30b64687e01f 7462 #define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */
<> 147:30b64687e01f 7463 #define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */
<> 147:30b64687e01f 7464 #define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */
<> 147:30b64687e01f 7465 #define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */
<> 147:30b64687e01f 7466 #define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */
<> 147:30b64687e01f 7467 #define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */
<> 147:30b64687e01f 7468 #define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */
<> 147:30b64687e01f 7469 #define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */
<> 147:30b64687e01f 7470 #define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */
<> 147:30b64687e01f 7471
<> 147:30b64687e01f 7472 /**
<> 147:30b64687e01f 7473 * @brief EXTI6 configuration
<> 147:30b64687e01f 7474 */
<> 147:30b64687e01f 7475 #define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */
<> 147:30b64687e01f 7476 #define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */
<> 147:30b64687e01f 7477 #define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */
<> 147:30b64687e01f 7478 #define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */
<> 147:30b64687e01f 7479 #define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */
<> 147:30b64687e01f 7480 #define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */
<> 147:30b64687e01f 7481 #define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */
<> 147:30b64687e01f 7482 #define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */
<> 147:30b64687e01f 7483 #define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */
<> 147:30b64687e01f 7484 #define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */
<> 147:30b64687e01f 7485 #define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */
<> 147:30b64687e01f 7486
<> 147:30b64687e01f 7487 /**
<> 147:30b64687e01f 7488 * @brief EXTI7 configuration
<> 147:30b64687e01f 7489 */
<> 147:30b64687e01f 7490 #define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */
<> 147:30b64687e01f 7491 #define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */
<> 147:30b64687e01f 7492 #define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */
<> 147:30b64687e01f 7493 #define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */
<> 147:30b64687e01f 7494 #define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */
<> 147:30b64687e01f 7495 #define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */
<> 147:30b64687e01f 7496 #define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */
<> 147:30b64687e01f 7497 #define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */
<> 147:30b64687e01f 7498 #define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */
<> 147:30b64687e01f 7499 #define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */
<> 147:30b64687e01f 7500 #define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */
<> 147:30b64687e01f 7501
<> 147:30b64687e01f 7502 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
<> 147:30b64687e01f 7503 #define SYSCFG_EXTICR3_EXTI8 0x000FU /*!<EXTI 8 configuration */
<> 147:30b64687e01f 7504 #define SYSCFG_EXTICR3_EXTI9 0x00F0U /*!<EXTI 9 configuration */
<> 147:30b64687e01f 7505 #define SYSCFG_EXTICR3_EXTI10 0x0F00U /*!<EXTI 10 configuration */
<> 147:30b64687e01f 7506 #define SYSCFG_EXTICR3_EXTI11 0xF000U /*!<EXTI 11 configuration */
<> 147:30b64687e01f 7507
<> 147:30b64687e01f 7508 /**
<> 147:30b64687e01f 7509 * @brief EXTI8 configuration
<> 147:30b64687e01f 7510 */
<> 147:30b64687e01f 7511 #define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */
<> 147:30b64687e01f 7512 #define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */
<> 147:30b64687e01f 7513 #define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */
<> 147:30b64687e01f 7514 #define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */
<> 147:30b64687e01f 7515 #define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */
<> 147:30b64687e01f 7516 #define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */
<> 147:30b64687e01f 7517 #define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */
<> 147:30b64687e01f 7518 #define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */
<> 147:30b64687e01f 7519 #define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */
<> 147:30b64687e01f 7520 #define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */
<> 147:30b64687e01f 7521
<> 147:30b64687e01f 7522 /**
<> 147:30b64687e01f 7523 * @brief EXTI9 configuration
<> 147:30b64687e01f 7524 */
<> 147:30b64687e01f 7525 #define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */
<> 147:30b64687e01f 7526 #define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */
<> 147:30b64687e01f 7527 #define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */
<> 147:30b64687e01f 7528 #define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */
<> 147:30b64687e01f 7529 #define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */
<> 147:30b64687e01f 7530 #define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */
<> 147:30b64687e01f 7531 #define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */
<> 147:30b64687e01f 7532 #define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */
<> 147:30b64687e01f 7533 #define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */
<> 147:30b64687e01f 7534 #define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */
<> 147:30b64687e01f 7535
<> 147:30b64687e01f 7536 /**
<> 147:30b64687e01f 7537 * @brief EXTI10 configuration
<> 147:30b64687e01f 7538 */
<> 147:30b64687e01f 7539 #define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */
<> 147:30b64687e01f 7540 #define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */
<> 147:30b64687e01f 7541 #define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */
<> 147:30b64687e01f 7542 #define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */
<> 147:30b64687e01f 7543 #define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */
<> 147:30b64687e01f 7544 #define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */
<> 147:30b64687e01f 7545 #define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */
<> 147:30b64687e01f 7546 #define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */
<> 147:30b64687e01f 7547 #define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */
<> 147:30b64687e01f 7548 #define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */
<> 147:30b64687e01f 7549
<> 147:30b64687e01f 7550 /**
<> 147:30b64687e01f 7551 * @brief EXTI11 configuration
<> 147:30b64687e01f 7552 */
<> 147:30b64687e01f 7553 #define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */
<> 147:30b64687e01f 7554 #define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */
<> 147:30b64687e01f 7555 #define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */
<> 147:30b64687e01f 7556 #define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */
<> 147:30b64687e01f 7557 #define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */
<> 147:30b64687e01f 7558 #define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */
<> 147:30b64687e01f 7559 #define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */
<> 147:30b64687e01f 7560 #define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */
<> 147:30b64687e01f 7561 #define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */
<> 147:30b64687e01f 7562 #define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */
<> 147:30b64687e01f 7563
<> 147:30b64687e01f 7564
<> 147:30b64687e01f 7565 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
<> 147:30b64687e01f 7566 #define SYSCFG_EXTICR4_EXTI12 0x000FU /*!<EXTI 12 configuration */
<> 147:30b64687e01f 7567 #define SYSCFG_EXTICR4_EXTI13 0x00F0U /*!<EXTI 13 configuration */
<> 147:30b64687e01f 7568 #define SYSCFG_EXTICR4_EXTI14 0x0F00U /*!<EXTI 14 configuration */
<> 147:30b64687e01f 7569 #define SYSCFG_EXTICR4_EXTI15 0xF000U /*!<EXTI 15 configuration */
<> 147:30b64687e01f 7570 /**
<> 147:30b64687e01f 7571 * @brief EXTI12 configuration
<> 147:30b64687e01f 7572 */
<> 147:30b64687e01f 7573 #define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */
<> 147:30b64687e01f 7574 #define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */
<> 147:30b64687e01f 7575 #define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */
<> 147:30b64687e01f 7576 #define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */
<> 147:30b64687e01f 7577 #define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */
<> 147:30b64687e01f 7578 #define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */
<> 147:30b64687e01f 7579 #define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */
<> 147:30b64687e01f 7580 #define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */
<> 147:30b64687e01f 7581 #define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */
<> 147:30b64687e01f 7582 #define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */
<> 147:30b64687e01f 7583
<> 147:30b64687e01f 7584 /**
<> 147:30b64687e01f 7585 * @brief EXTI13 configuration
<> 147:30b64687e01f 7586 */
<> 147:30b64687e01f 7587 #define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */
<> 147:30b64687e01f 7588 #define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */
<> 147:30b64687e01f 7589 #define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */
<> 147:30b64687e01f 7590 #define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */
<> 147:30b64687e01f 7591 #define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */
<> 147:30b64687e01f 7592 #define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */
<> 147:30b64687e01f 7593 #define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */
<> 147:30b64687e01f 7594 #define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */
<> 147:30b64687e01f 7595 #define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */
<> 147:30b64687e01f 7596 #define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */
<> 147:30b64687e01f 7597
<> 147:30b64687e01f 7598 /**
<> 147:30b64687e01f 7599 * @brief EXTI14 configuration
<> 147:30b64687e01f 7600 */
<> 147:30b64687e01f 7601 #define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */
<> 147:30b64687e01f 7602 #define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */
<> 147:30b64687e01f 7603 #define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */
<> 147:30b64687e01f 7604 #define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */
<> 147:30b64687e01f 7605 #define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */
<> 147:30b64687e01f 7606 #define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */
<> 147:30b64687e01f 7607 #define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */
<> 147:30b64687e01f 7608 #define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */
<> 147:30b64687e01f 7609 #define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */
<> 147:30b64687e01f 7610 #define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */
<> 147:30b64687e01f 7611
<> 147:30b64687e01f 7612 /**
<> 147:30b64687e01f 7613 * @brief EXTI15 configuration
<> 147:30b64687e01f 7614 */
<> 147:30b64687e01f 7615 #define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */
<> 147:30b64687e01f 7616 #define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */
<> 147:30b64687e01f 7617 #define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */
<> 147:30b64687e01f 7618 #define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */
<> 147:30b64687e01f 7619 #define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */
<> 147:30b64687e01f 7620 #define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */
<> 147:30b64687e01f 7621 #define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */
<> 147:30b64687e01f 7622 #define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */
<> 147:30b64687e01f 7623 #define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */
<> 147:30b64687e01f 7624 #define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */
<> 147:30b64687e01f 7625
<> 147:30b64687e01f 7626 /****************** Bit definition for SYSCFG_CBR register ******************/
<> 147:30b64687e01f 7627 #define SYSCFG_CBR_CLL 0x00000001U /*!<Core Lockup Lock */
<> 147:30b64687e01f 7628 #define SYSCFG_CBR_PVDL 0x00000004U /*!<PVD Lock */
<> 147:30b64687e01f 7629
<> 147:30b64687e01f 7630 /****************** Bit definition for SYSCFG_CMPCR register ****************/
<> 147:30b64687e01f 7631 #define SYSCFG_CMPCR_CMP_PD 0x00000001U /*!<Compensation cell power-down */
<> 147:30b64687e01f 7632 #define SYSCFG_CMPCR_READY 0x00000100U /*!<Compensation cell ready flag */
<> 147:30b64687e01f 7633
<> 147:30b64687e01f 7634 /******************************************************************************/
<> 147:30b64687e01f 7635 /* */
<> 147:30b64687e01f 7636 /* TIM */
<> 147:30b64687e01f 7637 /* */
<> 147:30b64687e01f 7638 /******************************************************************************/
<> 147:30b64687e01f 7639 /******************* Bit definition for TIM_CR1 register ********************/
<> 147:30b64687e01f 7640 #define TIM_CR1_CEN 0x0001U /*!<Counter enable */
<> 147:30b64687e01f 7641 #define TIM_CR1_UDIS 0x0002U /*!<Update disable */
<> 147:30b64687e01f 7642 #define TIM_CR1_URS 0x0004U /*!<Update request source */
<> 147:30b64687e01f 7643 #define TIM_CR1_OPM 0x0008U /*!<One pulse mode */
<> 147:30b64687e01f 7644 #define TIM_CR1_DIR 0x0010U /*!<Direction */
<> 147:30b64687e01f 7645
<> 147:30b64687e01f 7646 #define TIM_CR1_CMS 0x0060U /*!<CMS[1:0] bits (Center-aligned mode selection) */
<> 147:30b64687e01f 7647 #define TIM_CR1_CMS_0 0x0020U /*!<Bit 0 */
<> 147:30b64687e01f 7648 #define TIM_CR1_CMS_1 0x0040U /*!<Bit 1 */
<> 147:30b64687e01f 7649
<> 147:30b64687e01f 7650 #define TIM_CR1_ARPE 0x0080U /*!<Auto-reload preload enable */
<> 147:30b64687e01f 7651
<> 147:30b64687e01f 7652 #define TIM_CR1_CKD 0x0300U /*!<CKD[1:0] bits (clock division) */
<> 147:30b64687e01f 7653 #define TIM_CR1_CKD_0 0x0100U /*!<Bit 0 */
<> 147:30b64687e01f 7654 #define TIM_CR1_CKD_1 0x0200U /*!<Bit 1 */
<> 147:30b64687e01f 7655 #define TIM_CR1_UIFREMAP 0x0800U /*!<UIF status bit */
<> 147:30b64687e01f 7656
<> 147:30b64687e01f 7657 /******************* Bit definition for TIM_CR2 register ********************/
<> 147:30b64687e01f 7658 #define TIM_CR2_CCPC 0x00000001U /*!<Capture/Compare Preloaded Control */
<> 147:30b64687e01f 7659 #define TIM_CR2_CCUS 0x00000004U /*!<Capture/Compare Control Update Selection */
<> 147:30b64687e01f 7660 #define TIM_CR2_CCDS 0x00000008U /*!<Capture/Compare DMA Selection */
<> 147:30b64687e01f 7661
<> 147:30b64687e01f 7662 #define TIM_CR2_OIS5 0x00010000U /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 7663 #define TIM_CR2_OIS6 0x00040000U /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 7664
<> 147:30b64687e01f 7665 #define TIM_CR2_MMS 0x0070U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 147:30b64687e01f 7666 #define TIM_CR2_MMS_0 0x0010U /*!<Bit 0 */
<> 147:30b64687e01f 7667 #define TIM_CR2_MMS_1 0x0020U /*!<Bit 1 */
<> 147:30b64687e01f 7668 #define TIM_CR2_MMS_2 0x0040U /*!<Bit 2 */
<> 147:30b64687e01f 7669
<> 147:30b64687e01f 7670 #define TIM_CR2_MMS2 0x00F00000U /*!<MMS[2:0] bits (Master Mode Selection) */
<> 147:30b64687e01f 7671 #define TIM_CR2_MMS2_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 7672 #define TIM_CR2_MMS2_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 7673 #define TIM_CR2_MMS2_2 0x00400000U /*!<Bit 2 */
<> 147:30b64687e01f 7674 #define TIM_CR2_MMS2_3 0x00800000U /*!<Bit 2 */
<> 147:30b64687e01f 7675
<> 147:30b64687e01f 7676 #define TIM_CR2_TI1S 0x0080U /*!<TI1 Selection */
<> 147:30b64687e01f 7677 #define TIM_CR2_OIS1 0x0100U /*!<Output Idle state 1 (OC1 output) */
<> 147:30b64687e01f 7678 #define TIM_CR2_OIS1N 0x0200U /*!<Output Idle state 1 (OC1N output) */
<> 147:30b64687e01f 7679 #define TIM_CR2_OIS2 0x0400U /*!<Output Idle state 2 (OC2 output) */
<> 147:30b64687e01f 7680 #define TIM_CR2_OIS2N 0x0800U /*!<Output Idle state 2 (OC2N output) */
<> 147:30b64687e01f 7681 #define TIM_CR2_OIS3 0x1000U /*!<Output Idle state 3 (OC3 output) */
<> 147:30b64687e01f 7682 #define TIM_CR2_OIS3N 0x2000U /*!<Output Idle state 3 (OC3N output) */
<> 147:30b64687e01f 7683 #define TIM_CR2_OIS4 0x4000U /*!<Output Idle state 4 (OC4 output) */
<> 147:30b64687e01f 7684
<> 147:30b64687e01f 7685 /******************* Bit definition for TIM_SMCR register *******************/
<> 147:30b64687e01f 7686 #define TIM_SMCR_SMS 0x00010007U /*!<SMS[2:0] bits (Slave mode selection) */
<> 147:30b64687e01f 7687 #define TIM_SMCR_SMS_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 7688 #define TIM_SMCR_SMS_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 7689 #define TIM_SMCR_SMS_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 7690 #define TIM_SMCR_SMS_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 7691 #define TIM_SMCR_OCCS 0x00000008U /*!< OCREF clear selection */
<> 147:30b64687e01f 7692
<> 147:30b64687e01f 7693 #define TIM_SMCR_TS 0x0070U /*!<TS[2:0] bits (Trigger selection) */
<> 147:30b64687e01f 7694 #define TIM_SMCR_TS_0 0x0010U /*!<Bit 0 */
<> 147:30b64687e01f 7695 #define TIM_SMCR_TS_1 0x0020U /*!<Bit 1 */
<> 147:30b64687e01f 7696 #define TIM_SMCR_TS_2 0x0040U /*!<Bit 2 */
<> 147:30b64687e01f 7697
<> 147:30b64687e01f 7698 #define TIM_SMCR_MSM 0x0080U /*!<Master/slave mode */
<> 147:30b64687e01f 7699
<> 147:30b64687e01f 7700 #define TIM_SMCR_ETF 0x0F00U /*!<ETF[3:0] bits (External trigger filter) */
<> 147:30b64687e01f 7701 #define TIM_SMCR_ETF_0 0x0100U /*!<Bit 0 */
<> 147:30b64687e01f 7702 #define TIM_SMCR_ETF_1 0x0200U /*!<Bit 1 */
<> 147:30b64687e01f 7703 #define TIM_SMCR_ETF_2 0x0400U /*!<Bit 2 */
<> 147:30b64687e01f 7704 #define TIM_SMCR_ETF_3 0x0800U /*!<Bit 3 */
<> 147:30b64687e01f 7705
<> 147:30b64687e01f 7706 #define TIM_SMCR_ETPS 0x3000U /*!<ETPS[1:0] bits (External trigger prescaler) */
<> 147:30b64687e01f 7707 #define TIM_SMCR_ETPS_0 0x1000U /*!<Bit 0 */
<> 147:30b64687e01f 7708 #define TIM_SMCR_ETPS_1 0x2000U /*!<Bit 1 */
<> 147:30b64687e01f 7709
<> 147:30b64687e01f 7710 #define TIM_SMCR_ECE 0x4000U /*!<External clock enable */
<> 147:30b64687e01f 7711 #define TIM_SMCR_ETP 0x8000U /*!<External trigger polarity */
<> 147:30b64687e01f 7712
<> 147:30b64687e01f 7713 /******************* Bit definition for TIM_DIER register *******************/
<> 147:30b64687e01f 7714 #define TIM_DIER_UIE 0x0001U /*!<Update interrupt enable */
<> 147:30b64687e01f 7715 #define TIM_DIER_CC1IE 0x0002U /*!<Capture/Compare 1 interrupt enable */
<> 147:30b64687e01f 7716 #define TIM_DIER_CC2IE 0x0004U /*!<Capture/Compare 2 interrupt enable */
<> 147:30b64687e01f 7717 #define TIM_DIER_CC3IE 0x0008U /*!<Capture/Compare 3 interrupt enable */
<> 147:30b64687e01f 7718 #define TIM_DIER_CC4IE 0x0010U /*!<Capture/Compare 4 interrupt enable */
<> 147:30b64687e01f 7719 #define TIM_DIER_COMIE 0x0020U /*!<COM interrupt enable */
<> 147:30b64687e01f 7720 #define TIM_DIER_TIE 0x0040U /*!<Trigger interrupt enable */
<> 147:30b64687e01f 7721 #define TIM_DIER_BIE 0x0080U /*!<Break interrupt enable */
<> 147:30b64687e01f 7722 #define TIM_DIER_UDE 0x0100U /*!<Update DMA request enable */
<> 147:30b64687e01f 7723 #define TIM_DIER_CC1DE 0x0200U /*!<Capture/Compare 1 DMA request enable */
<> 147:30b64687e01f 7724 #define TIM_DIER_CC2DE 0x0400U /*!<Capture/Compare 2 DMA request enable */
<> 147:30b64687e01f 7725 #define TIM_DIER_CC3DE 0x0800U /*!<Capture/Compare 3 DMA request enable */
<> 147:30b64687e01f 7726 #define TIM_DIER_CC4DE 0x1000U /*!<Capture/Compare 4 DMA request enable */
<> 147:30b64687e01f 7727 #define TIM_DIER_COMDE 0x2000U /*!<COM DMA request enable */
<> 147:30b64687e01f 7728 #define TIM_DIER_TDE 0x4000U /*!<Trigger DMA request enable */
<> 147:30b64687e01f 7729
<> 147:30b64687e01f 7730 /******************** Bit definition for TIM_SR register ********************/
<> 147:30b64687e01f 7731 #define TIM_SR_UIF 0x0001U /*!<Update interrupt Flag */
<> 147:30b64687e01f 7732 #define TIM_SR_CC1IF 0x0002U /*!<Capture/Compare 1 interrupt Flag */
<> 147:30b64687e01f 7733 #define TIM_SR_CC2IF 0x0004U /*!<Capture/Compare 2 interrupt Flag */
<> 147:30b64687e01f 7734 #define TIM_SR_CC3IF 0x0008U /*!<Capture/Compare 3 interrupt Flag */
<> 147:30b64687e01f 7735 #define TIM_SR_CC4IF 0x0010U /*!<Capture/Compare 4 interrupt Flag */
<> 147:30b64687e01f 7736 #define TIM_SR_COMIF 0x0020U /*!<COM interrupt Flag */
<> 147:30b64687e01f 7737 #define TIM_SR_TIF 0x0040U /*!<Trigger interrupt Flag */
<> 147:30b64687e01f 7738 #define TIM_SR_BIF 0x0080U /*!<Break interrupt Flag */
<> 147:30b64687e01f 7739 #define TIM_SR_B2IF 0x0100U /*!<Break2 interrupt Flag */
<> 147:30b64687e01f 7740 #define TIM_SR_CC1OF 0x0200U /*!<Capture/Compare 1 Overcapture Flag */
<> 147:30b64687e01f 7741 #define TIM_SR_CC2OF 0x0400U /*!<Capture/Compare 2 Overcapture Flag */
<> 147:30b64687e01f 7742 #define TIM_SR_CC3OF 0x0800U /*!<Capture/Compare 3 Overcapture Flag */
<> 147:30b64687e01f 7743 #define TIM_SR_CC4OF 0x1000U /*!<Capture/Compare 4 Overcapture Flag */
<> 147:30b64687e01f 7744
<> 147:30b64687e01f 7745 /******************* Bit definition for TIM_EGR register ********************/
<> 147:30b64687e01f 7746 #define TIM_EGR_UG 0x00000001U /*!<Update Generation */
<> 147:30b64687e01f 7747 #define TIM_EGR_CC1G 0x00000002U /*!<Capture/Compare 1 Generation */
<> 147:30b64687e01f 7748 #define TIM_EGR_CC2G 0x00000004U /*!<Capture/Compare 2 Generation */
<> 147:30b64687e01f 7749 #define TIM_EGR_CC3G 0x00000008U /*!<Capture/Compare 3 Generation */
<> 147:30b64687e01f 7750 #define TIM_EGR_CC4G 0x00000010U /*!<Capture/Compare 4 Generation */
<> 147:30b64687e01f 7751 #define TIM_EGR_COMG 0x00000020U /*!<Capture/Compare Control Update Generation */
<> 147:30b64687e01f 7752 #define TIM_EGR_TG 0x00000040U /*!<Trigger Generation */
<> 147:30b64687e01f 7753 #define TIM_EGR_BG 0x00000080U /*!<Break Generation */
<> 147:30b64687e01f 7754 #define TIM_EGR_B2G 0x00000100U /*!<Break2 Generation */
<> 147:30b64687e01f 7755
<> 147:30b64687e01f 7756 /****************** Bit definition for TIM_CCMR1 register *******************/
<> 147:30b64687e01f 7757 #define TIM_CCMR1_CC1S 0x00000003U /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
<> 147:30b64687e01f 7758 #define TIM_CCMR1_CC1S_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 7759 #define TIM_CCMR1_CC1S_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 7760
<> 147:30b64687e01f 7761 #define TIM_CCMR1_OC1FE 0x00000004U /*!<Output Compare 1 Fast enable */
<> 147:30b64687e01f 7762 #define TIM_CCMR1_OC1PE 0x00000008U /*!<Output Compare 1 Preload enable */
<> 147:30b64687e01f 7763
<> 147:30b64687e01f 7764 #define TIM_CCMR1_OC1M 0x00010070U /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
<> 147:30b64687e01f 7765 #define TIM_CCMR1_OC1M_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 7766 #define TIM_CCMR1_OC1M_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 7767 #define TIM_CCMR1_OC1M_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 7768 #define TIM_CCMR1_OC1M_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 7769
<> 147:30b64687e01f 7770 #define TIM_CCMR1_OC1CE 0x00000080U /*!<Output Compare 1Clear Enable */
<> 147:30b64687e01f 7771
<> 147:30b64687e01f 7772 #define TIM_CCMR1_CC2S 0x00000300U /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
<> 147:30b64687e01f 7773 #define TIM_CCMR1_CC2S_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 7774 #define TIM_CCMR1_CC2S_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 7775
<> 147:30b64687e01f 7776 #define TIM_CCMR1_OC2FE 0x00000400U /*!<Output Compare 2 Fast enable */
<> 147:30b64687e01f 7777 #define TIM_CCMR1_OC2PE 0x00000800U /*!<Output Compare 2 Preload enable */
<> 147:30b64687e01f 7778
<> 147:30b64687e01f 7779 #define TIM_CCMR1_OC2M 0x01007000U /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
<> 147:30b64687e01f 7780 #define TIM_CCMR1_OC2M_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 7781 #define TIM_CCMR1_OC2M_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 7782 #define TIM_CCMR1_OC2M_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 7783 #define TIM_CCMR1_OC2M_3 0x01000000U /*!<Bit 3 */
<> 147:30b64687e01f 7784
<> 147:30b64687e01f 7785 #define TIM_CCMR1_OC2CE 0x00008000U /*!<Output Compare 2 Clear Enable */
<> 147:30b64687e01f 7786
<> 147:30b64687e01f 7787 /*----------------------------------------------------------------------------*/
<> 147:30b64687e01f 7788
<> 147:30b64687e01f 7789 #define TIM_CCMR1_IC1PSC 0x000CU /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
<> 147:30b64687e01f 7790 #define TIM_CCMR1_IC1PSC_0 0x0004U /*!<Bit 0 */
<> 147:30b64687e01f 7791 #define TIM_CCMR1_IC1PSC_1 0x0008U /*!<Bit 1 */
<> 147:30b64687e01f 7792
<> 147:30b64687e01f 7793 #define TIM_CCMR1_IC1F 0x00F0U /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
<> 147:30b64687e01f 7794 #define TIM_CCMR1_IC1F_0 0x0010U /*!<Bit 0 */
<> 147:30b64687e01f 7795 #define TIM_CCMR1_IC1F_1 0x0020U /*!<Bit 1 */
<> 147:30b64687e01f 7796 #define TIM_CCMR1_IC1F_2 0x0040U /*!<Bit 2 */
<> 147:30b64687e01f 7797 #define TIM_CCMR1_IC1F_3 0x0080U /*!<Bit 3 */
<> 147:30b64687e01f 7798
<> 147:30b64687e01f 7799 #define TIM_CCMR1_IC2PSC 0x0C00U /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
<> 147:30b64687e01f 7800 #define TIM_CCMR1_IC2PSC_0 0x0400U /*!<Bit 0 */
<> 147:30b64687e01f 7801 #define TIM_CCMR1_IC2PSC_1 0x0800U /*!<Bit 1 */
<> 147:30b64687e01f 7802
<> 147:30b64687e01f 7803 #define TIM_CCMR1_IC2F 0xF000U /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
<> 147:30b64687e01f 7804 #define TIM_CCMR1_IC2F_0 0x1000U /*!<Bit 0 */
<> 147:30b64687e01f 7805 #define TIM_CCMR1_IC2F_1 0x2000U /*!<Bit 1 */
<> 147:30b64687e01f 7806 #define TIM_CCMR1_IC2F_2 0x4000U /*!<Bit 2 */
<> 147:30b64687e01f 7807 #define TIM_CCMR1_IC2F_3 0x8000U /*!<Bit 3 */
<> 147:30b64687e01f 7808
<> 147:30b64687e01f 7809 /****************** Bit definition for TIM_CCMR2 register *******************/
<> 147:30b64687e01f 7810 #define TIM_CCMR2_CC3S 0x00000003U /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
<> 147:30b64687e01f 7811 #define TIM_CCMR2_CC3S_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 7812 #define TIM_CCMR2_CC3S_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 7813
<> 147:30b64687e01f 7814 #define TIM_CCMR2_OC3FE 0x00000004U /*!<Output Compare 3 Fast enable */
<> 147:30b64687e01f 7815 #define TIM_CCMR2_OC3PE 0x00000008U /*!<Output Compare 3 Preload enable */
<> 147:30b64687e01f 7816
<> 147:30b64687e01f 7817 #define TIM_CCMR2_OC3M 0x00010070U /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
<> 147:30b64687e01f 7818 #define TIM_CCMR2_OC3M_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 7819 #define TIM_CCMR2_OC3M_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 7820 #define TIM_CCMR2_OC3M_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 7821 #define TIM_CCMR2_OC3M_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 7822
<> 147:30b64687e01f 7823
<> 147:30b64687e01f 7824
<> 147:30b64687e01f 7825 #define TIM_CCMR2_OC3CE 0x00000080U /*!<Output Compare 3 Clear Enable */
<> 147:30b64687e01f 7826
<> 147:30b64687e01f 7827 #define TIM_CCMR2_CC4S 0x00000300U /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
<> 147:30b64687e01f 7828 #define TIM_CCMR2_CC4S_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 7829 #define TIM_CCMR2_CC4S_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 7830
<> 147:30b64687e01f 7831 #define TIM_CCMR2_OC4FE 0x00000400U /*!<Output Compare 4 Fast enable */
<> 147:30b64687e01f 7832 #define TIM_CCMR2_OC4PE 0x00000800U /*!<Output Compare 4 Preload enable */
<> 147:30b64687e01f 7833
<> 147:30b64687e01f 7834 #define TIM_CCMR2_OC4M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 147:30b64687e01f 7835 #define TIM_CCMR2_OC4M_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 7836 #define TIM_CCMR2_OC4M_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 7837 #define TIM_CCMR2_OC4M_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 7838 #define TIM_CCMR2_OC4M_3 0x01000000U /*!<Bit 3 */
<> 147:30b64687e01f 7839
<> 147:30b64687e01f 7840 #define TIM_CCMR2_OC4CE 0x8000U /*!<Output Compare 4 Clear Enable */
<> 147:30b64687e01f 7841
<> 147:30b64687e01f 7842 /*----------------------------------------------------------------------------*/
<> 147:30b64687e01f 7843
<> 147:30b64687e01f 7844 #define TIM_CCMR2_IC3PSC 0x000CU /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
<> 147:30b64687e01f 7845 #define TIM_CCMR2_IC3PSC_0 0x0004U /*!<Bit 0 */
<> 147:30b64687e01f 7846 #define TIM_CCMR2_IC3PSC_1 0x0008U /*!<Bit 1 */
<> 147:30b64687e01f 7847
<> 147:30b64687e01f 7848 #define TIM_CCMR2_IC3F 0x00F0U /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
<> 147:30b64687e01f 7849 #define TIM_CCMR2_IC3F_0 0x0010U /*!<Bit 0 */
<> 147:30b64687e01f 7850 #define TIM_CCMR2_IC3F_1 0x0020U /*!<Bit 1 */
<> 147:30b64687e01f 7851 #define TIM_CCMR2_IC3F_2 0x0040U /*!<Bit 2 */
<> 147:30b64687e01f 7852 #define TIM_CCMR2_IC3F_3 0x0080U /*!<Bit 3 */
<> 147:30b64687e01f 7853
<> 147:30b64687e01f 7854 #define TIM_CCMR2_IC4PSC 0x0C00U /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
<> 147:30b64687e01f 7855 #define TIM_CCMR2_IC4PSC_0 0x0400U /*!<Bit 0 */
<> 147:30b64687e01f 7856 #define TIM_CCMR2_IC4PSC_1 0x0800U /*!<Bit 1 */
<> 147:30b64687e01f 7857
<> 147:30b64687e01f 7858 #define TIM_CCMR2_IC4F 0xF000U /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
<> 147:30b64687e01f 7859 #define TIM_CCMR2_IC4F_0 0x1000U /*!<Bit 0 */
<> 147:30b64687e01f 7860 #define TIM_CCMR2_IC4F_1 0x2000U /*!<Bit 1 */
<> 147:30b64687e01f 7861 #define TIM_CCMR2_IC4F_2 0x4000U /*!<Bit 2 */
<> 147:30b64687e01f 7862 #define TIM_CCMR2_IC4F_3 0x8000U /*!<Bit 3 */
<> 147:30b64687e01f 7863
<> 147:30b64687e01f 7864 /******************* Bit definition for TIM_CCER register *******************/
<> 147:30b64687e01f 7865 #define TIM_CCER_CC1E 0x00000001U /*!<Capture/Compare 1 output enable */
<> 147:30b64687e01f 7866 #define TIM_CCER_CC1P 0x00000002U /*!<Capture/Compare 1 output Polarity */
<> 147:30b64687e01f 7867 #define TIM_CCER_CC1NE 0x00000004U /*!<Capture/Compare 1 Complementary output enable */
<> 147:30b64687e01f 7868 #define TIM_CCER_CC1NP 0x00000008U /*!<Capture/Compare 1 Complementary output Polarity */
<> 147:30b64687e01f 7869 #define TIM_CCER_CC2E 0x00000010U /*!<Capture/Compare 2 output enable */
<> 147:30b64687e01f 7870 #define TIM_CCER_CC2P 0x00000020U /*!<Capture/Compare 2 output Polarity */
<> 147:30b64687e01f 7871 #define TIM_CCER_CC2NE 0x00000040U /*!<Capture/Compare 2 Complementary output enable */
<> 147:30b64687e01f 7872 #define TIM_CCER_CC2NP 0x00000080U /*!<Capture/Compare 2 Complementary output Polarity */
<> 147:30b64687e01f 7873 #define TIM_CCER_CC3E 0x00000100U /*!<Capture/Compare 3 output enable */
<> 147:30b64687e01f 7874 #define TIM_CCER_CC3P 0x00000200U /*!<Capture/Compare 3 output Polarity */
<> 147:30b64687e01f 7875 #define TIM_CCER_CC3NE 0x00000400U /*!<Capture/Compare 3 Complementary output enable */
<> 147:30b64687e01f 7876 #define TIM_CCER_CC3NP 0x00000800U /*!<Capture/Compare 3 Complementary output Polarity */
<> 147:30b64687e01f 7877 #define TIM_CCER_CC4E 0x00001000U /*!<Capture/Compare 4 output enable */
<> 147:30b64687e01f 7878 #define TIM_CCER_CC4P 0x00002000U /*!<Capture/Compare 4 output Polarity */
<> 147:30b64687e01f 7879 #define TIM_CCER_CC4NP 0x00008000U /*!<Capture/Compare 4 Complementary output Polarity */
<> 147:30b64687e01f 7880 #define TIM_CCER_CC5E 0x00010000U /*!<Capture/Compare 5 output enable */
<> 147:30b64687e01f 7881 #define TIM_CCER_CC5P 0x00020000U /*!<Capture/Compare 5 output Polarity */
<> 147:30b64687e01f 7882 #define TIM_CCER_CC6E 0x00100000U /*!<Capture/Compare 6 output enable */
<> 147:30b64687e01f 7883 #define TIM_CCER_CC6P 0x00200000U /*!<Capture/Compare 6 output Polarity */
<> 147:30b64687e01f 7884
<> 147:30b64687e01f 7885
<> 147:30b64687e01f 7886 /******************* Bit definition for TIM_CNT register ********************/
<> 147:30b64687e01f 7887 #define TIM_CNT_CNT 0xFFFFU /*!<Counter Value */
<> 147:30b64687e01f 7888
<> 147:30b64687e01f 7889 /******************* Bit definition for TIM_PSC register ********************/
<> 147:30b64687e01f 7890 #define TIM_PSC_PSC 0xFFFFU /*!<Prescaler Value */
<> 147:30b64687e01f 7891
<> 147:30b64687e01f 7892 /******************* Bit definition for TIM_ARR register ********************/
<> 147:30b64687e01f 7893 #define TIM_ARR_ARR 0xFFFFU /*!<actual auto-reload Value */
<> 147:30b64687e01f 7894
<> 147:30b64687e01f 7895 /******************* Bit definition for TIM_RCR register ********************/
<> 147:30b64687e01f 7896 #define TIM_RCR_REP ((uint8_t)0xFFU) /*!<Repetition Counter Value */
<> 147:30b64687e01f 7897
<> 147:30b64687e01f 7898 /******************* Bit definition for TIM_CCR1 register *******************/
<> 147:30b64687e01f 7899 #define TIM_CCR1_CCR1 0xFFFFU /*!<Capture/Compare 1 Value */
<> 147:30b64687e01f 7900
<> 147:30b64687e01f 7901 /******************* Bit definition for TIM_CCR2 register *******************/
<> 147:30b64687e01f 7902 #define TIM_CCR2_CCR2 0xFFFFU /*!<Capture/Compare 2 Value */
<> 147:30b64687e01f 7903
<> 147:30b64687e01f 7904 /******************* Bit definition for TIM_CCR3 register *******************/
<> 147:30b64687e01f 7905 #define TIM_CCR3_CCR3 0xFFFFU /*!<Capture/Compare 3 Value */
<> 147:30b64687e01f 7906
<> 147:30b64687e01f 7907 /******************* Bit definition for TIM_CCR4 register *******************/
<> 147:30b64687e01f 7908 #define TIM_CCR4_CCR4 0xFFFFU /*!<Capture/Compare 4 Value */
<> 147:30b64687e01f 7909
<> 147:30b64687e01f 7910 /******************* Bit definition for TIM_BDTR register *******************/
<> 147:30b64687e01f 7911 #define TIM_BDTR_DTG 0x000000FFU /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
<> 147:30b64687e01f 7912 #define TIM_BDTR_DTG_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 7913 #define TIM_BDTR_DTG_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 7914 #define TIM_BDTR_DTG_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 7915 #define TIM_BDTR_DTG_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 7916 #define TIM_BDTR_DTG_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 7917 #define TIM_BDTR_DTG_5 0x00000020U /*!<Bit 5 */
<> 147:30b64687e01f 7918 #define TIM_BDTR_DTG_6 0x00000040U /*!<Bit 6 */
<> 147:30b64687e01f 7919 #define TIM_BDTR_DTG_7 0x00000080U /*!<Bit 7 */
<> 147:30b64687e01f 7920
<> 147:30b64687e01f 7921 #define TIM_BDTR_LOCK 0x00000300U /*!<LOCK[1:0] bits (Lock Configuration) */
<> 147:30b64687e01f 7922 #define TIM_BDTR_LOCK_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 7923 #define TIM_BDTR_LOCK_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 7924
<> 147:30b64687e01f 7925 #define TIM_BDTR_OSSI 0x00000400U /*!<Off-State Selection for Idle mode */
<> 147:30b64687e01f 7926 #define TIM_BDTR_OSSR 0x00000800U /*!<Off-State Selection for Run mode */
<> 147:30b64687e01f 7927 #define TIM_BDTR_BKE 0x00001000U /*!<Break enable */
<> 147:30b64687e01f 7928 #define TIM_BDTR_BKP 0x00002000U /*!<Break Polarity */
<> 147:30b64687e01f 7929 #define TIM_BDTR_AOE 0x00004000U /*!<Automatic Output enable */
<> 147:30b64687e01f 7930 #define TIM_BDTR_MOE 0x00008000U /*!<Main Output enable */
<> 147:30b64687e01f 7931 #define TIM_BDTR_BKF 0x000F0000U /*!<Break Filter for Break1 */
<> 147:30b64687e01f 7932 #define TIM_BDTR_BK2F 0x00F00000U /*!<Break Filter for Break2 */
<> 147:30b64687e01f 7933 #define TIM_BDTR_BK2E 0x01000000U /*!<Break enable for Break2 */
<> 147:30b64687e01f 7934 #define TIM_BDTR_BK2P 0x02000000U /*!<Break Polarity for Break2 */
<> 147:30b64687e01f 7935
<> 147:30b64687e01f 7936 /******************* Bit definition for TIM_DCR register ********************/
<> 147:30b64687e01f 7937 #define TIM_DCR_DBA 0x001FU /*!<DBA[4:0] bits (DMA Base Address) */
<> 147:30b64687e01f 7938 #define TIM_DCR_DBA_0 0x0001U /*!<Bit 0 */
<> 147:30b64687e01f 7939 #define TIM_DCR_DBA_1 0x0002U /*!<Bit 1 */
<> 147:30b64687e01f 7940 #define TIM_DCR_DBA_2 0x0004U /*!<Bit 2 */
<> 147:30b64687e01f 7941 #define TIM_DCR_DBA_3 0x0008U /*!<Bit 3 */
<> 147:30b64687e01f 7942 #define TIM_DCR_DBA_4 0x0010U /*!<Bit 4 */
<> 147:30b64687e01f 7943
<> 147:30b64687e01f 7944 #define TIM_DCR_DBL 0x1F00U /*!<DBL[4:0] bits (DMA Burst Length) */
<> 147:30b64687e01f 7945 #define TIM_DCR_DBL_0 0x0100U /*!<Bit 0 */
<> 147:30b64687e01f 7946 #define TIM_DCR_DBL_1 0x0200U /*!<Bit 1 */
<> 147:30b64687e01f 7947 #define TIM_DCR_DBL_2 0x0400U /*!<Bit 2 */
<> 147:30b64687e01f 7948 #define TIM_DCR_DBL_3 0x0800U /*!<Bit 3 */
<> 147:30b64687e01f 7949 #define TIM_DCR_DBL_4 0x1000U /*!<Bit 4 */
<> 147:30b64687e01f 7950
<> 147:30b64687e01f 7951 /******************* Bit definition for TIM_DMAR register *******************/
<> 147:30b64687e01f 7952 #define TIM_DMAR_DMAB 0xFFFFU /*!<DMA register for burst accesses */
<> 147:30b64687e01f 7953
<> 147:30b64687e01f 7954 /******************* Bit definition for TIM_OR regiter *********************/
<> 147:30b64687e01f 7955 #define TIM_OR_TI4_RMP 0x00C0U /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */
<> 147:30b64687e01f 7956 #define TIM_OR_TI4_RMP_0 0x0040U /*!<Bit 0 */
<> 147:30b64687e01f 7957 #define TIM_OR_TI4_RMP_1 0x0080U /*!<Bit 1 */
<> 147:30b64687e01f 7958 #define TIM_OR_ITR1_RMP 0x0C00U /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */
<> 147:30b64687e01f 7959 #define TIM_OR_ITR1_RMP_0 0x0400U /*!<Bit 0 */
<> 147:30b64687e01f 7960 #define TIM_OR_ITR1_RMP_1 0x0800U /*!<Bit 1 */
<> 147:30b64687e01f 7961
<> 147:30b64687e01f 7962 /****************** Bit definition for TIM_CCMR3 register *******************/
<> 147:30b64687e01f 7963 #define TIM_CCMR3_OC5FE 0x00000004U /*!<Output Compare 5 Fast enable */
<> 147:30b64687e01f 7964 #define TIM_CCMR3_OC5PE 0x00000008U /*!<Output Compare 5 Preload enable */
<> 147:30b64687e01f 7965
<> 147:30b64687e01f 7966 #define TIM_CCMR3_OC5M 0x00010070U /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
<> 147:30b64687e01f 7967 #define TIM_CCMR3_OC5M_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 7968 #define TIM_CCMR3_OC5M_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 7969 #define TIM_CCMR3_OC5M_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 7970 #define TIM_CCMR3_OC5M_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 7971
<> 147:30b64687e01f 7972 #define TIM_CCMR3_OC5CE 0x00000080U /*!<Output Compare 5 Clear Enable */
<> 147:30b64687e01f 7973
<> 147:30b64687e01f 7974 #define TIM_CCMR3_OC6FE 0x00000400U /*!<Output Compare 4 Fast enable */
<> 147:30b64687e01f 7975 #define TIM_CCMR3_OC6PE 0x00000800U /*!<Output Compare 4 Preload enable */
<> 147:30b64687e01f 7976
<> 147:30b64687e01f 7977 #define TIM_CCMR3_OC6M 0x01007000U /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
<> 147:30b64687e01f 7978 #define TIM_CCMR3_OC6M_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 7979 #define TIM_CCMR3_OC6M_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 7980 #define TIM_CCMR3_OC6M_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 7981 #define TIM_CCMR3_OC6M_3 0x01000000U /*!<Bit 3 */
<> 147:30b64687e01f 7982
<> 147:30b64687e01f 7983 #define TIM_CCMR3_OC6CE 0x00008000U /*!<Output Compare 4 Clear Enable */
<> 147:30b64687e01f 7984
<> 147:30b64687e01f 7985 /******************* Bit definition for TIM_CCR5 register *******************/
<> 147:30b64687e01f 7986 #define TIM_CCR5_CCR5 0xFFFFFFFFU /*!<Capture/Compare 5 Value */
<> 147:30b64687e01f 7987 #define TIM_CCR5_GC5C1 0x20000000U /*!<Group Channel 5 and Channel 1 */
<> 147:30b64687e01f 7988 #define TIM_CCR5_GC5C2 0x40000000U /*!<Group Channel 5 and Channel 2 */
<> 147:30b64687e01f 7989 #define TIM_CCR5_GC5C3 0x80000000U /*!<Group Channel 5 and Channel 3 */
<> 147:30b64687e01f 7990
<> 147:30b64687e01f 7991 /******************* Bit definition for TIM_CCR6 register *******************/
<> 147:30b64687e01f 7992 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */
<> 147:30b64687e01f 7993
<> 147:30b64687e01f 7994 /******************* Bit definition for TIM1_AF1 register *******************/
<> 147:30b64687e01f 7995 #define TIM1_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
<> 147:30b64687e01f 7996 #define TIM1_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
<> 147:30b64687e01f 7997
<> 147:30b64687e01f 7998 /******************* Bit definition for TIM1_AF2 register *******************/
<> 147:30b64687e01f 7999 #define TIM1_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN input enable */
<> 147:30b64687e01f 8000 #define TIM1_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
<> 147:30b64687e01f 8001
<> 147:30b64687e01f 8002 /******************* Bit definition for TIM8_AF1 register *******************/
<> 147:30b64687e01f 8003 #define TIM8_AF1_BKINE 0x00000001U /*!<BRK BKIN input enable */
<> 147:30b64687e01f 8004 #define TIM8_AF1_BKDF1BKE 0x00000100U /*!<BRK DFSDM1_BREAK enable */
<> 147:30b64687e01f 8005
<> 147:30b64687e01f 8006 /******************* Bit definition for TIM8_AF2 register *******************/
<> 147:30b64687e01f 8007 #define TIM8_AF2_BK2INE 0x00000001U /*!<BRK2 BKIN2 input enable */
<> 147:30b64687e01f 8008 #define TIM8_AF2_BK2DF1BKE 0x00000100U /*!<BRK2 DFSDM1_BREAK enable */
<> 147:30b64687e01f 8009
<> 147:30b64687e01f 8010 /******************************************************************************/
<> 147:30b64687e01f 8011 /* */
<> 147:30b64687e01f 8012 /* Low Power Timer (LPTIM) */
<> 147:30b64687e01f 8013 /* */
<> 147:30b64687e01f 8014 /******************************************************************************/
<> 147:30b64687e01f 8015 /****************** Bit definition for LPTIM_ISR register *******************/
<> 147:30b64687e01f 8016 #define LPTIM_ISR_CMPM 0x00000001U /*!< Compare match */
<> 147:30b64687e01f 8017 #define LPTIM_ISR_ARRM 0x00000002U /*!< Autoreload match */
<> 147:30b64687e01f 8018 #define LPTIM_ISR_EXTTRIG 0x00000004U /*!< External trigger edge event */
<> 147:30b64687e01f 8019 #define LPTIM_ISR_CMPOK 0x00000008U /*!< Compare register update OK */
<> 147:30b64687e01f 8020 #define LPTIM_ISR_ARROK 0x00000010U /*!< Autoreload register update OK */
<> 147:30b64687e01f 8021 #define LPTIM_ISR_UP 0x00000020U /*!< Counter direction change down to up */
<> 147:30b64687e01f 8022 #define LPTIM_ISR_DOWN 0x00000040U /*!< Counter direction change up to down */
<> 147:30b64687e01f 8023
<> 147:30b64687e01f 8024 /****************** Bit definition for LPTIM_ICR register *******************/
<> 147:30b64687e01f 8025 #define LPTIM_ICR_CMPMCF 0x00000001U /*!< Compare match Clear Flag */
<> 147:30b64687e01f 8026 #define LPTIM_ICR_ARRMCF 0x00000002U /*!< Autoreload match Clear Flag */
<> 147:30b64687e01f 8027 #define LPTIM_ICR_EXTTRIGCF 0x00000004U /*!< External trigger edge event Clear Flag */
<> 147:30b64687e01f 8028 #define LPTIM_ICR_CMPOKCF 0x00000008U /*!< Compare register update OK Clear Flag */
<> 147:30b64687e01f 8029 #define LPTIM_ICR_ARROKCF 0x00000010U /*!< Autoreload register update OK Clear Flag */
<> 147:30b64687e01f 8030 #define LPTIM_ICR_UPCF 0x00000020U /*!< Counter direction change down to up Clear Flag */
<> 147:30b64687e01f 8031 #define LPTIM_ICR_DOWNCF 0x00000040U /*!< Counter direction change up to down Clear Flag */
<> 147:30b64687e01f 8032
<> 147:30b64687e01f 8033 /****************** Bit definition for LPTIM_IER register *******************/
<> 147:30b64687e01f 8034 #define LPTIM_IER_CMPMIE 0x00000001U /*!< Compare match Interrupt Enable */
<> 147:30b64687e01f 8035 #define LPTIM_IER_ARRMIE 0x00000002U /*!< Autoreload match Interrupt Enable */
<> 147:30b64687e01f 8036 #define LPTIM_IER_EXTTRIGIE 0x00000004U /*!< External trigger edge event Interrupt Enable */
<> 147:30b64687e01f 8037 #define LPTIM_IER_CMPOKIE 0x00000008U /*!< Compare register update OK Interrupt Enable */
<> 147:30b64687e01f 8038 #define LPTIM_IER_ARROKIE 0x00000010U /*!< Autoreload register update OK Interrupt Enable */
<> 147:30b64687e01f 8039 #define LPTIM_IER_UPIE 0x00000020U /*!< Counter direction change down to up Interrupt Enable */
<> 147:30b64687e01f 8040 #define LPTIM_IER_DOWNIE 0x00000040U /*!< Counter direction change up to down Interrupt Enable */
<> 147:30b64687e01f 8041
<> 147:30b64687e01f 8042 /****************** Bit definition for LPTIM_CFGR register*******************/
<> 147:30b64687e01f 8043 #define LPTIM_CFGR_CKSEL 0x00000001U /*!< Clock selector */
<> 147:30b64687e01f 8044
<> 147:30b64687e01f 8045 #define LPTIM_CFGR_CKPOL 0x00000006U /*!< CKPOL[1:0] bits (Clock polarity) */
<> 147:30b64687e01f 8046 #define LPTIM_CFGR_CKPOL_0 0x00000002U /*!< Bit 0 */
<> 147:30b64687e01f 8047 #define LPTIM_CFGR_CKPOL_1 0x00000004U /*!< Bit 1 */
<> 147:30b64687e01f 8048
<> 147:30b64687e01f 8049 #define LPTIM_CFGR_CKFLT 0x00000018U /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
<> 147:30b64687e01f 8050 #define LPTIM_CFGR_CKFLT_0 0x00000008U /*!< Bit 0 */
<> 147:30b64687e01f 8051 #define LPTIM_CFGR_CKFLT_1 0x00000010U /*!< Bit 1 */
<> 147:30b64687e01f 8052
<> 147:30b64687e01f 8053 #define LPTIM_CFGR_TRGFLT 0x000000C0U /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
<> 147:30b64687e01f 8054 #define LPTIM_CFGR_TRGFLT_0 0x00000040U /*!< Bit 0 */
<> 147:30b64687e01f 8055 #define LPTIM_CFGR_TRGFLT_1 0x00000080U /*!< Bit 1 */
<> 147:30b64687e01f 8056
<> 147:30b64687e01f 8057 #define LPTIM_CFGR_PRESC 0x00000E00U /*!< PRESC[2:0] bits (Clock prescaler) */
<> 147:30b64687e01f 8058 #define LPTIM_CFGR_PRESC_0 0x00000200U /*!< Bit 0 */
<> 147:30b64687e01f 8059 #define LPTIM_CFGR_PRESC_1 0x00000400U /*!< Bit 1 */
<> 147:30b64687e01f 8060 #define LPTIM_CFGR_PRESC_2 0x00000800U /*!< Bit 2 */
<> 147:30b64687e01f 8061
<> 147:30b64687e01f 8062 #define LPTIM_CFGR_TRIGSEL 0x0000E000U /*!< TRIGSEL[2:0]] bits (Trigger selector) */
<> 147:30b64687e01f 8063 #define LPTIM_CFGR_TRIGSEL_0 0x00002000U /*!< Bit 0 */
<> 147:30b64687e01f 8064 #define LPTIM_CFGR_TRIGSEL_1 0x00004000U /*!< Bit 1 */
<> 147:30b64687e01f 8065 #define LPTIM_CFGR_TRIGSEL_2 0x00008000U /*!< Bit 2 */
<> 147:30b64687e01f 8066
<> 147:30b64687e01f 8067 #define LPTIM_CFGR_TRIGEN 0x00060000U /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
<> 147:30b64687e01f 8068 #define LPTIM_CFGR_TRIGEN_0 0x00020000U /*!< Bit 0 */
<> 147:30b64687e01f 8069 #define LPTIM_CFGR_TRIGEN_1 0x00040000U /*!< Bit 1 */
<> 147:30b64687e01f 8070
<> 147:30b64687e01f 8071 #define LPTIM_CFGR_TIMOUT 0x00080000U /*!< Timout enable */
<> 147:30b64687e01f 8072 #define LPTIM_CFGR_WAVE 0x00100000U /*!< Waveform shape */
<> 147:30b64687e01f 8073 #define LPTIM_CFGR_WAVPOL 0x00200000U /*!< Waveform shape polarity */
<> 147:30b64687e01f 8074 #define LPTIM_CFGR_PRELOAD 0x00400000U /*!< Reg update mode */
<> 147:30b64687e01f 8075 #define LPTIM_CFGR_COUNTMODE 0x00800000U /*!< Counter mode enable */
<> 147:30b64687e01f 8076 #define LPTIM_CFGR_ENC 0x01000000U /*!< Encoder mode enable */
<> 147:30b64687e01f 8077
<> 147:30b64687e01f 8078 /****************** Bit definition for LPTIM_CR register ********************/
<> 147:30b64687e01f 8079 #define LPTIM_CR_ENABLE 0x00000001U /*!< LPTIMer enable */
<> 147:30b64687e01f 8080 #define LPTIM_CR_SNGSTRT 0x00000002U /*!< Timer start in single mode */
<> 147:30b64687e01f 8081 #define LPTIM_CR_CNTSTRT 0x00000004U /*!< Timer start in continuous mode */
<> 147:30b64687e01f 8082
<> 147:30b64687e01f 8083 /****************** Bit definition for LPTIM_CMP register *******************/
<> 147:30b64687e01f 8084 #define LPTIM_CMP_CMP 0x0000FFFFU /*!< Compare register */
<> 147:30b64687e01f 8085
<> 147:30b64687e01f 8086 /****************** Bit definition for LPTIM_ARR register *******************/
<> 147:30b64687e01f 8087 #define LPTIM_ARR_ARR 0x0000FFFFU /*!< Auto reload register */
<> 147:30b64687e01f 8088
<> 147:30b64687e01f 8089 /****************** Bit definition for LPTIM_CNT register *******************/
<> 147:30b64687e01f 8090 #define LPTIM_CNT_CNT 0x0000FFFFU /*!< Counter register */
<> 147:30b64687e01f 8091 /******************************************************************************/
<> 147:30b64687e01f 8092 /* */
<> 147:30b64687e01f 8093 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
<> 147:30b64687e01f 8094 /* */
<> 147:30b64687e01f 8095 /******************************************************************************/
<> 147:30b64687e01f 8096 /****************** Bit definition for USART_CR1 register *******************/
<> 147:30b64687e01f 8097 #define USART_CR1_UE 0x00000001U /*!< USART Enable */
<> 147:30b64687e01f 8098 #define USART_CR1_RE 0x00000004U /*!< Receiver Enable */
<> 147:30b64687e01f 8099 #define USART_CR1_TE 0x00000008U /*!< Transmitter Enable */
<> 147:30b64687e01f 8100 #define USART_CR1_IDLEIE 0x00000010U /*!< IDLE Interrupt Enable */
<> 147:30b64687e01f 8101 #define USART_CR1_RXNEIE 0x00000020U /*!< RXNE Interrupt Enable */
<> 147:30b64687e01f 8102 #define USART_CR1_TCIE 0x00000040U /*!< Transmission Complete Interrupt Enable */
<> 147:30b64687e01f 8103 #define USART_CR1_TXEIE 0x00000080U /*!< TXE Interrupt Enable */
<> 147:30b64687e01f 8104 #define USART_CR1_PEIE 0x00000100U /*!< PE Interrupt Enable */
<> 147:30b64687e01f 8105 #define USART_CR1_PS 0x00000200U /*!< Parity Selection */
<> 147:30b64687e01f 8106 #define USART_CR1_PCE 0x00000400U /*!< Parity Control Enable */
<> 147:30b64687e01f 8107 #define USART_CR1_WAKE 0x00000800U /*!< Receiver Wakeup method */
<> 147:30b64687e01f 8108 #define USART_CR1_M 0x10001000U /*!< Word length */
<> 147:30b64687e01f 8109 #define USART_CR1_M_0 0x00001000U /*!< Word length - Bit 0 */
<> 147:30b64687e01f 8110 #define USART_CR1_MME 0x00002000U /*!< Mute Mode Enable */
<> 147:30b64687e01f 8111 #define USART_CR1_CMIE 0x00004000U /*!< Character match interrupt enable */
<> 147:30b64687e01f 8112 #define USART_CR1_OVER8 0x00008000U /*!< Oversampling by 8-bit or 16-bit mode */
<> 147:30b64687e01f 8113 #define USART_CR1_DEDT 0x001F0000U /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
<> 147:30b64687e01f 8114 #define USART_CR1_DEDT_0 0x00010000U /*!< Bit 0 */
<> 147:30b64687e01f 8115 #define USART_CR1_DEDT_1 0x00020000U /*!< Bit 1 */
<> 147:30b64687e01f 8116 #define USART_CR1_DEDT_2 0x00040000U /*!< Bit 2 */
<> 147:30b64687e01f 8117 #define USART_CR1_DEDT_3 0x00080000U /*!< Bit 3 */
<> 147:30b64687e01f 8118 #define USART_CR1_DEDT_4 0x00100000U /*!< Bit 4 */
<> 147:30b64687e01f 8119 #define USART_CR1_DEAT 0x03E00000U /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
<> 147:30b64687e01f 8120 #define USART_CR1_DEAT_0 0x00200000U /*!< Bit 0 */
<> 147:30b64687e01f 8121 #define USART_CR1_DEAT_1 0x00400000U /*!< Bit 1 */
<> 147:30b64687e01f 8122 #define USART_CR1_DEAT_2 0x00800000U /*!< Bit 2 */
<> 147:30b64687e01f 8123 #define USART_CR1_DEAT_3 0x01000000U /*!< Bit 3 */
<> 147:30b64687e01f 8124 #define USART_CR1_DEAT_4 0x02000000U /*!< Bit 4 */
<> 147:30b64687e01f 8125 #define USART_CR1_RTOIE 0x04000000U /*!< Receive Time Out interrupt enable */
<> 147:30b64687e01f 8126 #define USART_CR1_EOBIE 0x08000000U /*!< End of Block interrupt enable */
<> 147:30b64687e01f 8127 #define USART_CR1_M_1 0x10000000U /*!< Word length - Bit 1 */
<> 147:30b64687e01f 8128
<> 147:30b64687e01f 8129 /****************** Bit definition for USART_CR2 register *******************/
<> 147:30b64687e01f 8130 #define USART_CR2_ADDM7 0x00000010U /*!< 7-bit or 4-bit Address Detection */
<> 147:30b64687e01f 8131 #define USART_CR2_LBDL 0x00000020U /*!< LIN Break Detection Length */
<> 147:30b64687e01f 8132 #define USART_CR2_LBDIE 0x00000040U /*!< LIN Break Detection Interrupt Enable */
<> 147:30b64687e01f 8133 #define USART_CR2_LBCL 0x00000100U /*!< Last Bit Clock pulse */
<> 147:30b64687e01f 8134 #define USART_CR2_CPHA 0x00000200U /*!< Clock Phase */
<> 147:30b64687e01f 8135 #define USART_CR2_CPOL 0x00000400U /*!< Clock Polarity */
<> 147:30b64687e01f 8136 #define USART_CR2_CLKEN 0x00000800U /*!< Clock Enable */
<> 147:30b64687e01f 8137 #define USART_CR2_STOP 0x00003000U /*!< STOP[1:0] bits (STOP bits) */
<> 147:30b64687e01f 8138 #define USART_CR2_STOP_0 0x00001000U /*!< Bit 0 */
<> 147:30b64687e01f 8139 #define USART_CR2_STOP_1 0x00002000U /*!< Bit 1 */
<> 147:30b64687e01f 8140 #define USART_CR2_LINEN 0x00004000U /*!< LIN mode enable */
<> 147:30b64687e01f 8141 #define USART_CR2_SWAP 0x00008000U /*!< SWAP TX/RX pins */
<> 147:30b64687e01f 8142 #define USART_CR2_RXINV 0x00010000U /*!< RX pin active level inversion */
<> 147:30b64687e01f 8143 #define USART_CR2_TXINV 0x00020000U /*!< TX pin active level inversion */
<> 147:30b64687e01f 8144 #define USART_CR2_DATAINV 0x00040000U /*!< Binary data inversion */
<> 147:30b64687e01f 8145 #define USART_CR2_MSBFIRST 0x00080000U /*!< Most Significant Bit First */
<> 147:30b64687e01f 8146 #define USART_CR2_ABREN 0x00100000U /*!< Auto Baud-Rate Enable */
<> 147:30b64687e01f 8147 #define USART_CR2_ABRMODE 0x00600000U /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
<> 147:30b64687e01f 8148 #define USART_CR2_ABRMODE_0 0x00200000U /*!< Bit 0 */
<> 147:30b64687e01f 8149 #define USART_CR2_ABRMODE_1 0x00400000U /*!< Bit 1 */
<> 147:30b64687e01f 8150 #define USART_CR2_RTOEN 0x00800000U /*!< Receiver Time-Out enable */
<> 147:30b64687e01f 8151 #define USART_CR2_ADD 0xFF000000U /*!< Address of the USART node */
<> 147:30b64687e01f 8152
<> 147:30b64687e01f 8153 /****************** Bit definition for USART_CR3 register *******************/
<> 147:30b64687e01f 8154 #define USART_CR3_EIE 0x00000001U /*!< Error Interrupt Enable */
<> 147:30b64687e01f 8155 #define USART_CR3_IREN 0x00000002U /*!< IrDA mode Enable */
<> 147:30b64687e01f 8156 #define USART_CR3_IRLP 0x00000004U /*!< IrDA Low-Power */
<> 147:30b64687e01f 8157 #define USART_CR3_HDSEL 0x00000008U /*!< Half-Duplex Selection */
<> 147:30b64687e01f 8158 #define USART_CR3_NACK 0x00000010U /*!< SmartCard NACK enable */
<> 147:30b64687e01f 8159 #define USART_CR3_SCEN 0x00000020U /*!< SmartCard mode enable */
<> 147:30b64687e01f 8160 #define USART_CR3_DMAR 0x00000040U /*!< DMA Enable Receiver */
<> 147:30b64687e01f 8161 #define USART_CR3_DMAT 0x00000080U /*!< DMA Enable Transmitter */
<> 147:30b64687e01f 8162 #define USART_CR3_RTSE 0x00000100U /*!< RTS Enable */
<> 147:30b64687e01f 8163 #define USART_CR3_CTSE 0x00000200U /*!< CTS Enable */
<> 147:30b64687e01f 8164 #define USART_CR3_CTSIE 0x00000400U /*!< CTS Interrupt Enable */
<> 147:30b64687e01f 8165 #define USART_CR3_ONEBIT 0x00000800U /*!< One sample bit method enable */
<> 147:30b64687e01f 8166 #define USART_CR3_OVRDIS 0x00001000U /*!< Overrun Disable */
<> 147:30b64687e01f 8167 #define USART_CR3_DDRE 0x00002000U /*!< DMA Disable on Reception Error */
<> 147:30b64687e01f 8168 #define USART_CR3_DEM 0x00004000U /*!< Driver Enable Mode */
<> 147:30b64687e01f 8169 #define USART_CR3_DEP 0x00008000U /*!< Driver Enable Polarity Selection */
<> 147:30b64687e01f 8170 #define USART_CR3_SCARCNT 0x000E0000U /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
<> 147:30b64687e01f 8171 #define USART_CR3_SCARCNT_0 0x00020000U /*!< Bit 0 */
<> 147:30b64687e01f 8172 #define USART_CR3_SCARCNT_1 0x00040000U /*!< Bit 1 */
<> 147:30b64687e01f 8173 #define USART_CR3_SCARCNT_2 0x00080000U /*!< Bit 2 */
<> 147:30b64687e01f 8174
<> 147:30b64687e01f 8175
<> 147:30b64687e01f 8176 /****************** Bit definition for USART_BRR register *******************/
<> 147:30b64687e01f 8177 #define USART_BRR_DIV_FRACTION 0x000FU /*!< Fraction of USARTDIV */
<> 147:30b64687e01f 8178 #define USART_BRR_DIV_MANTISSA 0xFFF0U /*!< Mantissa of USARTDIV */
<> 147:30b64687e01f 8179
<> 147:30b64687e01f 8180 /****************** Bit definition for USART_GTPR register ******************/
<> 147:30b64687e01f 8181 #define USART_GTPR_PSC 0x00FFU /*!< PSC[7:0] bits (Prescaler value) */
<> 147:30b64687e01f 8182 #define USART_GTPR_GT 0xFF00U /*!< GT[7:0] bits (Guard time value) */
<> 147:30b64687e01f 8183
<> 147:30b64687e01f 8184
<> 147:30b64687e01f 8185 /******************* Bit definition for USART_RTOR register *****************/
<> 147:30b64687e01f 8186 #define USART_RTOR_RTO 0x00FFFFFFU /*!< Receiver Time Out Value */
<> 147:30b64687e01f 8187 #define USART_RTOR_BLEN 0xFF000000U /*!< Block Length */
<> 147:30b64687e01f 8188
<> 147:30b64687e01f 8189 /******************* Bit definition for USART_RQR register ******************/
<> 147:30b64687e01f 8190 #define USART_RQR_ABRRQ 0x0001U /*!< Auto-Baud Rate Request */
<> 147:30b64687e01f 8191 #define USART_RQR_SBKRQ 0x0002U /*!< Send Break Request */
<> 147:30b64687e01f 8192 #define USART_RQR_MMRQ 0x0004U /*!< Mute Mode Request */
<> 147:30b64687e01f 8193 #define USART_RQR_RXFRQ 0x0008U /*!< Receive Data flush Request */
<> 147:30b64687e01f 8194 #define USART_RQR_TXFRQ 0x0010U /*!< Transmit data flush Request */
<> 147:30b64687e01f 8195
<> 147:30b64687e01f 8196 /******************* Bit definition for USART_ISR register ******************/
<> 147:30b64687e01f 8197 #define USART_ISR_PE 0x00000001U /*!< Parity Error */
<> 147:30b64687e01f 8198 #define USART_ISR_FE 0x00000002U /*!< Framing Error */
<> 147:30b64687e01f 8199 #define USART_ISR_NE 0x00000004U /*!< Noise detected Flag */
<> 147:30b64687e01f 8200 #define USART_ISR_ORE 0x00000008U /*!< OverRun Error */
<> 147:30b64687e01f 8201 #define USART_ISR_IDLE 0x00000010U /*!< IDLE line detected */
<> 147:30b64687e01f 8202 #define USART_ISR_RXNE 0x00000020U /*!< Read Data Register Not Empty */
<> 147:30b64687e01f 8203 #define USART_ISR_TC 0x00000040U /*!< Transmission Complete */
<> 147:30b64687e01f 8204 #define USART_ISR_TXE 0x00000080U /*!< Transmit Data Register Empty */
<> 147:30b64687e01f 8205 #define USART_ISR_LBDF 0x00000100U /*!< LIN Break Detection Flag */
<> 147:30b64687e01f 8206 #define USART_ISR_CTSIF 0x00000200U /*!< CTS interrupt flag */
<> 147:30b64687e01f 8207 #define USART_ISR_CTS 0x00000400U /*!< CTS flag */
<> 147:30b64687e01f 8208 #define USART_ISR_RTOF 0x00000800U /*!< Receiver Time Out */
<> 147:30b64687e01f 8209 #define USART_ISR_EOBF 0x00001000U /*!< End Of Block Flag */
<> 147:30b64687e01f 8210 #define USART_ISR_ABRE 0x00004000U /*!< Auto-Baud Rate Error */
<> 147:30b64687e01f 8211 #define USART_ISR_ABRF 0x00008000U /*!< Auto-Baud Rate Flag */
<> 147:30b64687e01f 8212 #define USART_ISR_BUSY 0x00010000U /*!< Busy Flag */
<> 147:30b64687e01f 8213 #define USART_ISR_CMF 0x00020000U /*!< Character Match Flag */
<> 147:30b64687e01f 8214 #define USART_ISR_SBKF 0x00040000U /*!< Send Break Flag */
<> 147:30b64687e01f 8215 #define USART_ISR_RWU 0x00080000U /*!< Receive Wake Up from mute mode Flag */
<> 147:30b64687e01f 8216 #define USART_ISR_WUF 0x00100000U /*!< Wake Up from stop mode Flag */
<> 147:30b64687e01f 8217 #define USART_ISR_TEACK 0x00200000U /*!< Transmit Enable Acknowledge Flag */
<> 147:30b64687e01f 8218 #define USART_ISR_REACK 0x00400000U /*!< Receive Enable Acknowledge Flag */
<> 147:30b64687e01f 8219
<> 147:30b64687e01f 8220
<> 147:30b64687e01f 8221 /******************* Bit definition for USART_ICR register ******************/
<> 147:30b64687e01f 8222 #define USART_ICR_PECF 0x00000001U /*!< Parity Error Clear Flag */
<> 147:30b64687e01f 8223 #define USART_ICR_FECF 0x00000002U /*!< Framing Error Clear Flag */
<> 147:30b64687e01f 8224 #define USART_ICR_NCF 0x00000004U /*!< Noise detected Clear Flag */
<> 147:30b64687e01f 8225 #define USART_ICR_ORECF 0x00000008U /*!< OverRun Error Clear Flag */
<> 147:30b64687e01f 8226 #define USART_ICR_IDLECF 0x00000010U /*!< IDLE line detected Clear Flag */
<> 147:30b64687e01f 8227 #define USART_ICR_TCCF 0x00000040U /*!< Transmission Complete Clear Flag */
<> 147:30b64687e01f 8228 #define USART_ICR_LBDCF 0x00000100U /*!< LIN Break Detection Clear Flag */
<> 147:30b64687e01f 8229 #define USART_ICR_CTSCF 0x00000200U /*!< CTS Interrupt Clear Flag */
<> 147:30b64687e01f 8230 #define USART_ICR_RTOCF 0x00000800U /*!< Receiver Time Out Clear Flag */
<> 147:30b64687e01f 8231 #define USART_ICR_EOBCF 0x00001000U /*!< End Of Block Clear Flag */
<> 147:30b64687e01f 8232 #define USART_ICR_CMCF 0x00020000U /*!< Character Match Clear Flag */
<> 147:30b64687e01f 8233 #define USART_ICR_WUCF 0x00100000U /*!< Wake Up from stop mode Clear Flag */
<> 147:30b64687e01f 8234
<> 147:30b64687e01f 8235 /******************* Bit definition for USART_RDR register ******************/
<> 147:30b64687e01f 8236 #define USART_RDR_RDR 0x01FFU /*!< RDR[8:0] bits (Receive Data value) */
<> 147:30b64687e01f 8237
<> 147:30b64687e01f 8238 /******************* Bit definition for USART_TDR register ******************/
<> 147:30b64687e01f 8239 #define USART_TDR_TDR 0x01FFU /*!< TDR[8:0] bits (Transmit Data value) */
<> 147:30b64687e01f 8240
<> 147:30b64687e01f 8241 /******************************************************************************/
<> 147:30b64687e01f 8242 /* */
<> 147:30b64687e01f 8243 /* Window WATCHDOG */
<> 147:30b64687e01f 8244 /* */
<> 147:30b64687e01f 8245 /******************************************************************************/
<> 147:30b64687e01f 8246 /******************* Bit definition for WWDG_CR register ********************/
<> 147:30b64687e01f 8247 #define WWDG_CR_T 0x7FU /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
<> 147:30b64687e01f 8248 #define WWDG_CR_T_0 0x01U /*!<Bit 0 */
<> 147:30b64687e01f 8249 #define WWDG_CR_T_1 0x02U /*!<Bit 1 */
<> 147:30b64687e01f 8250 #define WWDG_CR_T_2 0x04U /*!<Bit 2 */
<> 147:30b64687e01f 8251 #define WWDG_CR_T_3 0x08U /*!<Bit 3 */
<> 147:30b64687e01f 8252 #define WWDG_CR_T_4 0x10U /*!<Bit 4 */
<> 147:30b64687e01f 8253 #define WWDG_CR_T_5 0x20U /*!<Bit 5 */
<> 147:30b64687e01f 8254 #define WWDG_CR_T_6 0x40U /*!<Bit 6 */
<> 147:30b64687e01f 8255
<> 147:30b64687e01f 8256
<> 147:30b64687e01f 8257 #define WWDG_CR_WDGA 0x80U /*!<Activation bit */
<> 147:30b64687e01f 8258
<> 147:30b64687e01f 8259 /******************* Bit definition for WWDG_CFR register *******************/
<> 147:30b64687e01f 8260 #define WWDG_CFR_W 0x007FU /*!<W[6:0] bits (7-bit window value) */
<> 147:30b64687e01f 8261 #define WWDG_CFR_W_0 0x0001U /*!<Bit 0 */
<> 147:30b64687e01f 8262 #define WWDG_CFR_W_1 0x0002U /*!<Bit 1 */
<> 147:30b64687e01f 8263 #define WWDG_CFR_W_2 0x0004U /*!<Bit 2 */
<> 147:30b64687e01f 8264 #define WWDG_CFR_W_3 0x0008U /*!<Bit 3 */
<> 147:30b64687e01f 8265 #define WWDG_CFR_W_4 0x0010U /*!<Bit 4 */
<> 147:30b64687e01f 8266 #define WWDG_CFR_W_5 0x0020U /*!<Bit 5 */
<> 147:30b64687e01f 8267 #define WWDG_CFR_W_6 0x0040U /*!<Bit 6 */
<> 147:30b64687e01f 8268
<> 147:30b64687e01f 8269
<> 147:30b64687e01f 8270 #define WWDG_CFR_WDGTB 0x0180U /*!<WDGTB[1:0] bits (Timer Base) */
<> 147:30b64687e01f 8271 #define WWDG_CFR_WDGTB_0 0x0080U /*!<Bit 0 */
<> 147:30b64687e01f 8272 #define WWDG_CFR_WDGTB_1 0x0100U /*!<Bit 1 */
<> 147:30b64687e01f 8273
<> 147:30b64687e01f 8274
<> 147:30b64687e01f 8275 #define WWDG_CFR_EWI 0x0200U /*!<Early Wakeup Interrupt */
<> 147:30b64687e01f 8276
<> 147:30b64687e01f 8277 /******************* Bit definition for WWDG_SR register ********************/
<> 147:30b64687e01f 8278 #define WWDG_SR_EWIF 0x01U /*!<Early Wakeup Interrupt Flag */
<> 147:30b64687e01f 8279
<> 147:30b64687e01f 8280 /******************************************************************************/
<> 147:30b64687e01f 8281 /* */
<> 147:30b64687e01f 8282 /* DBG */
<> 147:30b64687e01f 8283 /* */
<> 147:30b64687e01f 8284 /******************************************************************************/
<> 147:30b64687e01f 8285 /******************** Bit definition for DBGMCU_IDCODE register *************/
<> 147:30b64687e01f 8286 #define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
<> 147:30b64687e01f 8287 #define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
<> 147:30b64687e01f 8288
<> 147:30b64687e01f 8289 /******************** Bit definition for DBGMCU_CR register *****************/
<> 147:30b64687e01f 8290 #define DBGMCU_CR_DBG_SLEEP 0x00000001U
<> 147:30b64687e01f 8291 #define DBGMCU_CR_DBG_STOP 0x00000002U
<> 147:30b64687e01f 8292 #define DBGMCU_CR_DBG_STANDBY 0x00000004U
<> 147:30b64687e01f 8293 #define DBGMCU_CR_TRACE_IOEN 0x00000020U
<> 147:30b64687e01f 8294
<> 147:30b64687e01f 8295 #define DBGMCU_CR_TRACE_MODE 0x000000C0U
<> 147:30b64687e01f 8296 #define DBGMCU_CR_TRACE_MODE_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 8297 #define DBGMCU_CR_TRACE_MODE_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 8298
<> 147:30b64687e01f 8299 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
<> 147:30b64687e01f 8300 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
<> 147:30b64687e01f 8301 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
<> 147:30b64687e01f 8302 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
<> 147:30b64687e01f 8303 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
<> 147:30b64687e01f 8304 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
<> 147:30b64687e01f 8305 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
<> 147:30b64687e01f 8306 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
<> 147:30b64687e01f 8307 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
<> 147:30b64687e01f 8308 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
<> 147:30b64687e01f 8309 #define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
<> 147:30b64687e01f 8310 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
<> 147:30b64687e01f 8311 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
<> 147:30b64687e01f 8312 #define DBGMCU_APB1_FZ_DBG_CAN3_STOP 0x00002000U
<> 147:30b64687e01f 8313 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
<> 147:30b64687e01f 8314 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
<> 147:30b64687e01f 8315 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
<> 147:30b64687e01f 8316 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
<> 147:30b64687e01f 8317 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
<> 147:30b64687e01f 8318
<> 147:30b64687e01f 8319 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
<> 147:30b64687e01f 8320 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
<> 147:30b64687e01f 8321 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
<> 147:30b64687e01f 8322 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
<> 147:30b64687e01f 8323 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
<> 147:30b64687e01f 8324 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
<> 147:30b64687e01f 8325
<> 147:30b64687e01f 8326 /******************************************************************************/
<> 147:30b64687e01f 8327 /* */
<> 147:30b64687e01f 8328 /* Ethernet MAC Registers bits definitions */
<> 147:30b64687e01f 8329 /* */
<> 147:30b64687e01f 8330 /******************************************************************************/
<> 147:30b64687e01f 8331 /* Bit definition for Ethernet MAC Control Register register */
<> 147:30b64687e01f 8332 #define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
<> 147:30b64687e01f 8333 #define ETH_MACCR_JD 0x00400000U /* Jabber disable */
<> 147:30b64687e01f 8334 #define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
<> 147:30b64687e01f 8335 #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
<> 147:30b64687e01f 8336 #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
<> 147:30b64687e01f 8337 #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
<> 147:30b64687e01f 8338 #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
<> 147:30b64687e01f 8339 #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
<> 147:30b64687e01f 8340 #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
<> 147:30b64687e01f 8341 #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
<> 147:30b64687e01f 8342 #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
<> 147:30b64687e01f 8343 #define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
<> 147:30b64687e01f 8344 #define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
<> 147:30b64687e01f 8345 #define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
<> 147:30b64687e01f 8346 #define ETH_MACCR_LM 0x00001000U /* loopback mode */
<> 147:30b64687e01f 8347 #define ETH_MACCR_DM 0x00000800U /* Duplex mode */
<> 147:30b64687e01f 8348 #define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
<> 147:30b64687e01f 8349 #define ETH_MACCR_RD 0x00000200U /* Retry disable */
<> 147:30b64687e01f 8350 #define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
<> 147:30b64687e01f 8351 #define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
<> 147:30b64687e01f 8352 a transmission attempt during retries after a collision: 0 =< r <2^k */
<> 147:30b64687e01f 8353 #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
<> 147:30b64687e01f 8354 #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
<> 147:30b64687e01f 8355 #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
<> 147:30b64687e01f 8356 #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
<> 147:30b64687e01f 8357 #define ETH_MACCR_DC 0x00000010U /* Defferal check */
<> 147:30b64687e01f 8358 #define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
<> 147:30b64687e01f 8359 #define ETH_MACCR_RE 0x00000004U /* Receiver enable */
<> 147:30b64687e01f 8360
<> 147:30b64687e01f 8361 /* Bit definition for Ethernet MAC Frame Filter Register */
<> 147:30b64687e01f 8362 #define ETH_MACFFR_RA 0x80000000U /* Receive all */
<> 147:30b64687e01f 8363 #define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
<> 147:30b64687e01f 8364 #define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
<> 147:30b64687e01f 8365 #define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
<> 147:30b64687e01f 8366 #define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
<> 147:30b64687e01f 8367 #define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
<> 147:30b64687e01f 8368 #define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
<> 147:30b64687e01f 8369 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
<> 147:30b64687e01f 8370 #define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
<> 147:30b64687e01f 8371 #define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
<> 147:30b64687e01f 8372 #define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
<> 147:30b64687e01f 8373 #define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
<> 147:30b64687e01f 8374 #define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
<> 147:30b64687e01f 8375 #define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
<> 147:30b64687e01f 8376
<> 147:30b64687e01f 8377 /* Bit definition for Ethernet MAC Hash Table High Register */
<> 147:30b64687e01f 8378 #define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
<> 147:30b64687e01f 8379
<> 147:30b64687e01f 8380 /* Bit definition for Ethernet MAC Hash Table Low Register */
<> 147:30b64687e01f 8381 #define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
<> 147:30b64687e01f 8382
<> 147:30b64687e01f 8383 /* Bit definition for Ethernet MAC MII Address Register */
<> 147:30b64687e01f 8384 #define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
<> 147:30b64687e01f 8385 #define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
<> 147:30b64687e01f 8386 #define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
<> 147:30b64687e01f 8387 #define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
<> 147:30b64687e01f 8388 #define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
<> 147:30b64687e01f 8389 #define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
<> 147:30b64687e01f 8390 #define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
<> 147:30b64687e01f 8391 #define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
<> 147:30b64687e01f 8392 #define ETH_MACMIIAR_MW 0x00000002U /* MII write */
<> 147:30b64687e01f 8393 #define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
<> 147:30b64687e01f 8394
<> 147:30b64687e01f 8395 /* Bit definition for Ethernet MAC MII Data Register */
<> 147:30b64687e01f 8396 #define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
<> 147:30b64687e01f 8397
<> 147:30b64687e01f 8398 /* Bit definition for Ethernet MAC Flow Control Register */
<> 147:30b64687e01f 8399 #define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
<> 147:30b64687e01f 8400 #define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
<> 147:30b64687e01f 8401 #define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
<> 147:30b64687e01f 8402 #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
<> 147:30b64687e01f 8403 #define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
<> 147:30b64687e01f 8404 #define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
<> 147:30b64687e01f 8405 #define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
<> 147:30b64687e01f 8406 #define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
<> 147:30b64687e01f 8407 #define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
<> 147:30b64687e01f 8408 #define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
<> 147:30b64687e01f 8409 #define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
<> 147:30b64687e01f 8410
<> 147:30b64687e01f 8411 /* Bit definition for Ethernet MAC VLAN Tag Register */
<> 147:30b64687e01f 8412 #define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
<> 147:30b64687e01f 8413 #define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
<> 147:30b64687e01f 8414
<> 147:30b64687e01f 8415 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
<> 147:30b64687e01f 8416 #define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
<> 147:30b64687e01f 8417 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
<> 147:30b64687e01f 8418 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
<> 147:30b64687e01f 8419 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
<> 147:30b64687e01f 8420 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
<> 147:30b64687e01f 8421 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
<> 147:30b64687e01f 8422 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
<> 147:30b64687e01f 8423 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
<> 147:30b64687e01f 8424 RSVD - Filter1 Command - RSVD - Filter0 Command
<> 147:30b64687e01f 8425 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
<> 147:30b64687e01f 8426 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
<> 147:30b64687e01f 8427 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
<> 147:30b64687e01f 8428
<> 147:30b64687e01f 8429 /* Bit definition for Ethernet MAC PMT Control and Status Register */
<> 147:30b64687e01f 8430 #define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
<> 147:30b64687e01f 8431 #define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
<> 147:30b64687e01f 8432 #define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
<> 147:30b64687e01f 8433 #define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
<> 147:30b64687e01f 8434 #define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
<> 147:30b64687e01f 8435 #define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
<> 147:30b64687e01f 8436 #define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
<> 147:30b64687e01f 8437
<> 147:30b64687e01f 8438 /* Bit definition for Ethernet MAC Status Register */
<> 147:30b64687e01f 8439 #define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
<> 147:30b64687e01f 8440 #define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
<> 147:30b64687e01f 8441 #define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
<> 147:30b64687e01f 8442 #define ETH_MACSR_MMCS 0x00000010U /* MMC status */
<> 147:30b64687e01f 8443 #define ETH_MACSR_PMTS 0x00000008U /* PMT status */
<> 147:30b64687e01f 8444
<> 147:30b64687e01f 8445 /* Bit definition for Ethernet MAC Interrupt Mask Register */
<> 147:30b64687e01f 8446 #define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
<> 147:30b64687e01f 8447 #define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
<> 147:30b64687e01f 8448
<> 147:30b64687e01f 8449 /* Bit definition for Ethernet MAC Address0 High Register */
<> 147:30b64687e01f 8450 #define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
<> 147:30b64687e01f 8451
<> 147:30b64687e01f 8452 /* Bit definition for Ethernet MAC Address0 Low Register */
<> 147:30b64687e01f 8453 #define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
<> 147:30b64687e01f 8454
<> 147:30b64687e01f 8455 /* Bit definition for Ethernet MAC Address1 High Register */
<> 147:30b64687e01f 8456 #define ETH_MACA1HR_AE 0x80000000U /* Address enable */
<> 147:30b64687e01f 8457 #define ETH_MACA1HR_SA 0x40000000U /* Source address */
<> 147:30b64687e01f 8458 #define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
<> 147:30b64687e01f 8459 #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 147:30b64687e01f 8460 #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 147:30b64687e01f 8461 #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 147:30b64687e01f 8462 #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 147:30b64687e01f 8463 #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 147:30b64687e01f 8464 #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
<> 147:30b64687e01f 8465 #define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
<> 147:30b64687e01f 8466
<> 147:30b64687e01f 8467 /* Bit definition for Ethernet MAC Address1 Low Register */
<> 147:30b64687e01f 8468 #define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
<> 147:30b64687e01f 8469
<> 147:30b64687e01f 8470 /* Bit definition for Ethernet MAC Address2 High Register */
<> 147:30b64687e01f 8471 #define ETH_MACA2HR_AE 0x80000000U /* Address enable */
<> 147:30b64687e01f 8472 #define ETH_MACA2HR_SA 0x40000000U /* Source address */
<> 147:30b64687e01f 8473 #define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
<> 147:30b64687e01f 8474 #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 147:30b64687e01f 8475 #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 147:30b64687e01f 8476 #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 147:30b64687e01f 8477 #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 147:30b64687e01f 8478 #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 147:30b64687e01f 8479 #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 147:30b64687e01f 8480 #define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
<> 147:30b64687e01f 8481
<> 147:30b64687e01f 8482 /* Bit definition for Ethernet MAC Address2 Low Register */
<> 147:30b64687e01f 8483 #define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
<> 147:30b64687e01f 8484
<> 147:30b64687e01f 8485 /* Bit definition for Ethernet MAC Address3 High Register */
<> 147:30b64687e01f 8486 #define ETH_MACA3HR_AE 0x80000000U /* Address enable */
<> 147:30b64687e01f 8487 #define ETH_MACA3HR_SA 0x40000000U /* Source address */
<> 147:30b64687e01f 8488 #define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
<> 147:30b64687e01f 8489 #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
<> 147:30b64687e01f 8490 #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
<> 147:30b64687e01f 8491 #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
<> 147:30b64687e01f 8492 #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
<> 147:30b64687e01f 8493 #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
<> 147:30b64687e01f 8494 #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
<> 147:30b64687e01f 8495 #define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
<> 147:30b64687e01f 8496
<> 147:30b64687e01f 8497 /* Bit definition for Ethernet MAC Address3 Low Register */
<> 147:30b64687e01f 8498 #define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
<> 147:30b64687e01f 8499
<> 147:30b64687e01f 8500 /******************************************************************************/
<> 147:30b64687e01f 8501 /* Ethernet MMC Registers bits definition */
<> 147:30b64687e01f 8502 /******************************************************************************/
<> 147:30b64687e01f 8503
<> 147:30b64687e01f 8504 /* Bit definition for Ethernet MMC Contol Register */
<> 147:30b64687e01f 8505 #define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
<> 147:30b64687e01f 8506 #define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
<> 147:30b64687e01f 8507 #define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
<> 147:30b64687e01f 8508 #define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
<> 147:30b64687e01f 8509 #define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
<> 147:30b64687e01f 8510 #define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
<> 147:30b64687e01f 8511
<> 147:30b64687e01f 8512 /* Bit definition for Ethernet MMC Receive Interrupt Register */
<> 147:30b64687e01f 8513 #define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
<> 147:30b64687e01f 8514 #define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
<> 147:30b64687e01f 8515 #define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
<> 147:30b64687e01f 8516
<> 147:30b64687e01f 8517 /* Bit definition for Ethernet MMC Transmit Interrupt Register */
<> 147:30b64687e01f 8518 #define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
<> 147:30b64687e01f 8519 #define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
<> 147:30b64687e01f 8520 #define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
<> 147:30b64687e01f 8521
<> 147:30b64687e01f 8522 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
<> 147:30b64687e01f 8523 #define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
<> 147:30b64687e01f 8524 #define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
<> 147:30b64687e01f 8525 #define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
<> 147:30b64687e01f 8526
<> 147:30b64687e01f 8527 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
<> 147:30b64687e01f 8528 #define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
<> 147:30b64687e01f 8529 #define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
<> 147:30b64687e01f 8530 #define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
<> 147:30b64687e01f 8531
<> 147:30b64687e01f 8532 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
<> 147:30b64687e01f 8533 #define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
<> 147:30b64687e01f 8534
<> 147:30b64687e01f 8535 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
<> 147:30b64687e01f 8536 #define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
<> 147:30b64687e01f 8537
<> 147:30b64687e01f 8538 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
<> 147:30b64687e01f 8539 #define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
<> 147:30b64687e01f 8540
<> 147:30b64687e01f 8541 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
<> 147:30b64687e01f 8542 #define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
<> 147:30b64687e01f 8543
<> 147:30b64687e01f 8544 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
<> 147:30b64687e01f 8545 #define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
<> 147:30b64687e01f 8546
<> 147:30b64687e01f 8547 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
<> 147:30b64687e01f 8548 #define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
<> 147:30b64687e01f 8549
<> 147:30b64687e01f 8550 /******************************************************************************/
<> 147:30b64687e01f 8551 /* Ethernet PTP Registers bits definition */
<> 147:30b64687e01f 8552 /******************************************************************************/
<> 147:30b64687e01f 8553
<> 147:30b64687e01f 8554 /* Bit definition for Ethernet PTP Time Stamp Contol Register */
<> 147:30b64687e01f 8555 #define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
<> 147:30b64687e01f 8556 #define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
<> 147:30b64687e01f 8557 #define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
<> 147:30b64687e01f 8558 #define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
<> 147:30b64687e01f 8559 #define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
<> 147:30b64687e01f 8560 #define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
<> 147:30b64687e01f 8561 #define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
<> 147:30b64687e01f 8562 #define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
<> 147:30b64687e01f 8563 #define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
<> 147:30b64687e01f 8564
<> 147:30b64687e01f 8565 #define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
<> 147:30b64687e01f 8566 #define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
<> 147:30b64687e01f 8567 #define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
<> 147:30b64687e01f 8568 #define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
<> 147:30b64687e01f 8569 #define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
<> 147:30b64687e01f 8570 #define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
<> 147:30b64687e01f 8571
<> 147:30b64687e01f 8572 /* Bit definition for Ethernet PTP Sub-Second Increment Register */
<> 147:30b64687e01f 8573 #define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
<> 147:30b64687e01f 8574
<> 147:30b64687e01f 8575 /* Bit definition for Ethernet PTP Time Stamp High Register */
<> 147:30b64687e01f 8576 #define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
<> 147:30b64687e01f 8577
<> 147:30b64687e01f 8578 /* Bit definition for Ethernet PTP Time Stamp Low Register */
<> 147:30b64687e01f 8579 #define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
<> 147:30b64687e01f 8580 #define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
<> 147:30b64687e01f 8581
<> 147:30b64687e01f 8582 /* Bit definition for Ethernet PTP Time Stamp High Update Register */
<> 147:30b64687e01f 8583 #define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
<> 147:30b64687e01f 8584
<> 147:30b64687e01f 8585 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */
<> 147:30b64687e01f 8586 #define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
<> 147:30b64687e01f 8587 #define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
<> 147:30b64687e01f 8588
<> 147:30b64687e01f 8589 /* Bit definition for Ethernet PTP Time Stamp Addend Register */
<> 147:30b64687e01f 8590 #define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
<> 147:30b64687e01f 8591
<> 147:30b64687e01f 8592 /* Bit definition for Ethernet PTP Target Time High Register */
<> 147:30b64687e01f 8593 #define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
<> 147:30b64687e01f 8594
<> 147:30b64687e01f 8595 /* Bit definition for Ethernet PTP Target Time Low Register */
<> 147:30b64687e01f 8596 #define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
<> 147:30b64687e01f 8597
<> 147:30b64687e01f 8598 /* Bit definition for Ethernet PTP Time Stamp Status Register */
<> 147:30b64687e01f 8599 #define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
<> 147:30b64687e01f 8600 #define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
<> 147:30b64687e01f 8601
<> 147:30b64687e01f 8602 /******************************************************************************/
<> 147:30b64687e01f 8603 /* Ethernet DMA Registers bits definition */
<> 147:30b64687e01f 8604 /******************************************************************************/
<> 147:30b64687e01f 8605
<> 147:30b64687e01f 8606 /* Bit definition for Ethernet DMA Bus Mode Register */
<> 147:30b64687e01f 8607 #define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
<> 147:30b64687e01f 8608 #define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
<> 147:30b64687e01f 8609 #define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
<> 147:30b64687e01f 8610 #define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
<> 147:30b64687e01f 8611 #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 147:30b64687e01f 8612 #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 147:30b64687e01f 8613 #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 147:30b64687e01f 8614 #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 147:30b64687e01f 8615 #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 147:30b64687e01f 8616 #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 147:30b64687e01f 8617 #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 147:30b64687e01f 8618 #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 147:30b64687e01f 8619 #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 147:30b64687e01f 8620 #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 147:30b64687e01f 8621 #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 147:30b64687e01f 8622 #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 147:30b64687e01f 8623 #define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
<> 147:30b64687e01f 8624 #define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
<> 147:30b64687e01f 8625 #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
<> 147:30b64687e01f 8626 #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
<> 147:30b64687e01f 8627 #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
<> 147:30b64687e01f 8628 #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
<> 147:30b64687e01f 8629 #define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
<> 147:30b64687e01f 8630 #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 147:30b64687e01f 8631 #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 147:30b64687e01f 8632 #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 147:30b64687e01f 8633 #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 147:30b64687e01f 8634 #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 147:30b64687e01f 8635 #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 147:30b64687e01f 8636 #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 147:30b64687e01f 8637 #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 147:30b64687e01f 8638 #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 147:30b64687e01f 8639 #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 147:30b64687e01f 8640 #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 147:30b64687e01f 8641 #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 147:30b64687e01f 8642 #define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
<> 147:30b64687e01f 8643 #define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
<> 147:30b64687e01f 8644 #define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
<> 147:30b64687e01f 8645 #define ETH_DMABMR_SR 0x00000001U /* Software reset */
<> 147:30b64687e01f 8646
<> 147:30b64687e01f 8647 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */
<> 147:30b64687e01f 8648 #define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
<> 147:30b64687e01f 8649
<> 147:30b64687e01f 8650 /* Bit definition for Ethernet DMA Receive Poll Demand Register */
<> 147:30b64687e01f 8651 #define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
<> 147:30b64687e01f 8652
<> 147:30b64687e01f 8653 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
<> 147:30b64687e01f 8654 #define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
<> 147:30b64687e01f 8655
<> 147:30b64687e01f 8656 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
<> 147:30b64687e01f 8657 #define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
<> 147:30b64687e01f 8658
<> 147:30b64687e01f 8659 /* Bit definition for Ethernet DMA Status Register */
<> 147:30b64687e01f 8660 #define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
<> 147:30b64687e01f 8661 #define ETH_DMASR_PMTS 0x10000000U /* PMT status */
<> 147:30b64687e01f 8662 #define ETH_DMASR_MMCS 0x08000000U /* MMC status */
<> 147:30b64687e01f 8663 #define ETH_DMASR_EBS 0x03800000U /* Error bits status */
<> 147:30b64687e01f 8664 /* combination with EBS[2:0] for GetFlagStatus function */
<> 147:30b64687e01f 8665 #define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
<> 147:30b64687e01f 8666 #define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
<> 147:30b64687e01f 8667 #define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
<> 147:30b64687e01f 8668 #define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
<> 147:30b64687e01f 8669 #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
<> 147:30b64687e01f 8670 #define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
<> 147:30b64687e01f 8671 #define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
<> 147:30b64687e01f 8672 #define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
<> 147:30b64687e01f 8673 #define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
<> 147:30b64687e01f 8674 #define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
<> 147:30b64687e01f 8675 #define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
<> 147:30b64687e01f 8676 #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
<> 147:30b64687e01f 8677 #define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
<> 147:30b64687e01f 8678 #define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
<> 147:30b64687e01f 8679 #define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
<> 147:30b64687e01f 8680 #define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
<> 147:30b64687e01f 8681 #define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
<> 147:30b64687e01f 8682 #define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
<> 147:30b64687e01f 8683 #define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
<> 147:30b64687e01f 8684 #define ETH_DMASR_ERS 0x00004000U /* Early receive status */
<> 147:30b64687e01f 8685 #define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
<> 147:30b64687e01f 8686 #define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
<> 147:30b64687e01f 8687 #define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
<> 147:30b64687e01f 8688 #define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
<> 147:30b64687e01f 8689 #define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
<> 147:30b64687e01f 8690 #define ETH_DMASR_RS 0x00000040U /* Receive status */
<> 147:30b64687e01f 8691 #define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
<> 147:30b64687e01f 8692 #define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
<> 147:30b64687e01f 8693 #define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
<> 147:30b64687e01f 8694 #define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
<> 147:30b64687e01f 8695 #define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
<> 147:30b64687e01f 8696 #define ETH_DMASR_TS 0x00000001U /* Transmit status */
<> 147:30b64687e01f 8697
<> 147:30b64687e01f 8698 /* Bit definition for Ethernet DMA Operation Mode Register */
<> 147:30b64687e01f 8699 #define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
<> 147:30b64687e01f 8700 #define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
<> 147:30b64687e01f 8701 #define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
<> 147:30b64687e01f 8702 #define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
<> 147:30b64687e01f 8703 #define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
<> 147:30b64687e01f 8704 #define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
<> 147:30b64687e01f 8705 #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 147:30b64687e01f 8706 #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 147:30b64687e01f 8707 #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 147:30b64687e01f 8708 #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 147:30b64687e01f 8709 #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 147:30b64687e01f 8710 #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 147:30b64687e01f 8711 #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 147:30b64687e01f 8712 #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 147:30b64687e01f 8713 #define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
<> 147:30b64687e01f 8714 #define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
<> 147:30b64687e01f 8715 #define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
<> 147:30b64687e01f 8716 #define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
<> 147:30b64687e01f 8717 #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
<> 147:30b64687e01f 8718 #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
<> 147:30b64687e01f 8719 #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
<> 147:30b64687e01f 8720 #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
<> 147:30b64687e01f 8721 #define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
<> 147:30b64687e01f 8722 #define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
<> 147:30b64687e01f 8723
<> 147:30b64687e01f 8724 /* Bit definition for Ethernet DMA Interrupt Enable Register */
<> 147:30b64687e01f 8725 #define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
<> 147:30b64687e01f 8726 #define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
<> 147:30b64687e01f 8727 #define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
<> 147:30b64687e01f 8728 #define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
<> 147:30b64687e01f 8729 #define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
<> 147:30b64687e01f 8730 #define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
<> 147:30b64687e01f 8731 #define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
<> 147:30b64687e01f 8732 #define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
<> 147:30b64687e01f 8733 #define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
<> 147:30b64687e01f 8734 #define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
<> 147:30b64687e01f 8735 #define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
<> 147:30b64687e01f 8736 #define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
<> 147:30b64687e01f 8737 #define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
<> 147:30b64687e01f 8738 #define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
<> 147:30b64687e01f 8739 #define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
<> 147:30b64687e01f 8740
<> 147:30b64687e01f 8741 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
<> 147:30b64687e01f 8742 #define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
<> 147:30b64687e01f 8743 #define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
<> 147:30b64687e01f 8744 #define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
<> 147:30b64687e01f 8745 #define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
<> 147:30b64687e01f 8746
<> 147:30b64687e01f 8747 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
<> 147:30b64687e01f 8748 #define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
<> 147:30b64687e01f 8749
<> 147:30b64687e01f 8750 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
<> 147:30b64687e01f 8751 #define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
<> 147:30b64687e01f 8752
<> 147:30b64687e01f 8753 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
<> 147:30b64687e01f 8754 #define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
<> 147:30b64687e01f 8755
<> 147:30b64687e01f 8756 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
<> 147:30b64687e01f 8757 #define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
<> 147:30b64687e01f 8758
<> 147:30b64687e01f 8759 /******************************************************************************/
<> 147:30b64687e01f 8760 /* */
<> 147:30b64687e01f 8761 /* USB_OTG */
<> 147:30b64687e01f 8762 /* */
<> 147:30b64687e01f 8763 /******************************************************************************/
<> 147:30b64687e01f 8764 /******************** Bit definition for USB_OTG_GOTGCTL register ********************/
<> 147:30b64687e01f 8765 #define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /*!< Session request success */
<> 147:30b64687e01f 8766 #define USB_OTG_GOTGCTL_SRQ 0x00000002U /*!< Session request */
<> 147:30b64687e01f 8767 #define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /*!< VBUS valid override enable */
<> 147:30b64687e01f 8768 #define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /*!< VBUS valid override value */
<> 147:30b64687e01f 8769 #define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /*!< A-peripheral session valid override enable */
<> 147:30b64687e01f 8770 #define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /*!< A-peripheral session valid override value */
<> 147:30b64687e01f 8771 #define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /*!< B-peripheral session valid override enable */
<> 147:30b64687e01f 8772 #define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /*!< B-peripheral session valid override value */
<> 147:30b64687e01f 8773 #define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /*!< Host set HNP enable */
<> 147:30b64687e01f 8774 #define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /*!< HNP request */
<> 147:30b64687e01f 8775 #define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /*!< Host set HNP enable */
<> 147:30b64687e01f 8776 #define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /*!< Device HNP enabled */
<> 147:30b64687e01f 8777 #define USB_OTG_GOTGCTL_EHEN 0x00001000U /*!< Embedded host enable */
<> 147:30b64687e01f 8778 #define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /*!< Connector ID status */
<> 147:30b64687e01f 8779 #define USB_OTG_GOTGCTL_DBCT 0x00020000U /*!< Long/short debounce time */
<> 147:30b64687e01f 8780 #define USB_OTG_GOTGCTL_ASVLD 0x00040000U /*!< A-session valid */
<> 147:30b64687e01f 8781 #define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /*!< B-session valid */
<> 147:30b64687e01f 8782 #define USB_OTG_GOTGCTL_OTGVER 0x00100000U /*!< OTG version */
<> 147:30b64687e01f 8783
<> 147:30b64687e01f 8784 /******************** Bit definition for USB_OTG_HCFG register ********************/
<> 147:30b64687e01f 8785 #define USB_OTG_HCFG_FSLSPCS 0x00000003U /*!< FS/LS PHY clock select */
<> 147:30b64687e01f 8786 #define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 8787 #define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 8788 #define USB_OTG_HCFG_FSLSS 0x00000004U /*!< FS- and LS-only support */
<> 147:30b64687e01f 8789
<> 147:30b64687e01f 8790 /******************** Bit definition for USB_OTG_DCFG register ********************/
<> 147:30b64687e01f 8791 #define USB_OTG_DCFG_DSPD 0x00000003U /*!< Device speed */
<> 147:30b64687e01f 8792 #define USB_OTG_DCFG_DSPD_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 8793 #define USB_OTG_DCFG_DSPD_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 8794 #define USB_OTG_DCFG_NZLSOHSK 0x00000004U /*!< Nonzero-length status OUT handshake */
<> 147:30b64687e01f 8795
<> 147:30b64687e01f 8796 #define USB_OTG_DCFG_DAD 0x000007F0U /*!< Device address */
<> 147:30b64687e01f 8797 #define USB_OTG_DCFG_DAD_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 8798 #define USB_OTG_DCFG_DAD_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 8799 #define USB_OTG_DCFG_DAD_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 8800 #define USB_OTG_DCFG_DAD_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 8801 #define USB_OTG_DCFG_DAD_4 0x00000100U /*!<Bit 4 */
<> 147:30b64687e01f 8802 #define USB_OTG_DCFG_DAD_5 0x00000200U /*!<Bit 5 */
<> 147:30b64687e01f 8803 #define USB_OTG_DCFG_DAD_6 0x00000400U /*!<Bit 6 */
<> 147:30b64687e01f 8804
<> 147:30b64687e01f 8805 #define USB_OTG_DCFG_PFIVL 0x00001800U /*!< Periodic (micro)frame interval */
<> 147:30b64687e01f 8806 #define USB_OTG_DCFG_PFIVL_0 0x00000800U /*!<Bit 0 */
<> 147:30b64687e01f 8807 #define USB_OTG_DCFG_PFIVL_1 0x00001000U /*!<Bit 1 */
<> 147:30b64687e01f 8808
<> 147:30b64687e01f 8809 #define USB_OTG_DCFG_PERSCHIVL 0x03000000U /*!< Periodic scheduling interval */
<> 147:30b64687e01f 8810 #define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 8811 #define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 8812
<> 147:30b64687e01f 8813 /******************** Bit definition for USB_OTG_PCGCR register ********************/
<> 147:30b64687e01f 8814 #define USB_OTG_PCGCR_STPPCLK 0x00000001U /*!< Stop PHY clock */
<> 147:30b64687e01f 8815 #define USB_OTG_PCGCR_GATEHCLK 0x00000002U /*!< Gate HCLK */
<> 147:30b64687e01f 8816 #define USB_OTG_PCGCR_PHYSUSP 0x00000010U /*!< PHY suspended */
<> 147:30b64687e01f 8817
<> 147:30b64687e01f 8818 /******************** Bit definition for USB_OTG_GOTGINT register ********************/
<> 147:30b64687e01f 8819 #define USB_OTG_GOTGINT_SEDET 0x00000004U /*!< Session end detected */
<> 147:30b64687e01f 8820 #define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /*!< Session request success status change */
<> 147:30b64687e01f 8821 #define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /*!< Host negotiation success status change */
<> 147:30b64687e01f 8822 #define USB_OTG_GOTGINT_HNGDET 0x00020000U /*!< Host negotiation detected */
<> 147:30b64687e01f 8823 #define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /*!< A-device timeout change */
<> 147:30b64687e01f 8824 #define USB_OTG_GOTGINT_DBCDNE 0x00080000U /*!< Debounce done */
<> 147:30b64687e01f 8825 #define USB_OTG_GOTGINT_IDCHNG 0x00100000U /*!< Change in ID pin input value */
<> 147:30b64687e01f 8826
<> 147:30b64687e01f 8827 /******************** Bit definition for USB_OTG_DCTL register ********************/
<> 147:30b64687e01f 8828 #define USB_OTG_DCTL_RWUSIG 0x00000001U /*!< Remote wakeup signaling */
<> 147:30b64687e01f 8829 #define USB_OTG_DCTL_SDIS 0x00000002U /*!< Soft disconnect */
<> 147:30b64687e01f 8830 #define USB_OTG_DCTL_GINSTS 0x00000004U /*!< Global IN NAK status */
<> 147:30b64687e01f 8831 #define USB_OTG_DCTL_GONSTS 0x00000008U /*!< Global OUT NAK status */
<> 147:30b64687e01f 8832
<> 147:30b64687e01f 8833 #define USB_OTG_DCTL_TCTL 0x00000070U /*!< Test control */
<> 147:30b64687e01f 8834 #define USB_OTG_DCTL_TCTL_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 8835 #define USB_OTG_DCTL_TCTL_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 8836 #define USB_OTG_DCTL_TCTL_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 8837 #define USB_OTG_DCTL_SGINAK 0x00000080U /*!< Set global IN NAK */
<> 147:30b64687e01f 8838 #define USB_OTG_DCTL_CGINAK 0x00000100U /*!< Clear global IN NAK */
<> 147:30b64687e01f 8839 #define USB_OTG_DCTL_SGONAK 0x00000200U /*!< Set global OUT NAK */
<> 147:30b64687e01f 8840 #define USB_OTG_DCTL_CGONAK 0x00000400U /*!< Clear global OUT NAK */
<> 147:30b64687e01f 8841 #define USB_OTG_DCTL_POPRGDNE 0x00000800U /*!< Power-on programming done */
<> 147:30b64687e01f 8842
<> 147:30b64687e01f 8843 /******************** Bit definition for USB_OTG_HFIR register ********************/
<> 147:30b64687e01f 8844 #define USB_OTG_HFIR_FRIVL 0x0000FFFFU /*!< Frame interval */
<> 147:30b64687e01f 8845
<> 147:30b64687e01f 8846 /******************** Bit definition for USB_OTG_HFNUM register ********************/
<> 147:30b64687e01f 8847 #define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /*!< Frame number */
<> 147:30b64687e01f 8848 #define USB_OTG_HFNUM_FTREM 0xFFFF0000U /*!< Frame time remaining */
<> 147:30b64687e01f 8849
<> 147:30b64687e01f 8850 /******************** Bit definition for USB_OTG_DSTS register ********************/
<> 147:30b64687e01f 8851 #define USB_OTG_DSTS_SUSPSTS 0x00000001U /*!< Suspend status */
<> 147:30b64687e01f 8852
<> 147:30b64687e01f 8853 #define USB_OTG_DSTS_ENUMSPD 0x00000006U /*!< Enumerated speed */
<> 147:30b64687e01f 8854 #define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /*!<Bit 0 */
<> 147:30b64687e01f 8855 #define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /*!<Bit 1 */
<> 147:30b64687e01f 8856 #define USB_OTG_DSTS_EERR 0x00000008U /*!< Erratic error */
<> 147:30b64687e01f 8857 #define USB_OTG_DSTS_FNSOF 0x003FFF00U /*!< Frame number of the received SOF */
<> 147:30b64687e01f 8858
<> 147:30b64687e01f 8859 /******************** Bit definition for USB_OTG_GAHBCFG register ********************/
<> 147:30b64687e01f 8860 #define USB_OTG_GAHBCFG_GINT 0x00000001U /*!< Global interrupt mask */
<> 147:30b64687e01f 8861 #define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /*!< Burst length/type */
<> 147:30b64687e01f 8862 #define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /*!<Bit 0 */
<> 147:30b64687e01f 8863 #define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /*!<Bit 1 */
<> 147:30b64687e01f 8864 #define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /*!<Bit 2 */
<> 147:30b64687e01f 8865 #define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /*!<Bit 3 */
<> 147:30b64687e01f 8866 #define USB_OTG_GAHBCFG_DMAEN 0x00000020U /*!< DMA enable */
<> 147:30b64687e01f 8867 #define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /*!< TxFIFO empty level */
<> 147:30b64687e01f 8868 #define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /*!< Periodic TxFIFO empty level */
<> 147:30b64687e01f 8869
<> 147:30b64687e01f 8870 /******************** Bit definition for USB_OTG_GUSBCFG register ********************/
<> 147:30b64687e01f 8871 #define USB_OTG_GUSBCFG_TOCAL 0x00000007U /*!< FS timeout calibration */
<> 147:30b64687e01f 8872 #define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 8873 #define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 8874 #define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 8875 #define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
<> 147:30b64687e01f 8876 #define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /*!< SRP-capable */
<> 147:30b64687e01f 8877 #define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /*!< HNP-capable */
<> 147:30b64687e01f 8878 #define USB_OTG_GUSBCFG_TRDT 0x00003C00U /*!< USB turnaround time */
<> 147:30b64687e01f 8879 #define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 8880 #define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 8881 #define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /*!<Bit 2 */
<> 147:30b64687e01f 8882 #define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /*!<Bit 3 */
<> 147:30b64687e01f 8883 #define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /*!< PHY Low-power clock select */
<> 147:30b64687e01f 8884 #define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /*!< ULPI FS/LS select */
<> 147:30b64687e01f 8885 #define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /*!< ULPI Auto-resume */
<> 147:30b64687e01f 8886 #define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /*!< ULPI Clock SuspendM */
<> 147:30b64687e01f 8887 #define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /*!< ULPI External VBUS Drive */
<> 147:30b64687e01f 8888 #define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /*!< ULPI external VBUS indicator */
<> 147:30b64687e01f 8889 #define USB_OTG_GUSBCFG_TSDPS 0x00400000U /*!< TermSel DLine pulsing selection */
<> 147:30b64687e01f 8890 #define USB_OTG_GUSBCFG_PCCI 0x00800000U /*!< Indicator complement */
<> 147:30b64687e01f 8891 #define USB_OTG_GUSBCFG_PTCI 0x01000000U /*!< Indicator pass through */
<> 147:30b64687e01f 8892 #define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /*!< ULPI interface protect disable */
<> 147:30b64687e01f 8893 #define USB_OTG_GUSBCFG_FHMOD 0x20000000U /*!< Forced host mode */
<> 147:30b64687e01f 8894 #define USB_OTG_GUSBCFG_FDMOD 0x40000000U /*!< Forced peripheral mode */
<> 147:30b64687e01f 8895 #define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /*!< Corrupt Tx packet */
<> 147:30b64687e01f 8896
<> 147:30b64687e01f 8897 /******************** Bit definition for USB_OTG_GRSTCTL register ********************/
<> 147:30b64687e01f 8898 #define USB_OTG_GRSTCTL_CSRST 0x00000001U /*!< Core soft reset */
<> 147:30b64687e01f 8899 #define USB_OTG_GRSTCTL_HSRST 0x00000002U /*!< HCLK soft reset */
<> 147:30b64687e01f 8900 #define USB_OTG_GRSTCTL_FCRST 0x00000004U /*!< Host frame counter reset */
<> 147:30b64687e01f 8901 #define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /*!< RxFIFO flush */
<> 147:30b64687e01f 8902 #define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /*!< TxFIFO flush */
<> 147:30b64687e01f 8903 #define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /*!< TxFIFO number */
<> 147:30b64687e01f 8904 #define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 8905 #define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 8906 #define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /*!<Bit 2 */
<> 147:30b64687e01f 8907 #define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /*!<Bit 3 */
<> 147:30b64687e01f 8908 #define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /*!<Bit 4 */
<> 147:30b64687e01f 8909 #define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /*!< DMA request signal */
<> 147:30b64687e01f 8910 #define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /*!< AHB master idle */
<> 147:30b64687e01f 8911
<> 147:30b64687e01f 8912 /******************** Bit definition for USB_OTG_DIEPMSK register ********************/
<> 147:30b64687e01f 8913 #define USB_OTG_DIEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 147:30b64687e01f 8914 #define USB_OTG_DIEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 147:30b64687e01f 8915 #define USB_OTG_DIEPMSK_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 147:30b64687e01f 8916 #define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 147:30b64687e01f 8917 #define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 147:30b64687e01f 8918 #define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 147:30b64687e01f 8919 #define USB_OTG_DIEPMSK_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 147:30b64687e01f 8920 #define USB_OTG_DIEPMSK_BIM 0x00000200U /*!< BNA interrupt mask */
<> 147:30b64687e01f 8921
<> 147:30b64687e01f 8922 /******************** Bit definition for USB_OTG_HPTXSTS register ********************/
<> 147:30b64687e01f 8923 #define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /*!< Periodic transmit data FIFO space available */
<> 147:30b64687e01f 8924 #define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /*!< Periodic transmit request queue space available */
<> 147:30b64687e01f 8925 #define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 8926 #define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 8927 #define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 8928 #define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 8929 #define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /*!<Bit 4 */
<> 147:30b64687e01f 8930 #define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /*!<Bit 5 */
<> 147:30b64687e01f 8931 #define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /*!<Bit 6 */
<> 147:30b64687e01f 8932 #define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /*!<Bit 7 */
<> 147:30b64687e01f 8933
<> 147:30b64687e01f 8934 #define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /*!< Top of the periodic transmit request queue */
<> 147:30b64687e01f 8935 #define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 8936 #define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 8937 #define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 8938 #define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 8939 #define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 147:30b64687e01f 8940 #define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 147:30b64687e01f 8941 #define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 147:30b64687e01f 8942 #define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /*!<Bit 7 */
<> 147:30b64687e01f 8943
<> 147:30b64687e01f 8944 /******************** Bit definition for USB_OTG_HAINT register ********************/
<> 147:30b64687e01f 8945 #define USB_OTG_HAINT_HAINT 0x0000FFFFU /*!< Channel interrupts */
<> 147:30b64687e01f 8946
<> 147:30b64687e01f 8947 /******************** Bit definition for USB_OTG_DOEPMSK register ********************/
<> 147:30b64687e01f 8948 #define USB_OTG_DOEPMSK_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 147:30b64687e01f 8949 #define USB_OTG_DOEPMSK_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 147:30b64687e01f 8950 #define USB_OTG_DOEPMSK_STUPM 0x00000008U /*!< SETUP phase done mask */
<> 147:30b64687e01f 8951 #define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /*!< OUT token received when endpoint disabled mask */
<> 147:30b64687e01f 8952 #define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /*!< Status Phase Received mask */
<> 147:30b64687e01f 8953 #define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received mask */
<> 147:30b64687e01f 8954 #define USB_OTG_DOEPMSK_OPEM 0x00000100U /*!< OUT packet error mask */
<> 147:30b64687e01f 8955 #define USB_OTG_DOEPMSK_BOIM 0x00000200U /*!< BNA interrupt mask */
<> 147:30b64687e01f 8956
<> 147:30b64687e01f 8957 /******************** Bit definition for USB_OTG_GINTSTS register ********************/
<> 147:30b64687e01f 8958 #define USB_OTG_GINTSTS_CMOD 0x00000001U /*!< Current mode of operation */
<> 147:30b64687e01f 8959 #define USB_OTG_GINTSTS_MMIS 0x00000002U /*!< Mode mismatch interrupt */
<> 147:30b64687e01f 8960 #define USB_OTG_GINTSTS_OTGINT 0x00000004U /*!< OTG interrupt */
<> 147:30b64687e01f 8961 #define USB_OTG_GINTSTS_SOF 0x00000008U /*!< Start of frame */
<> 147:30b64687e01f 8962 #define USB_OTG_GINTSTS_RXFLVL 0x00000010U /*!< RxFIFO nonempty */
<> 147:30b64687e01f 8963 #define USB_OTG_GINTSTS_NPTXFE 0x00000020U /*!< Nonperiodic TxFIFO empty */
<> 147:30b64687e01f 8964 #define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /*!< Global IN nonperiodic NAK effective */
<> 147:30b64687e01f 8965 #define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /*!< Global OUT NAK effective */
<> 147:30b64687e01f 8966 #define USB_OTG_GINTSTS_ESUSP 0x00000400U /*!< Early suspend */
<> 147:30b64687e01f 8967 #define USB_OTG_GINTSTS_USBSUSP 0x00000800U /*!< USB suspend */
<> 147:30b64687e01f 8968 #define USB_OTG_GINTSTS_USBRST 0x00001000U /*!< USB reset */
<> 147:30b64687e01f 8969 #define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /*!< Enumeration done */
<> 147:30b64687e01f 8970 #define USB_OTG_GINTSTS_ISOODRP 0x00004000U /*!< Isochronous OUT packet dropped interrupt */
<> 147:30b64687e01f 8971 #define USB_OTG_GINTSTS_EOPF 0x00008000U /*!< End of periodic frame interrupt */
<> 147:30b64687e01f 8972 #define USB_OTG_GINTSTS_IEPINT 0x00040000U /*!< IN endpoint interrupt */
<> 147:30b64687e01f 8973 #define USB_OTG_GINTSTS_OEPINT 0x00080000U /*!< OUT endpoint interrupt */
<> 147:30b64687e01f 8974 #define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /*!< Incomplete isochronous IN transfer */
<> 147:30b64687e01f 8975 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /*!< Incomplete periodic transfer */
<> 147:30b64687e01f 8976 #define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /*!< Data fetch suspended */
<> 147:30b64687e01f 8977 #define USB_OTG_GINTSTS_RSTDET 0x00800000U /*!< Reset detected interrupt */
<> 147:30b64687e01f 8978 #define USB_OTG_GINTSTS_HPRTINT 0x01000000U /*!< Host port interrupt */
<> 147:30b64687e01f 8979 #define USB_OTG_GINTSTS_HCINT 0x02000000U /*!< Host channels interrupt */
<> 147:30b64687e01f 8980 #define USB_OTG_GINTSTS_PTXFE 0x04000000U /*!< Periodic TxFIFO empty */
<> 147:30b64687e01f 8981 #define USB_OTG_GINTSTS_LPMINT 0x08000000U /*!< LPM interrupt */
<> 147:30b64687e01f 8982 #define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /*!< Connector ID status change */
<> 147:30b64687e01f 8983 #define USB_OTG_GINTSTS_DISCINT 0x20000000U /*!< Disconnect detected interrupt */
<> 147:30b64687e01f 8984 #define USB_OTG_GINTSTS_SRQINT 0x40000000U /*!< Session request/new session detected interrupt */
<> 147:30b64687e01f 8985 #define USB_OTG_GINTSTS_WKUINT 0x80000000U /*!< Resume/remote wakeup detected interrupt */
<> 147:30b64687e01f 8986
<> 147:30b64687e01f 8987 /******************** Bit definition for USB_OTG_GINTMSK register ********************/
<> 147:30b64687e01f 8988 #define USB_OTG_GINTMSK_MMISM 0x00000002U /*!< Mode mismatch interrupt mask */
<> 147:30b64687e01f 8989 #define USB_OTG_GINTMSK_OTGINT 0x00000004U /*!< OTG interrupt mask */
<> 147:30b64687e01f 8990 #define USB_OTG_GINTMSK_SOFM 0x00000008U /*!< Start of frame mask */
<> 147:30b64687e01f 8991 #define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /*!< Receive FIFO nonempty mask */
<> 147:30b64687e01f 8992 #define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /*!< Nonperiodic TxFIFO empty mask */
<> 147:30b64687e01f 8993 #define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /*!< Global nonperiodic IN NAK effective mask */
<> 147:30b64687e01f 8994 #define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /*!< Global OUT NAK effective mask */
<> 147:30b64687e01f 8995 #define USB_OTG_GINTMSK_ESUSPM 0x00000400U /*!< Early suspend mask */
<> 147:30b64687e01f 8996 #define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /*!< USB suspend mask */
<> 147:30b64687e01f 8997 #define USB_OTG_GINTMSK_USBRST 0x00001000U /*!< USB reset mask */
<> 147:30b64687e01f 8998 #define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /*!< Enumeration done mask */
<> 147:30b64687e01f 8999 #define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /*!< Isochronous OUT packet dropped interrupt mask */
<> 147:30b64687e01f 9000 #define USB_OTG_GINTMSK_EOPFM 0x00008000U /*!< End of periodic frame interrupt mask */
<> 147:30b64687e01f 9001 #define USB_OTG_GINTMSK_EPMISM 0x00020000U /*!< Endpoint mismatch interrupt mask */
<> 147:30b64687e01f 9002 #define USB_OTG_GINTMSK_IEPINT 0x00040000U /*!< IN endpoints interrupt mask */
<> 147:30b64687e01f 9003 #define USB_OTG_GINTMSK_OEPINT 0x00080000U /*!< OUT endpoints interrupt mask */
<> 147:30b64687e01f 9004 #define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /*!< Incomplete isochronous IN transfer mask */
<> 147:30b64687e01f 9005 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /*!< Incomplete periodic transfer mask */
<> 147:30b64687e01f 9006 #define USB_OTG_GINTMSK_FSUSPM 0x00400000U /*!< Data fetch suspended mask */
<> 147:30b64687e01f 9007 #define USB_OTG_GINTMSK_RSTDEM 0x00800000U /*!< Reset detected interrupt mask */
<> 147:30b64687e01f 9008 #define USB_OTG_GINTMSK_PRTIM 0x01000000U /*!< Host port interrupt mask */
<> 147:30b64687e01f 9009 #define USB_OTG_GINTMSK_HCIM 0x02000000U /*!< Host channels interrupt mask */
<> 147:30b64687e01f 9010 #define USB_OTG_GINTMSK_PTXFEM 0x04000000U /*!< Periodic TxFIFO empty mask */
<> 147:30b64687e01f 9011 #define USB_OTG_GINTMSK_LPMINTM 0x08000000U /*!< LPM interrupt Mask */
<> 147:30b64687e01f 9012 #define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /*!< Connector ID status change mask */
<> 147:30b64687e01f 9013 #define USB_OTG_GINTMSK_DISCINT 0x20000000U /*!< Disconnect detected interrupt mask */
<> 147:30b64687e01f 9014 #define USB_OTG_GINTMSK_SRQIM 0x40000000U /*!< Session request/new session detected interrupt mask */
<> 147:30b64687e01f 9015 #define USB_OTG_GINTMSK_WUIM 0x80000000U /*!< Resume/remote wakeup detected interrupt mask */
<> 147:30b64687e01f 9016
<> 147:30b64687e01f 9017 /******************** Bit definition for USB_OTG_DAINT register ********************/
<> 147:30b64687e01f 9018 #define USB_OTG_DAINT_IEPINT 0x0000FFFFU /*!< IN endpoint interrupt bits */
<> 147:30b64687e01f 9019 #define USB_OTG_DAINT_OEPINT 0xFFFF0000U /*!< OUT endpoint interrupt bits */
<> 147:30b64687e01f 9020
<> 147:30b64687e01f 9021 /******************** Bit definition for USB_OTG_HAINTMSK register ********************/
<> 147:30b64687e01f 9022 #define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /*!< Channel interrupt mask */
<> 147:30b64687e01f 9023
<> 147:30b64687e01f 9024 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
<> 147:30b64687e01f 9025 #define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /*!< IN EP interrupt mask bits */
<> 147:30b64687e01f 9026 #define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /*!< OUT EP interrupt mask bits */
<> 147:30b64687e01f 9027 #define USB_OTG_GRXSTSP_DPID 0x00018000U /*!< OUT EP interrupt mask bits */
<> 147:30b64687e01f 9028 #define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /*!< OUT EP interrupt mask bits */
<> 147:30b64687e01f 9029
<> 147:30b64687e01f 9030 /******************** Bit definition for USB_OTG_DAINTMSK register ********************/
<> 147:30b64687e01f 9031 #define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /*!< IN EP interrupt mask bits */
<> 147:30b64687e01f 9032 #define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /*!< OUT EP interrupt mask bits */
<> 147:30b64687e01f 9033
<> 147:30b64687e01f 9034 /******************** Bit definition for OTG register ********************/
<> 147:30b64687e01f 9035
<> 147:30b64687e01f 9036 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 147:30b64687e01f 9037 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9038 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9039 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 9040 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 9041 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 147:30b64687e01f 9042
<> 147:30b64687e01f 9043 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 147:30b64687e01f 9044 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 9045 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 9046
<> 147:30b64687e01f 9047 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 147:30b64687e01f 9048 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 147:30b64687e01f 9049 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 147:30b64687e01f 9050 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 147:30b64687e01f 9051 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 147:30b64687e01f 9052
<> 147:30b64687e01f 9053 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 147:30b64687e01f 9054 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9055 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9056 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 9057 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 9058
<> 147:30b64687e01f 9059 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 147:30b64687e01f 9060 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 147:30b64687e01f 9061 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 147:30b64687e01f 9062 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 147:30b64687e01f 9063 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 147:30b64687e01f 9064
<> 147:30b64687e01f 9065 /******************** Bit definition for OTG register ********************/
<> 147:30b64687e01f 9066
<> 147:30b64687e01f 9067 #define USB_OTG_CHNUM 0x0000000FU /*!< Channel number */
<> 147:30b64687e01f 9068 #define USB_OTG_CHNUM_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9069 #define USB_OTG_CHNUM_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9070 #define USB_OTG_CHNUM_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 9071 #define USB_OTG_CHNUM_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 9072 #define USB_OTG_BCNT 0x00007FF0U /*!< Byte count */
<> 147:30b64687e01f 9073
<> 147:30b64687e01f 9074 #define USB_OTG_DPID 0x00018000U /*!< Data PID */
<> 147:30b64687e01f 9075 #define USB_OTG_DPID_0 0x00008000U /*!<Bit 0 */
<> 147:30b64687e01f 9076 #define USB_OTG_DPID_1 0x00010000U /*!<Bit 1 */
<> 147:30b64687e01f 9077
<> 147:30b64687e01f 9078 #define USB_OTG_PKTSTS 0x001E0000U /*!< Packet status */
<> 147:30b64687e01f 9079 #define USB_OTG_PKTSTS_0 0x00020000U /*!<Bit 0 */
<> 147:30b64687e01f 9080 #define USB_OTG_PKTSTS_1 0x00040000U /*!<Bit 1 */
<> 147:30b64687e01f 9081 #define USB_OTG_PKTSTS_2 0x00080000U /*!<Bit 2 */
<> 147:30b64687e01f 9082 #define USB_OTG_PKTSTS_3 0x00100000U /*!<Bit 3 */
<> 147:30b64687e01f 9083
<> 147:30b64687e01f 9084 #define USB_OTG_EPNUM 0x0000000FU /*!< Endpoint number */
<> 147:30b64687e01f 9085 #define USB_OTG_EPNUM_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9086 #define USB_OTG_EPNUM_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9087 #define USB_OTG_EPNUM_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 9088 #define USB_OTG_EPNUM_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 9089
<> 147:30b64687e01f 9090 #define USB_OTG_FRMNUM 0x01E00000U /*!< Frame number */
<> 147:30b64687e01f 9091 #define USB_OTG_FRMNUM_0 0x00200000U /*!<Bit 0 */
<> 147:30b64687e01f 9092 #define USB_OTG_FRMNUM_1 0x00400000U /*!<Bit 1 */
<> 147:30b64687e01f 9093 #define USB_OTG_FRMNUM_2 0x00800000U /*!<Bit 2 */
<> 147:30b64687e01f 9094 #define USB_OTG_FRMNUM_3 0x01000000U /*!<Bit 3 */
<> 147:30b64687e01f 9095
<> 147:30b64687e01f 9096 /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/
<> 147:30b64687e01f 9097 #define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /*!< RxFIFO depth */
<> 147:30b64687e01f 9098
<> 147:30b64687e01f 9099 /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/
<> 147:30b64687e01f 9100 #define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /*!< Device VBUS discharge time */
<> 147:30b64687e01f 9101
<> 147:30b64687e01f 9102 /******************** Bit definition for OTG register ********************/
<> 147:30b64687e01f 9103 #define USB_OTG_NPTXFSA 0x0000FFFFU /*!< Nonperiodic transmit RAM start address */
<> 147:30b64687e01f 9104 #define USB_OTG_NPTXFD 0xFFFF0000U /*!< Nonperiodic TxFIFO depth */
<> 147:30b64687e01f 9105 #define USB_OTG_TX0FSA 0x0000FFFFU /*!< Endpoint 0 transmit RAM start address */
<> 147:30b64687e01f 9106 #define USB_OTG_TX0FD 0xFFFF0000U /*!< Endpoint 0 TxFIFO depth */
<> 147:30b64687e01f 9107
<> 147:30b64687e01f 9108 /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/
<> 147:30b64687e01f 9109 #define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /*!< Device VBUS pulsing time */
<> 147:30b64687e01f 9110
<> 147:30b64687e01f 9111 /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/
<> 147:30b64687e01f 9112 #define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /*!< Nonperiodic TxFIFO space available */
<> 147:30b64687e01f 9113
<> 147:30b64687e01f 9114 #define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /*!< Nonperiodic transmit request queue space available */
<> 147:30b64687e01f 9115 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /*!<Bit 0 */
<> 147:30b64687e01f 9116 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /*!<Bit 1 */
<> 147:30b64687e01f 9117 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /*!<Bit 2 */
<> 147:30b64687e01f 9118 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /*!<Bit 3 */
<> 147:30b64687e01f 9119 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /*!<Bit 4 */
<> 147:30b64687e01f 9120 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /*!<Bit 5 */
<> 147:30b64687e01f 9121 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /*!<Bit 6 */
<> 147:30b64687e01f 9122 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /*!<Bit 7 */
<> 147:30b64687e01f 9123
<> 147:30b64687e01f 9124 #define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /*!< Top of the nonperiodic transmit request queue */
<> 147:30b64687e01f 9125 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /*!<Bit 0 */
<> 147:30b64687e01f 9126 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /*!<Bit 1 */
<> 147:30b64687e01f 9127 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /*!<Bit 2 */
<> 147:30b64687e01f 9128 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /*!<Bit 3 */
<> 147:30b64687e01f 9129 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /*!<Bit 4 */
<> 147:30b64687e01f 9130 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /*!<Bit 5 */
<> 147:30b64687e01f 9131 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /*!<Bit 6 */
<> 147:30b64687e01f 9132
<> 147:30b64687e01f 9133 /******************** Bit definition for USB_OTG_DTHRCTL register ********************/
<> 147:30b64687e01f 9134 #define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /*!< Nonisochronous IN endpoints threshold enable */
<> 147:30b64687e01f 9135 #define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /*!< ISO IN endpoint threshold enable */
<> 147:30b64687e01f 9136
<> 147:30b64687e01f 9137 #define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /*!< Transmit threshold length */
<> 147:30b64687e01f 9138 #define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 9139 #define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 9140 #define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /*!<Bit 2 */
<> 147:30b64687e01f 9141 #define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /*!<Bit 3 */
<> 147:30b64687e01f 9142 #define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /*!<Bit 4 */
<> 147:30b64687e01f 9143 #define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /*!<Bit 5 */
<> 147:30b64687e01f 9144 #define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /*!<Bit 6 */
<> 147:30b64687e01f 9145 #define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /*!<Bit 7 */
<> 147:30b64687e01f 9146 #define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /*!<Bit 8 */
<> 147:30b64687e01f 9147 #define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /*!< Receive threshold enable */
<> 147:30b64687e01f 9148
<> 147:30b64687e01f 9149 #define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /*!< Receive threshold length */
<> 147:30b64687e01f 9150 #define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /*!<Bit 0 */
<> 147:30b64687e01f 9151 #define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /*!<Bit 1 */
<> 147:30b64687e01f 9152 #define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /*!<Bit 2 */
<> 147:30b64687e01f 9153 #define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /*!<Bit 3 */
<> 147:30b64687e01f 9154 #define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /*!<Bit 4 */
<> 147:30b64687e01f 9155 #define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /*!<Bit 5 */
<> 147:30b64687e01f 9156 #define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /*!<Bit 6 */
<> 147:30b64687e01f 9157 #define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /*!<Bit 7 */
<> 147:30b64687e01f 9158 #define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /*!<Bit 8 */
<> 147:30b64687e01f 9159 #define USB_OTG_DTHRCTL_ARPEN 0x08000000U /*!< Arbiter parking enable */
<> 147:30b64687e01f 9160
<> 147:30b64687e01f 9161 /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/
<> 147:30b64687e01f 9162 #define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /*!< IN EP Tx FIFO empty interrupt mask bits */
<> 147:30b64687e01f 9163
<> 147:30b64687e01f 9164 /******************** Bit definition for USB_OTG_DEACHINT register ********************/
<> 147:30b64687e01f 9165 #define USB_OTG_DEACHINT_IEP1INT 0x00000002U /*!< IN endpoint 1interrupt bit */
<> 147:30b64687e01f 9166 #define USB_OTG_DEACHINT_OEP1INT 0x00020000U /*!< OUT endpoint 1 interrupt bit */
<> 147:30b64687e01f 9167
<> 147:30b64687e01f 9168 /******************** Bit definition for USB_OTG_GCCFG register ********************/
<> 147:30b64687e01f 9169 #define USB_OTG_GCCFG_PWRDWN 0x00010000U /*!< Power down */
<> 147:30b64687e01f 9170 #define USB_OTG_GCCFG_VBDEN 0x00200000U /*!< USB VBUS Detection Enable */
<> 147:30b64687e01f 9171
<> 147:30b64687e01f 9172 /******************** Bit definition for USB_OTG_GPWRDN) register ********************/
<> 147:30b64687e01f 9173 #define USB_OTG_GPWRDN_ADPMEN 0x00000001U /*!< ADP module enable */
<> 147:30b64687e01f 9174 #define USB_OTG_GPWRDN_ADPIF 0x00800000U /*!< ADP Interrupt flag */
<> 147:30b64687e01f 9175
<> 147:30b64687e01f 9176 /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/
<> 147:30b64687e01f 9177 #define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /*!< IN Endpoint 1 interrupt mask bit */
<> 147:30b64687e01f 9178 #define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /*!< OUT Endpoint 1 interrupt mask bit */
<> 147:30b64687e01f 9179
<> 147:30b64687e01f 9180 /******************** Bit definition for USB_OTG_CID register ********************/
<> 147:30b64687e01f 9181 #define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /*!< Product ID field */
<> 147:30b64687e01f 9182
<> 147:30b64687e01f 9183 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
<> 147:30b64687e01f 9184 #define USB_OTG_GLPMCFG_LPMEN 0x00000001U /*!< LPM support enable */
<> 147:30b64687e01f 9185 #define USB_OTG_GLPMCFG_LPMACK 0x00000002U /*!< LPM Token acknowledge enable */
<> 147:30b64687e01f 9186 #define USB_OTG_GLPMCFG_BESL 0x0000003CU /*!< BESL value received with last ACKed LPM Token */
<> 147:30b64687e01f 9187 #define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /*!< bRemoteWake value received with last ACKed LPM Token */
<> 147:30b64687e01f 9188 #define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /*!< L1 shallow sleep enable */
<> 147:30b64687e01f 9189 #define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /*!< BESL threshold */
<> 147:30b64687e01f 9190 #define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /*!< L1 deep sleep enable */
<> 147:30b64687e01f 9191 #define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /*!< LPM response */
<> 147:30b64687e01f 9192 #define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /*!< Port sleep status */
<> 147:30b64687e01f 9193 #define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /*!< Sleep State Resume OK */
<> 147:30b64687e01f 9194 #define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /*!< LPM Channel Index */
<> 147:30b64687e01f 9195 #define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /*!< LPM retry count */
<> 147:30b64687e01f 9196 #define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /*!< Send LPM transaction */
<> 147:30b64687e01f 9197 #define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /*!< LPM retry count status */
<> 147:30b64687e01f 9198 #define USB_OTG_GLPMCFG_ENBESL 0x10000000U /*!< Enable best effort service latency */
<> 147:30b64687e01f 9199
<> 147:30b64687e01f 9200 /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/
<> 147:30b64687e01f 9201 #define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 147:30b64687e01f 9202 #define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 147:30b64687e01f 9203 #define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask (nonisochronous endpoints) */
<> 147:30b64687e01f 9204 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 147:30b64687e01f 9205 #define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 147:30b64687e01f 9206 #define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 147:30b64687e01f 9207 #define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /*!< FIFO underrun mask */
<> 147:30b64687e01f 9208 #define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 147:30b64687e01f 9209 #define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 147:30b64687e01f 9210
<> 147:30b64687e01f 9211 /******************** Bit definition for USB_OTG_HPRT register ********************/
<> 147:30b64687e01f 9212 #define USB_OTG_HPRT_PCSTS 0x00000001U /*!< Port connect status */
<> 147:30b64687e01f 9213 #define USB_OTG_HPRT_PCDET 0x00000002U /*!< Port connect detected */
<> 147:30b64687e01f 9214 #define USB_OTG_HPRT_PENA 0x00000004U /*!< Port enable */
<> 147:30b64687e01f 9215 #define USB_OTG_HPRT_PENCHNG 0x00000008U /*!< Port enable/disable change */
<> 147:30b64687e01f 9216 #define USB_OTG_HPRT_POCA 0x00000010U /*!< Port overcurrent active */
<> 147:30b64687e01f 9217 #define USB_OTG_HPRT_POCCHNG 0x00000020U /*!< Port overcurrent change */
<> 147:30b64687e01f 9218 #define USB_OTG_HPRT_PRES 0x00000040U /*!< Port resume */
<> 147:30b64687e01f 9219 #define USB_OTG_HPRT_PSUSP 0x00000080U /*!< Port suspend */
<> 147:30b64687e01f 9220 #define USB_OTG_HPRT_PRST 0x00000100U /*!< Port reset */
<> 147:30b64687e01f 9221
<> 147:30b64687e01f 9222 #define USB_OTG_HPRT_PLSTS 0x00000C00U /*!< Port line status */
<> 147:30b64687e01f 9223 #define USB_OTG_HPRT_PLSTS_0 0x00000400U /*!<Bit 0 */
<> 147:30b64687e01f 9224 #define USB_OTG_HPRT_PLSTS_1 0x00000800U /*!<Bit 1 */
<> 147:30b64687e01f 9225 #define USB_OTG_HPRT_PPWR 0x00001000U /*!< Port power */
<> 147:30b64687e01f 9226
<> 147:30b64687e01f 9227 #define USB_OTG_HPRT_PTCTL 0x0001E000U /*!< Port test control */
<> 147:30b64687e01f 9228 #define USB_OTG_HPRT_PTCTL_0 0x00002000U /*!<Bit 0 */
<> 147:30b64687e01f 9229 #define USB_OTG_HPRT_PTCTL_1 0x00004000U /*!<Bit 1 */
<> 147:30b64687e01f 9230 #define USB_OTG_HPRT_PTCTL_2 0x00008000U /*!<Bit 2 */
<> 147:30b64687e01f 9231 #define USB_OTG_HPRT_PTCTL_3 0x00010000U /*!<Bit 3 */
<> 147:30b64687e01f 9232
<> 147:30b64687e01f 9233 #define USB_OTG_HPRT_PSPD 0x00060000U /*!< Port speed */
<> 147:30b64687e01f 9234 #define USB_OTG_HPRT_PSPD_0 0x00020000U /*!<Bit 0 */
<> 147:30b64687e01f 9235 #define USB_OTG_HPRT_PSPD_1 0x00040000U /*!<Bit 1 */
<> 147:30b64687e01f 9236
<> 147:30b64687e01f 9237 /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/
<> 147:30b64687e01f 9238 #define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /*!< Transfer completed interrupt mask */
<> 147:30b64687e01f 9239 #define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /*!< Endpoint disabled interrupt mask */
<> 147:30b64687e01f 9240 #define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /*!< Timeout condition mask */
<> 147:30b64687e01f 9241 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /*!< IN token received when TxFIFO empty mask */
<> 147:30b64687e01f 9242 #define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /*!< IN token received with EP mismatch mask */
<> 147:30b64687e01f 9243 #define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /*!< IN endpoint NAK effective mask */
<> 147:30b64687e01f 9244 #define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /*!< OUT packet error mask */
<> 147:30b64687e01f 9245 #define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /*!< BNA interrupt mask */
<> 147:30b64687e01f 9246 #define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /*!< Bubble error interrupt mask */
<> 147:30b64687e01f 9247 #define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /*!< NAK interrupt mask */
<> 147:30b64687e01f 9248 #define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /*!< NYET interrupt mask */
<> 147:30b64687e01f 9249
<> 147:30b64687e01f 9250 /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/
<> 147:30b64687e01f 9251 #define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /*!< Host periodic TxFIFO start address */
<> 147:30b64687e01f 9252 #define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /*!< Host periodic TxFIFO depth */
<> 147:30b64687e01f 9253
<> 147:30b64687e01f 9254 /******************** Bit definition for USB_OTG_DIEPCTL register ********************/
<> 147:30b64687e01f 9255 #define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 147:30b64687e01f 9256 #define USB_OTG_DIEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 147:30b64687e01f 9257 #define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /*!< Even/odd frame */
<> 147:30b64687e01f 9258 #define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 147:30b64687e01f 9259
<> 147:30b64687e01f 9260 #define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 147:30b64687e01f 9261 #define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 147:30b64687e01f 9262 #define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 147:30b64687e01f 9263 #define USB_OTG_DIEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 147:30b64687e01f 9264
<> 147:30b64687e01f 9265 #define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /*!< TxFIFO number */
<> 147:30b64687e01f 9266 #define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /*!<Bit 0 */
<> 147:30b64687e01f 9267 #define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /*!<Bit 1 */
<> 147:30b64687e01f 9268 #define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /*!<Bit 2 */
<> 147:30b64687e01f 9269 #define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /*!<Bit 3 */
<> 147:30b64687e01f 9270 #define USB_OTG_DIEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 147:30b64687e01f 9271 #define USB_OTG_DIEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 147:30b64687e01f 9272 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 147:30b64687e01f 9273 #define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 147:30b64687e01f 9274 #define USB_OTG_DIEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 147:30b64687e01f 9275 #define USB_OTG_DIEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 147:30b64687e01f 9276
<> 147:30b64687e01f 9277 /******************** Bit definition for USB_OTG_HCCHAR register ********************/
<> 147:30b64687e01f 9278 #define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /*!< Maximum packet size */
<> 147:30b64687e01f 9279
<> 147:30b64687e01f 9280 #define USB_OTG_HCCHAR_EPNUM 0x00007800U /*!< Endpoint number */
<> 147:30b64687e01f 9281 #define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /*!<Bit 0 */
<> 147:30b64687e01f 9282 #define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /*!<Bit 1 */
<> 147:30b64687e01f 9283 #define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /*!<Bit 2 */
<> 147:30b64687e01f 9284 #define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /*!<Bit 3 */
<> 147:30b64687e01f 9285 #define USB_OTG_HCCHAR_EPDIR 0x00008000U /*!< Endpoint direction */
<> 147:30b64687e01f 9286 #define USB_OTG_HCCHAR_LSDEV 0x00020000U /*!< Low-speed device */
<> 147:30b64687e01f 9287
<> 147:30b64687e01f 9288 #define USB_OTG_HCCHAR_EPTYP 0x000C0000U /*!< Endpoint type */
<> 147:30b64687e01f 9289 #define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 147:30b64687e01f 9290 #define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 147:30b64687e01f 9291
<> 147:30b64687e01f 9292 #define USB_OTG_HCCHAR_MC 0x00300000U /*!< Multi Count (MC) / Error Count (EC) */
<> 147:30b64687e01f 9293 #define USB_OTG_HCCHAR_MC_0 0x00100000U /*!<Bit 0 */
<> 147:30b64687e01f 9294 #define USB_OTG_HCCHAR_MC_1 0x00200000U /*!<Bit 1 */
<> 147:30b64687e01f 9295
<> 147:30b64687e01f 9296 #define USB_OTG_HCCHAR_DAD 0x1FC00000U /*!< Device address */
<> 147:30b64687e01f 9297 #define USB_OTG_HCCHAR_DAD_0 0x00400000U /*!<Bit 0 */
<> 147:30b64687e01f 9298 #define USB_OTG_HCCHAR_DAD_1 0x00800000U /*!<Bit 1 */
<> 147:30b64687e01f 9299 #define USB_OTG_HCCHAR_DAD_2 0x01000000U /*!<Bit 2 */
<> 147:30b64687e01f 9300 #define USB_OTG_HCCHAR_DAD_3 0x02000000U /*!<Bit 3 */
<> 147:30b64687e01f 9301 #define USB_OTG_HCCHAR_DAD_4 0x04000000U /*!<Bit 4 */
<> 147:30b64687e01f 9302 #define USB_OTG_HCCHAR_DAD_5 0x08000000U /*!<Bit 5 */
<> 147:30b64687e01f 9303 #define USB_OTG_HCCHAR_DAD_6 0x10000000U /*!<Bit 6 */
<> 147:30b64687e01f 9304 #define USB_OTG_HCCHAR_ODDFRM 0x20000000U /*!< Odd frame */
<> 147:30b64687e01f 9305 #define USB_OTG_HCCHAR_CHDIS 0x40000000U /*!< Channel disable */
<> 147:30b64687e01f 9306 #define USB_OTG_HCCHAR_CHENA 0x80000000U /*!< Channel enable */
<> 147:30b64687e01f 9307
<> 147:30b64687e01f 9308 /******************** Bit definition for USB_OTG_HCSPLT register ********************/
<> 147:30b64687e01f 9309
<> 147:30b64687e01f 9310 #define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /*!< Port address */
<> 147:30b64687e01f 9311 #define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9312 #define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9313 #define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /*!<Bit 2 */
<> 147:30b64687e01f 9314 #define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /*!<Bit 3 */
<> 147:30b64687e01f 9315 #define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /*!<Bit 4 */
<> 147:30b64687e01f 9316 #define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /*!<Bit 5 */
<> 147:30b64687e01f 9317 #define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /*!<Bit 6 */
<> 147:30b64687e01f 9318
<> 147:30b64687e01f 9319 #define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /*!< Hub address */
<> 147:30b64687e01f 9320 #define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /*!<Bit 0 */
<> 147:30b64687e01f 9321 #define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /*!<Bit 1 */
<> 147:30b64687e01f 9322 #define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /*!<Bit 2 */
<> 147:30b64687e01f 9323 #define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /*!<Bit 3 */
<> 147:30b64687e01f 9324 #define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /*!<Bit 4 */
<> 147:30b64687e01f 9325 #define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /*!<Bit 5 */
<> 147:30b64687e01f 9326 #define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /*!<Bit 6 */
<> 147:30b64687e01f 9327
<> 147:30b64687e01f 9328 #define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /*!< XACTPOS */
<> 147:30b64687e01f 9329 #define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /*!<Bit 0 */
<> 147:30b64687e01f 9330 #define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /*!<Bit 1 */
<> 147:30b64687e01f 9331 #define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /*!< Do complete split */
<> 147:30b64687e01f 9332 #define USB_OTG_HCSPLT_SPLITEN 0x80000000U /*!< Split enable */
<> 147:30b64687e01f 9333
<> 147:30b64687e01f 9334 /******************** Bit definition for USB_OTG_HCINT register ********************/
<> 147:30b64687e01f 9335 #define USB_OTG_HCINT_XFRC 0x00000001U /*!< Transfer completed */
<> 147:30b64687e01f 9336 #define USB_OTG_HCINT_CHH 0x00000002U /*!< Channel halted */
<> 147:30b64687e01f 9337 #define USB_OTG_HCINT_AHBERR 0x00000004U /*!< AHB error */
<> 147:30b64687e01f 9338 #define USB_OTG_HCINT_STALL 0x00000008U /*!< STALL response received interrupt */
<> 147:30b64687e01f 9339 #define USB_OTG_HCINT_NAK 0x00000010U /*!< NAK response received interrupt */
<> 147:30b64687e01f 9340 #define USB_OTG_HCINT_ACK 0x00000020U /*!< ACK response received/transmitted interrupt */
<> 147:30b64687e01f 9341 #define USB_OTG_HCINT_NYET 0x00000040U /*!< Response received interrupt */
<> 147:30b64687e01f 9342 #define USB_OTG_HCINT_TXERR 0x00000080U /*!< Transaction error */
<> 147:30b64687e01f 9343 #define USB_OTG_HCINT_BBERR 0x00000100U /*!< Babble error */
<> 147:30b64687e01f 9344 #define USB_OTG_HCINT_FRMOR 0x00000200U /*!< Frame overrun */
<> 147:30b64687e01f 9345 #define USB_OTG_HCINT_DTERR 0x00000400U /*!< Data toggle error */
<> 147:30b64687e01f 9346
<> 147:30b64687e01f 9347 /******************** Bit definition for USB_OTG_DIEPINT register ********************/
<> 147:30b64687e01f 9348 #define USB_OTG_DIEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 147:30b64687e01f 9349 #define USB_OTG_DIEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 147:30b64687e01f 9350 #define USB_OTG_DIEPINT_TOC 0x00000008U /*!< Timeout condition */
<> 147:30b64687e01f 9351 #define USB_OTG_DIEPINT_ITTXFE 0x00000010U /*!< IN token received when TxFIFO is empty */
<> 147:30b64687e01f 9352 #define USB_OTG_DIEPINT_INEPNE 0x00000040U /*!< IN endpoint NAK effective */
<> 147:30b64687e01f 9353 #define USB_OTG_DIEPINT_TXFE 0x00000080U /*!< Transmit FIFO empty */
<> 147:30b64687e01f 9354 #define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /*!< Transmit Fifo Underrun */
<> 147:30b64687e01f 9355 #define USB_OTG_DIEPINT_BNA 0x00000200U /*!< Buffer not available interrupt */
<> 147:30b64687e01f 9356 #define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /*!< Packet dropped status */
<> 147:30b64687e01f 9357 #define USB_OTG_DIEPINT_BERR 0x00001000U /*!< Babble error interrupt */
<> 147:30b64687e01f 9358 #define USB_OTG_DIEPINT_NAK 0x00002000U /*!< NAK interrupt */
<> 147:30b64687e01f 9359
<> 147:30b64687e01f 9360 /******************** Bit definition for USB_OTG_HCINTMSK register ********************/
<> 147:30b64687e01f 9361 #define USB_OTG_HCINTMSK_XFRCM 0x00000001U /*!< Transfer completed mask */
<> 147:30b64687e01f 9362 #define USB_OTG_HCINTMSK_CHHM 0x00000002U /*!< Channel halted mask */
<> 147:30b64687e01f 9363 #define USB_OTG_HCINTMSK_AHBERR 0x00000004U /*!< AHB error */
<> 147:30b64687e01f 9364 #define USB_OTG_HCINTMSK_STALLM 0x00000008U /*!< STALL response received interrupt mask */
<> 147:30b64687e01f 9365 #define USB_OTG_HCINTMSK_NAKM 0x00000010U /*!< NAK response received interrupt mask */
<> 147:30b64687e01f 9366 #define USB_OTG_HCINTMSK_ACKM 0x00000020U /*!< ACK response received/transmitted interrupt mask */
<> 147:30b64687e01f 9367 #define USB_OTG_HCINTMSK_NYET 0x00000040U /*!< response received interrupt mask */
<> 147:30b64687e01f 9368 #define USB_OTG_HCINTMSK_TXERRM 0x00000080U /*!< Transaction error mask */
<> 147:30b64687e01f 9369 #define USB_OTG_HCINTMSK_BBERRM 0x00000100U /*!< Babble error mask */
<> 147:30b64687e01f 9370 #define USB_OTG_HCINTMSK_FRMORM 0x00000200U /*!< Frame overrun mask */
<> 147:30b64687e01f 9371 #define USB_OTG_HCINTMSK_DTERRM 0x00000400U /*!< Data toggle error mask */
<> 147:30b64687e01f 9372
<> 147:30b64687e01f 9373 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
<> 147:30b64687e01f 9374
<> 147:30b64687e01f 9375 #define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 147:30b64687e01f 9376 #define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 147:30b64687e01f 9377 #define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /*!< Packet count */
<> 147:30b64687e01f 9378 /******************** Bit definition for USB_OTG_HCTSIZ register ********************/
<> 147:30b64687e01f 9379 #define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 147:30b64687e01f 9380 #define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 147:30b64687e01f 9381 #define USB_OTG_HCTSIZ_DOPING 0x80000000U /*!< Do PING */
<> 147:30b64687e01f 9382 #define USB_OTG_HCTSIZ_DPID 0x60000000U /*!< Data PID */
<> 147:30b64687e01f 9383 #define USB_OTG_HCTSIZ_DPID_0 0x20000000U /*!<Bit 0 */
<> 147:30b64687e01f 9384 #define USB_OTG_HCTSIZ_DPID_1 0x40000000U /*!<Bit 1 */
<> 147:30b64687e01f 9385
<> 147:30b64687e01f 9386 /******************** Bit definition for USB_OTG_DIEPDMA register ********************/
<> 147:30b64687e01f 9387 #define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 147:30b64687e01f 9388
<> 147:30b64687e01f 9389 /******************** Bit definition for USB_OTG_HCDMA register ********************/
<> 147:30b64687e01f 9390 #define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /*!< DMA address */
<> 147:30b64687e01f 9391
<> 147:30b64687e01f 9392 /******************** Bit definition for USB_OTG_DTXFSTS register ********************/
<> 147:30b64687e01f 9393 #define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /*!< IN endpoint TxFIFO space available */
<> 147:30b64687e01f 9394
<> 147:30b64687e01f 9395 /******************** Bit definition for USB_OTG_DIEPTXF register ********************/
<> 147:30b64687e01f 9396 #define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /*!< IN endpoint FIFOx transmit RAM start address */
<> 147:30b64687e01f 9397 #define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /*!< IN endpoint TxFIFO depth */
<> 147:30b64687e01f 9398
<> 147:30b64687e01f 9399 /******************** Bit definition for USB_OTG_DOEPCTL register ********************/
<> 147:30b64687e01f 9400 #define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /*!< Maximum packet size */ /*!<Bit 1 */
<> 147:30b64687e01f 9401 #define USB_OTG_DOEPCTL_USBAEP 0x00008000U /*!< USB active endpoint */
<> 147:30b64687e01f 9402 #define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /*!< NAK status */
<> 147:30b64687e01f 9403 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /*!< Set DATA0 PID */
<> 147:30b64687e01f 9404 #define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /*!< Set odd frame */
<> 147:30b64687e01f 9405 #define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /*!< Endpoint type */
<> 147:30b64687e01f 9406 #define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /*!<Bit 0 */
<> 147:30b64687e01f 9407 #define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /*!<Bit 1 */
<> 147:30b64687e01f 9408 #define USB_OTG_DOEPCTL_SNPM 0x00100000U /*!< Snoop mode */
<> 147:30b64687e01f 9409 #define USB_OTG_DOEPCTL_STALL 0x00200000U /*!< STALL handshake */
<> 147:30b64687e01f 9410 #define USB_OTG_DOEPCTL_CNAK 0x04000000U /*!< Clear NAK */
<> 147:30b64687e01f 9411 #define USB_OTG_DOEPCTL_SNAK 0x08000000U /*!< Set NAK */
<> 147:30b64687e01f 9412 #define USB_OTG_DOEPCTL_EPDIS 0x40000000U /*!< Endpoint disable */
<> 147:30b64687e01f 9413 #define USB_OTG_DOEPCTL_EPENA 0x80000000U /*!< Endpoint enable */
<> 147:30b64687e01f 9414
<> 147:30b64687e01f 9415 /******************** Bit definition for USB_OTG_DOEPINT register ********************/
<> 147:30b64687e01f 9416 #define USB_OTG_DOEPINT_XFRC 0x00000001U /*!< Transfer completed interrupt */
<> 147:30b64687e01f 9417 #define USB_OTG_DOEPINT_EPDISD 0x00000002U /*!< Endpoint disabled interrupt */
<> 147:30b64687e01f 9418 #define USB_OTG_DOEPINT_STUP 0x00000008U /*!< SETUP phase done */
<> 147:30b64687e01f 9419 #define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /*!< OUT token received when endpoint disabled */
<> 147:30b64687e01f 9420 #define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /*!< Status Phase Received For Control Write */
<> 147:30b64687e01f 9421 #define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /*!< Back-to-back SETUP packets received */
<> 147:30b64687e01f 9422 #define USB_OTG_DOEPINT_NYET 0x00004000U /*!< NYET interrupt */
<> 147:30b64687e01f 9423
<> 147:30b64687e01f 9424 /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/
<> 147:30b64687e01f 9425 #define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /*!< Transfer size */
<> 147:30b64687e01f 9426 #define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /*!< Packet count */
<> 147:30b64687e01f 9427
<> 147:30b64687e01f 9428 #define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /*!< SETUP packet count */
<> 147:30b64687e01f 9429 #define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /*!<Bit 0 */
<> 147:30b64687e01f 9430 #define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /*!<Bit 1 */
<> 147:30b64687e01f 9431
<> 147:30b64687e01f 9432 /******************** Bit definition for PCGCCTL register ********************/
<> 147:30b64687e01f 9433 #define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /*!< SETUP packet count */
<> 147:30b64687e01f 9434 #define USB_OTG_PCGCCTL_GATECLK 0x00000002U /*!<Bit 0 */
<> 147:30b64687e01f 9435 #define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /*!<Bit 1 */
<> 147:30b64687e01f 9436
<> 157:ff67d9f36b67 9437
<> 147:30b64687e01f 9438 /******************************************************************************/
<> 147:30b64687e01f 9439 /* */
<> 147:30b64687e01f 9440 /* JPEG Encoder/Decoder */
<> 147:30b64687e01f 9441 /* */
<> 147:30b64687e01f 9442 /******************************************************************************/
<> 147:30b64687e01f 9443 /******************** Bit definition for CONFR0 register ********************/
<> 147:30b64687e01f 9444 #define JPEG_CONFR0_START 0x00000001U /*!<Start/Stop bit */
<> 147:30b64687e01f 9445
<> 147:30b64687e01f 9446 /******************** Bit definition for CONFR1 register *******************/
<> 147:30b64687e01f 9447 #define JPEG_CONFR1_NF 0x00000003U /*!<Number of color components */
<> 147:30b64687e01f 9448 #define JPEG_CONFR1_NF_0 0x00000001U /*!<Bit 0 */
<> 147:30b64687e01f 9449 #define JPEG_CONFR1_NF_1 0x00000002U /*!<Bit 1 */
<> 147:30b64687e01f 9450 #define JPEG_CONFR1_RE 0x00000004U /*!<Restart maker Enable */
<> 147:30b64687e01f 9451 #define JPEG_CONFR1_DE 0x00000008U /*!<Decoding Enable */
<> 147:30b64687e01f 9452 #define JPEG_CONFR1_COLORSPACE 0x00000030U /*!<Color Space */
<> 147:30b64687e01f 9453 #define JPEG_CONFR1_COLORSPACE_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 9454 #define JPEG_CONFR1_COLORSPACE_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 9455 #define JPEG_CONFR1_NS 0x000000C0U /*!<Number of components for Scan */
<> 147:30b64687e01f 9456 #define JPEG_CONFR1_NS_0 0x00000040U /*!<Bit 0 */
<> 147:30b64687e01f 9457 #define JPEG_CONFR1_NS_1 0x00000080U /*!<Bit 1 */
<> 147:30b64687e01f 9458 #define JPEG_CONFR1_HDR 0x00000100U /*!<Header Processing On/Off */
<> 147:30b64687e01f 9459 #define JPEG_CONFR1_YSIZE 0xFFFF0000U /*!<Number of lines in source image */
<> 147:30b64687e01f 9460
<> 147:30b64687e01f 9461 /******************** Bit definition for CONFR2 register *******************/
<> 147:30b64687e01f 9462 #define JPEG_CONFR2_NMCU 0x03FFFFFFU /*!<Number of MCU units minus 1 to encode */
<> 147:30b64687e01f 9463
<> 147:30b64687e01f 9464 /******************** Bit definition for CONFR3 register *******************/
<> 147:30b64687e01f 9465 #define JPEG_CONFR3_NRST 0x0000FFFFU /*!<Number of MCU between two restart makers minus 1 */
<> 147:30b64687e01f 9466 #define JPEG_CONFR3_XSIZE 0xFFFF0000U /*!<Number of pixels per line */
<> 147:30b64687e01f 9467
<> 147:30b64687e01f 9468 /******************** Bit definition for CONFR4 register *******************/
<> 147:30b64687e01f 9469 #define JPEG_CONFR4_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
<> 147:30b64687e01f 9470 #define JPEG_CONFR4_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
<> 147:30b64687e01f 9471 #define JPEG_CONFR4_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
<> 147:30b64687e01f 9472 #define JPEG_CONFR4_QT_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 9473 #define JPEG_CONFR4_QT_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 9474 #define JPEG_CONFR4_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 147:30b64687e01f 9475 #define JPEG_CONFR4_NB_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 9476 #define JPEG_CONFR4_NB_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 9477 #define JPEG_CONFR4_NB_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 9478 #define JPEG_CONFR4_NB_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 9479 #define JPEG_CONFR4_VSF 0x00000F00U /*!<Vertical sampling factor for component 1 */
<> 147:30b64687e01f 9480 #define JPEG_CONFR4_VSF_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 9481 #define JPEG_CONFR4_VSF_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 9482 #define JPEG_CONFR4_VSF_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 9483 #define JPEG_CONFR4_VSF_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 9484 #define JPEG_CONFR4_HSF 0x0000F000U /*!<Horizontal sampling factor for component 1 */
<> 147:30b64687e01f 9485 #define JPEG_CONFR4_HSF_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 9486 #define JPEG_CONFR4_HSF_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 9487 #define JPEG_CONFR4_HSF_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 9488 #define JPEG_CONFR4_HSF_3 0x00008000U /*!<Bit 3 */
<> 147:30b64687e01f 9489
<> 147:30b64687e01f 9490 /******************** Bit definition for CONFR5 register *******************/
<> 147:30b64687e01f 9491 #define JPEG_CONFR5_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
<> 147:30b64687e01f 9492 #define JPEG_CONFR5_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
<> 147:30b64687e01f 9493 #define JPEG_CONFR5_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
<> 147:30b64687e01f 9494 #define JPEG_CONFR5_QT_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 9495 #define JPEG_CONFR5_QT_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 9496 #define JPEG_CONFR5_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 147:30b64687e01f 9497 #define JPEG_CONFR5_NB_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 9498 #define JPEG_CONFR5_NB_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 9499 #define JPEG_CONFR5_NB_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 9500 #define JPEG_CONFR5_NB_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 9501 #define JPEG_CONFR5_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
<> 147:30b64687e01f 9502 #define JPEG_CONFR5_VSF_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 9503 #define JPEG_CONFR5_VSF_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 9504 #define JPEG_CONFR5_VSF_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 9505 #define JPEG_CONFR5_VSF_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 9506 #define JPEG_CONFR5_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
<> 147:30b64687e01f 9507 #define JPEG_CONFR5_HSF_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 9508 #define JPEG_CONFR5_HSF_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 9509 #define JPEG_CONFR5_HSF_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 9510 #define JPEG_CONFR5_HSF_3 0x00008000U /*!<Bit 3 */
<> 147:30b64687e01f 9511
<> 147:30b64687e01f 9512 /******************** Bit definition for CONFR6 register *******************/
<> 147:30b64687e01f 9513 #define JPEG_CONFR6_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
<> 147:30b64687e01f 9514 #define JPEG_CONFR6_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
<> 147:30b64687e01f 9515 #define JPEG_CONFR6_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
<> 147:30b64687e01f 9516 #define JPEG_CONFR6_QT_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 9517 #define JPEG_CONFR6_QT_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 9518 #define JPEG_CONFR6_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 147:30b64687e01f 9519 #define JPEG_CONFR6_NB_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 9520 #define JPEG_CONFR6_NB_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 9521 #define JPEG_CONFR6_NB_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 9522 #define JPEG_CONFR6_NB_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 9523 #define JPEG_CONFR6_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
<> 147:30b64687e01f 9524 #define JPEG_CONFR6_VSF_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 9525 #define JPEG_CONFR6_VSF_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 9526 #define JPEG_CONFR6_VSF_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 9527 #define JPEG_CONFR6_VSF_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 9528 #define JPEG_CONFR6_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
<> 147:30b64687e01f 9529 #define JPEG_CONFR6_HSF_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 9530 #define JPEG_CONFR6_HSF_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 9531 #define JPEG_CONFR6_HSF_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 9532 #define JPEG_CONFR6_HSF_3 0x00008000U /*!<Bit 3 */
<> 147:30b64687e01f 9533
<> 147:30b64687e01f 9534 /******************** Bit definition for CONFR7 register *******************/
<> 147:30b64687e01f 9535 #define JPEG_CONFR7_HD 0x00000001U /*!<Selects the Huffman table for encoding the DC coefficients */
<> 147:30b64687e01f 9536 #define JPEG_CONFR7_HA 0x00000002U /*!<Selects the Huffman table for encoding the AC coefficients */
<> 147:30b64687e01f 9537 #define JPEG_CONFR7_QT 0x0000000CU /*!<Selects quantization table associated with a color component */
<> 147:30b64687e01f 9538 #define JPEG_CONFR7_QT_0 0x00000004U /*!<Bit 0 */
<> 147:30b64687e01f 9539 #define JPEG_CONFR7_QT_1 0x00000008U /*!<Bit 1 */
<> 147:30b64687e01f 9540 #define JPEG_CONFR7_NB 0x000000F0U /*!<Number of data units minus 1 that belong to a particular color in the MCU */
<> 147:30b64687e01f 9541 #define JPEG_CONFR7_NB_0 0x00000010U /*!<Bit 0 */
<> 147:30b64687e01f 9542 #define JPEG_CONFR7_NB_1 0x00000020U /*!<Bit 1 */
<> 147:30b64687e01f 9543 #define JPEG_CONFR7_NB_2 0x00000040U /*!<Bit 2 */
<> 147:30b64687e01f 9544 #define JPEG_CONFR7_NB_3 0x00000080U /*!<Bit 3 */
<> 147:30b64687e01f 9545 #define JPEG_CONFR7_VSF 0x00000F00U /*!<Vertical sampling factor for component 2 */
<> 147:30b64687e01f 9546 #define JPEG_CONFR7_VSF_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 9547 #define JPEG_CONFR7_VSF_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 9548 #define JPEG_CONFR7_VSF_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 9549 #define JPEG_CONFR7_VSF_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 9550 #define JPEG_CONFR7_HSF 0x0000F000U /*!<Horizontal sampling factor for component 2 */
<> 147:30b64687e01f 9551 #define JPEG_CONFR7_HSF_0 0x00001000U /*!<Bit 0 */
<> 147:30b64687e01f 9552 #define JPEG_CONFR7_HSF_1 0x00002000U /*!<Bit 1 */
<> 147:30b64687e01f 9553 #define JPEG_CONFR7_HSF_2 0x00004000U /*!<Bit 2 */
<> 147:30b64687e01f 9554 #define JPEG_CONFR7_HSF_3 0x00008000U /*!<Bit 3 */
<> 147:30b64687e01f 9555
<> 147:30b64687e01f 9556 /******************** Bit definition for CR register *******************/
<> 147:30b64687e01f 9557 #define JPEG_CR_JCEN 0x00000001U /*!<Enable the JPEG Codec Core */
<> 147:30b64687e01f 9558 #define JPEG_CR_IFTIE 0x00000002U /*!<Input FIFO Threshold Interrupt Enable */
<> 147:30b64687e01f 9559 #define JPEG_CR_IFNFIE 0x00000004U /*!<Input FIFO Not Full Interrupt Enable */
<> 147:30b64687e01f 9560 #define JPEG_CR_OFTIE 0x00000008U /*!<Output FIFO Threshold Interrupt Enable */
<> 147:30b64687e01f 9561 #define JPEG_CR_OFNEIE 0x00000010U /*!<Output FIFO Not Empty Interrupt Enable */
<> 147:30b64687e01f 9562 #define JPEG_CR_EOCIE 0x00000020U /*!<End of Conversion Interrupt Enable */
<> 147:30b64687e01f 9563 #define JPEG_CR_HPDIE 0x00000040U /*!<Header Parsing Done Interrupt Enable */
<> 147:30b64687e01f 9564 #define JPEG_CR_IDMAEN 0x00000800U /*!<Enable the DMA request generation for the input FIFO */
<> 147:30b64687e01f 9565 #define JPEG_CR_ODMAEN 0x00001000U /*!<Enable the DMA request generation for the output FIFO */
<> 147:30b64687e01f 9566 #define JPEG_CR_IFF 0x00002000U /*!<Flush the input FIFO */
<> 147:30b64687e01f 9567 #define JPEG_CR_OFF 0x00004000U /*!<Flush the output FIFO */
<> 147:30b64687e01f 9568
<> 147:30b64687e01f 9569 /******************** Bit definition for SR register *******************/
<> 147:30b64687e01f 9570 #define JPEG_SR_IFTF 0x00000002U /*!<Input FIFO is not full and is bellow its threshold flag */
<> 147:30b64687e01f 9571 #define JPEG_SR_IFNFF 0x00000004U /*!<Input FIFO Not Full Flag, a data can be written */
<> 147:30b64687e01f 9572 #define JPEG_SR_OFTF 0x00000008U /*!<Output FIFO is not empty and has reach its threshold */
<> 147:30b64687e01f 9573 #define JPEG_SR_OFNEF 0x000000010U /*!<Output FIFO is not empty, a data is available */
<> 147:30b64687e01f 9574 #define JPEG_SR_EOCF 0x000000020U /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
<> 147:30b64687e01f 9575 #define JPEG_SR_HPDF 0x000000040U /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
<> 147:30b64687e01f 9576 #define JPEG_SR_COF 0x000000080U /*!<JPEG Codec operation on going flag */
<> 147:30b64687e01f 9577
<> 147:30b64687e01f 9578 /******************** Bit definition for CFR register *******************/
<> 147:30b64687e01f 9579 #define JPEG_CFR_CEOCF 0x00000020U /*!<Clear End of Conversion Flag */
<> 147:30b64687e01f 9580 #define JPEG_CFR_CHPDF 0x00000040U /*!<Clear Header Parsing Done Flag */
<> 147:30b64687e01f 9581
<> 147:30b64687e01f 9582 /******************** Bit definition for DIR register ********************/
<> 147:30b64687e01f 9583 #define JPEG_DIR_DATAIN 0xFFFFFFFFU /*!<Data Input FIFO */
<> 147:30b64687e01f 9584
<> 147:30b64687e01f 9585 /******************** Bit definition for DOR register ********************/
<> 147:30b64687e01f 9586 #define JPEG_DOR_DATAOUT 0xFFFFFFFFU /*!<Data Output FIFO */
<> 147:30b64687e01f 9587
<> 147:30b64687e01f 9588 /******************************************************************************/
<> 147:30b64687e01f 9589 /* */
<> 147:30b64687e01f 9590 /* MDIOS */
<> 147:30b64687e01f 9591 /* */
<> 147:30b64687e01f 9592 /******************************************************************************/
<> 147:30b64687e01f 9593 /******************** Bit definition for MDIOS_CR register *******************/
<> 147:30b64687e01f 9594 #define MDIOS_CR_EN 0x00000001U /*!<Peripheral enable */
<> 147:30b64687e01f 9595 #define MDIOS_CR_WRIE 0x00000002U /*!<Register write interrupt enable */
<> 147:30b64687e01f 9596 #define MDIOS_CR_RDIE 0x00000004U /*!<Register Read Interrupt Enable */
<> 147:30b64687e01f 9597 #define MDIOS_CR_EIE 0x00000008U /*!<Error interrupt enable */
<> 147:30b64687e01f 9598 #define MDIOS_CR_DPC 0x00000080U /*!<Disable Preamble Check */
<> 147:30b64687e01f 9599 #define MDIOS_CR_PORT_ADDRESS 0x00001F00U /*!<PORT_ADDRESS[4:0] bits */
<> 147:30b64687e01f 9600 #define MDIOS_CR_PORT_ADDRESS_0 0x00000100U /*!<Bit 0 */
<> 147:30b64687e01f 9601 #define MDIOS_CR_PORT_ADDRESS_1 0x00000200U /*!<Bit 1 */
<> 147:30b64687e01f 9602 #define MDIOS_CR_PORT_ADDRESS_2 0x00000400U /*!<Bit 2 */
<> 147:30b64687e01f 9603 #define MDIOS_CR_PORT_ADDRESS_3 0x00000800U /*!<Bit 3 */
<> 147:30b64687e01f 9604 #define MDIOS_CR_PORT_ADDRESS_4 0x00001000U /*!<Bit 4 */
<> 147:30b64687e01f 9605
<> 147:30b64687e01f 9606 /******************** Bit definition for MDIOS_WRFR register *******************/
<> 147:30b64687e01f 9607 #define MDIOS_WRFR_WRF 0xFFFFFFFFU /*!<WRF[31:0] bits (Write flags for MDIO register 0 to 31) */
<> 147:30b64687e01f 9608
<> 147:30b64687e01f 9609 /******************** Bit definition for MDIOS_CWRFR register *******************/
<> 147:30b64687e01f 9610 #define MDIOS_CWRFR_CWRF 0xFFFFFFFFU /*!<CWRF[31:0] bits (Clear the write flag for MDIO register 0 to 31) */
<> 147:30b64687e01f 9611
<> 147:30b64687e01f 9612 /******************** Bit definition for MDIOS_RDFR register *******************/
<> 147:30b64687e01f 9613 #define MDIOS_RDFR_RDF 0xFFFFFFFFU /*!<RDF[31:0] bits (Read flags for MDIO registers 0 to 31) */
<> 147:30b64687e01f 9614
<> 147:30b64687e01f 9615 /******************** Bit definition for MDIOS_CRDFR register *******************/
<> 147:30b64687e01f 9616 #define MDIOS_CRDFR_CRDF 0xFFFFFFFFU /*!<CRDF[31:0] bits (Clear the read flag for MDIO registers 0 to 31) */
<> 147:30b64687e01f 9617
<> 147:30b64687e01f 9618 /******************** Bit definition for MDIOS_SR register *******************/
<> 147:30b64687e01f 9619 #define MDIOS_SR_PERF 0x00000001U /*!< Preamble error flag */
<> 147:30b64687e01f 9620 #define MDIOS_SR_SERF 0x00000002U /*!< Start error flag */
<> 147:30b64687e01f 9621 #define MDIOS_SR_TERF 0x00000004U /*!< Turnaround error flag */
<> 147:30b64687e01f 9622
<> 147:30b64687e01f 9623 /******************** Bit definition for MDIOS_CLRFR register *******************/
<> 147:30b64687e01f 9624 #define MDIOS_CLRFR_CPERF 0x00000001U /*!< Clear the preamble error flag */
<> 147:30b64687e01f 9625 #define MDIOS_CLRFR_CSERF 0x00000002U /*!< Clear the start error flag */
<> 147:30b64687e01f 9626 #define MDIOS_CLRFR_CTERF 0x00000004U /*!< Clear the turnaround error flag */
<> 147:30b64687e01f 9627
<> 147:30b64687e01f 9628 /******************************************************************************/
<> 147:30b64687e01f 9629 /* */
<> 147:30b64687e01f 9630 /* Display Serial Interface (DSI) */
<> 147:30b64687e01f 9631 /* */
<> 147:30b64687e01f 9632 /******************************************************************************/
<> 147:30b64687e01f 9633 /******************* Bit definition for DSI_VR register *****************/
<> 147:30b64687e01f 9634 #define DSI_VR 0x3133302AU /*!< DSI Host Version */
<> 147:30b64687e01f 9635
<> 147:30b64687e01f 9636 /******************* Bit definition for DSI_CR register *****************/
<> 147:30b64687e01f 9637 #define DSI_CR_EN 0x00000001U /*!< DSI Host power up and reset */
<> 147:30b64687e01f 9638
<> 147:30b64687e01f 9639 /******************* Bit definition for DSI_CCR register ****************/
<> 147:30b64687e01f 9640 #define DSI_CCR_TXECKDIV 0x000000FFU /*!< TX Escape Clock Division */
<> 147:30b64687e01f 9641 #define DSI_CCR_TXECKDIV0 0x00000001U
<> 147:30b64687e01f 9642 #define DSI_CCR_TXECKDIV1 0x00000002U
<> 147:30b64687e01f 9643 #define DSI_CCR_TXECKDIV2 0x00000004U
<> 147:30b64687e01f 9644 #define DSI_CCR_TXECKDIV3 0x00000008U
<> 147:30b64687e01f 9645 #define DSI_CCR_TXECKDIV4 0x00000010U
<> 147:30b64687e01f 9646 #define DSI_CCR_TXECKDIV5 0x00000020U
<> 147:30b64687e01f 9647 #define DSI_CCR_TXECKDIV6 0x00000040U
<> 147:30b64687e01f 9648 #define DSI_CCR_TXECKDIV7 0x00000080U
<> 147:30b64687e01f 9649
<> 147:30b64687e01f 9650 #define DSI_CCR_TOCKDIV 0x0000FF00U /*!< Timeout Clock Division */
<> 147:30b64687e01f 9651 #define DSI_CCR_TOCKDIV0 0x00000100U
<> 147:30b64687e01f 9652 #define DSI_CCR_TOCKDIV1 0x00000200U
<> 147:30b64687e01f 9653 #define DSI_CCR_TOCKDIV2 0x00000400U
<> 147:30b64687e01f 9654 #define DSI_CCR_TOCKDIV3 0x00000800U
<> 147:30b64687e01f 9655 #define DSI_CCR_TOCKDIV4 0x00001000U
<> 147:30b64687e01f 9656 #define DSI_CCR_TOCKDIV5 0x00002000U
<> 147:30b64687e01f 9657 #define DSI_CCR_TOCKDIV6 0x00004000U
<> 147:30b64687e01f 9658 #define DSI_CCR_TOCKDIV7 0x00008000U
<> 147:30b64687e01f 9659
<> 147:30b64687e01f 9660 /******************* Bit definition for DSI_LVCIDR register *************/
<> 147:30b64687e01f 9661 #define DSI_LVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
<> 147:30b64687e01f 9662 #define DSI_LVCIDR_VCID0 0x00000001U
<> 147:30b64687e01f 9663 #define DSI_LVCIDR_VCID1 0x00000002U
<> 147:30b64687e01f 9664
<> 147:30b64687e01f 9665 /******************* Bit definition for DSI_LCOLCR register *************/
<> 147:30b64687e01f 9666 #define DSI_LCOLCR_COLC 0x0000000FU /*!< Color Coding */
<> 147:30b64687e01f 9667 #define DSI_LCOLCR_COLC0 0x00000001U
<> 147:30b64687e01f 9668 #define DSI_LCOLCR_COLC1 0x00000020U
<> 147:30b64687e01f 9669 #define DSI_LCOLCR_COLC2 0x00000040U
<> 147:30b64687e01f 9670 #define DSI_LCOLCR_COLC3 0x00000080U
<> 147:30b64687e01f 9671
<> 147:30b64687e01f 9672 #define DSI_LCOLCR_LPE 0x00000100U /*!< Loosly Packet Enable */
<> 147:30b64687e01f 9673
<> 147:30b64687e01f 9674 /******************* Bit definition for DSI_LPCR register ***************/
<> 147:30b64687e01f 9675 #define DSI_LPCR_DEP 0x00000001U /*!< Data Enable Polarity */
<> 147:30b64687e01f 9676 #define DSI_LPCR_VSP 0x00000002U /*!< VSYNC Polarity */
<> 147:30b64687e01f 9677 #define DSI_LPCR_HSP 0x00000004U /*!< HSYNC Polarity */
<> 147:30b64687e01f 9678
<> 147:30b64687e01f 9679 /******************* Bit definition for DSI_LPMCR register **************/
<> 147:30b64687e01f 9680 #define DSI_LPMCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
<> 147:30b64687e01f 9681 #define DSI_LPMCR_VLPSIZE0 0x00000001U
<> 147:30b64687e01f 9682 #define DSI_LPMCR_VLPSIZE1 0x00000002U
<> 147:30b64687e01f 9683 #define DSI_LPMCR_VLPSIZE2 0x00000004U
<> 147:30b64687e01f 9684 #define DSI_LPMCR_VLPSIZE3 0x00000008U
<> 147:30b64687e01f 9685 #define DSI_LPMCR_VLPSIZE4 0x00000010U
<> 147:30b64687e01f 9686 #define DSI_LPMCR_VLPSIZE5 0x00000020U
<> 147:30b64687e01f 9687 #define DSI_LPMCR_VLPSIZE6 0x00000040U
<> 147:30b64687e01f 9688 #define DSI_LPMCR_VLPSIZE7 0x00000080U
<> 147:30b64687e01f 9689
<> 147:30b64687e01f 9690 #define DSI_LPMCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
<> 147:30b64687e01f 9691 #define DSI_LPMCR_LPSIZE0 0x00010000U
<> 147:30b64687e01f 9692 #define DSI_LPMCR_LPSIZE1 0x00020000U
<> 147:30b64687e01f 9693 #define DSI_LPMCR_LPSIZE2 0x00040000U
<> 147:30b64687e01f 9694 #define DSI_LPMCR_LPSIZE3 0x00080000U
<> 147:30b64687e01f 9695 #define DSI_LPMCR_LPSIZE4 0x00100000U
<> 147:30b64687e01f 9696 #define DSI_LPMCR_LPSIZE5 0x00200000U
<> 147:30b64687e01f 9697 #define DSI_LPMCR_LPSIZE6 0x00400000U
<> 147:30b64687e01f 9698 #define DSI_LPMCR_LPSIZE7 0x00800000U
<> 147:30b64687e01f 9699
<> 147:30b64687e01f 9700 /******************* Bit definition for DSI_PCR register ****************/
<> 147:30b64687e01f 9701 #define DSI_PCR_ETTXE 0x00000001U /*!< EoTp Transmission Enable */
<> 147:30b64687e01f 9702 #define DSI_PCR_ETRXE 0x00000002U /*!< EoTp Reception Enable */
<> 147:30b64687e01f 9703 #define DSI_PCR_BTAE 0x00000004U /*!< Bus Turn Around Enable */
<> 147:30b64687e01f 9704 #define DSI_PCR_ECCRXE 0x00000008U /*!< ECC Reception Enable */
<> 147:30b64687e01f 9705 #define DSI_PCR_CRCRXE 0x00000010U /*!< CRC Reception Enable */
<> 147:30b64687e01f 9706
<> 147:30b64687e01f 9707 /******************* Bit definition for DSI_GVCIDR register *************/
<> 147:30b64687e01f 9708 #define DSI_GVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
<> 147:30b64687e01f 9709 #define DSI_GVCIDR_VCID0 0x00000001U
<> 147:30b64687e01f 9710 #define DSI_GVCIDR_VCID1 0x00000002U
<> 147:30b64687e01f 9711
<> 147:30b64687e01f 9712 /******************* Bit definition for DSI_MCR register ****************/
<> 147:30b64687e01f 9713 #define DSI_MCR_CMDM 0x00000001U /*!< Command Mode */
<> 147:30b64687e01f 9714
<> 147:30b64687e01f 9715 /******************* Bit definition for DSI_VMCR register ***************/
<> 147:30b64687e01f 9716 #define DSI_VMCR_VMT 0x00000003U /*!< Video Mode Type */
<> 147:30b64687e01f 9717 #define DSI_VMCR_VMT0 0x00000001U
<> 147:30b64687e01f 9718 #define DSI_VMCR_VMT1 0x00000002U
<> 147:30b64687e01f 9719
<> 147:30b64687e01f 9720 #define DSI_VMCR_LPVSAE 0x00000100U /*!< Low-Power Vertical Sync Active Enable */
<> 147:30b64687e01f 9721 #define DSI_VMCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-Porch Enable */
<> 147:30b64687e01f 9722 #define DSI_VMCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
<> 147:30b64687e01f 9723 #define DSI_VMCR_LPVAE 0x00000800U /*!< Low-Power Vertical Active Enable */
<> 147:30b64687e01f 9724 #define DSI_VMCR_LPHBPE 0x00001000U /*!< Low-Power Horizontal Back-Porch Enable */
<> 147:30b64687e01f 9725 #define DSI_VMCR_LPHFPE 0x00002000U /*!< Low-Power Horizontal Front-Porch Enable */
<> 147:30b64687e01f 9726 #define DSI_VMCR_FBTAAE 0x00004000U /*!< Frame Bus-Turn-Around Acknowledge Enable */
<> 147:30b64687e01f 9727 #define DSI_VMCR_LPCE 0x00008000U /*!< Low-Power Command Enable */
<> 147:30b64687e01f 9728 #define DSI_VMCR_PGE 0x00010000U /*!< Pattern Generator Enable */
<> 147:30b64687e01f 9729 #define DSI_VMCR_PGM 0x00100000U /*!< Pattern Generator Mode */
<> 147:30b64687e01f 9730 #define DSI_VMCR_PGO 0x01000000U /*!< Pattern Generator Orientation */
<> 147:30b64687e01f 9731
<> 147:30b64687e01f 9732 /******************* Bit definition for DSI_VPCR register ***************/
<> 147:30b64687e01f 9733 #define DSI_VPCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
<> 147:30b64687e01f 9734 #define DSI_VPCR_VPSIZE0 0x00000001U
<> 147:30b64687e01f 9735 #define DSI_VPCR_VPSIZE1 0x00000002U
<> 147:30b64687e01f 9736 #define DSI_VPCR_VPSIZE2 0x00000004U
<> 147:30b64687e01f 9737 #define DSI_VPCR_VPSIZE3 0x00000008U
<> 147:30b64687e01f 9738 #define DSI_VPCR_VPSIZE4 0x00000010U
<> 147:30b64687e01f 9739 #define DSI_VPCR_VPSIZE5 0x00000020U
<> 147:30b64687e01f 9740 #define DSI_VPCR_VPSIZE6 0x00000040U
<> 147:30b64687e01f 9741 #define DSI_VPCR_VPSIZE7 0x00000080U
<> 147:30b64687e01f 9742 #define DSI_VPCR_VPSIZE8 0x00000100U
<> 147:30b64687e01f 9743 #define DSI_VPCR_VPSIZE9 0x00000200U
<> 147:30b64687e01f 9744 #define DSI_VPCR_VPSIZE10 0x00000400U
<> 147:30b64687e01f 9745 #define DSI_VPCR_VPSIZE11 0x00000800U
<> 147:30b64687e01f 9746 #define DSI_VPCR_VPSIZE12 0x00001000U
<> 147:30b64687e01f 9747 #define DSI_VPCR_VPSIZE13 0x00002000U
<> 147:30b64687e01f 9748
<> 147:30b64687e01f 9749 /******************* Bit definition for DSI_VCCR register ***************/
<> 147:30b64687e01f 9750 #define DSI_VCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
<> 147:30b64687e01f 9751 #define DSI_VCCR_NUMC0 0x00000001U
<> 147:30b64687e01f 9752 #define DSI_VCCR_NUMC1 0x00000002U
<> 147:30b64687e01f 9753 #define DSI_VCCR_NUMC2 0x00000004U
<> 147:30b64687e01f 9754 #define DSI_VCCR_NUMC3 0x00000008U
<> 147:30b64687e01f 9755 #define DSI_VCCR_NUMC4 0x00000010U
<> 147:30b64687e01f 9756 #define DSI_VCCR_NUMC5 0x00000020U
<> 147:30b64687e01f 9757 #define DSI_VCCR_NUMC6 0x00000040U
<> 147:30b64687e01f 9758 #define DSI_VCCR_NUMC7 0x00000080U
<> 147:30b64687e01f 9759 #define DSI_VCCR_NUMC8 0x00000100U
<> 147:30b64687e01f 9760 #define DSI_VCCR_NUMC9 0x00000200U
<> 147:30b64687e01f 9761 #define DSI_VCCR_NUMC10 0x00000400U
<> 147:30b64687e01f 9762 #define DSI_VCCR_NUMC11 0x00000800U
<> 147:30b64687e01f 9763 #define DSI_VCCR_NUMC12 0x00001000U
<> 147:30b64687e01f 9764
<> 147:30b64687e01f 9765 /******************* Bit definition for DSI_VNPCR register **************/
<> 147:30b64687e01f 9766 #define DSI_VNPCR_NPSIZE 0x00001FFFU /*!< Null Packet Size */
<> 147:30b64687e01f 9767 #define DSI_VNPCR_NPSIZE0 0x00000001U
<> 147:30b64687e01f 9768 #define DSI_VNPCR_NPSIZE1 0x00000002U
<> 147:30b64687e01f 9769 #define DSI_VNPCR_NPSIZE2 0x00000004U
<> 147:30b64687e01f 9770 #define DSI_VNPCR_NPSIZE3 0x00000008U
<> 147:30b64687e01f 9771 #define DSI_VNPCR_NPSIZE4 0x00000010U
<> 147:30b64687e01f 9772 #define DSI_VNPCR_NPSIZE5 0x00000020U
<> 147:30b64687e01f 9773 #define DSI_VNPCR_NPSIZE6 0x00000040U
<> 147:30b64687e01f 9774 #define DSI_VNPCR_NPSIZE7 0x00000080U
<> 147:30b64687e01f 9775 #define DSI_VNPCR_NPSIZE8 0x00000100U
<> 147:30b64687e01f 9776 #define DSI_VNPCR_NPSIZE9 0x00000200U
<> 147:30b64687e01f 9777 #define DSI_VNPCR_NPSIZE10 0x00000400U
<> 147:30b64687e01f 9778 #define DSI_VNPCR_NPSIZE11 0x00000800U
<> 147:30b64687e01f 9779 #define DSI_VNPCR_NPSIZE12 0x00001000U
<> 147:30b64687e01f 9780
<> 147:30b64687e01f 9781 /******************* Bit definition for DSI_VHSACR register *************/
<> 147:30b64687e01f 9782 #define DSI_VHSACR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
<> 147:30b64687e01f 9783 #define DSI_VHSACR_HSA0 0x00000001U
<> 147:30b64687e01f 9784 #define DSI_VHSACR_HSA1 0x00000002U
<> 147:30b64687e01f 9785 #define DSI_VHSACR_HSA2 0x00000004U
<> 147:30b64687e01f 9786 #define DSI_VHSACR_HSA3 0x00000008U
<> 147:30b64687e01f 9787 #define DSI_VHSACR_HSA4 0x00000010U
<> 147:30b64687e01f 9788 #define DSI_VHSACR_HSA5 0x00000020U
<> 147:30b64687e01f 9789 #define DSI_VHSACR_HSA6 0x00000040U
<> 147:30b64687e01f 9790 #define DSI_VHSACR_HSA7 0x00000080U
<> 147:30b64687e01f 9791 #define DSI_VHSACR_HSA8 0x00000100U
<> 147:30b64687e01f 9792 #define DSI_VHSACR_HSA9 0x00000200U
<> 147:30b64687e01f 9793 #define DSI_VHSACR_HSA10 0x00000400U
<> 147:30b64687e01f 9794 #define DSI_VHSACR_HSA11 0x00000800U
<> 147:30b64687e01f 9795
<> 147:30b64687e01f 9796 /******************* Bit definition for DSI_VHBPCR register *************/
<> 147:30b64687e01f 9797 #define DSI_VHBPCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
<> 147:30b64687e01f 9798 #define DSI_VHBPCR_HBP0 0x00000001U
<> 147:30b64687e01f 9799 #define DSI_VHBPCR_HBP1 0x00000002U
<> 147:30b64687e01f 9800 #define DSI_VHBPCR_HBP2 0x00000004U
<> 147:30b64687e01f 9801 #define DSI_VHBPCR_HBP3 0x00000008U
<> 147:30b64687e01f 9802 #define DSI_VHBPCR_HBP4 0x00000010U
<> 147:30b64687e01f 9803 #define DSI_VHBPCR_HBP5 0x00000020U
<> 147:30b64687e01f 9804 #define DSI_VHBPCR_HBP6 0x00000040U
<> 147:30b64687e01f 9805 #define DSI_VHBPCR_HBP7 0x00000080U
<> 147:30b64687e01f 9806 #define DSI_VHBPCR_HBP8 0x00000100U
<> 147:30b64687e01f 9807 #define DSI_VHBPCR_HBP9 0x00000200U
<> 147:30b64687e01f 9808 #define DSI_VHBPCR_HBP10 0x00000400U
<> 147:30b64687e01f 9809 #define DSI_VHBPCR_HBP11 0x00000800U
<> 147:30b64687e01f 9810
<> 147:30b64687e01f 9811 /******************* Bit definition for DSI_VLCR register ***************/
<> 147:30b64687e01f 9812 #define DSI_VLCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
<> 147:30b64687e01f 9813 #define DSI_VLCR_HLINE0 0x00000001U
<> 147:30b64687e01f 9814 #define DSI_VLCR_HLINE1 0x00000002U
<> 147:30b64687e01f 9815 #define DSI_VLCR_HLINE2 0x00000004U
<> 147:30b64687e01f 9816 #define DSI_VLCR_HLINE3 0x00000008U
<> 147:30b64687e01f 9817 #define DSI_VLCR_HLINE4 0x00000010U
<> 147:30b64687e01f 9818 #define DSI_VLCR_HLINE5 0x00000020U
<> 147:30b64687e01f 9819 #define DSI_VLCR_HLINE6 0x00000040U
<> 147:30b64687e01f 9820 #define DSI_VLCR_HLINE7 0x00000080U
<> 147:30b64687e01f 9821 #define DSI_VLCR_HLINE8 0x00000100U
<> 147:30b64687e01f 9822 #define DSI_VLCR_HLINE9 0x00000200U
<> 147:30b64687e01f 9823 #define DSI_VLCR_HLINE10 0x00000400U
<> 147:30b64687e01f 9824 #define DSI_VLCR_HLINE11 0x00000800U
<> 147:30b64687e01f 9825 #define DSI_VLCR_HLINE12 0x00001000U
<> 147:30b64687e01f 9826 #define DSI_VLCR_HLINE13 0x00002000U
<> 147:30b64687e01f 9827 #define DSI_VLCR_HLINE14 0x00004000U
<> 147:30b64687e01f 9828
<> 147:30b64687e01f 9829 /******************* Bit definition for DSI_VVSACR register *************/
<> 147:30b64687e01f 9830 #define DSI_VVSACR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
<> 147:30b64687e01f 9831 #define DSI_VVSACR_VSA0 0x00000001U
<> 147:30b64687e01f 9832 #define DSI_VVSACR_VSA1 0x00000002U
<> 147:30b64687e01f 9833 #define DSI_VVSACR_VSA2 0x00000004U
<> 147:30b64687e01f 9834 #define DSI_VVSACR_VSA3 0x00000008U
<> 147:30b64687e01f 9835 #define DSI_VVSACR_VSA4 0x00000010U
<> 147:30b64687e01f 9836 #define DSI_VVSACR_VSA5 0x00000020U
<> 147:30b64687e01f 9837 #define DSI_VVSACR_VSA6 0x00000040U
<> 147:30b64687e01f 9838 #define DSI_VVSACR_VSA7 0x00000080U
<> 147:30b64687e01f 9839 #define DSI_VVSACR_VSA8 0x00000100U
<> 147:30b64687e01f 9840 #define DSI_VVSACR_VSA9 0x00000200U
<> 147:30b64687e01f 9841
<> 147:30b64687e01f 9842 /******************* Bit definition for DSI_VVBPCR register *************/
<> 147:30b64687e01f 9843 #define DSI_VVBPCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
<> 147:30b64687e01f 9844 #define DSI_VVBPCR_VBP0 0x00000001U
<> 147:30b64687e01f 9845 #define DSI_VVBPCR_VBP1 0x00000002U
<> 147:30b64687e01f 9846 #define DSI_VVBPCR_VBP2 0x00000004U
<> 147:30b64687e01f 9847 #define DSI_VVBPCR_VBP3 0x00000008U
<> 147:30b64687e01f 9848 #define DSI_VVBPCR_VBP4 0x00000010U
<> 147:30b64687e01f 9849 #define DSI_VVBPCR_VBP5 0x00000020U
<> 147:30b64687e01f 9850 #define DSI_VVBPCR_VBP6 0x00000040U
<> 147:30b64687e01f 9851 #define DSI_VVBPCR_VBP7 0x00000080U
<> 147:30b64687e01f 9852 #define DSI_VVBPCR_VBP8 0x00000100U
<> 147:30b64687e01f 9853 #define DSI_VVBPCR_VBP9 0x00000200U
<> 147:30b64687e01f 9854
<> 147:30b64687e01f 9855 /******************* Bit definition for DSI_VVFPCR register *************/
<> 147:30b64687e01f 9856 #define DSI_VVFPCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
<> 147:30b64687e01f 9857 #define DSI_VVFPCR_VFP0 0x00000001U
<> 147:30b64687e01f 9858 #define DSI_VVFPCR_VFP1 0x00000002U
<> 147:30b64687e01f 9859 #define DSI_VVFPCR_VFP2 0x00000004U
<> 147:30b64687e01f 9860 #define DSI_VVFPCR_VFP3 0x00000008U
<> 147:30b64687e01f 9861 #define DSI_VVFPCR_VFP4 0x00000010U
<> 147:30b64687e01f 9862 #define DSI_VVFPCR_VFP5 0x00000020U
<> 147:30b64687e01f 9863 #define DSI_VVFPCR_VFP6 0x00000040U
<> 147:30b64687e01f 9864 #define DSI_VVFPCR_VFP7 0x00000080U
<> 147:30b64687e01f 9865 #define DSI_VVFPCR_VFP8 0x00000100U
<> 147:30b64687e01f 9866 #define DSI_VVFPCR_VFP9 0x00000200U
<> 147:30b64687e01f 9867
<> 147:30b64687e01f 9868 /******************* Bit definition for DSI_VVACR register **************/
<> 147:30b64687e01f 9869 #define DSI_VVACR_VA 0x00003FFFU /*!< Vertical Active duration */
<> 147:30b64687e01f 9870 #define DSI_VVACR_VA0 0x00000001U
<> 147:30b64687e01f 9871 #define DSI_VVACR_VA1 0x00000002U
<> 147:30b64687e01f 9872 #define DSI_VVACR_VA2 0x00000004U
<> 147:30b64687e01f 9873 #define DSI_VVACR_VA3 0x00000008U
<> 147:30b64687e01f 9874 #define DSI_VVACR_VA4 0x00000010U
<> 147:30b64687e01f 9875 #define DSI_VVACR_VA5 0x00000020U
<> 147:30b64687e01f 9876 #define DSI_VVACR_VA6 0x00000040U
<> 147:30b64687e01f 9877 #define DSI_VVACR_VA7 0x00000080U
<> 147:30b64687e01f 9878 #define DSI_VVACR_VA8 0x00000100U
<> 147:30b64687e01f 9879 #define DSI_VVACR_VA9 0x00000200U
<> 147:30b64687e01f 9880 #define DSI_VVACR_VA10 0x00000400U
<> 147:30b64687e01f 9881 #define DSI_VVACR_VA11 0x00000800U
<> 147:30b64687e01f 9882 #define DSI_VVACR_VA12 0x00001000U
<> 147:30b64687e01f 9883 #define DSI_VVACR_VA13 0x00002000U
<> 147:30b64687e01f 9884
<> 147:30b64687e01f 9885 /******************* Bit definition for DSI_LCCR register ***************/
<> 147:30b64687e01f 9886 #define DSI_LCCR_CMDSIZE 0x0000FFFFU /*!< Command Size */
<> 147:30b64687e01f 9887 #define DSI_LCCR_CMDSIZE0 0x00000001U
<> 147:30b64687e01f 9888 #define DSI_LCCR_CMDSIZE1 0x00000002U
<> 147:30b64687e01f 9889 #define DSI_LCCR_CMDSIZE2 0x00000004U
<> 147:30b64687e01f 9890 #define DSI_LCCR_CMDSIZE3 0x00000008U
<> 147:30b64687e01f 9891 #define DSI_LCCR_CMDSIZE4 0x00000010U
<> 147:30b64687e01f 9892 #define DSI_LCCR_CMDSIZE5 0x00000020U
<> 147:30b64687e01f 9893 #define DSI_LCCR_CMDSIZE6 0x00000040U
<> 147:30b64687e01f 9894 #define DSI_LCCR_CMDSIZE7 0x00000080U
<> 147:30b64687e01f 9895 #define DSI_LCCR_CMDSIZE8 0x00000100U
<> 147:30b64687e01f 9896 #define DSI_LCCR_CMDSIZE9 0x00000200U
<> 147:30b64687e01f 9897 #define DSI_LCCR_CMDSIZE10 0x00000400U
<> 147:30b64687e01f 9898 #define DSI_LCCR_CMDSIZE11 0x00000800U
<> 147:30b64687e01f 9899 #define DSI_LCCR_CMDSIZE12 0x00001000U
<> 147:30b64687e01f 9900 #define DSI_LCCR_CMDSIZE13 0x00002000U
<> 147:30b64687e01f 9901 #define DSI_LCCR_CMDSIZE14 0x00004000U
<> 147:30b64687e01f 9902 #define DSI_LCCR_CMDSIZE15 0x00008000U
<> 147:30b64687e01f 9903
<> 147:30b64687e01f 9904 /******************* Bit definition for DSI_CMCR register ***************/
<> 147:30b64687e01f 9905 #define DSI_CMCR_TEARE 0x00000001U /*!< Tearing Effect Acknowledge Request Enable */
<> 147:30b64687e01f 9906 #define DSI_CMCR_ARE 0x00000002U /*!< Acknowledge Request Enable */
<> 147:30b64687e01f 9907 #define DSI_CMCR_GSW0TX 0x00000100U /*!< Generic Short Write Zero parameters Transmission */
<> 147:30b64687e01f 9908 #define DSI_CMCR_GSW1TX 0x00000200U /*!< Generic Short Write One parameters Transmission */
<> 147:30b64687e01f 9909 #define DSI_CMCR_GSW2TX 0x00000400U /*!< Generic Short Write Two parameters Transmission */
<> 147:30b64687e01f 9910 #define DSI_CMCR_GSR0TX 0x00000800U /*!< Generic Short Read Zero parameters Transmission */
<> 147:30b64687e01f 9911 #define DSI_CMCR_GSR1TX 0x00001000U /*!< Generic Short Read One parameters Transmission */
<> 147:30b64687e01f 9912 #define DSI_CMCR_GSR2TX 0x00002000U /*!< Generic Short Read Two parameters Transmission */
<> 147:30b64687e01f 9913 #define DSI_CMCR_GLWTX 0x00004000U /*!< Generic Long Write Transmission */
<> 147:30b64687e01f 9914 #define DSI_CMCR_DSW0TX 0x00010000U /*!< DCS Short Write Zero parameter Transmission */
<> 147:30b64687e01f 9915 #define DSI_CMCR_DSW1TX 0x00020000U /*!< DCS Short Read One parameter Transmission */
<> 147:30b64687e01f 9916 #define DSI_CMCR_DSR0TX 0x00040000U /*!< DCS Short Read Zero parameter Transmission */
<> 147:30b64687e01f 9917 #define DSI_CMCR_DLWTX 0x00080000U /*!< DCS Long Write Transmission */
<> 147:30b64687e01f 9918 #define DSI_CMCR_MRDPS 0x01000000U /*!< Maximum Read Packet Size */
<> 147:30b64687e01f 9919
<> 147:30b64687e01f 9920 /******************* Bit definition for DSI_GHCR register ***************/
<> 147:30b64687e01f 9921 #define DSI_GHCR_DT 0x0000003FU /*!< Type */
<> 147:30b64687e01f 9922 #define DSI_GHCR_DT0 0x00000001U
<> 147:30b64687e01f 9923 #define DSI_GHCR_DT1 0x00000002U
<> 147:30b64687e01f 9924 #define DSI_GHCR_DT2 0x00000004U
<> 147:30b64687e01f 9925 #define DSI_GHCR_DT3 0x00000008U
<> 147:30b64687e01f 9926 #define DSI_GHCR_DT4 0x00000010U
<> 147:30b64687e01f 9927 #define DSI_GHCR_DT5 0x00000020U
<> 147:30b64687e01f 9928
<> 147:30b64687e01f 9929 #define DSI_GHCR_VCID 0x000000C0U /*!< Channel */
<> 147:30b64687e01f 9930 #define DSI_GHCR_VCID0 0x00000040U
<> 147:30b64687e01f 9931 #define DSI_GHCR_VCID1 0x00000080U
<> 147:30b64687e01f 9932
<> 147:30b64687e01f 9933 #define DSI_GHCR_WCLSB 0x0000FF00U /*!< WordCount LSB */
<> 147:30b64687e01f 9934 #define DSI_GHCR_WCLSB0 0x00000100U
<> 147:30b64687e01f 9935 #define DSI_GHCR_WCLSB1 0x00000200U
<> 147:30b64687e01f 9936 #define DSI_GHCR_WCLSB2 0x00000400U
<> 147:30b64687e01f 9937 #define DSI_GHCR_WCLSB3 0x00000800U
<> 147:30b64687e01f 9938 #define DSI_GHCR_WCLSB4 0x00001000U
<> 147:30b64687e01f 9939 #define DSI_GHCR_WCLSB5 0x00002000U
<> 147:30b64687e01f 9940 #define DSI_GHCR_WCLSB6 0x00004000U
<> 147:30b64687e01f 9941 #define DSI_GHCR_WCLSB7 0x00008000U
<> 147:30b64687e01f 9942
<> 147:30b64687e01f 9943 #define DSI_GHCR_WCMSB 0x00FF0000U /*!< WordCount MSB */
<> 147:30b64687e01f 9944 #define DSI_GHCR_WCMSB0 0x00010000U
<> 147:30b64687e01f 9945 #define DSI_GHCR_WCMSB1 0x00020000U
<> 147:30b64687e01f 9946 #define DSI_GHCR_WCMSB2 0x00040000U
<> 147:30b64687e01f 9947 #define DSI_GHCR_WCMSB3 0x00080000U
<> 147:30b64687e01f 9948 #define DSI_GHCR_WCMSB4 0x00100000U
<> 147:30b64687e01f 9949 #define DSI_GHCR_WCMSB5 0x00200000U
<> 147:30b64687e01f 9950 #define DSI_GHCR_WCMSB6 0x00400000U
<> 147:30b64687e01f 9951 #define DSI_GHCR_WCMSB7 0x00800000U
<> 147:30b64687e01f 9952
<> 147:30b64687e01f 9953 /******************* Bit definition for DSI_GPDR register ***************/
<> 147:30b64687e01f 9954 #define DSI_GPDR_DATA1 0x000000FFU /*!< Payload Byte 1 */
<> 147:30b64687e01f 9955 #define DSI_GPDR_DATA1_0 0x00000001U
<> 147:30b64687e01f 9956 #define DSI_GPDR_DATA1_1 0x00000002U
<> 147:30b64687e01f 9957 #define DSI_GPDR_DATA1_2 0x00000004U
<> 147:30b64687e01f 9958 #define DSI_GPDR_DATA1_3 0x00000008U
<> 147:30b64687e01f 9959 #define DSI_GPDR_DATA1_4 0x00000010U
<> 147:30b64687e01f 9960 #define DSI_GPDR_DATA1_5 0x00000020U
<> 147:30b64687e01f 9961 #define DSI_GPDR_DATA1_6 0x00000040U
<> 147:30b64687e01f 9962 #define DSI_GPDR_DATA1_7 0x00000080U
<> 147:30b64687e01f 9963
<> 147:30b64687e01f 9964 #define DSI_GPDR_DATA2 0x0000FF00U /*!< Payload Byte 2 */
<> 147:30b64687e01f 9965 #define DSI_GPDR_DATA2_0 0x00000100U
<> 147:30b64687e01f 9966 #define DSI_GPDR_DATA2_1 0x00000200U
<> 147:30b64687e01f 9967 #define DSI_GPDR_DATA2_2 0x00000400U
<> 147:30b64687e01f 9968 #define DSI_GPDR_DATA2_3 0x00000800U
<> 147:30b64687e01f 9969 #define DSI_GPDR_DATA2_4 0x00001000U
<> 147:30b64687e01f 9970 #define DSI_GPDR_DATA2_5 0x00002000U
<> 147:30b64687e01f 9971 #define DSI_GPDR_DATA2_6 0x00004000U
<> 147:30b64687e01f 9972 #define DSI_GPDR_DATA2_7 0x00008000U
<> 147:30b64687e01f 9973
<> 147:30b64687e01f 9974 #define DSI_GPDR_DATA3 0x00FF0000U /*!< Payload Byte 3 */
<> 147:30b64687e01f 9975 #define DSI_GPDR_DATA3_0 0x00010000U
<> 147:30b64687e01f 9976 #define DSI_GPDR_DATA3_1 0x00020000U
<> 147:30b64687e01f 9977 #define DSI_GPDR_DATA3_2 0x00040000U
<> 147:30b64687e01f 9978 #define DSI_GPDR_DATA3_3 0x00080000U
<> 147:30b64687e01f 9979 #define DSI_GPDR_DATA3_4 0x00100000U
<> 147:30b64687e01f 9980 #define DSI_GPDR_DATA3_5 0x00200000U
<> 147:30b64687e01f 9981 #define DSI_GPDR_DATA3_6 0x00400000U
<> 147:30b64687e01f 9982 #define DSI_GPDR_DATA3_7 0x00800000U
<> 147:30b64687e01f 9983
<> 147:30b64687e01f 9984 #define DSI_GPDR_DATA4 0xFF000000U /*!< Payload Byte 4 */
<> 147:30b64687e01f 9985 #define DSI_GPDR_DATA4_0 0x01000000U
<> 147:30b64687e01f 9986 #define DSI_GPDR_DATA4_1 0x02000000U
<> 147:30b64687e01f 9987 #define DSI_GPDR_DATA4_2 0x04000000U
<> 147:30b64687e01f 9988 #define DSI_GPDR_DATA4_3 0x08000000U
<> 147:30b64687e01f 9989 #define DSI_GPDR_DATA4_4 0x10000000U
<> 147:30b64687e01f 9990 #define DSI_GPDR_DATA4_5 0x20000000U
<> 147:30b64687e01f 9991 #define DSI_GPDR_DATA4_6 0x40000000U
<> 147:30b64687e01f 9992 #define DSI_GPDR_DATA4_7 0x80000000U
<> 147:30b64687e01f 9993
<> 147:30b64687e01f 9994 /******************* Bit definition for DSI_GPSR register ***************/
<> 147:30b64687e01f 9995 #define DSI_GPSR_CMDFE 0x00000001U /*!< Command FIFO Empty */
<> 147:30b64687e01f 9996 #define DSI_GPSR_CMDFF 0x00000002U /*!< Command FIFO Full */
<> 147:30b64687e01f 9997 #define DSI_GPSR_PWRFE 0x00000004U /*!< Payload Write FIFO Empty */
<> 147:30b64687e01f 9998 #define DSI_GPSR_PWRFF 0x00000008U /*!< Payload Write FIFO Full */
<> 147:30b64687e01f 9999 #define DSI_GPSR_PRDFE 0x00000010U /*!< Payload Read FIFO Empty */
<> 147:30b64687e01f 10000 #define DSI_GPSR_PRDFF 0x00000020U /*!< Payload Read FIFO Full */
<> 147:30b64687e01f 10001 #define DSI_GPSR_RCB 0x00000040U /*!< Read Command Busy */
<> 147:30b64687e01f 10002
<> 147:30b64687e01f 10003 /******************* Bit definition for DSI_TCCR0register **************/
<> 147:30b64687e01f 10004 #define DSI_TCCR0_LPRX_TOCNT 0x0000FFFFU /*!< Low-power Reception Timeout Counter */
<> 147:30b64687e01f 10005 #define DSI_TCCR0_LPRX_TOCNT0 0x00000001U
<> 147:30b64687e01f 10006 #define DSI_TCCR0_LPRX_TOCNT1 0x00000002U
<> 147:30b64687e01f 10007 #define DSI_TCCR0_LPRX_TOCNT2 0x00000004U
<> 147:30b64687e01f 10008 #define DSI_TCCR0_LPRX_TOCNT3 0x00000008U
<> 147:30b64687e01f 10009 #define DSI_TCCR0_LPRX_TOCNT4 0x00000010U
<> 147:30b64687e01f 10010 #define DSI_TCCR0_LPRX_TOCNT5 0x00000020U
<> 147:30b64687e01f 10011 #define DSI_TCCR0_LPRX_TOCNT6 0x00000040U
<> 147:30b64687e01f 10012 #define DSI_TCCR0_LPRX_TOCNT7 0x00000080U
<> 147:30b64687e01f 10013 #define DSI_TCCR0_LPRX_TOCNT8 0x00000100U
<> 147:30b64687e01f 10014 #define DSI_TCCR0_LPRX_TOCNT9 0x00000200U
<> 147:30b64687e01f 10015 #define DSI_TCCR0_LPRX_TOCNT10 0x00000400U
<> 147:30b64687e01f 10016 #define DSI_TCCR0_LPRX_TOCNT11 0x00000800U
<> 147:30b64687e01f 10017 #define DSI_TCCR0_LPRX_TOCNT12 0x00001000U
<> 147:30b64687e01f 10018 #define DSI_TCCR0_LPRX_TOCNT13 0x00002000U
<> 147:30b64687e01f 10019 #define DSI_TCCR0_LPRX_TOCNT14 0x00004000U
<> 147:30b64687e01f 10020 #define DSI_TCCR0_LPRX_TOCNT15 0x00008000U
<> 147:30b64687e01f 10021
<> 147:30b64687e01f 10022 #define DSI_TCCR0_HSTX_TOCNT 0xFFFF0000U /*!< High-Speed Transmission Timeout Counter */
<> 147:30b64687e01f 10023 #define DSI_TCCR0_HSTX_TOCNT0 0x00010000U
<> 147:30b64687e01f 10024 #define DSI_TCCR0_HSTX_TOCNT1 0x00020000U
<> 147:30b64687e01f 10025 #define DSI_TCCR0_HSTX_TOCNT2 0x00040000U
<> 147:30b64687e01f 10026 #define DSI_TCCR0_HSTX_TOCNT3 0x00080000U
<> 147:30b64687e01f 10027 #define DSI_TCCR0_HSTX_TOCNT4 0x00100000U
<> 147:30b64687e01f 10028 #define DSI_TCCR0_HSTX_TOCNT5 0x00200000U
<> 147:30b64687e01f 10029 #define DSI_TCCR0_HSTX_TOCNT6 0x00400000U
<> 147:30b64687e01f 10030 #define DSI_TCCR0_HSTX_TOCNT7 0x00800000U
<> 147:30b64687e01f 10031 #define DSI_TCCR0_HSTX_TOCNT8 0x01000000U
<> 147:30b64687e01f 10032 #define DSI_TCCR0_HSTX_TOCNT9 0x02000000U
<> 147:30b64687e01f 10033 #define DSI_TCCR0_HSTX_TOCNT10 0x04000000U
<> 147:30b64687e01f 10034 #define DSI_TCCR0_HSTX_TOCNT11 0x08000000U
<> 147:30b64687e01f 10035 #define DSI_TCCR0_HSTX_TOCNT12 0x10000000U
<> 147:30b64687e01f 10036 #define DSI_TCCR0_HSTX_TOCNT13 0x20000000U
<> 147:30b64687e01f 10037 #define DSI_TCCR0_HSTX_TOCNT14 0x40000000U
<> 147:30b64687e01f 10038 #define DSI_TCCR0_HSTX_TOCNT15 0x80000000U
<> 147:30b64687e01f 10039
<> 147:30b64687e01f 10040 /******************* Bit definition for DSI_TCCR1register **************/
<> 147:30b64687e01f 10041 #define DSI_TCCR1_HSRD_TOCNT 0x0000FFFFU /*!< High-Speed Read Timeout Counter */
<> 147:30b64687e01f 10042 #define DSI_TCCR1_HSRD_TOCNT0 0x00000001U
<> 147:30b64687e01f 10043 #define DSI_TCCR1_HSRD_TOCNT1 0x00000002U
<> 147:30b64687e01f 10044 #define DSI_TCCR1_HSRD_TOCNT2 0x00000004U
<> 147:30b64687e01f 10045 #define DSI_TCCR1_HSRD_TOCNT3 0x00000008U
<> 147:30b64687e01f 10046 #define DSI_TCCR1_HSRD_TOCNT4 0x00000010U
<> 147:30b64687e01f 10047 #define DSI_TCCR1_HSRD_TOCNT5 0x00000020U
<> 147:30b64687e01f 10048 #define DSI_TCCR1_HSRD_TOCNT6 0x00000040U
<> 147:30b64687e01f 10049 #define DSI_TCCR1_HSRD_TOCNT7 0x00000080U
<> 147:30b64687e01f 10050 #define DSI_TCCR1_HSRD_TOCNT8 0x00000100U
<> 147:30b64687e01f 10051 #define DSI_TCCR1_HSRD_TOCNT9 0x00000200U
<> 147:30b64687e01f 10052 #define DSI_TCCR1_HSRD_TOCNT10 0x00000400U
<> 147:30b64687e01f 10053 #define DSI_TCCR1_HSRD_TOCNT11 0x00000800U
<> 147:30b64687e01f 10054 #define DSI_TCCR1_HSRD_TOCNT12 0x00001000U
<> 147:30b64687e01f 10055 #define DSI_TCCR1_HSRD_TOCNT13 0x00002000U
<> 147:30b64687e01f 10056 #define DSI_TCCR1_HSRD_TOCNT14 0x00004000U
<> 147:30b64687e01f 10057 #define DSI_TCCR1_HSRD_TOCNT15 0x00008000U
<> 147:30b64687e01f 10058
<> 147:30b64687e01f 10059 /******************* Bit definition for DSI_TCCR2 register **************/
<> 147:30b64687e01f 10060 #define DSI_TCCR2_LPRD_TOCNT 0x0000FFFFU /*!< Low-Power Read Timeout Counter */
<> 147:30b64687e01f 10061 #define DSI_TCCR2_LPRD_TOCNT0 0x00000001U
<> 147:30b64687e01f 10062 #define DSI_TCCR2_LPRD_TOCNT1 0x00000002U
<> 147:30b64687e01f 10063 #define DSI_TCCR2_LPRD_TOCNT2 0x00000004U
<> 147:30b64687e01f 10064 #define DSI_TCCR2_LPRD_TOCNT3 0x00000008U
<> 147:30b64687e01f 10065 #define DSI_TCCR2_LPRD_TOCNT4 0x00000010U
<> 147:30b64687e01f 10066 #define DSI_TCCR2_LPRD_TOCNT5 0x00000020U
<> 147:30b64687e01f 10067 #define DSI_TCCR2_LPRD_TOCNT6 0x00000040U
<> 147:30b64687e01f 10068 #define DSI_TCCR2_LPRD_TOCNT7 0x00000080U
<> 147:30b64687e01f 10069 #define DSI_TCCR2_LPRD_TOCNT8 0x00000100U
<> 147:30b64687e01f 10070 #define DSI_TCCR2_LPRD_TOCNT9 0x00000200U
<> 147:30b64687e01f 10071 #define DSI_TCCR2_LPRD_TOCNT10 0x00000400U
<> 147:30b64687e01f 10072 #define DSI_TCCR2_LPRD_TOCNT11 0x00000800U
<> 147:30b64687e01f 10073 #define DSI_TCCR2_LPRD_TOCNT12 0x00001000U
<> 147:30b64687e01f 10074 #define DSI_TCCR2_LPRD_TOCNT13 0x00002000U
<> 147:30b64687e01f 10075 #define DSI_TCCR2_LPRD_TOCNT14 0x00004000U
<> 147:30b64687e01f 10076 #define DSI_TCCR2_LPRD_TOCNT15 0x00008000U
<> 147:30b64687e01f 10077
<> 147:30b64687e01f 10078 /******************* Bit definition for DSI_TCCR3 register **************/
<> 147:30b64687e01f 10079 #define DSI_TCCR3_HSWR_TOCNT 0x0000FFFFU /*!< High-Speed Write Timeout Counter */
<> 147:30b64687e01f 10080 #define DSI_TCCR3_HSWR_TOCNT0 0x00000001U
<> 147:30b64687e01f 10081 #define DSI_TCCR3_HSWR_TOCNT1 0x00000002U
<> 147:30b64687e01f 10082 #define DSI_TCCR3_HSWR_TOCNT2 0x00000004U
<> 147:30b64687e01f 10083 #define DSI_TCCR3_HSWR_TOCNT3 0x00000008U
<> 147:30b64687e01f 10084 #define DSI_TCCR3_HSWR_TOCNT4 0x00000010U
<> 147:30b64687e01f 10085 #define DSI_TCCR3_HSWR_TOCNT5 0x00000020U
<> 147:30b64687e01f 10086 #define DSI_TCCR3_HSWR_TOCNT6 0x00000040U
<> 147:30b64687e01f 10087 #define DSI_TCCR3_HSWR_TOCNT7 0x00000080U
<> 147:30b64687e01f 10088 #define DSI_TCCR3_HSWR_TOCNT8 0x00000100U
<> 147:30b64687e01f 10089 #define DSI_TCCR3_HSWR_TOCNT9 0x00000200U
<> 147:30b64687e01f 10090 #define DSI_TCCR3_HSWR_TOCNT10 0x00000400U
<> 147:30b64687e01f 10091 #define DSI_TCCR3_HSWR_TOCNT11 0x00000800U
<> 147:30b64687e01f 10092 #define DSI_TCCR3_HSWR_TOCNT12 0x00001000U
<> 147:30b64687e01f 10093 #define DSI_TCCR3_HSWR_TOCNT13 0x00002000U
<> 147:30b64687e01f 10094 #define DSI_TCCR3_HSWR_TOCNT14 0x00004000U
<> 147:30b64687e01f 10095 #define DSI_TCCR3_HSWR_TOCNT15 0x00008000U
<> 147:30b64687e01f 10096
<> 147:30b64687e01f 10097 #define DSI_TCCR3_PM 0x01000000U /*!< Presp Mode */
<> 147:30b64687e01f 10098
<> 147:30b64687e01f 10099 /******************* Bit definition for DSI_TCCR4 register **************/
<> 147:30b64687e01f 10100 #define DSI_TCCR4_LPWR_TOCNT 0x0000FFFFU /*!< Low-Power Write Timeout Counter */
<> 147:30b64687e01f 10101 #define DSI_TCCR4_LPWR_TOCNT0 0x00000001U
<> 147:30b64687e01f 10102 #define DSI_TCCR4_LPWR_TOCNT1 0x00000002U
<> 147:30b64687e01f 10103 #define DSI_TCCR4_LPWR_TOCNT2 0x00000004U
<> 147:30b64687e01f 10104 #define DSI_TCCR4_LPWR_TOCNT3 0x00000008U
<> 147:30b64687e01f 10105 #define DSI_TCCR4_LPWR_TOCNT4 0x00000010U
<> 147:30b64687e01f 10106 #define DSI_TCCR4_LPWR_TOCNT5 0x00000020U
<> 147:30b64687e01f 10107 #define DSI_TCCR4_LPWR_TOCNT6 0x00000040U
<> 147:30b64687e01f 10108 #define DSI_TCCR4_LPWR_TOCNT7 0x00000080U
<> 147:30b64687e01f 10109 #define DSI_TCCR4_LPWR_TOCNT8 0x00000100U
<> 147:30b64687e01f 10110 #define DSI_TCCR4_LPWR_TOCNT9 0x00000200U
<> 147:30b64687e01f 10111 #define DSI_TCCR4_LPWR_TOCNT10 0x00000400U
<> 147:30b64687e01f 10112 #define DSI_TCCR4_LPWR_TOCNT11 0x00000800U
<> 147:30b64687e01f 10113 #define DSI_TCCR4_LPWR_TOCNT12 0x00001000U
<> 147:30b64687e01f 10114 #define DSI_TCCR4_LPWR_TOCNT13 0x00002000U
<> 147:30b64687e01f 10115 #define DSI_TCCR4_LPWR_TOCNT14 0x00004000U
<> 147:30b64687e01f 10116 #define DSI_TCCR4_LPWR_TOCNT15 0x00008000U
<> 147:30b64687e01f 10117
<> 147:30b64687e01f 10118 /******************* Bit definition for DSI_TCCR5register **************/
<> 147:30b64687e01f 10119 #define DSI_TCCR5_BTA_TOCNT 0x0000FFFFU /*!< Bus-Turn-Around Timeout Counter */
<> 147:30b64687e01f 10120 #define DSI_TCCR5_BTA_TOCNT0 0x00000001U
<> 147:30b64687e01f 10121 #define DSI_TCCR5_BTA_TOCNT1 0x00000002U
<> 147:30b64687e01f 10122 #define DSI_TCCR5_BTA_TOCNT2 0x00000004U
<> 147:30b64687e01f 10123 #define DSI_TCCR5_BTA_TOCNT3 0x00000008U
<> 147:30b64687e01f 10124 #define DSI_TCCR5_BTA_TOCNT4 0x00000010U
<> 147:30b64687e01f 10125 #define DSI_TCCR5_BTA_TOCNT5 0x00000020U
<> 147:30b64687e01f 10126 #define DSI_TCCR5_BTA_TOCNT6 0x00000040U
<> 147:30b64687e01f 10127 #define DSI_TCCR5_BTA_TOCNT7 0x00000080U
<> 147:30b64687e01f 10128 #define DSI_TCCR5_BTA_TOCNT8 0x00000100U
<> 147:30b64687e01f 10129 #define DSI_TCCR5_BTA_TOCNT9 0x00000200U
<> 147:30b64687e01f 10130 #define DSI_TCCR5_BTA_TOCNT10 0x00000400U
<> 147:30b64687e01f 10131 #define DSI_TCCR5_BTA_TOCNT11 0x00000800U
<> 147:30b64687e01f 10132 #define DSI_TCCR5_BTA_TOCNT12 0x00001000U
<> 147:30b64687e01f 10133 #define DSI_TCCR5_BTA_TOCNT13 0x00002000U
<> 147:30b64687e01f 10134 #define DSI_TCCR5_BTA_TOCNT14 0x00004000U
<> 147:30b64687e01f 10135 #define DSI_TCCR5_BTA_TOCNT15 0x00008000U
<> 147:30b64687e01f 10136
<> 147:30b64687e01f 10137 /******************* Bit definition for DSI_TDCR register ***************/
<> 147:30b64687e01f 10138 #define DSI_TDCR_3DM 0x00000003U /*!< 3D Mode */
<> 147:30b64687e01f 10139 #define DSI_TDCR_3DM0 0x00000001U
<> 147:30b64687e01f 10140 #define DSI_TDCR_3DM1 0x00000002U
<> 147:30b64687e01f 10141
<> 147:30b64687e01f 10142 #define DSI_TDCR_3DF 0x0000000CU /*!< 3D Format */
<> 147:30b64687e01f 10143 #define DSI_TDCR_3DF0 0x00000004U
<> 147:30b64687e01f 10144 #define DSI_TDCR_3DF1 0x00000008U
<> 147:30b64687e01f 10145
<> 147:30b64687e01f 10146 #define DSI_TDCR_SVS 0x00000010U /*!< Second VSYNC */
<> 147:30b64687e01f 10147 #define DSI_TDCR_RF 0x00000020U /*!< Right First */
<> 147:30b64687e01f 10148 #define DSI_TDCR_S3DC 0x00010000U /*!< Send 3D Control */
<> 147:30b64687e01f 10149
<> 147:30b64687e01f 10150 /******************* Bit definition for DSI_CLCR register ***************/
<> 147:30b64687e01f 10151 #define DSI_CLCR_DPCC 0x00000001U /*!< D-PHY Clock Control */
<> 147:30b64687e01f 10152 #define DSI_CLCR_ACR 0x00000002U /*!< Automatic Clocklane Control */
<> 147:30b64687e01f 10153
<> 147:30b64687e01f 10154 /******************* Bit definition for DSI_CLTCR register **************/
<> 147:30b64687e01f 10155 #define DSI_CLTCR_LP2HS_TIME 0x000003FFU /*!< Low-Power to High-Speed Time */
<> 147:30b64687e01f 10156 #define DSI_CLTCR_LP2HS_TIME0 0x00000001U
<> 147:30b64687e01f 10157 #define DSI_CLTCR_LP2HS_TIME1 0x00000002U
<> 147:30b64687e01f 10158 #define DSI_CLTCR_LP2HS_TIME2 0x00000004U
<> 147:30b64687e01f 10159 #define DSI_CLTCR_LP2HS_TIME3 0x00000008U
<> 147:30b64687e01f 10160 #define DSI_CLTCR_LP2HS_TIME4 0x00000010U
<> 147:30b64687e01f 10161 #define DSI_CLTCR_LP2HS_TIME5 0x00000020U
<> 147:30b64687e01f 10162 #define DSI_CLTCR_LP2HS_TIME6 0x00000040U
<> 147:30b64687e01f 10163 #define DSI_CLTCR_LP2HS_TIME7 0x00000080U
<> 147:30b64687e01f 10164 #define DSI_CLTCR_LP2HS_TIME8 0x00000100U
<> 147:30b64687e01f 10165 #define DSI_CLTCR_LP2HS_TIME9 0x00000200U
<> 147:30b64687e01f 10166
<> 147:30b64687e01f 10167 #define DSI_CLTCR_HS2LP_TIME 0x03FF0000U /*!< High-Speed to Low-Power Time */
<> 147:30b64687e01f 10168 #define DSI_CLTCR_HS2LP_TIME0 0x00010000U
<> 147:30b64687e01f 10169 #define DSI_CLTCR_HS2LP_TIME1 0x00020000U
<> 147:30b64687e01f 10170 #define DSI_CLTCR_HS2LP_TIME2 0x00040000U
<> 147:30b64687e01f 10171 #define DSI_CLTCR_HS2LP_TIME3 0x00080000U
<> 147:30b64687e01f 10172 #define DSI_CLTCR_HS2LP_TIME4 0x00100000U
<> 147:30b64687e01f 10173 #define DSI_CLTCR_HS2LP_TIME5 0x00200000U
<> 147:30b64687e01f 10174 #define DSI_CLTCR_HS2LP_TIME6 0x00400000U
<> 147:30b64687e01f 10175 #define DSI_CLTCR_HS2LP_TIME7 0x00800000U
<> 147:30b64687e01f 10176 #define DSI_CLTCR_HS2LP_TIME8 0x01000000U
<> 147:30b64687e01f 10177 #define DSI_CLTCR_HS2LP_TIME9 0x02000000U
<> 147:30b64687e01f 10178
<> 147:30b64687e01f 10179 /******************* Bit definition for DSI_DLTCR register **************/
<> 147:30b64687e01f 10180 #define DSI_DLTCR_MRD_TIME 0x00007FFFU /*!< Maximum Read Time */
<> 147:30b64687e01f 10181 #define DSI_DLTCR_MRD_TIME0 0x00000001U
<> 147:30b64687e01f 10182 #define DSI_DLTCR_MRD_TIME1 0x00000002U
<> 147:30b64687e01f 10183 #define DSI_DLTCR_MRD_TIME2 0x00000004U
<> 147:30b64687e01f 10184 #define DSI_DLTCR_MRD_TIME3 0x00000008U
<> 147:30b64687e01f 10185 #define DSI_DLTCR_MRD_TIME4 0x00000010U
<> 147:30b64687e01f 10186 #define DSI_DLTCR_MRD_TIME5 0x00000020U
<> 147:30b64687e01f 10187 #define DSI_DLTCR_MRD_TIME6 0x00000040U
<> 147:30b64687e01f 10188 #define DSI_DLTCR_MRD_TIME7 0x00000080U
<> 147:30b64687e01f 10189 #define DSI_DLTCR_MRD_TIME8 0x00000100U
<> 147:30b64687e01f 10190 #define DSI_DLTCR_MRD_TIME9 0x00000200U
<> 147:30b64687e01f 10191 #define DSI_DLTCR_MRD_TIME10 0x00000400U
<> 147:30b64687e01f 10192 #define DSI_DLTCR_MRD_TIME11 0x00000800U
<> 147:30b64687e01f 10193 #define DSI_DLTCR_MRD_TIME12 0x00001000U
<> 147:30b64687e01f 10194 #define DSI_DLTCR_MRD_TIME13 0x00002000U
<> 147:30b64687e01f 10195 #define DSI_DLTCR_MRD_TIME14 0x00004000U
<> 147:30b64687e01f 10196
<> 147:30b64687e01f 10197 #define DSI_DLTCR_LP2HS_TIME 0x00FF0000U /*!< Low-Power To High-Speed Time */
<> 147:30b64687e01f 10198 #define DSI_DLTCR_LP2HS_TIME0 0x00010000U
<> 147:30b64687e01f 10199 #define DSI_DLTCR_LP2HS_TIME1 0x00020000U
<> 147:30b64687e01f 10200 #define DSI_DLTCR_LP2HS_TIME2 0x00040000U
<> 147:30b64687e01f 10201 #define DSI_DLTCR_LP2HS_TIME3 0x00080000U
<> 147:30b64687e01f 10202 #define DSI_DLTCR_LP2HS_TIME4 0x00100000U
<> 147:30b64687e01f 10203 #define DSI_DLTCR_LP2HS_TIME5 0x00200000U
<> 147:30b64687e01f 10204 #define DSI_DLTCR_LP2HS_TIME6 0x00400000U
<> 147:30b64687e01f 10205 #define DSI_DLTCR_LP2HS_TIME7 0x00800000U
<> 147:30b64687e01f 10206
<> 147:30b64687e01f 10207 #define DSI_DLTCR_HS2LP_TIME 0xFF000000U /*!< High-Speed To Low-Power Time */
<> 147:30b64687e01f 10208 #define DSI_DLTCR_HS2LP_TIME0 0x01000000U
<> 147:30b64687e01f 10209 #define DSI_DLTCR_HS2LP_TIME1 0x02000000U
<> 147:30b64687e01f 10210 #define DSI_DLTCR_HS2LP_TIME2 0x04000000U
<> 147:30b64687e01f 10211 #define DSI_DLTCR_HS2LP_TIME3 0x08000000U
<> 147:30b64687e01f 10212 #define DSI_DLTCR_HS2LP_TIME4 0x10000000U
<> 147:30b64687e01f 10213 #define DSI_DLTCR_HS2LP_TIME5 0x20000000U
<> 147:30b64687e01f 10214 #define DSI_DLTCR_HS2LP_TIME6 0x40000000U
<> 147:30b64687e01f 10215 #define DSI_DLTCR_HS2LP_TIME7 0x80000000U
<> 147:30b64687e01f 10216
<> 147:30b64687e01f 10217 /******************* Bit definition for DSI_PCTLRregister **************/
<> 147:30b64687e01f 10218 #define DSI_PCTLR_DEN 0x00000002U /*!< Digital Enable */
<> 147:30b64687e01f 10219 #define DSI_PCTLR_CKE 0x00000004U /*!< Clock Enable */
<> 147:30b64687e01f 10220
<> 147:30b64687e01f 10221 /******************* Bit definition for DSI_PCONFR register *************/
<> 147:30b64687e01f 10222 #define DSI_PCONFR_NL 0x00000003U /*!< Number of Lanes */
<> 147:30b64687e01f 10223 #define DSI_PCONFR_NL0 0x00000001U
<> 147:30b64687e01f 10224 #define DSI_PCONFR_NL1 0x00000002U
<> 147:30b64687e01f 10225
<> 147:30b64687e01f 10226 #define DSI_PCONFR_SW_TIME 0x0000FF00U /*!< Stop Wait Time */
<> 147:30b64687e01f 10227 #define DSI_PCONFR_SW_TIME0 0x00000100U
<> 147:30b64687e01f 10228 #define DSI_PCONFR_SW_TIME1 0x00000200U
<> 147:30b64687e01f 10229 #define DSI_PCONFR_SW_TIME2 0x00000400U
<> 147:30b64687e01f 10230 #define DSI_PCONFR_SW_TIME3 0x00000800U
<> 147:30b64687e01f 10231 #define DSI_PCONFR_SW_TIME4 0x00001000U
<> 147:30b64687e01f 10232 #define DSI_PCONFR_SW_TIME5 0x00002000U
<> 147:30b64687e01f 10233 #define DSI_PCONFR_SW_TIME6 0x00004000U
<> 147:30b64687e01f 10234 #define DSI_PCONFR_SW_TIME7 0x00008000U
<> 147:30b64687e01f 10235
<> 147:30b64687e01f 10236 /******************* Bit definition for DSI_PUCR register ***************/
<> 147:30b64687e01f 10237 #define DSI_PUCR_URCL 0x00000001U /*!< ULPS Request on Clock Lane */
<> 147:30b64687e01f 10238 #define DSI_PUCR_UECL 0x00000002U /*!< ULPS Exit on Clock Lane */
<> 147:30b64687e01f 10239 #define DSI_PUCR_URDL 0x00000004U /*!< ULPS Request on Data Lane */
<> 147:30b64687e01f 10240 #define DSI_PUCR_UEDL 0x00000008U /*!< ULPS Exit on Data Lane */
<> 147:30b64687e01f 10241
<> 147:30b64687e01f 10242 /******************* Bit definition for DSI_PTTCRregister **************/
<> 147:30b64687e01f 10243 #define DSI_PTTCR_TX_TRIG 0x0000000FU /*!< Transmission Trigger */
<> 147:30b64687e01f 10244 #define DSI_PTTCR_TX_TRIG0 0x00000001U
<> 147:30b64687e01f 10245 #define DSI_PTTCR_TX_TRIG1 0x00000002U
<> 147:30b64687e01f 10246 #define DSI_PTTCR_TX_TRIG2 0x00000004U
<> 147:30b64687e01f 10247 #define DSI_PTTCR_TX_TRIG3 0x00000008U
<> 147:30b64687e01f 10248
<> 147:30b64687e01f 10249 /******************* Bit definition for DSI_PSR register ****************/
<> 147:30b64687e01f 10250 #define DSI_PSR_PD 0x00000002U /*!< PHY Direction */
<> 147:30b64687e01f 10251 #define DSI_PSR_PSSC 0x00000004U /*!< PHY Stop State Clock lane */
<> 147:30b64687e01f 10252 #define DSI_PSR_UANC 0x00000008U /*!< ULPS Active Not Clock lane */
<> 147:30b64687e01f 10253 #define DSI_PSR_PSS0 0x00000010U /*!< PHY Stop State lane 0 */
<> 147:30b64687e01f 10254 #define DSI_PSR_UAN0 0x00000020U /*!< ULPS Active Not lane 0 */
<> 147:30b64687e01f 10255 #define DSI_PSR_RUE0 0x00000040U /*!< RX ULPS Escape lane 0 */
<> 147:30b64687e01f 10256 #define DSI_PSR_PSS1 0x00000080U /*!< PHY Stop State lane 1 */
<> 147:30b64687e01f 10257 #define DSI_PSR_UAN1 0x00000100U /*!< ULPS Active Not lane 1 */
<> 147:30b64687e01f 10258
<> 147:30b64687e01f 10259 /******************* Bit definition for DSI_ISR0 register ***************/
<> 147:30b64687e01f 10260 #define DSI_ISR0_AE0 0x00000001U /*!< Acknowledge Error 0 */
<> 147:30b64687e01f 10261 #define DSI_ISR0_AE1 0x00000002U /*!< Acknowledge Error 1 */
<> 147:30b64687e01f 10262 #define DSI_ISR0_AE2 0x00000004U /*!< Acknowledge Error 2 */
<> 147:30b64687e01f 10263 #define DSI_ISR0_AE3 0x00000008U /*!< Acknowledge Error 3 */
<> 147:30b64687e01f 10264 #define DSI_ISR0_AE4 0x00000010U /*!< Acknowledge Error 4 */
<> 147:30b64687e01f 10265 #define DSI_ISR0_AE5 0x00000020U /*!< Acknowledge Error 5 */
<> 147:30b64687e01f 10266 #define DSI_ISR0_AE6 0x00000040U /*!< Acknowledge Error 6 */
<> 147:30b64687e01f 10267 #define DSI_ISR0_AE7 0x00000080U /*!< Acknowledge Error 7 */
<> 147:30b64687e01f 10268 #define DSI_ISR0_AE8 0x00000100U /*!< Acknowledge Error 8 */
<> 147:30b64687e01f 10269 #define DSI_ISR0_AE9 0x00000200U /*!< Acknowledge Error 9 */
<> 147:30b64687e01f 10270 #define DSI_ISR0_AE10 0x00000400U /*!< Acknowledge Error 10 */
<> 147:30b64687e01f 10271 #define DSI_ISR0_AE11 0x00000800U /*!< Acknowledge Error 11 */
<> 147:30b64687e01f 10272 #define DSI_ISR0_AE12 0x00001000U /*!< Acknowledge Error 12 */
<> 147:30b64687e01f 10273 #define DSI_ISR0_AE13 0x00002000U /*!< Acknowledge Error 13 */
<> 147:30b64687e01f 10274 #define DSI_ISR0_AE14 0x00004000U /*!< Acknowledge Error 14 */
<> 147:30b64687e01f 10275 #define DSI_ISR0_AE15 0x00008000U /*!< Acknowledge Error 15 */
<> 147:30b64687e01f 10276 #define DSI_ISR0_PE0 0x00010000U /*!< PHY Error 0 */
<> 147:30b64687e01f 10277 #define DSI_ISR0_PE1 0x00020000U /*!< PHY Error 1 */
<> 147:30b64687e01f 10278 #define DSI_ISR0_PE2 0x00040000U /*!< PHY Error 2 */
<> 147:30b64687e01f 10279 #define DSI_ISR0_PE3 0x00080000U /*!< PHY Error 3 */
<> 147:30b64687e01f 10280 #define DSI_ISR0_PE4 0x00100000U /*!< PHY Error 4 */
<> 147:30b64687e01f 10281
<> 147:30b64687e01f 10282 /******************* Bit definition for DSI_ISR1 register ***************/
<> 147:30b64687e01f 10283 #define DSI_ISR1_TOHSTX 0x00000001U /*!< Timeout High-Speed Transmission */
<> 147:30b64687e01f 10284 #define DSI_ISR1_TOLPRX 0x00000002U /*!< Timeout Low-Power Reception */
<> 147:30b64687e01f 10285 #define DSI_ISR1_ECCSE 0x00000004U /*!< ECC Single-bit Error */
<> 147:30b64687e01f 10286 #define DSI_ISR1_ECCME 0x00000008U /*!< ECC Multi-bit Error */
<> 147:30b64687e01f 10287 #define DSI_ISR1_CRCE 0x00000010U /*!< CRC Error */
<> 147:30b64687e01f 10288 #define DSI_ISR1_PSE 0x00000020U /*!< Packet Size Error */
<> 147:30b64687e01f 10289 #define DSI_ISR1_EOTPE 0x00000040U /*!< EoTp Error */
<> 147:30b64687e01f 10290 #define DSI_ISR1_LPWRE 0x00000080U /*!< LTDC Payload Write Error */
<> 147:30b64687e01f 10291 #define DSI_ISR1_GCWRE 0x00000100U /*!< Generic Command Write Error */
<> 147:30b64687e01f 10292 #define DSI_ISR1_GPWRE 0x00000200U /*!< Generic Payload Write Error */
<> 147:30b64687e01f 10293 #define DSI_ISR1_GPTXE 0x00000400U /*!< Generic Payload Transmit Error */
<> 147:30b64687e01f 10294 #define DSI_ISR1_GPRDE 0x00000800U /*!< Generic Payload Read Error */
<> 147:30b64687e01f 10295 #define DSI_ISR1_GPRXE 0x00001000U /*!< Generic Payload Receive Error */
<> 147:30b64687e01f 10296
<> 147:30b64687e01f 10297 /******************* Bit definition for DSI_IER0 register ***************/
<> 147:30b64687e01f 10298 #define DSI_IER0_AE0IE 0x00000001U /*!< Acknowledge Error 0 Interrupt Enable */
<> 147:30b64687e01f 10299 #define DSI_IER0_AE1IE 0x00000002U /*!< Acknowledge Error 1 Interrupt Enable */
<> 147:30b64687e01f 10300 #define DSI_IER0_AE2IE 0x00000004U /*!< Acknowledge Error 2 Interrupt Enable */
<> 147:30b64687e01f 10301 #define DSI_IER0_AE3IE 0x00000008U /*!< Acknowledge Error 3 Interrupt Enable */
<> 147:30b64687e01f 10302 #define DSI_IER0_AE4IE 0x00000010U /*!< Acknowledge Error 4 Interrupt Enable */
<> 147:30b64687e01f 10303 #define DSI_IER0_AE5IE 0x00000020U /*!< Acknowledge Error 5 Interrupt Enable */
<> 147:30b64687e01f 10304 #define DSI_IER0_AE6IE 0x00000040U /*!< Acknowledge Error 6 Interrupt Enable */
<> 147:30b64687e01f 10305 #define DSI_IER0_AE7IE 0x00000080U /*!< Acknowledge Error 7 Interrupt Enable */
<> 147:30b64687e01f 10306 #define DSI_IER0_AE8IE 0x00000100U /*!< Acknowledge Error 8 Interrupt Enable */
<> 147:30b64687e01f 10307 #define DSI_IER0_AE9IE 0x00000200U /*!< Acknowledge Error 9 Interrupt Enable */
<> 147:30b64687e01f 10308 #define DSI_IER0_AE10IE 0x00000400U /*!< Acknowledge Error 10 Interrupt Enable */
<> 147:30b64687e01f 10309 #define DSI_IER0_AE11IE 0x00000800U /*!< Acknowledge Error 11 Interrupt Enable */
<> 147:30b64687e01f 10310 #define DSI_IER0_AE12IE 0x00001000U /*!< Acknowledge Error 12 Interrupt Enable */
<> 147:30b64687e01f 10311 #define DSI_IER0_AE13IE 0x00002000U /*!< Acknowledge Error 13 Interrupt Enable */
<> 147:30b64687e01f 10312 #define DSI_IER0_AE14IE 0x00004000U /*!< Acknowledge Error 14 Interrupt Enable */
<> 147:30b64687e01f 10313 #define DSI_IER0_AE15IE 0x00008000U /*!< Acknowledge Error 15 Interrupt Enable */
<> 147:30b64687e01f 10314 #define DSI_IER0_PE0IE 0x00010000U /*!< PHY Error 0 Interrupt Enable */
<> 147:30b64687e01f 10315 #define DSI_IER0_PE1IE 0x00020000U /*!< PHY Error 1 Interrupt Enable */
<> 147:30b64687e01f 10316 #define DSI_IER0_PE2IE 0x00040000U /*!< PHY Error 2 Interrupt Enable */
<> 147:30b64687e01f 10317 #define DSI_IER0_PE3IE 0x00080000U /*!< PHY Error 3 Interrupt Enable */
<> 147:30b64687e01f 10318 #define DSI_IER0_PE4IE 0x00100000U /*!< PHY Error 4 Interrupt Enable */
<> 147:30b64687e01f 10319
<> 147:30b64687e01f 10320 /******************* Bit definition for DSI_IER1 register ***************/
<> 147:30b64687e01f 10321 #define DSI_IER1_TOHSTXIE 0x00000001U /*!< Timeout High-Speed Transmission Interrupt Enable */
<> 147:30b64687e01f 10322 #define DSI_IER1_TOLPRXIE 0x00000002U /*!< Timeout Low-Power Reception Interrupt Enable */
<> 147:30b64687e01f 10323 #define DSI_IER1_ECCSEIE 0x00000004U /*!< ECC Single-bit Error Interrupt Enable */
<> 147:30b64687e01f 10324 #define DSI_IER1_ECCMEIE 0x00000008U /*!< ECC Multi-bit Error Interrupt Enable */
<> 147:30b64687e01f 10325 #define DSI_IER1_CRCEIE 0x00000010U /*!< CRC Error Interrupt Enable */
<> 147:30b64687e01f 10326 #define DSI_IER1_PSEIE 0x00000020U /*!< Packet Size Error Interrupt Enable */
<> 147:30b64687e01f 10327 #define DSI_IER1_EOTPEIE 0x00000040U /*!< EoTp Error Interrupt Enable */
<> 147:30b64687e01f 10328 #define DSI_IER1_LPWREIE 0x00000080U /*!< LTDC Payload Write Error Interrupt Enable */
<> 147:30b64687e01f 10329 #define DSI_IER1_GCWREIE 0x00000100U /*!< Generic Command Write Error Interrupt Enable */
<> 147:30b64687e01f 10330 #define DSI_IER1_GPWREIE 0x00000200U /*!< Generic Payload Write Error Interrupt Enable */
<> 147:30b64687e01f 10331 #define DSI_IER1_GPTXEIE 0x00000400U /*!< Generic Payload Transmit Error Interrupt Enable */
<> 147:30b64687e01f 10332 #define DSI_IER1_GPRDEIE 0x00000800U /*!< Generic Payload Read Error Interrupt Enable */
<> 147:30b64687e01f 10333 #define DSI_IER1_GPRXEIE 0x00001000U /*!< Generic Payload Receive Error Interrupt Enable */
<> 147:30b64687e01f 10334
<> 147:30b64687e01f 10335 /******************* Bit definition for DSI_FIR0 register ***************/
<> 147:30b64687e01f 10336 #define DSI_FIR0_FAE0 0x00000001U /*!< Force Acknowledge Error 0 */
<> 147:30b64687e01f 10337 #define DSI_FIR0_FAE1 0x00000002U /*!< Force Acknowledge Error 1 */
<> 147:30b64687e01f 10338 #define DSI_FIR0_FAE2 0x00000004U /*!< Force Acknowledge Error 2 */
<> 147:30b64687e01f 10339 #define DSI_FIR0_FAE3 0x00000008U /*!< Force Acknowledge Error 3 */
<> 147:30b64687e01f 10340 #define DSI_FIR0_FAE4 0x00000010U /*!< Force Acknowledge Error 4 */
<> 147:30b64687e01f 10341 #define DSI_FIR0_FAE5 0x00000020U /*!< Force Acknowledge Error 5 */
<> 147:30b64687e01f 10342 #define DSI_FIR0_FAE6 0x00000040U /*!< Force Acknowledge Error 6 */
<> 147:30b64687e01f 10343 #define DSI_FIR0_FAE7 0x00000080U /*!< Force Acknowledge Error 7 */
<> 147:30b64687e01f 10344 #define DSI_FIR0_FAE8 0x00000100U /*!< Force Acknowledge Error 8 */
<> 147:30b64687e01f 10345 #define DSI_FIR0_FAE9 0x00000200U /*!< Force Acknowledge Error 9 */
<> 147:30b64687e01f 10346 #define DSI_FIR0_FAE10 0x00000400U /*!< Force Acknowledge Error 10 */
<> 147:30b64687e01f 10347 #define DSI_FIR0_FAE11 0x00000800U /*!< Force Acknowledge Error 11 */
<> 147:30b64687e01f 10348 #define DSI_FIR0_FAE12 0x00001000U /*!< Force Acknowledge Error 12 */
<> 147:30b64687e01f 10349 #define DSI_FIR0_FAE13 0x00002000U /*!< Force Acknowledge Error 13 */
<> 147:30b64687e01f 10350 #define DSI_FIR0_FAE14 0x00004000U /*!< Force Acknowledge Error 14 */
<> 147:30b64687e01f 10351 #define DSI_FIR0_FAE15 0x00008000U /*!< Force Acknowledge Error 15 */
<> 147:30b64687e01f 10352 #define DSI_FIR0_FPE0 0x00010000U /*!< Force PHY Error 0 */
<> 147:30b64687e01f 10353 #define DSI_FIR0_FPE1 0x00020000U /*!< Force PHY Error 1 */
<> 147:30b64687e01f 10354 #define DSI_FIR0_FPE2 0x00040000U /*!< Force PHY Error 2 */
<> 147:30b64687e01f 10355 #define DSI_FIR0_FPE3 0x00080000U /*!< Force PHY Error 3 */
<> 147:30b64687e01f 10356 #define DSI_FIR0_FPE4 0x00100000U /*!< Force PHY Error 4 */
<> 147:30b64687e01f 10357
<> 147:30b64687e01f 10358 /******************* Bit definition for DSI_FIR1 register ***************/
<> 147:30b64687e01f 10359 #define DSI_FIR1_FTOHSTX 0x00000001U /*!< Force Timeout High-Speed Transmission */
<> 147:30b64687e01f 10360 #define DSI_FIR1_FTOLPRX 0x00000002U /*!< Force Timeout Low-Power Reception */
<> 147:30b64687e01f 10361 #define DSI_FIR1_FECCSE 0x00000004U /*!< Force ECC Single-bit Error */
<> 147:30b64687e01f 10362 #define DSI_FIR1_FECCME 0x00000008U /*!< Force ECC Multi-bit Error */
<> 147:30b64687e01f 10363 #define DSI_FIR1_FCRCE 0x00000010U /*!< Force CRC Error */
<> 147:30b64687e01f 10364 #define DSI_FIR1_FPSE 0x00000020U /*!< Force Packet Size Error */
<> 147:30b64687e01f 10365 #define DSI_FIR1_FEOTPE 0x00000040U /*!< Force EoTp Error */
<> 147:30b64687e01f 10366 #define DSI_FIR1_FLPWRE 0x00000080U /*!< Force LTDC Payload Write Error */
<> 147:30b64687e01f 10367 #define DSI_FIR1_FGCWRE 0x00000100U /*!< Force Generic Command Write Error */
<> 147:30b64687e01f 10368 #define DSI_FIR1_FGPWRE 0x00000200U /*!< Force Generic Payload Write Error */
<> 147:30b64687e01f 10369 #define DSI_FIR1_FGPTXE 0x00000400U /*!< Force Generic Payload Transmit Error */
<> 147:30b64687e01f 10370 #define DSI_FIR1_FGPRDE 0x00000800U /*!< Force Generic Payload Read Error */
<> 147:30b64687e01f 10371 #define DSI_FIR1_FGPRXE 0x00001000U /*!< Force Generic Payload Receive Error */
<> 147:30b64687e01f 10372
<> 147:30b64687e01f 10373 /******************* Bit definition for DSI_VSCR register ***************/
<> 147:30b64687e01f 10374 #define DSI_VSCR_EN 0x00000001U /*!< Enable */
<> 147:30b64687e01f 10375 #define DSI_VSCR_UR 0x00000100U /*!< Update Register */
<> 147:30b64687e01f 10376
<> 147:30b64687e01f 10377 /******************* Bit definition for DSI_LCVCIDR register ************/
<> 147:30b64687e01f 10378 #define DSI_LCVCIDR_VCID 0x00000003U /*!< Virtual Channel ID */
<> 147:30b64687e01f 10379 #define DSI_LCVCIDR_VCID0 0x00000001U
<> 147:30b64687e01f 10380 #define DSI_LCVCIDR_VCID1 0x00000002U
<> 147:30b64687e01f 10381
<> 147:30b64687e01f 10382 /******************* Bit definition for DSI_LCCCR register **************/
<> 147:30b64687e01f 10383 #define DSI_LCCCR_COLC 0x0000000FU /*!< Color Coding */
<> 147:30b64687e01f 10384 #define DSI_LCCCR_COLC0 0x00000001U
<> 147:30b64687e01f 10385 #define DSI_LCCCR_COLC1 0x00000002U
<> 147:30b64687e01f 10386 #define DSI_LCCCR_COLC2 0x00000004U
<> 147:30b64687e01f 10387 #define DSI_LCCCR_COLC3 0x00000008U
<> 147:30b64687e01f 10388
<> 147:30b64687e01f 10389 #define DSI_LCCCR_LPE 0x00000100U /*!< Loosely Packed Enable */
<> 147:30b64687e01f 10390
<> 147:30b64687e01f 10391 /******************* Bit definition for DSI_LPMCCR register *************/
<> 147:30b64687e01f 10392 #define DSI_LPMCCR_VLPSIZE 0x000000FFU /*!< VACT Largest Packet Size */
<> 147:30b64687e01f 10393 #define DSI_LPMCCR_VLPSIZE0 0x00000001U
<> 147:30b64687e01f 10394 #define DSI_LPMCCR_VLPSIZE1 0x00000002U
<> 147:30b64687e01f 10395 #define DSI_LPMCCR_VLPSIZE2 0x00000004U
<> 147:30b64687e01f 10396 #define DSI_LPMCCR_VLPSIZE3 0x00000008U
<> 147:30b64687e01f 10397 #define DSI_LPMCCR_VLPSIZE4 0x00000010U
<> 147:30b64687e01f 10398 #define DSI_LPMCCR_VLPSIZE5 0x00000020U
<> 147:30b64687e01f 10399 #define DSI_LPMCCR_VLPSIZE6 0x00000040U
<> 147:30b64687e01f 10400 #define DSI_LPMCCR_VLPSIZE7 0x00000080U
<> 147:30b64687e01f 10401
<> 147:30b64687e01f 10402 #define DSI_LPMCCR_LPSIZE 0x00FF0000U /*!< Largest Packet Size */
<> 147:30b64687e01f 10403 #define DSI_LPMCCR_LPSIZE0 0x00010000U
<> 147:30b64687e01f 10404 #define DSI_LPMCCR_LPSIZE1 0x00020000U
<> 147:30b64687e01f 10405 #define DSI_LPMCCR_LPSIZE2 0x00040000U
<> 147:30b64687e01f 10406 #define DSI_LPMCCR_LPSIZE3 0x00080000U
<> 147:30b64687e01f 10407 #define DSI_LPMCCR_LPSIZE4 0x00100000U
<> 147:30b64687e01f 10408 #define DSI_LPMCCR_LPSIZE5 0x00200000U
<> 147:30b64687e01f 10409 #define DSI_LPMCCR_LPSIZE6 0x00400000U
<> 147:30b64687e01f 10410 #define DSI_LPMCCR_LPSIZE7 0x00800000U
<> 147:30b64687e01f 10411
<> 147:30b64687e01f 10412 /******************* Bit definition for DSI_VMCCR register **************/
<> 147:30b64687e01f 10413 #define DSI_VMCCR_VMT 0x00000003U /*!< Video Mode Type */
<> 147:30b64687e01f 10414 #define DSI_VMCCR_VMT0 0x00000001U
<> 147:30b64687e01f 10415 #define DSI_VMCCR_VMT1 0x00000002U
<> 147:30b64687e01f 10416
<> 147:30b64687e01f 10417 #define DSI_VMCCR_LPVSAE 0x00000100U /*!< Low-power Vertical Sync time Enable */
<> 147:30b64687e01f 10418 #define DSI_VMCCR_LPVBPE 0x00000200U /*!< Low-power Vertical Back-porch Enable */
<> 147:30b64687e01f 10419 #define DSI_VMCCR_LPVFPE 0x00000400U /*!< Low-power Vertical Front-porch Enable */
<> 147:30b64687e01f 10420 #define DSI_VMCCR_LPVAE 0x00000800U /*!< Low-power Vertical Active Enable */
<> 147:30b64687e01f 10421 #define DSI_VMCCR_LPHBPE 0x00001000U /*!< Low-power Horizontal Back-porch Enable */
<> 147:30b64687e01f 10422 #define DSI_VMCCR_LPHFE 0x00002000U /*!< Low-power Horizontal Front-porch Enable */
<> 147:30b64687e01f 10423 #define DSI_VMCCR_FBTAAE 0x00004000U /*!< Frame BTA Acknowledge Enable */
<> 147:30b64687e01f 10424 #define DSI_VMCCR_LPCE 0x00008000U /*!< Low-power Command Enable */
<> 147:30b64687e01f 10425
<> 147:30b64687e01f 10426 /******************* Bit definition for DSI_VPCCR register **************/
<> 147:30b64687e01f 10427 #define DSI_VPCCR_VPSIZE 0x00003FFFU /*!< Video Packet Size */
<> 147:30b64687e01f 10428 #define DSI_VPCCR_VPSIZE0 0x00000001U
<> 147:30b64687e01f 10429 #define DSI_VPCCR_VPSIZE1 0x00000002U
<> 147:30b64687e01f 10430 #define DSI_VPCCR_VPSIZE2 0x00000004U
<> 147:30b64687e01f 10431 #define DSI_VPCCR_VPSIZE3 0x00000008U
<> 147:30b64687e01f 10432 #define DSI_VPCCR_VPSIZE4 0x00000010U
<> 147:30b64687e01f 10433 #define DSI_VPCCR_VPSIZE5 0x00000020U
<> 147:30b64687e01f 10434 #define DSI_VPCCR_VPSIZE6 0x00000040U
<> 147:30b64687e01f 10435 #define DSI_VPCCR_VPSIZE7 0x00000080U
<> 147:30b64687e01f 10436 #define DSI_VPCCR_VPSIZE8 0x00000100U
<> 147:30b64687e01f 10437 #define DSI_VPCCR_VPSIZE9 0x00000200U
<> 147:30b64687e01f 10438 #define DSI_VPCCR_VPSIZE10 0x00000400U
<> 147:30b64687e01f 10439 #define DSI_VPCCR_VPSIZE11 0x00000800U
<> 147:30b64687e01f 10440 #define DSI_VPCCR_VPSIZE12 0x00001000U
<> 147:30b64687e01f 10441 #define DSI_VPCCR_VPSIZE13 0x00002000U
<> 147:30b64687e01f 10442
<> 147:30b64687e01f 10443 /******************* Bit definition for DSI_VCCCR register **************/
<> 147:30b64687e01f 10444 #define DSI_VCCCR_NUMC 0x00001FFFU /*!< Number of Chunks */
<> 147:30b64687e01f 10445 #define DSI_VCCCR_NUMC0 0x00000001U
<> 147:30b64687e01f 10446 #define DSI_VCCCR_NUMC1 0x00000002U
<> 147:30b64687e01f 10447 #define DSI_VCCCR_NUMC2 0x00000004U
<> 147:30b64687e01f 10448 #define DSI_VCCCR_NUMC3 0x00000008U
<> 147:30b64687e01f 10449 #define DSI_VCCCR_NUMC4 0x00000010U
<> 147:30b64687e01f 10450 #define DSI_VCCCR_NUMC5 0x00000020U
<> 147:30b64687e01f 10451 #define DSI_VCCCR_NUMC6 0x00000040U
<> 147:30b64687e01f 10452 #define DSI_VCCCR_NUMC7 0x00000080U
<> 147:30b64687e01f 10453 #define DSI_VCCCR_NUMC8 0x00000100U
<> 147:30b64687e01f 10454 #define DSI_VCCCR_NUMC9 0x00000200U
<> 147:30b64687e01f 10455 #define DSI_VCCCR_NUMC10 0x00000400U
<> 147:30b64687e01f 10456 #define DSI_VCCCR_NUMC11 0x00000800U
<> 147:30b64687e01f 10457 #define DSI_VCCCR_NUMC12 0x00001000U
<> 147:30b64687e01f 10458
<> 147:30b64687e01f 10459 /******************* Bit definition for DSI_VNPCCR register *************/
<> 147:30b64687e01f 10460 #define DSI_VNPCCR_NPSIZE 0x00001FFFU /*!< Number of Chunks */
<> 147:30b64687e01f 10461 #define DSI_VNPCCR_NPSIZE0 0x00000001U
<> 147:30b64687e01f 10462 #define DSI_VNPCCR_NPSIZE1 0x00000002U
<> 147:30b64687e01f 10463 #define DSI_VNPCCR_NPSIZE2 0x00000004U
<> 147:30b64687e01f 10464 #define DSI_VNPCCR_NPSIZE3 0x00000008U
<> 147:30b64687e01f 10465 #define DSI_VNPCCR_NPSIZE4 0x00000010U
<> 147:30b64687e01f 10466 #define DSI_VNPCCR_NPSIZE5 0x00000020U
<> 147:30b64687e01f 10467 #define DSI_VNPCCR_NPSIZE6 0x00000040U
<> 147:30b64687e01f 10468 #define DSI_VNPCCR_NPSIZE7 0x00000080U
<> 147:30b64687e01f 10469 #define DSI_VNPCCR_NPSIZE8 0x00000100U
<> 147:30b64687e01f 10470 #define DSI_VNPCCR_NPSIZE9 0x00000200U
<> 147:30b64687e01f 10471 #define DSI_VNPCCR_NPSIZE10 0x00000400U
<> 147:30b64687e01f 10472 #define DSI_VNPCCR_NPSIZE11 0x00000800U
<> 147:30b64687e01f 10473 #define DSI_VNPCCR_NPSIZE12 0x00001000U
<> 147:30b64687e01f 10474
<> 147:30b64687e01f 10475 /******************* Bit definition for DSI_VHSACCR register ************/
<> 147:30b64687e01f 10476 #define DSI_VHSACCR_HSA 0x00000FFFU /*!< Horizontal Synchronism Active duration */
<> 147:30b64687e01f 10477 #define DSI_VHSACCR_HSA0 0x00000001U
<> 147:30b64687e01f 10478 #define DSI_VHSACCR_HSA1 0x00000002U
<> 147:30b64687e01f 10479 #define DSI_VHSACCR_HSA2 0x00000004U
<> 147:30b64687e01f 10480 #define DSI_VHSACCR_HSA3 0x00000008U
<> 147:30b64687e01f 10481 #define DSI_VHSACCR_HSA4 0x00000010U
<> 147:30b64687e01f 10482 #define DSI_VHSACCR_HSA5 0x00000020U
<> 147:30b64687e01f 10483 #define DSI_VHSACCR_HSA6 0x00000040U
<> 147:30b64687e01f 10484 #define DSI_VHSACCR_HSA7 0x00000080U
<> 147:30b64687e01f 10485 #define DSI_VHSACCR_HSA8 0x00000100U
<> 147:30b64687e01f 10486 #define DSI_VHSACCR_HSA9 0x00000200U
<> 147:30b64687e01f 10487 #define DSI_VHSACCR_HSA10 0x00000400U
<> 147:30b64687e01f 10488 #define DSI_VHSACCR_HSA11 0x00000800U
<> 147:30b64687e01f 10489
<> 147:30b64687e01f 10490 /******************* Bit definition for DSI_VHBPCCR register ************/
<> 147:30b64687e01f 10491 #define DSI_VHBPCCR_HBP 0x00000FFFU /*!< Horizontal Back-Porch duration */
<> 147:30b64687e01f 10492 #define DSI_VHBPCCR_HBP0 0x00000001U
<> 147:30b64687e01f 10493 #define DSI_VHBPCCR_HBP1 0x00000002U
<> 147:30b64687e01f 10494 #define DSI_VHBPCCR_HBP2 0x00000004U
<> 147:30b64687e01f 10495 #define DSI_VHBPCCR_HBP3 0x00000008U
<> 147:30b64687e01f 10496 #define DSI_VHBPCCR_HBP4 0x00000010U
<> 147:30b64687e01f 10497 #define DSI_VHBPCCR_HBP5 0x00000020U
<> 147:30b64687e01f 10498 #define DSI_VHBPCCR_HBP6 0x00000040U
<> 147:30b64687e01f 10499 #define DSI_VHBPCCR_HBP7 0x00000080U
<> 147:30b64687e01f 10500 #define DSI_VHBPCCR_HBP8 0x00000100U
<> 147:30b64687e01f 10501 #define DSI_VHBPCCR_HBP9 0x00000200U
<> 147:30b64687e01f 10502 #define DSI_VHBPCCR_HBP10 0x00000400U
<> 147:30b64687e01f 10503 #define DSI_VHBPCCR_HBP11 0x00000800U
<> 147:30b64687e01f 10504
<> 147:30b64687e01f 10505 /******************* Bit definition for DSI_VLCCR register **************/
<> 147:30b64687e01f 10506 #define DSI_VLCCR_HLINE 0x00007FFFU /*!< Horizontal Line duration */
<> 147:30b64687e01f 10507 #define DSI_VLCCR_HLINE0 0x00000001U
<> 147:30b64687e01f 10508 #define DSI_VLCCR_HLINE1 0x00000002U
<> 147:30b64687e01f 10509 #define DSI_VLCCR_HLINE2 0x00000004U
<> 147:30b64687e01f 10510 #define DSI_VLCCR_HLINE3 0x00000008U
<> 147:30b64687e01f 10511 #define DSI_VLCCR_HLINE4 0x00000010U
<> 147:30b64687e01f 10512 #define DSI_VLCCR_HLINE5 0x00000020U
<> 147:30b64687e01f 10513 #define DSI_VLCCR_HLINE6 0x00000040U
<> 147:30b64687e01f 10514 #define DSI_VLCCR_HLINE7 0x00000080U
<> 147:30b64687e01f 10515 #define DSI_VLCCR_HLINE8 0x00000100U
<> 147:30b64687e01f 10516 #define DSI_VLCCR_HLINE9 0x00000200U
<> 147:30b64687e01f 10517 #define DSI_VLCCR_HLINE10 0x00000400U
<> 147:30b64687e01f 10518 #define DSI_VLCCR_HLINE11 0x00000800U
<> 147:30b64687e01f 10519 #define DSI_VLCCR_HLINE12 0x00001000U
<> 147:30b64687e01f 10520 #define DSI_VLCCR_HLINE13 0x00002000U
<> 147:30b64687e01f 10521 #define DSI_VLCCR_HLINE14 0x00004000U
<> 147:30b64687e01f 10522
<> 147:30b64687e01f 10523 /******************* Bit definition for DSI_VVSACCR register ***************/
<> 147:30b64687e01f 10524 #define DSI_VVSACCR_VSA 0x000003FFU /*!< Vertical Synchronism Active duration */
<> 147:30b64687e01f 10525 #define DSI_VVSACCR_VSA0 0x00000001U
<> 147:30b64687e01f 10526 #define DSI_VVSACCR_VSA1 0x00000002U
<> 147:30b64687e01f 10527 #define DSI_VVSACCR_VSA2 0x00000004U
<> 147:30b64687e01f 10528 #define DSI_VVSACCR_VSA3 0x00000008U
<> 147:30b64687e01f 10529 #define DSI_VVSACCR_VSA4 0x00000010U
<> 147:30b64687e01f 10530 #define DSI_VVSACCR_VSA5 0x00000020U
<> 147:30b64687e01f 10531 #define DSI_VVSACCR_VSA6 0x00000040U
<> 147:30b64687e01f 10532 #define DSI_VVSACCR_VSA7 0x00000080U
<> 147:30b64687e01f 10533 #define DSI_VVSACCR_VSA8 0x00000100U
<> 147:30b64687e01f 10534 #define DSI_VVSACCR_VSA9 0x00000200U
<> 147:30b64687e01f 10535
<> 147:30b64687e01f 10536 /******************* Bit definition for DSI_VVBPCCR register ************/
<> 147:30b64687e01f 10537 #define DSI_VVBPCCR_VBP 0x000003FFU /*!< Vertical Back-Porch duration */
<> 147:30b64687e01f 10538 #define DSI_VVBPCCR_VBP0 0x00000001U
<> 147:30b64687e01f 10539 #define DSI_VVBPCCR_VBP1 0x00000002U
<> 147:30b64687e01f 10540 #define DSI_VVBPCCR_VBP2 0x00000004U
<> 147:30b64687e01f 10541 #define DSI_VVBPCCR_VBP3 0x00000008U
<> 147:30b64687e01f 10542 #define DSI_VVBPCCR_VBP4 0x00000010U
<> 147:30b64687e01f 10543 #define DSI_VVBPCCR_VBP5 0x00000020U
<> 147:30b64687e01f 10544 #define DSI_VVBPCCR_VBP6 0x00000040U
<> 147:30b64687e01f 10545 #define DSI_VVBPCCR_VBP7 0x00000080U
<> 147:30b64687e01f 10546 #define DSI_VVBPCCR_VBP8 0x00000100U
<> 147:30b64687e01f 10547 #define DSI_VVBPCCR_VBP9 0x00000200U
<> 147:30b64687e01f 10548
<> 147:30b64687e01f 10549 /******************* Bit definition for DSI_VVFPCCR register ************/
<> 147:30b64687e01f 10550 #define DSI_VVFPCCR_VFP 0x000003FFU /*!< Vertical Front-Porch duration */
<> 147:30b64687e01f 10551 #define DSI_VVFPCCR_VFP0 0x00000001U
<> 147:30b64687e01f 10552 #define DSI_VVFPCCR_VFP1 0x00000002U
<> 147:30b64687e01f 10553 #define DSI_VVFPCCR_VFP2 0x00000004U
<> 147:30b64687e01f 10554 #define DSI_VVFPCCR_VFP3 0x00000008U
<> 147:30b64687e01f 10555 #define DSI_VVFPCCR_VFP4 0x00000010U
<> 147:30b64687e01f 10556 #define DSI_VVFPCCR_VFP5 0x00000020U
<> 147:30b64687e01f 10557 #define DSI_VVFPCCR_VFP6 0x00000040U
<> 147:30b64687e01f 10558 #define DSI_VVFPCCR_VFP7 0x00000080U
<> 147:30b64687e01f 10559 #define DSI_VVFPCCR_VFP8 0x00000100U
<> 147:30b64687e01f 10560 #define DSI_VVFPCCR_VFP9 0x00000200U
<> 147:30b64687e01f 10561
<> 147:30b64687e01f 10562 /******************* Bit definition for DSI_VVACCR register *************/
<> 147:30b64687e01f 10563 #define DSI_VVACCR_VA 0x00003FFFU /*!< Vertical Active duration */
<> 147:30b64687e01f 10564 #define DSI_VVACCR_VA0 0x00000001U
<> 147:30b64687e01f 10565 #define DSI_VVACCR_VA1 0x00000002U
<> 147:30b64687e01f 10566 #define DSI_VVACCR_VA2 0x00000004U
<> 147:30b64687e01f 10567 #define DSI_VVACCR_VA3 0x00000008U
<> 147:30b64687e01f 10568 #define DSI_VVACCR_VA4 0x00000010U
<> 147:30b64687e01f 10569 #define DSI_VVACCR_VA5 0x00000020U
<> 147:30b64687e01f 10570 #define DSI_VVACCR_VA6 0x00000040U
<> 147:30b64687e01f 10571 #define DSI_VVACCR_VA7 0x00000080U
<> 147:30b64687e01f 10572 #define DSI_VVACCR_VA8 0x00000100U
<> 147:30b64687e01f 10573 #define DSI_VVACCR_VA9 0x00000200U
<> 147:30b64687e01f 10574 #define DSI_VVACCR_VA10 0x00000400U
<> 147:30b64687e01f 10575 #define DSI_VVACCR_VA11 0x00000800U
<> 147:30b64687e01f 10576 #define DSI_VVACCR_VA12 0x00001000U
<> 147:30b64687e01f 10577 #define DSI_VVACCR_VA13 0x00002000U
<> 147:30b64687e01f 10578
<> 147:30b64687e01f 10579 /******************* Bit definition for DSI_TDCCR register **************/
<> 147:30b64687e01f 10580 #define DSI_TDCCR_3DM 0x00000003U /*!< 3D Mode */
<> 147:30b64687e01f 10581 #define DSI_TDCCR_3DM0 0x00000001U
<> 147:30b64687e01f 10582 #define DSI_TDCCR_3DM1 0x00000002U
<> 147:30b64687e01f 10583
<> 147:30b64687e01f 10584 #define DSI_TDCCR_3DF 0x0000000CU /*!< 3D Format */
<> 147:30b64687e01f 10585 #define DSI_TDCCR_3DF0 0x00000004U
<> 147:30b64687e01f 10586 #define DSI_TDCCR_3DF1 0x00000008U
<> 147:30b64687e01f 10587
<> 147:30b64687e01f 10588 #define DSI_TDCCR_SVS 0x00000010U /*!< Second VSYNC */
<> 147:30b64687e01f 10589 #define DSI_TDCCR_RF 0x00000020U /*!< Right First */
<> 147:30b64687e01f 10590 #define DSI_TDCCR_S3DC 0x00010000U /*!< Send 3D Control */
<> 147:30b64687e01f 10591
<> 147:30b64687e01f 10592 /******************* Bit definition for DSI_WCFGR register ***************/
<> 147:30b64687e01f 10593 #define DSI_WCFGR_DSIM 0x00000001U /*!< DSI Mode */
<> 147:30b64687e01f 10594 #define DSI_WCFGR_COLMUX 0x0000000EU /*!< Color Multiplexing */
<> 147:30b64687e01f 10595 #define DSI_WCFGR_COLMUX0 0x00000002U
<> 147:30b64687e01f 10596 #define DSI_WCFGR_COLMUX1 0x00000004U
<> 147:30b64687e01f 10597 #define DSI_WCFGR_COLMUX2 0x00000008U
<> 147:30b64687e01f 10598
<> 147:30b64687e01f 10599 #define DSI_WCFGR_TESRC 0x00000010U /*!< Tearing Effect Source */
<> 147:30b64687e01f 10600 #define DSI_WCFGR_TEPOL 0x00000020U /*!< Tearing Effect Polarity */
<> 147:30b64687e01f 10601 #define DSI_WCFGR_AR 0x00000040U /*!< Automatic Refresh */
<> 147:30b64687e01f 10602 #define DSI_WCFGR_VSPOL 0x00000080U /*!< VSync Polarity */
<> 147:30b64687e01f 10603
<> 147:30b64687e01f 10604 /******************* Bit definition for DSI_WCR register *****************/
<> 147:30b64687e01f 10605 #define DSI_WCR_COLM 0x00000001U /*!< Color Mode */
<> 147:30b64687e01f 10606 #define DSI_WCR_SHTDN 0x00000002U /*!< Shutdown */
<> 147:30b64687e01f 10607 #define DSI_WCR_LTDCEN 0x00000004U /*!< LTDC Enable */
<> 147:30b64687e01f 10608 #define DSI_WCR_DSIEN 0x00000008U /*!< DSI Enable */
<> 147:30b64687e01f 10609
<> 147:30b64687e01f 10610 /******************* Bit definition for DSI_WIER register ****************/
<> 147:30b64687e01f 10611 #define DSI_WIER_TEIE 0x00000001U /*!< Tearing Effect Interrupt Enable */
<> 147:30b64687e01f 10612 #define DSI_WIER_ERIE 0x00000002U /*!< End of Refresh Interrupt Enable */
<> 147:30b64687e01f 10613 #define DSI_WIER_PLLLIE 0x00000200U /*!< PLL Lock Interrupt Enable */
<> 147:30b64687e01f 10614 #define DSI_WIER_PLLUIE 0x00000400U /*!< PLL Unlock Interrupt Enable */
<> 147:30b64687e01f 10615 #define DSI_WIER_RRIE 0x00002000U /*!< Regulator Ready Interrupt Enable */
<> 147:30b64687e01f 10616
<> 147:30b64687e01f 10617 /******************* Bit definition for DSI_WISR register ****************/
<> 147:30b64687e01f 10618 #define DSI_WISR_TEIF 0x00000001U /*!< Tearing Effect Interrupt Flag */
<> 147:30b64687e01f 10619 #define DSI_WISR_ERIF 0x00000002U /*!< End of Refresh Interrupt Flag */
<> 147:30b64687e01f 10620 #define DSI_WISR_BUSY 0x00000004U /*!< Busy Flag */
<> 147:30b64687e01f 10621 #define DSI_WISR_PLLLS 0x00000100U /*!< PLL Lock Status */
<> 147:30b64687e01f 10622 #define DSI_WISR_PLLLIF 0x00000200U /*!< PLL Lock Interrupt Flag */
<> 147:30b64687e01f 10623 #define DSI_WISR_PLLUIF 0x00000400U /*!< PLL Unlock Interrupt Flag */
<> 147:30b64687e01f 10624 #define DSI_WISR_RRS 0x00001000U /*!< Regulator Ready Flag */
<> 147:30b64687e01f 10625 #define DSI_WISR_RRIF 0x00002000U /*!< Regulator Ready Interrupt Flag */
<> 147:30b64687e01f 10626
<> 147:30b64687e01f 10627 /******************* Bit definition for DSI_WIFCR register ***************/
<> 147:30b64687e01f 10628 #define DSI_WIFCR_CTEIF 0x00000001U /*!< Clear Tearing Effect Interrupt Flag */
<> 147:30b64687e01f 10629 #define DSI_WIFCR_CERIF 0x00000002U /*!< Clear End of Refresh Interrupt Flag */
<> 147:30b64687e01f 10630 #define DSI_WIFCR_CPLLLIF 0x00000200U /*!< Clear PLL Lock Interrupt Flag */
<> 147:30b64687e01f 10631 #define DSI_WIFCR_CPLLUIF 0x00000400U /*!< Clear PLL Unlock Interrupt Flag */
<> 147:30b64687e01f 10632 #define DSI_WIFCR_CRRIF 0x00002000U /*!< Clear Regulator Ready Interrupt Flag */
<> 147:30b64687e01f 10633
<> 147:30b64687e01f 10634 /******************* Bit definition for DSI_WPCR0 register ***************/
<> 147:30b64687e01f 10635 #define DSI_WPCR0_UIX4 0x0000003FU /*!< Unit Interval multiplied by 4 */
<> 147:30b64687e01f 10636 #define DSI_WPCR0_UIX4_0 0x00000001U
<> 147:30b64687e01f 10637 #define DSI_WPCR0_UIX4_1 0x00000002U
<> 147:30b64687e01f 10638 #define DSI_WPCR0_UIX4_2 0x00000004U
<> 147:30b64687e01f 10639 #define DSI_WPCR0_UIX4_3 0x00000008U
<> 147:30b64687e01f 10640 #define DSI_WPCR0_UIX4_4 0x00000010U
<> 147:30b64687e01f 10641 #define DSI_WPCR0_UIX4_5 0x00000020U
<> 147:30b64687e01f 10642
<> 147:30b64687e01f 10643 #define DSI_WPCR0_SWCL 0x00000040U /*!< Swap pins on clock lane */
<> 147:30b64687e01f 10644 #define DSI_WPCR0_SWDL0 0x00000080U /*!< Swap pins on data lane 1 */
<> 147:30b64687e01f 10645 #define DSI_WPCR0_SWDL1 0x00000100U /*!< Swap pins on data lane 2 */
<> 147:30b64687e01f 10646 #define DSI_WPCR0_HSICL 0x00000200U /*!< Invert the high-speed data signal on clock lane */
<> 147:30b64687e01f 10647 #define DSI_WPCR0_HSIDL0 0x00000400U /*!< Invert the high-speed data signal on lane 1 */
<> 147:30b64687e01f 10648 #define DSI_WPCR0_HSIDL1 0x00000800U /*!< Invert the high-speed data signal on lane 2 */
<> 147:30b64687e01f 10649 #define DSI_WPCR0_FTXSMCL 0x00001000U /*!< Force clock lane in TX stop mode */
<> 147:30b64687e01f 10650 #define DSI_WPCR0_FTXSMDL 0x00002000U /*!< Force data lanes in TX stop mode */
<> 147:30b64687e01f 10651 #define DSI_WPCR0_CDOFFDL 0x00004000U /*!< Contention detection OFF */
<> 147:30b64687e01f 10652 #define DSI_WPCR0_TDDL 0x00010000U /*!< Turn Disable Data Lanes */
<> 147:30b64687e01f 10653 #define DSI_WPCR0_PDEN 0x00040000U /*!< Pull-Down Enable */
<> 147:30b64687e01f 10654 #define DSI_WPCR0_TCLKPREPEN 0x00080000U /*!< Timer for t-CLKPREP Enable */
<> 147:30b64687e01f 10655 #define DSI_WPCR0_TCLKZEROEN 0x00100000U /*!< Timer for t-CLKZERO Enable */
<> 147:30b64687e01f 10656 #define DSI_WPCR0_THSPREPEN 0x00200000U /*!< Timer for t-HSPREP Enable */
<> 147:30b64687e01f 10657 #define DSI_WPCR0_THSTRAILEN 0x00400000U /*!< Timer for t-HSTRAIL Enable */
<> 147:30b64687e01f 10658 #define DSI_WPCR0_THSZEROEN 0x00800000U /*!< Timer for t-HSZERO Enable */
<> 147:30b64687e01f 10659 #define DSI_WPCR0_TLPXDEN 0x01000000U /*!< Timer for t-LPXD Enable */
<> 147:30b64687e01f 10660 #define DSI_WPCR0_THSEXITEN 0x02000000U /*!< Timer for t-HSEXIT Enable */
<> 147:30b64687e01f 10661 #define DSI_WPCR0_TLPXCEN 0x04000000U /*!< Timer for t-LPXC Enable */
<> 147:30b64687e01f 10662 #define DSI_WPCR0_TCLKPOSTEN 0x08000000U /*!< Timer for t-CLKPOST Enable */
<> 147:30b64687e01f 10663
<> 147:30b64687e01f 10664 /******************* Bit definition for DSI_WPCR1 register ***************/
<> 147:30b64687e01f 10665 #define DSI_WPCR1_HSTXDCL 0x00000003U /*!< High-Speed Transmission Delay on Clock Lane */
<> 147:30b64687e01f 10666 #define DSI_WPCR1_HSTXDCL0 0x00000001U
<> 147:30b64687e01f 10667 #define DSI_WPCR1_HSTXDCL1 0x00000002U
<> 147:30b64687e01f 10668
<> 147:30b64687e01f 10669 #define DSI_WPCR1_HSTXDDL 0x0000000CU /*!< High-Speed Transmission Delay on Data Lane */
<> 147:30b64687e01f 10670 #define DSI_WPCR1_HSTXDDL0 0x00000004U
<> 147:30b64687e01f 10671 #define DSI_WPCR1_HSTXDDL1 0x00000008U
<> 147:30b64687e01f 10672
<> 147:30b64687e01f 10673 #define DSI_WPCR1_LPSRCCL 0x000000C0U /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
<> 147:30b64687e01f 10674 #define DSI_WPCR1_LPSRCCL0 0x00000040U
<> 147:30b64687e01f 10675 #define DSI_WPCR1_LPSRCCL1 0x00000080U
<> 147:30b64687e01f 10676
<> 147:30b64687e01f 10677 #define DSI_WPCR1_LPSRCDL 0x00000300U /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
<> 147:30b64687e01f 10678 #define DSI_WPCR1_LPSRCDL0 0x00000100U
<> 147:30b64687e01f 10679 #define DSI_WPCR1_LPSRCDL1 0x00000200U
<> 147:30b64687e01f 10680
<> 147:30b64687e01f 10681 #define DSI_WPCR1_SDDC 0x00001000U /*!< SDD Control */
<> 147:30b64687e01f 10682
<> 147:30b64687e01f 10683 #define DSI_WPCR1_LPRXVCDL 0x0000C000U /*!< Low-Power Reception V-IL Compensation on Data Lanes */
<> 147:30b64687e01f 10684 #define DSI_WPCR1_LPRXVCDL0 0x00004000U
<> 147:30b64687e01f 10685 #define DSI_WPCR1_LPRXVCDL1 0x00008000U
<> 147:30b64687e01f 10686
<> 147:30b64687e01f 10687 #define DSI_WPCR1_HSTXSRCCL 0x00030000U /*!< High-Speed Transmission Delay on Clock Lane */
<> 147:30b64687e01f 10688 #define DSI_WPCR1_HSTXSRCCL0 0x00010000U
<> 147:30b64687e01f 10689 #define DSI_WPCR1_HSTXSRCCL1 0x00020000U
<> 147:30b64687e01f 10690
<> 147:30b64687e01f 10691 #define DSI_WPCR1_HSTXSRCDL 0x000C0000U /*!< High-Speed Transmission Delay on Data Lane */
<> 147:30b64687e01f 10692 #define DSI_WPCR1_HSTXSRCDL0 0x00040000U
<> 147:30b64687e01f 10693 #define DSI_WPCR1_HSTXSRCDL1 0x00080000U
<> 147:30b64687e01f 10694
<> 147:30b64687e01f 10695 #define DSI_WPCR1_FLPRXLPM 0x00400000U /*!< Forces LP Receiver in Low-Power Mode */
<> 147:30b64687e01f 10696
<> 147:30b64687e01f 10697 #define DSI_WPCR1_LPRXFT 0x06000000U /*!< Low-Power RX low-pass Filtering Tuning */
<> 147:30b64687e01f 10698 #define DSI_WPCR1_LPRXFT0 0x02000000U
<> 147:30b64687e01f 10699 #define DSI_WPCR1_LPRXFT1 0x04000000U
<> 147:30b64687e01f 10700
<> 147:30b64687e01f 10701 /******************* Bit definition for DSI_WPCR2 register ***************/
<> 147:30b64687e01f 10702 #define DSI_WPCR2_TCLKPREP 0x000000FFU /*!< t-CLKPREP */
<> 147:30b64687e01f 10703 #define DSI_WPCR2_TCLKPREP0 0x00000001U
<> 147:30b64687e01f 10704 #define DSI_WPCR2_TCLKPREP1 0x00000002U
<> 147:30b64687e01f 10705 #define DSI_WPCR2_TCLKPREP2 0x00000004U
<> 147:30b64687e01f 10706 #define DSI_WPCR2_TCLKPREP3 0x00000008U
<> 147:30b64687e01f 10707 #define DSI_WPCR2_TCLKPREP4 0x00000010U
<> 147:30b64687e01f 10708 #define DSI_WPCR2_TCLKPREP5 0x00000020U
<> 147:30b64687e01f 10709 #define DSI_WPCR2_TCLKPREP6 0x00000040U
<> 147:30b64687e01f 10710 #define DSI_WPCR2_TCLKPREP7 0x00000080U
<> 147:30b64687e01f 10711
<> 147:30b64687e01f 10712 #define DSI_WPCR2_TCLKZERO 0x0000FF00U /*!< t-CLKZERO */
<> 147:30b64687e01f 10713 #define DSI_WPCR2_TCLKZERO0 0x00000100U
<> 147:30b64687e01f 10714 #define DSI_WPCR2_TCLKZERO1 0x00000200U
<> 147:30b64687e01f 10715 #define DSI_WPCR2_TCLKZERO2 0x00000400U
<> 147:30b64687e01f 10716 #define DSI_WPCR2_TCLKZERO3 0x00000800U
<> 147:30b64687e01f 10717 #define DSI_WPCR2_TCLKZERO4 0x00001000U
<> 147:30b64687e01f 10718 #define DSI_WPCR2_TCLKZERO5 0x00002000U
<> 147:30b64687e01f 10719 #define DSI_WPCR2_TCLKZERO6 0x00004000U
<> 147:30b64687e01f 10720 #define DSI_WPCR2_TCLKZERO7 0x00008000U
<> 147:30b64687e01f 10721
<> 147:30b64687e01f 10722 #define DSI_WPCR2_THSPREP 0x00FF0000U /*!< t-HSPREP */
<> 147:30b64687e01f 10723 #define DSI_WPCR2_THSPREP0 0x00010000U
<> 147:30b64687e01f 10724 #define DSI_WPCR2_THSPREP1 0x00020000U
<> 147:30b64687e01f 10725 #define DSI_WPCR2_THSPREP2 0x00040000U
<> 147:30b64687e01f 10726 #define DSI_WPCR2_THSPREP3 0x00080000U
<> 147:30b64687e01f 10727 #define DSI_WPCR2_THSPREP4 0x00100000U
<> 147:30b64687e01f 10728 #define DSI_WPCR2_THSPREP5 0x00200000U
<> 147:30b64687e01f 10729 #define DSI_WPCR2_THSPREP6 0x00400000U
<> 147:30b64687e01f 10730 #define DSI_WPCR2_THSPREP7 0x00800000U
<> 147:30b64687e01f 10731
<> 147:30b64687e01f 10732 #define DSI_WPCR2_THSTRAIL 0xFF000000U /*!< t-HSTRAIL */
<> 147:30b64687e01f 10733 #define DSI_WPCR2_THSTRAIL0 0x01000000U
<> 147:30b64687e01f 10734 #define DSI_WPCR2_THSTRAIL1 0x02000000U
<> 147:30b64687e01f 10735 #define DSI_WPCR2_THSTRAIL2 0x04000000U
<> 147:30b64687e01f 10736 #define DSI_WPCR2_THSTRAIL3 0x08000000U
<> 147:30b64687e01f 10737 #define DSI_WPCR2_THSTRAIL4 0x10000000U
<> 147:30b64687e01f 10738 #define DSI_WPCR2_THSTRAIL5 0x20000000U
<> 147:30b64687e01f 10739 #define DSI_WPCR2_THSTRAIL6 0x40000000U
<> 147:30b64687e01f 10740 #define DSI_WPCR2_THSTRAIL7 0x80000000U
<> 147:30b64687e01f 10741
<> 147:30b64687e01f 10742 /******************* Bit definition for DSI_WPCR3 register ***************/
<> 147:30b64687e01f 10743 #define DSI_WPCR3_THSZERO 0x000000FFU /*!< t-HSZERO */
<> 147:30b64687e01f 10744 #define DSI_WPCR3_THSZERO0 0x00000001U
<> 147:30b64687e01f 10745 #define DSI_WPCR3_THSZERO1 0x00000002U
<> 147:30b64687e01f 10746 #define DSI_WPCR3_THSZERO2 0x00000004U
<> 147:30b64687e01f 10747 #define DSI_WPCR3_THSZERO3 0x00000008U
<> 147:30b64687e01f 10748 #define DSI_WPCR3_THSZERO4 0x00000010U
<> 147:30b64687e01f 10749 #define DSI_WPCR3_THSZERO5 0x00000020U
<> 147:30b64687e01f 10750 #define DSI_WPCR3_THSZERO6 0x00000040U
<> 147:30b64687e01f 10751 #define DSI_WPCR3_THSZERO7 0x00000080U
<> 147:30b64687e01f 10752
<> 147:30b64687e01f 10753 #define DSI_WPCR3_TLPXD 0x0000FF00U /*!< t-LPXD */
<> 147:30b64687e01f 10754 #define DSI_WPCR3_TLPXD0 0x00000100U
<> 147:30b64687e01f 10755 #define DSI_WPCR3_TLPXD1 0x00000200U
<> 147:30b64687e01f 10756 #define DSI_WPCR3_TLPXD2 0x00000400U
<> 147:30b64687e01f 10757 #define DSI_WPCR3_TLPXD3 0x00000800U
<> 147:30b64687e01f 10758 #define DSI_WPCR3_TLPXD4 0x00001000U
<> 147:30b64687e01f 10759 #define DSI_WPCR3_TLPXD5 0x00002000U
<> 147:30b64687e01f 10760 #define DSI_WPCR3_TLPXD6 0x00004000U
<> 147:30b64687e01f 10761 #define DSI_WPCR3_TLPXD7 0x00008000U
<> 147:30b64687e01f 10762
<> 147:30b64687e01f 10763 #define DSI_WPCR3_THSEXIT 0x00FF0000U /*!< t-HSEXIT */
<> 147:30b64687e01f 10764 #define DSI_WPCR3_THSEXIT0 0x00010000U
<> 147:30b64687e01f 10765 #define DSI_WPCR3_THSEXIT1 0x00020000U
<> 147:30b64687e01f 10766 #define DSI_WPCR3_THSEXIT2 0x00040000U
<> 147:30b64687e01f 10767 #define DSI_WPCR3_THSEXIT3 0x00080000U
<> 147:30b64687e01f 10768 #define DSI_WPCR3_THSEXIT4 0x00100000U
<> 147:30b64687e01f 10769 #define DSI_WPCR3_THSEXIT5 0x00200000U
<> 147:30b64687e01f 10770 #define DSI_WPCR3_THSEXIT6 0x00400000U
<> 147:30b64687e01f 10771 #define DSI_WPCR3_THSEXIT7 0x00800000U
<> 147:30b64687e01f 10772
<> 147:30b64687e01f 10773 #define DSI_WPCR3_TLPXC 0xFF000000U /*!< t-LPXC */
<> 147:30b64687e01f 10774 #define DSI_WPCR3_TLPXC0 0x01000000U
<> 147:30b64687e01f 10775 #define DSI_WPCR3_TLPXC1 0x02000000U
<> 147:30b64687e01f 10776 #define DSI_WPCR3_TLPXC2 0x04000000U
<> 147:30b64687e01f 10777 #define DSI_WPCR3_TLPXC3 0x08000000U
<> 147:30b64687e01f 10778 #define DSI_WPCR3_TLPXC4 0x10000000U
<> 147:30b64687e01f 10779 #define DSI_WPCR3_TLPXC5 0x20000000U
<> 147:30b64687e01f 10780 #define DSI_WPCR3_TLPXC6 0x40000000U
<> 147:30b64687e01f 10781 #define DSI_WPCR3_TLPXC7 0x80000000U
<> 147:30b64687e01f 10782
<> 147:30b64687e01f 10783 /******************* Bit definition for DSI_WPCR4 register ***************/
<> 147:30b64687e01f 10784 #define DSI_WPCR4_TCLKPOST 0x000000FFU /*!< t-CLKPOST */
<> 147:30b64687e01f 10785 #define DSI_WPCR4_TCLKPOST0 0x00000001U
<> 147:30b64687e01f 10786 #define DSI_WPCR4_TCLKPOST1 0x00000002U
<> 147:30b64687e01f 10787 #define DSI_WPCR4_TCLKPOST2 0x00000004U
<> 147:30b64687e01f 10788 #define DSI_WPCR4_TCLKPOST3 0x00000008U
<> 147:30b64687e01f 10789 #define DSI_WPCR4_TCLKPOST4 0x00000010U
<> 147:30b64687e01f 10790 #define DSI_WPCR4_TCLKPOST5 0x00000020U
<> 147:30b64687e01f 10791 #define DSI_WPCR4_TCLKPOST6 0x00000040U
<> 147:30b64687e01f 10792 #define DSI_WPCR4_TCLKPOST7 0x00000080U
<> 147:30b64687e01f 10793
<> 147:30b64687e01f 10794 /******************* Bit definition for DSI_WRPCR register ***************/
<> 147:30b64687e01f 10795 #define DSI_WRPCR_PLLEN 0x00000001U /*!< PLL Enable */
<> 147:30b64687e01f 10796 #define DSI_WRPCR_PLL_NDIV 0x000001FCU /*!< PLL Loop Division Factor */
<> 147:30b64687e01f 10797 #define DSI_WRPCR_PLL_NDIV0 0x00000004U
<> 147:30b64687e01f 10798 #define DSI_WRPCR_PLL_NDIV1 0x00000008U
<> 147:30b64687e01f 10799 #define DSI_WRPCR_PLL_NDIV2 0x00000010U
<> 147:30b64687e01f 10800 #define DSI_WRPCR_PLL_NDIV3 0x00000020U
<> 147:30b64687e01f 10801 #define DSI_WRPCR_PLL_NDIV4 0x00000040U
<> 147:30b64687e01f 10802 #define DSI_WRPCR_PLL_NDIV5 0x00000080U
<> 147:30b64687e01f 10803 #define DSI_WRPCR_PLL_NDIV6 0x00000100U
<> 147:30b64687e01f 10804
<> 147:30b64687e01f 10805 #define DSI_WRPCR_PLL_IDF 0x00007800U /*!< PLL Input Division Factor */
<> 147:30b64687e01f 10806 #define DSI_WRPCR_PLL_IDF0 0x00000800U
<> 147:30b64687e01f 10807 #define DSI_WRPCR_PLL_IDF1 0x00001000U
<> 147:30b64687e01f 10808 #define DSI_WRPCR_PLL_IDF2 0x00002000U
<> 147:30b64687e01f 10809 #define DSI_WRPCR_PLL_IDF3 0x00004000U
<> 147:30b64687e01f 10810
<> 147:30b64687e01f 10811 #define DSI_WRPCR_PLL_ODF 0x00030000U /*!< PLL Output Division Factor */
<> 147:30b64687e01f 10812 #define DSI_WRPCR_PLL_ODF0 0x00010000U
<> 147:30b64687e01f 10813 #define DSI_WRPCR_PLL_ODF1 0x00020000U
<> 147:30b64687e01f 10814
<> 147:30b64687e01f 10815 #define DSI_WRPCR_REGEN 0x01000000U /*!< Regulator Enable */
<> 147:30b64687e01f 10816
<> 147:30b64687e01f 10817 /**
<> 147:30b64687e01f 10818 * @}
<> 147:30b64687e01f 10819 */
<> 147:30b64687e01f 10820
<> 147:30b64687e01f 10821 /**
<> 147:30b64687e01f 10822 * @}
<> 147:30b64687e01f 10823 */
<> 147:30b64687e01f 10824
<> 147:30b64687e01f 10825 /** @addtogroup Exported_macros
<> 147:30b64687e01f 10826 * @{
<> 147:30b64687e01f 10827 */
<> 147:30b64687e01f 10828
<> 147:30b64687e01f 10829 /******************************* ADC Instances ********************************/
<> 147:30b64687e01f 10830 #define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \
<> 147:30b64687e01f 10831 ((__INSTANCE__) == ADC2) || \
<> 147:30b64687e01f 10832 ((__INSTANCE__) == ADC3))
<> 147:30b64687e01f 10833
<> 147:30b64687e01f 10834 /******************************* CAN Instances ********************************/
<> 147:30b64687e01f 10835 #define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) || \
<> 147:30b64687e01f 10836 ((__INSTANCE__) == CAN2) || \
<> 147:30b64687e01f 10837 ((__INSTANCE__) == CAN3))
<> 147:30b64687e01f 10838 /******************************* CRC Instances ********************************/
<> 147:30b64687e01f 10839 #define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
<> 147:30b64687e01f 10840
<> 147:30b64687e01f 10841 /******************************* DAC Instances ********************************/
<> 147:30b64687e01f 10842 #define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
<> 147:30b64687e01f 10843
<> 147:30b64687e01f 10844 /******************************* DCMI Instances *******************************/
<> 147:30b64687e01f 10845 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
<> 147:30b64687e01f 10846
<> 147:30b64687e01f 10847 /****************************** DFSDM Instances *******************************/
<> 147:30b64687e01f 10848 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
<> 147:30b64687e01f 10849 ((INSTANCE) == DFSDM1_Filter1) || \
<> 147:30b64687e01f 10850 ((INSTANCE) == DFSDM1_Filter2) || \
<> 147:30b64687e01f 10851 ((INSTANCE) == DFSDM1_Filter3))
<> 147:30b64687e01f 10852
<> 147:30b64687e01f 10853 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
<> 147:30b64687e01f 10854 ((INSTANCE) == DFSDM1_Channel1) || \
<> 147:30b64687e01f 10855 ((INSTANCE) == DFSDM1_Channel2) || \
<> 147:30b64687e01f 10856 ((INSTANCE) == DFSDM1_Channel3) || \
<> 147:30b64687e01f 10857 ((INSTANCE) == DFSDM1_Channel4) || \
<> 147:30b64687e01f 10858 ((INSTANCE) == DFSDM1_Channel5) || \
<> 147:30b64687e01f 10859 ((INSTANCE) == DFSDM1_Channel6) || \
<> 147:30b64687e01f 10860 ((INSTANCE) == DFSDM1_Channel7))
<> 147:30b64687e01f 10861
<> 147:30b64687e01f 10862 /******************************* DMA2D Instances *******************************/
<> 147:30b64687e01f 10863 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
<> 147:30b64687e01f 10864
<> 147:30b64687e01f 10865 /******************************** DMA Instances *******************************/
<> 147:30b64687e01f 10866 #define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \
<> 147:30b64687e01f 10867 ((__INSTANCE__) == DMA1_Stream1) || \
<> 147:30b64687e01f 10868 ((__INSTANCE__) == DMA1_Stream2) || \
<> 147:30b64687e01f 10869 ((__INSTANCE__) == DMA1_Stream3) || \
<> 147:30b64687e01f 10870 ((__INSTANCE__) == DMA1_Stream4) || \
<> 147:30b64687e01f 10871 ((__INSTANCE__) == DMA1_Stream5) || \
<> 147:30b64687e01f 10872 ((__INSTANCE__) == DMA1_Stream6) || \
<> 147:30b64687e01f 10873 ((__INSTANCE__) == DMA1_Stream7) || \
<> 147:30b64687e01f 10874 ((__INSTANCE__) == DMA2_Stream0) || \
<> 147:30b64687e01f 10875 ((__INSTANCE__) == DMA2_Stream1) || \
<> 147:30b64687e01f 10876 ((__INSTANCE__) == DMA2_Stream2) || \
<> 147:30b64687e01f 10877 ((__INSTANCE__) == DMA2_Stream3) || \
<> 147:30b64687e01f 10878 ((__INSTANCE__) == DMA2_Stream4) || \
<> 147:30b64687e01f 10879 ((__INSTANCE__) == DMA2_Stream5) || \
<> 147:30b64687e01f 10880 ((__INSTANCE__) == DMA2_Stream6) || \
<> 147:30b64687e01f 10881 ((__INSTANCE__) == DMA2_Stream7))
<> 147:30b64687e01f 10882
<> 147:30b64687e01f 10883 /******************************* GPIO Instances *******************************/
<> 147:30b64687e01f 10884 #define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
<> 157:ff67d9f36b67 10885 ((__INSTANCE__) == GPIOB) || \
<> 157:ff67d9f36b67 10886 ((__INSTANCE__) == GPIOC) || \
<> 157:ff67d9f36b67 10887 ((__INSTANCE__) == GPIOD) || \
<> 157:ff67d9f36b67 10888 ((__INSTANCE__) == GPIOE) || \
<> 157:ff67d9f36b67 10889 ((__INSTANCE__) == GPIOF) || \
<> 157:ff67d9f36b67 10890 ((__INSTANCE__) == GPIOG) || \
<> 157:ff67d9f36b67 10891 ((__INSTANCE__) == GPIOH) || \
<> 157:ff67d9f36b67 10892 ((__INSTANCE__) == GPIOI) || \
<> 157:ff67d9f36b67 10893 ((__INSTANCE__) == GPIOJ) || \
<> 157:ff67d9f36b67 10894 ((__INSTANCE__) == GPIOK))
<> 147:30b64687e01f 10895
<> 147:30b64687e01f 10896 #define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \
<> 157:ff67d9f36b67 10897 ((__INSTANCE__) == GPIOB) || \
<> 157:ff67d9f36b67 10898 ((__INSTANCE__) == GPIOC) || \
<> 157:ff67d9f36b67 10899 ((__INSTANCE__) == GPIOD) || \
<> 157:ff67d9f36b67 10900 ((__INSTANCE__) == GPIOE) || \
<> 157:ff67d9f36b67 10901 ((__INSTANCE__) == GPIOF) || \
<> 157:ff67d9f36b67 10902 ((__INSTANCE__) == GPIOG) || \
<> 157:ff67d9f36b67 10903 ((__INSTANCE__) == GPIOH) || \
<> 157:ff67d9f36b67 10904 ((__INSTANCE__) == GPIOI) || \
<> 157:ff67d9f36b67 10905 ((__INSTANCE__) == GPIOJ) || \
<> 157:ff67d9f36b67 10906 ((__INSTANCE__) == GPIOK))
<> 147:30b64687e01f 10907
<> 147:30b64687e01f 10908 /****************************** CEC Instances *********************************/
<> 147:30b64687e01f 10909 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
<> 147:30b64687e01f 10910
<> 147:30b64687e01f 10911 /****************************** QSPI Instances *********************************/
<> 147:30b64687e01f 10912 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
<> 147:30b64687e01f 10913
<> 147:30b64687e01f 10914
<> 147:30b64687e01f 10915 /******************************** I2C Instances *******************************/
<> 147:30b64687e01f 10916 #define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \
<> 157:ff67d9f36b67 10917 ((__INSTANCE__) == I2C2) || \
<> 157:ff67d9f36b67 10918 ((__INSTANCE__) == I2C3) || \
<> 157:ff67d9f36b67 10919 ((__INSTANCE__) == I2C4))
<> 147:30b64687e01f 10920
<> 147:30b64687e01f 10921 /******************************** I2S Instances *******************************/
<> 147:30b64687e01f 10922 #define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
<> 157:ff67d9f36b67 10923 ((__INSTANCE__) == SPI2) || \
<> 157:ff67d9f36b67 10924 ((__INSTANCE__) == SPI3))
<> 147:30b64687e01f 10925
<> 147:30b64687e01f 10926 /******************************* LPTIM Instances ********************************/
<> 147:30b64687e01f 10927 #define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
<> 147:30b64687e01f 10928
<> 147:30b64687e01f 10929 /****************************** LTDC Instances ********************************/
<> 147:30b64687e01f 10930 #define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
<> 147:30b64687e01f 10931
<> 147:30b64687e01f 10932 /****************************** MDIOS Instances ********************************/
<> 147:30b64687e01f 10933 #define IS_MDIOS_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == MDIOS)
<> 147:30b64687e01f 10934
<> 147:30b64687e01f 10935 /****************************** MDIOS Instances ********************************/
<> 147:30b64687e01f 10936 #define IS_JPEG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == JPEG)
<> 147:30b64687e01f 10937
<> 157:ff67d9f36b67 10938
<> 147:30b64687e01f 10939 /******************************* RNG Instances ********************************/
<> 147:30b64687e01f 10940 #define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
<> 147:30b64687e01f 10941
<> 147:30b64687e01f 10942 /****************************** RTC Instances *********************************/
<> 147:30b64687e01f 10943 #define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
<> 147:30b64687e01f 10944
<> 147:30b64687e01f 10945 /******************************* SAI Instances ********************************/
<> 147:30b64687e01f 10946 #define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \
<> 147:30b64687e01f 10947 ((__PERIPH__) == SAI1_Block_B) || \
<> 147:30b64687e01f 10948 ((__PERIPH__) == SAI2_Block_A) || \
<> 147:30b64687e01f 10949 ((__PERIPH__) == SAI2_Block_B))
<> 147:30b64687e01f 10950 /* Legacy define */
<> 147:30b64687e01f 10951 #define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
<> 147:30b64687e01f 10952
<> 147:30b64687e01f 10953 /******************************** SDMMC Instances *******************************/
<> 147:30b64687e01f 10954 #define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \
<> 147:30b64687e01f 10955 ((__INSTANCE__) == SDMMC2))
<> 147:30b64687e01f 10956
<> 147:30b64687e01f 10957 /****************************** SPDIFRX Instances *********************************/
<> 147:30b64687e01f 10958 #define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
<> 147:30b64687e01f 10959
<> 147:30b64687e01f 10960 /******************************** SPI Instances *******************************/
<> 147:30b64687e01f 10961 #define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \
<> 157:ff67d9f36b67 10962 ((__INSTANCE__) == SPI2) || \
<> 157:ff67d9f36b67 10963 ((__INSTANCE__) == SPI3) || \
<> 157:ff67d9f36b67 10964 ((__INSTANCE__) == SPI4) || \
<> 157:ff67d9f36b67 10965 ((__INSTANCE__) == SPI5) || \
<> 157:ff67d9f36b67 10966 ((__INSTANCE__) == SPI6))
<> 147:30b64687e01f 10967
<> 147:30b64687e01f 10968 /****************** TIM Instances : All supported instances *******************/
<> 147:30b64687e01f 10969 #define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 10970 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 10971 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 10972 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 10973 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 10974 ((__INSTANCE__) == TIM6) || \
<> 147:30b64687e01f 10975 ((__INSTANCE__) == TIM7) || \
<> 147:30b64687e01f 10976 ((__INSTANCE__) == TIM8) || \
<> 147:30b64687e01f 10977 ((__INSTANCE__) == TIM9) || \
<> 147:30b64687e01f 10978 ((__INSTANCE__) == TIM10) || \
<> 147:30b64687e01f 10979 ((__INSTANCE__) == TIM11) || \
<> 147:30b64687e01f 10980 ((__INSTANCE__) == TIM12) || \
<> 147:30b64687e01f 10981 ((__INSTANCE__) == TIM13) || \
<> 147:30b64687e01f 10982 ((__INSTANCE__) == TIM14))
<> 147:30b64687e01f 10983
<> 147:30b64687e01f 10984 /************* TIM Instances : at least 1 capture/compare channel *************/
<> 147:30b64687e01f 10985 #define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 10986 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 10987 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 10988 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 10989 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 10990 ((__INSTANCE__) == TIM8) || \
<> 147:30b64687e01f 10991 ((__INSTANCE__) == TIM9) || \
<> 147:30b64687e01f 10992 ((__INSTANCE__) == TIM10) || \
<> 147:30b64687e01f 10993 ((__INSTANCE__) == TIM11) || \
<> 147:30b64687e01f 10994 ((__INSTANCE__) == TIM12) || \
<> 147:30b64687e01f 10995 ((__INSTANCE__) == TIM13) || \
<> 147:30b64687e01f 10996 ((__INSTANCE__) == TIM14))
<> 147:30b64687e01f 10997
<> 147:30b64687e01f 10998 /************ TIM Instances : at least 2 capture/compare channels *************/
<> 147:30b64687e01f 10999 #define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11000 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11001 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11002 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11003 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11004 ((__INSTANCE__) == TIM8) || \
<> 147:30b64687e01f 11005 ((__INSTANCE__) == TIM9) || \
<> 147:30b64687e01f 11006 ((__INSTANCE__) == TIM12))
<> 147:30b64687e01f 11007
<> 147:30b64687e01f 11008 /************ TIM Instances : at least 3 capture/compare channels *************/
<> 147:30b64687e01f 11009 #define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11010 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11011 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11012 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11013 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11014 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11015
<> 147:30b64687e01f 11016 /************ TIM Instances : at least 4 capture/compare channels *************/
<> 147:30b64687e01f 11017 #define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11018 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11019 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11020 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11021 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11022 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11023
<> 147:30b64687e01f 11024 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
<> 147:30b64687e01f 11025 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
<> 147:30b64687e01f 11026 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11027 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11028
<> 147:30b64687e01f 11029 /****************** TIM Instances : supporting OCxREF clear *******************/
<> 147:30b64687e01f 11030 #define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11031 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11032 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11033 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11034 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11035 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11036
<> 147:30b64687e01f 11037 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
<> 147:30b64687e01f 11038 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11039 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11040 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11041 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11042 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11043 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11044 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11045
<> 147:30b64687e01f 11046 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
<> 147:30b64687e01f 11047 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11048 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11049 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11050 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11051 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11052 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11053 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11054 /****************** TIM Instances : at least 5 capture/compare channels *******/
<> 147:30b64687e01f 11055 #define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11056 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11057 ((__INSTANCE__) == TIM8) )
<> 147:30b64687e01f 11058
<> 147:30b64687e01f 11059 /****************** TIM Instances : at least 6 capture/compare channels *******/
<> 147:30b64687e01f 11060 #define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11061 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11062 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11063
<> 147:30b64687e01f 11064
<> 147:30b64687e01f 11065 /******************** TIM Instances : Advanced-control timers *****************/
<> 147:30b64687e01f 11066 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11067 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11068
<> 147:30b64687e01f 11069 /****************** TIM Instances : supporting 2 break inputs *****************/
<> 147:30b64687e01f 11070 #define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11071 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11072 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11073
<> 147:30b64687e01f 11074 /******************* TIM Instances : Timer input XOR function *****************/
<> 147:30b64687e01f 11075 #define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11076 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11077 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11078 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11079 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11080 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11081
<> 147:30b64687e01f 11082 /****************** TIM Instances : DMA requests generation (UDE) *************/
<> 147:30b64687e01f 11083 #define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11084 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11085 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11086 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11087 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11088 ((__INSTANCE__) == TIM6) || \
<> 147:30b64687e01f 11089 ((__INSTANCE__) == TIM7) || \
<> 147:30b64687e01f 11090 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11091
<> 147:30b64687e01f 11092 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
<> 147:30b64687e01f 11093 #define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11094 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11095 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11096 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11097 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11098 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11099
<> 147:30b64687e01f 11100 /************ TIM Instances : DMA requests generation (COMDE) *****************/
<> 147:30b64687e01f 11101 #define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11102 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11103 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11104 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11105 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11106 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11107
<> 147:30b64687e01f 11108 /******************** TIM Instances : DMA burst feature ***********************/
<> 147:30b64687e01f 11109 #define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11110 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11111 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11112 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11113 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11114 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11115
<> 147:30b64687e01f 11116 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
<> 147:30b64687e01f 11117 #define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11118 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11119 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11120 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11121 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11122 ((__INSTANCE__) == TIM6) || \
<> 147:30b64687e01f 11123 ((__INSTANCE__) == TIM7) || \
<> 147:30b64687e01f 11124 ((__INSTANCE__) == TIM8) || \
<> 147:30b64687e01f 11125 ((__INSTANCE__) == TIM13) || \
<> 147:30b64687e01f 11126 ((__INSTANCE__) == TIM14))
<> 147:30b64687e01f 11127
<> 147:30b64687e01f 11128 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
<> 147:30b64687e01f 11129 #define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11130 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11131 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11132 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11133 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11134 ((__INSTANCE__) == TIM8) || \
<> 147:30b64687e01f 11135 ((__INSTANCE__) == TIM9) || \
<> 147:30b64687e01f 11136 ((__INSTANCE__) == TIM12))
<> 147:30b64687e01f 11137
<> 147:30b64687e01f 11138 /********************** TIM Instances : 32 bit Counter ************************/
<> 147:30b64687e01f 11139 #define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11140 ((__INSTANCE__) == TIM5))
<> 147:30b64687e01f 11141
<> 147:30b64687e01f 11142 /***************** TIM Instances : external trigger input available ************/
<> 147:30b64687e01f 11143 #define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11144 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11145 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11146 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11147 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11148 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11149
<> 147:30b64687e01f 11150 /****************** TIM Instances : remapping capability **********************/
<> 147:30b64687e01f 11151 #define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11152 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11153 ((__INSTANCE__) == TIM11))
<> 147:30b64687e01f 11154
<> 147:30b64687e01f 11155 /******************* TIM Instances : output(s) available **********************/
<> 147:30b64687e01f 11156 #define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
<> 147:30b64687e01f 11157 ((((__INSTANCE__) == TIM1) && \
<> 147:30b64687e01f 11158 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11159 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11160 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11161 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11162 || \
<> 147:30b64687e01f 11163 (((__INSTANCE__) == TIM2) && \
<> 147:30b64687e01f 11164 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11165 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11166 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11167 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11168 || \
<> 147:30b64687e01f 11169 (((__INSTANCE__) == TIM3) && \
<> 147:30b64687e01f 11170 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11171 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11172 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11173 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11174 || \
<> 147:30b64687e01f 11175 (((__INSTANCE__) == TIM4) && \
<> 147:30b64687e01f 11176 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11177 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11178 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11179 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11180 || \
<> 147:30b64687e01f 11181 (((__INSTANCE__) == TIM5) && \
<> 147:30b64687e01f 11182 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11183 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11184 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11185 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11186 || \
<> 147:30b64687e01f 11187 (((__INSTANCE__) == TIM8) && \
<> 147:30b64687e01f 11188 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11189 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11190 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 147:30b64687e01f 11191 ((__CHANNEL__) == TIM_CHANNEL_4))) \
<> 147:30b64687e01f 11192 || \
<> 147:30b64687e01f 11193 (((__INSTANCE__) == TIM9) && \
<> 147:30b64687e01f 11194 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11195 ((__CHANNEL__) == TIM_CHANNEL_2))) \
<> 147:30b64687e01f 11196 || \
<> 147:30b64687e01f 11197 (((__INSTANCE__) == TIM10) && \
<> 147:30b64687e01f 11198 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 147:30b64687e01f 11199 || \
<> 147:30b64687e01f 11200 (((__INSTANCE__) == TIM11) && \
<> 147:30b64687e01f 11201 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 147:30b64687e01f 11202 || \
<> 147:30b64687e01f 11203 (((__INSTANCE__) == TIM12) && \
<> 147:30b64687e01f 11204 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11205 ((__CHANNEL__) == TIM_CHANNEL_2))) \
<> 147:30b64687e01f 11206 || \
<> 147:30b64687e01f 11207 (((__INSTANCE__) == TIM13) && \
<> 147:30b64687e01f 11208 (((__CHANNEL__) == TIM_CHANNEL_1))) \
<> 147:30b64687e01f 11209 || \
<> 147:30b64687e01f 11210 (((__INSTANCE__) == TIM14) && \
<> 147:30b64687e01f 11211 (((__CHANNEL__) == TIM_CHANNEL_1))))
<> 147:30b64687e01f 11212
<> 147:30b64687e01f 11213 /************ TIM Instances : complementary output(s) available ***************/
<> 147:30b64687e01f 11214 #define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
<> 147:30b64687e01f 11215 ((((__INSTANCE__) == TIM1) && \
<> 147:30b64687e01f 11216 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11217 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11218 ((__CHANNEL__) == TIM_CHANNEL_3))) \
<> 147:30b64687e01f 11219 || \
<> 147:30b64687e01f 11220 (((__INSTANCE__) == TIM8) && \
<> 147:30b64687e01f 11221 (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 147:30b64687e01f 11222 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 147:30b64687e01f 11223 ((__CHANNEL__) == TIM_CHANNEL_3))))
<> 147:30b64687e01f 11224
<> 147:30b64687e01f 11225 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
<> 147:30b64687e01f 11226 #define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11227 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11228 ((__INSTANCE__) == TIM8) )
<> 147:30b64687e01f 11229
<> 147:30b64687e01f 11230 /****************** TIM Instances : supporting synchronization ****************/
<> 147:30b64687e01f 11231 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
<> 147:30b64687e01f 11232 (((__INSTANCE__) == TIM1) || \
<> 147:30b64687e01f 11233 ((__INSTANCE__) == TIM2) || \
<> 147:30b64687e01f 11234 ((__INSTANCE__) == TIM3) || \
<> 147:30b64687e01f 11235 ((__INSTANCE__) == TIM4) || \
<> 147:30b64687e01f 11236 ((__INSTANCE__) == TIM5) || \
<> 147:30b64687e01f 11237 ((__INSTANCE__) == TIM6) || \
<> 147:30b64687e01f 11238 ((__INSTANCE__) == TIM7) || \
<> 147:30b64687e01f 11239 ((__INSTANCE__) == TIM8))
<> 147:30b64687e01f 11240
<> 147:30b64687e01f 11241 /******************** USART Instances : Synchronous mode **********************/
<> 147:30b64687e01f 11242 #define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11243 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11244 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11245 ((__INSTANCE__) == USART6))
<> 147:30b64687e01f 11246
<> 147:30b64687e01f 11247 /******************** UART Instances : Asynchronous mode **********************/
<> 147:30b64687e01f 11248 #define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11249 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11250 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11251 ((__INSTANCE__) == UART4) || \
<> 147:30b64687e01f 11252 ((__INSTANCE__) == UART5) || \
<> 147:30b64687e01f 11253 ((__INSTANCE__) == USART6) || \
<> 147:30b64687e01f 11254 ((__INSTANCE__) == UART7) || \
<> 147:30b64687e01f 11255 ((__INSTANCE__) == UART8))
<> 147:30b64687e01f 11256
<> 147:30b64687e01f 11257 /****************** UART Instances : Driver Enable *****************/
<> 147:30b64687e01f 11258 #define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11259 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11260 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11261 ((__INSTANCE__) == UART4) || \
<> 147:30b64687e01f 11262 ((__INSTANCE__) == UART5) || \
<> 147:30b64687e01f 11263 ((__INSTANCE__) == USART6) || \
<> 147:30b64687e01f 11264 ((__INSTANCE__) == UART7) || \
<> 147:30b64687e01f 11265 ((__INSTANCE__) == UART8))
<> 147:30b64687e01f 11266
<> 147:30b64687e01f 11267 /****************** UART Instances : Hardware Flow control ********************/
<> 147:30b64687e01f 11268 #define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11269 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11270 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11271 ((__INSTANCE__) == UART4) || \
<> 147:30b64687e01f 11272 ((__INSTANCE__) == UART5) || \
<> 147:30b64687e01f 11273 ((__INSTANCE__) == USART6) || \
<> 147:30b64687e01f 11274 ((__INSTANCE__) == UART7) || \
<> 147:30b64687e01f 11275 ((__INSTANCE__) == UART8))
<> 147:30b64687e01f 11276
<> 147:30b64687e01f 11277 /********************* UART Instances : Smart card mode ***********************/
<> 147:30b64687e01f 11278 #define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11279 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11280 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11281 ((__INSTANCE__) == USART6))
<> 147:30b64687e01f 11282
<> 147:30b64687e01f 11283 /*********************** UART Instances : IRDA mode ***************************/
<> 147:30b64687e01f 11284 #define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \
<> 147:30b64687e01f 11285 ((__INSTANCE__) == USART2) || \
<> 147:30b64687e01f 11286 ((__INSTANCE__) == USART3) || \
<> 147:30b64687e01f 11287 ((__INSTANCE__) == UART4) || \
<> 147:30b64687e01f 11288 ((__INSTANCE__) == UART5) || \
<> 147:30b64687e01f 11289 ((__INSTANCE__) == USART6) || \
<> 147:30b64687e01f 11290 ((__INSTANCE__) == UART7) || \
<> 147:30b64687e01f 11291 ((__INSTANCE__) == UART8))
<> 147:30b64687e01f 11292
<> 147:30b64687e01f 11293 /****************************** IWDG Instances ********************************/
<> 147:30b64687e01f 11294 #define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
<> 147:30b64687e01f 11295
<> 147:30b64687e01f 11296 /****************************** WWDG Instances ********************************/
<> 147:30b64687e01f 11297 #define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
<> 147:30b64687e01f 11298
<> 147:30b64687e01f 11299
<> 147:30b64687e01f 11300 /******************************************************************************/
<> 147:30b64687e01f 11301 /* For a painless codes migration between the STM32F7xx device product */
<> 147:30b64687e01f 11302 /* lines, the aliases defined below are put in place to overcome the */
<> 147:30b64687e01f 11303 /* differences in the interrupt handlers and IRQn definitions. */
<> 147:30b64687e01f 11304 /* No need to update developed interrupt code when moving across */
<> 147:30b64687e01f 11305 /* product lines within the same STM32F7 Family */
<> 147:30b64687e01f 11306 /******************************************************************************/
<> 147:30b64687e01f 11307
<> 147:30b64687e01f 11308 /* Aliases for __IRQn */
<> 147:30b64687e01f 11309 #define HASH_RNG_IRQn RNG_IRQn
<> 147:30b64687e01f 11310
<> 147:30b64687e01f 11311 /* Aliases for __IRQHandler */
<> 147:30b64687e01f 11312 #define HASH_RNG_IRQHandler RNG_IRQHandler
<> 147:30b64687e01f 11313
<> 147:30b64687e01f 11314 /**
<> 147:30b64687e01f 11315 * @}
<> 147:30b64687e01f 11316 */
<> 147:30b64687e01f 11317
<> 147:30b64687e01f 11318 /**
<> 147:30b64687e01f 11319 * @}
<> 147:30b64687e01f 11320 */
<> 147:30b64687e01f 11321
<> 147:30b64687e01f 11322 /**
<> 147:30b64687e01f 11323 * @}
<> 147:30b64687e01f 11324 */
<> 147:30b64687e01f 11325
<> 147:30b64687e01f 11326 #ifdef __cplusplus
<> 147:30b64687e01f 11327 }
<> 147:30b64687e01f 11328 #endif /* __cplusplus */
<> 147:30b64687e01f 11329
<> 147:30b64687e01f 11330 #endif /* __STM32F769xx_H */
<> 147:30b64687e01f 11331
<> 147:30b64687e01f 11332
<> 147:30b64687e01f 11333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/