mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Parent:
167:e84263d55307 
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_hal_dcmi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @brief Header file of DCMI HAL module.
<> 144:ef7eb2e8f9f7 6 ******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @attention
<> 144:ef7eb2e8f9f7 8 *
AnnaBridge 167:e84263d55307 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 12 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 13 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 14 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 17 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 19 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 20 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 ******************************************************************************
<> 144:ef7eb2e8f9f7 34 */
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 37 #ifndef __STM32F4xx_HAL_DCMI_H
<> 144:ef7eb2e8f9f7 38 #define __STM32F4xx_HAL_DCMI_H
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 41 extern "C" {
<> 144:ef7eb2e8f9f7 42 #endif
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
<> 144:ef7eb2e8f9f7 45 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) ||\
<> 144:ef7eb2e8f9f7 46 defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 47 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 48 #include "stm32f4xx_hal_def.h"
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 /* Include DCMI HAL Extended module */
<> 144:ef7eb2e8f9f7 51 /* (include on top of file since DCMI structures are defined in extended file) */
<> 144:ef7eb2e8f9f7 52 #include "stm32f4xx_hal_dcmi_ex.h"
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup DCMI DCMI
<> 144:ef7eb2e8f9f7 59 * @brief DCMI HAL module driver
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 64 /** @defgroup DCMI_Exported_Types DCMI Exported Types
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67 /**
<> 144:ef7eb2e8f9f7 68 * @brief HAL DCMI State structures definition
<> 144:ef7eb2e8f9f7 69 */
<> 144:ef7eb2e8f9f7 70 typedef enum
<> 144:ef7eb2e8f9f7 71 {
<> 144:ef7eb2e8f9f7 72 HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 73 HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
<> 144:ef7eb2e8f9f7 74 HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
<> 144:ef7eb2e8f9f7 75 HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
<> 144:ef7eb2e8f9f7 76 HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
<> 144:ef7eb2e8f9f7 77 HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
<> 144:ef7eb2e8f9f7 78 }HAL_DCMI_StateTypeDef;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /**
<> 144:ef7eb2e8f9f7 81 * @brief DCMI handle Structure definition
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 typedef struct
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 DCMI_TypeDef *Instance; /*!< DCMI Register base address */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 DCMI_InitTypeDef Init; /*!< DCMI parameters */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 HAL_LockTypeDef Lock; /*!< DCMI locking object */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 __IO HAL_DCMI_StateTypeDef State; /*!< DCMI state */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 __IO uint32_t XferCount; /*!< DMA transfer counter */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 __IO uint32_t XferSize; /*!< DMA transfer size */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 uint32_t XferTransferNumber; /*!< DMA transfer number */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 uint32_t pBuffPtr; /*!< Pointer to DMA output buffer */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer to the DMA handler */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 __IO uint32_t ErrorCode; /*!< DCMI Error code */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 }DCMI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @}
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 111 /** @defgroup DCMI_Exported_Constants DCMI Exported Constants
<> 144:ef7eb2e8f9f7 112 * @{
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /** @defgroup DCMI_Error_Code DCMI Error Code
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
AnnaBridge 167:e84263d55307 118 #define HAL_DCMI_ERROR_NONE 0x00000000U /*!< No error */
AnnaBridge 167:e84263d55307 119 #define HAL_DCMI_ERROR_OVR 0x00000001U /*!< Overrun error */
AnnaBridge 167:e84263d55307 120 #define HAL_DCMI_ERROR_SYNC 0x00000002U /*!< Synchronization error */
AnnaBridge 167:e84263d55307 121 #define HAL_DCMI_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
AnnaBridge 167:e84263d55307 122 #define HAL_DCMI_ERROR_DMA 0x00000040U /*!< DMA error */
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @defgroup DCMI_Capture_Mode DCMI Capture Mode
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
AnnaBridge 167:e84263d55307 130 #define DCMI_MODE_CONTINUOUS 0x00000000U /*!< The received data are transferred continuously
<> 144:ef7eb2e8f9f7 131 into the destination memory through the DMA */
<> 144:ef7eb2e8f9f7 132 #define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
<> 144:ef7eb2e8f9f7 133 frame and then transfers a single frame through the DMA */
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
AnnaBridge 167:e84263d55307 141 #define DCMI_SYNCHRO_HARDWARE 0x00000000U /*!< Hardware synchronization data capture (frame/line start/stop)
AnnaBridge 167:e84263d55307 142 is synchronized with the HSYNC/VSYNC signals */
AnnaBridge 167:e84263d55307 143 #define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
AnnaBridge 167:e84263d55307 144 synchronization codes embedded in the data flow */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /**
<> 144:ef7eb2e8f9f7 147 * @}
<> 144:ef7eb2e8f9f7 148 */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
AnnaBridge 167:e84263d55307 153 #define DCMI_PCKPOLARITY_FALLING 0x00000000U /*!< Pixel clock active on Falling edge */
AnnaBridge 167:e84263d55307 154 #define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @}
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
<> 144:ef7eb2e8f9f7 161 * @{
<> 144:ef7eb2e8f9f7 162 */
AnnaBridge 167:e84263d55307 163 #define DCMI_VSPOLARITY_LOW 0x00000000U /*!< Vertical synchronization active Low */
AnnaBridge 167:e84263d55307 164 #define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
<> 144:ef7eb2e8f9f7 171 * @{
<> 144:ef7eb2e8f9f7 172 */
AnnaBridge 167:e84263d55307 173 #define DCMI_HSPOLARITY_LOW 0x00000000U /*!< Horizontal synchronization active Low */
AnnaBridge 167:e84263d55307 174 #define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /**
<> 144:ef7eb2e8f9f7 177 * @}
<> 144:ef7eb2e8f9f7 178 */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 /** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
<> 144:ef7eb2e8f9f7 181 * @{
<> 144:ef7eb2e8f9f7 182 */
AnnaBridge 167:e84263d55307 183 #define DCMI_JPEG_DISABLE 0x00000000U /*!< Mode JPEG Disabled */
AnnaBridge 167:e84263d55307 184 #define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /**
<> 144:ef7eb2e8f9f7 187 * @}
<> 144:ef7eb2e8f9f7 188 */
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /** @defgroup DCMI_Capture_Rate DCMI Capture Rate
<> 144:ef7eb2e8f9f7 191 * @{
<> 144:ef7eb2e8f9f7 192 */
AnnaBridge 167:e84263d55307 193 #define DCMI_CR_ALL_FRAME 0x00000000U /*!< All frames are captured */
<> 144:ef7eb2e8f9f7 194 #define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
<> 144:ef7eb2e8f9f7 195 #define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /**
<> 144:ef7eb2e8f9f7 198 * @}
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
<> 144:ef7eb2e8f9f7 202 * @{
<> 144:ef7eb2e8f9f7 203 */
AnnaBridge 167:e84263d55307 204 #define DCMI_EXTEND_DATA_8B 0x00000000U /*!< Interface captures 8-bit data on every pixel clock */
<> 144:ef7eb2e8f9f7 205 #define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
<> 144:ef7eb2e8f9f7 206 #define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
<> 144:ef7eb2e8f9f7 207 #define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
AnnaBridge 167:e84263d55307 216 #define DCMI_WINDOW_COORDINATE 0x3FFFU /*!< Window coordinate */
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /**
<> 144:ef7eb2e8f9f7 219 * @}
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /** @defgroup DCMI_Window_Height DCMI Window Height
<> 144:ef7eb2e8f9f7 223 * @{
<> 144:ef7eb2e8f9f7 224 */
AnnaBridge 167:e84263d55307 225 #define DCMI_WINDOW_HEIGHT 0x1FFFU /*!< Window Height */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @}
<> 144:ef7eb2e8f9f7 229 */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
<> 144:ef7eb2e8f9f7 232 * @{
<> 144:ef7eb2e8f9f7 233 */
AnnaBridge 182:a56a73fd2a6f 234 #define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */
AnnaBridge 182:a56a73fd2a6f 235 #define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 /**
<> 144:ef7eb2e8f9f7 238 * @}
<> 144:ef7eb2e8f9f7 239 */
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /** @defgroup DCMI_interrupt_sources DCMI interrupt sources
<> 144:ef7eb2e8f9f7 242 * @{
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244 #define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
<> 144:ef7eb2e8f9f7 245 #define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
<> 144:ef7eb2e8f9f7 246 #define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
<> 144:ef7eb2e8f9f7 247 #define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
<> 144:ef7eb2e8f9f7 248 #define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
<> 144:ef7eb2e8f9f7 249 /**
<> 144:ef7eb2e8f9f7 250 * @}
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /** @defgroup DCMI_Flags DCMI Flags
<> 144:ef7eb2e8f9f7 254 * @{
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief DCMI SR register
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 #define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
<> 144:ef7eb2e8f9f7 261 #define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
<> 144:ef7eb2e8f9f7 262 #define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief DCMI RIS register
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS) /*!< Frame capture complete interrupt flag */
<> 144:ef7eb2e8f9f7 267 #define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RISR_OVR_RIS) /*!< Overrun interrupt flag */
<> 144:ef7eb2e8f9f7 268 #define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS) /*!< Synchronization error interrupt flag */
<> 144:ef7eb2e8f9f7 269 #define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS) /*!< VSYNC interrupt flag */
<> 144:ef7eb2e8f9f7 270 #define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS) /*!< Line interrupt flag */
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @brief DCMI MIS register
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 #define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
<> 144:ef7eb2e8f9f7 275 #define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
<> 144:ef7eb2e8f9f7 276 #define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
<> 144:ef7eb2e8f9f7 277 #define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
<> 144:ef7eb2e8f9f7 278 #define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
<> 144:ef7eb2e8f9f7 279 /**
<> 144:ef7eb2e8f9f7 280 * @}
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 288 /** @defgroup DCMI_Exported_Macros DCMI Exported Macros
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /** @brief Reset DCMI handle state
AnnaBridge 182:a56a73fd2a6f 293 * @param __HANDLE__ specifies the DCMI handle.
<> 144:ef7eb2e8f9f7 294 * @retval None
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Enable the DCMI.
AnnaBridge 182:a56a73fd2a6f 300 * @param __HANDLE__ DCMI handle
<> 144:ef7eb2e8f9f7 301 * @retval None
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /**
<> 144:ef7eb2e8f9f7 306 * @brief Disable the DCMI.
AnnaBridge 182:a56a73fd2a6f 307 * @param __HANDLE__ DCMI handle
<> 144:ef7eb2e8f9f7 308 * @retval None
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310 #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /* Interrupt & Flag management */
<> 144:ef7eb2e8f9f7 313 /**
<> 144:ef7eb2e8f9f7 314 * @brief Get the DCMI pending flag.
AnnaBridge 182:a56a73fd2a6f 315 * @param __HANDLE__ DCMI handle
AnnaBridge 182:a56a73fd2a6f 316 * @param __FLAG__ Get the specified flag.
<> 144:ef7eb2e8f9f7 317 * This parameter can be one of the following values (no combination allowed)
<> 144:ef7eb2e8f9f7 318 * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
<> 144:ef7eb2e8f9f7 319 * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
<> 144:ef7eb2e8f9f7 320 * @arg DCMI_FLAG_FNE: FIFO empty flag
<> 144:ef7eb2e8f9f7 321 * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
<> 144:ef7eb2e8f9f7 322 * @arg DCMI_FLAG_OVRRI: Overrun flag mask
<> 144:ef7eb2e8f9f7 323 * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
<> 144:ef7eb2e8f9f7 324 * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
<> 144:ef7eb2e8f9f7 325 * @arg DCMI_FLAG_LINERI: Line flag mask
<> 144:ef7eb2e8f9f7 326 * @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
<> 144:ef7eb2e8f9f7 327 * @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
<> 144:ef7eb2e8f9f7 328 * @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
<> 144:ef7eb2e8f9f7 329 * @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
<> 144:ef7eb2e8f9f7 330 * @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
<> 144:ef7eb2e8f9f7 331 * @retval The state of FLAG.
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 #define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
AnnaBridge 167:e84263d55307 334 ((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0U)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
AnnaBridge 167:e84263d55307 335 (((__FLAG__) & DCMI_SR_INDEX) == 0x0U)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /**
<> 144:ef7eb2e8f9f7 338 * @brief Clear the DCMI pending flags.
AnnaBridge 182:a56a73fd2a6f 339 * @param __HANDLE__ DCMI handle
AnnaBridge 182:a56a73fd2a6f 340 * @param __FLAG__ specifies the flag to clear.
<> 144:ef7eb2e8f9f7 341 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 342 * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
<> 144:ef7eb2e8f9f7 343 * @arg DCMI_FLAG_OVRRI: Overrun flag mask
<> 144:ef7eb2e8f9f7 344 * @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
<> 144:ef7eb2e8f9f7 345 * @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
<> 144:ef7eb2e8f9f7 346 * @arg DCMI_FLAG_LINERI: Line flag mask
<> 144:ef7eb2e8f9f7 347 * @retval None
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 /**
<> 144:ef7eb2e8f9f7 352 * @brief Enable the specified DCMI interrupts.
AnnaBridge 182:a56a73fd2a6f 353 * @param __HANDLE__ DCMI handle
AnnaBridge 182:a56a73fd2a6f 354 * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 355 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 356 * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
<> 144:ef7eb2e8f9f7 357 * @arg DCMI_IT_OVR: Overrun interrupt mask
<> 144:ef7eb2e8f9f7 358 * @arg DCMI_IT_ERR: Synchronization error interrupt mask
<> 144:ef7eb2e8f9f7 359 * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
<> 144:ef7eb2e8f9f7 360 * @arg DCMI_IT_LINE: Line interrupt mask
<> 144:ef7eb2e8f9f7 361 * @retval None
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 #define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @brief Disable the specified DCMI interrupts.
AnnaBridge 182:a56a73fd2a6f 367 * @param __HANDLE__ DCMI handle
AnnaBridge 182:a56a73fd2a6f 368 * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
<> 144:ef7eb2e8f9f7 369 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 370 * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
<> 144:ef7eb2e8f9f7 371 * @arg DCMI_IT_OVR: Overrun interrupt mask
<> 144:ef7eb2e8f9f7 372 * @arg DCMI_IT_ERR: Synchronization error interrupt mask
<> 144:ef7eb2e8f9f7 373 * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
<> 144:ef7eb2e8f9f7 374 * @arg DCMI_IT_LINE: Line interrupt mask
<> 144:ef7eb2e8f9f7 375 * @retval None
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377 #define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /**
<> 144:ef7eb2e8f9f7 380 * @brief Check whether the specified DCMI interrupt has occurred or not.
AnnaBridge 182:a56a73fd2a6f 381 * @param __HANDLE__ DCMI handle
AnnaBridge 182:a56a73fd2a6f 382 * @param __INTERRUPT__ specifies the DCMI interrupt source to check.
<> 144:ef7eb2e8f9f7 383 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 384 * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
<> 144:ef7eb2e8f9f7 385 * @arg DCMI_IT_OVR: Overrun interrupt mask
<> 144:ef7eb2e8f9f7 386 * @arg DCMI_IT_ERR: Synchronization error interrupt mask
<> 144:ef7eb2e8f9f7 387 * @arg DCMI_IT_VSYNC: VSYNC interrupt mask
<> 144:ef7eb2e8f9f7 388 * @arg DCMI_IT_LINE: Line interrupt mask
<> 144:ef7eb2e8f9f7 389 * @retval The state of INTERRUPT.
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391 #define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 398 /** @addtogroup DCMI_Exported_Functions DCMI Exported Functions
<> 144:ef7eb2e8f9f7 399 * @{
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 403 * @{
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 406 HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 407 HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);
AnnaBridge 167:e84263d55307 408 void HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);
AnnaBridge 167:e84263d55307 409 void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
<> 144:ef7eb2e8f9f7 410 /**
<> 144:ef7eb2e8f9f7 411 * @}
<> 144:ef7eb2e8f9f7 412 */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 /** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions
<> 144:ef7eb2e8f9f7 415 * @{
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 418 HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
<> 144:ef7eb2e8f9f7 419 HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
<> 144:ef7eb2e8f9f7 420 HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
<> 144:ef7eb2e8f9f7 421 HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
<> 144:ef7eb2e8f9f7 422 void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 423 void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 424 void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 425 void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 426 void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 427 void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 428 void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436 /* Peripheral Control functions ***********************************************/
AnnaBridge 167:e84263d55307 437 HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
AnnaBridge 167:e84263d55307 438 HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
AnnaBridge 167:e84263d55307 439 HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 440 /**
<> 144:ef7eb2e8f9f7 441 * @}
<> 144:ef7eb2e8f9f7 442 */
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions
<> 144:ef7eb2e8f9f7 445 * @{
<> 144:ef7eb2e8f9f7 446 */
<> 144:ef7eb2e8f9f7 447 /* Peripheral State functions *************************************************/
<> 144:ef7eb2e8f9f7 448 HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 449 uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
<> 144:ef7eb2e8f9f7 450 /**
<> 144:ef7eb2e8f9f7 451 * @}
<> 144:ef7eb2e8f9f7 452 */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @}
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 459 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 460 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 461 /** @defgroup DCMI_Private_Constants DCMI Private Constants
<> 144:ef7eb2e8f9f7 462 * @{
<> 144:ef7eb2e8f9f7 463 */
AnnaBridge 167:e84263d55307 464 #define DCMI_MIS_INDEX 0x1000U /*!< DCMI MIS register index */
AnnaBridge 167:e84263d55307 465 #define DCMI_SR_INDEX 0x2000U /*!< DCMI SR register index */
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * @}
<> 144:ef7eb2e8f9f7 468 */
<> 144:ef7eb2e8f9f7 469 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 470 /** @defgroup DCMI_Private_Macros DCMI Private Macros
<> 144:ef7eb2e8f9f7 471 * @{
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 #define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \
<> 144:ef7eb2e8f9f7 474 ((MODE) == DCMI_MODE_SNAPSHOT))
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 #define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \
<> 144:ef7eb2e8f9f7 477 ((MODE) == DCMI_SYNCHRO_EMBEDDED))
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 #define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \
<> 144:ef7eb2e8f9f7 480 ((POLARITY) == DCMI_PCKPOLARITY_RISING))
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 #define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 483 ((POLARITY) == DCMI_VSPOLARITY_HIGH))
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 #define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 486 ((POLARITY) == DCMI_HSPOLARITY_HIGH))
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \
<> 144:ef7eb2e8f9f7 489 ((JPEG_MODE) == DCMI_JPEG_ENABLE))
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 #define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME) || \
<> 144:ef7eb2e8f9f7 492 ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \
<> 144:ef7eb2e8f9f7 493 ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 #define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B) || \
<> 144:ef7eb2e8f9f7 496 ((DATA) == DCMI_EXTEND_DATA_10B) || \
<> 144:ef7eb2e8f9f7 497 ((DATA) == DCMI_EXTEND_DATA_12B) || \
<> 144:ef7eb2e8f9f7 498 ((DATA) == DCMI_EXTEND_DATA_14B))
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 #define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /**
<> 144:ef7eb2e8f9f7 505 * @}
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 509 /** @addtogroup DCMI_Private_Functions DCMI Private Functions
<> 144:ef7eb2e8f9f7 510 * @{
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @}
<> 144:ef7eb2e8f9f7 515 */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 #endif /* STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
<> 144:ef7eb2e8f9f7 518 STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
<> 144:ef7eb2e8f9f7 519 STM32F479xx */
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /**
<> 144:ef7eb2e8f9f7 522 * @}
<> 144:ef7eb2e8f9f7 523 */
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /**
<> 144:ef7eb2e8f9f7 526 * @}
<> 144:ef7eb2e8f9f7 527 */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 530 }
<> 144:ef7eb2e8f9f7 531 #endif
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 #endif /* __STM32F4xx_HAL_DCMI_H */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/