mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c@182:a56a73fd2a6f, 2018-03-20 (annotated)

Committer:
AnnaBridge
Date:
Tue Mar 20 16:56:18 2018 +0000
Revision:
182:a56a73fd2a6f
Child:
187:0387e8f68319
mbed-dev library. Release version 160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 182:a56a73fd2a6f 1 /* mbed Microcontroller Library
AnnaBridge 182:a56a73fd2a6f 2 * Copyright (c) 2006-2017 ARM Limited
AnnaBridge 182:a56a73fd2a6f 3 *
AnnaBridge 182:a56a73fd2a6f 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 182:a56a73fd2a6f 5 * you may not use this file except in compliance with the License.
AnnaBridge 182:a56a73fd2a6f 6 * You may obtain a copy of the License at
AnnaBridge 182:a56a73fd2a6f 7 *
AnnaBridge 182:a56a73fd2a6f 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 182:a56a73fd2a6f 9 *
AnnaBridge 182:a56a73fd2a6f 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 182:a56a73fd2a6f 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 182:a56a73fd2a6f 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 182:a56a73fd2a6f 13 * See the License for the specific language governing permissions and
AnnaBridge 182:a56a73fd2a6f 14 * limitations under the License.
AnnaBridge 182:a56a73fd2a6f 15 */
AnnaBridge 182:a56a73fd2a6f 16
AnnaBridge 182:a56a73fd2a6f 17 /**
AnnaBridge 182:a56a73fd2a6f 18 * This file configures the system clock as follows:
AnnaBridge 182:a56a73fd2a6f 19 *-----------------------------------------------------------------------------
AnnaBridge 182:a56a73fd2a6f 20 * System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
AnnaBridge 182:a56a73fd2a6f 21 * | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
AnnaBridge 182:a56a73fd2a6f 22 * | 3- USE_PLL_HSI (internal 16 MHz)
AnnaBridge 182:a56a73fd2a6f 23 *-----------------------------------------------------------------------------
AnnaBridge 182:a56a73fd2a6f 24 * SYSCLK(MHz) | 84
AnnaBridge 182:a56a73fd2a6f 25 * AHBCLK (MHz) | 84
AnnaBridge 182:a56a73fd2a6f 26 * APB1CLK (MHz) | 42
AnnaBridge 182:a56a73fd2a6f 27 * APB2CLK (MHz) | 84
AnnaBridge 182:a56a73fd2a6f 28 * USB capable | YES
AnnaBridge 182:a56a73fd2a6f 29 *-----------------------------------------------------------------------------
AnnaBridge 182:a56a73fd2a6f 30 **/
AnnaBridge 182:a56a73fd2a6f 31
AnnaBridge 182:a56a73fd2a6f 32 #include "stm32f4xx.h"
AnnaBridge 182:a56a73fd2a6f 33 #include "mbed_assert.h"
AnnaBridge 182:a56a73fd2a6f 34
AnnaBridge 182:a56a73fd2a6f 35 /*!< Uncomment the following line if you need to relocate your vector Table in
AnnaBridge 182:a56a73fd2a6f 36 Internal SRAM. */
AnnaBridge 182:a56a73fd2a6f 37 /* #define VECT_TAB_SRAM */
AnnaBridge 182:a56a73fd2a6f 38 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
AnnaBridge 182:a56a73fd2a6f 39 This value must be a multiple of 0x200. */
AnnaBridge 182:a56a73fd2a6f 40
AnnaBridge 182:a56a73fd2a6f 41
AnnaBridge 182:a56a73fd2a6f 42 // clock source is selected with CLOCK_SOURCE in json config
AnnaBridge 182:a56a73fd2a6f 43 #define USE_PLL_HSE_EXTC 0x8 // Use external clock (Not connected on board)
AnnaBridge 182:a56a73fd2a6f 44 #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (Y1 on board)
AnnaBridge 182:a56a73fd2a6f 45 #define USE_PLL_HSI 0x2 // Use HSI internal clock
AnnaBridge 182:a56a73fd2a6f 46
AnnaBridge 182:a56a73fd2a6f 47
AnnaBridge 182:a56a73fd2a6f 48 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 182:a56a73fd2a6f 49 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
AnnaBridge 182:a56a73fd2a6f 50 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 182:a56a73fd2a6f 51
AnnaBridge 182:a56a73fd2a6f 52 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 182:a56a73fd2a6f 53 uint8_t SetSysClock_PLL_HSI(void);
AnnaBridge 182:a56a73fd2a6f 54 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
AnnaBridge 182:a56a73fd2a6f 55
AnnaBridge 182:a56a73fd2a6f 56
AnnaBridge 182:a56a73fd2a6f 57 /**
AnnaBridge 182:a56a73fd2a6f 58 * @brief Setup the microcontroller system
AnnaBridge 182:a56a73fd2a6f 59 * Initialize the FPU setting, vector table location and External memory
AnnaBridge 182:a56a73fd2a6f 60 * configuration.
AnnaBridge 182:a56a73fd2a6f 61 * @param None
AnnaBridge 182:a56a73fd2a6f 62 * @retval None
AnnaBridge 182:a56a73fd2a6f 63 */
AnnaBridge 182:a56a73fd2a6f 64 void SystemInit(void)
AnnaBridge 182:a56a73fd2a6f 65 {
AnnaBridge 182:a56a73fd2a6f 66 /* FPU settings ------------------------------------------------------------*/
AnnaBridge 182:a56a73fd2a6f 67 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
AnnaBridge 182:a56a73fd2a6f 68 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
AnnaBridge 182:a56a73fd2a6f 69 #endif
AnnaBridge 182:a56a73fd2a6f 70 /* Reset the RCC clock configuration to the default reset state ------------*/
AnnaBridge 182:a56a73fd2a6f 71 /* Set HSION bit */
AnnaBridge 182:a56a73fd2a6f 72 RCC->CR |= (uint32_t)0x00000001;
AnnaBridge 182:a56a73fd2a6f 73
AnnaBridge 182:a56a73fd2a6f 74 /* Reset CFGR register */
AnnaBridge 182:a56a73fd2a6f 75 RCC->CFGR = 0x00000000;
AnnaBridge 182:a56a73fd2a6f 76
AnnaBridge 182:a56a73fd2a6f 77 /* Reset HSEON, CSSON and PLLON bits */
AnnaBridge 182:a56a73fd2a6f 78 RCC->CR &= (uint32_t)0xFEF6FFFF;
AnnaBridge 182:a56a73fd2a6f 79
AnnaBridge 182:a56a73fd2a6f 80 /* Reset PLLCFGR register */
AnnaBridge 182:a56a73fd2a6f 81 RCC->PLLCFGR = 0x24003010;
AnnaBridge 182:a56a73fd2a6f 82
AnnaBridge 182:a56a73fd2a6f 83 /* Reset HSEBYP bit */
AnnaBridge 182:a56a73fd2a6f 84 RCC->CR &= (uint32_t)0xFFFBFFFF;
AnnaBridge 182:a56a73fd2a6f 85
AnnaBridge 182:a56a73fd2a6f 86 /* Disable all interrupts */
AnnaBridge 182:a56a73fd2a6f 87 RCC->CIR = 0x00000000;
AnnaBridge 182:a56a73fd2a6f 88
AnnaBridge 182:a56a73fd2a6f 89 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
AnnaBridge 182:a56a73fd2a6f 90 SystemInit_ExtMemCtl();
AnnaBridge 182:a56a73fd2a6f 91 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
AnnaBridge 182:a56a73fd2a6f 92
AnnaBridge 182:a56a73fd2a6f 93 /* Configure the Vector Table location add offset address ------------------*/
AnnaBridge 182:a56a73fd2a6f 94 #ifdef VECT_TAB_SRAM
AnnaBridge 182:a56a73fd2a6f 95 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
AnnaBridge 182:a56a73fd2a6f 96 #else
AnnaBridge 182:a56a73fd2a6f 97 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
AnnaBridge 182:a56a73fd2a6f 98 #endif
AnnaBridge 182:a56a73fd2a6f 99
AnnaBridge 182:a56a73fd2a6f 100 }
AnnaBridge 182:a56a73fd2a6f 101
AnnaBridge 182:a56a73fd2a6f 102 /*
AnnaBridge 182:a56a73fd2a6f 103 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
AnnaBridge 182:a56a73fd2a6f 104 * AHB/APBx prescalers and Flash settings
AnnaBridge 182:a56a73fd2a6f 105 * @note This function should be called only once the RCC clock configuration
AnnaBridge 182:a56a73fd2a6f 106 * is reset to the default reset state (done in SystemInit() function).
AnnaBridge 182:a56a73fd2a6f 107 * @param None
AnnaBridge 182:a56a73fd2a6f 108 * @retval None
AnnaBridge 182:a56a73fd2a6f 109 */
AnnaBridge 182:a56a73fd2a6f 110
AnnaBridge 182:a56a73fd2a6f 111 void SetSysClock(void)
AnnaBridge 182:a56a73fd2a6f 112 {
AnnaBridge 182:a56a73fd2a6f 113 #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
AnnaBridge 182:a56a73fd2a6f 114 /* 1- Try to start with HSE and external clock */
AnnaBridge 182:a56a73fd2a6f 115 if (SetSysClock_PLL_HSE(1) == 0)
AnnaBridge 182:a56a73fd2a6f 116 #endif
AnnaBridge 182:a56a73fd2a6f 117 {
AnnaBridge 182:a56a73fd2a6f 118 #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
AnnaBridge 182:a56a73fd2a6f 119 /* 2- If fail try to start with HSE and external xtal */
AnnaBridge 182:a56a73fd2a6f 120 if (SetSysClock_PLL_HSE(0) == 0)
AnnaBridge 182:a56a73fd2a6f 121 #endif
AnnaBridge 182:a56a73fd2a6f 122 {
AnnaBridge 182:a56a73fd2a6f 123 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 182:a56a73fd2a6f 124 /* 3- If fail start with HSI clock */
AnnaBridge 182:a56a73fd2a6f 125 if (SetSysClock_PLL_HSI() == 0)
AnnaBridge 182:a56a73fd2a6f 126 #endif
AnnaBridge 182:a56a73fd2a6f 127 {
AnnaBridge 182:a56a73fd2a6f 128 while(1) {
AnnaBridge 182:a56a73fd2a6f 129 MBED_ASSERT(1);
AnnaBridge 182:a56a73fd2a6f 130 }
AnnaBridge 182:a56a73fd2a6f 131 }
AnnaBridge 182:a56a73fd2a6f 132 }
AnnaBridge 182:a56a73fd2a6f 133 }
AnnaBridge 182:a56a73fd2a6f 134
AnnaBridge 182:a56a73fd2a6f 135 /* Output clock on MCO2 pin(PC9) for debugging purpose */
AnnaBridge 182:a56a73fd2a6f 136 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
AnnaBridge 182:a56a73fd2a6f 137 }
AnnaBridge 182:a56a73fd2a6f 138
AnnaBridge 182:a56a73fd2a6f 139 #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
AnnaBridge 182:a56a73fd2a6f 140 /******************************************************************************/
AnnaBridge 182:a56a73fd2a6f 141 /* PLL (clocked by HSE) used as System clock source */
AnnaBridge 182:a56a73fd2a6f 142 /******************************************************************************/
AnnaBridge 182:a56a73fd2a6f 143 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
AnnaBridge 182:a56a73fd2a6f 144 {
AnnaBridge 182:a56a73fd2a6f 145 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 182:a56a73fd2a6f 146 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 182:a56a73fd2a6f 147
AnnaBridge 182:a56a73fd2a6f 148 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 182:a56a73fd2a6f 149 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 182:a56a73fd2a6f 150 regarding system frequency refer to product datasheet. */
AnnaBridge 182:a56a73fd2a6f 151 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 182:a56a73fd2a6f 152 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 182:a56a73fd2a6f 153
AnnaBridge 182:a56a73fd2a6f 154 // Enable HSE oscillator and activate PLL with HSE as source
AnnaBridge 182:a56a73fd2a6f 155 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
AnnaBridge 182:a56a73fd2a6f 156 if (bypass == 0) {
AnnaBridge 182:a56a73fd2a6f 157 RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 25 MHz xtal on OSC_IN/OSC_OUT
AnnaBridge 182:a56a73fd2a6f 158 } else {
AnnaBridge 182:a56a73fd2a6f 159 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 25 MHz clock on OSC_IN
AnnaBridge 182:a56a73fd2a6f 160 }
AnnaBridge 182:a56a73fd2a6f 161
AnnaBridge 182:a56a73fd2a6f 162 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 182:a56a73fd2a6f 163 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
AnnaBridge 182:a56a73fd2a6f 164 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
AnnaBridge 182:a56a73fd2a6f 165 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
AnnaBridge 182:a56a73fd2a6f 166 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
AnnaBridge 182:a56a73fd2a6f 167 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
AnnaBridge 182:a56a73fd2a6f 168 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 182:a56a73fd2a6f 169 return 0; // FAIL
AnnaBridge 182:a56a73fd2a6f 170 }
AnnaBridge 182:a56a73fd2a6f 171
AnnaBridge 182:a56a73fd2a6f 172 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
AnnaBridge 182:a56a73fd2a6f 173 RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
AnnaBridge 182:a56a73fd2a6f 174 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 175 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 176 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
AnnaBridge 182:a56a73fd2a6f 177 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 178 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
AnnaBridge 182:a56a73fd2a6f 179 return 0; // FAIL
AnnaBridge 182:a56a73fd2a6f 180 }
AnnaBridge 182:a56a73fd2a6f 181
AnnaBridge 182:a56a73fd2a6f 182 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 182:a56a73fd2a6f 183 /*
AnnaBridge 182:a56a73fd2a6f 184 if (bypass == 0)
AnnaBridge 182:a56a73fd2a6f 185 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
AnnaBridge 182:a56a73fd2a6f 186 else
AnnaBridge 182:a56a73fd2a6f 187 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
AnnaBridge 182:a56a73fd2a6f 188 */
AnnaBridge 182:a56a73fd2a6f 189
AnnaBridge 182:a56a73fd2a6f 190 return 1; // OK
AnnaBridge 182:a56a73fd2a6f 191 }
AnnaBridge 182:a56a73fd2a6f 192 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
AnnaBridge 182:a56a73fd2a6f 193
AnnaBridge 182:a56a73fd2a6f 194 #if ((CLOCK_SOURCE) & USE_PLL_HSI)
AnnaBridge 182:a56a73fd2a6f 195 /******************************************************************************/
AnnaBridge 182:a56a73fd2a6f 196 /* PLL (clocked by HSI) used as System clock source */
AnnaBridge 182:a56a73fd2a6f 197 /******************************************************************************/
AnnaBridge 182:a56a73fd2a6f 198 uint8_t SetSysClock_PLL_HSI(void)
AnnaBridge 182:a56a73fd2a6f 199 {
AnnaBridge 182:a56a73fd2a6f 200 RCC_OscInitTypeDef RCC_OscInitStruct;
AnnaBridge 182:a56a73fd2a6f 201 RCC_ClkInitTypeDef RCC_ClkInitStruct;
AnnaBridge 182:a56a73fd2a6f 202
AnnaBridge 182:a56a73fd2a6f 203 /* The voltage scaling allows optimizing the power consumption when the device is
AnnaBridge 182:a56a73fd2a6f 204 clocked below the maximum system frequency, to update the voltage scaling value
AnnaBridge 182:a56a73fd2a6f 205 regarding system frequency refer to product datasheet. */
AnnaBridge 182:a56a73fd2a6f 206 __HAL_RCC_PWR_CLK_ENABLE();
AnnaBridge 182:a56a73fd2a6f 207 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
AnnaBridge 182:a56a73fd2a6f 208
AnnaBridge 182:a56a73fd2a6f 209 // Enable HSI oscillator and activate PLL with HSI as source
AnnaBridge 182:a56a73fd2a6f 210 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
AnnaBridge 182:a56a73fd2a6f 211 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
AnnaBridge 182:a56a73fd2a6f 212 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
AnnaBridge 182:a56a73fd2a6f 213 RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
AnnaBridge 182:a56a73fd2a6f 214 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
AnnaBridge 182:a56a73fd2a6f 215 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
AnnaBridge 182:a56a73fd2a6f 216 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
AnnaBridge 182:a56a73fd2a6f 217 RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
AnnaBridge 182:a56a73fd2a6f 218 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
AnnaBridge 182:a56a73fd2a6f 219 RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
AnnaBridge 182:a56a73fd2a6f 220 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 182:a56a73fd2a6f 221 return 0; // FAIL
AnnaBridge 182:a56a73fd2a6f 222 }
AnnaBridge 182:a56a73fd2a6f 223
AnnaBridge 182:a56a73fd2a6f 224 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
AnnaBridge 182:a56a73fd2a6f 225 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
AnnaBridge 182:a56a73fd2a6f 226 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 227 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 228 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
AnnaBridge 182:a56a73fd2a6f 229 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
AnnaBridge 182:a56a73fd2a6f 230 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
AnnaBridge 182:a56a73fd2a6f 231 return 0; // FAIL
AnnaBridge 182:a56a73fd2a6f 232 }
AnnaBridge 182:a56a73fd2a6f 233
AnnaBridge 182:a56a73fd2a6f 234 /* Output clock on MCO1 pin(PA8) for debugging purpose */
AnnaBridge 182:a56a73fd2a6f 235 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
AnnaBridge 182:a56a73fd2a6f 236
AnnaBridge 182:a56a73fd2a6f 237 return 1; // OK
AnnaBridge 182:a56a73fd2a6f 238 }
AnnaBridge 182:a56a73fd2a6f 239 #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */