mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/hal/TARGET_NXP/TARGET_LPC11XX_11CXX/gpio_irq_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <stddef.h>
bogdanm 0:9b334a45a8ff 17 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 18 #include "gpio_irq_api.h"
bogdanm 0:9b334a45a8ff 19 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 20 #include "gpio_api.h"
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 // The chip is capable of 42 GPIO interrupts.
bogdanm 0:9b334a45a8ff 23 // PIO0_0..PIO0_11, PIO1_0..PIO1_11, PIO2_0..PIO2_11, PIO3_0..PIO3_5
bogdanm 0:9b334a45a8ff 24 #define CHANNEL_NUM 42
bogdanm 0:9b334a45a8ff 25
bogdanm 0:9b334a45a8ff 26 static uint32_t channel_ids[CHANNEL_NUM] = {0};
bogdanm 0:9b334a45a8ff 27 static gpio_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 28
bogdanm 0:9b334a45a8ff 29 static inline int numofbits(uint32_t bits)
bogdanm 0:9b334a45a8ff 30 {
bogdanm 0:9b334a45a8ff 31 // Count number of bits
bogdanm 0:9b334a45a8ff 32 bits = (bits & 0x55555555) + (bits >> 1 & 0x55555555);
bogdanm 0:9b334a45a8ff 33 bits = (bits & 0x33333333) + (bits >> 2 & 0x33333333);
bogdanm 0:9b334a45a8ff 34 bits = (bits & 0x0f0f0f0f) + (bits >> 4 & 0x0f0f0f0f);
bogdanm 0:9b334a45a8ff 35 bits = (bits & 0x00ff00ff) + (bits >> 8 & 0x00ff00ff);
bogdanm 0:9b334a45a8ff 36 return (bits & 0x0000ffff) + (bits >>16 & 0x0000ffff);
bogdanm 0:9b334a45a8ff 37 }
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 static inline void handle_interrupt_in(uint32_t port) {
bogdanm 0:9b334a45a8ff 40 // Find out whether the interrupt has been triggered by a high or low value...
bogdanm 0:9b334a45a8ff 41 // As the LPC1114 doesn't have a specific register for this, we'll just have to read
bogdanm 0:9b334a45a8ff 42 // the level of the pin as if it were just a normal input...
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 uint32_t channel;
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 // Get the number of the pin being used and the port typedef
bogdanm 0:9b334a45a8ff 47 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (port * 0x10000)));
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 // Get index of function table from Mask Interrupt Status register
bogdanm 0:9b334a45a8ff 50 channel = numofbits(port_reg->MIS - 1) + (port * 12);
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 if (port_reg->MIS & port_reg->IBE) {
bogdanm 0:9b334a45a8ff 53 // both edge, read the level of pin
bogdanm 0:9b334a45a8ff 54 if ((port_reg->DATA & port_reg->MIS) != 0)
bogdanm 0:9b334a45a8ff 55 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 0:9b334a45a8ff 56 else
bogdanm 0:9b334a45a8ff 57 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 0:9b334a45a8ff 58 }
bogdanm 0:9b334a45a8ff 59 else if (port_reg->MIS & port_reg->IEV) {
bogdanm 0:9b334a45a8ff 60 irq_handler(channel_ids[channel], IRQ_RISE);
bogdanm 0:9b334a45a8ff 61 }
bogdanm 0:9b334a45a8ff 62 else {
bogdanm 0:9b334a45a8ff 63 irq_handler(channel_ids[channel], IRQ_FALL);
bogdanm 0:9b334a45a8ff 64 }
bogdanm 0:9b334a45a8ff 65
bogdanm 0:9b334a45a8ff 66 // Clear the interrupt...
bogdanm 0:9b334a45a8ff 67 port_reg->IC = port_reg->MIS;
bogdanm 0:9b334a45a8ff 68 }
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 void gpio_irq0(void) {handle_interrupt_in(0);}
bogdanm 0:9b334a45a8ff 71 void gpio_irq1(void) {handle_interrupt_in(1);}
bogdanm 0:9b334a45a8ff 72 void gpio_irq2(void) {handle_interrupt_in(2);}
bogdanm 0:9b334a45a8ff 73 void gpio_irq3(void) {handle_interrupt_in(3);}
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 76 int channel;
bogdanm 0:9b334a45a8ff 77 uint32_t port_num;
bogdanm 0:9b334a45a8ff 78
bogdanm 0:9b334a45a8ff 79 if (pin == NC) return -1;
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 // Firstly, we'll put some data in *obj so we can keep track of stuff.
bogdanm 0:9b334a45a8ff 82 obj->pin = pin;
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 // Set the handler to be the pointer at the top...
bogdanm 0:9b334a45a8ff 85 irq_handler = handler;
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 // Which port are we using?
bogdanm 0:9b334a45a8ff 88 port_num = ((pin & 0xF000) >> PORT_SHIFT);
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 switch (port_num) {
bogdanm 0:9b334a45a8ff 91 case 0:
bogdanm 0:9b334a45a8ff 92 NVIC_SetVector(EINT0_IRQn, (uint32_t)gpio_irq0);
bogdanm 0:9b334a45a8ff 93 NVIC_EnableIRQ(EINT0_IRQn);
bogdanm 0:9b334a45a8ff 94 break;
bogdanm 0:9b334a45a8ff 95 case 1:
bogdanm 0:9b334a45a8ff 96 NVIC_SetVector(EINT1_IRQn, (uint32_t)gpio_irq1);
bogdanm 0:9b334a45a8ff 97 NVIC_EnableIRQ(EINT1_IRQn);
bogdanm 0:9b334a45a8ff 98 break;
bogdanm 0:9b334a45a8ff 99 case 2:
bogdanm 0:9b334a45a8ff 100 NVIC_SetVector(EINT2_IRQn, (uint32_t)gpio_irq2);
bogdanm 0:9b334a45a8ff 101 NVIC_EnableIRQ(EINT2_IRQn);
bogdanm 0:9b334a45a8ff 102 break;
bogdanm 0:9b334a45a8ff 103 case 3:
bogdanm 0:9b334a45a8ff 104 NVIC_SetVector(EINT3_IRQn, (uint32_t)gpio_irq3);
bogdanm 0:9b334a45a8ff 105 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 106 break;
bogdanm 0:9b334a45a8ff 107 default:
bogdanm 0:9b334a45a8ff 108 return -1;
bogdanm 0:9b334a45a8ff 109 }
bogdanm 0:9b334a45a8ff 110
bogdanm 0:9b334a45a8ff 111 // Generate index of function pointer table
bogdanm 0:9b334a45a8ff 112 // PIO0_0 - PIO0_11 : 0..11
bogdanm 0:9b334a45a8ff 113 // PIO1_0 - PIO1_11 : 12..23
bogdanm 0:9b334a45a8ff 114 // PIO2_0 - PIO2_11 : 24..35
bogdanm 0:9b334a45a8ff 115 // PIO3_0 - PIO3_5 : 36..41
bogdanm 0:9b334a45a8ff 116 channel = (port_num * 12) + ((pin & 0x0F00) >> PIN_SHIFT);
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 channel_ids[channel] = id;
bogdanm 0:9b334a45a8ff 119 obj->ch = channel;
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 return 0;
bogdanm 0:9b334a45a8ff 122 }
bogdanm 0:9b334a45a8ff 123
bogdanm 0:9b334a45a8ff 124 void gpio_irq_free(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 125 channel_ids[obj->ch] = 0;
bogdanm 0:9b334a45a8ff 126 }
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
bogdanm 0:9b334a45a8ff 129 // Firstly, check if there is an existing event stored...
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 LPC_GPIO_TypeDef *port_reg = ((LPC_GPIO_TypeDef *) (LPC_GPIO0_BASE + (((obj->pin & 0xF000) >> PORT_SHIFT) * 0x10000)));
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 // Need to get the pin number of the pin, not the value of the enum
bogdanm 0:9b334a45a8ff 134 uint32_t pin_num = (1 << ((obj->pin & 0x0f00) >> PIN_SHIFT));
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 // Clear
bogdanm 0:9b334a45a8ff 137 port_reg->IC |= pin_num;
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 // Make it edge sensitive.
bogdanm 0:9b334a45a8ff 140 port_reg->IS &= ~pin_num;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 if ( (port_reg->IE & pin_num) != 0) {
bogdanm 0:9b334a45a8ff 143 // We have an event.
bogdanm 0:9b334a45a8ff 144 // Enable both edge interrupts.
bogdanm 0:9b334a45a8ff 145
bogdanm 0:9b334a45a8ff 146 if (enable) {
bogdanm 0:9b334a45a8ff 147 port_reg->IBE |= pin_num;
bogdanm 0:9b334a45a8ff 148 port_reg->IE |= pin_num;
bogdanm 0:9b334a45a8ff 149 }
bogdanm 0:9b334a45a8ff 150 else {
bogdanm 0:9b334a45a8ff 151 // These all need to be opposite, to reenable the other one.
bogdanm 0:9b334a45a8ff 152 port_reg->IBE &= ~pin_num;
bogdanm 0:9b334a45a8ff 153
bogdanm 0:9b334a45a8ff 154 if (event == IRQ_RISE)
bogdanm 0:9b334a45a8ff 155 port_reg->IEV &= ~pin_num;
bogdanm 0:9b334a45a8ff 156 else
bogdanm 0:9b334a45a8ff 157 port_reg->IEV |= pin_num;
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 port_reg->IE |= pin_num;
bogdanm 0:9b334a45a8ff 160 }
bogdanm 0:9b334a45a8ff 161 }
bogdanm 0:9b334a45a8ff 162 else {
bogdanm 0:9b334a45a8ff 163 // One edge
bogdanm 0:9b334a45a8ff 164 port_reg->IBE &= ~pin_num;
bogdanm 0:9b334a45a8ff 165 // Rising/falling?
bogdanm 0:9b334a45a8ff 166 if (event == IRQ_RISE)
bogdanm 0:9b334a45a8ff 167 port_reg->IEV |= pin_num;
bogdanm 0:9b334a45a8ff 168 else
bogdanm 0:9b334a45a8ff 169 port_reg->IEV &= ~pin_num;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 if (enable) {
bogdanm 0:9b334a45a8ff 172 port_reg->IE |= pin_num;
bogdanm 0:9b334a45a8ff 173 }
bogdanm 0:9b334a45a8ff 174 }
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 }
bogdanm 0:9b334a45a8ff 177
bogdanm 0:9b334a45a8ff 178 void gpio_irq_enable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 179 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
bogdanm 0:9b334a45a8ff 180 switch (port_num) {
bogdanm 0:9b334a45a8ff 181 case 0:
bogdanm 0:9b334a45a8ff 182 NVIC_EnableIRQ(EINT0_IRQn);
bogdanm 0:9b334a45a8ff 183 break;
bogdanm 0:9b334a45a8ff 184 case 1:
bogdanm 0:9b334a45a8ff 185 NVIC_EnableIRQ(EINT1_IRQn);
bogdanm 0:9b334a45a8ff 186 break;
bogdanm 0:9b334a45a8ff 187 case 2:
bogdanm 0:9b334a45a8ff 188 NVIC_EnableIRQ(EINT2_IRQn);
bogdanm 0:9b334a45a8ff 189 break;
bogdanm 0:9b334a45a8ff 190 case 3:
bogdanm 0:9b334a45a8ff 191 NVIC_EnableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 192 break;
bogdanm 0:9b334a45a8ff 193 default:
bogdanm 0:9b334a45a8ff 194 break;
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196 }
bogdanm 0:9b334a45a8ff 197
bogdanm 0:9b334a45a8ff 198 void gpio_irq_disable(gpio_irq_t *obj) {
bogdanm 0:9b334a45a8ff 199 uint32_t port_num = ((obj->pin & 0xF000) >> PORT_SHIFT);
bogdanm 0:9b334a45a8ff 200 switch (port_num) {
bogdanm 0:9b334a45a8ff 201 case 0:
bogdanm 0:9b334a45a8ff 202 NVIC_DisableIRQ(EINT0_IRQn);
bogdanm 0:9b334a45a8ff 203 break;
bogdanm 0:9b334a45a8ff 204 case 1:
bogdanm 0:9b334a45a8ff 205 NVIC_DisableIRQ(EINT1_IRQn);
bogdanm 0:9b334a45a8ff 206 break;
bogdanm 0:9b334a45a8ff 207 case 2:
bogdanm 0:9b334a45a8ff 208 NVIC_DisableIRQ(EINT2_IRQn);
bogdanm 0:9b334a45a8ff 209 break;
bogdanm 0:9b334a45a8ff 210 case 3:
bogdanm 0:9b334a45a8ff 211 NVIC_DisableIRQ(EINT3_IRQn);
bogdanm 0:9b334a45a8ff 212 break;
bogdanm 0:9b334a45a8ff 213 default:
bogdanm 0:9b334a45a8ff 214 break;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216 }