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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:: bogdanm
Date:: Thu Oct 01 15:25:22 2015 +0300
Revision:: 0:9b334a45a8ff
Child:: 144:ef7eb2e8f9f7

Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	0:9b334a45a8ff	1	/**
bogdanm	0:9b334a45a8ff	2	******************************************************************************
bogdanm	0:9b334a45a8ff	3	* @file stm32f0xx_hal_rcc_ex.h
bogdanm	0:9b334a45a8ff	4	* @author MCD Application Team
bogdanm	0:9b334a45a8ff	5	* @version V1.3.0
bogdanm	0:9b334a45a8ff	6	* @date 26-June-2015
bogdanm	0:9b334a45a8ff	7	* @brief Header file of RCC HAL Extension module.
bogdanm	0:9b334a45a8ff	8	******************************************************************************
bogdanm	0:9b334a45a8ff	9	* @attention
bogdanm	0:9b334a45a8ff	10	*
bogdanm	0:9b334a45a8ff	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	0:9b334a45a8ff	12	*
bogdanm	0:9b334a45a8ff	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	0:9b334a45a8ff	14	* are permitted provided that the following conditions are met:
bogdanm	0:9b334a45a8ff	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	0:9b334a45a8ff	16	* this list of conditions and the following disclaimer.
bogdanm	0:9b334a45a8ff	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	0:9b334a45a8ff	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	0:9b334a45a8ff	19	* and/or other materials provided with the distribution.
bogdanm	0:9b334a45a8ff	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	0:9b334a45a8ff	21	* may be used to endorse or promote products derived from this software
bogdanm	0:9b334a45a8ff	22	* without specific prior written permission.
bogdanm	0:9b334a45a8ff	23	*
bogdanm	0:9b334a45a8ff	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	0:9b334a45a8ff	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	0:9b334a45a8ff	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	0:9b334a45a8ff	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	0:9b334a45a8ff	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	0:9b334a45a8ff	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	0:9b334a45a8ff	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	0:9b334a45a8ff	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	0:9b334a45a8ff	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	0:9b334a45a8ff	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	0:9b334a45a8ff	34	*
bogdanm	0:9b334a45a8ff	35	******************************************************************************
bogdanm	0:9b334a45a8ff	36	*/
bogdanm	0:9b334a45a8ff	37
bogdanm	0:9b334a45a8ff	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	0:9b334a45a8ff	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	40	#define __HAL_RCC_STM32F0xx_HAL_RCC_EX_H
bogdanm	0:9b334a45a8ff	41
bogdanm	0:9b334a45a8ff	42	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	43	extern "C" {
bogdanm	0:9b334a45a8ff	44	#endif
bogdanm	0:9b334a45a8ff	45
bogdanm	0:9b334a45a8ff	46	/* Includes ------------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	47	#include "stm32f0xx_hal_def.h"
bogdanm	0:9b334a45a8ff	48
bogdanm	0:9b334a45a8ff	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	0:9b334a45a8ff	50	* @{
bogdanm	0:9b334a45a8ff	51	*/
bogdanm	0:9b334a45a8ff	52
bogdanm	0:9b334a45a8ff	53	/** @addtogroup RCC
bogdanm	0:9b334a45a8ff	54	* @{
bogdanm	0:9b334a45a8ff	55	*/
bogdanm	0:9b334a45a8ff	56
bogdanm	0:9b334a45a8ff	57	/** @addtogroup RCC_Private_Macros
bogdanm	0:9b334a45a8ff	58	* @{
bogdanm	0:9b334a45a8ff	59	*/
bogdanm	0:9b334a45a8ff	60	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	61	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	62	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	63	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	64	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	65	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	66	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	67	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	68	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
bogdanm	0:9b334a45a8ff	69	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
bogdanm	0:9b334a45a8ff	70	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	71	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	72	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
bogdanm	0:9b334a45a8ff	73	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
bogdanm	0:9b334a45a8ff	74
bogdanm	0:9b334a45a8ff	75	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	0:9b334a45a8ff	76	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	0:9b334a45a8ff	77	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
bogdanm	0:9b334a45a8ff	78	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
bogdanm	0:9b334a45a8ff	79	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	80	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
bogdanm	0:9b334a45a8ff	81	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	82	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
bogdanm	0:9b334a45a8ff	83	#else
bogdanm	0:9b334a45a8ff	84	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	85	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	86	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	87	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	88	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	89	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14))
bogdanm	0:9b334a45a8ff	90	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	91	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	92	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	93
bogdanm	0:9b334a45a8ff	94	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	0:9b334a45a8ff	95	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	0:9b334a45a8ff	96	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
bogdanm	0:9b334a45a8ff	97	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	98	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	0:9b334a45a8ff	99
bogdanm	0:9b334a45a8ff	100	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	101	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	102	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	103
bogdanm	0:9b334a45a8ff	104	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	105	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	106
bogdanm	0:9b334a45a8ff	107	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	108	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	109	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	110	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	111	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	112	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	113	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	0:9b334a45a8ff	114	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	115	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	0:9b334a45a8ff	116
bogdanm	0:9b334a45a8ff	117	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	118
bogdanm	0:9b334a45a8ff	119	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	120
bogdanm	0:9b334a45a8ff	121	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	122	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	123	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	124	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	125	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	126	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	127	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	128	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	0:9b334a45a8ff	129
bogdanm	0:9b334a45a8ff	130	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	131
bogdanm	0:9b334a45a8ff	132	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	133	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	134	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	135
bogdanm	0:9b334a45a8ff	136	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	0:9b334a45a8ff	137	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	0:9b334a45a8ff	138	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	139	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	140	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	141	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	0:9b334a45a8ff	142	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	0:9b334a45a8ff	143	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	144	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
bogdanm	0:9b334a45a8ff	145	((SOURCE) == RCC_MCOSOURCE_HSI48))
bogdanm	0:9b334a45a8ff	146
bogdanm	0:9b334a45a8ff	147	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	148	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	149	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	150
bogdanm	0:9b334a45a8ff	151	/**
bogdanm	0:9b334a45a8ff	152	* @}
bogdanm	0:9b334a45a8ff	153	*/
bogdanm	0:9b334a45a8ff	154
bogdanm	0:9b334a45a8ff	155	/** @addtogroup RCC_Exported_Constants
bogdanm	0:9b334a45a8ff	156	* @{
bogdanm	0:9b334a45a8ff	157	*/
bogdanm	0:9b334a45a8ff	158	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	159	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	160	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	161
bogdanm	0:9b334a45a8ff	162	/** @addtogroup RCC_PLL_Clock_Source
bogdanm	0:9b334a45a8ff	163	* @{
bogdanm	0:9b334a45a8ff	164	*/
bogdanm	0:9b334a45a8ff	165	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm	0:9b334a45a8ff	166	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
bogdanm	0:9b334a45a8ff	167
bogdanm	0:9b334a45a8ff	168	/**
bogdanm	0:9b334a45a8ff	169	* @}
bogdanm	0:9b334a45a8ff	170	*/
bogdanm	0:9b334a45a8ff	171
bogdanm	0:9b334a45a8ff	172	/** @addtogroup RCC_Oscillator_Type
bogdanm	0:9b334a45a8ff	173	* @{
bogdanm	0:9b334a45a8ff	174	*/
bogdanm	0:9b334a45a8ff	175	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	176	/**
bogdanm	0:9b334a45a8ff	177	* @}
bogdanm	0:9b334a45a8ff	178	*/
bogdanm	0:9b334a45a8ff	179
bogdanm	0:9b334a45a8ff	180	/** @addtogroup RCC_Interrupt
bogdanm	0:9b334a45a8ff	181	* @{
bogdanm	0:9b334a45a8ff	182	*/
bogdanm	0:9b334a45a8ff	183	#define RCC_IT_HSI48 RCC_CIR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
bogdanm	0:9b334a45a8ff	184	/**
bogdanm	0:9b334a45a8ff	185	* @}
bogdanm	0:9b334a45a8ff	186	*/
bogdanm	0:9b334a45a8ff	187
bogdanm	0:9b334a45a8ff	188	/** @addtogroup RCC_Flag
bogdanm	0:9b334a45a8ff	189	* @{
bogdanm	0:9b334a45a8ff	190	*/
bogdanm	0:9b334a45a8ff	191	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
bogdanm	0:9b334a45a8ff	192	/**
bogdanm	0:9b334a45a8ff	193	* @}
bogdanm	0:9b334a45a8ff	194	*/
bogdanm	0:9b334a45a8ff	195
bogdanm	0:9b334a45a8ff	196	/** @addtogroup RCC_System_Clock_Source
bogdanm	0:9b334a45a8ff	197	* @{
bogdanm	0:9b334a45a8ff	198	*/
bogdanm	0:9b334a45a8ff	199	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
bogdanm	0:9b334a45a8ff	200	/**
bogdanm	0:9b334a45a8ff	201	* @}
bogdanm	0:9b334a45a8ff	202	*/
bogdanm	0:9b334a45a8ff	203
bogdanm	0:9b334a45a8ff	204	/** @addtogroup RCC_System_Clock_Source_Status
bogdanm	0:9b334a45a8ff	205	* @{
bogdanm	0:9b334a45a8ff	206	*/
bogdanm	0:9b334a45a8ff	207	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
bogdanm	0:9b334a45a8ff	208	/**
bogdanm	0:9b334a45a8ff	209	* @}
bogdanm	0:9b334a45a8ff	210	*/
bogdanm	0:9b334a45a8ff	211
bogdanm	0:9b334a45a8ff	212	#else
bogdanm	0:9b334a45a8ff	213	/** @addtogroup RCC_PLL_Clock_Source
bogdanm	0:9b334a45a8ff	214	* @{
bogdanm	0:9b334a45a8ff	215	*/
bogdanm	0:9b334a45a8ff	216
bogdanm	0:9b334a45a8ff	217	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	218	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm	0:9b334a45a8ff	219	#else
bogdanm	0:9b334a45a8ff	220	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
bogdanm	0:9b334a45a8ff	221	#endif
bogdanm	0:9b334a45a8ff	222
bogdanm	0:9b334a45a8ff	223	/**
bogdanm	0:9b334a45a8ff	224	* @}
bogdanm	0:9b334a45a8ff	225	*/
bogdanm	0:9b334a45a8ff	226
bogdanm	0:9b334a45a8ff	227	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	228	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	229	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	230
bogdanm	0:9b334a45a8ff	231	/** @addtogroup RCC_MCO_Clock_Source
bogdanm	0:9b334a45a8ff	232	* @{
bogdanm	0:9b334a45a8ff	233	*/
bogdanm	0:9b334a45a8ff	234
bogdanm	0:9b334a45a8ff	235	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	236	\|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	237
bogdanm	0:9b334a45a8ff	238	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	0:9b334a45a8ff	239
bogdanm	0:9b334a45a8ff	240	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	241
bogdanm	0:9b334a45a8ff	242	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	243	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	244	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	245
bogdanm	0:9b334a45a8ff	246	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm	0:9b334a45a8ff	247	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	0:9b334a45a8ff	248
bogdanm	0:9b334a45a8ff	249	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	250	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	251	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	252	/**
bogdanm	0:9b334a45a8ff	253	* @}
bogdanm	0:9b334a45a8ff	254	*/
bogdanm	0:9b334a45a8ff	255
bogdanm	0:9b334a45a8ff	256	/**
bogdanm	0:9b334a45a8ff	257	* @}
bogdanm	0:9b334a45a8ff	258	*/
bogdanm	0:9b334a45a8ff	259
bogdanm	0:9b334a45a8ff	260	/**
bogdanm	0:9b334a45a8ff	261	* @}
bogdanm	0:9b334a45a8ff	262	*/
bogdanm	0:9b334a45a8ff	263
bogdanm	0:9b334a45a8ff	264	/** @addtogroup RCCEx
bogdanm	0:9b334a45a8ff	265	* @{
bogdanm	0:9b334a45a8ff	266	*/
bogdanm	0:9b334a45a8ff	267
bogdanm	0:9b334a45a8ff	268	/* Private macro -------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	269	/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm	0:9b334a45a8ff	270	* @{
bogdanm	0:9b334a45a8ff	271	*/
bogdanm	0:9b334a45a8ff	272	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	273	\|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	274
bogdanm	0:9b334a45a8ff	275	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	0:9b334a45a8ff	276	RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	277	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
bogdanm	0:9b334a45a8ff	278	STM32F030xC */
bogdanm	0:9b334a45a8ff	279
bogdanm	0:9b334a45a8ff	280	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	281
bogdanm	0:9b334a45a8ff	282	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	0:9b334a45a8ff	283	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
bogdanm	0:9b334a45a8ff	284	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	285
bogdanm	0:9b334a45a8ff	286	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	0:9b334a45a8ff	287
bogdanm	0:9b334a45a8ff	288	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	0:9b334a45a8ff	289	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
bogdanm	0:9b334a45a8ff	290	RCC_PERIPHCLK_USB))
bogdanm	0:9b334a45a8ff	291	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	0:9b334a45a8ff	292
bogdanm	0:9b334a45a8ff	293	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	294
bogdanm	0:9b334a45a8ff	295	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	0:9b334a45a8ff	296	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	297	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	298
bogdanm	0:9b334a45a8ff	299	#if defined(STM32F071xB)
bogdanm	0:9b334a45a8ff	300
bogdanm	0:9b334a45a8ff	301	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	0:9b334a45a8ff	302	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	0:9b334a45a8ff	303	RCC_PERIPHCLK_RTC))
bogdanm	0:9b334a45a8ff	304	#endif /* STM32F071xB */
bogdanm	0:9b334a45a8ff	305
bogdanm	0:9b334a45a8ff	306	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	0:9b334a45a8ff	307
bogdanm	0:9b334a45a8ff	308	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	0:9b334a45a8ff	309	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	0:9b334a45a8ff	310	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
bogdanm	0:9b334a45a8ff	311	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	0:9b334a45a8ff	312
bogdanm	0:9b334a45a8ff	313	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	314
bogdanm	0:9b334a45a8ff	315	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	0:9b334a45a8ff	316	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	0:9b334a45a8ff	317	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
bogdanm	0:9b334a45a8ff	318	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	319
bogdanm	0:9b334a45a8ff	320	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	0:9b334a45a8ff	321
bogdanm	0:9b334a45a8ff	322	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
bogdanm	0:9b334a45a8ff	323	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	324
bogdanm	0:9b334a45a8ff	325	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	0:9b334a45a8ff	326
bogdanm	0:9b334a45a8ff	327	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	328
bogdanm	0:9b334a45a8ff	329	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	0:9b334a45a8ff	330
bogdanm	0:9b334a45a8ff	331	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	332
bogdanm	0:9b334a45a8ff	333	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	334	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	335
bogdanm	0:9b334a45a8ff	336	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	337	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	338	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	339	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	340
bogdanm	0:9b334a45a8ff	341	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	342	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	343
bogdanm	0:9b334a45a8ff	344	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	345
bogdanm	0:9b334a45a8ff	346	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
bogdanm	0:9b334a45a8ff	347	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
bogdanm	0:9b334a45a8ff	348	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	349	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm	0:9b334a45a8ff	350	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	351
bogdanm	0:9b334a45a8ff	352
bogdanm	0:9b334a45a8ff	353	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	354	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	355	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	356	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	357
bogdanm	0:9b334a45a8ff	358	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
bogdanm	0:9b334a45a8ff	359	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	0:9b334a45a8ff	360	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	361	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	362	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	363	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	364
bogdanm	0:9b334a45a8ff	365	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	366
bogdanm	0:9b334a45a8ff	367	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1))
bogdanm	0:9b334a45a8ff	368
bogdanm	0:9b334a45a8ff	369	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	370
bogdanm	0:9b334a45a8ff	371	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	372	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	373	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	374	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	375
bogdanm	0:9b334a45a8ff	376	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	377	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	378	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
bogdanm	0:9b334a45a8ff	379	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
bogdanm	0:9b334a45a8ff	380
bogdanm	0:9b334a45a8ff	381	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	382	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	383	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	384
bogdanm	0:9b334a45a8ff	385	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	386	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	387	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	388
bogdanm	0:9b334a45a8ff	389	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
bogdanm	0:9b334a45a8ff	390	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
bogdanm	0:9b334a45a8ff	391	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	0:9b334a45a8ff	392	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
bogdanm	0:9b334a45a8ff	393	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
bogdanm	0:9b334a45a8ff	394	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
bogdanm	0:9b334a45a8ff	395	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
bogdanm	0:9b334a45a8ff	396	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
bogdanm	0:9b334a45a8ff	397	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	0:9b334a45a8ff	398	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
bogdanm	0:9b334a45a8ff	399	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
bogdanm	0:9b334a45a8ff	400	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
bogdanm	0:9b334a45a8ff	401	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
bogdanm	0:9b334a45a8ff	402	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	0:9b334a45a8ff	403	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	404	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	405	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	406	/**
bogdanm	0:9b334a45a8ff	407	* @}
bogdanm	0:9b334a45a8ff	408	*/
bogdanm	0:9b334a45a8ff	409
bogdanm	0:9b334a45a8ff	410	/* Exported types ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	411
bogdanm	0:9b334a45a8ff	412	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	0:9b334a45a8ff	413	* @{
bogdanm	0:9b334a45a8ff	414	*/
bogdanm	0:9b334a45a8ff	415
bogdanm	0:9b334a45a8ff	416	/**
bogdanm	0:9b334a45a8ff	417	* @brief RCC extended clocks structure definition
bogdanm	0:9b334a45a8ff	418	*/
bogdanm	0:9b334a45a8ff	419	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	420	\|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	421	typedef struct
bogdanm	0:9b334a45a8ff	422	{
bogdanm	0:9b334a45a8ff	423	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	424	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	425
bogdanm	0:9b334a45a8ff	426	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	427	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	428
bogdanm	0:9b334a45a8ff	429	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	430	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	431
bogdanm	0:9b334a45a8ff	432	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	433	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	434
bogdanm	0:9b334a45a8ff	435	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	436	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
bogdanm	0:9b334a45a8ff	437	STM32F030xC */
bogdanm	0:9b334a45a8ff	438
bogdanm	0:9b334a45a8ff	439	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	440	typedef struct
bogdanm	0:9b334a45a8ff	441	{
bogdanm	0:9b334a45a8ff	442	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	443	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	444
bogdanm	0:9b334a45a8ff	445	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	446	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	447
bogdanm	0:9b334a45a8ff	448	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	449	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	450
bogdanm	0:9b334a45a8ff	451	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	452	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	453
bogdanm	0:9b334a45a8ff	454	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	0:9b334a45a8ff	455	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	0:9b334a45a8ff	456
bogdanm	0:9b334a45a8ff	457	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	458	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	459
bogdanm	0:9b334a45a8ff	460	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	0:9b334a45a8ff	461	typedef struct
bogdanm	0:9b334a45a8ff	462	{
bogdanm	0:9b334a45a8ff	463	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	464	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	465
bogdanm	0:9b334a45a8ff	466	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	467	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	468
bogdanm	0:9b334a45a8ff	469	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	470	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	471
bogdanm	0:9b334a45a8ff	472	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	473	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	474
bogdanm	0:9b334a45a8ff	475	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	0:9b334a45a8ff	476	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	477
bogdanm	0:9b334a45a8ff	478	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	0:9b334a45a8ff	479	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	0:9b334a45a8ff	480
bogdanm	0:9b334a45a8ff	481	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	482	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	0:9b334a45a8ff	483
bogdanm	0:9b334a45a8ff	484	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	485	typedef struct
bogdanm	0:9b334a45a8ff	486	{
bogdanm	0:9b334a45a8ff	487	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	488	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	489
bogdanm	0:9b334a45a8ff	490	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	491	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	492
bogdanm	0:9b334a45a8ff	493	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	494	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	495
bogdanm	0:9b334a45a8ff	496	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	497	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	498
bogdanm	0:9b334a45a8ff	499	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	0:9b334a45a8ff	500	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	501
bogdanm	0:9b334a45a8ff	502	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	503	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	504
bogdanm	0:9b334a45a8ff	505	#if defined(STM32F071xB)
bogdanm	0:9b334a45a8ff	506	typedef struct
bogdanm	0:9b334a45a8ff	507	{
bogdanm	0:9b334a45a8ff	508	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	509	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	510
bogdanm	0:9b334a45a8ff	511	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	512	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	513
bogdanm	0:9b334a45a8ff	514	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	515	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	516
bogdanm	0:9b334a45a8ff	517	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	518	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	519
bogdanm	0:9b334a45a8ff	520	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	521	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	522
bogdanm	0:9b334a45a8ff	523	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	0:9b334a45a8ff	524	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	525
bogdanm	0:9b334a45a8ff	526	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	527	#endif /* STM32F071xB */
bogdanm	0:9b334a45a8ff	528
bogdanm	0:9b334a45a8ff	529	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	0:9b334a45a8ff	530	typedef struct
bogdanm	0:9b334a45a8ff	531	{
bogdanm	0:9b334a45a8ff	532	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	533	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	534
bogdanm	0:9b334a45a8ff	535	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	536	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	537
bogdanm	0:9b334a45a8ff	538	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	539	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	540
bogdanm	0:9b334a45a8ff	541	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	542	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	543
bogdanm	0:9b334a45a8ff	544	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	545	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	546
bogdanm	0:9b334a45a8ff	547	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	0:9b334a45a8ff	548	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	549
bogdanm	0:9b334a45a8ff	550	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	0:9b334a45a8ff	551	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	0:9b334a45a8ff	552
bogdanm	0:9b334a45a8ff	553	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	554	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	0:9b334a45a8ff	555
bogdanm	0:9b334a45a8ff	556
bogdanm	0:9b334a45a8ff	557	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	558	typedef struct
bogdanm	0:9b334a45a8ff	559	{
bogdanm	0:9b334a45a8ff	560	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	0:9b334a45a8ff	561	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	0:9b334a45a8ff	562
bogdanm	0:9b334a45a8ff	563	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	0:9b334a45a8ff	564	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	0:9b334a45a8ff	565
bogdanm	0:9b334a45a8ff	566	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	0:9b334a45a8ff	567	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	0:9b334a45a8ff	568
bogdanm	0:9b334a45a8ff	569	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	0:9b334a45a8ff	570	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	0:9b334a45a8ff	571
bogdanm	0:9b334a45a8ff	572	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	0:9b334a45a8ff	573	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm	0:9b334a45a8ff	574
bogdanm	0:9b334a45a8ff	575	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	0:9b334a45a8ff	576	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	0:9b334a45a8ff	577
bogdanm	0:9b334a45a8ff	578	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	0:9b334a45a8ff	579	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	0:9b334a45a8ff	580
bogdanm	0:9b334a45a8ff	581	}RCC_PeriphCLKInitTypeDef;
bogdanm	0:9b334a45a8ff	582	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	583
bogdanm	0:9b334a45a8ff	584	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	585	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	586	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	587
bogdanm	0:9b334a45a8ff	588	/**
bogdanm	0:9b334a45a8ff	589	* @brief RCC_CRS Init structure definition
bogdanm	0:9b334a45a8ff	590	*/
bogdanm	0:9b334a45a8ff	591	typedef struct
bogdanm	0:9b334a45a8ff	592	{
bogdanm	0:9b334a45a8ff	593	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	0:9b334a45a8ff	594	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	0:9b334a45a8ff	595
bogdanm	0:9b334a45a8ff	596	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	0:9b334a45a8ff	597	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	0:9b334a45a8ff	598
bogdanm	0:9b334a45a8ff	599	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	0:9b334a45a8ff	600	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	0:9b334a45a8ff	601
bogdanm	0:9b334a45a8ff	602	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	0:9b334a45a8ff	603	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	0:9b334a45a8ff	604	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	0:9b334a45a8ff	605
bogdanm	0:9b334a45a8ff	606	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	0:9b334a45a8ff	607	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	0:9b334a45a8ff	608
bogdanm	0:9b334a45a8ff	609	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	0:9b334a45a8ff	610	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	0:9b334a45a8ff	611
bogdanm	0:9b334a45a8ff	612	}RCC_CRSInitTypeDef;
bogdanm	0:9b334a45a8ff	613
bogdanm	0:9b334a45a8ff	614	/**
bogdanm	0:9b334a45a8ff	615	* @brief RCC_CRS Synchronization structure definition
bogdanm	0:9b334a45a8ff	616	*/
bogdanm	0:9b334a45a8ff	617	typedef struct
bogdanm	0:9b334a45a8ff	618	{
bogdanm	0:9b334a45a8ff	619	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	0:9b334a45a8ff	620	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	0:9b334a45a8ff	621
bogdanm	0:9b334a45a8ff	622	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	0:9b334a45a8ff	623	This parameter must be a number between 0 and 0x3F */
bogdanm	0:9b334a45a8ff	624
bogdanm	0:9b334a45a8ff	625	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	0:9b334a45a8ff	626	value latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	627	This parameter must be a number between 0 and 0xFFFF */
bogdanm	0:9b334a45a8ff	628
bogdanm	0:9b334a45a8ff	629	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	0:9b334a45a8ff	630	frequency error counter latched in the time of the last SYNC event.
bogdanm	0:9b334a45a8ff	631	It shows whether the actual frequency is below or above the target.
bogdanm	0:9b334a45a8ff	632	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	0:9b334a45a8ff	633
bogdanm	0:9b334a45a8ff	634	}RCC_CRSSynchroInfoTypeDef;
bogdanm	0:9b334a45a8ff	635
bogdanm	0:9b334a45a8ff	636	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	0:9b334a45a8ff	637	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	638	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	639
bogdanm	0:9b334a45a8ff	640	/**
bogdanm	0:9b334a45a8ff	641	* @}
bogdanm	0:9b334a45a8ff	642	*/
bogdanm	0:9b334a45a8ff	643
bogdanm	0:9b334a45a8ff	644	/* Exported constants --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	645
bogdanm	0:9b334a45a8ff	646	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	0:9b334a45a8ff	647	* @{
bogdanm	0:9b334a45a8ff	648	*/
bogdanm	0:9b334a45a8ff	649
bogdanm	0:9b334a45a8ff	650	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	651	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	652	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	653	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm	0:9b334a45a8ff	654	* @{
bogdanm	0:9b334a45a8ff	655	*/
bogdanm	0:9b334a45a8ff	656	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	657	#define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm	0:9b334a45a8ff	658
bogdanm	0:9b334a45a8ff	659	/**
bogdanm	0:9b334a45a8ff	660	* @}
bogdanm	0:9b334a45a8ff	661	*/
bogdanm	0:9b334a45a8ff	662
bogdanm	0:9b334a45a8ff	663	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
bogdanm	0:9b334a45a8ff	664	* @{
bogdanm	0:9b334a45a8ff	665	*/
bogdanm	0:9b334a45a8ff	666	#define RCC_CRS_NONE ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	667	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	668	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	669	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
bogdanm	0:9b334a45a8ff	670	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
bogdanm	0:9b334a45a8ff	671	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
bogdanm	0:9b334a45a8ff	672	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	673
bogdanm	0:9b334a45a8ff	674	/**
bogdanm	0:9b334a45a8ff	675	* @}
bogdanm	0:9b334a45a8ff	676	*/
bogdanm	0:9b334a45a8ff	677
bogdanm	0:9b334a45a8ff	678	#else
bogdanm	0:9b334a45a8ff	679
bogdanm	0:9b334a45a8ff	680	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm	0:9b334a45a8ff	681	* @{
bogdanm	0:9b334a45a8ff	682	*/
bogdanm	0:9b334a45a8ff	683	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	0:9b334a45a8ff	684	/**
bogdanm	0:9b334a45a8ff	685	* @}
bogdanm	0:9b334a45a8ff	686	*/
bogdanm	0:9b334a45a8ff	687
bogdanm	0:9b334a45a8ff	688	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	0:9b334a45a8ff	689	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	690	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	691
bogdanm	0:9b334a45a8ff	692	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
bogdanm	0:9b334a45a8ff	693	* @{
bogdanm	0:9b334a45a8ff	694	*/
bogdanm	0:9b334a45a8ff	695	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	696	\|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	697	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	698	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	699	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	700
bogdanm	0:9b334a45a8ff	701	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
bogdanm	0:9b334a45a8ff	702	STM32F030xC */
bogdanm	0:9b334a45a8ff	703
bogdanm	0:9b334a45a8ff	704	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	705	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	706	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	707	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	708	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	709
bogdanm	0:9b334a45a8ff	710	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	711
bogdanm	0:9b334a45a8ff	712	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	0:9b334a45a8ff	713	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	714	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	715	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	716	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	717	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	718
bogdanm	0:9b334a45a8ff	719	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	0:9b334a45a8ff	720
bogdanm	0:9b334a45a8ff	721	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	722	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	723	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	724	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	725	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	726
bogdanm	0:9b334a45a8ff	727	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	728
bogdanm	0:9b334a45a8ff	729	#if defined(STM32F071xB)
bogdanm	0:9b334a45a8ff	730	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	731	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	732	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	733	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	734	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	735
bogdanm	0:9b334a45a8ff	736	#endif /* STM32F071xB */
bogdanm	0:9b334a45a8ff	737
bogdanm	0:9b334a45a8ff	738	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	0:9b334a45a8ff	739	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	740	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	741	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	742	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	743	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	744	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	0:9b334a45a8ff	745
bogdanm	0:9b334a45a8ff	746	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	0:9b334a45a8ff	747
bogdanm	0:9b334a45a8ff	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	749	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	0:9b334a45a8ff	750	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	0:9b334a45a8ff	751	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	0:9b334a45a8ff	752	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	0:9b334a45a8ff	753	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	0:9b334a45a8ff	754	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
bogdanm	0:9b334a45a8ff	755
bogdanm	0:9b334a45a8ff	756	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	757
bogdanm	0:9b334a45a8ff	758	/**
bogdanm	0:9b334a45a8ff	759	* @}
bogdanm	0:9b334a45a8ff	760	*/
bogdanm	0:9b334a45a8ff	761
bogdanm	0:9b334a45a8ff	762	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	0:9b334a45a8ff	763
bogdanm	0:9b334a45a8ff	764	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm	0:9b334a45a8ff	765	* @{
bogdanm	0:9b334a45a8ff	766	*/
bogdanm	0:9b334a45a8ff	767	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
bogdanm	0:9b334a45a8ff	768	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm	0:9b334a45a8ff	769
bogdanm	0:9b334a45a8ff	770	/**
bogdanm	0:9b334a45a8ff	771	* @}
bogdanm	0:9b334a45a8ff	772	*/
bogdanm	0:9b334a45a8ff	773
bogdanm	0:9b334a45a8ff	774	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	0:9b334a45a8ff	775
bogdanm	0:9b334a45a8ff	776	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	777
bogdanm	0:9b334a45a8ff	778	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm	0:9b334a45a8ff	779	* @{
bogdanm	0:9b334a45a8ff	780	*/
bogdanm	0:9b334a45a8ff	781	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm	0:9b334a45a8ff	782
bogdanm	0:9b334a45a8ff	783	/**
bogdanm	0:9b334a45a8ff	784	* @}
bogdanm	0:9b334a45a8ff	785	*/
bogdanm	0:9b334a45a8ff	786
bogdanm	0:9b334a45a8ff	787	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	788
bogdanm	0:9b334a45a8ff	789	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	790	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	791
bogdanm	0:9b334a45a8ff	792	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm	0:9b334a45a8ff	793	* @{
bogdanm	0:9b334a45a8ff	794	*/
bogdanm	0:9b334a45a8ff	795	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	0:9b334a45a8ff	796	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	0:9b334a45a8ff	797	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	0:9b334a45a8ff	798	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	0:9b334a45a8ff	799
bogdanm	0:9b334a45a8ff	800	/**
bogdanm	0:9b334a45a8ff	801	* @}
bogdanm	0:9b334a45a8ff	802	*/
bogdanm	0:9b334a45a8ff	803
bogdanm	0:9b334a45a8ff	804	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	805	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	806
bogdanm	0:9b334a45a8ff	807	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	808
bogdanm	0:9b334a45a8ff	809	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm	0:9b334a45a8ff	810	* @{
bogdanm	0:9b334a45a8ff	811	*/
bogdanm	0:9b334a45a8ff	812	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	0:9b334a45a8ff	813	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	0:9b334a45a8ff	814	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	0:9b334a45a8ff	815	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	0:9b334a45a8ff	816
bogdanm	0:9b334a45a8ff	817	/**
bogdanm	0:9b334a45a8ff	818	* @}
bogdanm	0:9b334a45a8ff	819	*/
bogdanm	0:9b334a45a8ff	820
bogdanm	0:9b334a45a8ff	821	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	822
bogdanm	0:9b334a45a8ff	823
bogdanm	0:9b334a45a8ff	824	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	825	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	826	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	827	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	828
bogdanm	0:9b334a45a8ff	829	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm	0:9b334a45a8ff	830	* @{
bogdanm	0:9b334a45a8ff	831	*/
bogdanm	0:9b334a45a8ff	832	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	0:9b334a45a8ff	833	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	0:9b334a45a8ff	834
bogdanm	0:9b334a45a8ff	835	/**
bogdanm	0:9b334a45a8ff	836	* @}
bogdanm	0:9b334a45a8ff	837	*/
bogdanm	0:9b334a45a8ff	838
bogdanm	0:9b334a45a8ff	839	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	840	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	841	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	842	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	843
bogdanm	0:9b334a45a8ff	844	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
bogdanm	0:9b334a45a8ff	845	* @{
bogdanm	0:9b334a45a8ff	846	*/
bogdanm	0:9b334a45a8ff	847
bogdanm	0:9b334a45a8ff	848	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	0:9b334a45a8ff	849
bogdanm	0:9b334a45a8ff	850	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	851
bogdanm	0:9b334a45a8ff	852	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	0:9b334a45a8ff	853
bogdanm	0:9b334a45a8ff	854	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	855	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	856	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	857	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	858
bogdanm	0:9b334a45a8ff	859	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm	0:9b334a45a8ff	860	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm	0:9b334a45a8ff	861	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm	0:9b334a45a8ff	862	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm	0:9b334a45a8ff	863	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm	0:9b334a45a8ff	864	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm	0:9b334a45a8ff	865	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm	0:9b334a45a8ff	866	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm	0:9b334a45a8ff	867
bogdanm	0:9b334a45a8ff	868	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	869	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	870	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	871
bogdanm	0:9b334a45a8ff	872	/**
bogdanm	0:9b334a45a8ff	873	* @}
bogdanm	0:9b334a45a8ff	874	*/
bogdanm	0:9b334a45a8ff	875
bogdanm	0:9b334a45a8ff	876	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	877	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	878	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	879
bogdanm	0:9b334a45a8ff	880	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
bogdanm	0:9b334a45a8ff	881	* @{
bogdanm	0:9b334a45a8ff	882	*/
bogdanm	0:9b334a45a8ff	883	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
bogdanm	0:9b334a45a8ff	884	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	0:9b334a45a8ff	885	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	0:9b334a45a8ff	886
bogdanm	0:9b334a45a8ff	887	/**
bogdanm	0:9b334a45a8ff	888	* @}
bogdanm	0:9b334a45a8ff	889	*/
bogdanm	0:9b334a45a8ff	890
bogdanm	0:9b334a45a8ff	891	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
bogdanm	0:9b334a45a8ff	892	* @{
bogdanm	0:9b334a45a8ff	893	*/
bogdanm	0:9b334a45a8ff	894	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	0:9b334a45a8ff	895	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	0:9b334a45a8ff	896	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	0:9b334a45a8ff	897	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	0:9b334a45a8ff	898	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	0:9b334a45a8ff	899	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	0:9b334a45a8ff	900	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	0:9b334a45a8ff	901	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	0:9b334a45a8ff	902
bogdanm	0:9b334a45a8ff	903	/**
bogdanm	0:9b334a45a8ff	904	* @}
bogdanm	0:9b334a45a8ff	905	*/
bogdanm	0:9b334a45a8ff	906
bogdanm	0:9b334a45a8ff	907	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
bogdanm	0:9b334a45a8ff	908	* @{
bogdanm	0:9b334a45a8ff	909	*/
bogdanm	0:9b334a45a8ff	910	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	0:9b334a45a8ff	911	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	0:9b334a45a8ff	912
bogdanm	0:9b334a45a8ff	913	/**
bogdanm	0:9b334a45a8ff	914	* @}
bogdanm	0:9b334a45a8ff	915	*/
bogdanm	0:9b334a45a8ff	916
bogdanm	0:9b334a45a8ff	917	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
bogdanm	0:9b334a45a8ff	918	* @{
bogdanm	0:9b334a45a8ff	919	*/
bogdanm	0:9b334a45a8ff	920	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	0:9b334a45a8ff	921	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	0:9b334a45a8ff	922
bogdanm	0:9b334a45a8ff	923	/**
bogdanm	0:9b334a45a8ff	924	* @}
bogdanm	0:9b334a45a8ff	925	*/
bogdanm	0:9b334a45a8ff	926
bogdanm	0:9b334a45a8ff	927	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
bogdanm	0:9b334a45a8ff	928	* @{
bogdanm	0:9b334a45a8ff	929	*/
bogdanm	0:9b334a45a8ff	930	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	0:9b334a45a8ff	931
bogdanm	0:9b334a45a8ff	932	/**
bogdanm	0:9b334a45a8ff	933	* @}
bogdanm	0:9b334a45a8ff	934	*/
bogdanm	0:9b334a45a8ff	935
bogdanm	0:9b334a45a8ff	936	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
bogdanm	0:9b334a45a8ff	937	* @{
bogdanm	0:9b334a45a8ff	938	*/
bogdanm	0:9b334a45a8ff	939	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	0:9b334a45a8ff	940	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	0:9b334a45a8ff	941	corresponds to a higher output frequency */
bogdanm	0:9b334a45a8ff	942
bogdanm	0:9b334a45a8ff	943	/**
bogdanm	0:9b334a45a8ff	944	* @}
bogdanm	0:9b334a45a8ff	945	*/
bogdanm	0:9b334a45a8ff	946
bogdanm	0:9b334a45a8ff	947	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
bogdanm	0:9b334a45a8ff	948	* @{
bogdanm	0:9b334a45a8ff	949	*/
bogdanm	0:9b334a45a8ff	950	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	0:9b334a45a8ff	951	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	0:9b334a45a8ff	952
bogdanm	0:9b334a45a8ff	953	/**
bogdanm	0:9b334a45a8ff	954	* @}
bogdanm	0:9b334a45a8ff	955	*/
bogdanm	0:9b334a45a8ff	956
bogdanm	0:9b334a45a8ff	957	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
bogdanm	0:9b334a45a8ff	958	* @{
bogdanm	0:9b334a45a8ff	959	*/
bogdanm	0:9b334a45a8ff	960	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	0:9b334a45a8ff	961	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	0:9b334a45a8ff	962	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	0:9b334a45a8ff	963	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	0:9b334a45a8ff	964	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	965	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	966	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	967
bogdanm	0:9b334a45a8ff	968	/**
bogdanm	0:9b334a45a8ff	969	* @}
bogdanm	0:9b334a45a8ff	970	*/
bogdanm	0:9b334a45a8ff	971
bogdanm	0:9b334a45a8ff	972	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
bogdanm	0:9b334a45a8ff	973	* @{
bogdanm	0:9b334a45a8ff	974	*/
bogdanm	0:9b334a45a8ff	975	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	0:9b334a45a8ff	976	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	0:9b334a45a8ff	977	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	0:9b334a45a8ff	978	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	0:9b334a45a8ff	979	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	0:9b334a45a8ff	980	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	0:9b334a45a8ff	981	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	0:9b334a45a8ff	982
bogdanm	0:9b334a45a8ff	983	/**
bogdanm	0:9b334a45a8ff	984	* @}
bogdanm	0:9b334a45a8ff	985	*/
bogdanm	0:9b334a45a8ff	986
bogdanm	0:9b334a45a8ff	987	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	988	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	989	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	990
bogdanm	0:9b334a45a8ff	991	/**
bogdanm	0:9b334a45a8ff	992	* @}
bogdanm	0:9b334a45a8ff	993	*/
bogdanm	0:9b334a45a8ff	994
bogdanm	0:9b334a45a8ff	995	/* Exported macros ------------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	996	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	0:9b334a45a8ff	997	* @{
bogdanm	0:9b334a45a8ff	998	*/
bogdanm	0:9b334a45a8ff	999
bogdanm	0:9b334a45a8ff	1000	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm	0:9b334a45a8ff	1001	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	0:9b334a45a8ff	1002	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1003	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1004	* using it.
bogdanm	0:9b334a45a8ff	1005	* @{
bogdanm	0:9b334a45a8ff	1006	*/
bogdanm	0:9b334a45a8ff	1007	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1008	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1009	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1010	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1011
bogdanm	0:9b334a45a8ff	1012	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1013	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1014	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	1015	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1016	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIODEN);\
bogdanm	0:9b334a45a8ff	1017	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1018	} while(0)
bogdanm	0:9b334a45a8ff	1019
bogdanm	0:9b334a45a8ff	1020	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	0:9b334a45a8ff	1021
bogdanm	0:9b334a45a8ff	1022	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1023	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1024	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1025	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1026
bogdanm	0:9b334a45a8ff	1027	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1028	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1029
bogdanm	0:9b334a45a8ff	1030	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1031	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1032	SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	1033	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1034	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\
bogdanm	0:9b334a45a8ff	1035	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1036	} while(0)
bogdanm	0:9b334a45a8ff	1037
bogdanm	0:9b334a45a8ff	1038	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	0:9b334a45a8ff	1039
bogdanm	0:9b334a45a8ff	1040	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1041	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1042
bogdanm	0:9b334a45a8ff	1043	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1044	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1045	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1046	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1047
bogdanm	0:9b334a45a8ff	1048	#define __HAL_RCC_TSC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1049	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1050	SET_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
bogdanm	0:9b334a45a8ff	1051	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1052	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_TSCEN);\
bogdanm	0:9b334a45a8ff	1053	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1054	} while(0)
bogdanm	0:9b334a45a8ff	1055
bogdanm	0:9b334a45a8ff	1056	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	0:9b334a45a8ff	1057
bogdanm	0:9b334a45a8ff	1058	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1059	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1060	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1061	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1062
bogdanm	0:9b334a45a8ff	1063	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1064
bogdanm	0:9b334a45a8ff	1065	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1066	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1067	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
bogdanm	0:9b334a45a8ff	1068	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1069	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
bogdanm	0:9b334a45a8ff	1070	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1071	} while(0)
bogdanm	0:9b334a45a8ff	1072
bogdanm	0:9b334a45a8ff	1073	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	0:9b334a45a8ff	1074
bogdanm	0:9b334a45a8ff	1075	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1076
bogdanm	0:9b334a45a8ff	1077	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	0:9b334a45a8ff	1078	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1079	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1080	* using it.
bogdanm	0:9b334a45a8ff	1081	*/
bogdanm	0:9b334a45a8ff	1082	#if defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1083	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1084	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1085	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1086	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1087
bogdanm	0:9b334a45a8ff	1088	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1089	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1090	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	1091	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1092	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
bogdanm	0:9b334a45a8ff	1093	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1094	} while(0)
bogdanm	0:9b334a45a8ff	1095
bogdanm	0:9b334a45a8ff	1096	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	0:9b334a45a8ff	1097
bogdanm	0:9b334a45a8ff	1098	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1099	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1100	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1101	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1102
bogdanm	0:9b334a45a8ff	1103	#if defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1104	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1105	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1106	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1107	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1108
bogdanm	0:9b334a45a8ff	1109	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1110	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1111	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm	0:9b334a45a8ff	1112	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1113	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
bogdanm	0:9b334a45a8ff	1114	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1115	} while(0)
bogdanm	0:9b334a45a8ff	1116
bogdanm	0:9b334a45a8ff	1117	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	0:9b334a45a8ff	1118
bogdanm	0:9b334a45a8ff	1119	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1120	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1121	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1122	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1123
bogdanm	0:9b334a45a8ff	1124	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	1125	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1126	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1127	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1128	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1129
bogdanm	0:9b334a45a8ff	1130	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1131	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1132	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	1133	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1134	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
bogdanm	0:9b334a45a8ff	1135	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1136	} while(0)
bogdanm	0:9b334a45a8ff	1137
bogdanm	0:9b334a45a8ff	1138	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	0:9b334a45a8ff	1139
bogdanm	0:9b334a45a8ff	1140	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	0:9b334a45a8ff	1141	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1142	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1143	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1144	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1145
bogdanm	0:9b334a45a8ff	1146	#if defined(STM32F030x8) \
bogdanm	0:9b334a45a8ff	1147	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1148	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1149	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1150
bogdanm	0:9b334a45a8ff	1151	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1152	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1153	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1154	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1155	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
bogdanm	0:9b334a45a8ff	1156	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1157	} while(0)
bogdanm	0:9b334a45a8ff	1158	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1159	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1160	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm	0:9b334a45a8ff	1161	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1162	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
bogdanm	0:9b334a45a8ff	1163	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1164	} while(0)
bogdanm	0:9b334a45a8ff	1165
bogdanm	0:9b334a45a8ff	1166	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	0:9b334a45a8ff	1167	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	0:9b334a45a8ff	1168
bogdanm	0:9b334a45a8ff	1169	#endif /* STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1170	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1171	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1172	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1173
bogdanm	0:9b334a45a8ff	1174	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1177
bogdanm	0:9b334a45a8ff	1178	#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1179	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1180	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1181	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1182	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
bogdanm	0:9b334a45a8ff	1183	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1184	} while(0)
bogdanm	0:9b334a45a8ff	1185
bogdanm	0:9b334a45a8ff	1186	#define __HAL_RCC_DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	0:9b334a45a8ff	1187
bogdanm	0:9b334a45a8ff	1188	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1189	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1190	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1191
bogdanm	0:9b334a45a8ff	1192	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1193	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1194	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1195	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1196
bogdanm	0:9b334a45a8ff	1197	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1198	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1199	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	1200	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1201	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
bogdanm	0:9b334a45a8ff	1202	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1203	} while(0)
bogdanm	0:9b334a45a8ff	1204
bogdanm	0:9b334a45a8ff	1205	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	0:9b334a45a8ff	1206
bogdanm	0:9b334a45a8ff	1207	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1208	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1209	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1210	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1211
bogdanm	0:9b334a45a8ff	1212	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1213	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1214
bogdanm	0:9b334a45a8ff	1215	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1216	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1217	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1218	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1219	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
bogdanm	0:9b334a45a8ff	1220	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1221	} while(0)
bogdanm	0:9b334a45a8ff	1222	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1223	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1224	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1225	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1226	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
bogdanm	0:9b334a45a8ff	1227	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1228	} while(0)
bogdanm	0:9b334a45a8ff	1229	#define __HAL_RCC_USART4_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1230	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1231	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
bogdanm	0:9b334a45a8ff	1232	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1233	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART4EN);\
bogdanm	0:9b334a45a8ff	1234	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1235	} while(0)
bogdanm	0:9b334a45a8ff	1236
bogdanm	0:9b334a45a8ff	1237	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	0:9b334a45a8ff	1238	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	0:9b334a45a8ff	1239	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm	0:9b334a45a8ff	1240
bogdanm	0:9b334a45a8ff	1241	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1242	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1243
bogdanm	0:9b334a45a8ff	1244	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1245	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	1246
bogdanm	0:9b334a45a8ff	1247	#define __HAL_RCC_USB_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1248	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1249	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
bogdanm	0:9b334a45a8ff	1250	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1251	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
bogdanm	0:9b334a45a8ff	1252	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1253	} while(0)
bogdanm	0:9b334a45a8ff	1254
bogdanm	0:9b334a45a8ff	1255	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	0:9b334a45a8ff	1256
bogdanm	0:9b334a45a8ff	1257	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1258	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	1259
bogdanm	0:9b334a45a8ff	1260	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
bogdanm	0:9b334a45a8ff	1261	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1262
bogdanm	0:9b334a45a8ff	1263	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1264	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1265	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
bogdanm	0:9b334a45a8ff	1266	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1267	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CANEN);\
bogdanm	0:9b334a45a8ff	1268	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1269	} while(0)
bogdanm	0:9b334a45a8ff	1270	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	0:9b334a45a8ff	1271
bogdanm	0:9b334a45a8ff	1272	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	0:9b334a45a8ff	1273	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1274
bogdanm	0:9b334a45a8ff	1275	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1276	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1277	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1278
bogdanm	0:9b334a45a8ff	1279	#define __HAL_RCC_CRS_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1280	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1281	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
bogdanm	0:9b334a45a8ff	1282	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1283	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CRSEN);\
bogdanm	0:9b334a45a8ff	1284	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1285	} while(0)
bogdanm	0:9b334a45a8ff	1286
bogdanm	0:9b334a45a8ff	1287	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	0:9b334a45a8ff	1288
bogdanm	0:9b334a45a8ff	1289	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1290	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1291	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1292
bogdanm	0:9b334a45a8ff	1293	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1294
bogdanm	0:9b334a45a8ff	1295	#define __HAL_RCC_USART5_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1296	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1297	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
bogdanm	0:9b334a45a8ff	1298	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1299	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART5EN);\
bogdanm	0:9b334a45a8ff	1300	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1301	} while(0)
bogdanm	0:9b334a45a8ff	1302
bogdanm	0:9b334a45a8ff	1303	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
bogdanm	0:9b334a45a8ff	1304
bogdanm	0:9b334a45a8ff	1305	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1306
bogdanm	0:9b334a45a8ff	1307	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	0:9b334a45a8ff	1308	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1309	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1310	* using it.
bogdanm	0:9b334a45a8ff	1311	*/
bogdanm	0:9b334a45a8ff	1312	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1313	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1314	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1315	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1316
bogdanm	0:9b334a45a8ff	1317	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1318	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1319	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
bogdanm	0:9b334a45a8ff	1320	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1321	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
bogdanm	0:9b334a45a8ff	1322	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1323	} while(0)
bogdanm	0:9b334a45a8ff	1324
bogdanm	0:9b334a45a8ff	1325	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	0:9b334a45a8ff	1326
bogdanm	0:9b334a45a8ff	1327	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1328	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1329	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1330	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1331
bogdanm	0:9b334a45a8ff	1332	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1333
bogdanm	0:9b334a45a8ff	1334	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1335	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1336	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm	0:9b334a45a8ff	1337	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1338	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
bogdanm	0:9b334a45a8ff	1339	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1340	} while(0)
bogdanm	0:9b334a45a8ff	1341
bogdanm	0:9b334a45a8ff	1342	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm	0:9b334a45a8ff	1343
bogdanm	0:9b334a45a8ff	1344	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1345
bogdanm	0:9b334a45a8ff	1346	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1347
bogdanm	0:9b334a45a8ff	1348	#define __HAL_RCC_USART7_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1349	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1350	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
bogdanm	0:9b334a45a8ff	1351	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1352	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART7EN);\
bogdanm	0:9b334a45a8ff	1353	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1354	} while(0)
bogdanm	0:9b334a45a8ff	1355	#define __HAL_RCC_USART8_CLK_ENABLE() do { \
bogdanm	0:9b334a45a8ff	1356	__IO uint32_t tmpreg; \
bogdanm	0:9b334a45a8ff	1357	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
bogdanm	0:9b334a45a8ff	1358	/* Delay after an RCC peripheral clock enabling */ \
bogdanm	0:9b334a45a8ff	1359	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART8EN);\
bogdanm	0:9b334a45a8ff	1360	UNUSED(tmpreg); \
bogdanm	0:9b334a45a8ff	1361	} while(0)
bogdanm	0:9b334a45a8ff	1362
bogdanm	0:9b334a45a8ff	1363	#define __HAL_RCC_USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
bogdanm	0:9b334a45a8ff	1364	#define __HAL_RCC_USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
bogdanm	0:9b334a45a8ff	1365
bogdanm	0:9b334a45a8ff	1366	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1367
bogdanm	0:9b334a45a8ff	1368	/**
bogdanm	0:9b334a45a8ff	1369	* @}
bogdanm	0:9b334a45a8ff	1370	*/
bogdanm	0:9b334a45a8ff	1371
bogdanm	0:9b334a45a8ff	1372
bogdanm	0:9b334a45a8ff	1373	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm	0:9b334a45a8ff	1374	* @brief Forces or releases peripheral reset.
bogdanm	0:9b334a45a8ff	1375	* @{
bogdanm	0:9b334a45a8ff	1376	*/
bogdanm	0:9b334a45a8ff	1377
bogdanm	0:9b334a45a8ff	1378	/** @brief Force or release AHB peripheral reset.
bogdanm	0:9b334a45a8ff	1379	*/
bogdanm	0:9b334a45a8ff	1380	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1381	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1382	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1383	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1384
bogdanm	0:9b334a45a8ff	1385	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	1386
bogdanm	0:9b334a45a8ff	1387	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	0:9b334a45a8ff	1388
bogdanm	0:9b334a45a8ff	1389	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1390	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1391	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1392	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1393
bogdanm	0:9b334a45a8ff	1394	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1395	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1396
bogdanm	0:9b334a45a8ff	1397	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	1398
bogdanm	0:9b334a45a8ff	1399	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	0:9b334a45a8ff	1400
bogdanm	0:9b334a45a8ff	1401	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1402	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1403
bogdanm	0:9b334a45a8ff	1404	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1405	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1406	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1407	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1408
bogdanm	0:9b334a45a8ff	1409	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	0:9b334a45a8ff	1410
bogdanm	0:9b334a45a8ff	1411	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	0:9b334a45a8ff	1412
bogdanm	0:9b334a45a8ff	1413	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1414	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1415	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1416	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1417
bogdanm	0:9b334a45a8ff	1418	/** @brief Force or release APB1 peripheral reset.
bogdanm	0:9b334a45a8ff	1419	*/
bogdanm	0:9b334a45a8ff	1420	#if defined(STM32F030x8) \
bogdanm	0:9b334a45a8ff	1421	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1422	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1423	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1424	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1425
bogdanm	0:9b334a45a8ff	1426	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	1427	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	1428
bogdanm	0:9b334a45a8ff	1429	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	0:9b334a45a8ff	1430	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	0:9b334a45a8ff	1431
bogdanm	0:9b334a45a8ff	1432	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1433	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1434	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1435	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1436
bogdanm	0:9b334a45a8ff	1437	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	1438	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1439	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1440	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1441	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1442
bogdanm	0:9b334a45a8ff	1443	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	1444
bogdanm	0:9b334a45a8ff	1445	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	0:9b334a45a8ff	1446
bogdanm	0:9b334a45a8ff	1447	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	0:9b334a45a8ff	1448	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1449	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1450	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1451	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1452
bogdanm	0:9b334a45a8ff	1453	#if defined(STM32F030x8) \
bogdanm	0:9b334a45a8ff	1454	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1455	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1456	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1457
bogdanm	0:9b334a45a8ff	1458	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1459	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	1460
bogdanm	0:9b334a45a8ff	1461	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	0:9b334a45a8ff	1462	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	0:9b334a45a8ff	1463
bogdanm	0:9b334a45a8ff	1464	#endif /* STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1465	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1467	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1468
bogdanm	0:9b334a45a8ff	1469	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1470	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1471	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1472
bogdanm	0:9b334a45a8ff	1473	#define __HAL_RCC_DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1474
bogdanm	0:9b334a45a8ff	1475	#define __HAL_RCC_DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	0:9b334a45a8ff	1476
bogdanm	0:9b334a45a8ff	1477	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1478	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1479	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1480
bogdanm	0:9b334a45a8ff	1481	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1482	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1483	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1484	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1485
bogdanm	0:9b334a45a8ff	1486	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1487
bogdanm	0:9b334a45a8ff	1488	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	0:9b334a45a8ff	1489
bogdanm	0:9b334a45a8ff	1490	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1491	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1492	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1493	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1494
bogdanm	0:9b334a45a8ff	1495	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1496	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1497
bogdanm	0:9b334a45a8ff	1498	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1499	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1500	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	0:9b334a45a8ff	1501
bogdanm	0:9b334a45a8ff	1502	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	0:9b334a45a8ff	1503	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	0:9b334a45a8ff	1504	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm	0:9b334a45a8ff	1505
bogdanm	0:9b334a45a8ff	1506	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1507	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1508
bogdanm	0:9b334a45a8ff	1509	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1510	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	1511
bogdanm	0:9b334a45a8ff	1512	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	0:9b334a45a8ff	1513
bogdanm	0:9b334a45a8ff	1514	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	0:9b334a45a8ff	1515
bogdanm	0:9b334a45a8ff	1516	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1517	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	1518
bogdanm	0:9b334a45a8ff	1519	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
bogdanm	0:9b334a45a8ff	1520	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1521
bogdanm	0:9b334a45a8ff	1522	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	0:9b334a45a8ff	1523
bogdanm	0:9b334a45a8ff	1524	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	0:9b334a45a8ff	1525
bogdanm	0:9b334a45a8ff	1526	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	0:9b334a45a8ff	1527	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1528
bogdanm	0:9b334a45a8ff	1529	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1530	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1531	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1532
bogdanm	0:9b334a45a8ff	1533	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	0:9b334a45a8ff	1534
bogdanm	0:9b334a45a8ff	1535	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	0:9b334a45a8ff	1536
bogdanm	0:9b334a45a8ff	1537	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1538	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1539	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1540
bogdanm	0:9b334a45a8ff	1541	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1542
bogdanm	0:9b334a45a8ff	1543	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
bogdanm	0:9b334a45a8ff	1544
bogdanm	0:9b334a45a8ff	1545	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
bogdanm	0:9b334a45a8ff	1546
bogdanm	0:9b334a45a8ff	1547	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1548
bogdanm	0:9b334a45a8ff	1549
bogdanm	0:9b334a45a8ff	1550	/** @brief Force or release APB2 peripheral reset.
bogdanm	0:9b334a45a8ff	1551	*/
bogdanm	0:9b334a45a8ff	1552	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1553	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1554	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1555	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1556
bogdanm	0:9b334a45a8ff	1557	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	0:9b334a45a8ff	1558
bogdanm	0:9b334a45a8ff	1559	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	0:9b334a45a8ff	1560
bogdanm	0:9b334a45a8ff	1561	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1562	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1563	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1564	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1565
bogdanm	0:9b334a45a8ff	1566	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1567
bogdanm	0:9b334a45a8ff	1568	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
bogdanm	0:9b334a45a8ff	1569
bogdanm	0:9b334a45a8ff	1570	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm	0:9b334a45a8ff	1571
bogdanm	0:9b334a45a8ff	1572	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1573
bogdanm	0:9b334a45a8ff	1574	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1575
bogdanm	0:9b334a45a8ff	1576	#define __HAL_RCC_USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
bogdanm	0:9b334a45a8ff	1577	#define __HAL_RCC_USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
bogdanm	0:9b334a45a8ff	1578
bogdanm	0:9b334a45a8ff	1579	#define __HAL_RCC_USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
bogdanm	0:9b334a45a8ff	1580	#define __HAL_RCC_USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
bogdanm	0:9b334a45a8ff	1581
bogdanm	0:9b334a45a8ff	1582	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1583
bogdanm	0:9b334a45a8ff	1584	/**
bogdanm	0:9b334a45a8ff	1585	* @}
bogdanm	0:9b334a45a8ff	1586	*/
bogdanm	0:9b334a45a8ff	1587
bogdanm	0:9b334a45a8ff	1588	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	1589	* @brief Get the enable or disable status of peripheral clock.
bogdanm	0:9b334a45a8ff	1590	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	0:9b334a45a8ff	1591	* is disabled and the application software has to enable this clock before
bogdanm	0:9b334a45a8ff	1592	* using it.
bogdanm	0:9b334a45a8ff	1593	* @{
bogdanm	0:9b334a45a8ff	1594	*/
bogdanm	0:9b334a45a8ff	1595	/** @brief AHB Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	1596	*/
bogdanm	0:9b334a45a8ff	1597	#if defined(STM32F030x6) \|\| defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1598	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1599	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1600	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1601
bogdanm	0:9b334a45a8ff	1602	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) != RESET)
bogdanm	0:9b334a45a8ff	1603	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIODEN)) == RESET)
bogdanm	0:9b334a45a8ff	1604
bogdanm	0:9b334a45a8ff	1605	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1606	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1607	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1608	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1609
bogdanm	0:9b334a45a8ff	1610	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1611	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1612
bogdanm	0:9b334a45a8ff	1613	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != RESET)
bogdanm	0:9b334a45a8ff	1614	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == RESET)
bogdanm	0:9b334a45a8ff	1615
bogdanm	0:9b334a45a8ff	1616	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1617	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1618
bogdanm	0:9b334a45a8ff	1619	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1620	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1621	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1622	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1623
bogdanm	0:9b334a45a8ff	1624	#define __HAL_RCC_TSC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) != RESET)
bogdanm	0:9b334a45a8ff	1625	#define __HAL_RCC_TSC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_TSCEN)) == RESET)
bogdanm	0:9b334a45a8ff	1626
bogdanm	0:9b334a45a8ff	1627	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1628	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1629	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1630	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1631
bogdanm	0:9b334a45a8ff	1632	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1633
bogdanm	0:9b334a45a8ff	1634	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1635	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1636
bogdanm	0:9b334a45a8ff	1637	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1638
bogdanm	0:9b334a45a8ff	1639	/** @brief APB1 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	1640	*/
bogdanm	0:9b334a45a8ff	1641	#if defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1642	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1643	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1644	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1645	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1646
bogdanm	0:9b334a45a8ff	1647	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1648	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1649
bogdanm	0:9b334a45a8ff	1650	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1651	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1652	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1653	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1654
bogdanm	0:9b334a45a8ff	1655	#if defined(STM32F030x8)\
bogdanm	0:9b334a45a8ff	1656	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1657	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1658	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1659	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1660
bogdanm	0:9b334a45a8ff	1661	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1662	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1663
bogdanm	0:9b334a45a8ff	1664	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1665	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1666	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1667	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1668
bogdanm	0:9b334a45a8ff	1669	#if defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	1670	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1671	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1672	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1673	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1674
bogdanm	0:9b334a45a8ff	1675	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1676	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1677
bogdanm	0:9b334a45a8ff	1678	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	0:9b334a45a8ff	1679	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1680	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1681	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1682	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1683
bogdanm	0:9b334a45a8ff	1684	#if defined(STM32F030x8) \
bogdanm	0:9b334a45a8ff	1685	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1686	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1687	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1688
bogdanm	0:9b334a45a8ff	1689	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
bogdanm	0:9b334a45a8ff	1690	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
bogdanm	0:9b334a45a8ff	1691	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
bogdanm	0:9b334a45a8ff	1692	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
bogdanm	0:9b334a45a8ff	1693
bogdanm	0:9b334a45a8ff	1694	#endif /* STM32F030x8 \|\| */
bogdanm	0:9b334a45a8ff	1695	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1696	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1697	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1698
bogdanm	0:9b334a45a8ff	1699	#if defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1700	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1701	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1702
bogdanm	0:9b334a45a8ff	1703	#define __HAL_RCC_DAC1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1704	#define __HAL_RCC_DAC1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DAC1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1705
bogdanm	0:9b334a45a8ff	1706	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1707	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1708	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1709
bogdanm	0:9b334a45a8ff	1710	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1711	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1712	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1713	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1714
bogdanm	0:9b334a45a8ff	1715	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
bogdanm	0:9b334a45a8ff	1716	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
bogdanm	0:9b334a45a8ff	1717
bogdanm	0:9b334a45a8ff	1718	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1719	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1720	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1721	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1722
bogdanm	0:9b334a45a8ff	1723	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1724	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1725
bogdanm	0:9b334a45a8ff	1726	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
bogdanm	0:9b334a45a8ff	1727	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
bogdanm	0:9b334a45a8ff	1728	#define __HAL_RCC_USART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) != RESET)
bogdanm	0:9b334a45a8ff	1729	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
bogdanm	0:9b334a45a8ff	1730	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
bogdanm	0:9b334a45a8ff	1731	#define __HAL_RCC_USART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART4EN)) == RESET)
bogdanm	0:9b334a45a8ff	1732
bogdanm	0:9b334a45a8ff	1733	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1734	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1735
bogdanm	0:9b334a45a8ff	1736	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1737	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	1738
bogdanm	0:9b334a45a8ff	1739	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
bogdanm	0:9b334a45a8ff	1740	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
bogdanm	0:9b334a45a8ff	1741
bogdanm	0:9b334a45a8ff	1742	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1743	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	1744
bogdanm	0:9b334a45a8ff	1745	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB)\
bogdanm	0:9b334a45a8ff	1746	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1747
bogdanm	0:9b334a45a8ff	1748	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
bogdanm	0:9b334a45a8ff	1749	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
bogdanm	0:9b334a45a8ff	1750
bogdanm	0:9b334a45a8ff	1751	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	0:9b334a45a8ff	1752	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1753
bogdanm	0:9b334a45a8ff	1754	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1755	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1756	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1757
bogdanm	0:9b334a45a8ff	1758	#define __HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) != RESET)
bogdanm	0:9b334a45a8ff	1759	#define __HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CRSEN)) == RESET)
bogdanm	0:9b334a45a8ff	1760
bogdanm	0:9b334a45a8ff	1761	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1762	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1763	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1764
bogdanm	0:9b334a45a8ff	1765	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1766
bogdanm	0:9b334a45a8ff	1767	#define __HAL_RCC_USART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) != RESET)
bogdanm	0:9b334a45a8ff	1768	#define __HAL_RCC_USART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART5EN)) == RESET)
bogdanm	0:9b334a45a8ff	1769
bogdanm	0:9b334a45a8ff	1770	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1771
bogdanm	0:9b334a45a8ff	1772	/** @brief APB1 Peripheral Clock Enable Disable Status
bogdanm	0:9b334a45a8ff	1773	*/
bogdanm	0:9b334a45a8ff	1774	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1775	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1776	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1777	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1778
bogdanm	0:9b334a45a8ff	1779	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
bogdanm	0:9b334a45a8ff	1780	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
bogdanm	0:9b334a45a8ff	1781
bogdanm	0:9b334a45a8ff	1782	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1783	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1784	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1785	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1786
bogdanm	0:9b334a45a8ff	1787	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1788
bogdanm	0:9b334a45a8ff	1789	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
bogdanm	0:9b334a45a8ff	1790	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
bogdanm	0:9b334a45a8ff	1791
bogdanm	0:9b334a45a8ff	1792	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1793
bogdanm	0:9b334a45a8ff	1794	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1795
bogdanm	0:9b334a45a8ff	1796	#define __HAL_RCC_USART7_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) != RESET)
bogdanm	0:9b334a45a8ff	1797	#define __HAL_RCC_USART8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) != RESET)
bogdanm	0:9b334a45a8ff	1798	#define __HAL_RCC_USART7_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART7EN)) == RESET)
bogdanm	0:9b334a45a8ff	1799	#define __HAL_RCC_USART8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART8EN)) == RESET)
bogdanm	0:9b334a45a8ff	1800
bogdanm	0:9b334a45a8ff	1801	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1802	/**
bogdanm	0:9b334a45a8ff	1803	* @}
bogdanm	0:9b334a45a8ff	1804	*/
bogdanm	0:9b334a45a8ff	1805
bogdanm	0:9b334a45a8ff	1806
bogdanm	0:9b334a45a8ff	1807	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
bogdanm	0:9b334a45a8ff	1808	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm	0:9b334a45a8ff	1809	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	0:9b334a45a8ff	1810	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm	0:9b334a45a8ff	1811	* you have to select another source of the system clock then stop the HSI14.
bogdanm	0:9b334a45a8ff	1812	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm	0:9b334a45a8ff	1813	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm	0:9b334a45a8ff	1814	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	0:9b334a45a8ff	1815	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm	0:9b334a45a8ff	1816	* clock cycles.
bogdanm	0:9b334a45a8ff	1817	* @{
bogdanm	0:9b334a45a8ff	1818	*/
bogdanm	0:9b334a45a8ff	1819	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1820	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1821	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1822
bogdanm	0:9b334a45a8ff	1823	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	0:9b334a45a8ff	1824	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	0:9b334a45a8ff	1825
bogdanm	0:9b334a45a8ff	1826	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	0:9b334a45a8ff	1827	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1828	* @arg RCC_HSI48_ON: HSI48 enabled
bogdanm	0:9b334a45a8ff	1829	* @arg RCC_HSI48_OFF: HSI48 disabled
bogdanm	0:9b334a45a8ff	1830	*/
bogdanm	0:9b334a45a8ff	1831	#define __HAL_RCC_GET_HSI48_STATE() \
bogdanm	0:9b334a45a8ff	1832	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm	0:9b334a45a8ff	1833
bogdanm	0:9b334a45a8ff	1834	#else
bogdanm	0:9b334a45a8ff	1835
bogdanm	0:9b334a45a8ff	1836	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	0:9b334a45a8ff	1837	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1838	* @arg RCC_HSI_OFF: HSI48 disabled
bogdanm	0:9b334a45a8ff	1839	*/
bogdanm	0:9b334a45a8ff	1840	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
bogdanm	0:9b334a45a8ff	1841
bogdanm	0:9b334a45a8ff	1842	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1843	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1844	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	1845
bogdanm	0:9b334a45a8ff	1846	/**
bogdanm	0:9b334a45a8ff	1847	* @}
bogdanm	0:9b334a45a8ff	1848	*/
bogdanm	0:9b334a45a8ff	1849
bogdanm	0:9b334a45a8ff	1850	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
bogdanm	0:9b334a45a8ff	1851	* @{
bogdanm	0:9b334a45a8ff	1852	*/
bogdanm	0:9b334a45a8ff	1853	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1854	\|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1855	\|\| defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	0:9b334a45a8ff	1856
bogdanm	0:9b334a45a8ff	1857	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	0:9b334a45a8ff	1858	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	0:9b334a45a8ff	1859	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1860	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
bogdanm	0:9b334a45a8ff	1861	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1862	*/
bogdanm	0:9b334a45a8ff	1863	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	0:9b334a45a8ff	1864	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
bogdanm	0:9b334a45a8ff	1865
bogdanm	0:9b334a45a8ff	1866	/** @brief Macro to get the USB clock source.
bogdanm	0:9b334a45a8ff	1867	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1868	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	0:9b334a45a8ff	1869	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	0:9b334a45a8ff	1870	*/
bogdanm	0:9b334a45a8ff	1871	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm	0:9b334a45a8ff	1872
bogdanm	0:9b334a45a8ff	1873	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1874	/* STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1875	/* STM32F070x6 \|\| STM32F070xB */
bogdanm	0:9b334a45a8ff	1876
bogdanm	0:9b334a45a8ff	1877	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	1878	\|\| defined(STM32F051x8) \|\| defined(STM32F058xx)\
bogdanm	0:9b334a45a8ff	1879	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1880	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1881
bogdanm	0:9b334a45a8ff	1882	/** @brief Macro to configure the CEC clock.
bogdanm	0:9b334a45a8ff	1883	* @param __CECCLKSource__: specifies the CEC clock source.
bogdanm	0:9b334a45a8ff	1884	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1885	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	1886	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	0:9b334a45a8ff	1887	*/
bogdanm	0:9b334a45a8ff	1888	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm	0:9b334a45a8ff	1889	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm	0:9b334a45a8ff	1890
bogdanm	0:9b334a45a8ff	1891	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	0:9b334a45a8ff	1892	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1893	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	0:9b334a45a8ff	1894	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	0:9b334a45a8ff	1895	*/
bogdanm	0:9b334a45a8ff	1896	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	0:9b334a45a8ff	1897
bogdanm	0:9b334a45a8ff	1898	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1899	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	0:9b334a45a8ff	1900	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	1901	/* STM32F091xC \|\| defined(STM32F098xx) */
bogdanm	0:9b334a45a8ff	1902
bogdanm	0:9b334a45a8ff	1903	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx)\
bogdanm	0:9b334a45a8ff	1904	\|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6)\
bogdanm	0:9b334a45a8ff	1905	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)\
bogdanm	0:9b334a45a8ff	1906	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	0:9b334a45a8ff	1907
bogdanm	0:9b334a45a8ff	1908	/** @brief Macro to configure the MCO clock.
bogdanm	0:9b334a45a8ff	1909	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	0:9b334a45a8ff	1910	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1911	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	0:9b334a45a8ff	1912	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	0:9b334a45a8ff	1913	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	0:9b334a45a8ff	1914	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	0:9b334a45a8ff	1915	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
bogdanm	0:9b334a45a8ff	1916	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	0:9b334a45a8ff	1917	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	0:9b334a45a8ff	1918	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	0:9b334a45a8ff	1919	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	0:9b334a45a8ff	1920	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	0:9b334a45a8ff	1921	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1922	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
bogdanm	0:9b334a45a8ff	1923	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
bogdanm	0:9b334a45a8ff	1924	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
bogdanm	0:9b334a45a8ff	1925	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
bogdanm	0:9b334a45a8ff	1926	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
bogdanm	0:9b334a45a8ff	1927	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
bogdanm	0:9b334a45a8ff	1928	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
bogdanm	0:9b334a45a8ff	1929	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
bogdanm	0:9b334a45a8ff	1930	*/
bogdanm	0:9b334a45a8ff	1931	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	0:9b334a45a8ff	1932	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
bogdanm	0:9b334a45a8ff	1933	#else
bogdanm	0:9b334a45a8ff	1934
bogdanm	0:9b334a45a8ff	1935	/** @brief Macro to configure the MCO clock.
bogdanm	0:9b334a45a8ff	1936	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	0:9b334a45a8ff	1937	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1938	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	0:9b334a45a8ff	1939	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	0:9b334a45a8ff	1940	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	0:9b334a45a8ff	1941	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	0:9b334a45a8ff	1942	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	0:9b334a45a8ff	1943	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	0:9b334a45a8ff	1944	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	0:9b334a45a8ff	1945	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	0:9b334a45a8ff	1946	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	0:9b334a45a8ff	1947	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1948	* @arg RCC_MCODIV_1: No division applied on MCO clock source
bogdanm	0:9b334a45a8ff	1949	*/
bogdanm	0:9b334a45a8ff	1950	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	0:9b334a45a8ff	1951	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
bogdanm	0:9b334a45a8ff	1952
bogdanm	0:9b334a45a8ff	1953	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
bogdanm	0:9b334a45a8ff	1954	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	1955	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
bogdanm	0:9b334a45a8ff	1956	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	0:9b334a45a8ff	1957
bogdanm	0:9b334a45a8ff	1958	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	1959	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1960	/** @brief Macro to configure the USART2 clock (USART2CLK).
bogdanm	0:9b334a45a8ff	1961	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	0:9b334a45a8ff	1962	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1963	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1964	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1965	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1966	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	1967	*/
bogdanm	0:9b334a45a8ff	1968	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	0:9b334a45a8ff	1969	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
bogdanm	0:9b334a45a8ff	1970
bogdanm	0:9b334a45a8ff	1971	/** @brief Macro to get the USART2 clock source.
bogdanm	0:9b334a45a8ff	1972	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1973	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	0:9b334a45a8ff	1974	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	0:9b334a45a8ff	1975	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	0:9b334a45a8ff	1976	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	0:9b334a45a8ff	1977	*/
bogdanm	0:9b334a45a8ff	1978	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
bogdanm	0:9b334a45a8ff	1979	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
bogdanm	0:9b334a45a8ff	1980
bogdanm	0:9b334a45a8ff	1981	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	1982	/** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm	0:9b334a45a8ff	1983	* @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm	0:9b334a45a8ff	1984	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	1985	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	0:9b334a45a8ff	1986	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	0:9b334a45a8ff	1987	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	0:9b334a45a8ff	1988	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	0:9b334a45a8ff	1989	*/
bogdanm	0:9b334a45a8ff	1990	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm	0:9b334a45a8ff	1991	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm	0:9b334a45a8ff	1992
bogdanm	0:9b334a45a8ff	1993	/** @brief Macro to get the USART3 clock source.
bogdanm	0:9b334a45a8ff	1994	* @retval The clock source can be one of the following values:
bogdanm	0:9b334a45a8ff	1995	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	0:9b334a45a8ff	1996	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	0:9b334a45a8ff	1997	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	0:9b334a45a8ff	1998	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	0:9b334a45a8ff	1999	*/
bogdanm	0:9b334a45a8ff	2000	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm	0:9b334a45a8ff	2001
bogdanm	0:9b334a45a8ff	2002	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	2003	/**
bogdanm	0:9b334a45a8ff	2004	* @}
bogdanm	0:9b334a45a8ff	2005	*/
bogdanm	0:9b334a45a8ff	2006
bogdanm	0:9b334a45a8ff	2007	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	2008	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	2009	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	2010
bogdanm	0:9b334a45a8ff	2011	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
bogdanm	0:9b334a45a8ff	2012	* @{
bogdanm	0:9b334a45a8ff	2013	*/
bogdanm	0:9b334a45a8ff	2014	/* Interrupt & Flag management */
bogdanm	0:9b334a45a8ff	2015
bogdanm	0:9b334a45a8ff	2016	/**
bogdanm	0:9b334a45a8ff	2017	* @brief Enables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	2018	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	0:9b334a45a8ff	2019	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2020	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	2021	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	2022	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	2023	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	2024	* @retval None
bogdanm	0:9b334a45a8ff	2025	*/
bogdanm	0:9b334a45a8ff	2026	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2027
bogdanm	0:9b334a45a8ff	2028	/**
bogdanm	0:9b334a45a8ff	2029	* @brief Disables the specified CRS interrupts.
bogdanm	0:9b334a45a8ff	2030	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	0:9b334a45a8ff	2031	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2032	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	2033	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	2034	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	2035	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	2036	* @retval None
bogdanm	0:9b334a45a8ff	2037	*/
bogdanm	0:9b334a45a8ff	2038	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	0:9b334a45a8ff	2039
bogdanm	0:9b334a45a8ff	2040	/** @brief Check the CRS's interrupt has occurred or not.
bogdanm	0:9b334a45a8ff	2041	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	0:9b334a45a8ff	2042	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2043	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	2044	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	2045	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	2046	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	2047	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	0:9b334a45a8ff	2048	*/
bogdanm	0:9b334a45a8ff	2049	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	0:9b334a45a8ff	2050
bogdanm	0:9b334a45a8ff	2051	/** @brief Clear the CRS's interrupt pending bits
bogdanm	0:9b334a45a8ff	2052	* bits to clear the selected interrupt pending bits.
bogdanm	0:9b334a45a8ff	2053	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	0:9b334a45a8ff	2054	* This parameter can be any combination of the following values:
bogdanm	0:9b334a45a8ff	2055	* @arg RCC_CRS_IT_SYNCOK
bogdanm	0:9b334a45a8ff	2056	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	0:9b334a45a8ff	2057	* @arg RCC_CRS_IT_ERR
bogdanm	0:9b334a45a8ff	2058	* @arg RCC_CRS_IT_ESYNC
bogdanm	0:9b334a45a8ff	2059	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	0:9b334a45a8ff	2060	* @arg RCC_CRS_IT_SYNCERR
bogdanm	0:9b334a45a8ff	2061	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	0:9b334a45a8ff	2062	*/
bogdanm	0:9b334a45a8ff	2063	/* CRS IT Error Mask */
bogdanm	0:9b334a45a8ff	2064	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	0:9b334a45a8ff	2065
bogdanm	0:9b334a45a8ff	2066	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	2067	(CRS->ICR \|= (__INTERRUPT__)))
bogdanm	0:9b334a45a8ff	2068
bogdanm	0:9b334a45a8ff	2069	/**
bogdanm	0:9b334a45a8ff	2070	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	0:9b334a45a8ff	2071	* @param _FLAG_: specifies the flag to check.
bogdanm	0:9b334a45a8ff	2072	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2073	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	2074	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	2075	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	2076	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	2077	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	2078	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	2079	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	2080	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	0:9b334a45a8ff	2081	*/
bogdanm	0:9b334a45a8ff	2082	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm	0:9b334a45a8ff	2083
bogdanm	0:9b334a45a8ff	2084	/**
bogdanm	0:9b334a45a8ff	2085	* @brief Clears the CRS specified FLAG.
bogdanm	0:9b334a45a8ff	2086	* @param _FLAG_: specifies the flag to clear.
bogdanm	0:9b334a45a8ff	2087	* This parameter can be one of the following values:
bogdanm	0:9b334a45a8ff	2088	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	0:9b334a45a8ff	2089	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	0:9b334a45a8ff	2090	* @arg RCC_CRS_FLAG_ERR
bogdanm	0:9b334a45a8ff	2091	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	0:9b334a45a8ff	2092	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	0:9b334a45a8ff	2093	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	0:9b334a45a8ff	2094	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	0:9b334a45a8ff	2095	* @retval None
bogdanm	0:9b334a45a8ff	2096	*/
bogdanm	0:9b334a45a8ff	2097
bogdanm	0:9b334a45a8ff	2098	/* CRS Flag Error Mask */
bogdanm	0:9b334a45a8ff	2099	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	0:9b334a45a8ff	2100
bogdanm	0:9b334a45a8ff	2101	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	0:9b334a45a8ff	2102	(CRS->ICR \|= (__FLAG__)))
bogdanm	0:9b334a45a8ff	2103
bogdanm	0:9b334a45a8ff	2104	/**
bogdanm	0:9b334a45a8ff	2105	* @}
bogdanm	0:9b334a45a8ff	2106	*/
bogdanm	0:9b334a45a8ff	2107
bogdanm	0:9b334a45a8ff	2108	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
bogdanm	0:9b334a45a8ff	2109	* @{
bogdanm	0:9b334a45a8ff	2110	*/
bogdanm	0:9b334a45a8ff	2111	/**
bogdanm	0:9b334a45a8ff	2112	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	2113	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	2114	* @retval None
bogdanm	0:9b334a45a8ff	2115	*/
bogdanm	0:9b334a45a8ff	2116	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	2117
bogdanm	0:9b334a45a8ff	2118	/**
bogdanm	0:9b334a45a8ff	2119	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	0:9b334a45a8ff	2120	* @retval None
bogdanm	0:9b334a45a8ff	2121	*/
bogdanm	0:9b334a45a8ff	2122	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	0:9b334a45a8ff	2123
bogdanm	0:9b334a45a8ff	2124	/**
bogdanm	0:9b334a45a8ff	2125	* @brief Enables the automatic hardware adjustement of TRIM bits.
bogdanm	0:9b334a45a8ff	2126	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	0:9b334a45a8ff	2127	* @retval None
bogdanm	0:9b334a45a8ff	2128	*/
bogdanm	0:9b334a45a8ff	2129	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	2130
bogdanm	0:9b334a45a8ff	2131	/**
bogdanm	0:9b334a45a8ff	2132	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
bogdanm	0:9b334a45a8ff	2133	* @retval None
bogdanm	0:9b334a45a8ff	2134	*/
bogdanm	0:9b334a45a8ff	2135	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	0:9b334a45a8ff	2136
bogdanm	0:9b334a45a8ff	2137	/**
bogdanm	0:9b334a45a8ff	2138	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	0:9b334a45a8ff	2139	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	0:9b334a45a8ff	2140	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	0:9b334a45a8ff	2141	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	0:9b334a45a8ff	2142	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	0:9b334a45a8ff	2143	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	0:9b334a45a8ff	2144	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	0:9b334a45a8ff	2145	* @retval None
bogdanm	0:9b334a45a8ff	2146	*/
bogdanm	0:9b334a45a8ff	2147	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm	0:9b334a45a8ff	2148
bogdanm	0:9b334a45a8ff	2149	/**
bogdanm	0:9b334a45a8ff	2150	* @}
bogdanm	0:9b334a45a8ff	2151	*/
bogdanm	0:9b334a45a8ff	2152
bogdanm	0:9b334a45a8ff	2153	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	2154	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	2155	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	2156
bogdanm	0:9b334a45a8ff	2157	/**
bogdanm	0:9b334a45a8ff	2158	* @}
bogdanm	0:9b334a45a8ff	2159	*/
bogdanm	0:9b334a45a8ff	2160
bogdanm	0:9b334a45a8ff	2161	/* Exported functions --------------------------------------------------------*/
bogdanm	0:9b334a45a8ff	2162	/** @addtogroup RCCEx_Exported_Functions
bogdanm	0:9b334a45a8ff	2163	* @{
bogdanm	0:9b334a45a8ff	2164	*/
bogdanm	0:9b334a45a8ff	2165
bogdanm	0:9b334a45a8ff	2166	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	0:9b334a45a8ff	2167	* @{
bogdanm	0:9b334a45a8ff	2168	*/
bogdanm	0:9b334a45a8ff	2169
bogdanm	0:9b334a45a8ff	2170	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2171	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	0:9b334a45a8ff	2172	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
bogdanm	0:9b334a45a8ff	2173
bogdanm	0:9b334a45a8ff	2174	#if defined(STM32F042x6) \|\| defined(STM32F048xx)\
bogdanm	0:9b334a45a8ff	2175	\|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)\
bogdanm	0:9b334a45a8ff	2176	\|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	0:9b334a45a8ff	2177	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	0:9b334a45a8ff	2178	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	0:9b334a45a8ff	2179	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
bogdanm	0:9b334a45a8ff	2180	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	0:9b334a45a8ff	2181	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	0:9b334a45a8ff	2182	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	0:9b334a45a8ff	2183	/* STM32F091xC \|\| STM32F098xx */
bogdanm	0:9b334a45a8ff	2184
bogdanm	0:9b334a45a8ff	2185
bogdanm	0:9b334a45a8ff	2186	/**
bogdanm	0:9b334a45a8ff	2187	* @}
bogdanm	0:9b334a45a8ff	2188	*/
bogdanm	0:9b334a45a8ff	2189
bogdanm	0:9b334a45a8ff	2190	/**
bogdanm	0:9b334a45a8ff	2191	* @}
bogdanm	0:9b334a45a8ff	2192	*/
bogdanm	0:9b334a45a8ff	2193
bogdanm	0:9b334a45a8ff	2194	/**
bogdanm	0:9b334a45a8ff	2195	* @}
bogdanm	0:9b334a45a8ff	2196	*/
bogdanm	0:9b334a45a8ff	2197
bogdanm	0:9b334a45a8ff	2198	/**
bogdanm	0:9b334a45a8ff	2199	* @}
bogdanm	0:9b334a45a8ff	2200	*/
bogdanm	0:9b334a45a8ff	2201
bogdanm	0:9b334a45a8ff	2202	#ifdef __cplusplus
bogdanm	0:9b334a45a8ff	2203	}
bogdanm	0:9b334a45a8ff	2204	#endif
bogdanm	0:9b334a45a8ff	2205
bogdanm	0:9b334a45a8ff	2206	#endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm	0:9b334a45a8ff	2207
bogdanm	0:9b334a45a8ff	2208	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/