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mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f0xx_hal_rcc_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.3.0
bogdanm 0:9b334a45a8ff 6 * @date 26-June-2015
bogdanm 0:9b334a45a8ff 7 * @brief Extended RCC HAL module driver
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities RCC extension peripheral:
bogdanm 0:9b334a45a8ff 10 * + Extended Clock Source configuration functions
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 @verbatim
bogdanm 0:9b334a45a8ff 13 ==============================================================================
bogdanm 0:9b334a45a8ff 14 ##### How to use this driver #####
bogdanm 0:9b334a45a8ff 15 ==============================================================================
bogdanm 0:9b334a45a8ff 16
bogdanm 0:9b334a45a8ff 17 For CRS, RCC Extention HAL driver can be used as follows:
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 (#) In System clock config, HSI48 need to be enabled
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 (#] Enable CRS clock in IP MSP init which will use CRS functions
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 (#) Call CRS functions like this
bogdanm 0:9b334a45a8ff 24 (##) Prepare synchronization configuration necessary for HSI48 calibration
bogdanm 0:9b334a45a8ff 25 (+++) Default values can be set for frequency Error Measurement (reload and error limit)
bogdanm 0:9b334a45a8ff 26 and also HSI48 oscillator smooth trimming.
bogdanm 0:9b334a45a8ff 27 (+++) Macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE can be also used to calculate
bogdanm 0:9b334a45a8ff 28 directly reload value with target and sychronization frequencies values
bogdanm 0:9b334a45a8ff 29 (##) Call function HAL_RCCEx_CRSConfig which
bogdanm 0:9b334a45a8ff 30 (+++) Reset CRS registers to their default values.
bogdanm 0:9b334a45a8ff 31 (+++) Configure CRS registers with synchronization configuration
bogdanm 0:9b334a45a8ff 32 (+++) Enable automatic calibration and frequency error counter feature
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 (##) A polling function is provided to wait for complete Synchronization
bogdanm 0:9b334a45a8ff 35 (+++) Call function HAL_RCCEx_CRSWaitSynchronization()
bogdanm 0:9b334a45a8ff 36 (+++) According to CRS status, user can decide to adjust again the calibration or continue
bogdanm 0:9b334a45a8ff 37 application if synchronization is OK
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 (#) User can retrieve information related to synchronization in calling function
bogdanm 0:9b334a45a8ff 40 HAL_RCCEx_CRSGetSynchronizationInfo()
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 (#) Regarding synchronization status and synchronization information, user can try a new calibration
bogdanm 0:9b334a45a8ff 43 in changing synchronization configuration and call again HAL_RCCEx_CRSConfig.
bogdanm 0:9b334a45a8ff 44 Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value),
bogdanm 0:9b334a45a8ff 45 it means that the actual frequency is lower than the target (and so, that the TRIM value should be
bogdanm 0:9b334a45a8ff 46 incremented), while when it is detected during the upcounting phase it means that the actual frequency
bogdanm 0:9b334a45a8ff 47 is higher (and that the TRIM value should be decremented).
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 (#) To use IT mode, user needs to handle it in calling different macros available to do it
bogdanm 0:9b334a45a8ff 50 (__HAL_RCC_CRS_XXX_IT). Interuptions will go through RCC Handler (RCC_IRQn/RCC_CRS_IRQHandler)
bogdanm 0:9b334a45a8ff 51 (++) Call function HAL_RCCEx_CRSConfig()
bogdanm 0:9b334a45a8ff 52 (++) Enable RCC_IRQn (thnaks to NVIC functions)
bogdanm 0:9b334a45a8ff 53 (++) Enable CRS IT (__HAL_RCC_CRS_ENABLE_IT)
bogdanm 0:9b334a45a8ff 54 (++) Implement CRS status management in RCC_CRS_IRQHandler
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 (#) To force a SYNC EVENT, user can use function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). Function can be
bogdanm 0:9b334a45a8ff 57 called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler)
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 @endverbatim
bogdanm 0:9b334a45a8ff 60 ******************************************************************************
bogdanm 0:9b334a45a8ff 61 * @attention
bogdanm 0:9b334a45a8ff 62 *
bogdanm 0:9b334a45a8ff 63 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 64 *
bogdanm 0:9b334a45a8ff 65 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 66 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 67 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 68 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 69 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 70 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 71 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 72 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 73 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 74 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 75 *
bogdanm 0:9b334a45a8ff 76 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 77 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 78 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 79 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 80 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 81 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 82 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 83 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 84 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 85 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 86 *
bogdanm 0:9b334a45a8ff 87 ******************************************************************************
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 91 #include "stm32f0xx_hal.h"
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /** @addtogroup STM32F0xx_HAL_Driver
bogdanm 0:9b334a45a8ff 94 * @{
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 98
bogdanm 0:9b334a45a8ff 99 /** @defgroup RCCEx RCCEx
bogdanm 0:9b334a45a8ff 100 * @brief RCC Extension HAL module driver.
bogdanm 0:9b334a45a8ff 101 * @{
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 105 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 106 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109 /* Bit position in register */
bogdanm 0:9b334a45a8ff 110 #define CRS_CFGR_FELIM_BITNUMBER 16
bogdanm 0:9b334a45a8ff 111 #define CRS_CR_TRIM_BITNUMBER 8
bogdanm 0:9b334a45a8ff 112 #define CRS_ISR_FECAP_BITNUMBER 16
bogdanm 0:9b334a45a8ff 113 /**
bogdanm 0:9b334a45a8ff 114 * @}
bogdanm 0:9b334a45a8ff 115 */
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 118 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm 0:9b334a45a8ff 119 * @{
bogdanm 0:9b334a45a8ff 120 */
bogdanm 0:9b334a45a8ff 121 /**
bogdanm 0:9b334a45a8ff 122 * @}
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 125 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 126 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm 0:9b334a45a8ff 129 * @{
bogdanm 0:9b334a45a8ff 130 */
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 133 * @brief Extended RCC clocks control functions
bogdanm 0:9b334a45a8ff 134 *
bogdanm 0:9b334a45a8ff 135 @verbatim
bogdanm 0:9b334a45a8ff 136 ===============================================================================
bogdanm 0:9b334a45a8ff 137 ##### Extended Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 138 ===============================================================================
bogdanm 0:9b334a45a8ff 139 [..]
bogdanm 0:9b334a45a8ff 140 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 141 frequencies.
bogdanm 0:9b334a45a8ff 142 [..]
bogdanm 0:9b334a45a8ff 143 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm 0:9b334a45a8ff 144 select the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 145 order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 146 the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 @endverbatim
bogdanm 0:9b334a45a8ff 149 * @{
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /**
bogdanm 0:9b334a45a8ff 153 * @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm 0:9b334a45a8ff 154 * parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm 0:9b334a45a8ff 155 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 156 * contains the configuration information for the Extended Peripherals clocks
bogdanm 0:9b334a45a8ff 157 * (USART, RTC, I2C, CEC and USB).
bogdanm 0:9b334a45a8ff 158 *
bogdanm 0:9b334a45a8ff 159 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm 0:9b334a45a8ff 160 * the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 161 * order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 162 * the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 163 *
bogdanm 0:9b334a45a8ff 164 * @retval None
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 169 uint32_t temp_reg = 0;
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Check the parameters */
bogdanm 0:9b334a45a8ff 172 assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /*---------------------------- RTC configuration -------------------------------*/
bogdanm 0:9b334a45a8ff 175 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 /* Reset the Backup domain only if the RTC Clock source selction is modified */
bogdanm 0:9b334a45a8ff 178 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm 0:9b334a45a8ff 179 {
bogdanm 0:9b334a45a8ff 180 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 181 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 184 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 187 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 192 {
bogdanm 0:9b334a45a8ff 193 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 194 }
bogdanm 0:9b334a45a8ff 195 }
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* Store the content of BDCR register before the reset of Backup Domain */
bogdanm 0:9b334a45a8ff 198 temp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm 0:9b334a45a8ff 199 /* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm 0:9b334a45a8ff 200 __HAL_RCC_BACKUPRESET_FORCE();
bogdanm 0:9b334a45a8ff 201 __HAL_RCC_BACKUPRESET_RELEASE();
bogdanm 0:9b334a45a8ff 202 /* Restore the Content of BDCR register */
bogdanm 0:9b334a45a8ff 203 RCC->BDCR = temp_reg;
bogdanm 0:9b334a45a8ff 204
bogdanm 0:9b334a45a8ff 205 /* Wait for LSERDY if LSE was enabled */
bogdanm 0:9b334a45a8ff 206 if (HAL_IS_BIT_SET(temp_reg, RCC_BDCR_LSERDY))
bogdanm 0:9b334a45a8ff 207 {
bogdanm 0:9b334a45a8ff 208 /* Get timeout */
bogdanm 0:9b334a45a8ff 209 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 210
bogdanm 0:9b334a45a8ff 211 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 212 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 213 {
bogdanm 0:9b334a45a8ff 214 if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 215 {
bogdanm 0:9b334a45a8ff 216 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 217 }
bogdanm 0:9b334a45a8ff 218 }
bogdanm 0:9b334a45a8ff 219 }
bogdanm 0:9b334a45a8ff 220 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /*------------------------------- USART1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 225 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
bogdanm 0:9b334a45a8ff 226 {
bogdanm 0:9b334a45a8ff 227 /* Check the parameters */
bogdanm 0:9b334a45a8ff 228 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /* Configure the USART1 clock source */
bogdanm 0:9b334a45a8ff 231 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233
bogdanm 0:9b334a45a8ff 234 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
bogdanm 0:9b334a45a8ff 235 || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 236 /*----------------------------- USART2 Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 237 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 /* Check the parameters */
bogdanm 0:9b334a45a8ff 240 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 /* Configure the USART2 clock source */
bogdanm 0:9b334a45a8ff 243 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
bogdanm 0:9b334a45a8ff 244 }
bogdanm 0:9b334a45a8ff 245 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 0:9b334a45a8ff 246 /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 249 /*----------------------------- USART3 Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 250 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
bogdanm 0:9b334a45a8ff 251 {
bogdanm 0:9b334a45a8ff 252 /* Check the parameters */
bogdanm 0:9b334a45a8ff 253 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
bogdanm 0:9b334a45a8ff 254
bogdanm 0:9b334a45a8ff 255 /* Configure the USART3 clock source */
bogdanm 0:9b334a45a8ff 256 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
bogdanm 0:9b334a45a8ff 257 }
bogdanm 0:9b334a45a8ff 258 #endif /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 259
bogdanm 0:9b334a45a8ff 260 /*------------------------------ I2C1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 261 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
bogdanm 0:9b334a45a8ff 262 {
bogdanm 0:9b334a45a8ff 263 /* Check the parameters */
bogdanm 0:9b334a45a8ff 264 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
bogdanm 0:9b334a45a8ff 265
bogdanm 0:9b334a45a8ff 266 /* Configure the I2C1 clock source */
bogdanm 0:9b334a45a8ff 267 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
bogdanm 0:9b334a45a8ff 271 /*------------------------------ USB Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 272 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
bogdanm 0:9b334a45a8ff 273 {
bogdanm 0:9b334a45a8ff 274 /* Check the parameters */
bogdanm 0:9b334a45a8ff 275 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /* Configure the USB clock source */
bogdanm 0:9b334a45a8ff 278 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
bogdanm 0:9b334a45a8ff 279 }
bogdanm 0:9b334a45a8ff 280 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
bogdanm 0:9b334a45a8ff 281
bogdanm 0:9b334a45a8ff 282 #if defined(STM32F042x6) || defined(STM32F048xx)\
bogdanm 0:9b334a45a8ff 283 || defined(STM32F051x8) || defined(STM32F058xx)\
bogdanm 0:9b334a45a8ff 284 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
bogdanm 0:9b334a45a8ff 285 || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 286 /*------------------------------ CEC clock Configuration -------------------*/
bogdanm 0:9b334a45a8ff 287 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
bogdanm 0:9b334a45a8ff 288 {
bogdanm 0:9b334a45a8ff 289 /* Check the parameters */
bogdanm 0:9b334a45a8ff 290 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
bogdanm 0:9b334a45a8ff 291
bogdanm 0:9b334a45a8ff 292 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 293 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
bogdanm 0:9b334a45a8ff 294 }
bogdanm 0:9b334a45a8ff 295 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 0:9b334a45a8ff 296 /* STM32F051x8 || STM32F058xx || */
bogdanm 0:9b334a45a8ff 297 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 0:9b334a45a8ff 298 /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 return HAL_OK;
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 /**
bogdanm 0:9b334a45a8ff 304 * @brief Get the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 305 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 306 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 307 * returns the configuration information for the Extended Peripherals clocks
bogdanm 0:9b334a45a8ff 308 * (USART, RTC, I2C, CEC and USB).
bogdanm 0:9b334a45a8ff 309 * @retval None
bogdanm 0:9b334a45a8ff 310 */
bogdanm 0:9b334a45a8ff 311 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 312 {
bogdanm 0:9b334a45a8ff 313 /* Set all possible values for the extended clock type parameter------------*/
bogdanm 0:9b334a45a8ff 314 /* Common part first */
bogdanm 0:9b334a45a8ff 315 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
bogdanm 0:9b334a45a8ff 316 /* Get the RTC configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 317 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
bogdanm 0:9b334a45a8ff 318 /* Get the USART1 configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 319 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
bogdanm 0:9b334a45a8ff 320 /* Get the I2C1 clock source -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 321 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
bogdanm 0:9b334a45a8ff 324 || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 325 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART2;
bogdanm 0:9b334a45a8ff 326 /* Get the USART2 clock source ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 327 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
bogdanm 0:9b334a45a8ff 328 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 0:9b334a45a8ff 329 /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 #if defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 332 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USART3;
bogdanm 0:9b334a45a8ff 333 /* Get the USART3 clock source ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 334 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
bogdanm 0:9b334a45a8ff 335 #endif /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F070x6)
bogdanm 0:9b334a45a8ff 338 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
bogdanm 0:9b334a45a8ff 339 /* Get the USB clock source ---------------------------------------------*/
bogdanm 0:9b334a45a8ff 340 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
bogdanm 0:9b334a45a8ff 341 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB || STM32F070x6 */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 #if defined(STM32F042x6) || defined(STM32F048xx)\
bogdanm 0:9b334a45a8ff 344 || defined(STM32F051x8) || defined(STM32F058xx)\
bogdanm 0:9b334a45a8ff 345 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
bogdanm 0:9b334a45a8ff 346 || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 347 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
bogdanm 0:9b334a45a8ff 348 /* Get the CEC clock source ------------------------------------------------*/
bogdanm 0:9b334a45a8ff 349 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
bogdanm 0:9b334a45a8ff 350 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 0:9b334a45a8ff 351 /* STM32F051x8 || STM32F058xx || */
bogdanm 0:9b334a45a8ff 352 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 0:9b334a45a8ff 353 /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 /**
bogdanm 0:9b334a45a8ff 358 * @brief Returns the peripheral clock frequency
bogdanm 0:9b334a45a8ff 359 * @note Returns 0 if peripheral clock is unknown
bogdanm 0:9b334a45a8ff 360 * @param PeriphClk: Peripheral clock identifier
bogdanm 0:9b334a45a8ff 361 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 362 * @arg RCC_PERIPHCLK_RTC RTC peripheral clock
bogdanm 0:9b334a45a8ff 363 * @arg RCC_PERIPHCLK_USART1 USART1 peripheral clock
bogdanm 0:9b334a45a8ff 364 * @arg RCC_PERIPHCLK_USART2 USART2 peripheral clock (*)
bogdanm 0:9b334a45a8ff 365 * @arg RCC_PERIPHCLK_USART3 USART3 peripheral clock (*)
bogdanm 0:9b334a45a8ff 366 * @arg RCC_PERIPHCLK_I2C1 I2C1 peripheral clock
bogdanm 0:9b334a45a8ff 367 * @arg RCC_PERIPHCLK_USB USB peripheral clock (*)
bogdanm 0:9b334a45a8ff 368 * @arg RCC_PERIPHCLK_CEC CEC peripheral clock (*)
bogdanm 0:9b334a45a8ff 369 * @note (*) means that this peripheral is not present on all the STM32F0xx devices
bogdanm 0:9b334a45a8ff 370 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
bogdanm 0:9b334a45a8ff 371 */
bogdanm 0:9b334a45a8ff 372 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
bogdanm 0:9b334a45a8ff 373 {
bogdanm 0:9b334a45a8ff 374 uint32_t frequency = 0;
bogdanm 0:9b334a45a8ff 375 uint32_t srcclk = 0;
bogdanm 0:9b334a45a8ff 376 #if defined(USB)
bogdanm 0:9b334a45a8ff 377 uint32_t pllmull = 0, pllsource = 0, predivfactor = 0;
bogdanm 0:9b334a45a8ff 378 #endif /* USB */
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 /* Check the parameters */
bogdanm 0:9b334a45a8ff 381 assert_param(IS_RCC_PERIPHCLK(PeriphClk));
bogdanm 0:9b334a45a8ff 382
bogdanm 0:9b334a45a8ff 383 switch (PeriphClk)
bogdanm 0:9b334a45a8ff 384 {
bogdanm 0:9b334a45a8ff 385 case RCC_PERIPHCLK_RTC:
bogdanm 0:9b334a45a8ff 386 {
bogdanm 0:9b334a45a8ff 387 /* Get the current RTC source */
bogdanm 0:9b334a45a8ff 388 srcclk = __HAL_RCC_GET_RTC_SOURCE();
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 /* Check if LSE is ready and if RTC clock selection is LSE */
bogdanm 0:9b334a45a8ff 391 if ((srcclk == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 392 {
bogdanm 0:9b334a45a8ff 393 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 394 }
bogdanm 0:9b334a45a8ff 395 /* Check if LSI is ready and if RTC clock selection is LSI */
bogdanm 0:9b334a45a8ff 396 else if ((srcclk == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
bogdanm 0:9b334a45a8ff 397 {
bogdanm 0:9b334a45a8ff 398 frequency = LSI_VALUE;
bogdanm 0:9b334a45a8ff 399 }
bogdanm 0:9b334a45a8ff 400 /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/
bogdanm 0:9b334a45a8ff 401 else if ((srcclk == RCC_RTCCLKSOURCE_HSE_DIV32) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
bogdanm 0:9b334a45a8ff 402 {
bogdanm 0:9b334a45a8ff 403 frequency = HSE_VALUE / 32;
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 /* Clock not enabled for RTC*/
bogdanm 0:9b334a45a8ff 406 else
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 frequency = 0;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410 break;
bogdanm 0:9b334a45a8ff 411 }
bogdanm 0:9b334a45a8ff 412 case RCC_PERIPHCLK_USART1:
bogdanm 0:9b334a45a8ff 413 {
bogdanm 0:9b334a45a8ff 414 /* Get the current USART1 source */
bogdanm 0:9b334a45a8ff 415 srcclk = __HAL_RCC_GET_USART1_SOURCE();
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 /* Check if USART1 clock selection is PCLK1 */
bogdanm 0:9b334a45a8ff 418 if (srcclk == RCC_USART1CLKSOURCE_PCLK1)
bogdanm 0:9b334a45a8ff 419 {
bogdanm 0:9b334a45a8ff 420 frequency = HAL_RCC_GetPCLK1Freq();
bogdanm 0:9b334a45a8ff 421 }
bogdanm 0:9b334a45a8ff 422 /* Check if HSI is ready and if USART1 clock selection is HSI */
bogdanm 0:9b334a45a8ff 423 else if ((srcclk == RCC_USART1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
bogdanm 0:9b334a45a8ff 424 {
bogdanm 0:9b334a45a8ff 425 frequency = HSI_VALUE;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427 /* Check if USART1 clock selection is SYSCLK */
bogdanm 0:9b334a45a8ff 428 else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 429 {
bogdanm 0:9b334a45a8ff 430 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 431 }
bogdanm 0:9b334a45a8ff 432 /* Check if LSE is ready and if USART1 clock selection is LSE */
bogdanm 0:9b334a45a8ff 433 else if ((srcclk == RCC_USART1CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 434 {
bogdanm 0:9b334a45a8ff 435 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 436 }
bogdanm 0:9b334a45a8ff 437 /* Clock not enabled for USART1*/
bogdanm 0:9b334a45a8ff 438 else
bogdanm 0:9b334a45a8ff 439 {
bogdanm 0:9b334a45a8ff 440 frequency = 0;
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442 break;
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 #if defined(RCC_CFGR3_USART2SW)
bogdanm 0:9b334a45a8ff 445 case RCC_PERIPHCLK_USART2:
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 /* Get the current USART2 source */
bogdanm 0:9b334a45a8ff 448 srcclk = __HAL_RCC_GET_USART2_SOURCE();
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Check if USART2 clock selection is PCLK1 */
bogdanm 0:9b334a45a8ff 451 if (srcclk == RCC_USART2CLKSOURCE_PCLK1)
bogdanm 0:9b334a45a8ff 452 {
bogdanm 0:9b334a45a8ff 453 frequency = HAL_RCC_GetPCLK1Freq();
bogdanm 0:9b334a45a8ff 454 }
bogdanm 0:9b334a45a8ff 455 /* Check if HSI is ready and if USART2 clock selection is HSI */
bogdanm 0:9b334a45a8ff 456 else if ((srcclk == RCC_USART2CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
bogdanm 0:9b334a45a8ff 457 {
bogdanm 0:9b334a45a8ff 458 frequency = HSI_VALUE;
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460 /* Check if USART2 clock selection is SYSCLK */
bogdanm 0:9b334a45a8ff 461 else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 462 {
bogdanm 0:9b334a45a8ff 463 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 464 }
bogdanm 0:9b334a45a8ff 465 /* Check if LSE is ready and if USART2 clock selection is LSE */
bogdanm 0:9b334a45a8ff 466 else if ((srcclk == RCC_USART2CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 467 {
bogdanm 0:9b334a45a8ff 468 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 469 }
bogdanm 0:9b334a45a8ff 470 /* Clock not enabled for USART2*/
bogdanm 0:9b334a45a8ff 471 else
bogdanm 0:9b334a45a8ff 472 {
bogdanm 0:9b334a45a8ff 473 frequency = 0;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475 break;
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477 #endif /* RCC_CFGR3_USART2SW */
bogdanm 0:9b334a45a8ff 478 #if defined(RCC_CFGR3_USART3SW)
bogdanm 0:9b334a45a8ff 479 case RCC_PERIPHCLK_USART3:
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 /* Get the current USART3 source */
bogdanm 0:9b334a45a8ff 482 srcclk = __HAL_RCC_GET_USART3_SOURCE();
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Check if USART3 clock selection is PCLK1 */
bogdanm 0:9b334a45a8ff 485 if (srcclk == RCC_USART3CLKSOURCE_PCLK1)
bogdanm 0:9b334a45a8ff 486 {
bogdanm 0:9b334a45a8ff 487 frequency = HAL_RCC_GetPCLK1Freq();
bogdanm 0:9b334a45a8ff 488 }
bogdanm 0:9b334a45a8ff 489 /* Check if HSI is ready and if USART3 clock selection is HSI */
bogdanm 0:9b334a45a8ff 490 else if ((srcclk == RCC_USART3CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
bogdanm 0:9b334a45a8ff 491 {
bogdanm 0:9b334a45a8ff 492 frequency = HSI_VALUE;
bogdanm 0:9b334a45a8ff 493 }
bogdanm 0:9b334a45a8ff 494 /* Check if USART3 clock selection is SYSCLK */
bogdanm 0:9b334a45a8ff 495 else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 496 {
bogdanm 0:9b334a45a8ff 497 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 498 }
bogdanm 0:9b334a45a8ff 499 /* Check if LSE is ready and if USART3 clock selection is LSE */
bogdanm 0:9b334a45a8ff 500 else if ((srcclk == RCC_USART3CLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 /* Clock not enabled for USART3*/
bogdanm 0:9b334a45a8ff 505 else
bogdanm 0:9b334a45a8ff 506 {
bogdanm 0:9b334a45a8ff 507 frequency = 0;
bogdanm 0:9b334a45a8ff 508 }
bogdanm 0:9b334a45a8ff 509 break;
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511 #endif /* RCC_CFGR3_USART3SW */
bogdanm 0:9b334a45a8ff 512 case RCC_PERIPHCLK_I2C1:
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 /* Get the current I2C1 source */
bogdanm 0:9b334a45a8ff 515 srcclk = __HAL_RCC_GET_I2C1_SOURCE();
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517 /* Check if HSI is ready and if I2C1 clock selection is HSI */
bogdanm 0:9b334a45a8ff 518 if ((srcclk == RCC_I2C1CLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
bogdanm 0:9b334a45a8ff 519 {
bogdanm 0:9b334a45a8ff 520 frequency = HSI_VALUE;
bogdanm 0:9b334a45a8ff 521 }
bogdanm 0:9b334a45a8ff 522 /* Check if I2C1 clock selection is SYSCLK */
bogdanm 0:9b334a45a8ff 523 else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 524 {
bogdanm 0:9b334a45a8ff 525 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 526 }
bogdanm 0:9b334a45a8ff 527 /* Clock not enabled for I2C1*/
bogdanm 0:9b334a45a8ff 528 else
bogdanm 0:9b334a45a8ff 529 {
bogdanm 0:9b334a45a8ff 530 frequency = 0;
bogdanm 0:9b334a45a8ff 531 }
bogdanm 0:9b334a45a8ff 532 break;
bogdanm 0:9b334a45a8ff 533 }
bogdanm 0:9b334a45a8ff 534 #if defined(USB)
bogdanm 0:9b334a45a8ff 535 case RCC_PERIPHCLK_USB:
bogdanm 0:9b334a45a8ff 536 {
bogdanm 0:9b334a45a8ff 537 /* Get the current USB source */
bogdanm 0:9b334a45a8ff 538 srcclk = __HAL_RCC_GET_USB_SOURCE();
bogdanm 0:9b334a45a8ff 539
bogdanm 0:9b334a45a8ff 540 /* Check if PLL is ready and if USB clock selection is PLL */
bogdanm 0:9b334a45a8ff 541 if ((srcclk == RCC_USBCLKSOURCE_PLLCLK) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLLRDY)))
bogdanm 0:9b334a45a8ff 542 {
bogdanm 0:9b334a45a8ff 543 /* Get PLL clock source and multiplication factor ----------------------*/
bogdanm 0:9b334a45a8ff 544 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
bogdanm 0:9b334a45a8ff 545 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
bogdanm 0:9b334a45a8ff 546 pllmull = (pllmull >> RCC_CFGR_PLLMUL_BITNUMBER) + 2;
bogdanm 0:9b334a45a8ff 547 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
bogdanm 0:9b334a45a8ff 550 {
bogdanm 0:9b334a45a8ff 551 /* HSE used as PLL clock source : frequency = HSE/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 552 frequency = (HSE_VALUE/predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 553 }
bogdanm 0:9b334a45a8ff 554 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 555 else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
bogdanm 0:9b334a45a8ff 556 {
bogdanm 0:9b334a45a8ff 557 /* HSI48 used as PLL clock source : frequency = HSI48/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 558 frequency = (HSI48_VALUE / predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 559 }
bogdanm 0:9b334a45a8ff 560 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 561 else
bogdanm 0:9b334a45a8ff 562 {
bogdanm 0:9b334a45a8ff 563 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F072xB) || defined(STM32F070xB)
bogdanm 0:9b334a45a8ff 564 /* HSI used as PLL clock source : frequency = HSI/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 565 frequency = (HSI_VALUE / predivfactor) * pllmull;
bogdanm 0:9b334a45a8ff 566 #else
bogdanm 0:9b334a45a8ff 567 /* HSI used as PLL clock source : frequency = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 568 frequency = (HSI_VALUE >> 1) * pllmull;
bogdanm 0:9b334a45a8ff 569 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F070xB */
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571 }
bogdanm 0:9b334a45a8ff 572 #if defined(RCC_CR2_HSI48ON)
bogdanm 0:9b334a45a8ff 573 /* Check if HSI48 is ready and if USB clock selection is HSI48 */
bogdanm 0:9b334a45a8ff 574 else if ((srcclk == RCC_USBCLKSOURCE_HSI48) && (HAL_IS_BIT_SET(RCC->CR2, RCC_CR2_HSI48RDY)))
bogdanm 0:9b334a45a8ff 575 {
bogdanm 0:9b334a45a8ff 576 frequency = HSI48_VALUE;
bogdanm 0:9b334a45a8ff 577 }
bogdanm 0:9b334a45a8ff 578 #endif /* RCC_CR2_HSI48ON */
bogdanm 0:9b334a45a8ff 579 /* Clock not enabled for USB*/
bogdanm 0:9b334a45a8ff 580 else
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 frequency = 0;
bogdanm 0:9b334a45a8ff 583 }
bogdanm 0:9b334a45a8ff 584 break;
bogdanm 0:9b334a45a8ff 585 }
bogdanm 0:9b334a45a8ff 586 #endif /* USB */
bogdanm 0:9b334a45a8ff 587 #if defined(CEC)
bogdanm 0:9b334a45a8ff 588 case RCC_PERIPHCLK_CEC:
bogdanm 0:9b334a45a8ff 589 {
bogdanm 0:9b334a45a8ff 590 /* Get the current CEC source */
bogdanm 0:9b334a45a8ff 591 srcclk = __HAL_RCC_GET_CEC_SOURCE();
bogdanm 0:9b334a45a8ff 592
bogdanm 0:9b334a45a8ff 593 /* Check if HSI is ready and if CEC clock selection is HSI */
bogdanm 0:9b334a45a8ff 594 if ((srcclk == RCC_CECCLKSOURCE_HSI) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)))
bogdanm 0:9b334a45a8ff 595 {
bogdanm 0:9b334a45a8ff 596 frequency = HSI_VALUE;
bogdanm 0:9b334a45a8ff 597 }
bogdanm 0:9b334a45a8ff 598 /* Check if LSE is ready and if CEC clock selection is LSE */
bogdanm 0:9b334a45a8ff 599 else if ((srcclk == RCC_CECCLKSOURCE_LSE) && (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 600 {
bogdanm 0:9b334a45a8ff 601 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 602 }
bogdanm 0:9b334a45a8ff 603 /* Clock not enabled for CEC */
bogdanm 0:9b334a45a8ff 604 else
bogdanm 0:9b334a45a8ff 605 {
bogdanm 0:9b334a45a8ff 606 frequency = 0;
bogdanm 0:9b334a45a8ff 607 }
bogdanm 0:9b334a45a8ff 608 break;
bogdanm 0:9b334a45a8ff 609 }
bogdanm 0:9b334a45a8ff 610 #endif /* CEC */
bogdanm 0:9b334a45a8ff 611 default:
bogdanm 0:9b334a45a8ff 612 {
bogdanm 0:9b334a45a8ff 613 break;
bogdanm 0:9b334a45a8ff 614 }
bogdanm 0:9b334a45a8ff 615 }
bogdanm 0:9b334a45a8ff 616 return(frequency);
bogdanm 0:9b334a45a8ff 617 }
bogdanm 0:9b334a45a8ff 618
bogdanm 0:9b334a45a8ff 619 #if defined(STM32F042x6) || defined(STM32F048xx)\
bogdanm 0:9b334a45a8ff 620 || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)\
bogdanm 0:9b334a45a8ff 621 || defined(STM32F091xC) || defined(STM32F098xx)
bogdanm 0:9b334a45a8ff 622 /**
bogdanm 0:9b334a45a8ff 623 * @brief Start automatic synchronization using polling mode
bogdanm 0:9b334a45a8ff 624 * @param pInit Pointer on RCC_CRSInitTypeDef structure
bogdanm 0:9b334a45a8ff 625 * @retval None
bogdanm 0:9b334a45a8ff 626 */
bogdanm 0:9b334a45a8ff 627 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit)
bogdanm 0:9b334a45a8ff 628 {
bogdanm 0:9b334a45a8ff 629 /* Check the parameters */
bogdanm 0:9b334a45a8ff 630 assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler));
bogdanm 0:9b334a45a8ff 631 assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source));
bogdanm 0:9b334a45a8ff 632 assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity));
bogdanm 0:9b334a45a8ff 633 assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue));
bogdanm 0:9b334a45a8ff 634 assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue));
bogdanm 0:9b334a45a8ff 635 assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue));
bogdanm 0:9b334a45a8ff 636
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638 /* CONFIGURATION */
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 /* Before configuration, reset CRS registers to their default values*/
bogdanm 0:9b334a45a8ff 641 __HAL_RCC_CRS_FORCE_RESET();
bogdanm 0:9b334a45a8ff 642 __HAL_RCC_CRS_RELEASE_RESET();
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* Configure Synchronization input */
bogdanm 0:9b334a45a8ff 645 /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */
bogdanm 0:9b334a45a8ff 646 CRS->CFGR &= ~(CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL);
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to Prescaler value */
bogdanm 0:9b334a45a8ff 649 CRS->CFGR |= pInit->Prescaler;
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 /* Set the SYNCSRC[1:0] bits according to Source value */
bogdanm 0:9b334a45a8ff 652 CRS->CFGR |= pInit->Source;
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Set the SYNCSPOL bits according to Polarity value */
bogdanm 0:9b334a45a8ff 655 CRS->CFGR |= pInit->Polarity;
bogdanm 0:9b334a45a8ff 656
bogdanm 0:9b334a45a8ff 657 /* Configure Frequency Error Measurement */
bogdanm 0:9b334a45a8ff 658 /* Clear RELOAD[15:0] & FELIM[7:0] bits*/
bogdanm 0:9b334a45a8ff 659 CRS->CFGR &= ~(CRS_CFGR_RELOAD | CRS_CFGR_FELIM);
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /* Set the RELOAD[15:0] bits according to ReloadValue value */
bogdanm 0:9b334a45a8ff 662 CRS->CFGR |= pInit->ReloadValue;
bogdanm 0:9b334a45a8ff 663
bogdanm 0:9b334a45a8ff 664 /* Set the FELIM[7:0] bits according to ErrorLimitValue value */
bogdanm 0:9b334a45a8ff 665 CRS->CFGR |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_BITNUMBER);
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /* Adjust HSI48 oscillator smooth trimming */
bogdanm 0:9b334a45a8ff 668 /* Clear TRIM[5:0] bits */
bogdanm 0:9b334a45a8ff 669 CRS->CR &= ~CRS_CR_TRIM;
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */
bogdanm 0:9b334a45a8ff 672 CRS->CR |= (pInit->HSI48CalibrationValue << CRS_CR_TRIM_BITNUMBER);
bogdanm 0:9b334a45a8ff 673
bogdanm 0:9b334a45a8ff 674
bogdanm 0:9b334a45a8ff 675 /* START AUTOMATIC SYNCHRONIZATION*/
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 /* Enable Automatic trimming */
bogdanm 0:9b334a45a8ff 678 __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB();
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 /* Enable Frequency error counter */
bogdanm 0:9b334a45a8ff 681 __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER();
bogdanm 0:9b334a45a8ff 682
bogdanm 0:9b334a45a8ff 683 }
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 /**
bogdanm 0:9b334a45a8ff 686 * @brief Generate the software synchronization event
bogdanm 0:9b334a45a8ff 687 * @retval None
bogdanm 0:9b334a45a8ff 688 */
bogdanm 0:9b334a45a8ff 689 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void)
bogdanm 0:9b334a45a8ff 690 {
bogdanm 0:9b334a45a8ff 691 CRS->CR |= CRS_CR_SWSYNC;
bogdanm 0:9b334a45a8ff 692 }
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694
bogdanm 0:9b334a45a8ff 695 /**
bogdanm 0:9b334a45a8ff 696 * @brief Function to return synchronization info
bogdanm 0:9b334a45a8ff 697 * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure
bogdanm 0:9b334a45a8ff 698 * @retval None
bogdanm 0:9b334a45a8ff 699 */
bogdanm 0:9b334a45a8ff 700 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo)
bogdanm 0:9b334a45a8ff 701 {
bogdanm 0:9b334a45a8ff 702 /* Check the parameter */
bogdanm 0:9b334a45a8ff 703 assert_param(pSynchroInfo != NULL);
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 /* Get the reload value */
bogdanm 0:9b334a45a8ff 706 pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD);
bogdanm 0:9b334a45a8ff 707
bogdanm 0:9b334a45a8ff 708 /* Get HSI48 oscillator smooth trimming */
bogdanm 0:9b334a45a8ff 709 pSynchroInfo->HSI48CalibrationValue = (uint32_t)((CRS->CR & CRS_CR_TRIM) >> CRS_CR_TRIM_BITNUMBER);
bogdanm 0:9b334a45a8ff 710
bogdanm 0:9b334a45a8ff 711 /* Get Frequency error capture */
bogdanm 0:9b334a45a8ff 712 pSynchroInfo->FreqErrorCapture = (uint32_t)((CRS->ISR & CRS_ISR_FECAP) >> CRS_ISR_FECAP_BITNUMBER);
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 /* Get FFrequency error direction */
bogdanm 0:9b334a45a8ff 715 pSynchroInfo->FreqErrorDirection = (uint32_t)(CRS->ISR & CRS_ISR_FEDIR);
bogdanm 0:9b334a45a8ff 716
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 }
bogdanm 0:9b334a45a8ff 719
bogdanm 0:9b334a45a8ff 720 /**
bogdanm 0:9b334a45a8ff 721 * @brief This function handles CRS Synchronization Timeout.
bogdanm 0:9b334a45a8ff 722 * @param Timeout: Duration of the timeout
bogdanm 0:9b334a45a8ff 723 * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization
bogdanm 0:9b334a45a8ff 724 * frequency.
bogdanm 0:9b334a45a8ff 725 * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned.
bogdanm 0:9b334a45a8ff 726 * @retval Combination of Synchronization status
bogdanm 0:9b334a45a8ff 727 * This parameter can be a combination of the following values:
bogdanm 0:9b334a45a8ff 728 * @arg RCC_CRS_TIMEOUT
bogdanm 0:9b334a45a8ff 729 * @arg RCC_CRS_SYNCOK
bogdanm 0:9b334a45a8ff 730 * @arg RCC_CRS_SYNCWARM
bogdanm 0:9b334a45a8ff 731 * @arg RCC_CRS_SYNCERR
bogdanm 0:9b334a45a8ff 732 * @arg RCC_CRS_SYNCMISS
bogdanm 0:9b334a45a8ff 733 * @arg RCC_CRS_TRIMOV
bogdanm 0:9b334a45a8ff 734 */
bogdanm 0:9b334a45a8ff 735 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
bogdanm 0:9b334a45a8ff 736 {
bogdanm 0:9b334a45a8ff 737 uint32_t crsstatus = RCC_CRS_NONE;
bogdanm 0:9b334a45a8ff 738 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 739
bogdanm 0:9b334a45a8ff 740 /* Get timeout */
bogdanm 0:9b334a45a8ff 741 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 742
bogdanm 0:9b334a45a8ff 743 /* Check that if one of CRS flags have been set */
bogdanm 0:9b334a45a8ff 744 while(RCC_CRS_NONE == crsstatus)
bogdanm 0:9b334a45a8ff 745 {
bogdanm 0:9b334a45a8ff 746 if(Timeout != HAL_MAX_DELAY)
bogdanm 0:9b334a45a8ff 747 {
bogdanm 0:9b334a45a8ff 748 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
bogdanm 0:9b334a45a8ff 749 {
bogdanm 0:9b334a45a8ff 750 crsstatus = RCC_CRS_TIMEOUT;
bogdanm 0:9b334a45a8ff 751 }
bogdanm 0:9b334a45a8ff 752 }
bogdanm 0:9b334a45a8ff 753 /* Check CRS SYNCOK flag */
bogdanm 0:9b334a45a8ff 754 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK))
bogdanm 0:9b334a45a8ff 755 {
bogdanm 0:9b334a45a8ff 756 /* CRS SYNC event OK */
bogdanm 0:9b334a45a8ff 757 crsstatus |= RCC_CRS_SYNCOK;
bogdanm 0:9b334a45a8ff 758
bogdanm 0:9b334a45a8ff 759 /* Clear CRS SYNC event OK bit */
bogdanm 0:9b334a45a8ff 760 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK);
bogdanm 0:9b334a45a8ff 761 }
bogdanm 0:9b334a45a8ff 762
bogdanm 0:9b334a45a8ff 763 /* Check CRS SYNCWARN flag */
bogdanm 0:9b334a45a8ff 764 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN))
bogdanm 0:9b334a45a8ff 765 {
bogdanm 0:9b334a45a8ff 766 /* CRS SYNC warning */
bogdanm 0:9b334a45a8ff 767 crsstatus |= RCC_CRS_SYNCWARM;
bogdanm 0:9b334a45a8ff 768
bogdanm 0:9b334a45a8ff 769 /* Clear CRS SYNCWARN bit */
bogdanm 0:9b334a45a8ff 770 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN);
bogdanm 0:9b334a45a8ff 771 }
bogdanm 0:9b334a45a8ff 772
bogdanm 0:9b334a45a8ff 773 /* Check CRS TRIM overflow flag */
bogdanm 0:9b334a45a8ff 774 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF))
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776 /* CRS SYNC Error */
bogdanm 0:9b334a45a8ff 777 crsstatus |= RCC_CRS_TRIMOV;
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /* Clear CRS Error bit */
bogdanm 0:9b334a45a8ff 780 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF);
bogdanm 0:9b334a45a8ff 781 }
bogdanm 0:9b334a45a8ff 782
bogdanm 0:9b334a45a8ff 783 /* Check CRS Error flag */
bogdanm 0:9b334a45a8ff 784 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR))
bogdanm 0:9b334a45a8ff 785 {
bogdanm 0:9b334a45a8ff 786 /* CRS SYNC Error */
bogdanm 0:9b334a45a8ff 787 crsstatus |= RCC_CRS_SYNCERR;
bogdanm 0:9b334a45a8ff 788
bogdanm 0:9b334a45a8ff 789 /* Clear CRS Error bit */
bogdanm 0:9b334a45a8ff 790 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR);
bogdanm 0:9b334a45a8ff 791 }
bogdanm 0:9b334a45a8ff 792
bogdanm 0:9b334a45a8ff 793 /* Check CRS SYNC Missed flag */
bogdanm 0:9b334a45a8ff 794 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS))
bogdanm 0:9b334a45a8ff 795 {
bogdanm 0:9b334a45a8ff 796 /* CRS SYNC Missed */
bogdanm 0:9b334a45a8ff 797 crsstatus |= RCC_CRS_SYNCMISS;
bogdanm 0:9b334a45a8ff 798
bogdanm 0:9b334a45a8ff 799 /* Clear CRS SYNC Missed bit */
bogdanm 0:9b334a45a8ff 800 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS);
bogdanm 0:9b334a45a8ff 801 }
bogdanm 0:9b334a45a8ff 802
bogdanm 0:9b334a45a8ff 803 /* Check CRS Expected SYNC flag */
bogdanm 0:9b334a45a8ff 804 if(__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC))
bogdanm 0:9b334a45a8ff 805 {
bogdanm 0:9b334a45a8ff 806 /* frequency error counter reached a zero value */
bogdanm 0:9b334a45a8ff 807 __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC);
bogdanm 0:9b334a45a8ff 808 }
bogdanm 0:9b334a45a8ff 809 }
bogdanm 0:9b334a45a8ff 810
bogdanm 0:9b334a45a8ff 811 return crsstatus;
bogdanm 0:9b334a45a8ff 812 }
bogdanm 0:9b334a45a8ff 813
bogdanm 0:9b334a45a8ff 814 #endif /* STM32F042x6 || STM32F048xx || */
bogdanm 0:9b334a45a8ff 815 /* STM32F071xB || STM32F072xB || STM32F078xx || */
bogdanm 0:9b334a45a8ff 816 /* STM32F091xC || STM32F098xx */
bogdanm 0:9b334a45a8ff 817
bogdanm 0:9b334a45a8ff 818 /**
bogdanm 0:9b334a45a8ff 819 * @}
bogdanm 0:9b334a45a8ff 820 */
bogdanm 0:9b334a45a8ff 821
bogdanm 0:9b334a45a8ff 822 /**
bogdanm 0:9b334a45a8ff 823 * @}
bogdanm 0:9b334a45a8ff 824 */
bogdanm 0:9b334a45a8ff 825
bogdanm 0:9b334a45a8ff 826 /**
bogdanm 0:9b334a45a8ff 827 * @}
bogdanm 0:9b334a45a8ff 828 */
bogdanm 0:9b334a45a8ff 829
bogdanm 0:9b334a45a8ff 830 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 831
bogdanm 0:9b334a45a8ff 832 /**
bogdanm 0:9b334a45a8ff 833 * @}
bogdanm 0:9b334a45a8ff 834 */
bogdanm 0:9b334a45a8ff 835
bogdanm 0:9b334a45a8ff 836 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/