mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/cmsis_nvic.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * CMSIS-style functionality to support dynamic vectors
bogdanm 0:9b334a45a8ff 3 *******************************************************************************
bogdanm 0:9b334a45a8ff 4 * Copyright (c) 2011 ARM Limited. All rights reserved.
bogdanm 0:9b334a45a8ff 5 * All rights reserved.
bogdanm 0:9b334a45a8ff 6 *
bogdanm 0:9b334a45a8ff 7 * Redistribution and use in source and binary forms, with or without
bogdanm 0:9b334a45a8ff 8 * modification, are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 11 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 13 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 14 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 15 * 3. Neither the name of ARM Limited nor the names of its contributors
bogdanm 0:9b334a45a8ff 16 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 17 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 18 *
bogdanm 0:9b334a45a8ff 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 29 *******************************************************************************
bogdanm 0:9b334a45a8ff 30 */
bogdanm 0:9b334a45a8ff 31 #include "cmsis_nvic.h"
bogdanm 0:9b334a45a8ff 32
bogdanm 0:9b334a45a8ff 33 /* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
bogdanm 0:9b334a45a8ff 34 * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
bogdanm 0:9b334a45a8ff 35 * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
bogdanm 0:9b334a45a8ff 36 * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
bogdanm 0:9b334a45a8ff 37 *
bogdanm 0:9b334a45a8ff 38 * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
bogdanm 0:9b334a45a8ff 39 * above the vector table before 0x200 will actually go to RAM. So we need to provide
bogdanm 0:9b334a45a8ff 40 * a solution where the compiler gets the right results based on the memory map
bogdanm 0:9b334a45a8ff 41 *
bogdanm 0:9b334a45a8ff 42 * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
bogdanm 0:9b334a45a8ff 43 * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
bogdanm 0:9b334a45a8ff 44 * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
bogdanm 0:9b334a45a8ff 45 *
bogdanm 0:9b334a45a8ff 46 * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
bogdanm 0:9b334a45a8ff 47 * - No flash accesses will go to ram, as there will be nothing there
bogdanm 0:9b334a45a8ff 48 * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
bogdanm 0:9b334a45a8ff 49 * - RAM overhead: 0, FLASH overhead: 320 bytes
bogdanm 0:9b334a45a8ff 50 *
bogdanm 0:9b334a45a8ff 51 * Option 2 is the one to go for, as RAM is the most valuable resource
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 #define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
bogdanm 0:9b334a45a8ff 57 int i;
bogdanm 0:9b334a45a8ff 58 // Space for dynamic vectors, initialised to allocate in R/W
bogdanm 0:9b334a45a8ff 59 static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
bogdanm 0:9b334a45a8ff 60
bogdanm 0:9b334a45a8ff 61 // Copy and switch to dynamic vectors if first time called
bogdanm 0:9b334a45a8ff 62 if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
bogdanm 0:9b334a45a8ff 63 uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
bogdanm 0:9b334a45a8ff 64 for(i = 0; i < NVIC_NUM_VECTORS; i++) {
bogdanm 0:9b334a45a8ff 65 vectors[i] = old_vectors[i];
bogdanm 0:9b334a45a8ff 66 }
bogdanm 0:9b334a45a8ff 67 LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
bogdanm 0:9b334a45a8ff 68 }
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 // Set the vector
bogdanm 0:9b334a45a8ff 71 vectors[IRQn + 16] = vector;
bogdanm 0:9b334a45a8ff 72 }
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 uint32_t NVIC_GetVector(IRQn_Type IRQn) {
bogdanm 0:9b334a45a8ff 75 // We can always read vectors at 0x0, as the addresses are remapped
bogdanm 0:9b334a45a8ff 76 uint32_t *vectors = (uint32_t*)0;
bogdanm 0:9b334a45a8ff 77
bogdanm 0:9b334a45a8ff 78 // Return the vector
bogdanm 0:9b334a45a8ff 79 return vectors[IRQn + 16];
bogdanm 0:9b334a45a8ff 80 }
bogdanm 0:9b334a45a8ff 81