mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c@180:96ed750bd169, 2018-01-17 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed Jan 17 15:23:54 2018 +0000
- Revision:
- 180:96ed750bd169
- Parent:
- 156:95d6b41a828b
mbed-dev libray. Release version 158
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_i2c.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @brief I2C HAL module driver. |
<> | 156:95d6b41a828b | 6 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
<> | 144:ef7eb2e8f9f7 | 8 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 9 | * + IO operation functions |
<> | 144:ef7eb2e8f9f7 | 10 | * + Peripheral State and Errors functions |
<> | 156:95d6b41a828b | 11 | * |
<> | 144:ef7eb2e8f9f7 | 12 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 13 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 14 | ##### How to use this driver ##### |
<> | 144:ef7eb2e8f9f7 | 15 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 16 | [..] |
<> | 144:ef7eb2e8f9f7 | 17 | The I2C HAL driver can be used as follows: |
<> | 156:95d6b41a828b | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
<> | 156:95d6b41a828b | 20 | I2C_HandleTypeDef hi2c; |
<> | 144:ef7eb2e8f9f7 | 21 | |
<> | 144:ef7eb2e8f9f7 | 22 | (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: |
<> | 144:ef7eb2e8f9f7 | 23 | (##) Enable the I2Cx interface clock |
<> | 144:ef7eb2e8f9f7 | 24 | (##) I2C pins configuration |
<> | 144:ef7eb2e8f9f7 | 25 | (+++) Enable the clock for the I2C GPIOs |
<> | 144:ef7eb2e8f9f7 | 26 | (+++) Configure I2C pins as alternate function open-drain |
<> | 144:ef7eb2e8f9f7 | 27 | (##) NVIC configuration if you need to use interrupt process |
<> | 144:ef7eb2e8f9f7 | 28 | (+++) Configure the I2Cx interrupt priority |
<> | 144:ef7eb2e8f9f7 | 29 | (+++) Enable the NVIC I2C IRQ Channel |
<> | 144:ef7eb2e8f9f7 | 30 | (##) DMA Configuration if you need to use DMA process |
<> | 144:ef7eb2e8f9f7 | 31 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
<> | 144:ef7eb2e8f9f7 | 32 | (+++) Enable the DMAx interface clock using |
<> | 144:ef7eb2e8f9f7 | 33 | (+++) Configure the DMA handle parameters |
<> | 144:ef7eb2e8f9f7 | 34 | (+++) Configure the DMA Tx or Rx channel |
<> | 144:ef7eb2e8f9f7 | 35 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
<> | 156:95d6b41a828b | 36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
<> | 144:ef7eb2e8f9f7 | 37 | the DMA Tx or Rx channel |
<> | 144:ef7eb2e8f9f7 | 38 | |
<> | 144:ef7eb2e8f9f7 | 39 | (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, |
<> | 144:ef7eb2e8f9f7 | 40 | Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. |
<> | 144:ef7eb2e8f9f7 | 41 | |
<> | 156:95d6b41a828b | 42 | (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware |
<> | 144:ef7eb2e8f9f7 | 43 | (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. |
<> | 144:ef7eb2e8f9f7 | 44 | |
<> | 144:ef7eb2e8f9f7 | 45 | (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
<> | 144:ef7eb2e8f9f7 | 48 | |
<> | 144:ef7eb2e8f9f7 | 49 | *** Polling mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 50 | ================================= |
<> | 144:ef7eb2e8f9f7 | 51 | [..] |
<> | 144:ef7eb2e8f9f7 | 52 | (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() |
<> | 144:ef7eb2e8f9f7 | 53 | (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() |
<> | 144:ef7eb2e8f9f7 | 54 | (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() |
<> | 144:ef7eb2e8f9f7 | 55 | (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | *** Polling mode IO MEM operation *** |
<> | 144:ef7eb2e8f9f7 | 58 | ===================================== |
<> | 144:ef7eb2e8f9f7 | 59 | [..] |
<> | 144:ef7eb2e8f9f7 | 60 | (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() |
<> | 144:ef7eb2e8f9f7 | 61 | (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | |
<> | 144:ef7eb2e8f9f7 | 64 | *** Interrupt mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 65 | =================================== |
<> | 144:ef7eb2e8f9f7 | 66 | [..] |
<> | 144:ef7eb2e8f9f7 | 67 | (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 68 | (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 69 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 70 | (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 71 | (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 72 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 73 | (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 74 | (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 75 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 76 | (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 77 | (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 78 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 79 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 80 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 81 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
<> | 144:ef7eb2e8f9f7 | 82 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 83 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 84 | (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. |
<> | 144:ef7eb2e8f9f7 | 85 | This action will inform Master to generate a Stop condition to discard the communication. |
<> | 144:ef7eb2e8f9f7 | 86 | |
<> | 144:ef7eb2e8f9f7 | 87 | |
<> | 144:ef7eb2e8f9f7 | 88 | *** Interrupt mode IO sequential operation *** |
<> | 156:95d6b41a828b | 89 | ============================================== |
<> | 144:ef7eb2e8f9f7 | 90 | [..] |
<> | 144:ef7eb2e8f9f7 | 91 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
<> | 144:ef7eb2e8f9f7 | 92 | when a direction change during transfer |
<> | 144:ef7eb2e8f9f7 | 93 | [..] |
<> | 144:ef7eb2e8f9f7 | 94 | (+) A specific option field manage the different steps of a sequential transfer |
<> | 156:95d6b41a828b | 95 | (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below: |
<> | 144:ef7eb2e8f9f7 | 96 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode |
<> | 144:ef7eb2e8f9f7 | 97 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
<> | 144:ef7eb2e8f9f7 | 98 | and data to transfer without a final stop condition |
<> | 156:95d6b41a828b | 99 | (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address |
<> | 156:95d6b41a828b | 100 | and data to transfer without a final stop condition, an then permit a call the same master sequential interface |
<> | 156:95d6b41a828b | 101 | several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT()) |
<> | 144:ef7eb2e8f9f7 | 102 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
<> | 144:ef7eb2e8f9f7 | 103 | and with new data to transfer if the direction change or manage only the new data to transfer |
<> | 144:ef7eb2e8f9f7 | 104 | if no direction change and without a final stop condition in both cases |
<> | 144:ef7eb2e8f9f7 | 105 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
<> | 144:ef7eb2e8f9f7 | 106 | and with new data to transfer if the direction change or manage only the new data to transfer |
<> | 144:ef7eb2e8f9f7 | 107 | if no direction change and with a final stop condition in both cases |
<> | 144:ef7eb2e8f9f7 | 108 | |
<> | 144:ef7eb2e8f9f7 | 109 | (+) Differents sequential I2C interfaces are listed below: |
<> | 144:ef7eb2e8f9f7 | 110 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 111 | (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 112 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 113 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 114 | (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 115 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 116 | (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
<> | 144:ef7eb2e8f9f7 | 117 | (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 118 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 119 | (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() |
<> | 144:ef7eb2e8f9f7 | 120 | (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 121 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
<> | 144:ef7eb2e8f9f7 | 122 | (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 123 | add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 124 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 125 | (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 126 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 127 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 128 | (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 129 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 130 | (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 131 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 132 | (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
<> | 144:ef7eb2e8f9f7 | 133 | (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 134 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 135 | (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. |
<> | 144:ef7eb2e8f9f7 | 136 | This action will inform Master to generate a Stop condition to discard the communication. |
<> | 144:ef7eb2e8f9f7 | 137 | |
<> | 144:ef7eb2e8f9f7 | 138 | *** Interrupt mode IO MEM operation *** |
<> | 144:ef7eb2e8f9f7 | 139 | ======================================= |
<> | 144:ef7eb2e8f9f7 | 140 | [..] |
<> | 144:ef7eb2e8f9f7 | 141 | (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using |
<> | 144:ef7eb2e8f9f7 | 142 | HAL_I2C_Mem_Write_IT() |
<> | 144:ef7eb2e8f9f7 | 143 | (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 144 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 145 | (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using |
<> | 144:ef7eb2e8f9f7 | 146 | HAL_I2C_Mem_Read_IT() |
<> | 144:ef7eb2e8f9f7 | 147 | (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 148 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 149 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 150 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | *** DMA mode IO operation *** |
<> | 144:ef7eb2e8f9f7 | 153 | ============================== |
<> | 144:ef7eb2e8f9f7 | 154 | [..] |
<> | 144:ef7eb2e8f9f7 | 155 | (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using |
<> | 144:ef7eb2e8f9f7 | 156 | HAL_I2C_Master_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 157 | (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 158 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 159 | (+) Receive in master mode an amount of data in non-blocking mode (DMA) using |
<> | 144:ef7eb2e8f9f7 | 160 | HAL_I2C_Master_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 161 | (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 162 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 163 | (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using |
<> | 144:ef7eb2e8f9f7 | 164 | HAL_I2C_Slave_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 165 | (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 166 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 167 | (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using |
<> | 144:ef7eb2e8f9f7 | 168 | HAL_I2C_Slave_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 169 | (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 170 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 171 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 172 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 173 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
<> | 144:ef7eb2e8f9f7 | 174 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 175 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 176 | (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. |
<> | 144:ef7eb2e8f9f7 | 177 | This action will inform Master to generate a Stop condition to discard the communication. |
<> | 144:ef7eb2e8f9f7 | 178 | |
<> | 144:ef7eb2e8f9f7 | 179 | *** DMA mode IO MEM operation *** |
<> | 144:ef7eb2e8f9f7 | 180 | ================================= |
<> | 144:ef7eb2e8f9f7 | 181 | [..] |
<> | 144:ef7eb2e8f9f7 | 182 | (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using |
<> | 144:ef7eb2e8f9f7 | 183 | HAL_I2C_Mem_Write_DMA() |
<> | 144:ef7eb2e8f9f7 | 184 | (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 185 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 186 | (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using |
<> | 144:ef7eb2e8f9f7 | 187 | HAL_I2C_Mem_Read_DMA() |
<> | 144:ef7eb2e8f9f7 | 188 | (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can |
<> | 144:ef7eb2e8f9f7 | 189 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 190 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
<> | 144:ef7eb2e8f9f7 | 191 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | *** I2C HAL driver macros list *** |
<> | 144:ef7eb2e8f9f7 | 195 | ================================== |
<> | 144:ef7eb2e8f9f7 | 196 | [..] |
<> | 144:ef7eb2e8f9f7 | 197 | Below the list of most used macros in I2C HAL driver. |
<> | 144:ef7eb2e8f9f7 | 198 | |
<> | 156:95d6b41a828b | 199 | (+) __HAL_I2C_ENABLE: Enable the I2C peripheral |
<> | 156:95d6b41a828b | 200 | (+) __HAL_I2C_DISABLE: Disable the I2C peripheral |
<> | 144:ef7eb2e8f9f7 | 201 | (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode |
<> | 156:95d6b41a828b | 202 | (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not |
<> | 156:95d6b41a828b | 203 | (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag |
<> | 156:95d6b41a828b | 204 | (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
<> | 156:95d6b41a828b | 205 | (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
<> | 144:ef7eb2e8f9f7 | 206 | |
<> | 144:ef7eb2e8f9f7 | 207 | [..] |
<> | 144:ef7eb2e8f9f7 | 208 | (@) You can refer to the I2C HAL driver header file for more useful macros |
<> | 144:ef7eb2e8f9f7 | 209 | |
<> | 144:ef7eb2e8f9f7 | 210 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 211 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 212 | * @attention |
<> | 144:ef7eb2e8f9f7 | 213 | * |
<> | 144:ef7eb2e8f9f7 | 214 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 215 | * |
<> | 144:ef7eb2e8f9f7 | 216 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 217 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 218 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 219 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 220 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 221 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 222 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 223 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 224 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 225 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 226 | * |
<> | 144:ef7eb2e8f9f7 | 227 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 228 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 229 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 230 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 231 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 232 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 233 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 234 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 235 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 236 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 237 | * |
<> | 156:95d6b41a828b | 238 | ****************************************************************************** |
Anna Bridge |
180:96ed750bd169 | 239 | */ |
<> | 144:ef7eb2e8f9f7 | 240 | |
<> | 144:ef7eb2e8f9f7 | 241 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 242 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 245 | * @{ |
<> | 144:ef7eb2e8f9f7 | 246 | */ |
<> | 144:ef7eb2e8f9f7 | 247 | |
<> | 144:ef7eb2e8f9f7 | 248 | /** @defgroup I2C I2C |
<> | 144:ef7eb2e8f9f7 | 249 | * @brief I2C HAL module driver |
<> | 144:ef7eb2e8f9f7 | 250 | * @{ |
<> | 144:ef7eb2e8f9f7 | 251 | */ |
<> | 144:ef7eb2e8f9f7 | 252 | |
<> | 144:ef7eb2e8f9f7 | 253 | #ifdef HAL_I2C_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 254 | |
<> | 144:ef7eb2e8f9f7 | 255 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 256 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /** @defgroup I2C_Private_Define I2C Private Define |
<> | 144:ef7eb2e8f9f7 | 259 | * @{ |
<> | 144:ef7eb2e8f9f7 | 260 | */ |
<> | 144:ef7eb2e8f9f7 | 261 | #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ |
<> | 144:ef7eb2e8f9f7 | 262 | #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ |
<> | 144:ef7eb2e8f9f7 | 263 | #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 264 | #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 265 | #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 266 | #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 267 | #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 268 | #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 269 | #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 270 | #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | #define MAX_NBYTE_SIZE 255U |
<> | 144:ef7eb2e8f9f7 | 273 | #define SlaveAddr_SHIFT 7U |
<> | 144:ef7eb2e8f9f7 | 274 | #define SlaveAddr_MSK 0x06U |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | /* Private define for @ref PreviousState usage */ |
<> | 156:95d6b41a828b | 277 | #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ |
<> | 144:ef7eb2e8f9f7 | 278 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
<> | 144:ef7eb2e8f9f7 | 279 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 280 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 281 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 282 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 283 | #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 284 | #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | /* Private define to centralize the enable/disable of Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 288 | #define I2C_XFER_TX_IT (0x00000001U) |
<> | 144:ef7eb2e8f9f7 | 289 | #define I2C_XFER_RX_IT (0x00000002U) |
<> | 144:ef7eb2e8f9f7 | 290 | #define I2C_XFER_LISTEN_IT (0x00000004U) |
<> | 144:ef7eb2e8f9f7 | 291 | |
<> | 144:ef7eb2e8f9f7 | 292 | #define I2C_XFER_ERROR_IT (0x00000011U) |
<> | 144:ef7eb2e8f9f7 | 293 | #define I2C_XFER_CPLT_IT (0x00000012U) |
<> | 144:ef7eb2e8f9f7 | 294 | #define I2C_XFER_RELOAD_IT (0x00000012U) |
<> | 156:95d6b41a828b | 295 | |
<> | 156:95d6b41a828b | 296 | /* Private define Sequential Transfer Options default/reset value */ |
<> | 156:95d6b41a828b | 297 | #define I2C_NO_OPTION_FRAME (0xFFFF0000U) |
<> | 144:ef7eb2e8f9f7 | 298 | /** |
<> | 144:ef7eb2e8f9f7 | 299 | * @} |
<> | 156:95d6b41a828b | 300 | */ |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 303 | #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \ |
<> | 144:ef7eb2e8f9f7 | 304 | ((uint32_t)((__HANDLE__)->hdmatx->Instance->CNDTR)) : \ |
<> | 144:ef7eb2e8f9f7 | 305 | ((uint32_t)((__HANDLE__)->hdmarx->Instance->CNDTR))) |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 308 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 309 | |
<> | 144:ef7eb2e8f9f7 | 310 | /** @defgroup I2C_Private_Functions I2C Private Functions |
<> | 144:ef7eb2e8f9f7 | 311 | * @{ |
<> | 144:ef7eb2e8f9f7 | 312 | */ |
<> | 144:ef7eb2e8f9f7 | 313 | /* Private functions to handle DMA transfer */ |
<> | 144:ef7eb2e8f9f7 | 314 | static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 315 | static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 316 | static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 317 | static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 318 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 319 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | /* Private functions to handle IT transfer */ |
<> | 144:ef7eb2e8f9f7 | 322 | static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); |
<> | 144:ef7eb2e8f9f7 | 323 | static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c); |
<> | 144:ef7eb2e8f9f7 | 324 | static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c); |
<> | 144:ef7eb2e8f9f7 | 325 | static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); |
<> | 144:ef7eb2e8f9f7 | 326 | static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); |
<> | 144:ef7eb2e8f9f7 | 327 | static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); |
<> | 144:ef7eb2e8f9f7 | 328 | static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); |
<> | 144:ef7eb2e8f9f7 | 329 | |
<> | 144:ef7eb2e8f9f7 | 330 | /* Private functions to handle IT transfer */ |
<> | 144:ef7eb2e8f9f7 | 331 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 332 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /* Private functions for I2C transfer IRQ handler */ |
<> | 144:ef7eb2e8f9f7 | 335 | static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); |
<> | 144:ef7eb2e8f9f7 | 336 | static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); |
<> | 144:ef7eb2e8f9f7 | 337 | static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); |
<> | 144:ef7eb2e8f9f7 | 338 | static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); |
<> | 144:ef7eb2e8f9f7 | 339 | |
<> | 144:ef7eb2e8f9f7 | 340 | /* Private functions to handle flags during polling transfer */ |
<> | 144:ef7eb2e8f9f7 | 341 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 342 | static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 343 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 344 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 345 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | /* Private functions to centralize the enable/disable of Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 348 | static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); |
<> | 144:ef7eb2e8f9f7 | 349 | static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); |
<> | 144:ef7eb2e8f9f7 | 350 | |
<> | 144:ef7eb2e8f9f7 | 351 | /* Private functions to flush TXDR register */ |
<> | 144:ef7eb2e8f9f7 | 352 | static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); |
<> | 144:ef7eb2e8f9f7 | 353 | |
<> | 144:ef7eb2e8f9f7 | 354 | /* Private functions to handle start, restart or stop a transfer */ |
<> | 144:ef7eb2e8f9f7 | 355 | static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request); |
<> | 144:ef7eb2e8f9f7 | 356 | /** |
<> | 144:ef7eb2e8f9f7 | 357 | * @} |
<> | 156:95d6b41a828b | 358 | */ |
<> | 144:ef7eb2e8f9f7 | 359 | |
<> | 144:ef7eb2e8f9f7 | 360 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 361 | |
<> | 144:ef7eb2e8f9f7 | 362 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
<> | 144:ef7eb2e8f9f7 | 363 | * @{ |
<> | 144:ef7eb2e8f9f7 | 364 | */ |
<> | 144:ef7eb2e8f9f7 | 365 | |
<> | 144:ef7eb2e8f9f7 | 366 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
Anna Bridge |
180:96ed750bd169 | 367 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 368 | * |
<> | 144:ef7eb2e8f9f7 | 369 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 370 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 371 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 372 | =============================================================================== |
<> | 156:95d6b41a828b | 373 | [..] This subsection provides a set of functions allowing to initialize and |
<> | 144:ef7eb2e8f9f7 | 374 | deinitialize the I2Cx peripheral: |
<> | 144:ef7eb2e8f9f7 | 375 | |
<> | 156:95d6b41a828b | 376 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
<> | 144:ef7eb2e8f9f7 | 377 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). |
<> | 144:ef7eb2e8f9f7 | 378 | |
<> | 156:95d6b41a828b | 379 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
<> | 144:ef7eb2e8f9f7 | 380 | the selected configuration: |
<> | 144:ef7eb2e8f9f7 | 381 | (++) Clock Timing |
<> | 144:ef7eb2e8f9f7 | 382 | (++) Own Address 1 |
<> | 144:ef7eb2e8f9f7 | 383 | (++) Addressing mode (Master, Slave) |
<> | 144:ef7eb2e8f9f7 | 384 | (++) Dual Addressing mode |
<> | 144:ef7eb2e8f9f7 | 385 | (++) Own Address 2 |
<> | 144:ef7eb2e8f9f7 | 386 | (++) Own Address 2 Mask |
<> | 144:ef7eb2e8f9f7 | 387 | (++) General call mode |
<> | 144:ef7eb2e8f9f7 | 388 | (++) Nostretch mode |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 156:95d6b41a828b | 390 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
<> | 156:95d6b41a828b | 391 | of the selected I2Cx peripheral. |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 394 | * @{ |
<> | 144:ef7eb2e8f9f7 | 395 | */ |
<> | 144:ef7eb2e8f9f7 | 396 | |
<> | 144:ef7eb2e8f9f7 | 397 | /** |
<> | 156:95d6b41a828b | 398 | * @brief Initializes the I2C according to the specified parameters |
<> | 144:ef7eb2e8f9f7 | 399 | * in the I2C_InitTypeDef and initialize the associated handle. |
<> | 144:ef7eb2e8f9f7 | 400 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 401 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 402 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 403 | */ |
<> | 144:ef7eb2e8f9f7 | 404 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 405 | { |
<> | 144:ef7eb2e8f9f7 | 406 | /* Check the I2C handle allocation */ |
Anna Bridge |
180:96ed750bd169 | 407 | if (hi2c == NULL) |
<> | 144:ef7eb2e8f9f7 | 408 | { |
<> | 144:ef7eb2e8f9f7 | 409 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 410 | } |
<> | 144:ef7eb2e8f9f7 | 411 | |
<> | 144:ef7eb2e8f9f7 | 412 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 413 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
<> | 144:ef7eb2e8f9f7 | 414 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
<> | 144:ef7eb2e8f9f7 | 415 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
<> | 144:ef7eb2e8f9f7 | 416 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
<> | 144:ef7eb2e8f9f7 | 417 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
<> | 144:ef7eb2e8f9f7 | 418 | assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); |
<> | 144:ef7eb2e8f9f7 | 419 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
<> | 144:ef7eb2e8f9f7 | 420 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
<> | 144:ef7eb2e8f9f7 | 421 | |
Anna Bridge |
180:96ed750bd169 | 422 | if (hi2c->State == HAL_I2C_STATE_RESET) |
<> | 144:ef7eb2e8f9f7 | 423 | { |
<> | 144:ef7eb2e8f9f7 | 424 | /* Allocate lock resource and initialize it */ |
<> | 144:ef7eb2e8f9f7 | 425 | hi2c->Lock = HAL_UNLOCKED; |
<> | 156:95d6b41a828b | 426 | |
<> | 144:ef7eb2e8f9f7 | 427 | /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ |
<> | 144:ef7eb2e8f9f7 | 428 | HAL_I2C_MspInit(hi2c); |
<> | 144:ef7eb2e8f9f7 | 429 | } |
<> | 144:ef7eb2e8f9f7 | 430 | |
<> | 144:ef7eb2e8f9f7 | 431 | hi2c->State = HAL_I2C_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 432 | |
<> | 144:ef7eb2e8f9f7 | 433 | /* Disable the selected I2C peripheral */ |
<> | 144:ef7eb2e8f9f7 | 434 | __HAL_I2C_DISABLE(hi2c); |
<> | 144:ef7eb2e8f9f7 | 435 | |
<> | 144:ef7eb2e8f9f7 | 436 | /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ |
<> | 144:ef7eb2e8f9f7 | 437 | /* Configure I2Cx: Frequency range */ |
<> | 144:ef7eb2e8f9f7 | 438 | hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; |
<> | 144:ef7eb2e8f9f7 | 439 | |
<> | 144:ef7eb2e8f9f7 | 440 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
<> | 156:95d6b41a828b | 441 | /* Disable Own Address1 before set the Own Address1 configuration */ |
<> | 144:ef7eb2e8f9f7 | 442 | hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; |
<> | 156:95d6b41a828b | 443 | |
<> | 156:95d6b41a828b | 444 | /* Configure I2Cx: Own Address1 and ack own address1 mode */ |
Anna Bridge |
180:96ed750bd169 | 445 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
<> | 144:ef7eb2e8f9f7 | 446 | { |
<> | 156:95d6b41a828b | 447 | hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); |
<> | 156:95d6b41a828b | 448 | } |
<> | 156:95d6b41a828b | 449 | else /* I2C_ADDRESSINGMODE_10BIT */ |
<> | 156:95d6b41a828b | 450 | { |
<> | 156:95d6b41a828b | 451 | hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); |
<> | 144:ef7eb2e8f9f7 | 452 | } |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 455 | /* Configure I2Cx: Addressing Master mode */ |
Anna Bridge |
180:96ed750bd169 | 456 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
<> | 144:ef7eb2e8f9f7 | 457 | { |
<> | 144:ef7eb2e8f9f7 | 458 | hi2c->Instance->CR2 = (I2C_CR2_ADD10); |
<> | 144:ef7eb2e8f9f7 | 459 | } |
<> | 144:ef7eb2e8f9f7 | 460 | /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ |
<> | 144:ef7eb2e8f9f7 | 461 | hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
<> | 156:95d6b41a828b | 464 | /* Disable Own Address2 before set the Own Address2 configuration */ |
<> | 156:95d6b41a828b | 465 | hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; |
<> | 156:95d6b41a828b | 466 | |
<> | 144:ef7eb2e8f9f7 | 467 | /* Configure I2Cx: Dual mode and Own Address2 */ |
<> | 144:ef7eb2e8f9f7 | 468 | hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8)); |
<> | 144:ef7eb2e8f9f7 | 469 | |
<> | 144:ef7eb2e8f9f7 | 470 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 471 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
<> | 144:ef7eb2e8f9f7 | 472 | hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); |
<> | 144:ef7eb2e8f9f7 | 473 | |
<> | 144:ef7eb2e8f9f7 | 474 | /* Enable the selected I2C peripheral */ |
<> | 144:ef7eb2e8f9f7 | 475 | __HAL_I2C_ENABLE(hi2c); |
<> | 144:ef7eb2e8f9f7 | 476 | |
<> | 144:ef7eb2e8f9f7 | 477 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 478 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 479 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 480 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 481 | |
<> | 144:ef7eb2e8f9f7 | 482 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 483 | } |
<> | 144:ef7eb2e8f9f7 | 484 | |
<> | 144:ef7eb2e8f9f7 | 485 | /** |
<> | 156:95d6b41a828b | 486 | * @brief DeInitialize the I2C peripheral. |
<> | 144:ef7eb2e8f9f7 | 487 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 488 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 489 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 490 | */ |
<> | 144:ef7eb2e8f9f7 | 491 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 492 | { |
<> | 144:ef7eb2e8f9f7 | 493 | /* Check the I2C handle allocation */ |
Anna Bridge |
180:96ed750bd169 | 494 | if (hi2c == NULL) |
<> | 144:ef7eb2e8f9f7 | 495 | { |
<> | 144:ef7eb2e8f9f7 | 496 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 497 | } |
<> | 144:ef7eb2e8f9f7 | 498 | |
<> | 144:ef7eb2e8f9f7 | 499 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 500 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
<> | 144:ef7eb2e8f9f7 | 501 | |
<> | 144:ef7eb2e8f9f7 | 502 | hi2c->State = HAL_I2C_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | /* Disable the I2C Peripheral Clock */ |
<> | 144:ef7eb2e8f9f7 | 505 | __HAL_I2C_DISABLE(hi2c); |
<> | 144:ef7eb2e8f9f7 | 506 | |
<> | 144:ef7eb2e8f9f7 | 507 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
<> | 144:ef7eb2e8f9f7 | 508 | HAL_I2C_MspDeInit(hi2c); |
<> | 144:ef7eb2e8f9f7 | 509 | |
<> | 144:ef7eb2e8f9f7 | 510 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 511 | hi2c->State = HAL_I2C_STATE_RESET; |
<> | 144:ef7eb2e8f9f7 | 512 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 513 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 514 | |
<> | 144:ef7eb2e8f9f7 | 515 | /* Release Lock */ |
<> | 144:ef7eb2e8f9f7 | 516 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 517 | |
<> | 144:ef7eb2e8f9f7 | 518 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 519 | } |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | /** |
<> | 144:ef7eb2e8f9f7 | 522 | * @brief Initialize the I2C MSP. |
<> | 144:ef7eb2e8f9f7 | 523 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 524 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 525 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 526 | */ |
<> | 156:95d6b41a828b | 527 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 528 | { |
<> | 144:ef7eb2e8f9f7 | 529 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 530 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 533 | the HAL_I2C_MspInit could be implemented in the user file |
<> | 156:95d6b41a828b | 534 | */ |
<> | 144:ef7eb2e8f9f7 | 535 | } |
<> | 144:ef7eb2e8f9f7 | 536 | |
<> | 144:ef7eb2e8f9f7 | 537 | /** |
<> | 144:ef7eb2e8f9f7 | 538 | * @brief DeInitialize the I2C MSP. |
<> | 144:ef7eb2e8f9f7 | 539 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 540 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 541 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 542 | */ |
<> | 156:95d6b41a828b | 543 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 544 | { |
<> | 144:ef7eb2e8f9f7 | 545 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 546 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 547 | |
<> | 144:ef7eb2e8f9f7 | 548 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 549 | the HAL_I2C_MspDeInit could be implemented in the user file |
<> | 156:95d6b41a828b | 550 | */ |
<> | 144:ef7eb2e8f9f7 | 551 | } |
<> | 144:ef7eb2e8f9f7 | 552 | |
<> | 144:ef7eb2e8f9f7 | 553 | /** |
<> | 144:ef7eb2e8f9f7 | 554 | * @} |
<> | 144:ef7eb2e8f9f7 | 555 | */ |
<> | 144:ef7eb2e8f9f7 | 556 | |
<> | 156:95d6b41a828b | 557 | /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions |
Anna Bridge |
180:96ed750bd169 | 558 | * @brief Data transfers functions |
<> | 144:ef7eb2e8f9f7 | 559 | * |
<> | 156:95d6b41a828b | 560 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 561 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 562 | ##### IO operation functions ##### |
<> | 156:95d6b41a828b | 563 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 564 | [..] |
<> | 156:95d6b41a828b | 565 | This subsection provides a set of functions allowing to manage the I2C data |
<> | 144:ef7eb2e8f9f7 | 566 | transfers. |
<> | 144:ef7eb2e8f9f7 | 567 | |
<> | 144:ef7eb2e8f9f7 | 568 | (#) There are two modes of transfer: |
<> | 156:95d6b41a828b | 569 | (++) Blocking mode : The communication is performed in the polling mode. |
Anna Bridge |
180:96ed750bd169 | 570 | The status of all data processing is returned by the same function |
<> | 156:95d6b41a828b | 571 | after finishing transfer. |
<> | 156:95d6b41a828b | 572 | (++) No-Blocking mode : The communication is performed using Interrupts |
<> | 144:ef7eb2e8f9f7 | 573 | or DMA. These functions return the status of the transfer startup. |
<> | 156:95d6b41a828b | 574 | The end of the data processing will be indicated through the |
<> | 156:95d6b41a828b | 575 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
<> | 144:ef7eb2e8f9f7 | 576 | using DMA mode. |
<> | 144:ef7eb2e8f9f7 | 577 | |
<> | 144:ef7eb2e8f9f7 | 578 | (#) Blocking mode functions are : |
<> | 144:ef7eb2e8f9f7 | 579 | (++) HAL_I2C_Master_Transmit() |
<> | 144:ef7eb2e8f9f7 | 580 | (++) HAL_I2C_Master_Receive() |
<> | 144:ef7eb2e8f9f7 | 581 | (++) HAL_I2C_Slave_Transmit() |
<> | 144:ef7eb2e8f9f7 | 582 | (++) HAL_I2C_Slave_Receive() |
<> | 144:ef7eb2e8f9f7 | 583 | (++) HAL_I2C_Mem_Write() |
<> | 144:ef7eb2e8f9f7 | 584 | (++) HAL_I2C_Mem_Read() |
<> | 144:ef7eb2e8f9f7 | 585 | (++) HAL_I2C_IsDeviceReady() |
<> | 156:95d6b41a828b | 586 | |
<> | 144:ef7eb2e8f9f7 | 587 | (#) No-Blocking mode functions with Interrupt are : |
<> | 144:ef7eb2e8f9f7 | 588 | (++) HAL_I2C_Master_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 589 | (++) HAL_I2C_Master_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 590 | (++) HAL_I2C_Slave_Transmit_IT() |
<> | 144:ef7eb2e8f9f7 | 591 | (++) HAL_I2C_Slave_Receive_IT() |
<> | 144:ef7eb2e8f9f7 | 592 | (++) HAL_I2C_Mem_Write_IT() |
<> | 144:ef7eb2e8f9f7 | 593 | (++) HAL_I2C_Mem_Read_IT() |
<> | 144:ef7eb2e8f9f7 | 594 | |
<> | 144:ef7eb2e8f9f7 | 595 | (#) No-Blocking mode functions with DMA are : |
<> | 144:ef7eb2e8f9f7 | 596 | (++) HAL_I2C_Master_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 597 | (++) HAL_I2C_Master_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 598 | (++) HAL_I2C_Slave_Transmit_DMA() |
<> | 144:ef7eb2e8f9f7 | 599 | (++) HAL_I2C_Slave_Receive_DMA() |
<> | 144:ef7eb2e8f9f7 | 600 | (++) HAL_I2C_Mem_Write_DMA() |
<> | 144:ef7eb2e8f9f7 | 601 | (++) HAL_I2C_Mem_Read_DMA() |
<> | 144:ef7eb2e8f9f7 | 602 | |
<> | 144:ef7eb2e8f9f7 | 603 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
<> | 144:ef7eb2e8f9f7 | 604 | (++) HAL_I2C_MemTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 605 | (++) HAL_I2C_MemRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 606 | (++) HAL_I2C_MasterTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 607 | (++) HAL_I2C_MasterRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 608 | (++) HAL_I2C_SlaveTxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 609 | (++) HAL_I2C_SlaveRxCpltCallback() |
<> | 144:ef7eb2e8f9f7 | 610 | (++) HAL_I2C_ErrorCallback() |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 613 | * @{ |
<> | 144:ef7eb2e8f9f7 | 614 | */ |
<> | 144:ef7eb2e8f9f7 | 615 | |
<> | 144:ef7eb2e8f9f7 | 616 | /** |
<> | 144:ef7eb2e8f9f7 | 617 | * @brief Transmits in master mode an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 618 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 619 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 620 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 621 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 622 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 623 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 624 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 625 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 626 | */ |
<> | 144:ef7eb2e8f9f7 | 627 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 628 | { |
<> | 144:ef7eb2e8f9f7 | 629 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 630 | |
Anna Bridge |
180:96ed750bd169 | 631 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 632 | { |
<> | 144:ef7eb2e8f9f7 | 633 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 634 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 635 | |
<> | 144:ef7eb2e8f9f7 | 636 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 637 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 638 | |
Anna Bridge |
180:96ed750bd169 | 639 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 640 | { |
<> | 144:ef7eb2e8f9f7 | 641 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 642 | } |
<> | 144:ef7eb2e8f9f7 | 643 | |
<> | 156:95d6b41a828b | 644 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 645 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 156:95d6b41a828b | 646 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
Anna Bridge |
180:96ed750bd169 | 647 | |
<> | 144:ef7eb2e8f9f7 | 648 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 649 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 650 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 651 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 652 | |
<> | 144:ef7eb2e8f9f7 | 653 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 654 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 655 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 656 | { |
<> | 144:ef7eb2e8f9f7 | 657 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 658 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 659 | } |
<> | 144:ef7eb2e8f9f7 | 660 | else |
<> | 144:ef7eb2e8f9f7 | 661 | { |
<> | 144:ef7eb2e8f9f7 | 662 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 663 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 664 | } |
<> | 144:ef7eb2e8f9f7 | 665 | |
Anna Bridge |
180:96ed750bd169 | 666 | while (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 667 | { |
<> | 144:ef7eb2e8f9f7 | 668 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 669 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 670 | { |
Anna Bridge |
180:96ed750bd169 | 671 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 672 | { |
<> | 144:ef7eb2e8f9f7 | 673 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 674 | } |
<> | 144:ef7eb2e8f9f7 | 675 | else |
<> | 144:ef7eb2e8f9f7 | 676 | { |
<> | 144:ef7eb2e8f9f7 | 677 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 678 | } |
<> | 144:ef7eb2e8f9f7 | 679 | } |
<> | 144:ef7eb2e8f9f7 | 680 | /* Write data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 681 | hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 682 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 683 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 684 | |
Anna Bridge |
180:96ed750bd169 | 685 | if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) |
<> | 144:ef7eb2e8f9f7 | 686 | { |
<> | 144:ef7eb2e8f9f7 | 687 | /* Wait until TCR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 688 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 689 | { |
<> | 144:ef7eb2e8f9f7 | 690 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 691 | } |
<> | 156:95d6b41a828b | 692 | |
Anna Bridge |
180:96ed750bd169 | 693 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 694 | { |
<> | 144:ef7eb2e8f9f7 | 695 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 696 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 697 | } |
<> | 144:ef7eb2e8f9f7 | 698 | else |
<> | 144:ef7eb2e8f9f7 | 699 | { |
<> | 144:ef7eb2e8f9f7 | 700 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 701 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 702 | } |
<> | 144:ef7eb2e8f9f7 | 703 | } |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 156:95d6b41a828b | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
<> | 144:ef7eb2e8f9f7 | 707 | /* Wait until STOPF flag is set */ |
Anna Bridge |
180:96ed750bd169 | 708 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 709 | { |
Anna Bridge |
180:96ed750bd169 | 710 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 711 | { |
<> | 144:ef7eb2e8f9f7 | 712 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 713 | } |
<> | 144:ef7eb2e8f9f7 | 714 | else |
<> | 144:ef7eb2e8f9f7 | 715 | { |
<> | 144:ef7eb2e8f9f7 | 716 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 717 | } |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 721 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 722 | |
<> | 144:ef7eb2e8f9f7 | 723 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 724 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 725 | |
<> | 144:ef7eb2e8f9f7 | 726 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 156:95d6b41a828b | 727 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 156:95d6b41a828b | 728 | |
<> | 144:ef7eb2e8f9f7 | 729 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 730 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 731 | |
<> | 144:ef7eb2e8f9f7 | 732 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 733 | } |
<> | 144:ef7eb2e8f9f7 | 734 | else |
<> | 144:ef7eb2e8f9f7 | 735 | { |
<> | 144:ef7eb2e8f9f7 | 736 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 737 | } |
<> | 144:ef7eb2e8f9f7 | 738 | } |
<> | 144:ef7eb2e8f9f7 | 739 | |
<> | 144:ef7eb2e8f9f7 | 740 | /** |
<> | 156:95d6b41a828b | 741 | * @brief Receives in master mode an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 742 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 743 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 744 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 745 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 746 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 747 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 748 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 749 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 750 | */ |
<> | 144:ef7eb2e8f9f7 | 751 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 752 | { |
<> | 144:ef7eb2e8f9f7 | 753 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 754 | |
Anna Bridge |
180:96ed750bd169 | 755 | if (hi2c->State == HAL_I2C_STATE_READY) |
Anna Bridge |
180:96ed750bd169 | 756 | { |
<> | 144:ef7eb2e8f9f7 | 757 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 758 | __HAL_LOCK(hi2c); |
<> | 156:95d6b41a828b | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 761 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 762 | |
Anna Bridge |
180:96ed750bd169 | 763 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 764 | { |
<> | 144:ef7eb2e8f9f7 | 765 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 766 | } |
<> | 144:ef7eb2e8f9f7 | 767 | |
<> | 156:95d6b41a828b | 768 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 769 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 156:95d6b41a828b | 770 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 156:95d6b41a828b | 771 | |
<> | 144:ef7eb2e8f9f7 | 772 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 773 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 774 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 775 | hi2c->XferISR = NULL; |
<> | 156:95d6b41a828b | 776 | |
<> | 144:ef7eb2e8f9f7 | 777 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 778 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 779 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 780 | { |
<> | 144:ef7eb2e8f9f7 | 781 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 782 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 783 | } |
<> | 144:ef7eb2e8f9f7 | 784 | else |
<> | 144:ef7eb2e8f9f7 | 785 | { |
<> | 144:ef7eb2e8f9f7 | 786 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 787 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 788 | } |
<> | 144:ef7eb2e8f9f7 | 789 | |
Anna Bridge |
180:96ed750bd169 | 790 | while (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 791 | { |
<> | 144:ef7eb2e8f9f7 | 792 | /* Wait until RXNE flag is set */ |
Anna Bridge |
180:96ed750bd169 | 793 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 794 | { |
Anna Bridge |
180:96ed750bd169 | 795 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 796 | { |
<> | 144:ef7eb2e8f9f7 | 797 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 798 | } |
<> | 144:ef7eb2e8f9f7 | 799 | else |
<> | 144:ef7eb2e8f9f7 | 800 | { |
<> | 144:ef7eb2e8f9f7 | 801 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 802 | } |
<> | 144:ef7eb2e8f9f7 | 803 | } |
<> | 144:ef7eb2e8f9f7 | 804 | |
<> | 144:ef7eb2e8f9f7 | 805 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 806 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 807 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 808 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 809 | |
Anna Bridge |
180:96ed750bd169 | 810 | if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) |
<> | 144:ef7eb2e8f9f7 | 811 | { |
<> | 144:ef7eb2e8f9f7 | 812 | /* Wait until TCR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 813 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 816 | } |
<> | 156:95d6b41a828b | 817 | |
Anna Bridge |
180:96ed750bd169 | 818 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 819 | { |
<> | 144:ef7eb2e8f9f7 | 820 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 821 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 822 | } |
<> | 144:ef7eb2e8f9f7 | 823 | else |
<> | 144:ef7eb2e8f9f7 | 824 | { |
<> | 144:ef7eb2e8f9f7 | 825 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 826 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 827 | } |
<> | 144:ef7eb2e8f9f7 | 828 | } |
<> | 144:ef7eb2e8f9f7 | 829 | } |
<> | 144:ef7eb2e8f9f7 | 830 | |
<> | 144:ef7eb2e8f9f7 | 831 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
<> | 144:ef7eb2e8f9f7 | 832 | /* Wait until STOPF flag is set */ |
Anna Bridge |
180:96ed750bd169 | 833 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 834 | { |
Anna Bridge |
180:96ed750bd169 | 835 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 836 | { |
<> | 144:ef7eb2e8f9f7 | 837 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 838 | } |
<> | 144:ef7eb2e8f9f7 | 839 | else |
<> | 144:ef7eb2e8f9f7 | 840 | { |
<> | 144:ef7eb2e8f9f7 | 841 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 842 | } |
<> | 144:ef7eb2e8f9f7 | 843 | } |
Anna Bridge |
180:96ed750bd169 | 844 | |
<> | 144:ef7eb2e8f9f7 | 845 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 846 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 847 | |
<> | 144:ef7eb2e8f9f7 | 848 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 849 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 850 | |
<> | 144:ef7eb2e8f9f7 | 851 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 156:95d6b41a828b | 852 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 855 | __HAL_UNLOCK(hi2c); |
<> | 156:95d6b41a828b | 856 | |
<> | 144:ef7eb2e8f9f7 | 857 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 858 | } |
<> | 144:ef7eb2e8f9f7 | 859 | else |
<> | 144:ef7eb2e8f9f7 | 860 | { |
<> | 144:ef7eb2e8f9f7 | 861 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 862 | } |
<> | 144:ef7eb2e8f9f7 | 863 | } |
<> | 144:ef7eb2e8f9f7 | 864 | |
<> | 144:ef7eb2e8f9f7 | 865 | /** |
Anna Bridge |
180:96ed750bd169 | 866 | * @brief Transmits in slave mode an amount of data in blocking mode. |
<> | 144:ef7eb2e8f9f7 | 867 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 868 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 869 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 870 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 871 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 872 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 873 | */ |
<> | 144:ef7eb2e8f9f7 | 874 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 875 | { |
<> | 144:ef7eb2e8f9f7 | 876 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 877 | |
Anna Bridge |
180:96ed750bd169 | 878 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 156:95d6b41a828b | 879 | { |
Anna Bridge |
180:96ed750bd169 | 880 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 881 | { |
<> | 144:ef7eb2e8f9f7 | 882 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 883 | } |
<> | 144:ef7eb2e8f9f7 | 884 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 885 | __HAL_LOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 886 | |
<> | 144:ef7eb2e8f9f7 | 887 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 888 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 889 | |
<> | 156:95d6b41a828b | 890 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 891 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 156:95d6b41a828b | 892 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 156:95d6b41a828b | 893 | |
<> | 144:ef7eb2e8f9f7 | 894 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 895 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 896 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 897 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 898 | |
<> | 144:ef7eb2e8f9f7 | 899 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 900 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 901 | |
<> | 144:ef7eb2e8f9f7 | 902 | /* Wait until ADDR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 903 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 904 | { |
<> | 144:ef7eb2e8f9f7 | 905 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 906 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 907 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 908 | } |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | /* Clear ADDR flag */ |
Anna Bridge |
180:96ed750bd169 | 911 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | /* If 10bit addressing mode is selected */ |
Anna Bridge |
180:96ed750bd169 | 914 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
<> | 144:ef7eb2e8f9f7 | 915 | { |
<> | 144:ef7eb2e8f9f7 | 916 | /* Wait until ADDR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 917 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 918 | { |
<> | 144:ef7eb2e8f9f7 | 919 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 920 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 921 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 922 | } |
<> | 144:ef7eb2e8f9f7 | 923 | |
<> | 144:ef7eb2e8f9f7 | 924 | /* Clear ADDR flag */ |
Anna Bridge |
180:96ed750bd169 | 925 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 926 | } |
<> | 144:ef7eb2e8f9f7 | 927 | |
<> | 144:ef7eb2e8f9f7 | 928 | /* Wait until DIR flag is set Transmitter mode */ |
Anna Bridge |
180:96ed750bd169 | 929 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 930 | { |
<> | 144:ef7eb2e8f9f7 | 931 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 932 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 933 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 934 | } |
<> | 144:ef7eb2e8f9f7 | 935 | |
Anna Bridge |
180:96ed750bd169 | 936 | while (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 937 | { |
<> | 144:ef7eb2e8f9f7 | 938 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 939 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 940 | { |
<> | 144:ef7eb2e8f9f7 | 941 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 942 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 943 | |
Anna Bridge |
180:96ed750bd169 | 944 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 945 | { |
<> | 144:ef7eb2e8f9f7 | 946 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 947 | } |
<> | 144:ef7eb2e8f9f7 | 948 | else |
<> | 144:ef7eb2e8f9f7 | 949 | { |
<> | 144:ef7eb2e8f9f7 | 950 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 951 | } |
<> | 144:ef7eb2e8f9f7 | 952 | } |
<> | 156:95d6b41a828b | 953 | |
<> | 144:ef7eb2e8f9f7 | 954 | /* Write data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 955 | hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 956 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 957 | } |
<> | 144:ef7eb2e8f9f7 | 958 | |
<> | 144:ef7eb2e8f9f7 | 959 | /* Wait until STOP flag is set */ |
Anna Bridge |
180:96ed750bd169 | 960 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 961 | { |
<> | 144:ef7eb2e8f9f7 | 962 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 963 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 964 | |
Anna Bridge |
180:96ed750bd169 | 965 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 966 | { |
Anna Bridge |
180:96ed750bd169 | 967 | /* Normal use case for Transmitter mode */ |
Anna Bridge |
180:96ed750bd169 | 968 | /* A NACK is generated to confirm the end of transfer */ |
Anna Bridge |
180:96ed750bd169 | 969 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 970 | } |
<> | 144:ef7eb2e8f9f7 | 971 | else |
<> | 144:ef7eb2e8f9f7 | 972 | { |
<> | 144:ef7eb2e8f9f7 | 973 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 974 | } |
<> | 144:ef7eb2e8f9f7 | 975 | } |
<> | 156:95d6b41a828b | 976 | |
<> | 144:ef7eb2e8f9f7 | 977 | /* Clear STOP flag */ |
Anna Bridge |
180:96ed750bd169 | 978 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
Anna Bridge |
180:96ed750bd169 | 979 | |
Anna Bridge |
180:96ed750bd169 | 980 | /* Wait until BUSY flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 981 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 982 | { |
<> | 144:ef7eb2e8f9f7 | 983 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 984 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 985 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 986 | } |
<> | 144:ef7eb2e8f9f7 | 987 | |
<> | 144:ef7eb2e8f9f7 | 988 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 989 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 990 | |
<> | 144:ef7eb2e8f9f7 | 991 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 156:95d6b41a828b | 992 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 993 | |
<> | 144:ef7eb2e8f9f7 | 994 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 995 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 998 | } |
<> | 144:ef7eb2e8f9f7 | 999 | else |
<> | 144:ef7eb2e8f9f7 | 1000 | { |
<> | 144:ef7eb2e8f9f7 | 1001 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1002 | } |
<> | 144:ef7eb2e8f9f7 | 1003 | } |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | /** |
<> | 156:95d6b41a828b | 1006 | * @brief Receive in slave mode an amount of data in blocking mode |
<> | 144:ef7eb2e8f9f7 | 1007 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1008 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1009 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1010 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1011 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 1012 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1013 | */ |
<> | 144:ef7eb2e8f9f7 | 1014 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1015 | { |
<> | 144:ef7eb2e8f9f7 | 1016 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1017 | |
Anna Bridge |
180:96ed750bd169 | 1018 | if (hi2c->State == HAL_I2C_STATE_READY) |
Anna Bridge |
180:96ed750bd169 | 1019 | { |
Anna Bridge |
180:96ed750bd169 | 1020 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1021 | { |
<> | 144:ef7eb2e8f9f7 | 1022 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1023 | } |
<> | 144:ef7eb2e8f9f7 | 1024 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1025 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1026 | |
<> | 144:ef7eb2e8f9f7 | 1027 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 1028 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1029 | |
<> | 156:95d6b41a828b | 1030 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 1031 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 156:95d6b41a828b | 1032 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1033 | |
<> | 144:ef7eb2e8f9f7 | 1034 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 1035 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1036 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1037 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1038 | |
<> | 144:ef7eb2e8f9f7 | 1039 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1040 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1041 | |
<> | 144:ef7eb2e8f9f7 | 1042 | /* Wait until ADDR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1043 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1044 | { |
<> | 144:ef7eb2e8f9f7 | 1045 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1046 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1047 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1048 | } |
<> | 144:ef7eb2e8f9f7 | 1049 | |
<> | 144:ef7eb2e8f9f7 | 1050 | /* Clear ADDR flag */ |
Anna Bridge |
180:96ed750bd169 | 1051 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 1052 | |
<> | 144:ef7eb2e8f9f7 | 1053 | /* Wait until DIR flag is reset Receiver mode */ |
Anna Bridge |
180:96ed750bd169 | 1054 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1055 | { |
<> | 144:ef7eb2e8f9f7 | 1056 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1057 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1058 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1059 | } |
<> | 144:ef7eb2e8f9f7 | 1060 | |
Anna Bridge |
180:96ed750bd169 | 1061 | while (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 1062 | { |
<> | 144:ef7eb2e8f9f7 | 1063 | /* Wait until RXNE flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1064 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1065 | { |
<> | 144:ef7eb2e8f9f7 | 1066 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1067 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1068 | |
<> | 144:ef7eb2e8f9f7 | 1069 | /* Store Last receive data if any */ |
Anna Bridge |
180:96ed750bd169 | 1070 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
<> | 144:ef7eb2e8f9f7 | 1071 | { |
<> | 144:ef7eb2e8f9f7 | 1072 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 1073 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 1074 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 1075 | } |
<> | 144:ef7eb2e8f9f7 | 1076 | |
Anna Bridge |
180:96ed750bd169 | 1077 | if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT) |
<> | 144:ef7eb2e8f9f7 | 1078 | { |
<> | 144:ef7eb2e8f9f7 | 1079 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1080 | } |
<> | 144:ef7eb2e8f9f7 | 1081 | else |
<> | 144:ef7eb2e8f9f7 | 1082 | { |
<> | 144:ef7eb2e8f9f7 | 1083 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1084 | } |
<> | 144:ef7eb2e8f9f7 | 1085 | } |
<> | 156:95d6b41a828b | 1086 | |
<> | 144:ef7eb2e8f9f7 | 1087 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 1088 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 1089 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 1090 | } |
<> | 144:ef7eb2e8f9f7 | 1091 | |
<> | 144:ef7eb2e8f9f7 | 1092 | /* Wait until STOP flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1093 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1094 | { |
<> | 144:ef7eb2e8f9f7 | 1095 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1096 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1097 | |
Anna Bridge |
180:96ed750bd169 | 1098 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1099 | { |
<> | 144:ef7eb2e8f9f7 | 1100 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1101 | } |
<> | 144:ef7eb2e8f9f7 | 1102 | else |
<> | 144:ef7eb2e8f9f7 | 1103 | { |
<> | 144:ef7eb2e8f9f7 | 1104 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1105 | } |
<> | 144:ef7eb2e8f9f7 | 1106 | } |
<> | 144:ef7eb2e8f9f7 | 1107 | |
<> | 144:ef7eb2e8f9f7 | 1108 | /* Clear STOP flag */ |
Anna Bridge |
180:96ed750bd169 | 1109 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 1110 | |
<> | 156:95d6b41a828b | 1111 | /* Wait until BUSY flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 1112 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1113 | { |
<> | 144:ef7eb2e8f9f7 | 1114 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1115 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1116 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1117 | } |
<> | 144:ef7eb2e8f9f7 | 1118 | |
<> | 144:ef7eb2e8f9f7 | 1119 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1120 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1121 | |
<> | 144:ef7eb2e8f9f7 | 1122 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 156:95d6b41a828b | 1123 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 1124 | |
<> | 144:ef7eb2e8f9f7 | 1125 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1126 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1127 | |
<> | 144:ef7eb2e8f9f7 | 1128 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1129 | } |
<> | 144:ef7eb2e8f9f7 | 1130 | else |
<> | 144:ef7eb2e8f9f7 | 1131 | { |
<> | 144:ef7eb2e8f9f7 | 1132 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1133 | } |
<> | 144:ef7eb2e8f9f7 | 1134 | } |
<> | 144:ef7eb2e8f9f7 | 1135 | |
<> | 144:ef7eb2e8f9f7 | 1136 | /** |
<> | 144:ef7eb2e8f9f7 | 1137 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1138 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1139 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1140 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1141 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1142 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1143 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1144 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1145 | */ |
<> | 144:ef7eb2e8f9f7 | 1146 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1147 | { |
<> | 144:ef7eb2e8f9f7 | 1148 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 1149 | |
Anna Bridge |
180:96ed750bd169 | 1150 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1151 | { |
Anna Bridge |
180:96ed750bd169 | 1152 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 1153 | { |
<> | 144:ef7eb2e8f9f7 | 1154 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1155 | } |
<> | 144:ef7eb2e8f9f7 | 1156 | |
<> | 144:ef7eb2e8f9f7 | 1157 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1158 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1159 | |
<> | 156:95d6b41a828b | 1160 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 1161 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 1162 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1163 | |
<> | 144:ef7eb2e8f9f7 | 1164 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1165 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1166 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1167 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1168 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 1169 | |
Anna Bridge |
180:96ed750bd169 | 1170 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1171 | { |
<> | 144:ef7eb2e8f9f7 | 1172 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1173 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 1174 | } |
<> | 144:ef7eb2e8f9f7 | 1175 | else |
<> | 144:ef7eb2e8f9f7 | 1176 | { |
<> | 144:ef7eb2e8f9f7 | 1177 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1178 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 1179 | } |
<> | 144:ef7eb2e8f9f7 | 1180 | |
<> | 144:ef7eb2e8f9f7 | 1181 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1182 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ |
<> | 144:ef7eb2e8f9f7 | 1183 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 1184 | |
<> | 144:ef7eb2e8f9f7 | 1185 | /* Process Unlocked */ |
Anna Bridge |
180:96ed750bd169 | 1186 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1187 | |
<> | 156:95d6b41a828b | 1188 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1189 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1190 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1191 | |
<> | 144:ef7eb2e8f9f7 | 1192 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1193 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1194 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1195 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 1196 | |
<> | 144:ef7eb2e8f9f7 | 1197 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1198 | } |
<> | 144:ef7eb2e8f9f7 | 1199 | else |
<> | 144:ef7eb2e8f9f7 | 1200 | { |
<> | 144:ef7eb2e8f9f7 | 1201 | return HAL_BUSY; |
<> | 156:95d6b41a828b | 1202 | } |
<> | 144:ef7eb2e8f9f7 | 1203 | } |
<> | 144:ef7eb2e8f9f7 | 1204 | |
<> | 144:ef7eb2e8f9f7 | 1205 | /** |
<> | 144:ef7eb2e8f9f7 | 1206 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1207 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1208 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1209 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1210 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1211 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1212 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1213 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1214 | */ |
<> | 144:ef7eb2e8f9f7 | 1215 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1216 | { |
<> | 144:ef7eb2e8f9f7 | 1217 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 1218 | |
Anna Bridge |
180:96ed750bd169 | 1219 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1220 | { |
Anna Bridge |
180:96ed750bd169 | 1221 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 1222 | { |
<> | 144:ef7eb2e8f9f7 | 1223 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1224 | } |
<> | 144:ef7eb2e8f9f7 | 1225 | |
<> | 144:ef7eb2e8f9f7 | 1226 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1227 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1228 | |
<> | 156:95d6b41a828b | 1229 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 1230 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 1231 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1232 | |
<> | 144:ef7eb2e8f9f7 | 1233 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1234 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1235 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1236 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1237 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 1238 | |
Anna Bridge |
180:96ed750bd169 | 1239 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1240 | { |
<> | 144:ef7eb2e8f9f7 | 1241 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1242 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 1243 | } |
<> | 144:ef7eb2e8f9f7 | 1244 | else |
<> | 144:ef7eb2e8f9f7 | 1245 | { |
<> | 144:ef7eb2e8f9f7 | 1246 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1247 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 1248 | } |
<> | 144:ef7eb2e8f9f7 | 1249 | |
<> | 144:ef7eb2e8f9f7 | 1250 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1251 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ |
<> | 144:ef7eb2e8f9f7 | 1252 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); |
Anna Bridge |
180:96ed750bd169 | 1253 | |
<> | 144:ef7eb2e8f9f7 | 1254 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 1255 | __HAL_UNLOCK(hi2c); |
<> | 156:95d6b41a828b | 1256 | |
<> | 156:95d6b41a828b | 1257 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1258 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1259 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1260 | |
<> | 144:ef7eb2e8f9f7 | 1261 | /* Enable ERR, TC, STOP, NACK, RXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1262 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1263 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1264 | I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 1265 | |
<> | 144:ef7eb2e8f9f7 | 1266 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1267 | } |
<> | 144:ef7eb2e8f9f7 | 1268 | else |
<> | 144:ef7eb2e8f9f7 | 1269 | { |
<> | 156:95d6b41a828b | 1270 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1271 | } |
<> | 144:ef7eb2e8f9f7 | 1272 | } |
<> | 144:ef7eb2e8f9f7 | 1273 | |
<> | 144:ef7eb2e8f9f7 | 1274 | /** |
<> | 156:95d6b41a828b | 1275 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1276 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1277 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1278 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1279 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1280 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1281 | */ |
<> | 144:ef7eb2e8f9f7 | 1282 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1283 | { |
Anna Bridge |
180:96ed750bd169 | 1284 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1285 | { |
<> | 144:ef7eb2e8f9f7 | 1286 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1287 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1288 | |
<> | 156:95d6b41a828b | 1289 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 1290 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1291 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 156:95d6b41a828b | 1292 | |
<> | 144:ef7eb2e8f9f7 | 1293 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1294 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1295 | |
<> | 144:ef7eb2e8f9f7 | 1296 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1297 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1298 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1299 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1300 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1301 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 1302 | |
<> | 144:ef7eb2e8f9f7 | 1303 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 1304 | __HAL_UNLOCK(hi2c); |
<> | 156:95d6b41a828b | 1305 | |
<> | 156:95d6b41a828b | 1306 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1307 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1308 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1309 | |
<> | 144:ef7eb2e8f9f7 | 1310 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1311 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1312 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1313 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 1314 | |
<> | 144:ef7eb2e8f9f7 | 1315 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1316 | } |
<> | 144:ef7eb2e8f9f7 | 1317 | else |
<> | 144:ef7eb2e8f9f7 | 1318 | { |
<> | 156:95d6b41a828b | 1319 | return HAL_BUSY; |
<> | 156:95d6b41a828b | 1320 | } |
<> | 144:ef7eb2e8f9f7 | 1321 | } |
<> | 144:ef7eb2e8f9f7 | 1322 | |
<> | 144:ef7eb2e8f9f7 | 1323 | /** |
Anna Bridge |
180:96ed750bd169 | 1324 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 1325 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1326 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1327 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1328 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1329 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1330 | */ |
<> | 144:ef7eb2e8f9f7 | 1331 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1332 | { |
Anna Bridge |
180:96ed750bd169 | 1333 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1334 | { |
<> | 144:ef7eb2e8f9f7 | 1335 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1336 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1337 | |
<> | 156:95d6b41a828b | 1338 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 1339 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1340 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1341 | |
<> | 144:ef7eb2e8f9f7 | 1342 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1343 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1344 | |
<> | 144:ef7eb2e8f9f7 | 1345 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1346 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1347 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1348 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1349 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1350 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 1351 | |
<> | 144:ef7eb2e8f9f7 | 1352 | /* Process Unlocked */ |
<> | 156:95d6b41a828b | 1353 | __HAL_UNLOCK(hi2c); |
<> | 156:95d6b41a828b | 1354 | |
<> | 156:95d6b41a828b | 1355 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1356 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1357 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1358 | |
<> | 144:ef7eb2e8f9f7 | 1359 | /* Enable ERR, TC, STOP, NACK, RXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1360 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1361 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1362 | I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); |
<> | 156:95d6b41a828b | 1363 | |
<> | 144:ef7eb2e8f9f7 | 1364 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1365 | } |
<> | 144:ef7eb2e8f9f7 | 1366 | else |
<> | 144:ef7eb2e8f9f7 | 1367 | { |
<> | 156:95d6b41a828b | 1368 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1369 | } |
<> | 144:ef7eb2e8f9f7 | 1370 | } |
<> | 144:ef7eb2e8f9f7 | 1371 | |
<> | 144:ef7eb2e8f9f7 | 1372 | /** |
<> | 144:ef7eb2e8f9f7 | 1373 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 1374 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1375 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1376 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1377 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1378 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1379 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1380 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1381 | */ |
<> | 144:ef7eb2e8f9f7 | 1382 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1383 | { |
<> | 144:ef7eb2e8f9f7 | 1384 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 1385 | |
Anna Bridge |
180:96ed750bd169 | 1386 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1387 | { |
Anna Bridge |
180:96ed750bd169 | 1388 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 1389 | { |
<> | 144:ef7eb2e8f9f7 | 1390 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1391 | } |
<> | 144:ef7eb2e8f9f7 | 1392 | |
<> | 144:ef7eb2e8f9f7 | 1393 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1394 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1395 | |
<> | 156:95d6b41a828b | 1396 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 1397 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 1398 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1399 | |
<> | 144:ef7eb2e8f9f7 | 1400 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1401 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1402 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1403 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1404 | hi2c->XferISR = I2C_Master_ISR_DMA; |
Anna Bridge |
180:96ed750bd169 | 1405 | |
Anna Bridge |
180:96ed750bd169 | 1406 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1407 | { |
<> | 144:ef7eb2e8f9f7 | 1408 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1409 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 1410 | } |
<> | 144:ef7eb2e8f9f7 | 1411 | else |
<> | 144:ef7eb2e8f9f7 | 1412 | { |
<> | 144:ef7eb2e8f9f7 | 1413 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1414 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 1415 | } |
<> | 144:ef7eb2e8f9f7 | 1416 | |
Anna Bridge |
180:96ed750bd169 | 1417 | if (hi2c->XferSize > 0U) |
<> | 144:ef7eb2e8f9f7 | 1418 | { |
<> | 144:ef7eb2e8f9f7 | 1419 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1420 | hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1421 | |
<> | 144:ef7eb2e8f9f7 | 1422 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1423 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1424 | |
<> | 144:ef7eb2e8f9f7 | 1425 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 1426 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1427 | hi2c->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1428 | |
<> | 144:ef7eb2e8f9f7 | 1429 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1430 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 1431 | |
<> | 144:ef7eb2e8f9f7 | 1432 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1433 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
<> | 144:ef7eb2e8f9f7 | 1434 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 1435 | |
<> | 144:ef7eb2e8f9f7 | 1436 | /* Update XferCount value */ |
<> | 144:ef7eb2e8f9f7 | 1437 | hi2c->XferCount -= hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 1438 | |
<> | 144:ef7eb2e8f9f7 | 1439 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1440 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1441 | |
<> | 144:ef7eb2e8f9f7 | 1442 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1443 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1444 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1445 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1446 | I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); |
<> | 144:ef7eb2e8f9f7 | 1447 | |
<> | 144:ef7eb2e8f9f7 | 1448 | /* Enable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1449 | hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 1450 | } |
<> | 144:ef7eb2e8f9f7 | 1451 | else |
<> | 144:ef7eb2e8f9f7 | 1452 | { |
<> | 144:ef7eb2e8f9f7 | 1453 | /* Update Transfer ISR function pointer */ |
<> | 144:ef7eb2e8f9f7 | 1454 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 1455 | |
<> | 144:ef7eb2e8f9f7 | 1456 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1457 | /* Set NBYTES to write and generate START condition */ |
<> | 144:ef7eb2e8f9f7 | 1458 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 1459 | |
<> | 144:ef7eb2e8f9f7 | 1460 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1461 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1462 | |
<> | 144:ef7eb2e8f9f7 | 1463 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1464 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1465 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1466 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1467 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1468 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1469 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 1470 | } |
<> | 144:ef7eb2e8f9f7 | 1471 | |
<> | 144:ef7eb2e8f9f7 | 1472 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1473 | } |
<> | 144:ef7eb2e8f9f7 | 1474 | else |
<> | 144:ef7eb2e8f9f7 | 1475 | { |
<> | 144:ef7eb2e8f9f7 | 1476 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1477 | } |
<> | 144:ef7eb2e8f9f7 | 1478 | } |
<> | 144:ef7eb2e8f9f7 | 1479 | |
<> | 144:ef7eb2e8f9f7 | 1480 | /** |
<> | 156:95d6b41a828b | 1481 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 1482 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1483 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1484 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1485 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1486 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1487 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1488 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1489 | */ |
<> | 144:ef7eb2e8f9f7 | 1490 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1491 | { |
<> | 144:ef7eb2e8f9f7 | 1492 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 1493 | |
Anna Bridge |
180:96ed750bd169 | 1494 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1495 | { |
Anna Bridge |
180:96ed750bd169 | 1496 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 1497 | { |
<> | 144:ef7eb2e8f9f7 | 1498 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1499 | } |
<> | 144:ef7eb2e8f9f7 | 1500 | |
<> | 144:ef7eb2e8f9f7 | 1501 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1502 | __HAL_LOCK(hi2c); |
<> | 156:95d6b41a828b | 1503 | |
<> | 156:95d6b41a828b | 1504 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 1505 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 1506 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1507 | |
<> | 144:ef7eb2e8f9f7 | 1508 | /* Prepare transfer parameters */ |
<> | 156:95d6b41a828b | 1509 | hi2c->pBuffPtr = pData; |
<> | 156:95d6b41a828b | 1510 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1511 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1512 | hi2c->XferISR = I2C_Master_ISR_DMA; |
Anna Bridge |
180:96ed750bd169 | 1513 | |
Anna Bridge |
180:96ed750bd169 | 1514 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1515 | { |
<> | 144:ef7eb2e8f9f7 | 1516 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1517 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 1518 | } |
<> | 144:ef7eb2e8f9f7 | 1519 | else |
<> | 144:ef7eb2e8f9f7 | 1520 | { |
<> | 144:ef7eb2e8f9f7 | 1521 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1522 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 1523 | } |
<> | 144:ef7eb2e8f9f7 | 1524 | |
Anna Bridge |
180:96ed750bd169 | 1525 | if (hi2c->XferSize > 0U) |
<> | 144:ef7eb2e8f9f7 | 1526 | { |
<> | 144:ef7eb2e8f9f7 | 1527 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1528 | hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1529 | |
<> | 144:ef7eb2e8f9f7 | 1530 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1531 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1532 | |
<> | 144:ef7eb2e8f9f7 | 1533 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 1534 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1535 | hi2c->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1536 | |
<> | 144:ef7eb2e8f9f7 | 1537 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1538 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 1539 | |
<> | 144:ef7eb2e8f9f7 | 1540 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1541 | /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 1542 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 1543 | |
<> | 144:ef7eb2e8f9f7 | 1544 | /* Update XferCount value */ |
<> | 144:ef7eb2e8f9f7 | 1545 | hi2c->XferCount -= hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 1546 | |
<> | 144:ef7eb2e8f9f7 | 1547 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1548 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1549 | |
<> | 144:ef7eb2e8f9f7 | 1550 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1551 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1552 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1553 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1554 | I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); |
<> | 144:ef7eb2e8f9f7 | 1555 | |
<> | 144:ef7eb2e8f9f7 | 1556 | /* Enable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 1557 | hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 1558 | } |
<> | 144:ef7eb2e8f9f7 | 1559 | else |
<> | 144:ef7eb2e8f9f7 | 1560 | { |
<> | 144:ef7eb2e8f9f7 | 1561 | /* Update Transfer ISR function pointer */ |
<> | 144:ef7eb2e8f9f7 | 1562 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 1563 | |
<> | 144:ef7eb2e8f9f7 | 1564 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1565 | /* Set NBYTES to read and generate START condition */ |
<> | 144:ef7eb2e8f9f7 | 1566 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 1567 | |
<> | 144:ef7eb2e8f9f7 | 1568 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1569 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1570 | |
<> | 144:ef7eb2e8f9f7 | 1571 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1572 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1573 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1574 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 1575 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 1576 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 1577 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 1578 | } |
<> | 144:ef7eb2e8f9f7 | 1579 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1580 | } |
<> | 144:ef7eb2e8f9f7 | 1581 | else |
<> | 144:ef7eb2e8f9f7 | 1582 | { |
<> | 144:ef7eb2e8f9f7 | 1583 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1584 | } |
<> | 144:ef7eb2e8f9f7 | 1585 | } |
<> | 144:ef7eb2e8f9f7 | 1586 | |
<> | 144:ef7eb2e8f9f7 | 1587 | /** |
<> | 156:95d6b41a828b | 1588 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 1589 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1590 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1591 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1592 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1593 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1594 | */ |
<> | 144:ef7eb2e8f9f7 | 1595 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1596 | { |
Anna Bridge |
180:96ed750bd169 | 1597 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1598 | { |
Anna Bridge |
180:96ed750bd169 | 1599 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1600 | { |
<> | 144:ef7eb2e8f9f7 | 1601 | return HAL_ERROR; |
Anna Bridge |
180:96ed750bd169 | 1602 | } |
<> | 144:ef7eb2e8f9f7 | 1603 | /* Process Locked */ |
<> | 156:95d6b41a828b | 1604 | __HAL_LOCK(hi2c); |
<> | 156:95d6b41a828b | 1605 | |
<> | 156:95d6b41a828b | 1606 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 156:95d6b41a828b | 1607 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1608 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 156:95d6b41a828b | 1609 | |
<> | 144:ef7eb2e8f9f7 | 1610 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 1611 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1612 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1613 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1614 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1615 | hi2c->XferISR = I2C_Slave_ISR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1616 | |
<> | 144:ef7eb2e8f9f7 | 1617 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1618 | hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 1619 | |
<> | 144:ef7eb2e8f9f7 | 1620 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1621 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1622 | |
<> | 144:ef7eb2e8f9f7 | 1623 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 1624 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1625 | hi2c->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1626 | |
<> | 144:ef7eb2e8f9f7 | 1627 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1628 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 1629 | |
<> | 144:ef7eb2e8f9f7 | 1630 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1631 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1632 | |
<> | 144:ef7eb2e8f9f7 | 1633 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1634 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1635 | |
<> | 144:ef7eb2e8f9f7 | 1636 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1637 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1638 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1639 | /* Enable ERR, STOP, NACK, ADDR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1640 | I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 1641 | |
<> | 144:ef7eb2e8f9f7 | 1642 | /* Enable DMA Request */ |
Anna Bridge |
180:96ed750bd169 | 1643 | hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 1644 | |
<> | 144:ef7eb2e8f9f7 | 1645 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1646 | } |
<> | 144:ef7eb2e8f9f7 | 1647 | else |
<> | 144:ef7eb2e8f9f7 | 1648 | { |
<> | 144:ef7eb2e8f9f7 | 1649 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1650 | } |
<> | 144:ef7eb2e8f9f7 | 1651 | } |
<> | 144:ef7eb2e8f9f7 | 1652 | |
<> | 144:ef7eb2e8f9f7 | 1653 | /** |
<> | 156:95d6b41a828b | 1654 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
<> | 144:ef7eb2e8f9f7 | 1655 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1656 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1657 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1658 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1659 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1660 | */ |
<> | 144:ef7eb2e8f9f7 | 1661 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 1662 | { |
Anna Bridge |
180:96ed750bd169 | 1663 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1664 | { |
Anna Bridge |
180:96ed750bd169 | 1665 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1666 | { |
<> | 156:95d6b41a828b | 1667 | return HAL_ERROR; |
Anna Bridge |
180:96ed750bd169 | 1668 | } |
<> | 144:ef7eb2e8f9f7 | 1669 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1670 | __HAL_LOCK(hi2c); |
<> | 156:95d6b41a828b | 1671 | |
<> | 156:95d6b41a828b | 1672 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 156:95d6b41a828b | 1673 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 1674 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 156:95d6b41a828b | 1675 | |
<> | 144:ef7eb2e8f9f7 | 1676 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 1677 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1678 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1679 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1680 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 1681 | hi2c->XferISR = I2C_Slave_ISR_DMA; |
<> | 144:ef7eb2e8f9f7 | 1682 | |
<> | 144:ef7eb2e8f9f7 | 1683 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 1684 | hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 1685 | |
<> | 144:ef7eb2e8f9f7 | 1686 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 1687 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 1688 | |
<> | 144:ef7eb2e8f9f7 | 1689 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 1690 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1691 | hi2c->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 1692 | |
<> | 144:ef7eb2e8f9f7 | 1693 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 1694 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 1695 | |
<> | 144:ef7eb2e8f9f7 | 1696 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 1697 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 1698 | |
<> | 144:ef7eb2e8f9f7 | 1699 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1700 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1701 | |
<> | 144:ef7eb2e8f9f7 | 1702 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 1703 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 1704 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 1705 | /* Enable ERR, STOP, NACK, ADDR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 1706 | I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 1707 | |
<> | 144:ef7eb2e8f9f7 | 1708 | /* Enable DMA Request */ |
<> | 156:95d6b41a828b | 1709 | hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 1710 | |
<> | 144:ef7eb2e8f9f7 | 1711 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1712 | } |
<> | 144:ef7eb2e8f9f7 | 1713 | else |
<> | 144:ef7eb2e8f9f7 | 1714 | { |
<> | 144:ef7eb2e8f9f7 | 1715 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1716 | } |
<> | 144:ef7eb2e8f9f7 | 1717 | } |
<> | 144:ef7eb2e8f9f7 | 1718 | /** |
<> | 144:ef7eb2e8f9f7 | 1719 | * @brief Write an amount of data in blocking mode to a specific memory address |
<> | 144:ef7eb2e8f9f7 | 1720 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1721 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1722 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1723 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1724 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 1725 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 1726 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1727 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1728 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 1729 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1730 | */ |
<> | 144:ef7eb2e8f9f7 | 1731 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1732 | { |
<> | 144:ef7eb2e8f9f7 | 1733 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1734 | |
<> | 144:ef7eb2e8f9f7 | 1735 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1736 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 156:95d6b41a828b | 1737 | |
Anna Bridge |
180:96ed750bd169 | 1738 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 156:95d6b41a828b | 1739 | { |
Anna Bridge |
180:96ed750bd169 | 1740 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1741 | { |
<> | 144:ef7eb2e8f9f7 | 1742 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1743 | } |
<> | 144:ef7eb2e8f9f7 | 1744 | |
<> | 144:ef7eb2e8f9f7 | 1745 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1746 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1747 | |
<> | 144:ef7eb2e8f9f7 | 1748 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 1749 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1750 | |
Anna Bridge |
180:96ed750bd169 | 1751 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1752 | { |
<> | 144:ef7eb2e8f9f7 | 1753 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1754 | } |
<> | 144:ef7eb2e8f9f7 | 1755 | |
<> | 144:ef7eb2e8f9f7 | 1756 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 1757 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 1758 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1759 | |
<> | 144:ef7eb2e8f9f7 | 1760 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 1761 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1762 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1763 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1764 | |
<> | 144:ef7eb2e8f9f7 | 1765 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 1766 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1767 | { |
Anna Bridge |
180:96ed750bd169 | 1768 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1769 | { |
<> | 144:ef7eb2e8f9f7 | 1770 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1771 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1772 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1773 | } |
<> | 144:ef7eb2e8f9f7 | 1774 | else |
<> | 144:ef7eb2e8f9f7 | 1775 | { |
<> | 144:ef7eb2e8f9f7 | 1776 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1777 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1778 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1779 | } |
<> | 144:ef7eb2e8f9f7 | 1780 | } |
<> | 144:ef7eb2e8f9f7 | 1781 | |
<> | 144:ef7eb2e8f9f7 | 1782 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ |
Anna Bridge |
180:96ed750bd169 | 1783 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1784 | { |
<> | 144:ef7eb2e8f9f7 | 1785 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1786 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1787 | } |
<> | 144:ef7eb2e8f9f7 | 1788 | else |
<> | 144:ef7eb2e8f9f7 | 1789 | { |
<> | 144:ef7eb2e8f9f7 | 1790 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1791 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1792 | } |
<> | 144:ef7eb2e8f9f7 | 1793 | |
<> | 144:ef7eb2e8f9f7 | 1794 | do |
<> | 144:ef7eb2e8f9f7 | 1795 | { |
<> | 144:ef7eb2e8f9f7 | 1796 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1797 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1798 | { |
Anna Bridge |
180:96ed750bd169 | 1799 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1800 | { |
<> | 144:ef7eb2e8f9f7 | 1801 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1802 | } |
<> | 144:ef7eb2e8f9f7 | 1803 | else |
<> | 144:ef7eb2e8f9f7 | 1804 | { |
<> | 144:ef7eb2e8f9f7 | 1805 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1806 | } |
<> | 144:ef7eb2e8f9f7 | 1807 | } |
<> | 144:ef7eb2e8f9f7 | 1808 | |
<> | 144:ef7eb2e8f9f7 | 1809 | /* Write data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 1810 | hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 1811 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 1812 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 1813 | |
Anna Bridge |
180:96ed750bd169 | 1814 | if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) |
<> | 144:ef7eb2e8f9f7 | 1815 | { |
<> | 144:ef7eb2e8f9f7 | 1816 | /* Wait until TCR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1817 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1818 | { |
<> | 144:ef7eb2e8f9f7 | 1819 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1820 | } |
<> | 144:ef7eb2e8f9f7 | 1821 | |
Anna Bridge |
180:96ed750bd169 | 1822 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1823 | { |
<> | 144:ef7eb2e8f9f7 | 1824 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1825 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1826 | } |
<> | 144:ef7eb2e8f9f7 | 1827 | else |
<> | 144:ef7eb2e8f9f7 | 1828 | { |
<> | 144:ef7eb2e8f9f7 | 1829 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1830 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1831 | } |
<> | 144:ef7eb2e8f9f7 | 1832 | } |
<> | 144:ef7eb2e8f9f7 | 1833 | |
Anna Bridge |
180:96ed750bd169 | 1834 | } |
Anna Bridge |
180:96ed750bd169 | 1835 | while (hi2c->XferCount > 0U); |
<> | 144:ef7eb2e8f9f7 | 1836 | |
<> | 144:ef7eb2e8f9f7 | 1837 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
Anna Bridge |
180:96ed750bd169 | 1838 | /* Wait until STOPF flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 1839 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1840 | { |
Anna Bridge |
180:96ed750bd169 | 1841 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1842 | { |
<> | 144:ef7eb2e8f9f7 | 1843 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1844 | } |
<> | 144:ef7eb2e8f9f7 | 1845 | else |
<> | 144:ef7eb2e8f9f7 | 1846 | { |
<> | 144:ef7eb2e8f9f7 | 1847 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1848 | } |
<> | 144:ef7eb2e8f9f7 | 1849 | } |
<> | 144:ef7eb2e8f9f7 | 1850 | |
<> | 144:ef7eb2e8f9f7 | 1851 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 1852 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 156:95d6b41a828b | 1853 | |
<> | 144:ef7eb2e8f9f7 | 1854 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 1855 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1856 | |
<> | 144:ef7eb2e8f9f7 | 1857 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 156:95d6b41a828b | 1858 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 1859 | |
<> | 144:ef7eb2e8f9f7 | 1860 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1861 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1862 | |
<> | 144:ef7eb2e8f9f7 | 1863 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 1864 | } |
<> | 144:ef7eb2e8f9f7 | 1865 | else |
<> | 144:ef7eb2e8f9f7 | 1866 | { |
<> | 144:ef7eb2e8f9f7 | 1867 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 1868 | } |
<> | 144:ef7eb2e8f9f7 | 1869 | } |
<> | 144:ef7eb2e8f9f7 | 1870 | |
<> | 144:ef7eb2e8f9f7 | 1871 | /** |
<> | 144:ef7eb2e8f9f7 | 1872 | * @brief Read an amount of data in blocking mode from a specific memory address |
<> | 144:ef7eb2e8f9f7 | 1873 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 1874 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 1875 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 1876 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 1877 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 1878 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 1879 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 1880 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 1881 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 1882 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 1883 | */ |
<> | 144:ef7eb2e8f9f7 | 1884 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 1885 | { |
<> | 144:ef7eb2e8f9f7 | 1886 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 1887 | |
<> | 144:ef7eb2e8f9f7 | 1888 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 1889 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 144:ef7eb2e8f9f7 | 1890 | |
Anna Bridge |
180:96ed750bd169 | 1891 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 1892 | { |
Anna Bridge |
180:96ed750bd169 | 1893 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 1894 | { |
<> | 144:ef7eb2e8f9f7 | 1895 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1896 | } |
<> | 144:ef7eb2e8f9f7 | 1897 | |
<> | 144:ef7eb2e8f9f7 | 1898 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 1899 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1900 | |
<> | 144:ef7eb2e8f9f7 | 1901 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 1902 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 1903 | |
Anna Bridge |
180:96ed750bd169 | 1904 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1905 | { |
<> | 144:ef7eb2e8f9f7 | 1906 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1907 | } |
<> | 144:ef7eb2e8f9f7 | 1908 | |
<> | 144:ef7eb2e8f9f7 | 1909 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 1910 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 1911 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 1912 | |
<> | 144:ef7eb2e8f9f7 | 1913 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 1914 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 1915 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 1916 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 1917 | |
<> | 144:ef7eb2e8f9f7 | 1918 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 1919 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1920 | { |
Anna Bridge |
180:96ed750bd169 | 1921 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1922 | { |
<> | 144:ef7eb2e8f9f7 | 1923 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1924 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1925 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1926 | } |
<> | 144:ef7eb2e8f9f7 | 1927 | else |
<> | 144:ef7eb2e8f9f7 | 1928 | { |
<> | 144:ef7eb2e8f9f7 | 1929 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 1930 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 1931 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1932 | } |
<> | 144:ef7eb2e8f9f7 | 1933 | } |
<> | 144:ef7eb2e8f9f7 | 1934 | |
<> | 144:ef7eb2e8f9f7 | 1935 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 1936 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 1937 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1938 | { |
<> | 144:ef7eb2e8f9f7 | 1939 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1940 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 1941 | } |
<> | 144:ef7eb2e8f9f7 | 1942 | else |
<> | 144:ef7eb2e8f9f7 | 1943 | { |
<> | 144:ef7eb2e8f9f7 | 1944 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1945 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 1946 | } |
<> | 144:ef7eb2e8f9f7 | 1947 | |
<> | 144:ef7eb2e8f9f7 | 1948 | do |
<> | 144:ef7eb2e8f9f7 | 1949 | { |
<> | 144:ef7eb2e8f9f7 | 1950 | /* Wait until RXNE flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1951 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1952 | { |
<> | 144:ef7eb2e8f9f7 | 1953 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1954 | } |
<> | 144:ef7eb2e8f9f7 | 1955 | |
<> | 144:ef7eb2e8f9f7 | 1956 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 1957 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 1958 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 1959 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 1960 | |
Anna Bridge |
180:96ed750bd169 | 1961 | if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) |
<> | 144:ef7eb2e8f9f7 | 1962 | { |
<> | 144:ef7eb2e8f9f7 | 1963 | /* Wait until TCR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 1964 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1965 | { |
<> | 144:ef7eb2e8f9f7 | 1966 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1967 | } |
<> | 144:ef7eb2e8f9f7 | 1968 | |
Anna Bridge |
180:96ed750bd169 | 1969 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 1970 | { |
<> | 144:ef7eb2e8f9f7 | 1971 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 1972 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1973 | } |
<> | 144:ef7eb2e8f9f7 | 1974 | else |
<> | 144:ef7eb2e8f9f7 | 1975 | { |
<> | 144:ef7eb2e8f9f7 | 1976 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 1977 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 1978 | } |
<> | 144:ef7eb2e8f9f7 | 1979 | } |
Anna Bridge |
180:96ed750bd169 | 1980 | } |
Anna Bridge |
180:96ed750bd169 | 1981 | while (hi2c->XferCount > 0U); |
<> | 144:ef7eb2e8f9f7 | 1982 | |
<> | 144:ef7eb2e8f9f7 | 1983 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
Anna Bridge |
180:96ed750bd169 | 1984 | /* Wait until STOPF flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 1985 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 1986 | { |
Anna Bridge |
180:96ed750bd169 | 1987 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 1988 | { |
<> | 144:ef7eb2e8f9f7 | 1989 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 1990 | } |
<> | 144:ef7eb2e8f9f7 | 1991 | else |
<> | 144:ef7eb2e8f9f7 | 1992 | { |
<> | 144:ef7eb2e8f9f7 | 1993 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 1994 | } |
<> | 144:ef7eb2e8f9f7 | 1995 | } |
<> | 144:ef7eb2e8f9f7 | 1996 | |
<> | 144:ef7eb2e8f9f7 | 1997 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 1998 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 1999 | |
<> | 144:ef7eb2e8f9f7 | 2000 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 2001 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2002 | |
<> | 144:ef7eb2e8f9f7 | 2003 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2004 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 2005 | |
<> | 144:ef7eb2e8f9f7 | 2006 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2007 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2008 | |
<> | 144:ef7eb2e8f9f7 | 2009 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2010 | } |
<> | 144:ef7eb2e8f9f7 | 2011 | else |
<> | 144:ef7eb2e8f9f7 | 2012 | { |
<> | 144:ef7eb2e8f9f7 | 2013 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2014 | } |
<> | 144:ef7eb2e8f9f7 | 2015 | } |
<> | 144:ef7eb2e8f9f7 | 2016 | /** |
<> | 144:ef7eb2e8f9f7 | 2017 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
<> | 144:ef7eb2e8f9f7 | 2018 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2019 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2020 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2021 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2022 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 2023 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 2024 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2025 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2026 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2027 | */ |
<> | 144:ef7eb2e8f9f7 | 2028 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 2029 | { |
<> | 144:ef7eb2e8f9f7 | 2030 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2031 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2032 | |
<> | 144:ef7eb2e8f9f7 | 2033 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2034 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 144:ef7eb2e8f9f7 | 2035 | |
Anna Bridge |
180:96ed750bd169 | 2036 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2037 | { |
Anna Bridge |
180:96ed750bd169 | 2038 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2039 | { |
<> | 144:ef7eb2e8f9f7 | 2040 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2041 | } |
Anna Bridge |
180:96ed750bd169 | 2042 | |
Anna Bridge |
180:96ed750bd169 | 2043 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 2044 | { |
<> | 144:ef7eb2e8f9f7 | 2045 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2046 | } |
<> | 144:ef7eb2e8f9f7 | 2047 | |
<> | 144:ef7eb2e8f9f7 | 2048 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2049 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2050 | |
<> | 144:ef7eb2e8f9f7 | 2051 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2052 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2053 | |
<> | 144:ef7eb2e8f9f7 | 2054 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 2055 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 2056 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2057 | |
<> | 144:ef7eb2e8f9f7 | 2058 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2059 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2060 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2061 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 2062 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 2063 | |
Anna Bridge |
180:96ed750bd169 | 2064 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2065 | { |
<> | 144:ef7eb2e8f9f7 | 2066 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2067 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2068 | } |
<> | 144:ef7eb2e8f9f7 | 2069 | else |
<> | 144:ef7eb2e8f9f7 | 2070 | { |
<> | 144:ef7eb2e8f9f7 | 2071 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2072 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 2073 | } |
<> | 144:ef7eb2e8f9f7 | 2074 | |
<> | 144:ef7eb2e8f9f7 | 2075 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 2076 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2077 | { |
Anna Bridge |
180:96ed750bd169 | 2078 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 2079 | { |
<> | 144:ef7eb2e8f9f7 | 2080 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2081 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2082 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2083 | } |
<> | 144:ef7eb2e8f9f7 | 2084 | else |
<> | 144:ef7eb2e8f9f7 | 2085 | { |
<> | 144:ef7eb2e8f9f7 | 2086 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2087 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2088 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2089 | } |
<> | 144:ef7eb2e8f9f7 | 2090 | } |
<> | 144:ef7eb2e8f9f7 | 2091 | |
<> | 144:ef7eb2e8f9f7 | 2092 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 2093 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 2094 | |
<> | 144:ef7eb2e8f9f7 | 2095 | /* Process Unlocked */ |
Anna Bridge |
180:96ed750bd169 | 2096 | __HAL_UNLOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 2097 | |
Anna Bridge |
180:96ed750bd169 | 2098 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2099 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2100 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2101 | |
<> | 144:ef7eb2e8f9f7 | 2102 | /* Enable ERR, TC, STOP, NACK, TXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2103 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 2104 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 2105 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 2106 | |
<> | 144:ef7eb2e8f9f7 | 2107 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2108 | } |
<> | 144:ef7eb2e8f9f7 | 2109 | else |
<> | 144:ef7eb2e8f9f7 | 2110 | { |
<> | 144:ef7eb2e8f9f7 | 2111 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2112 | } |
<> | 144:ef7eb2e8f9f7 | 2113 | } |
<> | 144:ef7eb2e8f9f7 | 2114 | |
<> | 144:ef7eb2e8f9f7 | 2115 | /** |
<> | 144:ef7eb2e8f9f7 | 2116 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
<> | 144:ef7eb2e8f9f7 | 2117 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2118 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2119 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2120 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2121 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 2122 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 2123 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2124 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2125 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2126 | */ |
<> | 144:ef7eb2e8f9f7 | 2127 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 2128 | { |
<> | 144:ef7eb2e8f9f7 | 2129 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2130 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2131 | |
<> | 144:ef7eb2e8f9f7 | 2132 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2133 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 144:ef7eb2e8f9f7 | 2134 | |
Anna Bridge |
180:96ed750bd169 | 2135 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2136 | { |
Anna Bridge |
180:96ed750bd169 | 2137 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2138 | { |
<> | 144:ef7eb2e8f9f7 | 2139 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2140 | } |
Anna Bridge |
180:96ed750bd169 | 2141 | |
Anna Bridge |
180:96ed750bd169 | 2142 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 2143 | { |
<> | 144:ef7eb2e8f9f7 | 2144 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2145 | } |
<> | 144:ef7eb2e8f9f7 | 2146 | |
<> | 144:ef7eb2e8f9f7 | 2147 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2148 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2149 | |
<> | 144:ef7eb2e8f9f7 | 2150 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2151 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2152 | |
<> | 144:ef7eb2e8f9f7 | 2153 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 2154 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 2155 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2156 | |
<> | 144:ef7eb2e8f9f7 | 2157 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2158 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2159 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2160 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 2161 | hi2c->XferISR = I2C_Master_ISR_IT; |
Anna Bridge |
180:96ed750bd169 | 2162 | |
Anna Bridge |
180:96ed750bd169 | 2163 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2164 | { |
<> | 144:ef7eb2e8f9f7 | 2165 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2166 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2167 | } |
<> | 144:ef7eb2e8f9f7 | 2168 | else |
<> | 144:ef7eb2e8f9f7 | 2169 | { |
<> | 144:ef7eb2e8f9f7 | 2170 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2171 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 2172 | } |
<> | 144:ef7eb2e8f9f7 | 2173 | |
<> | 144:ef7eb2e8f9f7 | 2174 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 2175 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2176 | { |
Anna Bridge |
180:96ed750bd169 | 2177 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 2178 | { |
<> | 144:ef7eb2e8f9f7 | 2179 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2180 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2181 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2182 | } |
<> | 144:ef7eb2e8f9f7 | 2183 | else |
<> | 144:ef7eb2e8f9f7 | 2184 | { |
<> | 144:ef7eb2e8f9f7 | 2185 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2186 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2187 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2188 | } |
<> | 144:ef7eb2e8f9f7 | 2189 | } |
<> | 144:ef7eb2e8f9f7 | 2190 | |
<> | 144:ef7eb2e8f9f7 | 2191 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 2192 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 2193 | |
<> | 144:ef7eb2e8f9f7 | 2194 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2195 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2196 | |
<> | 144:ef7eb2e8f9f7 | 2197 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2198 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2199 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2200 | |
<> | 144:ef7eb2e8f9f7 | 2201 | /* Enable ERR, TC, STOP, NACK, RXI interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2202 | /* possible to enable all of these */ |
<> | 144:ef7eb2e8f9f7 | 2203 | /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ |
<> | 144:ef7eb2e8f9f7 | 2204 | I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 2205 | |
<> | 144:ef7eb2e8f9f7 | 2206 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2207 | } |
<> | 144:ef7eb2e8f9f7 | 2208 | else |
<> | 144:ef7eb2e8f9f7 | 2209 | { |
<> | 144:ef7eb2e8f9f7 | 2210 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2211 | } |
<> | 144:ef7eb2e8f9f7 | 2212 | } |
<> | 144:ef7eb2e8f9f7 | 2213 | /** |
<> | 144:ef7eb2e8f9f7 | 2214 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
<> | 144:ef7eb2e8f9f7 | 2215 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2216 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2217 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2218 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2219 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 2220 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 2221 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2222 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2223 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2224 | */ |
<> | 144:ef7eb2e8f9f7 | 2225 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 2226 | { |
<> | 144:ef7eb2e8f9f7 | 2227 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2228 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2229 | |
<> | 144:ef7eb2e8f9f7 | 2230 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2231 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 144:ef7eb2e8f9f7 | 2232 | |
Anna Bridge |
180:96ed750bd169 | 2233 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2234 | { |
Anna Bridge |
180:96ed750bd169 | 2235 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2236 | { |
<> | 144:ef7eb2e8f9f7 | 2237 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2238 | } |
<> | 144:ef7eb2e8f9f7 | 2239 | |
Anna Bridge |
180:96ed750bd169 | 2240 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 2241 | { |
<> | 144:ef7eb2e8f9f7 | 2242 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2243 | } |
<> | 144:ef7eb2e8f9f7 | 2244 | |
<> | 144:ef7eb2e8f9f7 | 2245 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2246 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2247 | |
<> | 144:ef7eb2e8f9f7 | 2248 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2249 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2250 | |
<> | 144:ef7eb2e8f9f7 | 2251 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 2252 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 2253 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2254 | |
<> | 144:ef7eb2e8f9f7 | 2255 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2256 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2257 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2258 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 2259 | hi2c->XferISR = I2C_Master_ISR_DMA; |
Anna Bridge |
180:96ed750bd169 | 2260 | |
Anna Bridge |
180:96ed750bd169 | 2261 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2262 | { |
<> | 144:ef7eb2e8f9f7 | 2263 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2264 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2265 | } |
<> | 144:ef7eb2e8f9f7 | 2266 | else |
<> | 144:ef7eb2e8f9f7 | 2267 | { |
<> | 144:ef7eb2e8f9f7 | 2268 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2269 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 2270 | } |
<> | 144:ef7eb2e8f9f7 | 2271 | |
<> | 144:ef7eb2e8f9f7 | 2272 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 2273 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2274 | { |
Anna Bridge |
180:96ed750bd169 | 2275 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 2276 | { |
<> | 144:ef7eb2e8f9f7 | 2277 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2278 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2279 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2280 | } |
<> | 144:ef7eb2e8f9f7 | 2281 | else |
<> | 144:ef7eb2e8f9f7 | 2282 | { |
<> | 144:ef7eb2e8f9f7 | 2283 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2284 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2285 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2286 | } |
<> | 144:ef7eb2e8f9f7 | 2287 | } |
<> | 144:ef7eb2e8f9f7 | 2288 | |
<> | 144:ef7eb2e8f9f7 | 2289 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 2290 | hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; |
<> | 144:ef7eb2e8f9f7 | 2291 | |
<> | 144:ef7eb2e8f9f7 | 2292 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 2293 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 2294 | |
<> | 144:ef7eb2e8f9f7 | 2295 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 2296 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 2297 | hi2c->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 2298 | |
<> | 144:ef7eb2e8f9f7 | 2299 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 2300 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 2301 | |
<> | 144:ef7eb2e8f9f7 | 2302 | /* Send Slave Address */ |
<> | 144:ef7eb2e8f9f7 | 2303 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
<> | 144:ef7eb2e8f9f7 | 2304 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 2305 | |
<> | 144:ef7eb2e8f9f7 | 2306 | /* Update XferCount value */ |
<> | 144:ef7eb2e8f9f7 | 2307 | hi2c->XferCount -= hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 2308 | |
<> | 144:ef7eb2e8f9f7 | 2309 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2310 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2311 | |
<> | 144:ef7eb2e8f9f7 | 2312 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2313 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2314 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2315 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 2316 | I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); |
<> | 144:ef7eb2e8f9f7 | 2317 | |
<> | 144:ef7eb2e8f9f7 | 2318 | /* Enable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 2319 | hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 2320 | |
<> | 144:ef7eb2e8f9f7 | 2321 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2322 | } |
<> | 144:ef7eb2e8f9f7 | 2323 | else |
<> | 144:ef7eb2e8f9f7 | 2324 | { |
<> | 144:ef7eb2e8f9f7 | 2325 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2326 | } |
<> | 144:ef7eb2e8f9f7 | 2327 | } |
<> | 144:ef7eb2e8f9f7 | 2328 | |
<> | 144:ef7eb2e8f9f7 | 2329 | /** |
<> | 144:ef7eb2e8f9f7 | 2330 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
<> | 144:ef7eb2e8f9f7 | 2331 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2332 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2333 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2334 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2335 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 2336 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 2337 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2338 | * @param Size Amount of data to be read |
<> | 144:ef7eb2e8f9f7 | 2339 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2340 | */ |
<> | 144:ef7eb2e8f9f7 | 2341 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
<> | 144:ef7eb2e8f9f7 | 2342 | { |
<> | 144:ef7eb2e8f9f7 | 2343 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 2344 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2345 | |
<> | 144:ef7eb2e8f9f7 | 2346 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2347 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
<> | 144:ef7eb2e8f9f7 | 2348 | |
Anna Bridge |
180:96ed750bd169 | 2349 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2350 | { |
Anna Bridge |
180:96ed750bd169 | 2351 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2352 | { |
<> | 144:ef7eb2e8f9f7 | 2353 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2354 | } |
<> | 144:ef7eb2e8f9f7 | 2355 | |
Anna Bridge |
180:96ed750bd169 | 2356 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 2357 | { |
<> | 144:ef7eb2e8f9f7 | 2358 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2359 | } |
<> | 144:ef7eb2e8f9f7 | 2360 | |
<> | 144:ef7eb2e8f9f7 | 2361 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2362 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2363 | |
<> | 144:ef7eb2e8f9f7 | 2364 | /* Init tickstart for timeout management*/ |
<> | 144:ef7eb2e8f9f7 | 2365 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 2366 | |
<> | 144:ef7eb2e8f9f7 | 2367 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 2368 | hi2c->Mode = HAL_I2C_MODE_MEM; |
<> | 144:ef7eb2e8f9f7 | 2369 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2370 | |
<> | 144:ef7eb2e8f9f7 | 2371 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2372 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2373 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2374 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 2375 | hi2c->XferISR = I2C_Master_ISR_DMA; |
<> | 144:ef7eb2e8f9f7 | 2376 | |
Anna Bridge |
180:96ed750bd169 | 2377 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2378 | { |
<> | 144:ef7eb2e8f9f7 | 2379 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2380 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2381 | } |
<> | 144:ef7eb2e8f9f7 | 2382 | else |
<> | 144:ef7eb2e8f9f7 | 2383 | { |
<> | 144:ef7eb2e8f9f7 | 2384 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2385 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 2386 | } |
<> | 144:ef7eb2e8f9f7 | 2387 | |
<> | 144:ef7eb2e8f9f7 | 2388 | /* Send Slave Address and Memory Address */ |
Anna Bridge |
180:96ed750bd169 | 2389 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2390 | { |
Anna Bridge |
180:96ed750bd169 | 2391 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 2392 | { |
<> | 144:ef7eb2e8f9f7 | 2393 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2394 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2395 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2396 | } |
<> | 144:ef7eb2e8f9f7 | 2397 | else |
<> | 144:ef7eb2e8f9f7 | 2398 | { |
<> | 144:ef7eb2e8f9f7 | 2399 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2400 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2401 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2402 | } |
<> | 144:ef7eb2e8f9f7 | 2403 | } |
<> | 144:ef7eb2e8f9f7 | 2404 | |
<> | 144:ef7eb2e8f9f7 | 2405 | /* Set the I2C DMA transfer complete callback */ |
<> | 144:ef7eb2e8f9f7 | 2406 | hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; |
<> | 144:ef7eb2e8f9f7 | 2407 | |
<> | 144:ef7eb2e8f9f7 | 2408 | /* Set the DMA error callback */ |
<> | 144:ef7eb2e8f9f7 | 2409 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
<> | 144:ef7eb2e8f9f7 | 2410 | |
<> | 144:ef7eb2e8f9f7 | 2411 | /* Set the unused DMA callbacks to NULL */ |
<> | 144:ef7eb2e8f9f7 | 2412 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 2413 | hi2c->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 2414 | |
<> | 144:ef7eb2e8f9f7 | 2415 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 2416 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 2417 | |
<> | 144:ef7eb2e8f9f7 | 2418 | /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ |
Anna Bridge |
180:96ed750bd169 | 2419 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); |
<> | 144:ef7eb2e8f9f7 | 2420 | |
<> | 144:ef7eb2e8f9f7 | 2421 | /* Update XferCount value */ |
<> | 144:ef7eb2e8f9f7 | 2422 | hi2c->XferCount -= hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 2423 | |
<> | 144:ef7eb2e8f9f7 | 2424 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2425 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2426 | |
<> | 144:ef7eb2e8f9f7 | 2427 | /* Enable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 2428 | hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 2429 | |
<> | 144:ef7eb2e8f9f7 | 2430 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2431 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2432 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2433 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 2434 | I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); |
<> | 144:ef7eb2e8f9f7 | 2435 | |
<> | 144:ef7eb2e8f9f7 | 2436 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2437 | } |
<> | 144:ef7eb2e8f9f7 | 2438 | else |
<> | 144:ef7eb2e8f9f7 | 2439 | { |
<> | 144:ef7eb2e8f9f7 | 2440 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2441 | } |
<> | 144:ef7eb2e8f9f7 | 2442 | } |
<> | 144:ef7eb2e8f9f7 | 2443 | |
<> | 144:ef7eb2e8f9f7 | 2444 | /** |
<> | 156:95d6b41a828b | 2445 | * @brief Checks if target device is ready for communication. |
<> | 144:ef7eb2e8f9f7 | 2446 | * @note This function is used with Memory devices |
<> | 144:ef7eb2e8f9f7 | 2447 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2448 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2449 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2450 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2451 | * @param Trials Number of trials |
<> | 144:ef7eb2e8f9f7 | 2452 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 2453 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2454 | */ |
<> | 144:ef7eb2e8f9f7 | 2455 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 2456 | { |
<> | 144:ef7eb2e8f9f7 | 2457 | uint32_t tickstart = 0U; |
<> | 156:95d6b41a828b | 2458 | |
<> | 144:ef7eb2e8f9f7 | 2459 | __IO uint32_t I2C_Trials = 0U; |
<> | 156:95d6b41a828b | 2460 | |
Anna Bridge |
180:96ed750bd169 | 2461 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2462 | { |
Anna Bridge |
180:96ed750bd169 | 2463 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) |
<> | 144:ef7eb2e8f9f7 | 2464 | { |
<> | 144:ef7eb2e8f9f7 | 2465 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2466 | } |
<> | 144:ef7eb2e8f9f7 | 2467 | |
<> | 144:ef7eb2e8f9f7 | 2468 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2469 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2470 | |
<> | 144:ef7eb2e8f9f7 | 2471 | hi2c->State = HAL_I2C_STATE_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2472 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2473 | |
<> | 144:ef7eb2e8f9f7 | 2474 | do |
<> | 144:ef7eb2e8f9f7 | 2475 | { |
<> | 144:ef7eb2e8f9f7 | 2476 | /* Generate Start */ |
Anna Bridge |
180:96ed750bd169 | 2477 | hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); |
<> | 144:ef7eb2e8f9f7 | 2478 | |
<> | 144:ef7eb2e8f9f7 | 2479 | /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ |
<> | 144:ef7eb2e8f9f7 | 2480 | /* Wait until STOPF flag is set or a NACK flag is set*/ |
<> | 144:ef7eb2e8f9f7 | 2481 | tickstart = HAL_GetTick(); |
Anna Bridge |
180:96ed750bd169 | 2482 | while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT)) |
<> | 144:ef7eb2e8f9f7 | 2483 | { |
Anna Bridge |
180:96ed750bd169 | 2484 | if (Timeout != HAL_MAX_DELAY) |
Anna Bridge |
180:96ed750bd169 | 2485 | { |
Anna Bridge |
180:96ed750bd169 | 2486 | if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 2487 | { |
<> | 144:ef7eb2e8f9f7 | 2488 | /* Device is ready */ |
<> | 144:ef7eb2e8f9f7 | 2489 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2490 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2491 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2492 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2493 | } |
Anna Bridge |
180:96ed750bd169 | 2494 | } |
<> | 144:ef7eb2e8f9f7 | 2495 | } |
<> | 144:ef7eb2e8f9f7 | 2496 | |
<> | 144:ef7eb2e8f9f7 | 2497 | /* Check if the NACKF flag has not been set */ |
<> | 144:ef7eb2e8f9f7 | 2498 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) |
<> | 144:ef7eb2e8f9f7 | 2499 | { |
Anna Bridge |
180:96ed750bd169 | 2500 | /* Wait until STOPF flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 2501 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2502 | { |
<> | 144:ef7eb2e8f9f7 | 2503 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2504 | } |
<> | 144:ef7eb2e8f9f7 | 2505 | |
<> | 144:ef7eb2e8f9f7 | 2506 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 2507 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 2508 | |
<> | 144:ef7eb2e8f9f7 | 2509 | /* Device is ready */ |
<> | 144:ef7eb2e8f9f7 | 2510 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2511 | |
<> | 144:ef7eb2e8f9f7 | 2512 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2513 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2514 | |
<> | 144:ef7eb2e8f9f7 | 2515 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2516 | } |
<> | 144:ef7eb2e8f9f7 | 2517 | else |
<> | 144:ef7eb2e8f9f7 | 2518 | { |
<> | 144:ef7eb2e8f9f7 | 2519 | /* Wait until STOPF flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 2520 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2521 | { |
<> | 144:ef7eb2e8f9f7 | 2522 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2523 | } |
<> | 144:ef7eb2e8f9f7 | 2524 | |
<> | 144:ef7eb2e8f9f7 | 2525 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 2526 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 2527 | |
<> | 144:ef7eb2e8f9f7 | 2528 | /* Clear STOP Flag, auto generated with autoend*/ |
<> | 144:ef7eb2e8f9f7 | 2529 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 2530 | } |
<> | 144:ef7eb2e8f9f7 | 2531 | |
<> | 144:ef7eb2e8f9f7 | 2532 | /* Check if the maximum allowed number of trials has been reached */ |
<> | 144:ef7eb2e8f9f7 | 2533 | if (I2C_Trials++ == Trials) |
<> | 144:ef7eb2e8f9f7 | 2534 | { |
<> | 144:ef7eb2e8f9f7 | 2535 | /* Generate Stop */ |
<> | 144:ef7eb2e8f9f7 | 2536 | hi2c->Instance->CR2 |= I2C_CR2_STOP; |
<> | 144:ef7eb2e8f9f7 | 2537 | |
Anna Bridge |
180:96ed750bd169 | 2538 | /* Wait until STOPF flag is reset */ |
Anna Bridge |
180:96ed750bd169 | 2539 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 2540 | { |
<> | 144:ef7eb2e8f9f7 | 2541 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2542 | } |
<> | 144:ef7eb2e8f9f7 | 2543 | |
<> | 144:ef7eb2e8f9f7 | 2544 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 2545 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 2546 | } |
Anna Bridge |
180:96ed750bd169 | 2547 | } |
Anna Bridge |
180:96ed750bd169 | 2548 | while (I2C_Trials < Trials); |
<> | 144:ef7eb2e8f9f7 | 2549 | |
<> | 144:ef7eb2e8f9f7 | 2550 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2551 | |
<> | 144:ef7eb2e8f9f7 | 2552 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2553 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2554 | |
<> | 144:ef7eb2e8f9f7 | 2555 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 2556 | } |
<> | 144:ef7eb2e8f9f7 | 2557 | else |
<> | 144:ef7eb2e8f9f7 | 2558 | { |
<> | 144:ef7eb2e8f9f7 | 2559 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2560 | } |
<> | 144:ef7eb2e8f9f7 | 2561 | } |
<> | 144:ef7eb2e8f9f7 | 2562 | |
<> | 144:ef7eb2e8f9f7 | 2563 | /** |
<> | 144:ef7eb2e8f9f7 | 2564 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 2565 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
<> | 144:ef7eb2e8f9f7 | 2566 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2567 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2568 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2569 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2570 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2571 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2572 | * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS |
<> | 144:ef7eb2e8f9f7 | 2573 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2574 | */ |
<> | 144:ef7eb2e8f9f7 | 2575 | HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
<> | 144:ef7eb2e8f9f7 | 2576 | { |
<> | 144:ef7eb2e8f9f7 | 2577 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2578 | uint32_t xferrequest = I2C_GENERATE_START_WRITE; |
<> | 144:ef7eb2e8f9f7 | 2579 | |
<> | 144:ef7eb2e8f9f7 | 2580 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2581 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
<> | 144:ef7eb2e8f9f7 | 2582 | |
Anna Bridge |
180:96ed750bd169 | 2583 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2584 | { |
<> | 144:ef7eb2e8f9f7 | 2585 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2586 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2587 | |
<> | 144:ef7eb2e8f9f7 | 2588 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 2589 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 2590 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2591 | |
<> | 144:ef7eb2e8f9f7 | 2592 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2593 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2594 | hi2c->XferCount = Size; |
<> | 153:fa9ff456f731 | 2595 | hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); |
<> | 144:ef7eb2e8f9f7 | 2596 | hi2c->XferISR = I2C_Master_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 2597 | |
<> | 144:ef7eb2e8f9f7 | 2598 | /* If size > MAX_NBYTE_SIZE, use reload mode */ |
Anna Bridge |
180:96ed750bd169 | 2599 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2600 | { |
<> | 144:ef7eb2e8f9f7 | 2601 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2602 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2603 | } |
<> | 144:ef7eb2e8f9f7 | 2604 | else |
<> | 144:ef7eb2e8f9f7 | 2605 | { |
<> | 144:ef7eb2e8f9f7 | 2606 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2607 | xfermode = hi2c->XferOptions; |
<> | 144:ef7eb2e8f9f7 | 2608 | } |
<> | 144:ef7eb2e8f9f7 | 2609 | |
<> | 144:ef7eb2e8f9f7 | 2610 | /* Send Slave Address and set NBYTES to write */ |
<> | 144:ef7eb2e8f9f7 | 2611 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); |
<> | 144:ef7eb2e8f9f7 | 2612 | |
<> | 144:ef7eb2e8f9f7 | 2613 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2614 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2615 | |
<> | 144:ef7eb2e8f9f7 | 2616 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2617 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2618 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2619 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 2620 | |
<> | 144:ef7eb2e8f9f7 | 2621 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2622 | } |
<> | 144:ef7eb2e8f9f7 | 2623 | else |
<> | 144:ef7eb2e8f9f7 | 2624 | { |
<> | 144:ef7eb2e8f9f7 | 2625 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2626 | } |
<> | 144:ef7eb2e8f9f7 | 2627 | } |
<> | 144:ef7eb2e8f9f7 | 2628 | |
<> | 144:ef7eb2e8f9f7 | 2629 | /** |
<> | 144:ef7eb2e8f9f7 | 2630 | * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 2631 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
<> | 144:ef7eb2e8f9f7 | 2632 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2633 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2634 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2635 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2636 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2637 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2638 | * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS |
<> | 144:ef7eb2e8f9f7 | 2639 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2640 | */ |
<> | 144:ef7eb2e8f9f7 | 2641 | HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
<> | 144:ef7eb2e8f9f7 | 2642 | { |
<> | 144:ef7eb2e8f9f7 | 2643 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 2644 | uint32_t xferrequest = I2C_GENERATE_START_READ; |
<> | 144:ef7eb2e8f9f7 | 2645 | |
<> | 144:ef7eb2e8f9f7 | 2646 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2647 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
<> | 144:ef7eb2e8f9f7 | 2648 | |
Anna Bridge |
180:96ed750bd169 | 2649 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2650 | { |
<> | 144:ef7eb2e8f9f7 | 2651 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2652 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2653 | |
<> | 144:ef7eb2e8f9f7 | 2654 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 2655 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
<> | 144:ef7eb2e8f9f7 | 2656 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2657 | |
<> | 144:ef7eb2e8f9f7 | 2658 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2659 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2660 | hi2c->XferCount = Size; |
<> | 153:fa9ff456f731 | 2661 | hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); |
<> | 144:ef7eb2e8f9f7 | 2662 | hi2c->XferISR = I2C_Master_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 2663 | |
<> | 144:ef7eb2e8f9f7 | 2664 | /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ |
Anna Bridge |
180:96ed750bd169 | 2665 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 2666 | { |
<> | 144:ef7eb2e8f9f7 | 2667 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 2668 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 2669 | } |
<> | 144:ef7eb2e8f9f7 | 2670 | else |
<> | 144:ef7eb2e8f9f7 | 2671 | { |
<> | 144:ef7eb2e8f9f7 | 2672 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2673 | xfermode = hi2c->XferOptions; |
<> | 144:ef7eb2e8f9f7 | 2674 | } |
<> | 144:ef7eb2e8f9f7 | 2675 | |
<> | 144:ef7eb2e8f9f7 | 2676 | /* Send Slave Address and set NBYTES to read */ |
Anna Bridge |
180:96ed750bd169 | 2677 | I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); |
<> | 144:ef7eb2e8f9f7 | 2678 | |
<> | 144:ef7eb2e8f9f7 | 2679 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2680 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2681 | |
<> | 144:ef7eb2e8f9f7 | 2682 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2683 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2684 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2685 | I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 2686 | |
<> | 144:ef7eb2e8f9f7 | 2687 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2688 | } |
<> | 144:ef7eb2e8f9f7 | 2689 | else |
<> | 144:ef7eb2e8f9f7 | 2690 | { |
<> | 144:ef7eb2e8f9f7 | 2691 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2692 | } |
<> | 144:ef7eb2e8f9f7 | 2693 | } |
<> | 144:ef7eb2e8f9f7 | 2694 | |
<> | 144:ef7eb2e8f9f7 | 2695 | /** |
<> | 144:ef7eb2e8f9f7 | 2696 | * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 2697 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
<> | 144:ef7eb2e8f9f7 | 2698 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2699 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2700 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2701 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2702 | * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS |
<> | 144:ef7eb2e8f9f7 | 2703 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2704 | */ |
<> | 144:ef7eb2e8f9f7 | 2705 | HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
<> | 144:ef7eb2e8f9f7 | 2706 | { |
<> | 144:ef7eb2e8f9f7 | 2707 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2708 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
<> | 144:ef7eb2e8f9f7 | 2709 | |
Anna Bridge |
180:96ed750bd169 | 2710 | if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 2711 | { |
Anna Bridge |
180:96ed750bd169 | 2712 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2713 | { |
<> | 144:ef7eb2e8f9f7 | 2714 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2715 | } |
<> | 144:ef7eb2e8f9f7 | 2716 | |
<> | 144:ef7eb2e8f9f7 | 2717 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
<> | 144:ef7eb2e8f9f7 | 2718 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 2719 | |
<> | 144:ef7eb2e8f9f7 | 2720 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2721 | __HAL_LOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 2722 | |
<> | 156:95d6b41a828b | 2723 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
<> | 156:95d6b41a828b | 2724 | /* and then toggle the HAL slave RX state to TX state */ |
Anna Bridge |
180:96ed750bd169 | 2725 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
<> | 156:95d6b41a828b | 2726 | { |
<> | 156:95d6b41a828b | 2727 | /* Disable associated Interrupts */ |
<> | 156:95d6b41a828b | 2728 | I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 156:95d6b41a828b | 2729 | } |
<> | 144:ef7eb2e8f9f7 | 2730 | |
<> | 144:ef7eb2e8f9f7 | 2731 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 2732 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 2733 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2734 | |
<> | 144:ef7eb2e8f9f7 | 2735 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 2736 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 2737 | |
<> | 144:ef7eb2e8f9f7 | 2738 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2739 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2740 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2741 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2742 | hi2c->XferOptions = XferOptions; |
<> | 144:ef7eb2e8f9f7 | 2743 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 2744 | |
Anna Bridge |
180:96ed750bd169 | 2745 | if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) |
<> | 144:ef7eb2e8f9f7 | 2746 | { |
<> | 144:ef7eb2e8f9f7 | 2747 | /* Clear ADDR flag after prepare the transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2748 | /* This action will generate an acknowledge to the Master */ |
Anna Bridge |
180:96ed750bd169 | 2749 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 2750 | } |
<> | 144:ef7eb2e8f9f7 | 2751 | |
<> | 144:ef7eb2e8f9f7 | 2752 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2753 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2754 | |
<> | 144:ef7eb2e8f9f7 | 2755 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2756 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2757 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2758 | /* REnable ADDR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2759 | I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 2760 | |
<> | 144:ef7eb2e8f9f7 | 2761 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2762 | } |
<> | 144:ef7eb2e8f9f7 | 2763 | else |
<> | 144:ef7eb2e8f9f7 | 2764 | { |
<> | 144:ef7eb2e8f9f7 | 2765 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2766 | } |
<> | 144:ef7eb2e8f9f7 | 2767 | } |
<> | 144:ef7eb2e8f9f7 | 2768 | |
<> | 144:ef7eb2e8f9f7 | 2769 | /** |
<> | 144:ef7eb2e8f9f7 | 2770 | * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt |
<> | 144:ef7eb2e8f9f7 | 2771 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
<> | 144:ef7eb2e8f9f7 | 2772 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2773 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2774 | * @param pData Pointer to data buffer |
<> | 144:ef7eb2e8f9f7 | 2775 | * @param Size Amount of data to be sent |
<> | 144:ef7eb2e8f9f7 | 2776 | * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS |
<> | 144:ef7eb2e8f9f7 | 2777 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2778 | */ |
<> | 144:ef7eb2e8f9f7 | 2779 | HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
<> | 144:ef7eb2e8f9f7 | 2780 | { |
<> | 144:ef7eb2e8f9f7 | 2781 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 2782 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
<> | 144:ef7eb2e8f9f7 | 2783 | |
Anna Bridge |
180:96ed750bd169 | 2784 | if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 2785 | { |
Anna Bridge |
180:96ed750bd169 | 2786 | if ((pData == NULL) || (Size == 0U)) |
<> | 144:ef7eb2e8f9f7 | 2787 | { |
<> | 144:ef7eb2e8f9f7 | 2788 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2789 | } |
<> | 144:ef7eb2e8f9f7 | 2790 | |
<> | 144:ef7eb2e8f9f7 | 2791 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
<> | 144:ef7eb2e8f9f7 | 2792 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 2793 | |
<> | 144:ef7eb2e8f9f7 | 2794 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2795 | __HAL_LOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 2796 | |
<> | 156:95d6b41a828b | 2797 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
<> | 156:95d6b41a828b | 2798 | /* and then toggle the HAL slave TX state to RX state */ |
Anna Bridge |
180:96ed750bd169 | 2799 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
<> | 156:95d6b41a828b | 2800 | { |
<> | 156:95d6b41a828b | 2801 | /* Disable associated Interrupts */ |
<> | 156:95d6b41a828b | 2802 | I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 156:95d6b41a828b | 2803 | } |
Anna Bridge |
180:96ed750bd169 | 2804 | |
<> | 144:ef7eb2e8f9f7 | 2805 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 2806 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
<> | 144:ef7eb2e8f9f7 | 2807 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
<> | 144:ef7eb2e8f9f7 | 2808 | |
<> | 144:ef7eb2e8f9f7 | 2809 | /* Enable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 2810 | hi2c->Instance->CR2 &= ~I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 2811 | |
<> | 144:ef7eb2e8f9f7 | 2812 | /* Prepare transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2813 | hi2c->pBuffPtr = pData; |
<> | 144:ef7eb2e8f9f7 | 2814 | hi2c->XferCount = Size; |
<> | 144:ef7eb2e8f9f7 | 2815 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 2816 | hi2c->XferOptions = XferOptions; |
<> | 144:ef7eb2e8f9f7 | 2817 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 2818 | |
Anna Bridge |
180:96ed750bd169 | 2819 | if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) |
<> | 144:ef7eb2e8f9f7 | 2820 | { |
<> | 144:ef7eb2e8f9f7 | 2821 | /* Clear ADDR flag after prepare the transfer parameters */ |
<> | 144:ef7eb2e8f9f7 | 2822 | /* This action will generate an acknowledge to the Master */ |
Anna Bridge |
180:96ed750bd169 | 2823 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 2824 | } |
<> | 144:ef7eb2e8f9f7 | 2825 | |
<> | 144:ef7eb2e8f9f7 | 2826 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2827 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2828 | |
<> | 144:ef7eb2e8f9f7 | 2829 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2830 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2831 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2832 | /* REnable ADDR interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2833 | I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 2834 | |
<> | 144:ef7eb2e8f9f7 | 2835 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2836 | } |
<> | 144:ef7eb2e8f9f7 | 2837 | else |
<> | 144:ef7eb2e8f9f7 | 2838 | { |
<> | 144:ef7eb2e8f9f7 | 2839 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2840 | } |
<> | 144:ef7eb2e8f9f7 | 2841 | } |
<> | 144:ef7eb2e8f9f7 | 2842 | |
<> | 144:ef7eb2e8f9f7 | 2843 | /** |
<> | 144:ef7eb2e8f9f7 | 2844 | * @brief Enable the Address listen mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 2845 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2846 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2847 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2848 | */ |
<> | 144:ef7eb2e8f9f7 | 2849 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 2850 | { |
Anna Bridge |
180:96ed750bd169 | 2851 | if (hi2c->State == HAL_I2C_STATE_READY) |
<> | 144:ef7eb2e8f9f7 | 2852 | { |
<> | 144:ef7eb2e8f9f7 | 2853 | hi2c->State = HAL_I2C_STATE_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 2854 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 2855 | |
<> | 144:ef7eb2e8f9f7 | 2856 | /* Enable the Address Match interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2857 | I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 2858 | |
<> | 144:ef7eb2e8f9f7 | 2859 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2860 | } |
<> | 144:ef7eb2e8f9f7 | 2861 | else |
<> | 144:ef7eb2e8f9f7 | 2862 | { |
<> | 144:ef7eb2e8f9f7 | 2863 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2864 | } |
<> | 144:ef7eb2e8f9f7 | 2865 | } |
<> | 144:ef7eb2e8f9f7 | 2866 | |
<> | 144:ef7eb2e8f9f7 | 2867 | /** |
<> | 144:ef7eb2e8f9f7 | 2868 | * @brief Disable the Address listen mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 2869 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2870 | * the configuration information for the specified I2C |
<> | 144:ef7eb2e8f9f7 | 2871 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2872 | */ |
<> | 144:ef7eb2e8f9f7 | 2873 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 2874 | { |
<> | 144:ef7eb2e8f9f7 | 2875 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
<> | 144:ef7eb2e8f9f7 | 2876 | uint32_t tmp; |
<> | 144:ef7eb2e8f9f7 | 2877 | |
<> | 144:ef7eb2e8f9f7 | 2878 | /* Disable Address listen mode only if a transfer is not ongoing */ |
Anna Bridge |
180:96ed750bd169 | 2879 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 2880 | { |
<> | 144:ef7eb2e8f9f7 | 2881 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
<> | 144:ef7eb2e8f9f7 | 2882 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
<> | 144:ef7eb2e8f9f7 | 2883 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 2884 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 2885 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 2886 | |
<> | 144:ef7eb2e8f9f7 | 2887 | /* Disable the Address Match interrupt */ |
<> | 144:ef7eb2e8f9f7 | 2888 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 2889 | |
<> | 144:ef7eb2e8f9f7 | 2890 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2891 | } |
<> | 144:ef7eb2e8f9f7 | 2892 | else |
<> | 144:ef7eb2e8f9f7 | 2893 | { |
<> | 144:ef7eb2e8f9f7 | 2894 | return HAL_BUSY; |
<> | 144:ef7eb2e8f9f7 | 2895 | } |
<> | 144:ef7eb2e8f9f7 | 2896 | } |
<> | 144:ef7eb2e8f9f7 | 2897 | |
<> | 144:ef7eb2e8f9f7 | 2898 | /** |
<> | 144:ef7eb2e8f9f7 | 2899 | * @brief Abort a master I2C IT or DMA process communication with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 2900 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2901 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2902 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 2903 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 2904 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 2905 | */ |
<> | 144:ef7eb2e8f9f7 | 2906 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
<> | 144:ef7eb2e8f9f7 | 2907 | { |
Anna Bridge |
180:96ed750bd169 | 2908 | if (hi2c->Mode == HAL_I2C_MODE_MASTER) |
<> | 144:ef7eb2e8f9f7 | 2909 | { |
<> | 144:ef7eb2e8f9f7 | 2910 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 2911 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2912 | |
<> | 144:ef7eb2e8f9f7 | 2913 | /* Disable Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 2914 | I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 2915 | I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 2916 | |
<> | 144:ef7eb2e8f9f7 | 2917 | /* Set State at HAL_I2C_STATE_ABORT */ |
<> | 144:ef7eb2e8f9f7 | 2918 | hi2c->State = HAL_I2C_STATE_ABORT; |
<> | 144:ef7eb2e8f9f7 | 2919 | |
<> | 144:ef7eb2e8f9f7 | 2920 | /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ |
<> | 144:ef7eb2e8f9f7 | 2921 | /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ |
<> | 144:ef7eb2e8f9f7 | 2922 | I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); |
<> | 144:ef7eb2e8f9f7 | 2923 | |
<> | 144:ef7eb2e8f9f7 | 2924 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 2925 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 2926 | |
Anna Bridge |
180:96ed750bd169 | 2927 | /* Note : The I2C interrupts must be enabled after unlocking current process |
<> | 144:ef7eb2e8f9f7 | 2928 | to avoid the risk of I2C interrupt handle execution before current |
<> | 144:ef7eb2e8f9f7 | 2929 | process unlock */ |
<> | 144:ef7eb2e8f9f7 | 2930 | I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); |
<> | 144:ef7eb2e8f9f7 | 2931 | |
<> | 144:ef7eb2e8f9f7 | 2932 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 2933 | } |
<> | 144:ef7eb2e8f9f7 | 2934 | else |
<> | 144:ef7eb2e8f9f7 | 2935 | { |
<> | 144:ef7eb2e8f9f7 | 2936 | /* Wrong usage of abort function */ |
<> | 144:ef7eb2e8f9f7 | 2937 | /* This function should be used only in case of abort monitored by master device */ |
<> | 144:ef7eb2e8f9f7 | 2938 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 2939 | } |
<> | 144:ef7eb2e8f9f7 | 2940 | } |
<> | 144:ef7eb2e8f9f7 | 2941 | |
<> | 144:ef7eb2e8f9f7 | 2942 | /** |
<> | 144:ef7eb2e8f9f7 | 2943 | * @} |
<> | 144:ef7eb2e8f9f7 | 2944 | */ |
<> | 144:ef7eb2e8f9f7 | 2945 | |
<> | 144:ef7eb2e8f9f7 | 2946 | /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
<> | 144:ef7eb2e8f9f7 | 2947 | * @{ |
Anna Bridge |
180:96ed750bd169 | 2948 | */ |
<> | 144:ef7eb2e8f9f7 | 2949 | |
<> | 144:ef7eb2e8f9f7 | 2950 | /** |
<> | 144:ef7eb2e8f9f7 | 2951 | * @brief This function handles I2C event interrupt request. |
<> | 144:ef7eb2e8f9f7 | 2952 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2953 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2954 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2955 | */ |
<> | 144:ef7eb2e8f9f7 | 2956 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 2957 | { |
<> | 144:ef7eb2e8f9f7 | 2958 | /* Get current IT Flags and IT sources value */ |
<> | 144:ef7eb2e8f9f7 | 2959 | uint32_t itflags = READ_REG(hi2c->Instance->ISR); |
<> | 144:ef7eb2e8f9f7 | 2960 | uint32_t itsources = READ_REG(hi2c->Instance->CR1); |
<> | 144:ef7eb2e8f9f7 | 2961 | |
<> | 144:ef7eb2e8f9f7 | 2962 | /* I2C events treatment -------------------------------------*/ |
Anna Bridge |
180:96ed750bd169 | 2963 | if (hi2c->XferISR != NULL) |
<> | 144:ef7eb2e8f9f7 | 2964 | { |
<> | 144:ef7eb2e8f9f7 | 2965 | hi2c->XferISR(hi2c, itflags, itsources); |
<> | 144:ef7eb2e8f9f7 | 2966 | } |
<> | 144:ef7eb2e8f9f7 | 2967 | } |
<> | 144:ef7eb2e8f9f7 | 2968 | |
<> | 144:ef7eb2e8f9f7 | 2969 | /** |
<> | 144:ef7eb2e8f9f7 | 2970 | * @brief This function handles I2C error interrupt request. |
<> | 144:ef7eb2e8f9f7 | 2971 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 2972 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 2973 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 2974 | */ |
<> | 144:ef7eb2e8f9f7 | 2975 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 2976 | { |
<> | 144:ef7eb2e8f9f7 | 2977 | uint32_t itflags = READ_REG(hi2c->Instance->ISR); |
<> | 144:ef7eb2e8f9f7 | 2978 | uint32_t itsources = READ_REG(hi2c->Instance->CR1); |
<> | 144:ef7eb2e8f9f7 | 2979 | |
<> | 144:ef7eb2e8f9f7 | 2980 | /* I2C Bus error interrupt occurred ------------------------------------*/ |
Anna Bridge |
180:96ed750bd169 | 2981 | if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 2982 | { |
<> | 144:ef7eb2e8f9f7 | 2983 | hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; |
<> | 144:ef7eb2e8f9f7 | 2984 | |
<> | 144:ef7eb2e8f9f7 | 2985 | /* Clear BERR flag */ |
<> | 144:ef7eb2e8f9f7 | 2986 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
<> | 144:ef7eb2e8f9f7 | 2987 | } |
<> | 144:ef7eb2e8f9f7 | 2988 | |
<> | 144:ef7eb2e8f9f7 | 2989 | /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ |
Anna Bridge |
180:96ed750bd169 | 2990 | if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 2991 | { |
<> | 144:ef7eb2e8f9f7 | 2992 | hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; |
<> | 144:ef7eb2e8f9f7 | 2993 | |
<> | 144:ef7eb2e8f9f7 | 2994 | /* Clear OVR flag */ |
<> | 144:ef7eb2e8f9f7 | 2995 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
<> | 144:ef7eb2e8f9f7 | 2996 | } |
<> | 144:ef7eb2e8f9f7 | 2997 | |
<> | 144:ef7eb2e8f9f7 | 2998 | /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ |
Anna Bridge |
180:96ed750bd169 | 2999 | if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3000 | { |
<> | 144:ef7eb2e8f9f7 | 3001 | hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; |
<> | 144:ef7eb2e8f9f7 | 3002 | |
<> | 144:ef7eb2e8f9f7 | 3003 | /* Clear ARLO flag */ |
<> | 144:ef7eb2e8f9f7 | 3004 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
<> | 144:ef7eb2e8f9f7 | 3005 | } |
<> | 144:ef7eb2e8f9f7 | 3006 | |
<> | 144:ef7eb2e8f9f7 | 3007 | /* Call the Error Callback in case of Error detected */ |
Anna Bridge |
180:96ed750bd169 | 3008 | if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 3009 | { |
<> | 144:ef7eb2e8f9f7 | 3010 | I2C_ITError(hi2c, hi2c->ErrorCode); |
<> | 144:ef7eb2e8f9f7 | 3011 | } |
<> | 144:ef7eb2e8f9f7 | 3012 | } |
<> | 144:ef7eb2e8f9f7 | 3013 | |
<> | 144:ef7eb2e8f9f7 | 3014 | /** |
<> | 144:ef7eb2e8f9f7 | 3015 | * @brief Master Tx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3016 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3017 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3018 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3019 | */ |
<> | 156:95d6b41a828b | 3020 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3021 | { |
<> | 144:ef7eb2e8f9f7 | 3022 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3023 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3024 | |
<> | 144:ef7eb2e8f9f7 | 3025 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3026 | the HAL_I2C_MasterTxCpltCallback could be implemented in the user file |
<> | 156:95d6b41a828b | 3027 | */ |
<> | 144:ef7eb2e8f9f7 | 3028 | } |
<> | 144:ef7eb2e8f9f7 | 3029 | |
<> | 144:ef7eb2e8f9f7 | 3030 | /** |
<> | 144:ef7eb2e8f9f7 | 3031 | * @brief Master Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3032 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3033 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3034 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3035 | */ |
<> | 144:ef7eb2e8f9f7 | 3036 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3037 | { |
<> | 144:ef7eb2e8f9f7 | 3038 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3039 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3040 | |
<> | 144:ef7eb2e8f9f7 | 3041 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3042 | the HAL_I2C_MasterRxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3043 | */ |
<> | 144:ef7eb2e8f9f7 | 3044 | } |
<> | 144:ef7eb2e8f9f7 | 3045 | |
<> | 144:ef7eb2e8f9f7 | 3046 | /** @brief Slave Tx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3047 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3048 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3049 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3050 | */ |
<> | 156:95d6b41a828b | 3051 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3052 | { |
<> | 144:ef7eb2e8f9f7 | 3053 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3054 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3055 | |
<> | 144:ef7eb2e8f9f7 | 3056 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3057 | the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file |
<> | 156:95d6b41a828b | 3058 | */ |
<> | 144:ef7eb2e8f9f7 | 3059 | } |
<> | 144:ef7eb2e8f9f7 | 3060 | |
<> | 144:ef7eb2e8f9f7 | 3061 | /** |
<> | 144:ef7eb2e8f9f7 | 3062 | * @brief Slave Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3063 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3064 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3065 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3066 | */ |
<> | 144:ef7eb2e8f9f7 | 3067 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3068 | { |
<> | 144:ef7eb2e8f9f7 | 3069 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3070 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3071 | |
<> | 144:ef7eb2e8f9f7 | 3072 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3073 | the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3074 | */ |
<> | 144:ef7eb2e8f9f7 | 3075 | } |
<> | 144:ef7eb2e8f9f7 | 3076 | |
<> | 144:ef7eb2e8f9f7 | 3077 | /** |
<> | 144:ef7eb2e8f9f7 | 3078 | * @brief Slave Address Match callback. |
<> | 144:ef7eb2e8f9f7 | 3079 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3080 | * the configuration information for the specified I2C. |
Anna Bridge |
180:96ed750bd169 | 3081 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION |
Anna Bridge |
180:96ed750bd169 | 3082 | * @param AddrMatchCode Address Match Code |
<> | 144:ef7eb2e8f9f7 | 3083 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3084 | */ |
<> | 144:ef7eb2e8f9f7 | 3085 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
<> | 144:ef7eb2e8f9f7 | 3086 | { |
<> | 144:ef7eb2e8f9f7 | 3087 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3088 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3089 | UNUSED(TransferDirection); |
<> | 144:ef7eb2e8f9f7 | 3090 | UNUSED(AddrMatchCode); |
<> | 144:ef7eb2e8f9f7 | 3091 | |
<> | 144:ef7eb2e8f9f7 | 3092 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3093 | the HAL_I2C_AddrCallback() could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3094 | */ |
<> | 144:ef7eb2e8f9f7 | 3095 | } |
<> | 144:ef7eb2e8f9f7 | 3096 | |
<> | 144:ef7eb2e8f9f7 | 3097 | /** |
<> | 144:ef7eb2e8f9f7 | 3098 | * @brief Listen Complete callback. |
<> | 144:ef7eb2e8f9f7 | 3099 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3100 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3101 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3102 | */ |
<> | 144:ef7eb2e8f9f7 | 3103 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3104 | { |
<> | 144:ef7eb2e8f9f7 | 3105 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3106 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3107 | |
<> | 144:ef7eb2e8f9f7 | 3108 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3109 | the HAL_I2C_ListenCpltCallback() could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3110 | */ |
<> | 144:ef7eb2e8f9f7 | 3111 | } |
<> | 144:ef7eb2e8f9f7 | 3112 | |
<> | 144:ef7eb2e8f9f7 | 3113 | /** |
<> | 144:ef7eb2e8f9f7 | 3114 | * @brief Memory Tx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3115 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3116 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3117 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3118 | */ |
<> | 156:95d6b41a828b | 3119 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3120 | { |
<> | 144:ef7eb2e8f9f7 | 3121 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3122 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3123 | |
<> | 144:ef7eb2e8f9f7 | 3124 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3125 | the HAL_I2C_MemTxCpltCallback could be implemented in the user file |
<> | 156:95d6b41a828b | 3126 | */ |
<> | 144:ef7eb2e8f9f7 | 3127 | } |
<> | 144:ef7eb2e8f9f7 | 3128 | |
<> | 144:ef7eb2e8f9f7 | 3129 | /** |
<> | 144:ef7eb2e8f9f7 | 3130 | * @brief Memory Rx Transfer completed callback. |
<> | 144:ef7eb2e8f9f7 | 3131 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3132 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3133 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3134 | */ |
<> | 144:ef7eb2e8f9f7 | 3135 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3136 | { |
<> | 144:ef7eb2e8f9f7 | 3137 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3138 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3139 | |
<> | 144:ef7eb2e8f9f7 | 3140 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3141 | the HAL_I2C_MemRxCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3142 | */ |
<> | 144:ef7eb2e8f9f7 | 3143 | } |
<> | 144:ef7eb2e8f9f7 | 3144 | |
<> | 144:ef7eb2e8f9f7 | 3145 | /** |
<> | 144:ef7eb2e8f9f7 | 3146 | * @brief I2C error callback. |
<> | 144:ef7eb2e8f9f7 | 3147 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3148 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3149 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3150 | */ |
<> | 156:95d6b41a828b | 3151 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3152 | { |
<> | 144:ef7eb2e8f9f7 | 3153 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3154 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3155 | |
<> | 144:ef7eb2e8f9f7 | 3156 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3157 | the HAL_I2C_ErrorCallback could be implemented in the user file |
<> | 156:95d6b41a828b | 3158 | */ |
<> | 144:ef7eb2e8f9f7 | 3159 | } |
<> | 144:ef7eb2e8f9f7 | 3160 | |
<> | 144:ef7eb2e8f9f7 | 3161 | /** |
<> | 144:ef7eb2e8f9f7 | 3162 | * @brief I2C abort callback. |
<> | 144:ef7eb2e8f9f7 | 3163 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3164 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3165 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3166 | */ |
<> | 144:ef7eb2e8f9f7 | 3167 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3168 | { |
<> | 144:ef7eb2e8f9f7 | 3169 | /* Prevent unused argument(s) compilation warning */ |
<> | 144:ef7eb2e8f9f7 | 3170 | UNUSED(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3171 | |
<> | 144:ef7eb2e8f9f7 | 3172 | /* NOTE : This function should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 3173 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 3174 | */ |
<> | 144:ef7eb2e8f9f7 | 3175 | } |
<> | 144:ef7eb2e8f9f7 | 3176 | |
<> | 144:ef7eb2e8f9f7 | 3177 | /** |
<> | 144:ef7eb2e8f9f7 | 3178 | * @} |
<> | 144:ef7eb2e8f9f7 | 3179 | */ |
<> | 144:ef7eb2e8f9f7 | 3180 | |
<> | 144:ef7eb2e8f9f7 | 3181 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
<> | 144:ef7eb2e8f9f7 | 3182 | * @brief Peripheral State, Mode and Error functions |
<> | 144:ef7eb2e8f9f7 | 3183 | * |
<> | 156:95d6b41a828b | 3184 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 3185 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 3186 | ##### Peripheral State, Mode and Error functions ##### |
<> | 156:95d6b41a828b | 3187 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 3188 | [..] |
<> | 156:95d6b41a828b | 3189 | This subsection permit to get in run-time the status of the peripheral |
<> | 144:ef7eb2e8f9f7 | 3190 | and the data flow. |
<> | 144:ef7eb2e8f9f7 | 3191 | |
<> | 144:ef7eb2e8f9f7 | 3192 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 3193 | * @{ |
<> | 144:ef7eb2e8f9f7 | 3194 | */ |
<> | 144:ef7eb2e8f9f7 | 3195 | |
<> | 144:ef7eb2e8f9f7 | 3196 | /** |
<> | 144:ef7eb2e8f9f7 | 3197 | * @brief Return the I2C handle state. |
<> | 144:ef7eb2e8f9f7 | 3198 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3199 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3200 | * @retval HAL state |
<> | 144:ef7eb2e8f9f7 | 3201 | */ |
<> | 144:ef7eb2e8f9f7 | 3202 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3203 | { |
<> | 144:ef7eb2e8f9f7 | 3204 | /* Return I2C handle state */ |
<> | 144:ef7eb2e8f9f7 | 3205 | return hi2c->State; |
<> | 144:ef7eb2e8f9f7 | 3206 | } |
<> | 144:ef7eb2e8f9f7 | 3207 | |
<> | 144:ef7eb2e8f9f7 | 3208 | /** |
<> | 144:ef7eb2e8f9f7 | 3209 | * @brief Returns the I2C Master, Slave, Memory or no mode. |
<> | 144:ef7eb2e8f9f7 | 3210 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3211 | * the configuration information for I2C module |
<> | 144:ef7eb2e8f9f7 | 3212 | * @retval HAL mode |
<> | 144:ef7eb2e8f9f7 | 3213 | */ |
<> | 144:ef7eb2e8f9f7 | 3214 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3215 | { |
<> | 144:ef7eb2e8f9f7 | 3216 | return hi2c->Mode; |
<> | 144:ef7eb2e8f9f7 | 3217 | } |
<> | 144:ef7eb2e8f9f7 | 3218 | |
<> | 144:ef7eb2e8f9f7 | 3219 | /** |
<> | 144:ef7eb2e8f9f7 | 3220 | * @brief Return the I2C error code. |
<> | 144:ef7eb2e8f9f7 | 3221 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3222 | * the configuration information for the specified I2C. |
<> | 156:95d6b41a828b | 3223 | * @retval I2C Error Code |
<> | 144:ef7eb2e8f9f7 | 3224 | */ |
<> | 144:ef7eb2e8f9f7 | 3225 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3226 | { |
<> | 144:ef7eb2e8f9f7 | 3227 | return hi2c->ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 3228 | } |
<> | 144:ef7eb2e8f9f7 | 3229 | |
<> | 144:ef7eb2e8f9f7 | 3230 | /** |
<> | 144:ef7eb2e8f9f7 | 3231 | * @} |
Anna Bridge |
180:96ed750bd169 | 3232 | */ |
<> | 144:ef7eb2e8f9f7 | 3233 | |
<> | 144:ef7eb2e8f9f7 | 3234 | /** |
<> | 144:ef7eb2e8f9f7 | 3235 | * @} |
<> | 156:95d6b41a828b | 3236 | */ |
<> | 144:ef7eb2e8f9f7 | 3237 | |
<> | 144:ef7eb2e8f9f7 | 3238 | /** @addtogroup I2C_Private_Functions |
<> | 144:ef7eb2e8f9f7 | 3239 | * @{ |
<> | 144:ef7eb2e8f9f7 | 3240 | */ |
<> | 156:95d6b41a828b | 3241 | |
<> | 144:ef7eb2e8f9f7 | 3242 | /** |
<> | 144:ef7eb2e8f9f7 | 3243 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 3244 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3245 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3246 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3247 | * @param ITSources Interrupt sources enabled. |
<> | 144:ef7eb2e8f9f7 | 3248 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3249 | */ |
Anna Bridge |
180:96ed750bd169 | 3250 | static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) |
<> | 144:ef7eb2e8f9f7 | 3251 | { |
<> | 144:ef7eb2e8f9f7 | 3252 | uint16_t devaddress = 0U; |
<> | 144:ef7eb2e8f9f7 | 3253 | |
<> | 144:ef7eb2e8f9f7 | 3254 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 3255 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3256 | |
Anna Bridge |
180:96ed750bd169 | 3257 | if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3258 | { |
<> | 144:ef7eb2e8f9f7 | 3259 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3260 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3261 | |
<> | 144:ef7eb2e8f9f7 | 3262 | /* Set corresponding Error Code */ |
<> | 144:ef7eb2e8f9f7 | 3263 | /* No need to generate STOP, it is automatically done */ |
<> | 144:ef7eb2e8f9f7 | 3264 | /* Error callback will be send during stop flag treatment */ |
<> | 144:ef7eb2e8f9f7 | 3265 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 3266 | |
<> | 144:ef7eb2e8f9f7 | 3267 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 3268 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3269 | } |
Anna Bridge |
180:96ed750bd169 | 3270 | else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3271 | { |
<> | 144:ef7eb2e8f9f7 | 3272 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 3273 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 3274 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 3275 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 3276 | } |
Anna Bridge |
180:96ed750bd169 | 3277 | else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3278 | { |
<> | 144:ef7eb2e8f9f7 | 3279 | /* Write data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 3280 | hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 3281 | hi2c->XferSize--; |
Anna Bridge |
180:96ed750bd169 | 3282 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 3283 | } |
Anna Bridge |
180:96ed750bd169 | 3284 | else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3285 | { |
Anna Bridge |
180:96ed750bd169 | 3286 | if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U)) |
<> | 144:ef7eb2e8f9f7 | 3287 | { |
<> | 144:ef7eb2e8f9f7 | 3288 | devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); |
Anna Bridge |
180:96ed750bd169 | 3289 | |
Anna Bridge |
180:96ed750bd169 | 3290 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 3291 | { |
<> | 144:ef7eb2e8f9f7 | 3292 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 3293 | I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 3294 | } |
<> | 144:ef7eb2e8f9f7 | 3295 | else |
<> | 144:ef7eb2e8f9f7 | 3296 | { |
<> | 144:ef7eb2e8f9f7 | 3297 | hi2c->XferSize = hi2c->XferCount; |
Anna Bridge |
180:96ed750bd169 | 3298 | if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) |
<> | 144:ef7eb2e8f9f7 | 3299 | { |
<> | 144:ef7eb2e8f9f7 | 3300 | I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 3301 | } |
<> | 144:ef7eb2e8f9f7 | 3302 | else |
<> | 144:ef7eb2e8f9f7 | 3303 | { |
<> | 144:ef7eb2e8f9f7 | 3304 | I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 3305 | } |
<> | 144:ef7eb2e8f9f7 | 3306 | } |
<> | 144:ef7eb2e8f9f7 | 3307 | } |
<> | 144:ef7eb2e8f9f7 | 3308 | else |
<> | 144:ef7eb2e8f9f7 | 3309 | { |
<> | 144:ef7eb2e8f9f7 | 3310 | /* Call TxCpltCallback() if no stop mode is set */ |
Anna Bridge |
180:96ed750bd169 | 3311 | if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) |
<> | 144:ef7eb2e8f9f7 | 3312 | { |
<> | 144:ef7eb2e8f9f7 | 3313 | /* Call I2C Master Sequential complete process */ |
<> | 144:ef7eb2e8f9f7 | 3314 | I2C_ITMasterSequentialCplt(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3315 | } |
<> | 144:ef7eb2e8f9f7 | 3316 | else |
<> | 144:ef7eb2e8f9f7 | 3317 | { |
<> | 144:ef7eb2e8f9f7 | 3318 | /* Wrong size Status regarding TCR flag event */ |
<> | 144:ef7eb2e8f9f7 | 3319 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3320 | I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); |
<> | 144:ef7eb2e8f9f7 | 3321 | } |
<> | 144:ef7eb2e8f9f7 | 3322 | } |
<> | 144:ef7eb2e8f9f7 | 3323 | } |
Anna Bridge |
180:96ed750bd169 | 3324 | else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3325 | { |
Anna Bridge |
180:96ed750bd169 | 3326 | if (hi2c->XferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 3327 | { |
Anna Bridge |
180:96ed750bd169 | 3328 | if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) |
<> | 144:ef7eb2e8f9f7 | 3329 | { |
<> | 144:ef7eb2e8f9f7 | 3330 | /* Generate a stop condition in case of no transfer option */ |
Anna Bridge |
180:96ed750bd169 | 3331 | if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) |
<> | 144:ef7eb2e8f9f7 | 3332 | { |
<> | 144:ef7eb2e8f9f7 | 3333 | /* Generate Stop */ |
<> | 144:ef7eb2e8f9f7 | 3334 | hi2c->Instance->CR2 |= I2C_CR2_STOP; |
<> | 144:ef7eb2e8f9f7 | 3335 | } |
<> | 144:ef7eb2e8f9f7 | 3336 | else |
<> | 144:ef7eb2e8f9f7 | 3337 | { |
<> | 144:ef7eb2e8f9f7 | 3338 | /* Call I2C Master Sequential complete process */ |
<> | 144:ef7eb2e8f9f7 | 3339 | I2C_ITMasterSequentialCplt(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3340 | } |
<> | 144:ef7eb2e8f9f7 | 3341 | } |
<> | 144:ef7eb2e8f9f7 | 3342 | } |
<> | 144:ef7eb2e8f9f7 | 3343 | else |
<> | 144:ef7eb2e8f9f7 | 3344 | { |
<> | 144:ef7eb2e8f9f7 | 3345 | /* Wrong size Status regarding TC flag event */ |
<> | 144:ef7eb2e8f9f7 | 3346 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3347 | I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); |
<> | 144:ef7eb2e8f9f7 | 3348 | } |
<> | 144:ef7eb2e8f9f7 | 3349 | } |
<> | 144:ef7eb2e8f9f7 | 3350 | |
Anna Bridge |
180:96ed750bd169 | 3351 | if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3352 | { |
<> | 144:ef7eb2e8f9f7 | 3353 | /* Call I2C Master complete process */ |
<> | 144:ef7eb2e8f9f7 | 3354 | I2C_ITMasterCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3355 | } |
<> | 144:ef7eb2e8f9f7 | 3356 | |
<> | 144:ef7eb2e8f9f7 | 3357 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3358 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3359 | |
<> | 144:ef7eb2e8f9f7 | 3360 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3361 | } |
<> | 144:ef7eb2e8f9f7 | 3362 | |
<> | 144:ef7eb2e8f9f7 | 3363 | /** |
<> | 144:ef7eb2e8f9f7 | 3364 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. |
<> | 144:ef7eb2e8f9f7 | 3365 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3366 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3367 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3368 | * @param ITSources Interrupt sources enabled. |
<> | 144:ef7eb2e8f9f7 | 3369 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3370 | */ |
Anna Bridge |
180:96ed750bd169 | 3371 | static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) |
<> | 144:ef7eb2e8f9f7 | 3372 | { |
<> | 144:ef7eb2e8f9f7 | 3373 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 3374 | __HAL_LOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 3375 | |
Anna Bridge |
180:96ed750bd169 | 3376 | if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3377 | { |
<> | 144:ef7eb2e8f9f7 | 3378 | /* Check that I2C transfer finished */ |
<> | 144:ef7eb2e8f9f7 | 3379 | /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ |
<> | 144:ef7eb2e8f9f7 | 3380 | /* Mean XferCount == 0*/ |
<> | 144:ef7eb2e8f9f7 | 3381 | /* So clear Flag NACKF only */ |
Anna Bridge |
180:96ed750bd169 | 3382 | if (hi2c->XferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 3383 | { |
Anna Bridge |
180:96ed750bd169 | 3384 | if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \ |
Anna Bridge |
180:96ed750bd169 | 3385 | (hi2c->State == HAL_I2C_STATE_LISTEN)) |
<> | 144:ef7eb2e8f9f7 | 3386 | { |
<> | 144:ef7eb2e8f9f7 | 3387 | /* Call I2C Listen complete process */ |
<> | 144:ef7eb2e8f9f7 | 3388 | I2C_ITListenCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3389 | } |
Anna Bridge |
180:96ed750bd169 | 3390 | else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
<> | 144:ef7eb2e8f9f7 | 3391 | { |
<> | 144:ef7eb2e8f9f7 | 3392 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3393 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3394 | |
<> | 144:ef7eb2e8f9f7 | 3395 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 3396 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3397 | |
<> | 144:ef7eb2e8f9f7 | 3398 | /* Last Byte is Transmitted */ |
<> | 144:ef7eb2e8f9f7 | 3399 | /* Call I2C Slave Sequential complete process */ |
<> | 144:ef7eb2e8f9f7 | 3400 | I2C_ITSlaveSequentialCplt(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3401 | } |
<> | 144:ef7eb2e8f9f7 | 3402 | else |
<> | 144:ef7eb2e8f9f7 | 3403 | { |
<> | 144:ef7eb2e8f9f7 | 3404 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3405 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3406 | } |
<> | 144:ef7eb2e8f9f7 | 3407 | } |
<> | 144:ef7eb2e8f9f7 | 3408 | else |
<> | 144:ef7eb2e8f9f7 | 3409 | { |
<> | 144:ef7eb2e8f9f7 | 3410 | /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ |
<> | 144:ef7eb2e8f9f7 | 3411 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3412 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3413 | |
<> | 144:ef7eb2e8f9f7 | 3414 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 3415 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 3416 | } |
<> | 144:ef7eb2e8f9f7 | 3417 | } |
Anna Bridge |
180:96ed750bd169 | 3418 | else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3419 | { |
Anna Bridge |
180:96ed750bd169 | 3420 | if (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 3421 | { |
<> | 144:ef7eb2e8f9f7 | 3422 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 3423 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 3424 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 3425 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 3426 | } |
<> | 144:ef7eb2e8f9f7 | 3427 | |
Anna Bridge |
180:96ed750bd169 | 3428 | if ((hi2c->XferCount == 0U) && \ |
Anna Bridge |
180:96ed750bd169 | 3429 | (hi2c->XferOptions != I2C_NO_OPTION_FRAME)) |
<> | 144:ef7eb2e8f9f7 | 3430 | { |
<> | 144:ef7eb2e8f9f7 | 3431 | /* Call I2C Slave Sequential complete process */ |
<> | 144:ef7eb2e8f9f7 | 3432 | I2C_ITSlaveSequentialCplt(hi2c); |
Anna Bridge |
180:96ed750bd169 | 3433 | } |
<> | 144:ef7eb2e8f9f7 | 3434 | } |
Anna Bridge |
180:96ed750bd169 | 3435 | else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3436 | { |
<> | 144:ef7eb2e8f9f7 | 3437 | I2C_ITAddrCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3438 | } |
Anna Bridge |
180:96ed750bd169 | 3439 | else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3440 | { |
<> | 144:ef7eb2e8f9f7 | 3441 | /* Write data to TXDR only if XferCount not reach "0" */ |
<> | 144:ef7eb2e8f9f7 | 3442 | /* A TXIS flag can be set, during STOP treatment */ |
<> | 144:ef7eb2e8f9f7 | 3443 | /* Check if all Datas have already been sent */ |
<> | 144:ef7eb2e8f9f7 | 3444 | /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ |
Anna Bridge |
180:96ed750bd169 | 3445 | if (hi2c->XferCount > 0U) |
<> | 144:ef7eb2e8f9f7 | 3446 | { |
<> | 144:ef7eb2e8f9f7 | 3447 | /* Write data to TXDR */ |
<> | 144:ef7eb2e8f9f7 | 3448 | hi2c->Instance->TXDR = (*hi2c->pBuffPtr++); |
<> | 144:ef7eb2e8f9f7 | 3449 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 3450 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 3451 | } |
<> | 144:ef7eb2e8f9f7 | 3452 | else |
<> | 144:ef7eb2e8f9f7 | 3453 | { |
Anna Bridge |
180:96ed750bd169 | 3454 | if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME)) |
<> | 144:ef7eb2e8f9f7 | 3455 | { |
<> | 144:ef7eb2e8f9f7 | 3456 | /* Last Byte is Transmitted */ |
<> | 144:ef7eb2e8f9f7 | 3457 | /* Call I2C Slave Sequential complete process */ |
<> | 144:ef7eb2e8f9f7 | 3458 | I2C_ITSlaveSequentialCplt(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3459 | } |
<> | 144:ef7eb2e8f9f7 | 3460 | } |
<> | 144:ef7eb2e8f9f7 | 3461 | } |
<> | 144:ef7eb2e8f9f7 | 3462 | |
<> | 144:ef7eb2e8f9f7 | 3463 | /* Check if STOPF is set */ |
Anna Bridge |
180:96ed750bd169 | 3464 | if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3465 | { |
<> | 144:ef7eb2e8f9f7 | 3466 | /* Call I2C Slave complete process */ |
<> | 144:ef7eb2e8f9f7 | 3467 | I2C_ITSlaveCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3468 | } |
<> | 144:ef7eb2e8f9f7 | 3469 | |
<> | 144:ef7eb2e8f9f7 | 3470 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3471 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3472 | |
<> | 144:ef7eb2e8f9f7 | 3473 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3474 | } |
<> | 144:ef7eb2e8f9f7 | 3475 | |
<> | 144:ef7eb2e8f9f7 | 3476 | /** |
<> | 144:ef7eb2e8f9f7 | 3477 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 3478 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3479 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3480 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3481 | * @param ITSources Interrupt sources enabled. |
<> | 144:ef7eb2e8f9f7 | 3482 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3483 | */ |
Anna Bridge |
180:96ed750bd169 | 3484 | static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) |
<> | 144:ef7eb2e8f9f7 | 3485 | { |
<> | 144:ef7eb2e8f9f7 | 3486 | uint16_t devaddress = 0U; |
<> | 144:ef7eb2e8f9f7 | 3487 | uint32_t xfermode = 0U; |
<> | 144:ef7eb2e8f9f7 | 3488 | |
<> | 144:ef7eb2e8f9f7 | 3489 | /* Process Locked */ |
<> | 144:ef7eb2e8f9f7 | 3490 | __HAL_LOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3491 | |
Anna Bridge |
180:96ed750bd169 | 3492 | if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3493 | { |
<> | 144:ef7eb2e8f9f7 | 3494 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3495 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3496 | |
<> | 144:ef7eb2e8f9f7 | 3497 | /* Set corresponding Error Code */ |
<> | 144:ef7eb2e8f9f7 | 3498 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
Anna Bridge |
180:96ed750bd169 | 3499 | |
<> | 144:ef7eb2e8f9f7 | 3500 | /* No need to generate STOP, it is automatically done */ |
<> | 144:ef7eb2e8f9f7 | 3501 | /* But enable STOP interrupt, to treat it */ |
<> | 144:ef7eb2e8f9f7 | 3502 | /* Error callback will be send during stop flag treatment */ |
<> | 144:ef7eb2e8f9f7 | 3503 | I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); |
<> | 144:ef7eb2e8f9f7 | 3504 | |
<> | 144:ef7eb2e8f9f7 | 3505 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 3506 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3507 | } |
Anna Bridge |
180:96ed750bd169 | 3508 | else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3509 | { |
<> | 144:ef7eb2e8f9f7 | 3510 | /* Disable TC interrupt */ |
<> | 144:ef7eb2e8f9f7 | 3511 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); |
Anna Bridge |
180:96ed750bd169 | 3512 | |
Anna Bridge |
180:96ed750bd169 | 3513 | if (hi2c->XferCount != 0U) |
<> | 144:ef7eb2e8f9f7 | 3514 | { |
<> | 144:ef7eb2e8f9f7 | 3515 | /* Recover Slave address */ |
<> | 144:ef7eb2e8f9f7 | 3516 | devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); |
Anna Bridge |
180:96ed750bd169 | 3517 | |
<> | 144:ef7eb2e8f9f7 | 3518 | /* Prepare the new XferSize to transfer */ |
Anna Bridge |
180:96ed750bd169 | 3519 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 3520 | { |
<> | 144:ef7eb2e8f9f7 | 3521 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 3522 | xfermode = I2C_RELOAD_MODE; |
<> | 144:ef7eb2e8f9f7 | 3523 | } |
<> | 144:ef7eb2e8f9f7 | 3524 | else |
<> | 144:ef7eb2e8f9f7 | 3525 | { |
<> | 144:ef7eb2e8f9f7 | 3526 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 3527 | xfermode = I2C_AUTOEND_MODE; |
<> | 144:ef7eb2e8f9f7 | 3528 | } |
<> | 144:ef7eb2e8f9f7 | 3529 | |
<> | 144:ef7eb2e8f9f7 | 3530 | /* Set the new XferSize in Nbytes register */ |
<> | 144:ef7eb2e8f9f7 | 3531 | I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); |
<> | 144:ef7eb2e8f9f7 | 3532 | |
<> | 144:ef7eb2e8f9f7 | 3533 | /* Update XferCount value */ |
<> | 144:ef7eb2e8f9f7 | 3534 | hi2c->XferCount -= hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 3535 | |
<> | 144:ef7eb2e8f9f7 | 3536 | /* Enable DMA Request */ |
Anna Bridge |
180:96ed750bd169 | 3537 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 3538 | { |
<> | 144:ef7eb2e8f9f7 | 3539 | hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 3540 | } |
<> | 144:ef7eb2e8f9f7 | 3541 | else |
<> | 144:ef7eb2e8f9f7 | 3542 | { |
<> | 144:ef7eb2e8f9f7 | 3543 | hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 3544 | } |
<> | 144:ef7eb2e8f9f7 | 3545 | } |
<> | 144:ef7eb2e8f9f7 | 3546 | else |
<> | 144:ef7eb2e8f9f7 | 3547 | { |
<> | 144:ef7eb2e8f9f7 | 3548 | /* Wrong size Status regarding TCR flag event */ |
<> | 144:ef7eb2e8f9f7 | 3549 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3550 | I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); |
<> | 144:ef7eb2e8f9f7 | 3551 | } |
<> | 144:ef7eb2e8f9f7 | 3552 | } |
Anna Bridge |
180:96ed750bd169 | 3553 | else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3554 | { |
<> | 144:ef7eb2e8f9f7 | 3555 | /* Call I2C Master complete process */ |
<> | 144:ef7eb2e8f9f7 | 3556 | I2C_ITMasterCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3557 | } |
<> | 144:ef7eb2e8f9f7 | 3558 | |
<> | 144:ef7eb2e8f9f7 | 3559 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3560 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3561 | |
<> | 144:ef7eb2e8f9f7 | 3562 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3563 | } |
<> | 144:ef7eb2e8f9f7 | 3564 | |
<> | 144:ef7eb2e8f9f7 | 3565 | /** |
<> | 144:ef7eb2e8f9f7 | 3566 | * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. |
<> | 144:ef7eb2e8f9f7 | 3567 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3568 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3569 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3570 | * @param ITSources Interrupt sources enabled. |
<> | 144:ef7eb2e8f9f7 | 3571 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3572 | */ |
Anna Bridge |
180:96ed750bd169 | 3573 | static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources) |
<> | 144:ef7eb2e8f9f7 | 3574 | { |
<> | 144:ef7eb2e8f9f7 | 3575 | /* Process locked */ |
<> | 144:ef7eb2e8f9f7 | 3576 | __HAL_LOCK(hi2c); |
Anna Bridge |
180:96ed750bd169 | 3577 | |
Anna Bridge |
180:96ed750bd169 | 3578 | if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3579 | { |
<> | 144:ef7eb2e8f9f7 | 3580 | /* Check that I2C transfer finished */ |
<> | 144:ef7eb2e8f9f7 | 3581 | /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ |
<> | 144:ef7eb2e8f9f7 | 3582 | /* Mean XferCount == 0 */ |
<> | 144:ef7eb2e8f9f7 | 3583 | /* So clear Flag NACKF only */ |
Anna Bridge |
180:96ed750bd169 | 3584 | if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U) |
<> | 144:ef7eb2e8f9f7 | 3585 | { |
<> | 144:ef7eb2e8f9f7 | 3586 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3587 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3588 | } |
<> | 144:ef7eb2e8f9f7 | 3589 | else |
<> | 144:ef7eb2e8f9f7 | 3590 | { |
<> | 144:ef7eb2e8f9f7 | 3591 | /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ |
<> | 144:ef7eb2e8f9f7 | 3592 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3593 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
Anna Bridge |
180:96ed750bd169 | 3594 | |
<> | 144:ef7eb2e8f9f7 | 3595 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 3596 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 3597 | } |
<> | 144:ef7eb2e8f9f7 | 3598 | } |
Anna Bridge |
180:96ed750bd169 | 3599 | else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3600 | { |
<> | 144:ef7eb2e8f9f7 | 3601 | /* Clear ADDR flag */ |
<> | 144:ef7eb2e8f9f7 | 3602 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 3603 | } |
Anna Bridge |
180:96ed750bd169 | 3604 | else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 3605 | { |
<> | 144:ef7eb2e8f9f7 | 3606 | /* Call I2C Slave complete process */ |
<> | 144:ef7eb2e8f9f7 | 3607 | I2C_ITSlaveCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 3608 | } |
<> | 144:ef7eb2e8f9f7 | 3609 | |
<> | 144:ef7eb2e8f9f7 | 3610 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3611 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3612 | |
<> | 144:ef7eb2e8f9f7 | 3613 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3614 | } |
<> | 144:ef7eb2e8f9f7 | 3615 | |
<> | 144:ef7eb2e8f9f7 | 3616 | /** |
<> | 144:ef7eb2e8f9f7 | 3617 | * @brief Master sends target device address followed by internal memory address for write request. |
<> | 144:ef7eb2e8f9f7 | 3618 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3619 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3620 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 3621 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 3622 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 3623 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 3624 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 3625 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 3626 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3627 | */ |
<> | 144:ef7eb2e8f9f7 | 3628 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 3629 | { |
Anna Bridge |
180:96ed750bd169 | 3630 | I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 3631 | |
<> | 144:ef7eb2e8f9f7 | 3632 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3633 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3634 | { |
Anna Bridge |
180:96ed750bd169 | 3635 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 3636 | { |
<> | 144:ef7eb2e8f9f7 | 3637 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 3638 | } |
<> | 144:ef7eb2e8f9f7 | 3639 | else |
<> | 144:ef7eb2e8f9f7 | 3640 | { |
<> | 144:ef7eb2e8f9f7 | 3641 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3642 | } |
<> | 144:ef7eb2e8f9f7 | 3643 | } |
<> | 144:ef7eb2e8f9f7 | 3644 | |
<> | 144:ef7eb2e8f9f7 | 3645 | /* If Memory address size is 8Bit */ |
Anna Bridge |
180:96ed750bd169 | 3646 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 3647 | { |
<> | 144:ef7eb2e8f9f7 | 3648 | /* Send Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3649 | hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3650 | } |
<> | 144:ef7eb2e8f9f7 | 3651 | /* If Memory address size is 16Bit */ |
<> | 144:ef7eb2e8f9f7 | 3652 | else |
<> | 144:ef7eb2e8f9f7 | 3653 | { |
<> | 144:ef7eb2e8f9f7 | 3654 | /* Send MSB of Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3655 | hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3656 | |
<> | 144:ef7eb2e8f9f7 | 3657 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3658 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3659 | { |
Anna Bridge |
180:96ed750bd169 | 3660 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 3661 | { |
<> | 144:ef7eb2e8f9f7 | 3662 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 3663 | } |
<> | 144:ef7eb2e8f9f7 | 3664 | else |
<> | 144:ef7eb2e8f9f7 | 3665 | { |
<> | 144:ef7eb2e8f9f7 | 3666 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3667 | } |
<> | 144:ef7eb2e8f9f7 | 3668 | } |
Anna Bridge |
180:96ed750bd169 | 3669 | |
<> | 144:ef7eb2e8f9f7 | 3670 | /* Send LSB of Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3671 | hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3672 | } |
<> | 144:ef7eb2e8f9f7 | 3673 | |
<> | 144:ef7eb2e8f9f7 | 3674 | /* Wait until TCR flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3675 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3676 | { |
<> | 144:ef7eb2e8f9f7 | 3677 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3678 | } |
<> | 144:ef7eb2e8f9f7 | 3679 | |
Anna Bridge |
180:96ed750bd169 | 3680 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3681 | } |
<> | 144:ef7eb2e8f9f7 | 3682 | |
<> | 144:ef7eb2e8f9f7 | 3683 | /** |
<> | 144:ef7eb2e8f9f7 | 3684 | * @brief Master sends target device address followed by internal memory address for read request. |
<> | 144:ef7eb2e8f9f7 | 3685 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 3686 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 3687 | * @param DevAddress Target device address: The device 7 bits address value |
<> | 144:ef7eb2e8f9f7 | 3688 | * in datasheet must be shift at right before call interface |
<> | 144:ef7eb2e8f9f7 | 3689 | * @param MemAddress Internal memory address |
<> | 144:ef7eb2e8f9f7 | 3690 | * @param MemAddSize Size of internal memory address |
<> | 144:ef7eb2e8f9f7 | 3691 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 3692 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 3693 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 3694 | */ |
<> | 144:ef7eb2e8f9f7 | 3695 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 3696 | { |
Anna Bridge |
180:96ed750bd169 | 3697 | I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); |
<> | 144:ef7eb2e8f9f7 | 3698 | |
<> | 144:ef7eb2e8f9f7 | 3699 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3700 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3701 | { |
Anna Bridge |
180:96ed750bd169 | 3702 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 3703 | { |
<> | 144:ef7eb2e8f9f7 | 3704 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 3705 | } |
<> | 144:ef7eb2e8f9f7 | 3706 | else |
<> | 144:ef7eb2e8f9f7 | 3707 | { |
<> | 144:ef7eb2e8f9f7 | 3708 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3709 | } |
<> | 144:ef7eb2e8f9f7 | 3710 | } |
<> | 144:ef7eb2e8f9f7 | 3711 | |
<> | 144:ef7eb2e8f9f7 | 3712 | /* If Memory address size is 8Bit */ |
Anna Bridge |
180:96ed750bd169 | 3713 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
<> | 144:ef7eb2e8f9f7 | 3714 | { |
<> | 144:ef7eb2e8f9f7 | 3715 | /* Send Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3716 | hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3717 | } |
<> | 144:ef7eb2e8f9f7 | 3718 | /* If Memory address size is 16Bit */ |
<> | 144:ef7eb2e8f9f7 | 3719 | else |
<> | 144:ef7eb2e8f9f7 | 3720 | { |
<> | 144:ef7eb2e8f9f7 | 3721 | /* Send MSB of Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3722 | hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3723 | |
<> | 144:ef7eb2e8f9f7 | 3724 | /* Wait until TXIS flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3725 | if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3726 | { |
Anna Bridge |
180:96ed750bd169 | 3727 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
<> | 144:ef7eb2e8f9f7 | 3728 | { |
<> | 144:ef7eb2e8f9f7 | 3729 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 3730 | } |
<> | 144:ef7eb2e8f9f7 | 3731 | else |
<> | 144:ef7eb2e8f9f7 | 3732 | { |
<> | 144:ef7eb2e8f9f7 | 3733 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3734 | } |
<> | 144:ef7eb2e8f9f7 | 3735 | } |
Anna Bridge |
180:96ed750bd169 | 3736 | |
<> | 144:ef7eb2e8f9f7 | 3737 | /* Send LSB of Memory Address */ |
<> | 144:ef7eb2e8f9f7 | 3738 | hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); |
<> | 144:ef7eb2e8f9f7 | 3739 | } |
<> | 144:ef7eb2e8f9f7 | 3740 | |
<> | 144:ef7eb2e8f9f7 | 3741 | /* Wait until TC flag is set */ |
Anna Bridge |
180:96ed750bd169 | 3742 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 3743 | { |
<> | 144:ef7eb2e8f9f7 | 3744 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 3745 | } |
Anna Bridge |
180:96ed750bd169 | 3746 | |
<> | 144:ef7eb2e8f9f7 | 3747 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 3748 | } |
<> | 144:ef7eb2e8f9f7 | 3749 | |
<> | 144:ef7eb2e8f9f7 | 3750 | /** |
<> | 144:ef7eb2e8f9f7 | 3751 | * @brief I2C Address complete process callback. |
<> | 144:ef7eb2e8f9f7 | 3752 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 3753 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3754 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3755 | */ |
<> | 144:ef7eb2e8f9f7 | 3756 | static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) |
<> | 144:ef7eb2e8f9f7 | 3757 | { |
<> | 144:ef7eb2e8f9f7 | 3758 | uint8_t transferdirection = 0U; |
<> | 144:ef7eb2e8f9f7 | 3759 | uint16_t slaveaddrcode = 0U; |
<> | 144:ef7eb2e8f9f7 | 3760 | uint16_t ownadd1code = 0U; |
<> | 144:ef7eb2e8f9f7 | 3761 | uint16_t ownadd2code = 0U; |
<> | 144:ef7eb2e8f9f7 | 3762 | |
<> | 156:95d6b41a828b | 3763 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 3764 | UNUSED(ITFlags); |
<> | 156:95d6b41a828b | 3765 | |
<> | 144:ef7eb2e8f9f7 | 3766 | /* In case of Listen state, need to inform upper layer of address match code event */ |
Anna Bridge |
180:96ed750bd169 | 3767 | if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 3768 | { |
<> | 144:ef7eb2e8f9f7 | 3769 | transferdirection = I2C_GET_DIR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3770 | slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3771 | ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3772 | ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3773 | |
<> | 144:ef7eb2e8f9f7 | 3774 | /* If 10bits addressing mode is selected */ |
Anna Bridge |
180:96ed750bd169 | 3775 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
<> | 144:ef7eb2e8f9f7 | 3776 | { |
Anna Bridge |
180:96ed750bd169 | 3777 | if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) |
<> | 144:ef7eb2e8f9f7 | 3778 | { |
<> | 144:ef7eb2e8f9f7 | 3779 | slaveaddrcode = ownadd1code; |
<> | 144:ef7eb2e8f9f7 | 3780 | hi2c->AddrEventCount++; |
Anna Bridge |
180:96ed750bd169 | 3781 | if (hi2c->AddrEventCount == 2U) |
<> | 144:ef7eb2e8f9f7 | 3782 | { |
<> | 144:ef7eb2e8f9f7 | 3783 | /* Reset Address Event counter */ |
<> | 144:ef7eb2e8f9f7 | 3784 | hi2c->AddrEventCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 3785 | |
<> | 144:ef7eb2e8f9f7 | 3786 | /* Clear ADDR flag */ |
Anna Bridge |
180:96ed750bd169 | 3787 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 3788 | |
<> | 144:ef7eb2e8f9f7 | 3789 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3790 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3791 | |
<> | 144:ef7eb2e8f9f7 | 3792 | /* Call Slave Addr callback */ |
<> | 144:ef7eb2e8f9f7 | 3793 | HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); |
<> | 144:ef7eb2e8f9f7 | 3794 | } |
<> | 144:ef7eb2e8f9f7 | 3795 | } |
<> | 144:ef7eb2e8f9f7 | 3796 | else |
<> | 144:ef7eb2e8f9f7 | 3797 | { |
<> | 144:ef7eb2e8f9f7 | 3798 | slaveaddrcode = ownadd2code; |
<> | 144:ef7eb2e8f9f7 | 3799 | |
<> | 144:ef7eb2e8f9f7 | 3800 | /* Disable ADDR Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3801 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 3802 | |
<> | 144:ef7eb2e8f9f7 | 3803 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3804 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3805 | |
<> | 144:ef7eb2e8f9f7 | 3806 | /* Call Slave Addr callback */ |
<> | 144:ef7eb2e8f9f7 | 3807 | HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); |
<> | 144:ef7eb2e8f9f7 | 3808 | } |
<> | 144:ef7eb2e8f9f7 | 3809 | } |
<> | 144:ef7eb2e8f9f7 | 3810 | /* else 7 bits addressing mode is selected */ |
<> | 144:ef7eb2e8f9f7 | 3811 | else |
<> | 144:ef7eb2e8f9f7 | 3812 | { |
<> | 144:ef7eb2e8f9f7 | 3813 | /* Disable ADDR Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3814 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); |
<> | 144:ef7eb2e8f9f7 | 3815 | |
<> | 144:ef7eb2e8f9f7 | 3816 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3817 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3818 | |
<> | 144:ef7eb2e8f9f7 | 3819 | /* Call Slave Addr callback */ |
<> | 144:ef7eb2e8f9f7 | 3820 | HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); |
<> | 144:ef7eb2e8f9f7 | 3821 | } |
<> | 144:ef7eb2e8f9f7 | 3822 | } |
<> | 144:ef7eb2e8f9f7 | 3823 | /* Else clear address flag only */ |
<> | 144:ef7eb2e8f9f7 | 3824 | else |
<> | 144:ef7eb2e8f9f7 | 3825 | { |
<> | 144:ef7eb2e8f9f7 | 3826 | /* Clear ADDR flag */ |
<> | 144:ef7eb2e8f9f7 | 3827 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 3828 | |
<> | 144:ef7eb2e8f9f7 | 3829 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3830 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3831 | } |
<> | 144:ef7eb2e8f9f7 | 3832 | } |
<> | 144:ef7eb2e8f9f7 | 3833 | |
<> | 144:ef7eb2e8f9f7 | 3834 | /** |
<> | 144:ef7eb2e8f9f7 | 3835 | * @brief I2C Master sequential complete process. |
<> | 144:ef7eb2e8f9f7 | 3836 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 3837 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3838 | */ |
<> | 144:ef7eb2e8f9f7 | 3839 | static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3840 | { |
<> | 144:ef7eb2e8f9f7 | 3841 | /* Reset I2C handle mode */ |
<> | 144:ef7eb2e8f9f7 | 3842 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3843 | |
<> | 144:ef7eb2e8f9f7 | 3844 | /* No Generate Stop, to permit restart mode */ |
<> | 144:ef7eb2e8f9f7 | 3845 | /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ |
<> | 144:ef7eb2e8f9f7 | 3846 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 3847 | { |
<> | 144:ef7eb2e8f9f7 | 3848 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 3849 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 3850 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 3851 | |
<> | 144:ef7eb2e8f9f7 | 3852 | /* Disable Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3853 | I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 3854 | |
<> | 144:ef7eb2e8f9f7 | 3855 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3856 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3857 | |
<> | 144:ef7eb2e8f9f7 | 3858 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3859 | HAL_I2C_MasterTxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3860 | } |
<> | 144:ef7eb2e8f9f7 | 3861 | /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ |
<> | 144:ef7eb2e8f9f7 | 3862 | else |
<> | 144:ef7eb2e8f9f7 | 3863 | { |
<> | 144:ef7eb2e8f9f7 | 3864 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 3865 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 3866 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 3867 | |
<> | 144:ef7eb2e8f9f7 | 3868 | /* Disable Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3869 | I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 3870 | |
<> | 144:ef7eb2e8f9f7 | 3871 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3872 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3873 | |
<> | 144:ef7eb2e8f9f7 | 3874 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3875 | HAL_I2C_MasterRxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3876 | } |
<> | 144:ef7eb2e8f9f7 | 3877 | } |
<> | 144:ef7eb2e8f9f7 | 3878 | |
<> | 144:ef7eb2e8f9f7 | 3879 | /** |
<> | 144:ef7eb2e8f9f7 | 3880 | * @brief I2C Slave sequential complete process. |
<> | 144:ef7eb2e8f9f7 | 3881 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 3882 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3883 | */ |
<> | 144:ef7eb2e8f9f7 | 3884 | static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 3885 | { |
<> | 144:ef7eb2e8f9f7 | 3886 | /* Reset I2C handle mode */ |
<> | 144:ef7eb2e8f9f7 | 3887 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3888 | |
Anna Bridge |
180:96ed750bd169 | 3889 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 3890 | { |
<> | 144:ef7eb2e8f9f7 | 3891 | /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ |
<> | 144:ef7eb2e8f9f7 | 3892 | hi2c->State = HAL_I2C_STATE_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 3893 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
<> | 144:ef7eb2e8f9f7 | 3894 | |
<> | 144:ef7eb2e8f9f7 | 3895 | /* Disable Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3896 | I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 3897 | |
<> | 144:ef7eb2e8f9f7 | 3898 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3899 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3900 | |
<> | 144:ef7eb2e8f9f7 | 3901 | /* Call the Tx complete callback to inform upper layer of the end of transmit process */ |
<> | 144:ef7eb2e8f9f7 | 3902 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3903 | } |
<> | 144:ef7eb2e8f9f7 | 3904 | |
Anna Bridge |
180:96ed750bd169 | 3905 | else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 3906 | { |
<> | 144:ef7eb2e8f9f7 | 3907 | /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ |
<> | 144:ef7eb2e8f9f7 | 3908 | hi2c->State = HAL_I2C_STATE_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 3909 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
<> | 144:ef7eb2e8f9f7 | 3910 | |
<> | 144:ef7eb2e8f9f7 | 3911 | /* Disable Interrupts */ |
<> | 144:ef7eb2e8f9f7 | 3912 | I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 3913 | |
<> | 144:ef7eb2e8f9f7 | 3914 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3915 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3916 | |
<> | 144:ef7eb2e8f9f7 | 3917 | /* Call the Rx complete callback to inform upper layer of the end of receive process */ |
<> | 144:ef7eb2e8f9f7 | 3918 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3919 | } |
<> | 144:ef7eb2e8f9f7 | 3920 | } |
<> | 144:ef7eb2e8f9f7 | 3921 | |
<> | 144:ef7eb2e8f9f7 | 3922 | /** |
<> | 144:ef7eb2e8f9f7 | 3923 | * @brief I2C Master complete process. |
<> | 144:ef7eb2e8f9f7 | 3924 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 3925 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 3926 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 3927 | */ |
<> | 144:ef7eb2e8f9f7 | 3928 | static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) |
<> | 144:ef7eb2e8f9f7 | 3929 | { |
<> | 144:ef7eb2e8f9f7 | 3930 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 3931 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 3932 | |
<> | 144:ef7eb2e8f9f7 | 3933 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 3934 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3935 | |
<> | 144:ef7eb2e8f9f7 | 3936 | /* Reset handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 3937 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3938 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 3939 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 3940 | |
Anna Bridge |
180:96ed750bd169 | 3941 | if ((ITFlags & I2C_FLAG_AF) != RESET) |
<> | 144:ef7eb2e8f9f7 | 3942 | { |
<> | 144:ef7eb2e8f9f7 | 3943 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 3944 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 3945 | |
<> | 144:ef7eb2e8f9f7 | 3946 | /* Set acknowledge error code */ |
<> | 144:ef7eb2e8f9f7 | 3947 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 3948 | } |
<> | 144:ef7eb2e8f9f7 | 3949 | |
<> | 144:ef7eb2e8f9f7 | 3950 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 3951 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3952 | |
<> | 144:ef7eb2e8f9f7 | 3953 | /* Disable Interrupts */ |
Anna Bridge |
180:96ed750bd169 | 3954 | I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 3955 | |
<> | 144:ef7eb2e8f9f7 | 3956 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
Anna Bridge |
180:96ed750bd169 | 3957 | if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT)) |
<> | 144:ef7eb2e8f9f7 | 3958 | { |
<> | 144:ef7eb2e8f9f7 | 3959 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3960 | I2C_ITError(hi2c, hi2c->ErrorCode); |
<> | 144:ef7eb2e8f9f7 | 3961 | } |
<> | 144:ef7eb2e8f9f7 | 3962 | /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ |
Anna Bridge |
180:96ed750bd169 | 3963 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
<> | 144:ef7eb2e8f9f7 | 3964 | { |
<> | 144:ef7eb2e8f9f7 | 3965 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 3966 | |
<> | 144:ef7eb2e8f9f7 | 3967 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
<> | 144:ef7eb2e8f9f7 | 3968 | { |
<> | 144:ef7eb2e8f9f7 | 3969 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3970 | |
<> | 144:ef7eb2e8f9f7 | 3971 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3972 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3973 | |
<> | 144:ef7eb2e8f9f7 | 3974 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3975 | HAL_I2C_MemTxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3976 | } |
<> | 144:ef7eb2e8f9f7 | 3977 | else |
<> | 144:ef7eb2e8f9f7 | 3978 | { |
<> | 144:ef7eb2e8f9f7 | 3979 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3980 | |
<> | 144:ef7eb2e8f9f7 | 3981 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3982 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3983 | |
<> | 144:ef7eb2e8f9f7 | 3984 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 3985 | HAL_I2C_MasterTxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3986 | } |
<> | 144:ef7eb2e8f9f7 | 3987 | } |
<> | 144:ef7eb2e8f9f7 | 3988 | /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ |
Anna Bridge |
180:96ed750bd169 | 3989 | else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 3990 | { |
<> | 144:ef7eb2e8f9f7 | 3991 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 3992 | |
<> | 144:ef7eb2e8f9f7 | 3993 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
<> | 144:ef7eb2e8f9f7 | 3994 | { |
<> | 144:ef7eb2e8f9f7 | 3995 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 3996 | |
<> | 144:ef7eb2e8f9f7 | 3997 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 3998 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 3999 | |
<> | 144:ef7eb2e8f9f7 | 4000 | HAL_I2C_MemRxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4001 | } |
<> | 144:ef7eb2e8f9f7 | 4002 | else |
<> | 144:ef7eb2e8f9f7 | 4003 | { |
<> | 144:ef7eb2e8f9f7 | 4004 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4005 | |
<> | 144:ef7eb2e8f9f7 | 4006 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4007 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4008 | |
<> | 144:ef7eb2e8f9f7 | 4009 | HAL_I2C_MasterRxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4010 | } |
<> | 144:ef7eb2e8f9f7 | 4011 | } |
<> | 144:ef7eb2e8f9f7 | 4012 | } |
<> | 144:ef7eb2e8f9f7 | 4013 | |
<> | 144:ef7eb2e8f9f7 | 4014 | /** |
<> | 144:ef7eb2e8f9f7 | 4015 | * @brief I2C Slave complete process. |
<> | 144:ef7eb2e8f9f7 | 4016 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 4017 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 4018 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4019 | */ |
<> | 144:ef7eb2e8f9f7 | 4020 | static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) |
<> | 144:ef7eb2e8f9f7 | 4021 | { |
<> | 144:ef7eb2e8f9f7 | 4022 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 4023 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 4024 | |
<> | 144:ef7eb2e8f9f7 | 4025 | /* Clear ADDR flag */ |
Anna Bridge |
180:96ed750bd169 | 4026 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); |
<> | 144:ef7eb2e8f9f7 | 4027 | |
<> | 144:ef7eb2e8f9f7 | 4028 | /* Disable all interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4029 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); |
<> | 144:ef7eb2e8f9f7 | 4030 | |
<> | 144:ef7eb2e8f9f7 | 4031 | /* Disable Address Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4032 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 4033 | |
<> | 144:ef7eb2e8f9f7 | 4034 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 4035 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4036 | |
<> | 144:ef7eb2e8f9f7 | 4037 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 4038 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4039 | |
<> | 144:ef7eb2e8f9f7 | 4040 | /* If a DMA is ongoing, Update handle size context */ |
Anna Bridge |
180:96ed750bd169 | 4041 | if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) || |
Anna Bridge |
180:96ed750bd169 | 4042 | ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)) |
<> | 144:ef7eb2e8f9f7 | 4043 | { |
<> | 144:ef7eb2e8f9f7 | 4044 | hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4045 | } |
<> | 144:ef7eb2e8f9f7 | 4046 | |
<> | 144:ef7eb2e8f9f7 | 4047 | /* All data are not transferred, so set error code accordingly */ |
Anna Bridge |
180:96ed750bd169 | 4048 | if (hi2c->XferCount != 0U) |
<> | 144:ef7eb2e8f9f7 | 4049 | { |
<> | 144:ef7eb2e8f9f7 | 4050 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4051 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 4052 | } |
<> | 144:ef7eb2e8f9f7 | 4053 | |
<> | 144:ef7eb2e8f9f7 | 4054 | /* Store Last receive data if any */ |
Anna Bridge |
180:96ed750bd169 | 4055 | if (((ITFlags & I2C_FLAG_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 4056 | { |
<> | 144:ef7eb2e8f9f7 | 4057 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 4058 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 4059 | |
Anna Bridge |
180:96ed750bd169 | 4060 | if ((hi2c->XferSize > 0U)) |
<> | 144:ef7eb2e8f9f7 | 4061 | { |
<> | 144:ef7eb2e8f9f7 | 4062 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 4063 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 4064 | |
<> | 144:ef7eb2e8f9f7 | 4065 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4066 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 4067 | } |
<> | 144:ef7eb2e8f9f7 | 4068 | } |
<> | 144:ef7eb2e8f9f7 | 4069 | |
<> | 144:ef7eb2e8f9f7 | 4070 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4071 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4072 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 4073 | |
Anna Bridge |
180:96ed750bd169 | 4074 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
<> | 144:ef7eb2e8f9f7 | 4075 | { |
<> | 144:ef7eb2e8f9f7 | 4076 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4077 | I2C_ITError(hi2c, hi2c->ErrorCode); |
<> | 144:ef7eb2e8f9f7 | 4078 | |
<> | 144:ef7eb2e8f9f7 | 4079 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
Anna Bridge |
180:96ed750bd169 | 4080 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 4081 | { |
<> | 144:ef7eb2e8f9f7 | 4082 | /* Call I2C Listen complete process */ |
<> | 144:ef7eb2e8f9f7 | 4083 | I2C_ITListenCplt(hi2c, ITFlags); |
<> | 144:ef7eb2e8f9f7 | 4084 | } |
<> | 144:ef7eb2e8f9f7 | 4085 | } |
Anna Bridge |
180:96ed750bd169 | 4086 | else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) |
<> | 144:ef7eb2e8f9f7 | 4087 | { |
<> | 144:ef7eb2e8f9f7 | 4088 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 4089 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4090 | |
<> | 144:ef7eb2e8f9f7 | 4091 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4092 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4093 | |
<> | 144:ef7eb2e8f9f7 | 4094 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
<> | 144:ef7eb2e8f9f7 | 4095 | HAL_I2C_ListenCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4096 | } |
<> | 144:ef7eb2e8f9f7 | 4097 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
Anna Bridge |
180:96ed750bd169 | 4098 | else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
<> | 144:ef7eb2e8f9f7 | 4099 | { |
<> | 144:ef7eb2e8f9f7 | 4100 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4101 | |
<> | 144:ef7eb2e8f9f7 | 4102 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4103 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4104 | |
<> | 144:ef7eb2e8f9f7 | 4105 | /* Call the Slave Rx Complete callback */ |
<> | 144:ef7eb2e8f9f7 | 4106 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4107 | } |
<> | 144:ef7eb2e8f9f7 | 4108 | else |
<> | 144:ef7eb2e8f9f7 | 4109 | { |
<> | 144:ef7eb2e8f9f7 | 4110 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4111 | |
<> | 144:ef7eb2e8f9f7 | 4112 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4113 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4114 | |
<> | 144:ef7eb2e8f9f7 | 4115 | /* Call the Slave Tx Complete callback */ |
<> | 144:ef7eb2e8f9f7 | 4116 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4117 | } |
<> | 144:ef7eb2e8f9f7 | 4118 | } |
<> | 144:ef7eb2e8f9f7 | 4119 | |
<> | 144:ef7eb2e8f9f7 | 4120 | /** |
<> | 144:ef7eb2e8f9f7 | 4121 | * @brief I2C Listen complete process. |
<> | 144:ef7eb2e8f9f7 | 4122 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 4123 | * @param ITFlags Interrupt flags to handle. |
<> | 144:ef7eb2e8f9f7 | 4124 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4125 | */ |
<> | 144:ef7eb2e8f9f7 | 4126 | static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) |
<> | 144:ef7eb2e8f9f7 | 4127 | { |
<> | 144:ef7eb2e8f9f7 | 4128 | /* Reset handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 4129 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 4130 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4131 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4132 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4133 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 4134 | |
<> | 144:ef7eb2e8f9f7 | 4135 | /* Store Last receive data if any */ |
Anna Bridge |
180:96ed750bd169 | 4136 | if (((ITFlags & I2C_FLAG_RXNE) != RESET)) |
<> | 144:ef7eb2e8f9f7 | 4137 | { |
<> | 144:ef7eb2e8f9f7 | 4138 | /* Read data from RXDR */ |
<> | 144:ef7eb2e8f9f7 | 4139 | (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR; |
<> | 144:ef7eb2e8f9f7 | 4140 | |
Anna Bridge |
180:96ed750bd169 | 4141 | if ((hi2c->XferSize > 0U)) |
<> | 144:ef7eb2e8f9f7 | 4142 | { |
<> | 144:ef7eb2e8f9f7 | 4143 | hi2c->XferSize--; |
<> | 144:ef7eb2e8f9f7 | 4144 | hi2c->XferCount--; |
<> | 144:ef7eb2e8f9f7 | 4145 | |
<> | 144:ef7eb2e8f9f7 | 4146 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4147 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
<> | 144:ef7eb2e8f9f7 | 4148 | } |
<> | 144:ef7eb2e8f9f7 | 4149 | } |
<> | 144:ef7eb2e8f9f7 | 4150 | |
<> | 144:ef7eb2e8f9f7 | 4151 | /* Disable all Interrupts*/ |
<> | 144:ef7eb2e8f9f7 | 4152 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 4153 | |
<> | 144:ef7eb2e8f9f7 | 4154 | /* Clear NACK Flag */ |
<> | 144:ef7eb2e8f9f7 | 4155 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 4156 | |
<> | 144:ef7eb2e8f9f7 | 4157 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4158 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4159 | |
<> | 144:ef7eb2e8f9f7 | 4160 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
<> | 144:ef7eb2e8f9f7 | 4161 | HAL_I2C_ListenCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4162 | } |
<> | 144:ef7eb2e8f9f7 | 4163 | |
<> | 144:ef7eb2e8f9f7 | 4164 | /** |
<> | 144:ef7eb2e8f9f7 | 4165 | * @brief I2C interrupts error process. |
<> | 144:ef7eb2e8f9f7 | 4166 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 4167 | * @param ErrorCode Error code to handle. |
<> | 144:ef7eb2e8f9f7 | 4168 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4169 | */ |
<> | 144:ef7eb2e8f9f7 | 4170 | static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) |
<> | 144:ef7eb2e8f9f7 | 4171 | { |
<> | 144:ef7eb2e8f9f7 | 4172 | /* Reset handle parameters */ |
<> | 144:ef7eb2e8f9f7 | 4173 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4174 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
<> | 144:ef7eb2e8f9f7 | 4175 | hi2c->XferCount = 0U; |
<> | 144:ef7eb2e8f9f7 | 4176 | |
<> | 144:ef7eb2e8f9f7 | 4177 | /* Set new error code */ |
<> | 144:ef7eb2e8f9f7 | 4178 | hi2c->ErrorCode |= ErrorCode; |
<> | 144:ef7eb2e8f9f7 | 4179 | |
<> | 144:ef7eb2e8f9f7 | 4180 | /* Disable Interrupts */ |
Anna Bridge |
180:96ed750bd169 | 4181 | if ((hi2c->State == HAL_I2C_STATE_LISTEN) || |
Anna Bridge |
180:96ed750bd169 | 4182 | (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) || |
Anna Bridge |
180:96ed750bd169 | 4183 | (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
<> | 144:ef7eb2e8f9f7 | 4184 | { |
<> | 144:ef7eb2e8f9f7 | 4185 | /* Disable all interrupts, except interrupts related to LISTEN state */ |
<> | 144:ef7eb2e8f9f7 | 4186 | I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); |
<> | 144:ef7eb2e8f9f7 | 4187 | |
<> | 144:ef7eb2e8f9f7 | 4188 | /* keep HAL_I2C_STATE_LISTEN if set */ |
<> | 144:ef7eb2e8f9f7 | 4189 | hi2c->State = HAL_I2C_STATE_LISTEN; |
<> | 144:ef7eb2e8f9f7 | 4190 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4191 | hi2c->XferISR = I2C_Slave_ISR_IT; |
<> | 144:ef7eb2e8f9f7 | 4192 | } |
<> | 144:ef7eb2e8f9f7 | 4193 | else |
<> | 144:ef7eb2e8f9f7 | 4194 | { |
<> | 144:ef7eb2e8f9f7 | 4195 | /* Disable all interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4196 | I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); |
Anna Bridge |
180:96ed750bd169 | 4197 | |
<> | 144:ef7eb2e8f9f7 | 4198 | /* If state is an abort treatment on goind, don't change state */ |
<> | 144:ef7eb2e8f9f7 | 4199 | /* This change will be do later */ |
Anna Bridge |
180:96ed750bd169 | 4200 | if (hi2c->State != HAL_I2C_STATE_ABORT) |
<> | 144:ef7eb2e8f9f7 | 4201 | { |
<> | 144:ef7eb2e8f9f7 | 4202 | /* Set HAL_I2C_STATE_READY */ |
<> | 144:ef7eb2e8f9f7 | 4203 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4204 | } |
<> | 144:ef7eb2e8f9f7 | 4205 | hi2c->PreviousState = I2C_STATE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4206 | hi2c->XferISR = NULL; |
<> | 144:ef7eb2e8f9f7 | 4207 | } |
<> | 144:ef7eb2e8f9f7 | 4208 | |
<> | 144:ef7eb2e8f9f7 | 4209 | /* Abort DMA TX transfer if any */ |
Anna Bridge |
180:96ed750bd169 | 4210 | if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) |
<> | 144:ef7eb2e8f9f7 | 4211 | { |
<> | 144:ef7eb2e8f9f7 | 4212 | hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 4213 | |
<> | 144:ef7eb2e8f9f7 | 4214 | /* Set the I2C DMA Abort callback : |
<> | 144:ef7eb2e8f9f7 | 4215 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
<> | 144:ef7eb2e8f9f7 | 4216 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
<> | 144:ef7eb2e8f9f7 | 4217 | |
<> | 144:ef7eb2e8f9f7 | 4218 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4219 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4220 | |
<> | 144:ef7eb2e8f9f7 | 4221 | /* Abort DMA TX */ |
Anna Bridge |
180:96ed750bd169 | 4222 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 4223 | { |
<> | 144:ef7eb2e8f9f7 | 4224 | /* Call Directly XferAbortCallback function in case of error */ |
<> | 144:ef7eb2e8f9f7 | 4225 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
<> | 144:ef7eb2e8f9f7 | 4226 | } |
<> | 144:ef7eb2e8f9f7 | 4227 | } |
<> | 144:ef7eb2e8f9f7 | 4228 | /* Abort DMA RX transfer if any */ |
Anna Bridge |
180:96ed750bd169 | 4229 | else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) |
<> | 144:ef7eb2e8f9f7 | 4230 | { |
<> | 144:ef7eb2e8f9f7 | 4231 | hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 4232 | |
<> | 144:ef7eb2e8f9f7 | 4233 | /* Set the I2C DMA Abort callback : |
<> | 144:ef7eb2e8f9f7 | 4234 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
<> | 144:ef7eb2e8f9f7 | 4235 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
<> | 144:ef7eb2e8f9f7 | 4236 | |
<> | 144:ef7eb2e8f9f7 | 4237 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4238 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4239 | |
<> | 144:ef7eb2e8f9f7 | 4240 | /* Abort DMA RX */ |
Anna Bridge |
180:96ed750bd169 | 4241 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 4242 | { |
<> | 144:ef7eb2e8f9f7 | 4243 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
<> | 144:ef7eb2e8f9f7 | 4244 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
<> | 144:ef7eb2e8f9f7 | 4245 | } |
<> | 144:ef7eb2e8f9f7 | 4246 | } |
Anna Bridge |
180:96ed750bd169 | 4247 | else if (hi2c->State == HAL_I2C_STATE_ABORT) |
<> | 144:ef7eb2e8f9f7 | 4248 | { |
<> | 144:ef7eb2e8f9f7 | 4249 | hi2c->State = HAL_I2C_STATE_READY; |
Anna Bridge |
180:96ed750bd169 | 4250 | |
<> | 144:ef7eb2e8f9f7 | 4251 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4252 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4253 | |
<> | 144:ef7eb2e8f9f7 | 4254 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4255 | HAL_I2C_AbortCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4256 | } |
<> | 144:ef7eb2e8f9f7 | 4257 | else |
<> | 144:ef7eb2e8f9f7 | 4258 | { |
<> | 144:ef7eb2e8f9f7 | 4259 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4260 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4261 | |
<> | 144:ef7eb2e8f9f7 | 4262 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4263 | HAL_I2C_ErrorCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4264 | } |
<> | 144:ef7eb2e8f9f7 | 4265 | } |
<> | 144:ef7eb2e8f9f7 | 4266 | |
<> | 144:ef7eb2e8f9f7 | 4267 | /** |
<> | 144:ef7eb2e8f9f7 | 4268 | * @brief I2C Tx data register flush process. |
<> | 144:ef7eb2e8f9f7 | 4269 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 4270 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4271 | */ |
<> | 144:ef7eb2e8f9f7 | 4272 | static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) |
<> | 144:ef7eb2e8f9f7 | 4273 | { |
<> | 144:ef7eb2e8f9f7 | 4274 | /* If a pending TXIS flag is set */ |
<> | 144:ef7eb2e8f9f7 | 4275 | /* Write a dummy data in TXDR to clear it */ |
Anna Bridge |
180:96ed750bd169 | 4276 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) |
<> | 144:ef7eb2e8f9f7 | 4277 | { |
Anna Bridge |
180:96ed750bd169 | 4278 | hi2c->Instance->TXDR = 0x00U; |
<> | 144:ef7eb2e8f9f7 | 4279 | } |
<> | 144:ef7eb2e8f9f7 | 4280 | |
<> | 144:ef7eb2e8f9f7 | 4281 | /* Flush TX register if not empty */ |
Anna Bridge |
180:96ed750bd169 | 4282 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
<> | 144:ef7eb2e8f9f7 | 4283 | { |
<> | 144:ef7eb2e8f9f7 | 4284 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); |
<> | 144:ef7eb2e8f9f7 | 4285 | } |
<> | 144:ef7eb2e8f9f7 | 4286 | } |
<> | 144:ef7eb2e8f9f7 | 4287 | |
<> | 144:ef7eb2e8f9f7 | 4288 | /** |
<> | 144:ef7eb2e8f9f7 | 4289 | * @brief DMA I2C master transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 4290 | * @param hdma DMA handle |
<> | 144:ef7eb2e8f9f7 | 4291 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4292 | */ |
<> | 156:95d6b41a828b | 4293 | static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 4294 | { |
Anna Bridge |
180:96ed750bd169 | 4295 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 4296 | |
<> | 144:ef7eb2e8f9f7 | 4297 | /* Disable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 4298 | hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 4299 | |
<> | 144:ef7eb2e8f9f7 | 4300 | /* If last transfer, enable STOP interrupt */ |
Anna Bridge |
180:96ed750bd169 | 4301 | if (hi2c->XferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 4302 | { |
<> | 144:ef7eb2e8f9f7 | 4303 | /* Enable STOP interrupt */ |
<> | 144:ef7eb2e8f9f7 | 4304 | I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); |
<> | 144:ef7eb2e8f9f7 | 4305 | } |
<> | 144:ef7eb2e8f9f7 | 4306 | /* else prepare a new DMA transfer and enable TCReload interrupt */ |
<> | 144:ef7eb2e8f9f7 | 4307 | else |
<> | 144:ef7eb2e8f9f7 | 4308 | { |
<> | 144:ef7eb2e8f9f7 | 4309 | /* Update Buffer pointer */ |
<> | 144:ef7eb2e8f9f7 | 4310 | hi2c->pBuffPtr += hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 4311 | |
<> | 144:ef7eb2e8f9f7 | 4312 | /* Set the XferSize to transfer */ |
Anna Bridge |
180:96ed750bd169 | 4313 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 4314 | { |
<> | 144:ef7eb2e8f9f7 | 4315 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 4316 | } |
<> | 144:ef7eb2e8f9f7 | 4317 | else |
<> | 144:ef7eb2e8f9f7 | 4318 | { |
<> | 144:ef7eb2e8f9f7 | 4319 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 4320 | } |
<> | 144:ef7eb2e8f9f7 | 4321 | |
<> | 144:ef7eb2e8f9f7 | 4322 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 4323 | HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 4324 | |
<> | 144:ef7eb2e8f9f7 | 4325 | /* Enable TC interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4326 | I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); |
<> | 144:ef7eb2e8f9f7 | 4327 | } |
<> | 144:ef7eb2e8f9f7 | 4328 | } |
<> | 144:ef7eb2e8f9f7 | 4329 | |
<> | 144:ef7eb2e8f9f7 | 4330 | /** |
<> | 156:95d6b41a828b | 4331 | * @brief DMA I2C slave transmit process complete callback. |
<> | 144:ef7eb2e8f9f7 | 4332 | * @param hdma DMA handle |
<> | 144:ef7eb2e8f9f7 | 4333 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4334 | */ |
<> | 156:95d6b41a828b | 4335 | static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 4336 | { |
<> | 156:95d6b41a828b | 4337 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 4338 | UNUSED(hdma); |
<> | 156:95d6b41a828b | 4339 | |
<> | 144:ef7eb2e8f9f7 | 4340 | /* No specific action, Master fully manage the generation of STOP condition */ |
<> | 144:ef7eb2e8f9f7 | 4341 | /* Mean that this generation can arrive at any time, at the end or during DMA process */ |
<> | 144:ef7eb2e8f9f7 | 4342 | /* So STOP condition should be manage through Interrupt treatment */ |
<> | 144:ef7eb2e8f9f7 | 4343 | } |
<> | 144:ef7eb2e8f9f7 | 4344 | |
<> | 144:ef7eb2e8f9f7 | 4345 | /** |
<> | 144:ef7eb2e8f9f7 | 4346 | * @brief DMA I2C master receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 4347 | * @param hdma DMA handle |
<> | 144:ef7eb2e8f9f7 | 4348 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4349 | */ |
<> | 156:95d6b41a828b | 4350 | static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 4351 | { |
Anna Bridge |
180:96ed750bd169 | 4352 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 4353 | |
<> | 144:ef7eb2e8f9f7 | 4354 | /* Disable DMA Request */ |
<> | 144:ef7eb2e8f9f7 | 4355 | hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; |
<> | 144:ef7eb2e8f9f7 | 4356 | |
<> | 144:ef7eb2e8f9f7 | 4357 | /* If last transfer, enable STOP interrupt */ |
Anna Bridge |
180:96ed750bd169 | 4358 | if (hi2c->XferCount == 0U) |
<> | 144:ef7eb2e8f9f7 | 4359 | { |
<> | 144:ef7eb2e8f9f7 | 4360 | /* Enable STOP interrupt */ |
<> | 144:ef7eb2e8f9f7 | 4361 | I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); |
<> | 144:ef7eb2e8f9f7 | 4362 | } |
<> | 144:ef7eb2e8f9f7 | 4363 | /* else prepare a new DMA transfer and enable TCReload interrupt */ |
<> | 144:ef7eb2e8f9f7 | 4364 | else |
<> | 144:ef7eb2e8f9f7 | 4365 | { |
<> | 144:ef7eb2e8f9f7 | 4366 | /* Update Buffer pointer */ |
<> | 144:ef7eb2e8f9f7 | 4367 | hi2c->pBuffPtr += hi2c->XferSize; |
<> | 144:ef7eb2e8f9f7 | 4368 | |
<> | 144:ef7eb2e8f9f7 | 4369 | /* Set the XferSize to transfer */ |
Anna Bridge |
180:96ed750bd169 | 4370 | if (hi2c->XferCount > MAX_NBYTE_SIZE) |
<> | 144:ef7eb2e8f9f7 | 4371 | { |
<> | 144:ef7eb2e8f9f7 | 4372 | hi2c->XferSize = MAX_NBYTE_SIZE; |
<> | 144:ef7eb2e8f9f7 | 4373 | } |
<> | 144:ef7eb2e8f9f7 | 4374 | else |
<> | 144:ef7eb2e8f9f7 | 4375 | { |
<> | 144:ef7eb2e8f9f7 | 4376 | hi2c->XferSize = hi2c->XferCount; |
<> | 144:ef7eb2e8f9f7 | 4377 | } |
<> | 144:ef7eb2e8f9f7 | 4378 | |
<> | 144:ef7eb2e8f9f7 | 4379 | /* Enable the DMA channel */ |
<> | 144:ef7eb2e8f9f7 | 4380 | HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
<> | 144:ef7eb2e8f9f7 | 4381 | |
<> | 144:ef7eb2e8f9f7 | 4382 | /* Enable TC interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4383 | I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); |
<> | 144:ef7eb2e8f9f7 | 4384 | } |
<> | 144:ef7eb2e8f9f7 | 4385 | } |
<> | 144:ef7eb2e8f9f7 | 4386 | |
<> | 144:ef7eb2e8f9f7 | 4387 | /** |
<> | 144:ef7eb2e8f9f7 | 4388 | * @brief DMA I2C slave receive process complete callback. |
<> | 144:ef7eb2e8f9f7 | 4389 | * @param hdma DMA handle |
<> | 144:ef7eb2e8f9f7 | 4390 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4391 | */ |
<> | 156:95d6b41a828b | 4392 | static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) |
<> | 156:95d6b41a828b | 4393 | { |
<> | 156:95d6b41a828b | 4394 | /* Prevent unused argument(s) compilation warning */ |
<> | 156:95d6b41a828b | 4395 | UNUSED(hdma); |
<> | 156:95d6b41a828b | 4396 | |
<> | 144:ef7eb2e8f9f7 | 4397 | /* No specific action, Master fully manage the generation of STOP condition */ |
<> | 144:ef7eb2e8f9f7 | 4398 | /* Mean that this generation can arrive at any time, at the end or during DMA process */ |
<> | 144:ef7eb2e8f9f7 | 4399 | /* So STOP condition should be manage through Interrupt treatment */ |
<> | 144:ef7eb2e8f9f7 | 4400 | } |
<> | 144:ef7eb2e8f9f7 | 4401 | |
<> | 144:ef7eb2e8f9f7 | 4402 | /** |
<> | 144:ef7eb2e8f9f7 | 4403 | * @brief DMA I2C communication error callback. |
<> | 144:ef7eb2e8f9f7 | 4404 | * @param hdma DMA handle |
<> | 144:ef7eb2e8f9f7 | 4405 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4406 | */ |
<> | 144:ef7eb2e8f9f7 | 4407 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 4408 | { |
Anna Bridge |
180:96ed750bd169 | 4409 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 4410 | |
<> | 144:ef7eb2e8f9f7 | 4411 | /* Disable Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4412 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 4413 | |
<> | 144:ef7eb2e8f9f7 | 4414 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4415 | I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); |
<> | 144:ef7eb2e8f9f7 | 4416 | } |
<> | 144:ef7eb2e8f9f7 | 4417 | |
<> | 144:ef7eb2e8f9f7 | 4418 | /** |
<> | 144:ef7eb2e8f9f7 | 4419 | * @brief DMA I2C communication abort callback |
<> | 144:ef7eb2e8f9f7 | 4420 | * (To be called at end of DMA Abort procedure). |
Anna Bridge |
180:96ed750bd169 | 4421 | * @param hdma DMA handle. |
<> | 144:ef7eb2e8f9f7 | 4422 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4423 | */ |
<> | 144:ef7eb2e8f9f7 | 4424 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
<> | 144:ef7eb2e8f9f7 | 4425 | { |
Anna Bridge |
180:96ed750bd169 | 4426 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; |
<> | 144:ef7eb2e8f9f7 | 4427 | |
<> | 144:ef7eb2e8f9f7 | 4428 | /* Disable Acknowledge */ |
<> | 144:ef7eb2e8f9f7 | 4429 | hi2c->Instance->CR2 |= I2C_CR2_NACK; |
<> | 144:ef7eb2e8f9f7 | 4430 | |
<> | 144:ef7eb2e8f9f7 | 4431 | /* Reset AbortCpltCallback */ |
<> | 144:ef7eb2e8f9f7 | 4432 | hi2c->hdmatx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 4433 | hi2c->hdmarx->XferAbortCallback = NULL; |
<> | 144:ef7eb2e8f9f7 | 4434 | |
<> | 144:ef7eb2e8f9f7 | 4435 | /* Check if come from abort from user */ |
Anna Bridge |
180:96ed750bd169 | 4436 | if (hi2c->State == HAL_I2C_STATE_ABORT) |
<> | 144:ef7eb2e8f9f7 | 4437 | { |
<> | 144:ef7eb2e8f9f7 | 4438 | hi2c->State = HAL_I2C_STATE_READY; |
Anna Bridge |
180:96ed750bd169 | 4439 | |
<> | 144:ef7eb2e8f9f7 | 4440 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4441 | HAL_I2C_AbortCpltCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4442 | } |
<> | 144:ef7eb2e8f9f7 | 4443 | else |
<> | 144:ef7eb2e8f9f7 | 4444 | { |
<> | 144:ef7eb2e8f9f7 | 4445 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
<> | 144:ef7eb2e8f9f7 | 4446 | HAL_I2C_ErrorCallback(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4447 | } |
<> | 144:ef7eb2e8f9f7 | 4448 | } |
<> | 144:ef7eb2e8f9f7 | 4449 | |
<> | 144:ef7eb2e8f9f7 | 4450 | /** |
<> | 144:ef7eb2e8f9f7 | 4451 | * @brief This function handles I2C Communication Timeout. |
<> | 144:ef7eb2e8f9f7 | 4452 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4453 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4454 | * @param Flag Specifies the I2C flag to check. |
<> | 144:ef7eb2e8f9f7 | 4455 | * @param Status The new Flag status (SET or RESET). |
<> | 144:ef7eb2e8f9f7 | 4456 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 4457 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 4458 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4459 | */ |
<> | 144:ef7eb2e8f9f7 | 4460 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 4461 | { |
Anna Bridge |
180:96ed750bd169 | 4462 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) |
<> | 144:ef7eb2e8f9f7 | 4463 | { |
<> | 144:ef7eb2e8f9f7 | 4464 | /* Check for the Timeout */ |
Anna Bridge |
180:96ed750bd169 | 4465 | if (Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 4466 | { |
Anna Bridge |
180:96ed750bd169 | 4467 | if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 4468 | { |
Anna Bridge |
180:96ed750bd169 | 4469 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4470 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4471 | |
<> | 144:ef7eb2e8f9f7 | 4472 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4473 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4474 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 4475 | } |
<> | 144:ef7eb2e8f9f7 | 4476 | } |
<> | 144:ef7eb2e8f9f7 | 4477 | } |
<> | 144:ef7eb2e8f9f7 | 4478 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4479 | } |
<> | 144:ef7eb2e8f9f7 | 4480 | |
<> | 144:ef7eb2e8f9f7 | 4481 | /** |
<> | 144:ef7eb2e8f9f7 | 4482 | * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. |
<> | 144:ef7eb2e8f9f7 | 4483 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4484 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4485 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 4486 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 4487 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4488 | */ |
<> | 144:ef7eb2e8f9f7 | 4489 | static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 4490 | { |
Anna Bridge |
180:96ed750bd169 | 4491 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) |
<> | 144:ef7eb2e8f9f7 | 4492 | { |
<> | 144:ef7eb2e8f9f7 | 4493 | /* Check if a NACK is detected */ |
Anna Bridge |
180:96ed750bd169 | 4494 | if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 4495 | { |
<> | 144:ef7eb2e8f9f7 | 4496 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 4497 | } |
<> | 144:ef7eb2e8f9f7 | 4498 | |
<> | 144:ef7eb2e8f9f7 | 4499 | /* Check for the Timeout */ |
Anna Bridge |
180:96ed750bd169 | 4500 | if (Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 4501 | { |
Anna Bridge |
180:96ed750bd169 | 4502 | if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 4503 | { |
<> | 144:ef7eb2e8f9f7 | 4504 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
Anna Bridge |
180:96ed750bd169 | 4505 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4506 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4507 | |
<> | 144:ef7eb2e8f9f7 | 4508 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4509 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4510 | |
<> | 144:ef7eb2e8f9f7 | 4511 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 4512 | } |
<> | 144:ef7eb2e8f9f7 | 4513 | } |
<> | 144:ef7eb2e8f9f7 | 4514 | } |
<> | 144:ef7eb2e8f9f7 | 4515 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4516 | } |
<> | 144:ef7eb2e8f9f7 | 4517 | |
<> | 144:ef7eb2e8f9f7 | 4518 | /** |
<> | 144:ef7eb2e8f9f7 | 4519 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
<> | 144:ef7eb2e8f9f7 | 4520 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4521 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4522 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 4523 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 4524 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4525 | */ |
<> | 144:ef7eb2e8f9f7 | 4526 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 4527 | { |
Anna Bridge |
180:96ed750bd169 | 4528 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
<> | 144:ef7eb2e8f9f7 | 4529 | { |
<> | 144:ef7eb2e8f9f7 | 4530 | /* Check if a NACK is detected */ |
Anna Bridge |
180:96ed750bd169 | 4531 | if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 4532 | { |
<> | 144:ef7eb2e8f9f7 | 4533 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 4534 | } |
<> | 144:ef7eb2e8f9f7 | 4535 | |
<> | 144:ef7eb2e8f9f7 | 4536 | /* Check for the Timeout */ |
Anna Bridge |
180:96ed750bd169 | 4537 | if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 4538 | { |
<> | 144:ef7eb2e8f9f7 | 4539 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
Anna Bridge |
180:96ed750bd169 | 4540 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4541 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4542 | |
<> | 144:ef7eb2e8f9f7 | 4543 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4544 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4545 | |
<> | 144:ef7eb2e8f9f7 | 4546 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 4547 | } |
<> | 144:ef7eb2e8f9f7 | 4548 | } |
<> | 144:ef7eb2e8f9f7 | 4549 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4550 | } |
<> | 144:ef7eb2e8f9f7 | 4551 | |
<> | 144:ef7eb2e8f9f7 | 4552 | /** |
<> | 144:ef7eb2e8f9f7 | 4553 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
<> | 144:ef7eb2e8f9f7 | 4554 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4555 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4556 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 4557 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 4558 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4559 | */ |
<> | 144:ef7eb2e8f9f7 | 4560 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 4561 | { |
Anna Bridge |
180:96ed750bd169 | 4562 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
<> | 144:ef7eb2e8f9f7 | 4563 | { |
<> | 144:ef7eb2e8f9f7 | 4564 | /* Check if a NACK is detected */ |
Anna Bridge |
180:96ed750bd169 | 4565 | if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK) |
<> | 144:ef7eb2e8f9f7 | 4566 | { |
<> | 144:ef7eb2e8f9f7 | 4567 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 4568 | } |
<> | 144:ef7eb2e8f9f7 | 4569 | |
<> | 144:ef7eb2e8f9f7 | 4570 | /* Check if a STOPF is detected */ |
Anna Bridge |
180:96ed750bd169 | 4571 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
<> | 144:ef7eb2e8f9f7 | 4572 | { |
<> | 144:ef7eb2e8f9f7 | 4573 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 4574 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 4575 | |
<> | 144:ef7eb2e8f9f7 | 4576 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 4577 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4578 | |
<> | 144:ef7eb2e8f9f7 | 4579 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
Anna Bridge |
180:96ed750bd169 | 4580 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4581 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4582 | |
<> | 144:ef7eb2e8f9f7 | 4583 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4584 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4585 | |
<> | 144:ef7eb2e8f9f7 | 4586 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 4587 | } |
<> | 144:ef7eb2e8f9f7 | 4588 | |
<> | 144:ef7eb2e8f9f7 | 4589 | /* Check for the Timeout */ |
Anna Bridge |
180:96ed750bd169 | 4590 | if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 4591 | { |
<> | 144:ef7eb2e8f9f7 | 4592 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
Anna Bridge |
180:96ed750bd169 | 4593 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4594 | |
<> | 144:ef7eb2e8f9f7 | 4595 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4596 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4597 | |
<> | 144:ef7eb2e8f9f7 | 4598 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 4599 | } |
<> | 144:ef7eb2e8f9f7 | 4600 | } |
<> | 144:ef7eb2e8f9f7 | 4601 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4602 | } |
<> | 144:ef7eb2e8f9f7 | 4603 | |
<> | 144:ef7eb2e8f9f7 | 4604 | /** |
<> | 144:ef7eb2e8f9f7 | 4605 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
<> | 144:ef7eb2e8f9f7 | 4606 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4607 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4608 | * @param Timeout Timeout duration |
<> | 144:ef7eb2e8f9f7 | 4609 | * @param Tickstart Tick start value |
<> | 144:ef7eb2e8f9f7 | 4610 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4611 | */ |
<> | 144:ef7eb2e8f9f7 | 4612 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
<> | 144:ef7eb2e8f9f7 | 4613 | { |
Anna Bridge |
180:96ed750bd169 | 4614 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
<> | 144:ef7eb2e8f9f7 | 4615 | { |
<> | 144:ef7eb2e8f9f7 | 4616 | /* Wait until STOP Flag is reset */ |
<> | 144:ef7eb2e8f9f7 | 4617 | /* AutoEnd should be initiate after AF */ |
Anna Bridge |
180:96ed750bd169 | 4618 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
<> | 144:ef7eb2e8f9f7 | 4619 | { |
<> | 144:ef7eb2e8f9f7 | 4620 | /* Check for the Timeout */ |
Anna Bridge |
180:96ed750bd169 | 4621 | if (Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 4622 | { |
Anna Bridge |
180:96ed750bd169 | 4623 | if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 4624 | { |
Anna Bridge |
180:96ed750bd169 | 4625 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4626 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4627 | |
<> | 144:ef7eb2e8f9f7 | 4628 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4629 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4630 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 4631 | } |
<> | 144:ef7eb2e8f9f7 | 4632 | } |
<> | 144:ef7eb2e8f9f7 | 4633 | } |
<> | 144:ef7eb2e8f9f7 | 4634 | |
<> | 144:ef7eb2e8f9f7 | 4635 | /* Clear NACKF Flag */ |
<> | 144:ef7eb2e8f9f7 | 4636 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
<> | 144:ef7eb2e8f9f7 | 4637 | |
<> | 144:ef7eb2e8f9f7 | 4638 | /* Clear STOP Flag */ |
<> | 144:ef7eb2e8f9f7 | 4639 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
<> | 144:ef7eb2e8f9f7 | 4640 | |
<> | 144:ef7eb2e8f9f7 | 4641 | /* Flush TX register */ |
<> | 144:ef7eb2e8f9f7 | 4642 | I2C_Flush_TXDR(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4643 | |
<> | 144:ef7eb2e8f9f7 | 4644 | /* Clear Configuration Register 2 */ |
<> | 144:ef7eb2e8f9f7 | 4645 | I2C_RESET_CR2(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4646 | |
<> | 144:ef7eb2e8f9f7 | 4647 | hi2c->ErrorCode = HAL_I2C_ERROR_AF; |
Anna Bridge |
180:96ed750bd169 | 4648 | hi2c->State = HAL_I2C_STATE_READY; |
<> | 144:ef7eb2e8f9f7 | 4649 | hi2c->Mode = HAL_I2C_MODE_NONE; |
<> | 144:ef7eb2e8f9f7 | 4650 | |
<> | 144:ef7eb2e8f9f7 | 4651 | /* Process Unlocked */ |
<> | 144:ef7eb2e8f9f7 | 4652 | __HAL_UNLOCK(hi2c); |
<> | 144:ef7eb2e8f9f7 | 4653 | |
<> | 144:ef7eb2e8f9f7 | 4654 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 4655 | } |
<> | 144:ef7eb2e8f9f7 | 4656 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4657 | } |
<> | 144:ef7eb2e8f9f7 | 4658 | |
<> | 144:ef7eb2e8f9f7 | 4659 | /** |
<> | 144:ef7eb2e8f9f7 | 4660 | * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). |
<> | 144:ef7eb2e8f9f7 | 4661 | * @param hi2c I2C handle. |
<> | 144:ef7eb2e8f9f7 | 4662 | * @param DevAddress Specifies the slave address to be programmed. |
<> | 144:ef7eb2e8f9f7 | 4663 | * @param Size Specifies the number of bytes to be programmed. |
<> | 144:ef7eb2e8f9f7 | 4664 | * This parameter must be a value between 0 and 255. |
<> | 144:ef7eb2e8f9f7 | 4665 | * @param Mode New state of the I2C START condition generation. |
<> | 144:ef7eb2e8f9f7 | 4666 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 4667 | * @arg @ref I2C_RELOAD_MODE Enable Reload mode . |
<> | 144:ef7eb2e8f9f7 | 4668 | * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. |
<> | 144:ef7eb2e8f9f7 | 4669 | * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. |
<> | 144:ef7eb2e8f9f7 | 4670 | * @param Request New state of the I2C START condition generation. |
<> | 144:ef7eb2e8f9f7 | 4671 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 4672 | * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. |
<> | 144:ef7eb2e8f9f7 | 4673 | * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). |
<> | 144:ef7eb2e8f9f7 | 4674 | * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. |
<> | 144:ef7eb2e8f9f7 | 4675 | * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. |
<> | 144:ef7eb2e8f9f7 | 4676 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 4677 | */ |
<> | 144:ef7eb2e8f9f7 | 4678 | static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) |
<> | 144:ef7eb2e8f9f7 | 4679 | { |
<> | 144:ef7eb2e8f9f7 | 4680 | uint32_t tmpreg = 0U; |
<> | 144:ef7eb2e8f9f7 | 4681 | |
<> | 144:ef7eb2e8f9f7 | 4682 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 4683 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
<> | 144:ef7eb2e8f9f7 | 4684 | assert_param(IS_TRANSFER_MODE(Mode)); |
<> | 144:ef7eb2e8f9f7 | 4685 | assert_param(IS_TRANSFER_REQUEST(Request)); |
<> | 144:ef7eb2e8f9f7 | 4686 | |
<> | 144:ef7eb2e8f9f7 | 4687 | /* Get the CR2 register value */ |
<> | 144:ef7eb2e8f9f7 | 4688 | tmpreg = hi2c->Instance->CR2; |
<> | 144:ef7eb2e8f9f7 | 4689 | |
<> | 144:ef7eb2e8f9f7 | 4690 | /* clear tmpreg specific bits */ |
<> | 144:ef7eb2e8f9f7 | 4691 | tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); |
<> | 144:ef7eb2e8f9f7 | 4692 | |
<> | 144:ef7eb2e8f9f7 | 4693 | /* update tmpreg */ |
Anna Bridge |
180:96ed750bd169 | 4694 | tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16) & I2C_CR2_NBYTES) | \ |
Anna Bridge |
180:96ed750bd169 | 4695 | (uint32_t)Mode | (uint32_t)Request); |
<> | 144:ef7eb2e8f9f7 | 4696 | |
<> | 144:ef7eb2e8f9f7 | 4697 | /* update CR2 register */ |
<> | 144:ef7eb2e8f9f7 | 4698 | hi2c->Instance->CR2 = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 4699 | } |
<> | 144:ef7eb2e8f9f7 | 4700 | |
<> | 144:ef7eb2e8f9f7 | 4701 | /** |
<> | 144:ef7eb2e8f9f7 | 4702 | * @brief Manage the enabling of Interrupts. |
<> | 144:ef7eb2e8f9f7 | 4703 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4704 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4705 | * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. |
<> | 144:ef7eb2e8f9f7 | 4706 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4707 | */ |
<> | 144:ef7eb2e8f9f7 | 4708 | static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) |
<> | 144:ef7eb2e8f9f7 | 4709 | { |
<> | 144:ef7eb2e8f9f7 | 4710 | uint32_t tmpisr = 0U; |
<> | 144:ef7eb2e8f9f7 | 4711 | |
Anna Bridge |
180:96ed750bd169 | 4712 | if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \ |
Anna Bridge |
180:96ed750bd169 | 4713 | (hi2c->XferISR == I2C_Slave_ISR_DMA)) |
<> | 144:ef7eb2e8f9f7 | 4714 | { |
Anna Bridge |
180:96ed750bd169 | 4715 | if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) |
<> | 144:ef7eb2e8f9f7 | 4716 | { |
<> | 144:ef7eb2e8f9f7 | 4717 | /* Enable ERR, STOP, NACK and ADDR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4718 | tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; |
<> | 144:ef7eb2e8f9f7 | 4719 | } |
<> | 144:ef7eb2e8f9f7 | 4720 | |
Anna Bridge |
180:96ed750bd169 | 4721 | if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) |
<> | 144:ef7eb2e8f9f7 | 4722 | { |
<> | 144:ef7eb2e8f9f7 | 4723 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4724 | tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; |
<> | 144:ef7eb2e8f9f7 | 4725 | } |
<> | 144:ef7eb2e8f9f7 | 4726 | |
Anna Bridge |
180:96ed750bd169 | 4727 | if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) |
<> | 144:ef7eb2e8f9f7 | 4728 | { |
<> | 144:ef7eb2e8f9f7 | 4729 | /* Enable STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4730 | tmpisr |= I2C_IT_STOPI; |
<> | 144:ef7eb2e8f9f7 | 4731 | } |
Anna Bridge |
180:96ed750bd169 | 4732 | |
Anna Bridge |
180:96ed750bd169 | 4733 | if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) |
<> | 144:ef7eb2e8f9f7 | 4734 | { |
<> | 144:ef7eb2e8f9f7 | 4735 | /* Enable TC interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4736 | tmpisr |= I2C_IT_TCI; |
<> | 144:ef7eb2e8f9f7 | 4737 | } |
<> | 144:ef7eb2e8f9f7 | 4738 | } |
<> | 144:ef7eb2e8f9f7 | 4739 | else |
<> | 144:ef7eb2e8f9f7 | 4740 | { |
Anna Bridge |
180:96ed750bd169 | 4741 | if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) |
<> | 144:ef7eb2e8f9f7 | 4742 | { |
<> | 144:ef7eb2e8f9f7 | 4743 | /* Enable ERR, STOP, NACK, and ADDR interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4744 | tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; |
<> | 144:ef7eb2e8f9f7 | 4745 | } |
<> | 144:ef7eb2e8f9f7 | 4746 | |
Anna Bridge |
180:96ed750bd169 | 4747 | if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) |
<> | 144:ef7eb2e8f9f7 | 4748 | { |
<> | 144:ef7eb2e8f9f7 | 4749 | /* Enable ERR, TC, STOP, NACK and RXI interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4750 | tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; |
<> | 144:ef7eb2e8f9f7 | 4751 | } |
<> | 144:ef7eb2e8f9f7 | 4752 | |
Anna Bridge |
180:96ed750bd169 | 4753 | if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) |
<> | 144:ef7eb2e8f9f7 | 4754 | { |
<> | 144:ef7eb2e8f9f7 | 4755 | /* Enable ERR, TC, STOP, NACK and TXI interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4756 | tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; |
<> | 144:ef7eb2e8f9f7 | 4757 | } |
<> | 144:ef7eb2e8f9f7 | 4758 | |
Anna Bridge |
180:96ed750bd169 | 4759 | if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) |
<> | 144:ef7eb2e8f9f7 | 4760 | { |
<> | 144:ef7eb2e8f9f7 | 4761 | /* Enable STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4762 | tmpisr |= I2C_IT_STOPI; |
<> | 144:ef7eb2e8f9f7 | 4763 | } |
<> | 144:ef7eb2e8f9f7 | 4764 | } |
Anna Bridge |
180:96ed750bd169 | 4765 | |
<> | 144:ef7eb2e8f9f7 | 4766 | /* Enable interrupts only at the end */ |
<> | 144:ef7eb2e8f9f7 | 4767 | /* to avoid the risk of I2C interrupt handle execution before */ |
<> | 144:ef7eb2e8f9f7 | 4768 | /* all interrupts requested done */ |
<> | 144:ef7eb2e8f9f7 | 4769 | __HAL_I2C_ENABLE_IT(hi2c, tmpisr); |
<> | 144:ef7eb2e8f9f7 | 4770 | |
<> | 144:ef7eb2e8f9f7 | 4771 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4772 | } |
<> | 144:ef7eb2e8f9f7 | 4773 | |
<> | 144:ef7eb2e8f9f7 | 4774 | /** |
<> | 144:ef7eb2e8f9f7 | 4775 | * @brief Manage the disabling of Interrupts. |
<> | 144:ef7eb2e8f9f7 | 4776 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
<> | 144:ef7eb2e8f9f7 | 4777 | * the configuration information for the specified I2C. |
<> | 144:ef7eb2e8f9f7 | 4778 | * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. |
<> | 144:ef7eb2e8f9f7 | 4779 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 4780 | */ |
<> | 144:ef7eb2e8f9f7 | 4781 | static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) |
<> | 144:ef7eb2e8f9f7 | 4782 | { |
<> | 144:ef7eb2e8f9f7 | 4783 | uint32_t tmpisr = 0U; |
<> | 144:ef7eb2e8f9f7 | 4784 | |
Anna Bridge |
180:96ed750bd169 | 4785 | if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) |
<> | 144:ef7eb2e8f9f7 | 4786 | { |
<> | 144:ef7eb2e8f9f7 | 4787 | /* Disable TC and TXI interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4788 | tmpisr |= I2C_IT_TCI | I2C_IT_TXI; |
<> | 144:ef7eb2e8f9f7 | 4789 | |
Anna Bridge |
180:96ed750bd169 | 4790 | if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 4791 | { |
<> | 144:ef7eb2e8f9f7 | 4792 | /* Disable NACK and STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4793 | tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; |
<> | 144:ef7eb2e8f9f7 | 4794 | } |
<> | 144:ef7eb2e8f9f7 | 4795 | } |
<> | 144:ef7eb2e8f9f7 | 4796 | |
Anna Bridge |
180:96ed750bd169 | 4797 | if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) |
<> | 144:ef7eb2e8f9f7 | 4798 | { |
<> | 144:ef7eb2e8f9f7 | 4799 | /* Disable TC and RXI interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4800 | tmpisr |= I2C_IT_TCI | I2C_IT_RXI; |
<> | 144:ef7eb2e8f9f7 | 4801 | |
Anna Bridge |
180:96ed750bd169 | 4802 | if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN) |
<> | 144:ef7eb2e8f9f7 | 4803 | { |
<> | 144:ef7eb2e8f9f7 | 4804 | /* Disable NACK and STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4805 | tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; |
<> | 144:ef7eb2e8f9f7 | 4806 | } |
<> | 144:ef7eb2e8f9f7 | 4807 | } |
<> | 144:ef7eb2e8f9f7 | 4808 | |
Anna Bridge |
180:96ed750bd169 | 4809 | if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) |
<> | 144:ef7eb2e8f9f7 | 4810 | { |
<> | 144:ef7eb2e8f9f7 | 4811 | /* Disable ADDR, NACK and STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4812 | tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; |
<> | 144:ef7eb2e8f9f7 | 4813 | } |
<> | 144:ef7eb2e8f9f7 | 4814 | |
Anna Bridge |
180:96ed750bd169 | 4815 | if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT) |
<> | 144:ef7eb2e8f9f7 | 4816 | { |
<> | 144:ef7eb2e8f9f7 | 4817 | /* Enable ERR and NACK interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4818 | tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; |
<> | 144:ef7eb2e8f9f7 | 4819 | } |
<> | 144:ef7eb2e8f9f7 | 4820 | |
Anna Bridge |
180:96ed750bd169 | 4821 | if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT) |
<> | 144:ef7eb2e8f9f7 | 4822 | { |
<> | 144:ef7eb2e8f9f7 | 4823 | /* Enable STOP interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4824 | tmpisr |= I2C_IT_STOPI; |
<> | 144:ef7eb2e8f9f7 | 4825 | } |
Anna Bridge |
180:96ed750bd169 | 4826 | |
Anna Bridge |
180:96ed750bd169 | 4827 | if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT) |
<> | 144:ef7eb2e8f9f7 | 4828 | { |
<> | 144:ef7eb2e8f9f7 | 4829 | /* Enable TC interrupts */ |
<> | 144:ef7eb2e8f9f7 | 4830 | tmpisr |= I2C_IT_TCI; |
<> | 144:ef7eb2e8f9f7 | 4831 | } |
<> | 144:ef7eb2e8f9f7 | 4832 | |
<> | 144:ef7eb2e8f9f7 | 4833 | /* Disable interrupts only at the end */ |
<> | 144:ef7eb2e8f9f7 | 4834 | /* to avoid a breaking situation like at "t" time */ |
<> | 144:ef7eb2e8f9f7 | 4835 | /* all disable interrupts request are not done */ |
<> | 144:ef7eb2e8f9f7 | 4836 | __HAL_I2C_DISABLE_IT(hi2c, tmpisr); |
<> | 144:ef7eb2e8f9f7 | 4837 | |
<> | 144:ef7eb2e8f9f7 | 4838 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 4839 | } |
<> | 144:ef7eb2e8f9f7 | 4840 | |
<> | 144:ef7eb2e8f9f7 | 4841 | /** |
<> | 144:ef7eb2e8f9f7 | 4842 | * @} |
<> | 156:95d6b41a828b | 4843 | */ |
<> | 144:ef7eb2e8f9f7 | 4844 | |
<> | 144:ef7eb2e8f9f7 | 4845 | #endif /* HAL_I2C_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 4846 | /** |
<> | 144:ef7eb2e8f9f7 | 4847 | * @} |
<> | 144:ef7eb2e8f9f7 | 4848 | */ |
<> | 144:ef7eb2e8f9f7 | 4849 | |
<> | 144:ef7eb2e8f9f7 | 4850 | /** |
<> | 144:ef7eb2e8f9f7 | 4851 | * @} |
<> | 144:ef7eb2e8f9f7 | 4852 | */ |
<> | 144:ef7eb2e8f9f7 | 4853 | |
<> | 144:ef7eb2e8f9f7 | 4854 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |