mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/TOOLCHAIN_GCC_ARM/startup_stm32f091xc.S@180:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
180:96ed750bd169
Parent:
150:02e0a0aed4ec 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file startup_stm32f091xc.s
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
Anna Bridge 180:96ed750bd169 5 * @brief STM32F091xC devices vector table for GCC toolchain.
<> 144:ef7eb2e8f9f7 6 * This module performs:
<> 144:ef7eb2e8f9f7 7 * - Set the initial SP
<> 144:ef7eb2e8f9f7 8 * - Set the initial PC == Reset_Handler,
<> 144:ef7eb2e8f9f7 9 * - Set the vector table entries with the exceptions ISR address
<> 144:ef7eb2e8f9f7 10 * - Branches to main in the C library (which eventually
<> 144:ef7eb2e8f9f7 11 * calls main()).
<> 144:ef7eb2e8f9f7 12 * After Reset the Cortex-M0 processor is in Thread mode,
<> 144:ef7eb2e8f9f7 13 * priority is Privileged, and the Stack is set to Main.
<> 144:ef7eb2e8f9f7 14 ******************************************************************************
<> 144:ef7eb2e8f9f7 15 *
<> 144:ef7eb2e8f9f7 16 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 17 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 18 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 19 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 20 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 21 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 22 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 23 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 24 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 25 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 28 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 30 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 34 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 37 *
<> 144:ef7eb2e8f9f7 38 ******************************************************************************
<> 144:ef7eb2e8f9f7 39 */
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 .syntax unified
<> 144:ef7eb2e8f9f7 42 .cpu cortex-m0
<> 144:ef7eb2e8f9f7 43 .fpu softvfp
<> 144:ef7eb2e8f9f7 44 .thumb
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 .global g_pfnVectors
<> 144:ef7eb2e8f9f7 47 .global Default_Handler
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /* start address for the initialization values of the .data section.
<> 144:ef7eb2e8f9f7 50 defined in linker script */
<> 144:ef7eb2e8f9f7 51 .word _sidata
<> 144:ef7eb2e8f9f7 52 /* start address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 53 .word _sdata
<> 144:ef7eb2e8f9f7 54 /* end address for the .data section. defined in linker script */
<> 144:ef7eb2e8f9f7 55 .word _edata
Anna Bridge 180:96ed750bd169 56 /* start address for the .bss section. defined in linker script */
Anna Bridge 180:96ed750bd169 57 .word _sbss
Anna Bridge 180:96ed750bd169 58 /* end address for the .bss section. defined in linker script */
Anna Bridge 180:96ed750bd169 59 .word _ebss
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 .section .text.Reset_Handler
<> 144:ef7eb2e8f9f7 62 .weak Reset_Handler
<> 144:ef7eb2e8f9f7 63 .type Reset_Handler, %function
<> 144:ef7eb2e8f9f7 64 Reset_Handler:
<> 144:ef7eb2e8f9f7 65 ldr r0, =_estack
<> 144:ef7eb2e8f9f7 66 mov sp, r0 /* set stack pointer */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* Copy the data segment initializers from flash to SRAM */
Anna Bridge 180:96ed750bd169 69 ldr r0, =_sdata
Anna Bridge 180:96ed750bd169 70 ldr r1, =_edata
Anna Bridge 180:96ed750bd169 71 ldr r2, =_sidata
Anna Bridge 180:96ed750bd169 72 movs r3, #0
<> 144:ef7eb2e8f9f7 73 b LoopCopyDataInit
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 CopyDataInit:
Anna Bridge 180:96ed750bd169 76 ldr r4, [r2, r3]
Anna Bridge 180:96ed750bd169 77 str r4, [r0, r3]
Anna Bridge 180:96ed750bd169 78 adds r3, r3, #4
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 LoopCopyDataInit:
Anna Bridge 180:96ed750bd169 81 adds r4, r0, r3
Anna Bridge 180:96ed750bd169 82 cmp r4, r1
<> 144:ef7eb2e8f9f7 83 bcc CopyDataInit
Anna Bridge 180:96ed750bd169 84
Anna Bridge 180:96ed750bd169 85 /* Zero fill the bss segment. */
Anna Bridge 180:96ed750bd169 86 ldr r2, =_sbss
Anna Bridge 180:96ed750bd169 87 ldr r4, =_ebss
Anna Bridge 180:96ed750bd169 88 movs r3, #0
Anna Bridge 180:96ed750bd169 89 b LoopFillZerobss
Anna Bridge 180:96ed750bd169 90
Anna Bridge 180:96ed750bd169 91 FillZerobss:
Anna Bridge 180:96ed750bd169 92 str r3, [r2]
Anna Bridge 180:96ed750bd169 93 adds r2, r2, #4
Anna Bridge 180:96ed750bd169 94
Anna Bridge 180:96ed750bd169 95 LoopFillZerobss:
Anna Bridge 180:96ed750bd169 96 cmp r2, r4
Anna Bridge 180:96ed750bd169 97 bcc FillZerobss
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Call the clock system intitialization function.*/
<> 144:ef7eb2e8f9f7 100 bl SystemInit
<> 144:ef7eb2e8f9f7 101 /* Call static constructors */
<> 144:ef7eb2e8f9f7 102 //bl __libc_init_array
<> 144:ef7eb2e8f9f7 103 /* Call the application's entry point.*/
<> 144:ef7eb2e8f9f7 104 //bl main
<> 144:ef7eb2e8f9f7 105 /**
<> 144:ef7eb2e8f9f7 106 * Calling the crt0 'cold-start' entry point. There __libc_init_array is called
<> 144:ef7eb2e8f9f7 107 * and when existing hardware_init_hook() and software_init_hook() before
<> 144:ef7eb2e8f9f7 108 * starting main(). software_init_hook() is available and has to be called due
<> 144:ef7eb2e8f9f7 109 * to initializsation when using rtos.
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 bl _start
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 LoopForever:
<> 144:ef7eb2e8f9f7 114 b LoopForever
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 .size Reset_Handler, .-Reset_Handler
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @brief This is the code that gets called when the processor receives an
<> 144:ef7eb2e8f9f7 121 * unexpected interrupt. This simply enters an infinite loop, preserving
<> 144:ef7eb2e8f9f7 122 * the system state for examination by a debugger.
<> 144:ef7eb2e8f9f7 123 *
<> 144:ef7eb2e8f9f7 124 * @param None
<> 144:ef7eb2e8f9f7 125 * @retval : None
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 .section .text.Default_Handler,"ax",%progbits
<> 144:ef7eb2e8f9f7 128 Default_Handler:
<> 144:ef7eb2e8f9f7 129 Infinite_Loop:
<> 144:ef7eb2e8f9f7 130 b Infinite_Loop
<> 144:ef7eb2e8f9f7 131 .size Default_Handler, .-Default_Handler
<> 144:ef7eb2e8f9f7 132 /******************************************************************************
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 * The minimal vector table for a Cortex M0. Note that the proper constructs
<> 144:ef7eb2e8f9f7 135 * must be placed on this to ensure that it ends up at physical address
<> 144:ef7eb2e8f9f7 136 * 0x0000.0000.
<> 144:ef7eb2e8f9f7 137 *
<> 144:ef7eb2e8f9f7 138 ******************************************************************************/
<> 144:ef7eb2e8f9f7 139 .section .isr_vector,"a",%progbits
<> 144:ef7eb2e8f9f7 140 .type g_pfnVectors, %object
<> 144:ef7eb2e8f9f7 141 .size g_pfnVectors, .-g_pfnVectors
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 g_pfnVectors:
<> 144:ef7eb2e8f9f7 145 .word _estack
<> 144:ef7eb2e8f9f7 146 .word Reset_Handler
<> 144:ef7eb2e8f9f7 147 .word NMI_Handler
<> 144:ef7eb2e8f9f7 148 .word HardFault_Handler
<> 144:ef7eb2e8f9f7 149 .word 0
<> 144:ef7eb2e8f9f7 150 .word 0
<> 144:ef7eb2e8f9f7 151 .word 0
<> 144:ef7eb2e8f9f7 152 .word 0
<> 144:ef7eb2e8f9f7 153 .word 0
<> 144:ef7eb2e8f9f7 154 .word 0
<> 144:ef7eb2e8f9f7 155 .word 0
<> 144:ef7eb2e8f9f7 156 .word SVC_Handler
<> 144:ef7eb2e8f9f7 157 .word 0
<> 144:ef7eb2e8f9f7 158 .word 0
<> 144:ef7eb2e8f9f7 159 .word PendSV_Handler
<> 144:ef7eb2e8f9f7 160 .word SysTick_Handler
<> 144:ef7eb2e8f9f7 161 .word WWDG_IRQHandler /* Window WatchDog */
<> 144:ef7eb2e8f9f7 162 .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */
<> 144:ef7eb2e8f9f7 163 .word RTC_IRQHandler /* RTC through the EXTI line */
<> 144:ef7eb2e8f9f7 164 .word FLASH_IRQHandler /* FLASH */
<> 144:ef7eb2e8f9f7 165 .word RCC_CRS_IRQHandler /* RCC and CRS */
<> 144:ef7eb2e8f9f7 166 .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
<> 144:ef7eb2e8f9f7 167 .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
<> 144:ef7eb2e8f9f7 168 .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
<> 144:ef7eb2e8f9f7 169 .word TSC_IRQHandler /* TSC */
<> 144:ef7eb2e8f9f7 170 .word DMA1_Ch1_IRQHandler /* DMA1 Channel 1 */
<> 144:ef7eb2e8f9f7 171 .word DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler /* DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 */
<> 144:ef7eb2e8f9f7 172 .word DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler /* DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 */
<> 144:ef7eb2e8f9f7 173 .word ADC1_COMP_IRQHandler /* ADC1, COMP1 and COMP2 */
<> 144:ef7eb2e8f9f7 174 .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
<> 144:ef7eb2e8f9f7 175 .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
<> 144:ef7eb2e8f9f7 176 .word TIM2_IRQHandler /* TIM2 */
<> 144:ef7eb2e8f9f7 177 .word TIM3_IRQHandler /* TIM3 */
<> 144:ef7eb2e8f9f7 178 .word TIM6_DAC_IRQHandler /* TIM6 and DAC */
<> 144:ef7eb2e8f9f7 179 .word TIM7_IRQHandler /* TIM7 */
<> 144:ef7eb2e8f9f7 180 .word TIM14_IRQHandler /* TIM14 */
<> 144:ef7eb2e8f9f7 181 .word TIM15_IRQHandler /* TIM15 */
<> 144:ef7eb2e8f9f7 182 .word TIM16_IRQHandler /* TIM16 */
<> 144:ef7eb2e8f9f7 183 .word TIM17_IRQHandler /* TIM17 */
<> 144:ef7eb2e8f9f7 184 .word I2C1_IRQHandler /* I2C1 */
<> 144:ef7eb2e8f9f7 185 .word I2C2_IRQHandler /* I2C2 */
<> 144:ef7eb2e8f9f7 186 .word SPI1_IRQHandler /* SPI1 */
<> 144:ef7eb2e8f9f7 187 .word SPI2_IRQHandler /* SPI2 */
<> 144:ef7eb2e8f9f7 188 .word USART1_IRQHandler /* USART1 */
<> 144:ef7eb2e8f9f7 189 .word USART2_IRQHandler /* USART2 */
<> 144:ef7eb2e8f9f7 190 .word USART3_8_IRQHandler /* USART3, USART4, USART5, USART6, USART7, USART8 */
<> 144:ef7eb2e8f9f7 191 .word CEC_CAN_IRQHandler /* CEC and CAN */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /*******************************************************************************
<> 144:ef7eb2e8f9f7 194 *
<> 144:ef7eb2e8f9f7 195 * Provide weak aliases for each Exception handler to the Default_Handler.
<> 144:ef7eb2e8f9f7 196 * As they are weak aliases, any function with the same name will override
<> 144:ef7eb2e8f9f7 197 * this definition.
<> 144:ef7eb2e8f9f7 198 *
<> 144:ef7eb2e8f9f7 199 *******************************************************************************/
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 .weak NMI_Handler
<> 144:ef7eb2e8f9f7 202 .thumb_set NMI_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 .weak HardFault_Handler
<> 144:ef7eb2e8f9f7 205 .thumb_set HardFault_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 .weak SVC_Handler
<> 144:ef7eb2e8f9f7 208 .thumb_set SVC_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 .weak PendSV_Handler
<> 144:ef7eb2e8f9f7 211 .thumb_set PendSV_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 .weak SysTick_Handler
<> 144:ef7eb2e8f9f7 214 .thumb_set SysTick_Handler,Default_Handler
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 .weak WWDG_IRQHandler
<> 144:ef7eb2e8f9f7 217 .thumb_set WWDG_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 .weak PVD_VDDIO2_IRQHandler
<> 144:ef7eb2e8f9f7 220 .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 .weak RTC_IRQHandler
<> 144:ef7eb2e8f9f7 223 .thumb_set RTC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 .weak FLASH_IRQHandler
<> 144:ef7eb2e8f9f7 226 .thumb_set FLASH_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 .weak RCC_CRS_IRQHandler
<> 144:ef7eb2e8f9f7 229 .thumb_set RCC_CRS_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 .weak EXTI0_1_IRQHandler
<> 144:ef7eb2e8f9f7 232 .thumb_set EXTI0_1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 .weak EXTI2_3_IRQHandler
<> 144:ef7eb2e8f9f7 235 .thumb_set EXTI2_3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 .weak EXTI4_15_IRQHandler
<> 144:ef7eb2e8f9f7 238 .thumb_set EXTI4_15_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 .weak TSC_IRQHandler
<> 144:ef7eb2e8f9f7 241 .thumb_set TSC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 .weak DMA1_Ch1_IRQHandler
<> 144:ef7eb2e8f9f7 244 .thumb_set DMA1_Ch1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 .weak DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
<> 144:ef7eb2e8f9f7 247 .thumb_set DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 .weak DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
<> 144:ef7eb2e8f9f7 250 .thumb_set DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 .weak ADC1_COMP_IRQHandler
<> 144:ef7eb2e8f9f7 253 .thumb_set ADC1_COMP_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 .weak TIM1_BRK_UP_TRG_COM_IRQHandler
<> 144:ef7eb2e8f9f7 256 .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 .weak TIM1_CC_IRQHandler
<> 144:ef7eb2e8f9f7 259 .thumb_set TIM1_CC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 .weak TIM2_IRQHandler
<> 144:ef7eb2e8f9f7 262 .thumb_set TIM2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 .weak TIM3_IRQHandler
<> 144:ef7eb2e8f9f7 265 .thumb_set TIM3_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 .weak TIM6_DAC_IRQHandler
<> 144:ef7eb2e8f9f7 268 .thumb_set TIM6_DAC_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 .weak TIM7_IRQHandler
<> 144:ef7eb2e8f9f7 271 .thumb_set TIM7_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 .weak TIM14_IRQHandler
<> 144:ef7eb2e8f9f7 274 .thumb_set TIM14_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 .weak TIM15_IRQHandler
<> 144:ef7eb2e8f9f7 277 .thumb_set TIM15_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 .weak TIM16_IRQHandler
<> 144:ef7eb2e8f9f7 280 .thumb_set TIM16_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 .weak TIM17_IRQHandler
<> 144:ef7eb2e8f9f7 283 .thumb_set TIM17_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 .weak I2C1_IRQHandler
<> 144:ef7eb2e8f9f7 286 .thumb_set I2C1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 .weak I2C2_IRQHandler
<> 144:ef7eb2e8f9f7 289 .thumb_set I2C2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 .weak SPI1_IRQHandler
<> 144:ef7eb2e8f9f7 292 .thumb_set SPI1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 .weak SPI2_IRQHandler
<> 144:ef7eb2e8f9f7 295 .thumb_set SPI2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 .weak USART1_IRQHandler
<> 144:ef7eb2e8f9f7 298 .thumb_set USART1_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 .weak USART2_IRQHandler
<> 144:ef7eb2e8f9f7 301 .thumb_set USART2_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 .weak USART3_8_IRQHandler
<> 144:ef7eb2e8f9f7 304 .thumb_set USART3_8_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 .weak CEC_CAN_IRQHandler
<> 144:ef7eb2e8f9f7 307 .thumb_set CEC_CAN_IRQHandler,Default_Handler
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 310