mbed-dev - mbed library sources. Supersedes mbed-src.

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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_i2c.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 15:03:32 2017 +0000
Revision:: 156:95d6b41a828b
Child:: 180:96ed750bd169

This updates the lib to the mbed lib v134

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_i2c.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @version V1.4.0
<>	156:95d6b41a828b	6	* @date 27-May-2016
<>	156:95d6b41a828b	7	* @brief Header file of I2C LL module.
<>	156:95d6b41a828b	8	******************************************************************************
<>	156:95d6b41a828b	9	* @attention
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	12	*
<>	156:95d6b41a828b	13	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	14	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	18	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	19	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	21	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	22	* without specific prior written permission.
<>	156:95d6b41a828b	23	*
<>	156:95d6b41a828b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	34	*
<>	156:95d6b41a828b	35	******************************************************************************
<>	156:95d6b41a828b	36	*/
<>	156:95d6b41a828b	37
<>	156:95d6b41a828b	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	39	#ifndef __STM32F0xx_LL_I2C_H
<>	156:95d6b41a828b	40	#define __STM32F0xx_LL_I2C_H
<>	156:95d6b41a828b	41
<>	156:95d6b41a828b	42	#ifdef __cplusplus
<>	156:95d6b41a828b	43	extern "C" {
<>	156:95d6b41a828b	44	#endif
<>	156:95d6b41a828b	45
<>	156:95d6b41a828b	46	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	47	#include "stm32f0xx.h"
<>	156:95d6b41a828b	48
<>	156:95d6b41a828b	49	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	50	* @{
<>	156:95d6b41a828b	51	*/
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	#if defined (I2C1) \|\| defined (I2C2)
<>	156:95d6b41a828b	54
<>	156:95d6b41a828b	55	/** @defgroup I2C_LL I2C
<>	156:95d6b41a828b	56	* @{
<>	156:95d6b41a828b	57	*/
<>	156:95d6b41a828b	58
<>	156:95d6b41a828b	59	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	60	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	61
<>	156:95d6b41a828b	62	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
<>	156:95d6b41a828b	64	* @{
<>	156:95d6b41a828b	65	*/
<>	156:95d6b41a828b	66	/* Defines used for the bit position in the register and perform offsets */
<>	156:95d6b41a828b	67	#define I2C_POSITION_CR1_DNF (uint32_t)8U
<>	156:95d6b41a828b	68	#define I2C_POSITION_CR2_NBYTES (uint32_t)16U
<>	156:95d6b41a828b	69	#define I2C_POSITION_TIMINGR_PRESC (uint32_t)28U
<>	156:95d6b41a828b	70	#define I2C_POSITION_TIMINGR_SCLDEL (uint32_t)20U
<>	156:95d6b41a828b	71	#define I2C_POSITION_TIMINGR_SDADEL (uint32_t)16U
<>	156:95d6b41a828b	72	#define I2C_POSITION_TIMINGR_SCLH (uint32_t)8U
<>	156:95d6b41a828b	73	#define I2C_POSITION_TIMINGR_SCLL (uint32_t)0U
<>	156:95d6b41a828b	74	#define I2C_POSITION_ISR_ADDCODE (uint32_t)17U
<>	156:95d6b41a828b	75	#define I2C_POSITION_TIMEOUTR_TIMEOUTB (uint32_t)16U
<>	156:95d6b41a828b	76	/**
<>	156:95d6b41a828b	77	* @}
<>	156:95d6b41a828b	78	*/
<>	156:95d6b41a828b	79
<>	156:95d6b41a828b	80	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	81	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	82	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
<>	156:95d6b41a828b	83	* @{
<>	156:95d6b41a828b	84	*/
<>	156:95d6b41a828b	85	/**
<>	156:95d6b41a828b	86	* @}
<>	156:95d6b41a828b	87	*/
<>	156:95d6b41a828b	88	#endif /USE_FULL_LL_DRIVER/
<>	156:95d6b41a828b	89
<>	156:95d6b41a828b	90	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	91	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	92	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
<>	156:95d6b41a828b	93	* @{
<>	156:95d6b41a828b	94	*/
<>	156:95d6b41a828b	95	typedef struct
<>	156:95d6b41a828b	96	{
<>	156:95d6b41a828b	97	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
<>	156:95d6b41a828b	98	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
<>	156:95d6b41a828b	99
<>	156:95d6b41a828b	100	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
<>	156:95d6b41a828b	101
<>	156:95d6b41a828b	102	uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
<>	156:95d6b41a828b	103	This parameter must be set by referring to the STM32CubeMX Tool and
<>	156:95d6b41a828b	104	the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
<>	156:95d6b41a828b	105
<>	156:95d6b41a828b	106	This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
<>	156:95d6b41a828b	107
<>	156:95d6b41a828b	108	uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
<>	156:95d6b41a828b	109	This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
<>	156:95d6b41a828b	110
<>	156:95d6b41a828b	111	This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
<>	156:95d6b41a828b	112
<>	156:95d6b41a828b	113	uint32_t DigitalFilter; /*!< Configures the digital noise filter.
<>	156:95d6b41a828b	114	This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
<>	156:95d6b41a828b	115
<>	156:95d6b41a828b	116	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
<>	156:95d6b41a828b	117
<>	156:95d6b41a828b	118	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
<>	156:95d6b41a828b	119	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
<>	156:95d6b41a828b	120
<>	156:95d6b41a828b	121	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	156:95d6b41a828b	122
<>	156:95d6b41a828b	123	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	156:95d6b41a828b	124	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
<>	156:95d6b41a828b	125
<>	156:95d6b41a828b	126	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
<>	156:95d6b41a828b	127
<>	156:95d6b41a828b	128	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
<>	156:95d6b41a828b	129	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
<>	156:95d6b41a828b	130
<>	156:95d6b41a828b	131	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
<>	156:95d6b41a828b	132	} LL_I2C_InitTypeDef;
<>	156:95d6b41a828b	133	/**
<>	156:95d6b41a828b	134	* @}
<>	156:95d6b41a828b	135	*/
<>	156:95d6b41a828b	136	#endif /USE_FULL_LL_DRIVER/
<>	156:95d6b41a828b	137
<>	156:95d6b41a828b	138	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	139	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
<>	156:95d6b41a828b	140	* @{
<>	156:95d6b41a828b	141	*/
<>	156:95d6b41a828b	142
<>	156:95d6b41a828b	143	/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	156:95d6b41a828b	144	* @brief Flags defines which can be used with LL_I2C_WriteReg function
<>	156:95d6b41a828b	145	* @{
<>	156:95d6b41a828b	146	*/
<>	156:95d6b41a828b	147	#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /!< Address Matched flag /
<>	156:95d6b41a828b	148	#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /!< Not Acknowledge flag /
<>	156:95d6b41a828b	149	#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /!< Stop detection flag /
<>	156:95d6b41a828b	150	#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /!< Bus error flag /
<>	156:95d6b41a828b	151	#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /!< Arbitration Lost flag /
<>	156:95d6b41a828b	152	#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /!< Overrun/Underrun flag /
<>	156:95d6b41a828b	153	#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /!< PEC error flag /
<>	156:95d6b41a828b	154	#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /!< Timeout detection flag /
<>	156:95d6b41a828b	155	#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /!< Alert flag /
<>	156:95d6b41a828b	156	/**
<>	156:95d6b41a828b	157	* @}
<>	156:95d6b41a828b	158	*/
<>	156:95d6b41a828b	159
<>	156:95d6b41a828b	160	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
<>	156:95d6b41a828b	161	* @brief Flags defines which can be used with LL_I2C_ReadReg function
<>	156:95d6b41a828b	162	* @{
<>	156:95d6b41a828b	163	*/
<>	156:95d6b41a828b	164	#define LL_I2C_ISR_TXE I2C_ISR_TXE /!< Transmit data register empty /
<>	156:95d6b41a828b	165	#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /!< Transmit interrupt status /
<>	156:95d6b41a828b	166	#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /!< Receive data register not empty /
<>	156:95d6b41a828b	167	#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /!< Address matched (slave mode) /
<>	156:95d6b41a828b	168	#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /!< Not Acknowledge received flag /
<>	156:95d6b41a828b	169	#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /!< Stop detection flag /
<>	156:95d6b41a828b	170	#define LL_I2C_ISR_TC I2C_ISR_TC /!< Transfer Complete (master mode) /
<>	156:95d6b41a828b	171	#define LL_I2C_ISR_TCR I2C_ISR_TCR /!< Transfer Complete Reload /
<>	156:95d6b41a828b	172	#define LL_I2C_ISR_BERR I2C_ISR_BERR /!< Bus error /
<>	156:95d6b41a828b	173	#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /!< Arbitration lost /
<>	156:95d6b41a828b	174	#define LL_I2C_ISR_OVR I2C_ISR_OVR /!< Overrun/Underrun (slave mode) /
<>	156:95d6b41a828b	175	#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
<>	156:95d6b41a828b	176	#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
<>	156:95d6b41a828b	177	#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /!< SMBus alert (SMBus mode) /
<>	156:95d6b41a828b	178	#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /!< Bus busy /
<>	156:95d6b41a828b	179	/**
<>	156:95d6b41a828b	180	* @}
<>	156:95d6b41a828b	181	*/
<>	156:95d6b41a828b	182
<>	156:95d6b41a828b	183	/** @defgroup I2C_LL_EC_IT IT Defines
<>	156:95d6b41a828b	184	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
<>	156:95d6b41a828b	185	* @{
<>	156:95d6b41a828b	186	*/
<>	156:95d6b41a828b	187	#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /!< TX Interrupt enable /
<>	156:95d6b41a828b	188	#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /!< RX Interrupt enable /
<>	156:95d6b41a828b	189	#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /!< Address match Interrupt enable (slave only) /
<>	156:95d6b41a828b	190	#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /!< Not acknowledge received Interrupt enable /
<>	156:95d6b41a828b	191	#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /!< STOP detection Interrupt enable /
<>	156:95d6b41a828b	192	#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /!< Transfer Complete interrupt enable /
<>	156:95d6b41a828b	193	#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /!< Error interrupts enable /
<>	156:95d6b41a828b	194	/**
<>	156:95d6b41a828b	195	* @}
<>	156:95d6b41a828b	196	*/
<>	156:95d6b41a828b	197
<>	156:95d6b41a828b	198	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
<>	156:95d6b41a828b	199	* @{
<>	156:95d6b41a828b	200	*/
<>	156:95d6b41a828b	201	#define LL_I2C_MODE_I2C ((uint32_t)0x00000000U) /!< I2C Master or Slave mode /
<>	156:95d6b41a828b	202	#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /!< SMBus Host address acknowledge /
<>	156:95d6b41a828b	203	#define LL_I2C_MODE_SMBUS_DEVICE ((uint32_t)0x00000000U) /!< SMBus Device default mode (Default address not acknowledge) /
<>	156:95d6b41a828b	204	#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /!< SMBus Device Default address acknowledge /
<>	156:95d6b41a828b	205	/**
<>	156:95d6b41a828b	206	* @}
<>	156:95d6b41a828b	207	*/
<>	156:95d6b41a828b	208
<>	156:95d6b41a828b	209	/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
<>	156:95d6b41a828b	210	* @{
<>	156:95d6b41a828b	211	*/
<>	156:95d6b41a828b	212	#define LL_I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) /!< Analog filter is enabled. /
<>	156:95d6b41a828b	213	#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /!< Analog filter is disabled. /
<>	156:95d6b41a828b	214	/**
<>	156:95d6b41a828b	215	* @}
<>	156:95d6b41a828b	216	*/
<>	156:95d6b41a828b	217
<>	156:95d6b41a828b	218	/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
<>	156:95d6b41a828b	219	* @{
<>	156:95d6b41a828b	220	*/
<>	156:95d6b41a828b	221	#define LL_I2C_ADDRESSING_MODE_7BIT ((uint32_t) 0x00000000U) /!< Master operates in 7-bit addressing mode. /
<>	156:95d6b41a828b	222	#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /!< Master operates in 10-bit addressing mode./
<>	156:95d6b41a828b	223	/**
<>	156:95d6b41a828b	224	* @}
<>	156:95d6b41a828b	225	*/
<>	156:95d6b41a828b	226
<>	156:95d6b41a828b	227	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
<>	156:95d6b41a828b	228	* @{
<>	156:95d6b41a828b	229	*/
<>	156:95d6b41a828b	230	#define LL_I2C_OWNADDRESS1_7BIT ((uint32_t)0x00000000U) /!< Own address 1 is a 7-bit address. /
<>	156:95d6b41a828b	231	#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /!< Own address 1 is a 10-bit address./
<>	156:95d6b41a828b	232	/**
<>	156:95d6b41a828b	233	* @}
<>	156:95d6b41a828b	234	*/
<>	156:95d6b41a828b	235
<>	156:95d6b41a828b	236	/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
<>	156:95d6b41a828b	237	* @{
<>	156:95d6b41a828b	238	*/
<>	156:95d6b41a828b	239	#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /!< Own Address2 No mask. /
<>	156:95d6b41a828b	240	#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /!< Only Address2 bits[7:2] are compared. /
<>	156:95d6b41a828b	241	#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /!< Only Address2 bits[7:3] are compared. /
<>	156:95d6b41a828b	242	#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /!< Only Address2 bits[7:4] are compared. /
<>	156:95d6b41a828b	243	#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /!< Only Address2 bits[7:5] are compared. /
<>	156:95d6b41a828b	244	#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /!< Only Address2 bits[7:6] are compared. /
<>	156:95d6b41a828b	245	#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /!< Only Address2 bits[7] are compared. /
<>	156:95d6b41a828b	246	#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /!< No comparison is done. All Address2 are acknowledged./
<>	156:95d6b41a828b	247	/**
<>	156:95d6b41a828b	248	* @}
<>	156:95d6b41a828b	249	*/
<>	156:95d6b41a828b	250
<>	156:95d6b41a828b	251	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
<>	156:95d6b41a828b	252	* @{
<>	156:95d6b41a828b	253	*/
<>	156:95d6b41a828b	254	#define LL_I2C_ACK ((uint32_t) 0x00000000U) /!< ACK is sent after current received byte. /
<>	156:95d6b41a828b	255	#define LL_I2C_NACK I2C_CR2_NACK /!< NACK is sent after current received byte./
<>	156:95d6b41a828b	256	/**
<>	156:95d6b41a828b	257	* @}
<>	156:95d6b41a828b	258	*/
<>	156:95d6b41a828b	259
<>	156:95d6b41a828b	260	/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
<>	156:95d6b41a828b	261	* @{
<>	156:95d6b41a828b	262	*/
<>	156:95d6b41a828b	263	#define LL_I2C_ADDRSLAVE_7BIT ((uint32_t)0x00000000U) /!< Slave Address in 7-bit. /
<>	156:95d6b41a828b	264	#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /!< Slave Address in 10-bit./
<>	156:95d6b41a828b	265	/**
<>	156:95d6b41a828b	266	* @}
<>	156:95d6b41a828b	267	*/
<>	156:95d6b41a828b	268
<>	156:95d6b41a828b	269	/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
<>	156:95d6b41a828b	270	* @{
<>	156:95d6b41a828b	271	*/
<>	156:95d6b41a828b	272	#define LL_I2C_REQUEST_WRITE ((uint32_t)0x00000000U) /!< Master request a write transfer. /
<>	156:95d6b41a828b	273	#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /!< Master request a read transfer. /
<>	156:95d6b41a828b	274	/**
<>	156:95d6b41a828b	275	* @}
<>	156:95d6b41a828b	276	*/
<>	156:95d6b41a828b	277
<>	156:95d6b41a828b	278	/** @defgroup I2C_LL_EC_MODE Transfer End Mode
<>	156:95d6b41a828b	279	* @{
<>	156:95d6b41a828b	280	*/
<>	156:95d6b41a828b	281	#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /!< Enable I2C Reload mode. /
<>	156:95d6b41a828b	282	#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /!< Enable I2C Automatic end mode with no HW PEC comparison. /
<>	156:95d6b41a828b	283	#define LL_I2C_MODE_SOFTEND ((uint32_t)0x00000000U) /!< Enable I2C Software end mode with no HW PEC comparison. /
<>	156:95d6b41a828b	284	#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	156:95d6b41a828b	285	#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	156:95d6b41a828b	286	#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	156:95d6b41a828b	287	#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Automatic end mode with HW PEC comparison. /
<>	156:95d6b41a828b	288	#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND \| I2C_CR2_PECBYTE) /!< Enable SMBUS Software end mode with HW PEC comparison. /
<>	156:95d6b41a828b	289	/**
<>	156:95d6b41a828b	290	* @}
<>	156:95d6b41a828b	291	*/
<>	156:95d6b41a828b	292
<>	156:95d6b41a828b	293	/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
<>	156:95d6b41a828b	294	* @{
<>	156:95d6b41a828b	295	*/
<>	156:95d6b41a828b	296	#define LL_I2C_GENERATE_NOSTARTSTOP ((uint32_t)0x00000000U) /!< Don't Generate Stop and Start condition. /
<>	156:95d6b41a828b	297	#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /!< Generate Stop condition (Size should be set to 0). /
<>	156:95d6b41a828b	298	#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Start for read request. /
<>	156:95d6b41a828b	299	#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /!< Generate Start for write request. /
<>	156:95d6b41a828b	300	#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN) /!< Generate Restart for read request, slave 7Bit address. /
<>	156:95d6b41a828b	301	#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 7Bit address. /
<>	156:95d6b41a828b	302	#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START \| I2C_CR2_RD_WRN \| I2C_CR2_HEAD10R) /!< Generate Restart for read request, slave 10Bit address. /
<>	156:95d6b41a828b	303	#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /!< Generate Restart for write request, slave 10Bit address./
<>	156:95d6b41a828b	304	/**
<>	156:95d6b41a828b	305	* @}
<>	156:95d6b41a828b	306	*/
<>	156:95d6b41a828b	307
<>	156:95d6b41a828b	308	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
<>	156:95d6b41a828b	309	* @{
<>	156:95d6b41a828b	310	*/
<>	156:95d6b41a828b	311	#define LL_I2C_DIRECTION_WRITE ((uint32_t)0x00000000U) /!< Write transfer request by master, slave enters receiver mode. /
<>	156:95d6b41a828b	312	#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /!< Read transfer request by master, slave enters transmitter mode./
<>	156:95d6b41a828b	313	/**
<>	156:95d6b41a828b	314	* @}
<>	156:95d6b41a828b	315	*/
<>	156:95d6b41a828b	316
<>	156:95d6b41a828b	317	/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
<>	156:95d6b41a828b	318	* @{
<>	156:95d6b41a828b	319	*/
<>	156:95d6b41a828b	320	#define LL_I2C_DMA_REG_DATA_TRANSMIT ((uint32_t)0x00000000U) /!< Get address of data register used for transmission /
<>	156:95d6b41a828b	321	#define LL_I2C_DMA_REG_DATA_RECEIVE ((uint32_t)0x00000001U) /!< Get address of data register used for reception /
<>	156:95d6b41a828b	322	/**
<>	156:95d6b41a828b	323	* @}
<>	156:95d6b41a828b	324	*/
<>	156:95d6b41a828b	325
<>	156:95d6b41a828b	326	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
<>	156:95d6b41a828b	327	* @{
<>	156:95d6b41a828b	328	*/
<>	156:95d6b41a828b	329	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW ((uint32_t) 0x00000000U) /!< TimeoutA is used to detect SCL low level timeout. /
<>	156:95d6b41a828b	330	#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /!< TimeoutA is used to detect both SCL and SDA high level timeout./
<>	156:95d6b41a828b	331	/**
<>	156:95d6b41a828b	332	* @}
<>	156:95d6b41a828b	333	*/
<>	156:95d6b41a828b	334
<>	156:95d6b41a828b	335	/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
<>	156:95d6b41a828b	336	* @{
<>	156:95d6b41a828b	337	*/
<>	156:95d6b41a828b	338	#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /!< TimeoutA enable bit /
<>	156:95d6b41a828b	339	#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /!< TimeoutB (extended clock) enable bit /
<>	156:95d6b41a828b	340	#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN) /!< TimeoutA and TimeoutB (extended clock) enable bits /
<>	156:95d6b41a828b	341	/**
<>	156:95d6b41a828b	342	* @}
<>	156:95d6b41a828b	343	*/
<>	156:95d6b41a828b	344
<>	156:95d6b41a828b	345	/**
<>	156:95d6b41a828b	346	* @}
<>	156:95d6b41a828b	347	*/
<>	156:95d6b41a828b	348
<>	156:95d6b41a828b	349	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	350	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
<>	156:95d6b41a828b	351	* @{
<>	156:95d6b41a828b	352	*/
<>	156:95d6b41a828b	353
<>	156:95d6b41a828b	354	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
<>	156:95d6b41a828b	355	* @{
<>	156:95d6b41a828b	356	*/
<>	156:95d6b41a828b	357
<>	156:95d6b41a828b	358	/**
<>	156:95d6b41a828b	359	* @brief Write a value in I2C register
<>	156:95d6b41a828b	360	* @param __INSTANCE__ I2C Instance
<>	156:95d6b41a828b	361	* @param __REG__ Register to be written
<>	156:95d6b41a828b	362	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	363	* @retval None
<>	156:95d6b41a828b	364	*/
<>	156:95d6b41a828b	365	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	366
<>	156:95d6b41a828b	367	/**
<>	156:95d6b41a828b	368	* @brief Read a value in I2C register
<>	156:95d6b41a828b	369	* @param __INSTANCE__ I2C Instance
<>	156:95d6b41a828b	370	* @param __REG__ Register to be read
<>	156:95d6b41a828b	371	* @retval Register value
<>	156:95d6b41a828b	372	*/
<>	156:95d6b41a828b	373	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	374	/**
<>	156:95d6b41a828b	375	* @}
<>	156:95d6b41a828b	376	*/
<>	156:95d6b41a828b	377
<>	156:95d6b41a828b	378	/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
<>	156:95d6b41a828b	379	* @{
<>	156:95d6b41a828b	380	*/
<>	156:95d6b41a828b	381	/**
<>	156:95d6b41a828b	382	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	156:95d6b41a828b	383	* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
<>	156:95d6b41a828b	384	* @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
<>	156:95d6b41a828b	385	* @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
<>	156:95d6b41a828b	386	* @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
<>	156:95d6b41a828b	387	* @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
<>	156:95d6b41a828b	388	* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
<>	156:95d6b41a828b	389	*/
<>	156:95d6b41a828b	390	#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
<>	156:95d6b41a828b	391	((((uint32_t)(__PRESCALER__) << I2C_POSITION_TIMINGR_PRESC) & I2C_TIMINGR_PRESC) \| \
<>	156:95d6b41a828b	392	(((uint32_t)(__DATA_SETUP_TIME__) << I2C_POSITION_TIMINGR_SCLDEL) & I2C_TIMINGR_SCLDEL) \| \
<>	156:95d6b41a828b	393	(((uint32_t)(__DATA_HOLD_TIME__) << I2C_POSITION_TIMINGR_SDADEL) & I2C_TIMINGR_SDADEL) \| \
<>	156:95d6b41a828b	394	(((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_POSITION_TIMINGR_SCLH) & I2C_TIMINGR_SCLH) \| \
<>	156:95d6b41a828b	395	(((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_POSITION_TIMINGR_SCLL) & I2C_TIMINGR_SCLL))
<>	156:95d6b41a828b	396	/**
<>	156:95d6b41a828b	397	* @}
<>	156:95d6b41a828b	398	*/
<>	156:95d6b41a828b	399
<>	156:95d6b41a828b	400	/**
<>	156:95d6b41a828b	401	* @}
<>	156:95d6b41a828b	402	*/
<>	156:95d6b41a828b	403
<>	156:95d6b41a828b	404	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	405	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
<>	156:95d6b41a828b	406	* @{
<>	156:95d6b41a828b	407	*/
<>	156:95d6b41a828b	408
<>	156:95d6b41a828b	409	/** @defgroup I2C_LL_EF_Configuration Configuration
<>	156:95d6b41a828b	410	* @{
<>	156:95d6b41a828b	411	*/
<>	156:95d6b41a828b	412
<>	156:95d6b41a828b	413	/**
<>	156:95d6b41a828b	414	* @brief Enable I2C peripheral (PE = 1).
<>	156:95d6b41a828b	415	* @rmtoll CR1 PE LL_I2C_Enable
<>	156:95d6b41a828b	416	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	417	* @retval None
<>	156:95d6b41a828b	418	*/
<>	156:95d6b41a828b	419	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	420	{
<>	156:95d6b41a828b	421	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	156:95d6b41a828b	422	}
<>	156:95d6b41a828b	423
<>	156:95d6b41a828b	424	/**
<>	156:95d6b41a828b	425	* @brief Disable I2C peripheral (PE = 0).
<>	156:95d6b41a828b	426	* @note When PE = 0, the I2C SCL and SDA lines are released.
<>	156:95d6b41a828b	427	* Internal state machines and status bits are put back to their reset value.
<>	156:95d6b41a828b	428	* When cleared, PE must be kept low for at least 3 APB clock cycles.
<>	156:95d6b41a828b	429	* @rmtoll CR1 PE LL_I2C_Disable
<>	156:95d6b41a828b	430	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	431	* @retval None
<>	156:95d6b41a828b	432	*/
<>	156:95d6b41a828b	433	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	434	{
<>	156:95d6b41a828b	435	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
<>	156:95d6b41a828b	436	}
<>	156:95d6b41a828b	437
<>	156:95d6b41a828b	438	/**
<>	156:95d6b41a828b	439	* @brief Check if the I2C peripheral is enabled or disabled.
<>	156:95d6b41a828b	440	* @rmtoll CR1 PE LL_I2C_IsEnabled
<>	156:95d6b41a828b	441	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	442	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	443	*/
<>	156:95d6b41a828b	444	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	445	{
<>	156:95d6b41a828b	446	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
<>	156:95d6b41a828b	447	}
<>	156:95d6b41a828b	448
<>	156:95d6b41a828b	449	/**
<>	156:95d6b41a828b	450	* @brief Configure Noise Filters (Analog and Digital).
<>	156:95d6b41a828b	451	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	156:95d6b41a828b	452	* The filters can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	453	* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
<>	156:95d6b41a828b	454	* CR1 DNF LL_I2C_ConfigFilters
<>	156:95d6b41a828b	455	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	456	* @param AnalogFilter This parameter can be one of the following values:
<>	156:95d6b41a828b	457	* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
<>	156:95d6b41a828b	458	* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
<>	156:95d6b41a828b	459	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	156:95d6b41a828b	460	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	156:95d6b41a828b	461	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	156:95d6b41a828b	462	* @retval None
<>	156:95d6b41a828b	463	*/
<>	156:95d6b41a828b	464	__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
<>	156:95d6b41a828b	465	{
<>	156:95d6b41a828b	466	MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF \| I2C_CR1_DNF, AnalogFilter \| (DigitalFilter << I2C_POSITION_CR1_DNF));
<>	156:95d6b41a828b	467	}
<>	156:95d6b41a828b	468
<>	156:95d6b41a828b	469	/**
<>	156:95d6b41a828b	470	* @brief Configure Digital Noise Filter.
<>	156:95d6b41a828b	471	* @note If the analog filter is also enabled, the digital filter is added to analog filter.
<>	156:95d6b41a828b	472	* This filter can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	473	* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
<>	156:95d6b41a828b	474	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	475	* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
<>	156:95d6b41a828b	476	* This parameter is used to configure the digital noise filter on SDA and SCL input.
<>	156:95d6b41a828b	477	* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
<>	156:95d6b41a828b	478	* @retval None
<>	156:95d6b41a828b	479	*/
<>	156:95d6b41a828b	480	__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
<>	156:95d6b41a828b	481	{
<>	156:95d6b41a828b	482	MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_POSITION_CR1_DNF);
<>	156:95d6b41a828b	483	}
<>	156:95d6b41a828b	484
<>	156:95d6b41a828b	485	/**
<>	156:95d6b41a828b	486	* @brief Get the current Digital Noise Filter configuration.
<>	156:95d6b41a828b	487	* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
<>	156:95d6b41a828b	488	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	489	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	156:95d6b41a828b	490	*/
<>	156:95d6b41a828b	491	__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	492	{
<>	156:95d6b41a828b	493	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_POSITION_CR1_DNF);
<>	156:95d6b41a828b	494	}
<>	156:95d6b41a828b	495
<>	156:95d6b41a828b	496	/**
<>	156:95d6b41a828b	497	* @brief Enable Analog Noise Filter.
<>	156:95d6b41a828b	498	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	499	* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
<>	156:95d6b41a828b	500	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	501	* @retval None
<>	156:95d6b41a828b	502	*/
<>	156:95d6b41a828b	503	__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	504	{
<>	156:95d6b41a828b	505	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	156:95d6b41a828b	506	}
<>	156:95d6b41a828b	507
<>	156:95d6b41a828b	508	/**
<>	156:95d6b41a828b	509	* @brief Disable Analog Noise Filter.
<>	156:95d6b41a828b	510	* @note This filter can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	511	* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
<>	156:95d6b41a828b	512	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	513	* @retval None
<>	156:95d6b41a828b	514	*/
<>	156:95d6b41a828b	515	__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	516	{
<>	156:95d6b41a828b	517	SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
<>	156:95d6b41a828b	518	}
<>	156:95d6b41a828b	519
<>	156:95d6b41a828b	520	/**
<>	156:95d6b41a828b	521	* @brief Check if Analog Noise Filter is enabled or disabled.
<>	156:95d6b41a828b	522	* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
<>	156:95d6b41a828b	523	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	524	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	525	*/
<>	156:95d6b41a828b	526	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	527	{
<>	156:95d6b41a828b	528	return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
<>	156:95d6b41a828b	529	}
<>	156:95d6b41a828b	530
<>	156:95d6b41a828b	531	/**
<>	156:95d6b41a828b	532	* @brief Enable DMA transmission requests.
<>	156:95d6b41a828b	533	* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
<>	156:95d6b41a828b	534	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	535	* @retval None
<>	156:95d6b41a828b	536	*/
<>	156:95d6b41a828b	537	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	538	{
<>	156:95d6b41a828b	539	SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	156:95d6b41a828b	540	}
<>	156:95d6b41a828b	541
<>	156:95d6b41a828b	542	/**
<>	156:95d6b41a828b	543	* @brief Disable DMA transmission requests.
<>	156:95d6b41a828b	544	* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
<>	156:95d6b41a828b	545	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	546	* @retval None
<>	156:95d6b41a828b	547	*/
<>	156:95d6b41a828b	548	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	549	{
<>	156:95d6b41a828b	550	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
<>	156:95d6b41a828b	551	}
<>	156:95d6b41a828b	552
<>	156:95d6b41a828b	553	/**
<>	156:95d6b41a828b	554	* @brief Check if DMA transmission requests are enabled or disabled.
<>	156:95d6b41a828b	555	* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
<>	156:95d6b41a828b	556	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	557	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	558	*/
<>	156:95d6b41a828b	559	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	560	{
<>	156:95d6b41a828b	561	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
<>	156:95d6b41a828b	562	}
<>	156:95d6b41a828b	563
<>	156:95d6b41a828b	564	/**
<>	156:95d6b41a828b	565	* @brief Enable DMA reception requests.
<>	156:95d6b41a828b	566	* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
<>	156:95d6b41a828b	567	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	568	* @retval None
<>	156:95d6b41a828b	569	*/
<>	156:95d6b41a828b	570	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	571	{
<>	156:95d6b41a828b	572	SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	156:95d6b41a828b	573	}
<>	156:95d6b41a828b	574
<>	156:95d6b41a828b	575	/**
<>	156:95d6b41a828b	576	* @brief Disable DMA reception requests.
<>	156:95d6b41a828b	577	* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
<>	156:95d6b41a828b	578	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	579	* @retval None
<>	156:95d6b41a828b	580	*/
<>	156:95d6b41a828b	581	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	582	{
<>	156:95d6b41a828b	583	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
<>	156:95d6b41a828b	584	}
<>	156:95d6b41a828b	585
<>	156:95d6b41a828b	586	/**
<>	156:95d6b41a828b	587	* @brief Check if DMA reception requests are enabled or disabled.
<>	156:95d6b41a828b	588	* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
<>	156:95d6b41a828b	589	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	590	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	591	*/
<>	156:95d6b41a828b	592	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	593	{
<>	156:95d6b41a828b	594	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
<>	156:95d6b41a828b	595	}
<>	156:95d6b41a828b	596
<>	156:95d6b41a828b	597	/**
<>	156:95d6b41a828b	598	* @brief Get the data register address used for DMA transfer
<>	156:95d6b41a828b	599	* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
<>	156:95d6b41a828b	600	* RXDR RXDATA LL_I2C_DMA_GetRegAddr
<>	156:95d6b41a828b	601	* @param I2Cx I2C Instance
<>	156:95d6b41a828b	602	* @param Direction This parameter can be one of the following values:
<>	156:95d6b41a828b	603	* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
<>	156:95d6b41a828b	604	* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
<>	156:95d6b41a828b	605	* @retval Address of data register
<>	156:95d6b41a828b	606	*/
<>	156:95d6b41a828b	607	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
<>	156:95d6b41a828b	608	{
<>	156:95d6b41a828b	609	register uint32_t data_reg_addr = 0U;
<>	156:95d6b41a828b	610
<>	156:95d6b41a828b	611	if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
<>	156:95d6b41a828b	612	{
<>	156:95d6b41a828b	613	/* return address of TXDR register */
<>	156:95d6b41a828b	614	data_reg_addr = (uint32_t) & (I2Cx->TXDR);
<>	156:95d6b41a828b	615	}
<>	156:95d6b41a828b	616	else
<>	156:95d6b41a828b	617	{
<>	156:95d6b41a828b	618	/* return address of RXDR register */
<>	156:95d6b41a828b	619	data_reg_addr = (uint32_t) & (I2Cx->RXDR);
<>	156:95d6b41a828b	620	}
<>	156:95d6b41a828b	621
<>	156:95d6b41a828b	622	return data_reg_addr;
<>	156:95d6b41a828b	623	}
<>	156:95d6b41a828b	624
<>	156:95d6b41a828b	625	/**
<>	156:95d6b41a828b	626	* @brief Enable Clock stretching.
<>	156:95d6b41a828b	627	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	628	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
<>	156:95d6b41a828b	629	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	630	* @retval None
<>	156:95d6b41a828b	631	*/
<>	156:95d6b41a828b	632	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	633	{
<>	156:95d6b41a828b	634	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	156:95d6b41a828b	635	}
<>	156:95d6b41a828b	636
<>	156:95d6b41a828b	637	/**
<>	156:95d6b41a828b	638	* @brief Disable Clock stretching.
<>	156:95d6b41a828b	639	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	640	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
<>	156:95d6b41a828b	641	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	642	* @retval None
<>	156:95d6b41a828b	643	*/
<>	156:95d6b41a828b	644	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	645	{
<>	156:95d6b41a828b	646	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
<>	156:95d6b41a828b	647	}
<>	156:95d6b41a828b	648
<>	156:95d6b41a828b	649	/**
<>	156:95d6b41a828b	650	* @brief Check if Clock stretching is enabled or disabled.
<>	156:95d6b41a828b	651	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
<>	156:95d6b41a828b	652	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	653	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	654	*/
<>	156:95d6b41a828b	655	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	656	{
<>	156:95d6b41a828b	657	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
<>	156:95d6b41a828b	658	}
<>	156:95d6b41a828b	659
<>	156:95d6b41a828b	660	/**
<>	156:95d6b41a828b	661	* @brief Enable hardware byte control in slave mode.
<>	156:95d6b41a828b	662	* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
<>	156:95d6b41a828b	663	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	664	* @retval None
<>	156:95d6b41a828b	665	*/
<>	156:95d6b41a828b	666	__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	667	{
<>	156:95d6b41a828b	668	SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	156:95d6b41a828b	669	}
<>	156:95d6b41a828b	670
<>	156:95d6b41a828b	671	/**
<>	156:95d6b41a828b	672	* @brief Disable hardware byte control in slave mode.
<>	156:95d6b41a828b	673	* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
<>	156:95d6b41a828b	674	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	675	* @retval None
<>	156:95d6b41a828b	676	*/
<>	156:95d6b41a828b	677	__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	678	{
<>	156:95d6b41a828b	679	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
<>	156:95d6b41a828b	680	}
<>	156:95d6b41a828b	681
<>	156:95d6b41a828b	682	/**
<>	156:95d6b41a828b	683	* @brief Check if hardware byte control in slave mode is enabled or disabled.
<>	156:95d6b41a828b	684	* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
<>	156:95d6b41a828b	685	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	686	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	687	*/
<>	156:95d6b41a828b	688	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	689	{
<>	156:95d6b41a828b	690	return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
<>	156:95d6b41a828b	691	}
<>	156:95d6b41a828b	692
<>	156:95d6b41a828b	693	#if defined(I2C_CR1_WUPEN)
<>	156:95d6b41a828b	694	/**
<>	156:95d6b41a828b	695	* @brief Enable Wakeup from STOP.
<>	156:95d6b41a828b	696	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	697	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	698	* @note This bit can only be programmed when Digital Filter is disabled.
<>	156:95d6b41a828b	699	* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
<>	156:95d6b41a828b	700	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	701	* @retval None
<>	156:95d6b41a828b	702	*/
<>	156:95d6b41a828b	703	__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	704	{
<>	156:95d6b41a828b	705	SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	156:95d6b41a828b	706	}
<>	156:95d6b41a828b	707
<>	156:95d6b41a828b	708	/**
<>	156:95d6b41a828b	709	* @brief Disable Wakeup from STOP.
<>	156:95d6b41a828b	710	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	711	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	712	* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
<>	156:95d6b41a828b	713	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	714	* @retval None
<>	156:95d6b41a828b	715	*/
<>	156:95d6b41a828b	716	__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	717	{
<>	156:95d6b41a828b	718	CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
<>	156:95d6b41a828b	719	}
<>	156:95d6b41a828b	720
<>	156:95d6b41a828b	721	/**
<>	156:95d6b41a828b	722	* @brief Check if Wakeup from STOP is enabled or disabled.
<>	156:95d6b41a828b	723	* @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	724	* WakeUpFromStop feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	725	* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
<>	156:95d6b41a828b	726	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	727	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	728	*/
<>	156:95d6b41a828b	729	__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	730	{
<>	156:95d6b41a828b	731	return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN));
<>	156:95d6b41a828b	732	}
<>	156:95d6b41a828b	733	#endif
<>	156:95d6b41a828b	734
<>	156:95d6b41a828b	735	/**
<>	156:95d6b41a828b	736	* @brief Enable General Call.
<>	156:95d6b41a828b	737	* @note When enabled the Address 0x00 is ACKed.
<>	156:95d6b41a828b	738	* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
<>	156:95d6b41a828b	739	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	740	* @retval None
<>	156:95d6b41a828b	741	*/
<>	156:95d6b41a828b	742	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	743	{
<>	156:95d6b41a828b	744	SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	156:95d6b41a828b	745	}
<>	156:95d6b41a828b	746
<>	156:95d6b41a828b	747	/**
<>	156:95d6b41a828b	748	* @brief Disable General Call.
<>	156:95d6b41a828b	749	* @note When disabled the Address 0x00 is NACKed.
<>	156:95d6b41a828b	750	* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
<>	156:95d6b41a828b	751	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	752	* @retval None
<>	156:95d6b41a828b	753	*/
<>	156:95d6b41a828b	754	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	755	{
<>	156:95d6b41a828b	756	CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
<>	156:95d6b41a828b	757	}
<>	156:95d6b41a828b	758
<>	156:95d6b41a828b	759	/**
<>	156:95d6b41a828b	760	* @brief Check if General Call is enabled or disabled.
<>	156:95d6b41a828b	761	* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
<>	156:95d6b41a828b	762	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	763	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	764	*/
<>	156:95d6b41a828b	765	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	766	{
<>	156:95d6b41a828b	767	return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
<>	156:95d6b41a828b	768	}
<>	156:95d6b41a828b	769
<>	156:95d6b41a828b	770	/**
<>	156:95d6b41a828b	771	* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
<>	156:95d6b41a828b	772	* @note Changing this bit is not allowed, when the START bit is set.
<>	156:95d6b41a828b	773	* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
<>	156:95d6b41a828b	774	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	775	* @param AddressingMode This parameter can be one of the following values:
<>	156:95d6b41a828b	776	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	156:95d6b41a828b	777	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	156:95d6b41a828b	778	* @retval None
<>	156:95d6b41a828b	779	*/
<>	156:95d6b41a828b	780	__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
<>	156:95d6b41a828b	781	{
<>	156:95d6b41a828b	782	MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
<>	156:95d6b41a828b	783	}
<>	156:95d6b41a828b	784
<>	156:95d6b41a828b	785	/**
<>	156:95d6b41a828b	786	* @brief Get the Master addressing mode.
<>	156:95d6b41a828b	787	* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
<>	156:95d6b41a828b	788	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	789	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	790	* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
<>	156:95d6b41a828b	791	* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
<>	156:95d6b41a828b	792	*/
<>	156:95d6b41a828b	793	__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	794	{
<>	156:95d6b41a828b	795	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
<>	156:95d6b41a828b	796	}
<>	156:95d6b41a828b	797
<>	156:95d6b41a828b	798	/**
<>	156:95d6b41a828b	799	* @brief Set the Own Address1.
<>	156:95d6b41a828b	800	* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
<>	156:95d6b41a828b	801	* OAR1 OA1MODE LL_I2C_SetOwnAddress1
<>	156:95d6b41a828b	802	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	803	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
<>	156:95d6b41a828b	804	* @param OwnAddrSize This parameter can be one of the following values:
<>	156:95d6b41a828b	805	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
<>	156:95d6b41a828b	806	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
<>	156:95d6b41a828b	807	* @retval None
<>	156:95d6b41a828b	808	*/
<>	156:95d6b41a828b	809	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
<>	156:95d6b41a828b	810	{
<>	156:95d6b41a828b	811	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 \| I2C_OAR1_OA1MODE, OwnAddress1 \| OwnAddrSize);
<>	156:95d6b41a828b	812	}
<>	156:95d6b41a828b	813
<>	156:95d6b41a828b	814	/**
<>	156:95d6b41a828b	815	* @brief Enable acknowledge on Own Address1 match address.
<>	156:95d6b41a828b	816	* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
<>	156:95d6b41a828b	817	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	818	* @retval None
<>	156:95d6b41a828b	819	*/
<>	156:95d6b41a828b	820	__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	821	{
<>	156:95d6b41a828b	822	SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	156:95d6b41a828b	823	}
<>	156:95d6b41a828b	824
<>	156:95d6b41a828b	825	/**
<>	156:95d6b41a828b	826	* @brief Disable acknowledge on Own Address1 match address.
<>	156:95d6b41a828b	827	* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
<>	156:95d6b41a828b	828	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	829	* @retval None
<>	156:95d6b41a828b	830	*/
<>	156:95d6b41a828b	831	__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	832	{
<>	156:95d6b41a828b	833	CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
<>	156:95d6b41a828b	834	}
<>	156:95d6b41a828b	835
<>	156:95d6b41a828b	836	/**
<>	156:95d6b41a828b	837	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	156:95d6b41a828b	838	* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
<>	156:95d6b41a828b	839	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	840	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	841	*/
<>	156:95d6b41a828b	842	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	843	{
<>	156:95d6b41a828b	844	return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
<>	156:95d6b41a828b	845	}
<>	156:95d6b41a828b	846
<>	156:95d6b41a828b	847	/**
<>	156:95d6b41a828b	848	* @brief Set the 7bits Own Address2.
<>	156:95d6b41a828b	849	* @note This action has no effect if own address2 is enabled.
<>	156:95d6b41a828b	850	* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
<>	156:95d6b41a828b	851	* OAR2 OA2MSK LL_I2C_SetOwnAddress2
<>	156:95d6b41a828b	852	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	853	* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
<>	156:95d6b41a828b	854	* @param OwnAddrMask This parameter can be one of the following values:
<>	156:95d6b41a828b	855	* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
<>	156:95d6b41a828b	856	* @arg @ref LL_I2C_OWNADDRESS2_MASK01
<>	156:95d6b41a828b	857	* @arg @ref LL_I2C_OWNADDRESS2_MASK02
<>	156:95d6b41a828b	858	* @arg @ref LL_I2C_OWNADDRESS2_MASK03
<>	156:95d6b41a828b	859	* @arg @ref LL_I2C_OWNADDRESS2_MASK04
<>	156:95d6b41a828b	860	* @arg @ref LL_I2C_OWNADDRESS2_MASK05
<>	156:95d6b41a828b	861	* @arg @ref LL_I2C_OWNADDRESS2_MASK06
<>	156:95d6b41a828b	862	* @arg @ref LL_I2C_OWNADDRESS2_MASK07
<>	156:95d6b41a828b	863	* @retval None
<>	156:95d6b41a828b	864	*/
<>	156:95d6b41a828b	865	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
<>	156:95d6b41a828b	866	{
<>	156:95d6b41a828b	867	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 \| I2C_OAR2_OA2MSK, OwnAddress2 \| OwnAddrMask);
<>	156:95d6b41a828b	868	}
<>	156:95d6b41a828b	869
<>	156:95d6b41a828b	870	/**
<>	156:95d6b41a828b	871	* @brief Enable acknowledge on Own Address2 match address.
<>	156:95d6b41a828b	872	* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
<>	156:95d6b41a828b	873	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	874	* @retval None
<>	156:95d6b41a828b	875	*/
<>	156:95d6b41a828b	876	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	877	{
<>	156:95d6b41a828b	878	SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	156:95d6b41a828b	879	}
<>	156:95d6b41a828b	880
<>	156:95d6b41a828b	881	/**
<>	156:95d6b41a828b	882	* @brief Disable acknowledge on Own Address2 match address.
<>	156:95d6b41a828b	883	* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
<>	156:95d6b41a828b	884	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	885	* @retval None
<>	156:95d6b41a828b	886	*/
<>	156:95d6b41a828b	887	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	888	{
<>	156:95d6b41a828b	889	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
<>	156:95d6b41a828b	890	}
<>	156:95d6b41a828b	891
<>	156:95d6b41a828b	892	/**
<>	156:95d6b41a828b	893	* @brief Check if Own Address1 acknowledge is enabled or disabled.
<>	156:95d6b41a828b	894	* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
<>	156:95d6b41a828b	895	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	896	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	897	*/
<>	156:95d6b41a828b	898	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	899	{
<>	156:95d6b41a828b	900	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
<>	156:95d6b41a828b	901	}
<>	156:95d6b41a828b	902
<>	156:95d6b41a828b	903	/**
<>	156:95d6b41a828b	904	* @brief Configure the SDA setup, hold time and the SCL high, low period.
<>	156:95d6b41a828b	905	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
<>	156:95d6b41a828b	906	* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
<>	156:95d6b41a828b	907	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	908	* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
<>	156:95d6b41a828b	909	* @note This parameter is computed with the STM32CubeMX Tool.
<>	156:95d6b41a828b	910	* @retval None
<>	156:95d6b41a828b	911	*/
<>	156:95d6b41a828b	912	__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
<>	156:95d6b41a828b	913	{
<>	156:95d6b41a828b	914	WRITE_REG(I2Cx->TIMINGR, Timing);
<>	156:95d6b41a828b	915	}
<>	156:95d6b41a828b	916
<>	156:95d6b41a828b	917	/**
<>	156:95d6b41a828b	918	* @brief Get the Timing Prescaler setting.
<>	156:95d6b41a828b	919	* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
<>	156:95d6b41a828b	920	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	921	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	156:95d6b41a828b	922	*/
<>	156:95d6b41a828b	923	__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	924	{
<>	156:95d6b41a828b	925	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_POSITION_TIMINGR_PRESC);
<>	156:95d6b41a828b	926	}
<>	156:95d6b41a828b	927
<>	156:95d6b41a828b	928	/**
<>	156:95d6b41a828b	929	* @brief Get the SCL low period setting.
<>	156:95d6b41a828b	930	* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
<>	156:95d6b41a828b	931	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	932	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	933	*/
<>	156:95d6b41a828b	934	__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	935	{
<>	156:95d6b41a828b	936	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_POSITION_TIMINGR_SCLL);
<>	156:95d6b41a828b	937	}
<>	156:95d6b41a828b	938
<>	156:95d6b41a828b	939	/**
<>	156:95d6b41a828b	940	* @brief Get the SCL high period setting.
<>	156:95d6b41a828b	941	* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
<>	156:95d6b41a828b	942	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	943	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	944	*/
<>	156:95d6b41a828b	945	__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	946	{
<>	156:95d6b41a828b	947	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_POSITION_TIMINGR_SCLH);
<>	156:95d6b41a828b	948	}
<>	156:95d6b41a828b	949
<>	156:95d6b41a828b	950	/**
<>	156:95d6b41a828b	951	* @brief Get the SDA hold time.
<>	156:95d6b41a828b	952	* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
<>	156:95d6b41a828b	953	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	954	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	156:95d6b41a828b	955	*/
<>	156:95d6b41a828b	956	__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	957	{
<>	156:95d6b41a828b	958	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_POSITION_TIMINGR_SDADEL);
<>	156:95d6b41a828b	959	}
<>	156:95d6b41a828b	960
<>	156:95d6b41a828b	961	/**
<>	156:95d6b41a828b	962	* @brief Get the SDA setup time.
<>	156:95d6b41a828b	963	* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
<>	156:95d6b41a828b	964	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	965	* @retval Value between Min_Data=0x0 and Max_Data=0xF
<>	156:95d6b41a828b	966	*/
<>	156:95d6b41a828b	967	__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	968	{
<>	156:95d6b41a828b	969	return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_POSITION_TIMINGR_SCLDEL);
<>	156:95d6b41a828b	970	}
<>	156:95d6b41a828b	971
<>	156:95d6b41a828b	972	/**
<>	156:95d6b41a828b	973	* @brief Configure peripheral mode.
<>	156:95d6b41a828b	974	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	975	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	976	* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
<>	156:95d6b41a828b	977	* CR1 SMBDEN LL_I2C_SetMode
<>	156:95d6b41a828b	978	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	979	* @param PeripheralMode This parameter can be one of the following values:
<>	156:95d6b41a828b	980	* @arg @ref LL_I2C_MODE_I2C
<>	156:95d6b41a828b	981	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	156:95d6b41a828b	982	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	156:95d6b41a828b	983	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	156:95d6b41a828b	984	* @retval None
<>	156:95d6b41a828b	985	*/
<>	156:95d6b41a828b	986	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
<>	156:95d6b41a828b	987	{
<>	156:95d6b41a828b	988	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN, PeripheralMode);
<>	156:95d6b41a828b	989	}
<>	156:95d6b41a828b	990
<>	156:95d6b41a828b	991	/**
<>	156:95d6b41a828b	992	* @brief Get peripheral mode.
<>	156:95d6b41a828b	993	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	994	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	995	* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
<>	156:95d6b41a828b	996	* CR1 SMBDEN LL_I2C_GetMode
<>	156:95d6b41a828b	997	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	998	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	999	* @arg @ref LL_I2C_MODE_I2C
<>	156:95d6b41a828b	1000	* @arg @ref LL_I2C_MODE_SMBUS_HOST
<>	156:95d6b41a828b	1001	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
<>	156:95d6b41a828b	1002	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
<>	156:95d6b41a828b	1003	*/
<>	156:95d6b41a828b	1004	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1005	{
<>	156:95d6b41a828b	1006	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN \| I2C_CR1_SMBDEN));
<>	156:95d6b41a828b	1007	}
<>	156:95d6b41a828b	1008
<>	156:95d6b41a828b	1009	/**
<>	156:95d6b41a828b	1010	* @brief Enable SMBus alert (Host or Device mode)
<>	156:95d6b41a828b	1011	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1012	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1013	* @note SMBus Device mode:
<>	156:95d6b41a828b	1014	* - SMBus Alert pin is drived low and
<>	156:95d6b41a828b	1015	* Alert Response Address Header acknowledge is enabled.
<>	156:95d6b41a828b	1016	* SMBus Host mode:
<>	156:95d6b41a828b	1017	* - SMBus Alert pin management is supported.
<>	156:95d6b41a828b	1018	* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
<>	156:95d6b41a828b	1019	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1020	* @retval None
<>	156:95d6b41a828b	1021	*/
<>	156:95d6b41a828b	1022	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1023	{
<>	156:95d6b41a828b	1024	SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	156:95d6b41a828b	1025	}
<>	156:95d6b41a828b	1026
<>	156:95d6b41a828b	1027	/**
<>	156:95d6b41a828b	1028	* @brief Disable SMBus alert (Host or Device mode)
<>	156:95d6b41a828b	1029	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1030	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1031	* @note SMBus Device mode:
<>	156:95d6b41a828b	1032	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
<>	156:95d6b41a828b	1033	* Alert Response Address Header acknowledge is disabled.
<>	156:95d6b41a828b	1034	* SMBus Host mode:
<>	156:95d6b41a828b	1035	* - SMBus Alert pin management is not supported.
<>	156:95d6b41a828b	1036	* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
<>	156:95d6b41a828b	1037	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1038	* @retval None
<>	156:95d6b41a828b	1039	*/
<>	156:95d6b41a828b	1040	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1041	{
<>	156:95d6b41a828b	1042	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
<>	156:95d6b41a828b	1043	}
<>	156:95d6b41a828b	1044
<>	156:95d6b41a828b	1045	/**
<>	156:95d6b41a828b	1046	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
<>	156:95d6b41a828b	1047	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1048	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1049	* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
<>	156:95d6b41a828b	1050	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1051	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1052	*/
<>	156:95d6b41a828b	1053	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1054	{
<>	156:95d6b41a828b	1055	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
<>	156:95d6b41a828b	1056	}
<>	156:95d6b41a828b	1057
<>	156:95d6b41a828b	1058	/**
<>	156:95d6b41a828b	1059	* @brief Enable SMBus Packet Error Calculation (PEC).
<>	156:95d6b41a828b	1060	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1061	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1062	* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
<>	156:95d6b41a828b	1063	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1064	* @retval None
<>	156:95d6b41a828b	1065	*/
<>	156:95d6b41a828b	1066	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1067	{
<>	156:95d6b41a828b	1068	SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	156:95d6b41a828b	1069	}
<>	156:95d6b41a828b	1070
<>	156:95d6b41a828b	1071	/**
<>	156:95d6b41a828b	1072	* @brief Disable SMBus Packet Error Calculation (PEC).
<>	156:95d6b41a828b	1073	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1074	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1075	* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
<>	156:95d6b41a828b	1076	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1077	* @retval None
<>	156:95d6b41a828b	1078	*/
<>	156:95d6b41a828b	1079	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1080	{
<>	156:95d6b41a828b	1081	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
<>	156:95d6b41a828b	1082	}
<>	156:95d6b41a828b	1083
<>	156:95d6b41a828b	1084	/**
<>	156:95d6b41a828b	1085	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
<>	156:95d6b41a828b	1086	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1087	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1088	* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
<>	156:95d6b41a828b	1089	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1090	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1091	*/
<>	156:95d6b41a828b	1092	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1093	{
<>	156:95d6b41a828b	1094	return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
<>	156:95d6b41a828b	1095	}
<>	156:95d6b41a828b	1096
<>	156:95d6b41a828b	1097	/**
<>	156:95d6b41a828b	1098	* @brief Configure the SMBus Clock Timeout.
<>	156:95d6b41a828b	1099	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1100	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1101	* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
<>	156:95d6b41a828b	1102	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
<>	156:95d6b41a828b	1103	* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
<>	156:95d6b41a828b	1104	* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
<>	156:95d6b41a828b	1105	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1106	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	156:95d6b41a828b	1107	* @param TimeoutAMode This parameter can be one of the following values:
<>	156:95d6b41a828b	1108	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	156:95d6b41a828b	1109	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	156:95d6b41a828b	1110	* @param TimeoutB
<>	156:95d6b41a828b	1111	* @retval None
<>	156:95d6b41a828b	1112	*/
<>	156:95d6b41a828b	1113	__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
<>	156:95d6b41a828b	1114	uint32_t TimeoutB)
<>	156:95d6b41a828b	1115	{
<>	156:95d6b41a828b	1116	MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA \| I2C_TIMEOUTR_TIDLE \| I2C_TIMEOUTR_TIMEOUTB,
<>	156:95d6b41a828b	1117	TimeoutA \| TimeoutAMode \| (TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB));
<>	156:95d6b41a828b	1118	}
<>	156:95d6b41a828b	1119
<>	156:95d6b41a828b	1120	/**
<>	156:95d6b41a828b	1121	* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
<>	156:95d6b41a828b	1122	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1123	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1124	* @note These bits can only be programmed when TimeoutA is disabled.
<>	156:95d6b41a828b	1125	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
<>	156:95d6b41a828b	1126	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1127	* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	156:95d6b41a828b	1128	* @retval None
<>	156:95d6b41a828b	1129	*/
<>	156:95d6b41a828b	1130	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
<>	156:95d6b41a828b	1131	{
<>	156:95d6b41a828b	1132	WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
<>	156:95d6b41a828b	1133	}
<>	156:95d6b41a828b	1134
<>	156:95d6b41a828b	1135	/**
<>	156:95d6b41a828b	1136	* @brief Get the SMBus Clock TimeoutA setting.
<>	156:95d6b41a828b	1137	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1138	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1139	* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
<>	156:95d6b41a828b	1140	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1141	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	156:95d6b41a828b	1142	*/
<>	156:95d6b41a828b	1143	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1144	{
<>	156:95d6b41a828b	1145	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
<>	156:95d6b41a828b	1146	}
<>	156:95d6b41a828b	1147
<>	156:95d6b41a828b	1148	/**
<>	156:95d6b41a828b	1149	* @brief Set the SMBus Clock TimeoutA mode.
<>	156:95d6b41a828b	1150	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1151	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1152	* @note This bit can only be programmed when TimeoutA is disabled.
<>	156:95d6b41a828b	1153	* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
<>	156:95d6b41a828b	1154	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1155	* @param TimeoutAMode This parameter can be one of the following values:
<>	156:95d6b41a828b	1156	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	156:95d6b41a828b	1157	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	156:95d6b41a828b	1158	* @retval None
<>	156:95d6b41a828b	1159	*/
<>	156:95d6b41a828b	1160	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
<>	156:95d6b41a828b	1161	{
<>	156:95d6b41a828b	1162	WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
<>	156:95d6b41a828b	1163	}
<>	156:95d6b41a828b	1164
<>	156:95d6b41a828b	1165	/**
<>	156:95d6b41a828b	1166	* @brief Get the SMBus Clock TimeoutA mode.
<>	156:95d6b41a828b	1167	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1168	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1169	* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
<>	156:95d6b41a828b	1170	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1171	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1172	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
<>	156:95d6b41a828b	1173	* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
<>	156:95d6b41a828b	1174	*/
<>	156:95d6b41a828b	1175	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1176	{
<>	156:95d6b41a828b	1177	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
<>	156:95d6b41a828b	1178	}
<>	156:95d6b41a828b	1179
<>	156:95d6b41a828b	1180	/**
<>	156:95d6b41a828b	1181	* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
<>	156:95d6b41a828b	1182	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1183	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1184	* @note These bits can only be programmed when TimeoutB is disabled.
<>	156:95d6b41a828b	1185	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
<>	156:95d6b41a828b	1186	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1187	* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
<>	156:95d6b41a828b	1188	* @retval None
<>	156:95d6b41a828b	1189	*/
<>	156:95d6b41a828b	1190	__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
<>	156:95d6b41a828b	1191	{
<>	156:95d6b41a828b	1192	WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_POSITION_TIMEOUTR_TIMEOUTB);
<>	156:95d6b41a828b	1193	}
<>	156:95d6b41a828b	1194
<>	156:95d6b41a828b	1195	/**
<>	156:95d6b41a828b	1196	* @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
<>	156:95d6b41a828b	1197	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1198	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1199	* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
<>	156:95d6b41a828b	1200	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1201	* @retval Value between Min_Data=0 and Max_Data=0xFFF
<>	156:95d6b41a828b	1202	*/
<>	156:95d6b41a828b	1203	__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1204	{
<>	156:95d6b41a828b	1205	return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_POSITION_TIMEOUTR_TIMEOUTB);
<>	156:95d6b41a828b	1206	}
<>	156:95d6b41a828b	1207
<>	156:95d6b41a828b	1208	/**
<>	156:95d6b41a828b	1209	* @brief Enable the SMBus Clock Timeout.
<>	156:95d6b41a828b	1210	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1211	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1212	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
<>	156:95d6b41a828b	1213	* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
<>	156:95d6b41a828b	1214	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1215	* @param ClockTimeout This parameter can be one of the following values:
<>	156:95d6b41a828b	1216	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	156:95d6b41a828b	1217	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	156:95d6b41a828b	1218	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	156:95d6b41a828b	1219	* @retval None
<>	156:95d6b41a828b	1220	*/
<>	156:95d6b41a828b	1221	__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	156:95d6b41a828b	1222	{
<>	156:95d6b41a828b	1223	SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	156:95d6b41a828b	1224	}
<>	156:95d6b41a828b	1225
<>	156:95d6b41a828b	1226	/**
<>	156:95d6b41a828b	1227	* @brief Disable the SMBus Clock Timeout.
<>	156:95d6b41a828b	1228	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1229	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1230	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
<>	156:95d6b41a828b	1231	* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
<>	156:95d6b41a828b	1232	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1233	* @param ClockTimeout This parameter can be one of the following values:
<>	156:95d6b41a828b	1234	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	156:95d6b41a828b	1235	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	156:95d6b41a828b	1236	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	156:95d6b41a828b	1237	* @retval None
<>	156:95d6b41a828b	1238	*/
<>	156:95d6b41a828b	1239	__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	156:95d6b41a828b	1240	{
<>	156:95d6b41a828b	1241	CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
<>	156:95d6b41a828b	1242	}
<>	156:95d6b41a828b	1243
<>	156:95d6b41a828b	1244	/**
<>	156:95d6b41a828b	1245	* @brief Check if the SMBus Clock Timeout is enabled or disabled.
<>	156:95d6b41a828b	1246	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1247	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1248	* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
<>	156:95d6b41a828b	1249	* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
<>	156:95d6b41a828b	1250	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1251	* @param ClockTimeout This parameter can be one of the following values:
<>	156:95d6b41a828b	1252	* @arg @ref LL_I2C_SMBUS_TIMEOUTA
<>	156:95d6b41a828b	1253	* @arg @ref LL_I2C_SMBUS_TIMEOUTB
<>	156:95d6b41a828b	1254	* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
<>	156:95d6b41a828b	1255	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1256	*/
<>	156:95d6b41a828b	1257	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
<>	156:95d6b41a828b	1258	{
<>	156:95d6b41a828b	1259	return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN \| I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
<>	156:95d6b41a828b	1260	}
<>	156:95d6b41a828b	1261
<>	156:95d6b41a828b	1262	/**
<>	156:95d6b41a828b	1263	* @}
<>	156:95d6b41a828b	1264	*/
<>	156:95d6b41a828b	1265
<>	156:95d6b41a828b	1266	/** @defgroup I2C_LL_EF_IT_Management IT_Management
<>	156:95d6b41a828b	1267	* @{
<>	156:95d6b41a828b	1268	*/
<>	156:95d6b41a828b	1269
<>	156:95d6b41a828b	1270	/**
<>	156:95d6b41a828b	1271	* @brief Enable TXIS interrupt.
<>	156:95d6b41a828b	1272	* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
<>	156:95d6b41a828b	1273	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1274	* @retval None
<>	156:95d6b41a828b	1275	*/
<>	156:95d6b41a828b	1276	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1277	{
<>	156:95d6b41a828b	1278	SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	156:95d6b41a828b	1279	}
<>	156:95d6b41a828b	1280
<>	156:95d6b41a828b	1281	/**
<>	156:95d6b41a828b	1282	* @brief Disable TXIS interrupt.
<>	156:95d6b41a828b	1283	* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
<>	156:95d6b41a828b	1284	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1285	* @retval None
<>	156:95d6b41a828b	1286	*/
<>	156:95d6b41a828b	1287	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1288	{
<>	156:95d6b41a828b	1289	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
<>	156:95d6b41a828b	1290	}
<>	156:95d6b41a828b	1291
<>	156:95d6b41a828b	1292	/**
<>	156:95d6b41a828b	1293	* @brief Check if the TXIS Interrupt is enabled or disabled.
<>	156:95d6b41a828b	1294	* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
<>	156:95d6b41a828b	1295	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1296	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1297	*/
<>	156:95d6b41a828b	1298	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1299	{
<>	156:95d6b41a828b	1300	return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
<>	156:95d6b41a828b	1301	}
<>	156:95d6b41a828b	1302
<>	156:95d6b41a828b	1303	/**
<>	156:95d6b41a828b	1304	* @brief Enable RXNE interrupt.
<>	156:95d6b41a828b	1305	* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
<>	156:95d6b41a828b	1306	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1307	* @retval None
<>	156:95d6b41a828b	1308	*/
<>	156:95d6b41a828b	1309	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1310	{
<>	156:95d6b41a828b	1311	SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	156:95d6b41a828b	1312	}
<>	156:95d6b41a828b	1313
<>	156:95d6b41a828b	1314	/**
<>	156:95d6b41a828b	1315	* @brief Disable RXNE interrupt.
<>	156:95d6b41a828b	1316	* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
<>	156:95d6b41a828b	1317	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1318	* @retval None
<>	156:95d6b41a828b	1319	*/
<>	156:95d6b41a828b	1320	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1321	{
<>	156:95d6b41a828b	1322	CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
<>	156:95d6b41a828b	1323	}
<>	156:95d6b41a828b	1324
<>	156:95d6b41a828b	1325	/**
<>	156:95d6b41a828b	1326	* @brief Check if the RXNE Interrupt is enabled or disabled.
<>	156:95d6b41a828b	1327	* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
<>	156:95d6b41a828b	1328	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1329	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1330	*/
<>	156:95d6b41a828b	1331	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1332	{
<>	156:95d6b41a828b	1333	return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
<>	156:95d6b41a828b	1334	}
<>	156:95d6b41a828b	1335
<>	156:95d6b41a828b	1336	/**
<>	156:95d6b41a828b	1337	* @brief Enable Address match interrupt (slave mode only).
<>	156:95d6b41a828b	1338	* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
<>	156:95d6b41a828b	1339	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1340	* @retval None
<>	156:95d6b41a828b	1341	*/
<>	156:95d6b41a828b	1342	__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1343	{
<>	156:95d6b41a828b	1344	SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	156:95d6b41a828b	1345	}
<>	156:95d6b41a828b	1346
<>	156:95d6b41a828b	1347	/**
<>	156:95d6b41a828b	1348	* @brief Disable Address match interrupt (slave mode only).
<>	156:95d6b41a828b	1349	* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
<>	156:95d6b41a828b	1350	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1351	* @retval None
<>	156:95d6b41a828b	1352	*/
<>	156:95d6b41a828b	1353	__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1354	{
<>	156:95d6b41a828b	1355	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
<>	156:95d6b41a828b	1356	}
<>	156:95d6b41a828b	1357
<>	156:95d6b41a828b	1358	/**
<>	156:95d6b41a828b	1359	* @brief Check if Address match interrupt is enabled or disabled.
<>	156:95d6b41a828b	1360	* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
<>	156:95d6b41a828b	1361	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1362	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1363	*/
<>	156:95d6b41a828b	1364	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1365	{
<>	156:95d6b41a828b	1366	return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
<>	156:95d6b41a828b	1367	}
<>	156:95d6b41a828b	1368
<>	156:95d6b41a828b	1369	/**
<>	156:95d6b41a828b	1370	* @brief Enable Not acknowledge received interrupt.
<>	156:95d6b41a828b	1371	* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
<>	156:95d6b41a828b	1372	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1373	* @retval None
<>	156:95d6b41a828b	1374	*/
<>	156:95d6b41a828b	1375	__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1376	{
<>	156:95d6b41a828b	1377	SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	156:95d6b41a828b	1378	}
<>	156:95d6b41a828b	1379
<>	156:95d6b41a828b	1380	/**
<>	156:95d6b41a828b	1381	* @brief Disable Not acknowledge received interrupt.
<>	156:95d6b41a828b	1382	* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
<>	156:95d6b41a828b	1383	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1384	* @retval None
<>	156:95d6b41a828b	1385	*/
<>	156:95d6b41a828b	1386	__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1387	{
<>	156:95d6b41a828b	1388	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
<>	156:95d6b41a828b	1389	}
<>	156:95d6b41a828b	1390
<>	156:95d6b41a828b	1391	/**
<>	156:95d6b41a828b	1392	* @brief Check if Not acknowledge received interrupt is enabled or disabled.
<>	156:95d6b41a828b	1393	* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
<>	156:95d6b41a828b	1394	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1395	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1396	*/
<>	156:95d6b41a828b	1397	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1398	{
<>	156:95d6b41a828b	1399	return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
<>	156:95d6b41a828b	1400	}
<>	156:95d6b41a828b	1401
<>	156:95d6b41a828b	1402	/**
<>	156:95d6b41a828b	1403	* @brief Enable STOP detection interrupt.
<>	156:95d6b41a828b	1404	* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
<>	156:95d6b41a828b	1405	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1406	* @retval None
<>	156:95d6b41a828b	1407	*/
<>	156:95d6b41a828b	1408	__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1409	{
<>	156:95d6b41a828b	1410	SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	156:95d6b41a828b	1411	}
<>	156:95d6b41a828b	1412
<>	156:95d6b41a828b	1413	/**
<>	156:95d6b41a828b	1414	* @brief Disable STOP detection interrupt.
<>	156:95d6b41a828b	1415	* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
<>	156:95d6b41a828b	1416	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1417	* @retval None
<>	156:95d6b41a828b	1418	*/
<>	156:95d6b41a828b	1419	__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1420	{
<>	156:95d6b41a828b	1421	CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
<>	156:95d6b41a828b	1422	}
<>	156:95d6b41a828b	1423
<>	156:95d6b41a828b	1424	/**
<>	156:95d6b41a828b	1425	* @brief Check if STOP detection interrupt is enabled or disabled.
<>	156:95d6b41a828b	1426	* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
<>	156:95d6b41a828b	1427	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1428	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1429	*/
<>	156:95d6b41a828b	1430	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1431	{
<>	156:95d6b41a828b	1432	return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
<>	156:95d6b41a828b	1433	}
<>	156:95d6b41a828b	1434
<>	156:95d6b41a828b	1435	/**
<>	156:95d6b41a828b	1436	* @brief Enable Transfer Complete interrupt.
<>	156:95d6b41a828b	1437	* @note Any of these events will generate interrupt :
<>	156:95d6b41a828b	1438	* Transfer Complete (TC)
<>	156:95d6b41a828b	1439	* Transfer Complete Reload (TCR)
<>	156:95d6b41a828b	1440	* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
<>	156:95d6b41a828b	1441	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1442	* @retval None
<>	156:95d6b41a828b	1443	*/
<>	156:95d6b41a828b	1444	__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1445	{
<>	156:95d6b41a828b	1446	SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	156:95d6b41a828b	1447	}
<>	156:95d6b41a828b	1448
<>	156:95d6b41a828b	1449	/**
<>	156:95d6b41a828b	1450	* @brief Disable Transfer Complete interrupt.
<>	156:95d6b41a828b	1451	* @note Any of these events will generate interrupt :
<>	156:95d6b41a828b	1452	* Transfer Complete (TC)
<>	156:95d6b41a828b	1453	* Transfer Complete Reload (TCR)
<>	156:95d6b41a828b	1454	* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
<>	156:95d6b41a828b	1455	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1456	* @retval None
<>	156:95d6b41a828b	1457	*/
<>	156:95d6b41a828b	1458	__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1459	{
<>	156:95d6b41a828b	1460	CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
<>	156:95d6b41a828b	1461	}
<>	156:95d6b41a828b	1462
<>	156:95d6b41a828b	1463	/**
<>	156:95d6b41a828b	1464	* @brief Check if Transfer Complete interrupt is enabled or disabled.
<>	156:95d6b41a828b	1465	* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
<>	156:95d6b41a828b	1466	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1467	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1468	*/
<>	156:95d6b41a828b	1469	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1470	{
<>	156:95d6b41a828b	1471	return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
<>	156:95d6b41a828b	1472	}
<>	156:95d6b41a828b	1473
<>	156:95d6b41a828b	1474	/**
<>	156:95d6b41a828b	1475	* @brief Enable Error interrupts.
<>	156:95d6b41a828b	1476	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1477	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1478	* @note Any of these errors will generate interrupt :
<>	156:95d6b41a828b	1479	* Arbitration Loss (ARLO)
<>	156:95d6b41a828b	1480	* Bus Error detection (BERR)
<>	156:95d6b41a828b	1481	* Overrun/Underrun (OVR)
<>	156:95d6b41a828b	1482	* SMBus Timeout detection (TIMEOUT)
<>	156:95d6b41a828b	1483	* SMBus PEC error detection (PECERR)
<>	156:95d6b41a828b	1484	* SMBus Alert pin event detection (ALERT)
<>	156:95d6b41a828b	1485	* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
<>	156:95d6b41a828b	1486	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1487	* @retval None
<>	156:95d6b41a828b	1488	*/
<>	156:95d6b41a828b	1489	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1490	{
<>	156:95d6b41a828b	1491	SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	156:95d6b41a828b	1492	}
<>	156:95d6b41a828b	1493
<>	156:95d6b41a828b	1494	/**
<>	156:95d6b41a828b	1495	* @brief Disable Error interrupts.
<>	156:95d6b41a828b	1496	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1497	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1498	* @note Any of these errors will generate interrupt :
<>	156:95d6b41a828b	1499	* Arbitration Loss (ARLO)
<>	156:95d6b41a828b	1500	* Bus Error detection (BERR)
<>	156:95d6b41a828b	1501	* Overrun/Underrun (OVR)
<>	156:95d6b41a828b	1502	* SMBus Timeout detection (TIMEOUT)
<>	156:95d6b41a828b	1503	* SMBus PEC error detection (PECERR)
<>	156:95d6b41a828b	1504	* SMBus Alert pin event detection (ALERT)
<>	156:95d6b41a828b	1505	* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
<>	156:95d6b41a828b	1506	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1507	* @retval None
<>	156:95d6b41a828b	1508	*/
<>	156:95d6b41a828b	1509	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1510	{
<>	156:95d6b41a828b	1511	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
<>	156:95d6b41a828b	1512	}
<>	156:95d6b41a828b	1513
<>	156:95d6b41a828b	1514	/**
<>	156:95d6b41a828b	1515	* @brief Check if Error interrupts are enabled or disabled.
<>	156:95d6b41a828b	1516	* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
<>	156:95d6b41a828b	1517	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1518	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1519	*/
<>	156:95d6b41a828b	1520	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1521	{
<>	156:95d6b41a828b	1522	return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
<>	156:95d6b41a828b	1523	}
<>	156:95d6b41a828b	1524
<>	156:95d6b41a828b	1525	/**
<>	156:95d6b41a828b	1526	* @}
<>	156:95d6b41a828b	1527	*/
<>	156:95d6b41a828b	1528
<>	156:95d6b41a828b	1529	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
<>	156:95d6b41a828b	1530	* @{
<>	156:95d6b41a828b	1531	*/
<>	156:95d6b41a828b	1532
<>	156:95d6b41a828b	1533	/**
<>	156:95d6b41a828b	1534	* @brief Indicate the status of Transmit data register empty flag.
<>	156:95d6b41a828b	1535	* @note RESET: When next data is written in Transmit data register.
<>	156:95d6b41a828b	1536	* SET: When Transmit data register is empty.
<>	156:95d6b41a828b	1537	* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
<>	156:95d6b41a828b	1538	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1539	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1540	*/
<>	156:95d6b41a828b	1541	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1542	{
<>	156:95d6b41a828b	1543	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
<>	156:95d6b41a828b	1544	}
<>	156:95d6b41a828b	1545
<>	156:95d6b41a828b	1546	/**
<>	156:95d6b41a828b	1547	* @brief Indicate the status of Transmit interrupt flag.
<>	156:95d6b41a828b	1548	* @note RESET: When next data is written in Transmit data register.
<>	156:95d6b41a828b	1549	* SET: When Transmit data register is empty.
<>	156:95d6b41a828b	1550	* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
<>	156:95d6b41a828b	1551	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1552	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1553	*/
<>	156:95d6b41a828b	1554	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1555	{
<>	156:95d6b41a828b	1556	return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
<>	156:95d6b41a828b	1557	}
<>	156:95d6b41a828b	1558
<>	156:95d6b41a828b	1559	/**
<>	156:95d6b41a828b	1560	* @brief Indicate the status of Receive data register not empty flag.
<>	156:95d6b41a828b	1561	* @note RESET: When Receive data register is read.
<>	156:95d6b41a828b	1562	* SET: When the received data is copied in Receive data register.
<>	156:95d6b41a828b	1563	* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
<>	156:95d6b41a828b	1564	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1565	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1566	*/
<>	156:95d6b41a828b	1567	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1568	{
<>	156:95d6b41a828b	1569	return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
<>	156:95d6b41a828b	1570	}
<>	156:95d6b41a828b	1571
<>	156:95d6b41a828b	1572	/**
<>	156:95d6b41a828b	1573	* @brief Indicate the status of Address matched flag (slave mode).
<>	156:95d6b41a828b	1574	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1575	* SET: When the received slave address matched with one of the enabled slave address.
<>	156:95d6b41a828b	1576	* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
<>	156:95d6b41a828b	1577	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1578	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1579	*/
<>	156:95d6b41a828b	1580	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1581	{
<>	156:95d6b41a828b	1582	return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
<>	156:95d6b41a828b	1583	}
<>	156:95d6b41a828b	1584
<>	156:95d6b41a828b	1585	/**
<>	156:95d6b41a828b	1586	* @brief Indicate the status of Not Acknowledge received flag.
<>	156:95d6b41a828b	1587	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1588	* SET: When a NACK is received after a byte transmission.
<>	156:95d6b41a828b	1589	* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
<>	156:95d6b41a828b	1590	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1591	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1592	*/
<>	156:95d6b41a828b	1593	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1594	{
<>	156:95d6b41a828b	1595	return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
<>	156:95d6b41a828b	1596	}
<>	156:95d6b41a828b	1597
<>	156:95d6b41a828b	1598	/**
<>	156:95d6b41a828b	1599	* @brief Indicate the status of Stop detection flag.
<>	156:95d6b41a828b	1600	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1601	* SET: When a Stop condition is detected.
<>	156:95d6b41a828b	1602	* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
<>	156:95d6b41a828b	1603	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1604	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1605	*/
<>	156:95d6b41a828b	1606	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1607	{
<>	156:95d6b41a828b	1608	return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
<>	156:95d6b41a828b	1609	}
<>	156:95d6b41a828b	1610
<>	156:95d6b41a828b	1611	/**
<>	156:95d6b41a828b	1612	* @brief Indicate the status of Transfer complete flag (master mode).
<>	156:95d6b41a828b	1613	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1614	* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
<>	156:95d6b41a828b	1615	* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
<>	156:95d6b41a828b	1616	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1617	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1618	*/
<>	156:95d6b41a828b	1619	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1620	{
<>	156:95d6b41a828b	1621	return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
<>	156:95d6b41a828b	1622	}
<>	156:95d6b41a828b	1623
<>	156:95d6b41a828b	1624	/**
<>	156:95d6b41a828b	1625	* @brief Indicate the status of Transfer complete flag (master mode).
<>	156:95d6b41a828b	1626	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1627	* SET: When RELOAD=1 and NBYTES date have been transferred.
<>	156:95d6b41a828b	1628	* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
<>	156:95d6b41a828b	1629	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1630	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1631	*/
<>	156:95d6b41a828b	1632	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1633	{
<>	156:95d6b41a828b	1634	return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
<>	156:95d6b41a828b	1635	}
<>	156:95d6b41a828b	1636
<>	156:95d6b41a828b	1637	/**
<>	156:95d6b41a828b	1638	* @brief Indicate the status of Bus error flag.
<>	156:95d6b41a828b	1639	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1640	* SET: When a misplaced Start or Stop condition is detected.
<>	156:95d6b41a828b	1641	* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
<>	156:95d6b41a828b	1642	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1643	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1644	*/
<>	156:95d6b41a828b	1645	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1646	{
<>	156:95d6b41a828b	1647	return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
<>	156:95d6b41a828b	1648	}
<>	156:95d6b41a828b	1649
<>	156:95d6b41a828b	1650	/**
<>	156:95d6b41a828b	1651	* @brief Indicate the status of Arbitration lost flag.
<>	156:95d6b41a828b	1652	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1653	* SET: When arbitration lost.
<>	156:95d6b41a828b	1654	* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
<>	156:95d6b41a828b	1655	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1656	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1657	*/
<>	156:95d6b41a828b	1658	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1659	{
<>	156:95d6b41a828b	1660	return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
<>	156:95d6b41a828b	1661	}
<>	156:95d6b41a828b	1662
<>	156:95d6b41a828b	1663	/**
<>	156:95d6b41a828b	1664	* @brief Indicate the status of Overrun/Underrun flag (slave mode).
<>	156:95d6b41a828b	1665	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1666	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
<>	156:95d6b41a828b	1667	* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
<>	156:95d6b41a828b	1668	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1669	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1670	*/
<>	156:95d6b41a828b	1671	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1672	{
<>	156:95d6b41a828b	1673	return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
<>	156:95d6b41a828b	1674	}
<>	156:95d6b41a828b	1675
<>	156:95d6b41a828b	1676	/**
<>	156:95d6b41a828b	1677	* @brief Indicate the status of SMBus PEC error flag in reception.
<>	156:95d6b41a828b	1678	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1679	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1680	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1681	* SET: When the received PEC does not match with the PEC register content.
<>	156:95d6b41a828b	1682	* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
<>	156:95d6b41a828b	1683	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1684	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1685	*/
<>	156:95d6b41a828b	1686	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1687	{
<>	156:95d6b41a828b	1688	return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
<>	156:95d6b41a828b	1689	}
<>	156:95d6b41a828b	1690
<>	156:95d6b41a828b	1691	/**
<>	156:95d6b41a828b	1692	* @brief Indicate the status of SMBus Timeout detection flag.
<>	156:95d6b41a828b	1693	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1694	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1695	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1696	* SET: When a timeout or extended clock timeout occurs.
<>	156:95d6b41a828b	1697	* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
<>	156:95d6b41a828b	1698	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1699	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1700	*/
<>	156:95d6b41a828b	1701	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1702	{
<>	156:95d6b41a828b	1703	return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
<>	156:95d6b41a828b	1704	}
<>	156:95d6b41a828b	1705
<>	156:95d6b41a828b	1706	/**
<>	156:95d6b41a828b	1707	* @brief Indicate the status of SMBus alert flag.
<>	156:95d6b41a828b	1708	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1709	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1710	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1711	* SET: When SMBus host configuration, SMBus alert enabled and
<>	156:95d6b41a828b	1712	* a falling edge event occurs on SMBA pin.
<>	156:95d6b41a828b	1713	* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
<>	156:95d6b41a828b	1714	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1715	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1716	*/
<>	156:95d6b41a828b	1717	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1718	{
<>	156:95d6b41a828b	1719	return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
<>	156:95d6b41a828b	1720	}
<>	156:95d6b41a828b	1721
<>	156:95d6b41a828b	1722	/**
<>	156:95d6b41a828b	1723	* @brief Indicate the status of Bus Busy flag.
<>	156:95d6b41a828b	1724	* @note RESET: Clear default value.
<>	156:95d6b41a828b	1725	* SET: When a Start condition is detected.
<>	156:95d6b41a828b	1726	* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
<>	156:95d6b41a828b	1727	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1728	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1729	*/
<>	156:95d6b41a828b	1730	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1731	{
<>	156:95d6b41a828b	1732	return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
<>	156:95d6b41a828b	1733	}
<>	156:95d6b41a828b	1734
<>	156:95d6b41a828b	1735	/**
<>	156:95d6b41a828b	1736	* @brief Clear Address Matched flag.
<>	156:95d6b41a828b	1737	* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
<>	156:95d6b41a828b	1738	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1739	* @retval None
<>	156:95d6b41a828b	1740	*/
<>	156:95d6b41a828b	1741	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1742	{
<>	156:95d6b41a828b	1743	SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
<>	156:95d6b41a828b	1744	}
<>	156:95d6b41a828b	1745
<>	156:95d6b41a828b	1746	/**
<>	156:95d6b41a828b	1747	* @brief Clear Not Acknowledge flag.
<>	156:95d6b41a828b	1748	* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
<>	156:95d6b41a828b	1749	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1750	* @retval None
<>	156:95d6b41a828b	1751	*/
<>	156:95d6b41a828b	1752	__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1753	{
<>	156:95d6b41a828b	1754	SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
<>	156:95d6b41a828b	1755	}
<>	156:95d6b41a828b	1756
<>	156:95d6b41a828b	1757	/**
<>	156:95d6b41a828b	1758	* @brief Clear Stop detection flag.
<>	156:95d6b41a828b	1759	* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
<>	156:95d6b41a828b	1760	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1761	* @retval None
<>	156:95d6b41a828b	1762	*/
<>	156:95d6b41a828b	1763	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1764	{
<>	156:95d6b41a828b	1765	SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
<>	156:95d6b41a828b	1766	}
<>	156:95d6b41a828b	1767
<>	156:95d6b41a828b	1768	/**
<>	156:95d6b41a828b	1769	* @brief Clear Transmit data register empty flag (TXE).
<>	156:95d6b41a828b	1770	* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
<>	156:95d6b41a828b	1771	* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
<>	156:95d6b41a828b	1772	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1773	* @retval None
<>	156:95d6b41a828b	1774	*/
<>	156:95d6b41a828b	1775	__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1776	{
<>	156:95d6b41a828b	1777	WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
<>	156:95d6b41a828b	1778	}
<>	156:95d6b41a828b	1779
<>	156:95d6b41a828b	1780	/**
<>	156:95d6b41a828b	1781	* @brief Clear Bus error flag.
<>	156:95d6b41a828b	1782	* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
<>	156:95d6b41a828b	1783	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1784	* @retval None
<>	156:95d6b41a828b	1785	*/
<>	156:95d6b41a828b	1786	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1787	{
<>	156:95d6b41a828b	1788	SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
<>	156:95d6b41a828b	1789	}
<>	156:95d6b41a828b	1790
<>	156:95d6b41a828b	1791	/**
<>	156:95d6b41a828b	1792	* @brief Clear Arbitration lost flag.
<>	156:95d6b41a828b	1793	* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
<>	156:95d6b41a828b	1794	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1795	* @retval None
<>	156:95d6b41a828b	1796	*/
<>	156:95d6b41a828b	1797	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1798	{
<>	156:95d6b41a828b	1799	SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
<>	156:95d6b41a828b	1800	}
<>	156:95d6b41a828b	1801
<>	156:95d6b41a828b	1802	/**
<>	156:95d6b41a828b	1803	* @brief Clear Overrun/Underrun flag.
<>	156:95d6b41a828b	1804	* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
<>	156:95d6b41a828b	1805	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1806	* @retval None
<>	156:95d6b41a828b	1807	*/
<>	156:95d6b41a828b	1808	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1809	{
<>	156:95d6b41a828b	1810	SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
<>	156:95d6b41a828b	1811	}
<>	156:95d6b41a828b	1812
<>	156:95d6b41a828b	1813	/**
<>	156:95d6b41a828b	1814	* @brief Clear SMBus PEC error flag.
<>	156:95d6b41a828b	1815	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1816	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1817	* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
<>	156:95d6b41a828b	1818	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1819	* @retval None
<>	156:95d6b41a828b	1820	*/
<>	156:95d6b41a828b	1821	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1822	{
<>	156:95d6b41a828b	1823	SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
<>	156:95d6b41a828b	1824	}
<>	156:95d6b41a828b	1825
<>	156:95d6b41a828b	1826	/**
<>	156:95d6b41a828b	1827	* @brief Clear SMBus Timeout detection flag.
<>	156:95d6b41a828b	1828	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1829	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1830	* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
<>	156:95d6b41a828b	1831	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1832	* @retval None
<>	156:95d6b41a828b	1833	*/
<>	156:95d6b41a828b	1834	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1835	{
<>	156:95d6b41a828b	1836	SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
<>	156:95d6b41a828b	1837	}
<>	156:95d6b41a828b	1838
<>	156:95d6b41a828b	1839	/**
<>	156:95d6b41a828b	1840	* @brief Clear SMBus Alert flag.
<>	156:95d6b41a828b	1841	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	1842	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	1843	* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
<>	156:95d6b41a828b	1844	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1845	* @retval None
<>	156:95d6b41a828b	1846	*/
<>	156:95d6b41a828b	1847	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1848	{
<>	156:95d6b41a828b	1849	SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
<>	156:95d6b41a828b	1850	}
<>	156:95d6b41a828b	1851
<>	156:95d6b41a828b	1852	/**
<>	156:95d6b41a828b	1853	* @}
<>	156:95d6b41a828b	1854	*/
<>	156:95d6b41a828b	1855
<>	156:95d6b41a828b	1856	/** @defgroup I2C_LL_EF_Data_Management Data_Management
<>	156:95d6b41a828b	1857	* @{
<>	156:95d6b41a828b	1858	*/
<>	156:95d6b41a828b	1859
<>	156:95d6b41a828b	1860	/**
<>	156:95d6b41a828b	1861	* @brief Enable automatic STOP condition generation (master mode).
<>	156:95d6b41a828b	1862	* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
<>	156:95d6b41a828b	1863	* This bit has no effect in slave mode or when RELOAD bit is set.
<>	156:95d6b41a828b	1864	* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
<>	156:95d6b41a828b	1865	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1866	* @retval None
<>	156:95d6b41a828b	1867	*/
<>	156:95d6b41a828b	1868	__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1869	{
<>	156:95d6b41a828b	1870	SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	156:95d6b41a828b	1871	}
<>	156:95d6b41a828b	1872
<>	156:95d6b41a828b	1873	/**
<>	156:95d6b41a828b	1874	* @brief Disable automatic STOP condition generation (master mode).
<>	156:95d6b41a828b	1875	* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
<>	156:95d6b41a828b	1876	* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
<>	156:95d6b41a828b	1877	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1878	* @retval None
<>	156:95d6b41a828b	1879	*/
<>	156:95d6b41a828b	1880	__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1881	{
<>	156:95d6b41a828b	1882	CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
<>	156:95d6b41a828b	1883	}
<>	156:95d6b41a828b	1884
<>	156:95d6b41a828b	1885	/**
<>	156:95d6b41a828b	1886	* @brief Check if automatic STOP condition is enabled or disabled.
<>	156:95d6b41a828b	1887	* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
<>	156:95d6b41a828b	1888	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1889	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1890	*/
<>	156:95d6b41a828b	1891	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1892	{
<>	156:95d6b41a828b	1893	return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
<>	156:95d6b41a828b	1894	}
<>	156:95d6b41a828b	1895
<>	156:95d6b41a828b	1896	/**
<>	156:95d6b41a828b	1897	* @brief Enable reload mode (master mode).
<>	156:95d6b41a828b	1898	* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
<>	156:95d6b41a828b	1899	* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
<>	156:95d6b41a828b	1900	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1901	* @retval None
<>	156:95d6b41a828b	1902	*/
<>	156:95d6b41a828b	1903	__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1904	{
<>	156:95d6b41a828b	1905	SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	156:95d6b41a828b	1906	}
<>	156:95d6b41a828b	1907
<>	156:95d6b41a828b	1908	/**
<>	156:95d6b41a828b	1909	* @brief Disable reload mode (master mode).
<>	156:95d6b41a828b	1910	* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
<>	156:95d6b41a828b	1911	* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
<>	156:95d6b41a828b	1912	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1913	* @retval None
<>	156:95d6b41a828b	1914	*/
<>	156:95d6b41a828b	1915	__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1916	{
<>	156:95d6b41a828b	1917	CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
<>	156:95d6b41a828b	1918	}
<>	156:95d6b41a828b	1919
<>	156:95d6b41a828b	1920	/**
<>	156:95d6b41a828b	1921	* @brief Check if reload mode is enabled or disabled.
<>	156:95d6b41a828b	1922	* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
<>	156:95d6b41a828b	1923	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1924	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	1925	*/
<>	156:95d6b41a828b	1926	__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1927	{
<>	156:95d6b41a828b	1928	return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
<>	156:95d6b41a828b	1929	}
<>	156:95d6b41a828b	1930
<>	156:95d6b41a828b	1931	/**
<>	156:95d6b41a828b	1932	* @brief Configure the number of bytes for transfer.
<>	156:95d6b41a828b	1933	* @note Changing these bits when START bit is set is not allowed.
<>	156:95d6b41a828b	1934	* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
<>	156:95d6b41a828b	1935	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1936	* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
<>	156:95d6b41a828b	1937	* @retval None
<>	156:95d6b41a828b	1938	*/
<>	156:95d6b41a828b	1939	__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
<>	156:95d6b41a828b	1940	{
<>	156:95d6b41a828b	1941	MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_POSITION_CR2_NBYTES);
<>	156:95d6b41a828b	1942	}
<>	156:95d6b41a828b	1943
<>	156:95d6b41a828b	1944	/**
<>	156:95d6b41a828b	1945	* @brief Get the number of bytes configured for transfer.
<>	156:95d6b41a828b	1946	* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
<>	156:95d6b41a828b	1947	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1948	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
<>	156:95d6b41a828b	1949	*/
<>	156:95d6b41a828b	1950	__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1951	{
<>	156:95d6b41a828b	1952	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_POSITION_CR2_NBYTES);
<>	156:95d6b41a828b	1953	}
<>	156:95d6b41a828b	1954
<>	156:95d6b41a828b	1955	/**
<>	156:95d6b41a828b	1956	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
<>	156:95d6b41a828b	1957	* @note Usage in Slave mode only.
<>	156:95d6b41a828b	1958	* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
<>	156:95d6b41a828b	1959	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1960	* @param TypeAcknowledge This parameter can be one of the following values:
<>	156:95d6b41a828b	1961	* @arg @ref LL_I2C_ACK
<>	156:95d6b41a828b	1962	* @arg @ref LL_I2C_NACK
<>	156:95d6b41a828b	1963	* @retval None
<>	156:95d6b41a828b	1964	*/
<>	156:95d6b41a828b	1965	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
<>	156:95d6b41a828b	1966	{
<>	156:95d6b41a828b	1967	MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
<>	156:95d6b41a828b	1968	}
<>	156:95d6b41a828b	1969
<>	156:95d6b41a828b	1970	/**
<>	156:95d6b41a828b	1971	* @brief Generate a START or RESTART condition
<>	156:95d6b41a828b	1972	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
<>	156:95d6b41a828b	1973	* This action has no effect when RELOAD is set.
<>	156:95d6b41a828b	1974	* @rmtoll CR2 START LL_I2C_GenerateStartCondition
<>	156:95d6b41a828b	1975	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1976	* @retval None
<>	156:95d6b41a828b	1977	*/
<>	156:95d6b41a828b	1978	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1979	{
<>	156:95d6b41a828b	1980	SET_BIT(I2Cx->CR2, I2C_CR2_START);
<>	156:95d6b41a828b	1981	}
<>	156:95d6b41a828b	1982
<>	156:95d6b41a828b	1983	/**
<>	156:95d6b41a828b	1984	* @brief Generate a STOP condition after the current byte transfer (master mode).
<>	156:95d6b41a828b	1985	* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
<>	156:95d6b41a828b	1986	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	1987	* @retval None
<>	156:95d6b41a828b	1988	*/
<>	156:95d6b41a828b	1989	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	1990	{
<>	156:95d6b41a828b	1991	SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
<>	156:95d6b41a828b	1992	}
<>	156:95d6b41a828b	1993
<>	156:95d6b41a828b	1994	/**
<>	156:95d6b41a828b	1995	* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
<>	156:95d6b41a828b	1996	* @note The master sends the complete 10bit slave address read sequence :
<>	156:95d6b41a828b	1997	* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
<>	156:95d6b41a828b	1998	* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
<>	156:95d6b41a828b	1999	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2000	* @retval None
<>	156:95d6b41a828b	2001	*/
<>	156:95d6b41a828b	2002	__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2003	{
<>	156:95d6b41a828b	2004	CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	156:95d6b41a828b	2005	}
<>	156:95d6b41a828b	2006
<>	156:95d6b41a828b	2007	/**
<>	156:95d6b41a828b	2008	* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
<>	156:95d6b41a828b	2009	* @note The master only sends the first 7 bits of 10bit address in Read direction.
<>	156:95d6b41a828b	2010	* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
<>	156:95d6b41a828b	2011	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2012	* @retval None
<>	156:95d6b41a828b	2013	*/
<>	156:95d6b41a828b	2014	__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2015	{
<>	156:95d6b41a828b	2016	SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
<>	156:95d6b41a828b	2017	}
<>	156:95d6b41a828b	2018
<>	156:95d6b41a828b	2019	/**
<>	156:95d6b41a828b	2020	* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
<>	156:95d6b41a828b	2021	* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
<>	156:95d6b41a828b	2022	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2023	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2024	*/
<>	156:95d6b41a828b	2025	__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2026	{
<>	156:95d6b41a828b	2027	return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
<>	156:95d6b41a828b	2028	}
<>	156:95d6b41a828b	2029
<>	156:95d6b41a828b	2030	/**
<>	156:95d6b41a828b	2031	* @brief Configure the transfer direction (master mode).
<>	156:95d6b41a828b	2032	* @note Changing these bits when START bit is set is not allowed.
<>	156:95d6b41a828b	2033	* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
<>	156:95d6b41a828b	2034	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2035	* @param TransferRequest This parameter can be one of the following values:
<>	156:95d6b41a828b	2036	* @arg @ref LL_I2C_REQUEST_WRITE
<>	156:95d6b41a828b	2037	* @arg @ref LL_I2C_REQUEST_READ
<>	156:95d6b41a828b	2038	* @retval None
<>	156:95d6b41a828b	2039	*/
<>	156:95d6b41a828b	2040	__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
<>	156:95d6b41a828b	2041	{
<>	156:95d6b41a828b	2042	MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
<>	156:95d6b41a828b	2043	}
<>	156:95d6b41a828b	2044
<>	156:95d6b41a828b	2045	/**
<>	156:95d6b41a828b	2046	* @brief Get the transfer direction requested (master mode).
<>	156:95d6b41a828b	2047	* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
<>	156:95d6b41a828b	2048	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2049	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2050	* @arg @ref LL_I2C_REQUEST_WRITE
<>	156:95d6b41a828b	2051	* @arg @ref LL_I2C_REQUEST_READ
<>	156:95d6b41a828b	2052	*/
<>	156:95d6b41a828b	2053	__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2054	{
<>	156:95d6b41a828b	2055	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
<>	156:95d6b41a828b	2056	}
<>	156:95d6b41a828b	2057
<>	156:95d6b41a828b	2058	/**
<>	156:95d6b41a828b	2059	* @brief Configure the slave address for transfer (master mode).
<>	156:95d6b41a828b	2060	* @note Changing these bits when START bit is set is not allowed.
<>	156:95d6b41a828b	2061	* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
<>	156:95d6b41a828b	2062	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2063	* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
<>	156:95d6b41a828b	2064	* @retval None
<>	156:95d6b41a828b	2065	*/
<>	156:95d6b41a828b	2066	__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
<>	156:95d6b41a828b	2067	{
<>	156:95d6b41a828b	2068	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
<>	156:95d6b41a828b	2069	}
<>	156:95d6b41a828b	2070
<>	156:95d6b41a828b	2071	/**
<>	156:95d6b41a828b	2072	* @brief Get the slave address programmed for transfer.
<>	156:95d6b41a828b	2073	* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
<>	156:95d6b41a828b	2074	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2075	* @retval Value between Min_Data=0x0 and Max_Data=0x3F
<>	156:95d6b41a828b	2076	*/
<>	156:95d6b41a828b	2077	__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2078	{
<>	156:95d6b41a828b	2079	return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
<>	156:95d6b41a828b	2080	}
<>	156:95d6b41a828b	2081
<>	156:95d6b41a828b	2082	/**
<>	156:95d6b41a828b	2083	* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
<>	156:95d6b41a828b	2084	* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2085	* CR2 ADD10 LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2086	* CR2 RD_WRN LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2087	* CR2 START LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2088	* CR2 STOP LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2089	* CR2 RELOAD LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2090	* CR2 NBYTES LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2091	* CR2 AUTOEND LL_I2C_HandleTransfer\n
<>	156:95d6b41a828b	2092	* CR2 HEAD10R LL_I2C_HandleTransfer
<>	156:95d6b41a828b	2093	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2094	* @param SlaveAddr Specifies the slave address to be programmed.
<>	156:95d6b41a828b	2095	* @param SlaveAddrSize This parameter can be one of the following values:
<>	156:95d6b41a828b	2096	* @arg @ref LL_I2C_ADDRSLAVE_7BIT
<>	156:95d6b41a828b	2097	* @arg @ref LL_I2C_ADDRSLAVE_10BIT
<>	156:95d6b41a828b	2098	* @param TransferSize Specifies the number of bytes to be programmed.
<>	156:95d6b41a828b	2099	* This parameter must be a value between Min_Data=0 and Max_Data=255.
<>	156:95d6b41a828b	2100	* @param EndMode This parameter can be one of the following values:
<>	156:95d6b41a828b	2101	* @arg @ref LL_I2C_MODE_RELOAD
<>	156:95d6b41a828b	2102	* @arg @ref LL_I2C_MODE_AUTOEND
<>	156:95d6b41a828b	2103	* @arg @ref LL_I2C_MODE_SOFTEND
<>	156:95d6b41a828b	2104	* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
<>	156:95d6b41a828b	2105	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
<>	156:95d6b41a828b	2106	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
<>	156:95d6b41a828b	2107	* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
<>	156:95d6b41a828b	2108	* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
<>	156:95d6b41a828b	2109	* @param Request This parameter can be one of the following values:
<>	156:95d6b41a828b	2110	* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
<>	156:95d6b41a828b	2111	* @arg @ref LL_I2C_GENERATE_STOP
<>	156:95d6b41a828b	2112	* @arg @ref LL_I2C_GENERATE_START_READ
<>	156:95d6b41a828b	2113	* @arg @ref LL_I2C_GENERATE_START_WRITE
<>	156:95d6b41a828b	2114	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
<>	156:95d6b41a828b	2115	* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
<>	156:95d6b41a828b	2116	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
<>	156:95d6b41a828b	2117	* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
<>	156:95d6b41a828b	2118	* @retval None
<>	156:95d6b41a828b	2119	*/
<>	156:95d6b41a828b	2120	__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
<>	156:95d6b41a828b	2121	uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
<>	156:95d6b41a828b	2122	{
<>	156:95d6b41a828b	2123	MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD \| I2C_CR2_ADD10 \| I2C_CR2_RD_WRN \| I2C_CR2_START \| I2C_CR2_STOP \| I2C_CR2_RELOAD \|
<>	156:95d6b41a828b	2124	I2C_CR2_NBYTES \| I2C_CR2_AUTOEND \| I2C_CR2_HEAD10R,
<>	156:95d6b41a828b	2125	SlaveAddr \| SlaveAddrSize \| TransferSize << I2C_POSITION_CR2_NBYTES \| EndMode \| Request);
<>	156:95d6b41a828b	2126	}
<>	156:95d6b41a828b	2127
<>	156:95d6b41a828b	2128	/**
<>	156:95d6b41a828b	2129	* @brief Indicate the value of transfer direction (slave mode).
<>	156:95d6b41a828b	2130	* @note RESET: Write transfer, Slave enters in receiver mode.
<>	156:95d6b41a828b	2131	* SET: Read transfer, Slave enters in transmitter mode.
<>	156:95d6b41a828b	2132	* @rmtoll ISR DIR LL_I2C_GetTransferDirection
<>	156:95d6b41a828b	2133	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2134	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2135	* @arg @ref LL_I2C_DIRECTION_WRITE
<>	156:95d6b41a828b	2136	* @arg @ref LL_I2C_DIRECTION_READ
<>	156:95d6b41a828b	2137	*/
<>	156:95d6b41a828b	2138	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2139	{
<>	156:95d6b41a828b	2140	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
<>	156:95d6b41a828b	2141	}
<>	156:95d6b41a828b	2142
<>	156:95d6b41a828b	2143	/**
<>	156:95d6b41a828b	2144	* @brief Return the slave matched address.
<>	156:95d6b41a828b	2145	* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
<>	156:95d6b41a828b	2146	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2147	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	156:95d6b41a828b	2148	*/
<>	156:95d6b41a828b	2149	__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2150	{
<>	156:95d6b41a828b	2151	return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_POSITION_ISR_ADDCODE << 1);
<>	156:95d6b41a828b	2152	}
<>	156:95d6b41a828b	2153
<>	156:95d6b41a828b	2154	/**
<>	156:95d6b41a828b	2155	* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
<>	156:95d6b41a828b	2156	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	2157	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	2158	* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
<>	156:95d6b41a828b	2159	* This bit has no effect when RELOAD bit is set.
<>	156:95d6b41a828b	2160	* This bit has no effect in device mode when SBC bit is not set.
<>	156:95d6b41a828b	2161	* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
<>	156:95d6b41a828b	2162	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2163	* @retval None
<>	156:95d6b41a828b	2164	*/
<>	156:95d6b41a828b	2165	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2166	{
<>	156:95d6b41a828b	2167	SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
<>	156:95d6b41a828b	2168	}
<>	156:95d6b41a828b	2169
<>	156:95d6b41a828b	2170	/**
<>	156:95d6b41a828b	2171	* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
<>	156:95d6b41a828b	2172	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	2173	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	2174	* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
<>	156:95d6b41a828b	2175	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2176	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	2177	*/
<>	156:95d6b41a828b	2178	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2179	{
<>	156:95d6b41a828b	2180	return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
<>	156:95d6b41a828b	2181	}
<>	156:95d6b41a828b	2182
<>	156:95d6b41a828b	2183	/**
<>	156:95d6b41a828b	2184	* @brief Get the SMBus Packet Error byte calculated.
<>	156:95d6b41a828b	2185	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
<>	156:95d6b41a828b	2186	* SMBus feature is supported by the I2Cx Instance.
<>	156:95d6b41a828b	2187	* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
<>	156:95d6b41a828b	2188	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2189	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	2190	*/
<>	156:95d6b41a828b	2191	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2192	{
<>	156:95d6b41a828b	2193	return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
<>	156:95d6b41a828b	2194	}
<>	156:95d6b41a828b	2195
<>	156:95d6b41a828b	2196	/**
<>	156:95d6b41a828b	2197	* @brief Read Receive Data register.
<>	156:95d6b41a828b	2198	* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
<>	156:95d6b41a828b	2199	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2200	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	2201	*/
<>	156:95d6b41a828b	2202	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
<>	156:95d6b41a828b	2203	{
<>	156:95d6b41a828b	2204	return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
<>	156:95d6b41a828b	2205	}
<>	156:95d6b41a828b	2206
<>	156:95d6b41a828b	2207	/**
<>	156:95d6b41a828b	2208	* @brief Write in Transmit Data Register .
<>	156:95d6b41a828b	2209	* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
<>	156:95d6b41a828b	2210	* @param I2Cx I2C Instance.
<>	156:95d6b41a828b	2211	* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	2212	* @retval None
<>	156:95d6b41a828b	2213	*/
<>	156:95d6b41a828b	2214	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
<>	156:95d6b41a828b	2215	{
<>	156:95d6b41a828b	2216	WRITE_REG(I2Cx->TXDR, Data);
<>	156:95d6b41a828b	2217	}
<>	156:95d6b41a828b	2218
<>	156:95d6b41a828b	2219	/**
<>	156:95d6b41a828b	2220	* @}
<>	156:95d6b41a828b	2221	*/
<>	156:95d6b41a828b	2222
<>	156:95d6b41a828b	2223	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	2224	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
<>	156:95d6b41a828b	2225	* @{
<>	156:95d6b41a828b	2226	*/
<>	156:95d6b41a828b	2227
<>	156:95d6b41a828b	2228	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
<>	156:95d6b41a828b	2229	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
<>	156:95d6b41a828b	2230	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
<>	156:95d6b41a828b	2231
<>	156:95d6b41a828b	2232
<>	156:95d6b41a828b	2233	/**
<>	156:95d6b41a828b	2234	* @}
<>	156:95d6b41a828b	2235	*/
<>	156:95d6b41a828b	2236	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	2237
<>	156:95d6b41a828b	2238	/**
<>	156:95d6b41a828b	2239	* @}
<>	156:95d6b41a828b	2240	*/
<>	156:95d6b41a828b	2241
<>	156:95d6b41a828b	2242	/**
<>	156:95d6b41a828b	2243	* @}
<>	156:95d6b41a828b	2244	*/
<>	156:95d6b41a828b	2245
<>	156:95d6b41a828b	2246	#endif /* I2C1 \|\| I2C2 */
<>	156:95d6b41a828b	2247
<>	156:95d6b41a828b	2248	/**
<>	156:95d6b41a828b	2249	* @}
<>	156:95d6b41a828b	2250	*/
<>	156:95d6b41a828b	2251
<>	156:95d6b41a828b	2252	#ifdef __cplusplus
<>	156:95d6b41a828b	2253	}
<>	156:95d6b41a828b	2254	#endif
<>	156:95d6b41a828b	2255
<>	156:95d6b41a828b	2256	#endif /* __STM32F0xx_LL_I2C_H */
<>	156:95d6b41a828b	2257
<>	156:95d6b41a828b	2258	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/