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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_adc.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:: <>
Date:: Mon Jan 16 15:03:32 2017 +0000
Revision:: 156:95d6b41a828b
Child:: 180:96ed750bd169

This updates the lib to the mbed lib v134

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	156:95d6b41a828b	1	/**
<>	156:95d6b41a828b	2	******************************************************************************
<>	156:95d6b41a828b	3	* @file stm32f0xx_ll_adc.h
<>	156:95d6b41a828b	4	* @author MCD Application Team
<>	156:95d6b41a828b	5	* @version V1.4.0
<>	156:95d6b41a828b	6	* @date 27-May-2016
<>	156:95d6b41a828b	7	* @brief Header file of ADC LL module.
<>	156:95d6b41a828b	8	******************************************************************************
<>	156:95d6b41a828b	9	* @attention
<>	156:95d6b41a828b	10	*
<>	156:95d6b41a828b	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	156:95d6b41a828b	12	*
<>	156:95d6b41a828b	13	* Redistribution and use in source and binary forms, with or without modification,
<>	156:95d6b41a828b	14	* are permitted provided that the following conditions are met:
<>	156:95d6b41a828b	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	156:95d6b41a828b	16	* this list of conditions and the following disclaimer.
<>	156:95d6b41a828b	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	156:95d6b41a828b	18	* this list of conditions and the following disclaimer in the documentation
<>	156:95d6b41a828b	19	* and/or other materials provided with the distribution.
<>	156:95d6b41a828b	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	156:95d6b41a828b	21	* may be used to endorse or promote products derived from this software
<>	156:95d6b41a828b	22	* without specific prior written permission.
<>	156:95d6b41a828b	23	*
<>	156:95d6b41a828b	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	156:95d6b41a828b	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	156:95d6b41a828b	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	156:95d6b41a828b	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	156:95d6b41a828b	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	156:95d6b41a828b	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	156:95d6b41a828b	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	156:95d6b41a828b	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	156:95d6b41a828b	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	156:95d6b41a828b	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	156:95d6b41a828b	34	*
<>	156:95d6b41a828b	35	******************************************************************************
<>	156:95d6b41a828b	36	*/
<>	156:95d6b41a828b	37
<>	156:95d6b41a828b	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	156:95d6b41a828b	39	#ifndef __STM32F0xx_LL_ADC_H
<>	156:95d6b41a828b	40	#define __STM32F0xx_LL_ADC_H
<>	156:95d6b41a828b	41
<>	156:95d6b41a828b	42	#ifdef __cplusplus
<>	156:95d6b41a828b	43	extern "C" {
<>	156:95d6b41a828b	44	#endif
<>	156:95d6b41a828b	45
<>	156:95d6b41a828b	46	/* Includes ------------------------------------------------------------------*/
<>	156:95d6b41a828b	47	#include "stm32f0xx.h"
<>	156:95d6b41a828b	48
<>	156:95d6b41a828b	49	/** @addtogroup STM32F0xx_LL_Driver
<>	156:95d6b41a828b	50	* @{
<>	156:95d6b41a828b	51	*/
<>	156:95d6b41a828b	52
<>	156:95d6b41a828b	53	#if defined (ADC1)
<>	156:95d6b41a828b	54
<>	156:95d6b41a828b	55	/** @defgroup ADC_LL ADC
<>	156:95d6b41a828b	56	* @{
<>	156:95d6b41a828b	57	*/
<>	156:95d6b41a828b	58
<>	156:95d6b41a828b	59	/* Private types -------------------------------------------------------------*/
<>	156:95d6b41a828b	60	/* Private variables ---------------------------------------------------------*/
<>	156:95d6b41a828b	61
<>	156:95d6b41a828b	62	/* Private constants ---------------------------------------------------------*/
<>	156:95d6b41a828b	63	/** @defgroup ADC_LL_Private_Constants ADC Private Constants
<>	156:95d6b41a828b	64	* @{
<>	156:95d6b41a828b	65	*/
<>	156:95d6b41a828b	66
<>	156:95d6b41a828b	67	/* Internal mask for ADC group regular trigger: */
<>	156:95d6b41a828b	68	/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
<>	156:95d6b41a828b	69	/* - regular trigger source */
<>	156:95d6b41a828b	70	/* - regular trigger edge */
<>	156:95d6b41a828b	71	#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
<>	156:95d6b41a828b	72
<>	156:95d6b41a828b	73	/* Mask containing trigger source masks for each of possible */
<>	156:95d6b41a828b	74	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	156:95d6b41a828b	75	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	156:95d6b41a828b	76	#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) \| \
<>	156:95d6b41a828b	77	((ADC_CFGR1_EXTSEL) << (4U * 1U)) \| \
<>	156:95d6b41a828b	78	((ADC_CFGR1_EXTSEL) << (4U * 2U)) \| \
<>	156:95d6b41a828b	79	((ADC_CFGR1_EXTSEL) << (4U * 3U)) )
<>	156:95d6b41a828b	80
<>	156:95d6b41a828b	81	/* Mask containing trigger edge masks for each of possible */
<>	156:95d6b41a828b	82	/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
<>	156:95d6b41a828b	83	/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
<>	156:95d6b41a828b	84	#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) \| \
<>	156:95d6b41a828b	85	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) \| \
<>	156:95d6b41a828b	86	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) \| \
<>	156:95d6b41a828b	87	((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) )
<>	156:95d6b41a828b	88
<>	156:95d6b41a828b	89	/* Definition of ADC group regular trigger bits information. */
<>	156:95d6b41a828b	90	#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */
<>	156:95d6b41a828b	91	#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */
<>	156:95d6b41a828b	92
<>	156:95d6b41a828b	93
<>	156:95d6b41a828b	94
<>	156:95d6b41a828b	95	/* Internal mask for ADC channel: */
<>	156:95d6b41a828b	96	/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
<>	156:95d6b41a828b	97	/* - channel identifier defined by number */
<>	156:95d6b41a828b	98	/* - channel identifier defined by bitfield */
<>	156:95d6b41a828b	99	/* - channel differentiation between external channels (connected to */
<>	156:95d6b41a828b	100	/* GPIO pins) and internal channels (connected to internal paths) */
<>	156:95d6b41a828b	101	#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH)
<>	156:95d6b41a828b	102	#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL)
<>	156:95d6b41a828b	103	#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ((uint32_t)26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
<>	156:95d6b41a828b	104	#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK \| ADC_CHANNEL_ID_BITFIELD_MASK \| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	156:95d6b41a828b	105	/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
<>	156:95d6b41a828b	106	#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 ((uint32_t)0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
<>	156:95d6b41a828b	107
<>	156:95d6b41a828b	108	/* Channel differentiation between external and internal channels */
<>	156:95d6b41a828b	109	#define ADC_CHANNEL_ID_INTERNAL_CH ((uint32_t)0x80000000U) /* Marker of internal channel */
<>	156:95d6b41a828b	110	#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH)
<>	156:95d6b41a828b	111
<>	156:95d6b41a828b	112	/* Definition of channels ID number information to be inserted into */
<>	156:95d6b41a828b	113	/* channels literals definition. */
<>	156:95d6b41a828b	114	#define ADC_CHANNEL_0_NUMBER ((uint32_t)0x00000000U)
<>	156:95d6b41a828b	115	#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	116	#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 )
<>	156:95d6b41a828b	117	#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	118	#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 )
<>	156:95d6b41a828b	119	#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	120	#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
<>	156:95d6b41a828b	121	#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	122	#define ADC_CHANNEL_8_NUMBER ( ADC_CFGR1_AWDCH_3 )
<>	156:95d6b41a828b	123	#define ADC_CHANNEL_9_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	124	#define ADC_CHANNEL_10_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 )
<>	156:95d6b41a828b	125	#define ADC_CHANNEL_11_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	126	#define ADC_CHANNEL_12_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 )
<>	156:95d6b41a828b	127	#define ADC_CHANNEL_13_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	128	#define ADC_CHANNEL_14_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 )
<>	156:95d6b41a828b	129	#define ADC_CHANNEL_15_NUMBER ( ADC_CFGR1_AWDCH_3 \| ADC_CFGR1_AWDCH_2 \| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	130	#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWDCH_4 )
<>	156:95d6b41a828b	131	#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_0)
<>	156:95d6b41a828b	132	#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWDCH_4 \| ADC_CFGR1_AWDCH_1 )
<>	156:95d6b41a828b	133
<>	156:95d6b41a828b	134	/* Definition of channels ID bitfield information to be inserted into */
<>	156:95d6b41a828b	135	/* channels literals definition. */
<>	156:95d6b41a828b	136	#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0)
<>	156:95d6b41a828b	137	#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1)
<>	156:95d6b41a828b	138	#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2)
<>	156:95d6b41a828b	139	#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3)
<>	156:95d6b41a828b	140	#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4)
<>	156:95d6b41a828b	141	#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5)
<>	156:95d6b41a828b	142	#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6)
<>	156:95d6b41a828b	143	#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7)
<>	156:95d6b41a828b	144	#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8)
<>	156:95d6b41a828b	145	#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9)
<>	156:95d6b41a828b	146	#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10)
<>	156:95d6b41a828b	147	#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11)
<>	156:95d6b41a828b	148	#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12)
<>	156:95d6b41a828b	149	#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13)
<>	156:95d6b41a828b	150	#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14)
<>	156:95d6b41a828b	151	#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15)
<>	156:95d6b41a828b	152	#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16)
<>	156:95d6b41a828b	153	#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17)
<>	156:95d6b41a828b	154	#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18)
<>	156:95d6b41a828b	155
<>	156:95d6b41a828b	156	/* Internal mask for ADC analog watchdog: */
<>	156:95d6b41a828b	157	/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
<>	156:95d6b41a828b	158	/* (concatenation of multiple bits used in different analog watchdogs, */
<>	156:95d6b41a828b	159	/* (feature of several watchdogs not available on all STM32 families)). */
<>	156:95d6b41a828b	160	/* - analog watchdog 1: monitored channel defined by number, */
<>	156:95d6b41a828b	161	/* selection of ADC group (ADC group regular). */
<>	156:95d6b41a828b	162
<>	156:95d6b41a828b	163	/* Internal register offset for ADC analog watchdog channel configuration */
<>	156:95d6b41a828b	164	#define ADC_AWD_CR1_REGOFFSET ((uint32_t)0x00000000U)
<>	156:95d6b41a828b	165
<>	156:95d6b41a828b	166	#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
<>	156:95d6b41a828b	167
<>	156:95d6b41a828b	168	#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
<>	156:95d6b41a828b	169	#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
<>	156:95d6b41a828b	170
<>	156:95d6b41a828b	171	/* Internal register offset for ADC analog watchdog threshold configuration */
<>	156:95d6b41a828b	172	#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
<>	156:95d6b41a828b	173	#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET)
<>	156:95d6b41a828b	174
<>	156:95d6b41a828b	175
<>	156:95d6b41a828b	176	/* ADC registers bits positions */
<>	156:95d6b41a828b	177	#define ADC_CFGR1_RES_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RES) */
<>	156:95d6b41a828b	178	#define ADC_CFGR1_AWDSGL_BITOFFSET_POS ((uint32_t)22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */
<>	156:95d6b41a828b	179	#define ADC_TR_HT_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
<>	156:95d6b41a828b	180	#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ((uint32_t) 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */
<>	156:95d6b41a828b	181	#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ((uint32_t) 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */
<>	156:95d6b41a828b	182	#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ((uint32_t) 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */
<>	156:95d6b41a828b	183	#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ((uint32_t) 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */
<>	156:95d6b41a828b	184	#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ((uint32_t) 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */
<>	156:95d6b41a828b	185	#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ((uint32_t) 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */
<>	156:95d6b41a828b	186	#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ((uint32_t) 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */
<>	156:95d6b41a828b	187	#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ((uint32_t) 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */
<>	156:95d6b41a828b	188	#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ((uint32_t) 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */
<>	156:95d6b41a828b	189	#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ((uint32_t) 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */
<>	156:95d6b41a828b	190	#define ADC_CHSELR_CHSEL10_BITOFFSET_POS ((uint32_t)10U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL10) */
<>	156:95d6b41a828b	191	#define ADC_CHSELR_CHSEL11_BITOFFSET_POS ((uint32_t)11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */
<>	156:95d6b41a828b	192	#define ADC_CHSELR_CHSEL12_BITOFFSET_POS ((uint32_t)12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */
<>	156:95d6b41a828b	193	#define ADC_CHSELR_CHSEL13_BITOFFSET_POS ((uint32_t)13U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL13) */
<>	156:95d6b41a828b	194	#define ADC_CHSELR_CHSEL14_BITOFFSET_POS ((uint32_t)14U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL14) */
<>	156:95d6b41a828b	195	#define ADC_CHSELR_CHSEL15_BITOFFSET_POS ((uint32_t)15U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL15) */
<>	156:95d6b41a828b	196	#define ADC_CHSELR_CHSEL16_BITOFFSET_POS ((uint32_t)16U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL16) */
<>	156:95d6b41a828b	197	#define ADC_CHSELR_CHSEL17_BITOFFSET_POS ((uint32_t)17U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL17) */
<>	156:95d6b41a828b	198	#define ADC_CHSELR_CHSEL18_BITOFFSET_POS ((uint32_t)18U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL18) */
<>	156:95d6b41a828b	199
<>	156:95d6b41a828b	200
<>	156:95d6b41a828b	201	/* ADC registers bits groups */
<>	156:95d6b41a828b	202	#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
<>	156:95d6b41a828b	203
<>	156:95d6b41a828b	204
<>	156:95d6b41a828b	205	/* ADC internal channels related definitions */
<>	156:95d6b41a828b	206	/* Internal voltage reference VrefInt */
<>	156:95d6b41a828b	207	#define VREFINT_CAL_ADDR ((uint16_t) ((uint32_t)0x1FFFF7BAU)) / Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	156:95d6b41a828b	208	#define VREFINT_CAL_VREF ((uint32_t) 3300U) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
<>	156:95d6b41a828b	209	/* Temperature sensor */
<>	156:95d6b41a828b	210	#define TEMPSENSOR_CAL1_ADDR ((uint16_t) ((uint32_t)0x1FFFF7B8U)) / Internal temperature sensor, address of parameter TS_CAL1: On STM32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	156:95d6b41a828b	211	#define TEMPSENSOR_CAL2_ADDR ((uint16_t) ((uint32_t)0x1FFFF7C2U)) / Internal temperature sensor, address of parameter TS_CAL2: On STM32F0, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
<>	156:95d6b41a828b	212	#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	156:95d6b41a828b	213	#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
<>	156:95d6b41a828b	214	#define TEMPSENSOR_CAL_VREFANALOG ((uint32_t) 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
<>	156:95d6b41a828b	215
<>	156:95d6b41a828b	216
<>	156:95d6b41a828b	217	/**
<>	156:95d6b41a828b	218	* @}
<>	156:95d6b41a828b	219	*/
<>	156:95d6b41a828b	220
<>	156:95d6b41a828b	221
<>	156:95d6b41a828b	222	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	223	/* Private macros ------------------------------------------------------------*/
<>	156:95d6b41a828b	224	/** @defgroup ADC_LL_Private_Macros ADC Private Macros
<>	156:95d6b41a828b	225	* @{
<>	156:95d6b41a828b	226	*/
<>	156:95d6b41a828b	227
<>	156:95d6b41a828b	228
<>	156:95d6b41a828b	229	/**
<>	156:95d6b41a828b	230	* @}
<>	156:95d6b41a828b	231	*/
<>	156:95d6b41a828b	232
<>	156:95d6b41a828b	233	#endif
<>	156:95d6b41a828b	234
<>	156:95d6b41a828b	235	/* Exported types ------------------------------------------------------------*/
<>	156:95d6b41a828b	236	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	237	/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
<>	156:95d6b41a828b	238	* @{
<>	156:95d6b41a828b	239	*/
<>	156:95d6b41a828b	240
<>	156:95d6b41a828b	241	/**
<>	156:95d6b41a828b	242	* @brief Structure definition of some features of ADC instance.
<>	156:95d6b41a828b	243	* @note These parameters have an impact on ADC scope: ADC instance.
<>	156:95d6b41a828b	244	* Refer to corresponding unitary functions into
<>	156:95d6b41a828b	245	* @ref ADC_LL_EF_Configuration_ADC_Instance .
<>	156:95d6b41a828b	246	* @note The setting of these parameters by function @ref LL_ADC_Init()
<>	156:95d6b41a828b	247	* is conditioned to ADC state:
<>	156:95d6b41a828b	248	* ADC instance must be disabled.
<>	156:95d6b41a828b	249	* This condition is applied to all ADC features, for efficiency
<>	156:95d6b41a828b	250	* and compatibility over all STM32 families. However, the different
<>	156:95d6b41a828b	251	* features can be set under different ADC state conditions
<>	156:95d6b41a828b	252	* (setting possible with ADC enabled without conversion on going,
<>	156:95d6b41a828b	253	* ADC enabled with conversion on going, ...)
<>	156:95d6b41a828b	254	* Each feature can be updated afterwards with a unitary function
<>	156:95d6b41a828b	255	* and potentially with ADC in a different state than disabled,
<>	156:95d6b41a828b	256	* refer to description of each function for setting
<>	156:95d6b41a828b	257	* conditioned to ADC state.
<>	156:95d6b41a828b	258	*/
<>	156:95d6b41a828b	259	typedef struct
<>	156:95d6b41a828b	260	{
<>	156:95d6b41a828b	261	uint32_t Clock; /*!< Set ADC instance clock source and prescaler.
<>	156:95d6b41a828b	262	This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
<>	156:95d6b41a828b	263	@note On this STM32 serie, this parameter has some clock ratio constraints:
<>	156:95d6b41a828b	264	ADC clock synchronous (from PCLK) with prescaler 1 must be enabled only if PCLK has a 50% duty clock cycle
<>	156:95d6b41a828b	265	(APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle).
<>	156:95d6b41a828b	266
<>	156:95d6b41a828b	267
<>	156:95d6b41a828b	268	This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock().
<>	156:95d6b41a828b	269	For more details, refer to description of this function. */
<>	156:95d6b41a828b	270
<>	156:95d6b41a828b	271	uint32_t Resolution; /*!< Set ADC resolution.
<>	156:95d6b41a828b	272	This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
<>	156:95d6b41a828b	273
<>	156:95d6b41a828b	274	This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
<>	156:95d6b41a828b	275
<>	156:95d6b41a828b	276	uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
<>	156:95d6b41a828b	277	This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
<>	156:95d6b41a828b	278
<>	156:95d6b41a828b	279	This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
<>	156:95d6b41a828b	280
<>	156:95d6b41a828b	281	uint32_t LowPowerMode; /*!< Set ADC low power mode.
<>	156:95d6b41a828b	282	This parameter can be a value of @ref ADC_LL_EC_LP_MODE
<>	156:95d6b41a828b	283
<>	156:95d6b41a828b	284	This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
<>	156:95d6b41a828b	285
<>	156:95d6b41a828b	286	} LL_ADC_InitTypeDef;
<>	156:95d6b41a828b	287
<>	156:95d6b41a828b	288	/**
<>	156:95d6b41a828b	289	* @brief Structure definition of some features of ADC group regular.
<>	156:95d6b41a828b	290	* @note These parameters have an impact on ADC scope: ADC group regular.
<>	156:95d6b41a828b	291	* Refer to corresponding unitary functions into
<>	156:95d6b41a828b	292	* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
<>	156:95d6b41a828b	293	* (functions with prefix "REG").
<>	156:95d6b41a828b	294	* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
<>	156:95d6b41a828b	295	* is conditioned to ADC state:
<>	156:95d6b41a828b	296	* ADC instance must be disabled.
<>	156:95d6b41a828b	297	* This condition is applied to all ADC features, for efficiency
<>	156:95d6b41a828b	298	* and compatibility over all STM32 families. However, the different
<>	156:95d6b41a828b	299	* features can be set under different ADC state conditions
<>	156:95d6b41a828b	300	* (setting possible with ADC enabled without conversion on going,
<>	156:95d6b41a828b	301	* ADC enabled with conversion on going, ...)
<>	156:95d6b41a828b	302	* Each feature can be updated afterwards with a unitary function
<>	156:95d6b41a828b	303	* and potentially with ADC in a different state than disabled,
<>	156:95d6b41a828b	304	* refer to description of each function for setting
<>	156:95d6b41a828b	305	* conditioned to ADC state.
<>	156:95d6b41a828b	306	*/
<>	156:95d6b41a828b	307	typedef struct
<>	156:95d6b41a828b	308	{
<>	156:95d6b41a828b	309	uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
<>	156:95d6b41a828b	310	This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
<>	156:95d6b41a828b	311	@note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge
<>	156:95d6b41a828b	312	(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
<>	156:95d6b41a828b	313	In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
<>	156:95d6b41a828b	314
<>	156:95d6b41a828b	315	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
<>	156:95d6b41a828b	316
<>	156:95d6b41a828b	317	uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
<>	156:95d6b41a828b	318	This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
<>	156:95d6b41a828b	319	@note This parameter has an effect only if group regular sequencer is enabled
<>	156:95d6b41a828b	320	(several ADC channels enabled in group regular sequencer).
<>	156:95d6b41a828b	321
<>	156:95d6b41a828b	322	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
<>	156:95d6b41a828b	323
<>	156:95d6b41a828b	324	uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
<>	156:95d6b41a828b	325	This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
<>	156:95d6b41a828b	326	Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
<>	156:95d6b41a828b	327
<>	156:95d6b41a828b	328	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
<>	156:95d6b41a828b	329
<>	156:95d6b41a828b	330	uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
<>	156:95d6b41a828b	331	This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
<>	156:95d6b41a828b	332
<>	156:95d6b41a828b	333	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
<>	156:95d6b41a828b	334
<>	156:95d6b41a828b	335	uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
<>	156:95d6b41a828b	336	data preserved or overwritten.
<>	156:95d6b41a828b	337	This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
<>	156:95d6b41a828b	338
<>	156:95d6b41a828b	339	This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
<>	156:95d6b41a828b	340
<>	156:95d6b41a828b	341	} LL_ADC_REG_InitTypeDef;
<>	156:95d6b41a828b	342
<>	156:95d6b41a828b	343	/**
<>	156:95d6b41a828b	344	* @}
<>	156:95d6b41a828b	345	*/
<>	156:95d6b41a828b	346	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	347
<>	156:95d6b41a828b	348	/* Exported constants --------------------------------------------------------*/
<>	156:95d6b41a828b	349	/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
<>	156:95d6b41a828b	350	* @{
<>	156:95d6b41a828b	351	*/
<>	156:95d6b41a828b	352
<>	156:95d6b41a828b	353	/** @defgroup ADC_LL_EC_FLAG ADC flags
<>	156:95d6b41a828b	354	* @brief Flags defines which can be used with LL_ADC_ReadReg function
<>	156:95d6b41a828b	355	* @{
<>	156:95d6b41a828b	356	*/
<>	156:95d6b41a828b	357	#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /!< ADC flag ADC instance ready /
<>	156:95d6b41a828b	358	#define LL_ADC_FLAG_EOC ADC_ISR_EOC /!< ADC flag ADC group regular end of unitary conversion /
<>	156:95d6b41a828b	359	#define LL_ADC_FLAG_EOS ADC_ISR_EOS /!< ADC flag ADC group regular end of sequence conversions /
<>	156:95d6b41a828b	360	#define LL_ADC_FLAG_OVR ADC_ISR_OVR /!< ADC flag ADC group regular overrun /
<>	156:95d6b41a828b	361	#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC flag ADC group regular end of sampling phase /
<>	156:95d6b41a828b	362	#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD /!< ADC flag ADC analog watchdog 1 /
<>	156:95d6b41a828b	363	/**
<>	156:95d6b41a828b	364	* @}
<>	156:95d6b41a828b	365	*/
<>	156:95d6b41a828b	366
<>	156:95d6b41a828b	367	/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
<>	156:95d6b41a828b	368	* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
<>	156:95d6b41a828b	369	* @{
<>	156:95d6b41a828b	370	*/
<>	156:95d6b41a828b	371	#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /!< ADC interruption ADC instance ready /
<>	156:95d6b41a828b	372	#define LL_ADC_IT_EOC ADC_IER_EOCIE /!< ADC interruption ADC group regular end of unitary conversion /
<>	156:95d6b41a828b	373	#define LL_ADC_IT_EOS ADC_IER_EOSIE /!< ADC interruption ADC group regular end of sequence conversions /
<>	156:95d6b41a828b	374	#define LL_ADC_IT_OVR ADC_IER_OVRIE /!< ADC interruption ADC group regular overrun /
<>	156:95d6b41a828b	375	#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC interruption ADC group regular end of sampling phase /
<>	156:95d6b41a828b	376	#define LL_ADC_IT_AWD1 ADC_IER_AWDIE /!< ADC interruption ADC analog watchdog 1 /
<>	156:95d6b41a828b	377	/**
<>	156:95d6b41a828b	378	* @}
<>	156:95d6b41a828b	379	*/
<>	156:95d6b41a828b	380
<>	156:95d6b41a828b	381	/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
<>	156:95d6b41a828b	382	* @{
<>	156:95d6b41a828b	383	*/
<>	156:95d6b41a828b	384	/* List of ADC registers intended to be used (most commonly) with */
<>	156:95d6b41a828b	385	/* DMA transfer. */
<>	156:95d6b41a828b	386	/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
<>	156:95d6b41a828b	387	#define LL_ADC_DMA_REG_REGULAR_DATA ((uint32_t)0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
<>	156:95d6b41a828b	388	/**
<>	156:95d6b41a828b	389	* @}
<>	156:95d6b41a828b	390	*/
<>	156:95d6b41a828b	391
<>	156:95d6b41a828b	392	/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
<>	156:95d6b41a828b	393	* @{
<>	156:95d6b41a828b	394	*/
<>	156:95d6b41a828b	395	/* Note: Other measurement paths to internal channels may be available */
<>	156:95d6b41a828b	396	/* (connections to other peripherals). */
<>	156:95d6b41a828b	397	/* If they are not listed below, they do not require any specific */
<>	156:95d6b41a828b	398	/* path enable. In this case, Access to measurement path is done */
<>	156:95d6b41a828b	399	/* only by selecting the corresponding ADC internal channel. */
<>	156:95d6b41a828b	400	#define LL_ADC_PATH_INTERNAL_NONE ((uint32_t)0x00000000U)/!< ADC measurement pathes all disabled /
<>	156:95d6b41a828b	401	#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /!< ADC measurement path to internal channel VrefInt /
<>	156:95d6b41a828b	402	#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /!< ADC measurement path to internal channel temperature sensor /
<>	156:95d6b41a828b	403	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	404	#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /!< ADC measurement path to internal channel Vbat /
<>	156:95d6b41a828b	405	#endif
<>	156:95d6b41a828b	406	/**
<>	156:95d6b41a828b	407	* @}
<>	156:95d6b41a828b	408	*/
<>	156:95d6b41a828b	409
<>	156:95d6b41a828b	410	/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source
<>	156:95d6b41a828b	411	* @{
<>	156:95d6b41a828b	412	*/
<>	156:95d6b41a828b	413	#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /!< ADC synchronous clock derived from AHB clock divided by 4 /
<>	156:95d6b41a828b	414	#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /!< ADC synchronous clock derived from AHB clock divided by 2 /
<>	156:95d6b41a828b	415	#define LL_ADC_CLOCK_ASYNC ((uint32_t)0x00000000U) /!< ADC asynchronous clock. On this STM32 serie, asynchronous clock has no prescaler. /
<>	156:95d6b41a828b	416	/**
<>	156:95d6b41a828b	417	* @}
<>	156:95d6b41a828b	418	*/
<>	156:95d6b41a828b	419
<>	156:95d6b41a828b	420	/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
<>	156:95d6b41a828b	421	* @{
<>	156:95d6b41a828b	422	*/
<>	156:95d6b41a828b	423	#define LL_ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC resolution 12 bits /
<>	156:95d6b41a828b	424	#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /!< ADC resolution 10 bits /
<>	156:95d6b41a828b	425	#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /!< ADC resolution 8 bits /
<>	156:95d6b41a828b	426	#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 \| ADC_CFGR1_RES_0) /!< ADC resolution 6 bits /
<>	156:95d6b41a828b	427	/**
<>	156:95d6b41a828b	428	* @}
<>	156:95d6b41a828b	429	*/
<>	156:95d6b41a828b	430
<>	156:95d6b41a828b	431	/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
<>	156:95d6b41a828b	432	* @{
<>	156:95d6b41a828b	433	*/
<>	156:95d6b41a828b	434	#define LL_ADC_DATA_ALIGN_RIGHT ((uint32_t)0x00000000U)/!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)/
<>	156:95d6b41a828b	435	#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)/
<>	156:95d6b41a828b	436	/**
<>	156:95d6b41a828b	437	* @}
<>	156:95d6b41a828b	438	*/
<>	156:95d6b41a828b	439
<>	156:95d6b41a828b	440	/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
<>	156:95d6b41a828b	441	* @{
<>	156:95d6b41a828b	442	*/
<>	156:95d6b41a828b	443	#define LL_ADC_LP_MODE_NONE ((uint32_t)0x00000000U) /!< No ADC low power mode activated /
<>	156:95d6b41a828b	444	#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). /
<>	156:95d6b41a828b	445	#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). Note: On STM32F0, if enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) during auto wait phase. /
<>	156:95d6b41a828b	446	#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF) /!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). /
<>	156:95d6b41a828b	447	/**
<>	156:95d6b41a828b	448	* @}
<>	156:95d6b41a828b	449	*/
<>	156:95d6b41a828b	450
<>	156:95d6b41a828b	451	/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
<>	156:95d6b41a828b	452	* @{
<>	156:95d6b41a828b	453	*/
<>	156:95d6b41a828b	454	#define LL_ADC_GROUP_REGULAR ((uint32_t)0x00000001U) /!< ADC group regular (available on all STM32 devices) /
<>	156:95d6b41a828b	455	/**
<>	156:95d6b41a828b	456	* @}
<>	156:95d6b41a828b	457	*/
<>	156:95d6b41a828b	458
<>	156:95d6b41a828b	459	/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
<>	156:95d6b41a828b	460	* @{
<>	156:95d6b41a828b	461	*/
<>	156:95d6b41a828b	462	#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \| ADC_CHANNEL_0_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 /
<>	156:95d6b41a828b	463	#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \| ADC_CHANNEL_1_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 /
<>	156:95d6b41a828b	464	#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \| ADC_CHANNEL_2_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 /
<>	156:95d6b41a828b	465	#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \| ADC_CHANNEL_3_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 /
<>	156:95d6b41a828b	466	#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \| ADC_CHANNEL_4_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 /
<>	156:95d6b41a828b	467	#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \| ADC_CHANNEL_5_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 /
<>	156:95d6b41a828b	468	#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \| ADC_CHANNEL_6_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 /
<>	156:95d6b41a828b	469	#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \| ADC_CHANNEL_7_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 /
<>	156:95d6b41a828b	470	#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \| ADC_CHANNEL_8_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 /
<>	156:95d6b41a828b	471	#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \| ADC_CHANNEL_9_BITFIELD ) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 /
<>	156:95d6b41a828b	472	#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \| ADC_CHANNEL_10_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 /
<>	156:95d6b41a828b	473	#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \| ADC_CHANNEL_11_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 /
<>	156:95d6b41a828b	474	#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \| ADC_CHANNEL_12_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 /
<>	156:95d6b41a828b	475	#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \| ADC_CHANNEL_13_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 /
<>	156:95d6b41a828b	476	#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \| ADC_CHANNEL_14_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 /
<>	156:95d6b41a828b	477	#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \| ADC_CHANNEL_15_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 /
<>	156:95d6b41a828b	478	#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \| ADC_CHANNEL_16_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 /
<>	156:95d6b41a828b	479	#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \| ADC_CHANNEL_17_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 /
<>	156:95d6b41a828b	480	#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to VrefInt: Internal voltage reference. /
<>	156:95d6b41a828b	481	#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Temperature sensor. /
<>	156:95d6b41a828b	482	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	483	#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \| ADC_CHANNEL_18_BITFIELD) /!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 /
<>	156:95d6b41a828b	484	#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 \| ADC_CHANNEL_ID_INTERNAL_CH) /!< ADC internal channel connected to Vbat/2: Vbat voltage through a divider ladder of factor 1/2 to have Vbat always below Vdda. /
<>	156:95d6b41a828b	485	#endif
<>	156:95d6b41a828b	486	/**
<>	156:95d6b41a828b	487	* @}
<>	156:95d6b41a828b	488	*/
<>	156:95d6b41a828b	489
<>	156:95d6b41a828b	490	/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
<>	156:95d6b41a828b	491	* @{
<>	156:95d6b41a828b	492	*/
<>	156:95d6b41a828b	493	#define LL_ADC_REG_TRIG_SOFTWARE ((uint32_t)0x00000000U) /!< ADC group regular conversion trigger internal: SW start. /
<>	156:95d6b41a828b	494	#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
<>	156:95d6b41a828b	495	#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
<>	156:95d6b41a828b	496	#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
<>	156:95d6b41a828b	497	#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 \| ADC_CFGR1_EXTSEL_0 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
<>	156:95d6b41a828b	498	#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR1_EXTSEL_2 \| ADC_REG_TRIG_EXT_EDGE_DEFAULT) /!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
<>	156:95d6b41a828b	499	/**
<>	156:95d6b41a828b	500	* @}
<>	156:95d6b41a828b	501	*/
<>	156:95d6b41a828b	502
<>	156:95d6b41a828b	503	/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
<>	156:95d6b41a828b	504	* @{
<>	156:95d6b41a828b	505	*/
<>	156:95d6b41a828b	506	#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to rising edge /
<>	156:95d6b41a828b	507	#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /!< ADC group regular conversion trigger polarity set to falling edge /
<>	156:95d6b41a828b	508	#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 \| ADC_CFGR1_EXTEN_0) /!< ADC group regular conversion trigger polarity set to both rising and falling edges /
<>	156:95d6b41a828b	509	/**
<>	156:95d6b41a828b	510	* @}
<>	156:95d6b41a828b	511	*/
<>	156:95d6b41a828b	512
<>	156:95d6b41a828b	513	/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
<>	156:95d6b41a828b	514	* @{
<>	156:95d6b41a828b	515	*/
<>	156:95d6b41a828b	516	#define LL_ADC_REG_CONV_SINGLE ((uint32_t)0x00000000U) /!< ADC conversions are performed in single mode: one conversion per trigger /
<>	156:95d6b41a828b	517	#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically /
<>	156:95d6b41a828b	518	/**
<>	156:95d6b41a828b	519	* @}
<>	156:95d6b41a828b	520	*/
<>	156:95d6b41a828b	521
<>	156:95d6b41a828b	522	/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
<>	156:95d6b41a828b	523	* @{
<>	156:95d6b41a828b	524	*/
<>	156:95d6b41a828b	525	#define LL_ADC_REG_DMA_TRANSFER_NONE ((uint32_t)0x00000000U) /!< ADC conversions are not transferred by DMA /
<>	156:95d6b41a828b	526	#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. /
<>	156:95d6b41a828b	527	#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG \| ADC_CFGR1_DMAEN) /!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. /
<>	156:95d6b41a828b	528	/**
<>	156:95d6b41a828b	529	* @}
<>	156:95d6b41a828b	530	*/
<>	156:95d6b41a828b	531
<>	156:95d6b41a828b	532	/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
<>	156:95d6b41a828b	533	* @{
<>	156:95d6b41a828b	534	*/
<>	156:95d6b41a828b	535	#define LL_ADC_REG_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)/!< ADC group regular behavior in case of overrun: data preserved /
<>	156:95d6b41a828b	536	#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /!< ADC group regular behavior in case of overrun: data overwritten /
<>	156:95d6b41a828b	537	/**
<>	156:95d6b41a828b	538	* @}
<>	156:95d6b41a828b	539	*/
<>	156:95d6b41a828b	540
<>	156:95d6b41a828b	541	/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction
<>	156:95d6b41a828b	542	* @{
<>	156:95d6b41a828b	543	*/
<>	156:95d6b41a828b	544	#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD ((uint32_t)0x00000000U)/!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. /
<>	156:95d6b41a828b	545	#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) /
<>	156:95d6b41a828b	546	/**
<>	156:95d6b41a828b	547	* @}
<>	156:95d6b41a828b	548	*/
<>	156:95d6b41a828b	549
<>	156:95d6b41a828b	550	/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
<>	156:95d6b41a828b	551	* @{
<>	156:95d6b41a828b	552	*/
<>	156:95d6b41a828b	553	#define LL_ADC_REG_SEQ_DISCONT_DISABLE ((uint32_t)0x00000000U) /!< ADC group regular sequencer discontinuous mode disable /
<>	156:95d6b41a828b	554	#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank /
<>	156:95d6b41a828b	555	/**
<>	156:95d6b41a828b	556	* @}
<>	156:95d6b41a828b	557	*/
<>	156:95d6b41a828b	558
<>	156:95d6b41a828b	559	/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
<>	156:95d6b41a828b	560	* @{
<>	156:95d6b41a828b	561	*/
<>	156:95d6b41a828b	562	#define LL_ADC_SAMPLINGTIME_1CYCLE_5 ((uint32_t)0x00000000U) /!< Sampling time 1.5 ADC clock cycle /
<>	156:95d6b41a828b	563	#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP_0) /!< Sampling time 7.5 ADC clock cycles /
<>	156:95d6b41a828b	564	#define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR_SMP_1) /!< Sampling time 13.5 ADC clock cycles /
<>	156:95d6b41a828b	565	#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 28.5 ADC clock cycles /
<>	156:95d6b41a828b	566	#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2) /!< Sampling time 41.5 ADC clock cycles /
<>	156:95d6b41a828b	567	#define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_0) /!< Sampling time 55.5 ADC clock cycles /
<>	156:95d6b41a828b	568	#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1) /!< Sampling time 71.5 ADC clock cycles /
<>	156:95d6b41a828b	569	#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 \| ADC_SMPR_SMP_1 \| ADC_SMPR_SMP_0) /!< Sampling time 239.5 ADC clock cycles /
<>	156:95d6b41a828b	570	/**
<>	156:95d6b41a828b	571	* @}
<>	156:95d6b41a828b	572	*/
<>	156:95d6b41a828b	573
<>	156:95d6b41a828b	574	/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
<>	156:95d6b41a828b	575	* @{
<>	156:95d6b41a828b	576	*/
<>	156:95d6b41a828b	577	#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \| ADC_AWD_CR1_REGOFFSET) /!< ADC analog watchdog number 1 /
<>	156:95d6b41a828b	578	/**
<>	156:95d6b41a828b	579	* @}
<>	156:95d6b41a828b	580	*/
<>	156:95d6b41a828b	581
<>	156:95d6b41a828b	582	/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
<>	156:95d6b41a828b	583	* @{
<>	156:95d6b41a828b	584	*/
<>	156:95d6b41a828b	585	#define LL_ADC_AWD_DISABLE ((uint32_t)0x00000000U) /!< ADC analog watchdog monitoring disabled /
<>	156:95d6b41a828b	586	#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /!< ADC analog watchdog monitoring of all channels, converted by group regular only /
<>	156:95d6b41a828b	587	#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only /
<>	156:95d6b41a828b	588	#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only /
<>	156:95d6b41a828b	589	#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only /
<>	156:95d6b41a828b	590	#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only /
<>	156:95d6b41a828b	591	#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only /
<>	156:95d6b41a828b	592	#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only /
<>	156:95d6b41a828b	593	#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only /
<>	156:95d6b41a828b	594	#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only /
<>	156:95d6b41a828b	595	#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only /
<>	156:95d6b41a828b	596	#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only /
<>	156:95d6b41a828b	597	#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only /
<>	156:95d6b41a828b	598	#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only /
<>	156:95d6b41a828b	599	#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only /
<>	156:95d6b41a828b	600	#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only /
<>	156:95d6b41a828b	601	#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only /
<>	156:95d6b41a828b	602	#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only /
<>	156:95d6b41a828b	603	#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only /
<>	156:95d6b41a828b	604	#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only /
<>	156:95d6b41a828b	605	#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only /
<>	156:95d6b41a828b	606	#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only /
<>	156:95d6b41a828b	607	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	608	#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only /
<>	156:95d6b41a828b	609	#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL) /!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only /
<>	156:95d6b41a828b	610	#endif
<>	156:95d6b41a828b	611	/**
<>	156:95d6b41a828b	612	* @}
<>	156:95d6b41a828b	613	*/
<>	156:95d6b41a828b	614
<>	156:95d6b41a828b	615	/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
<>	156:95d6b41a828b	616	* @{
<>	156:95d6b41a828b	617	*/
<>	156:95d6b41a828b	618	#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /!< ADC analog watchdog threshold high /
<>	156:95d6b41a828b	619	#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /!< ADC analog watchdog threshold low /
<>	156:95d6b41a828b	620	#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT \| ADC_TR_LT) /!< ADC analog watchdog both thresholds high and low concatenated into the same data /
<>	156:95d6b41a828b	621	/**
<>	156:95d6b41a828b	622	* @}
<>	156:95d6b41a828b	623	*/
<>	156:95d6b41a828b	624
<>	156:95d6b41a828b	625
<>	156:95d6b41a828b	626	/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
<>	156:95d6b41a828b	627	* @note Only ADC IP HW delays are defined in ADC LL driver driver,
<>	156:95d6b41a828b	628	* not timeout values.
<>	156:95d6b41a828b	629	* For details on delays values, refer to descriptions in source code
<>	156:95d6b41a828b	630	* above each literal definition.
<>	156:95d6b41a828b	631	* @{
<>	156:95d6b41a828b	632	*/
<>	156:95d6b41a828b	633
<>	156:95d6b41a828b	634	/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
<>	156:95d6b41a828b	635	/* not timeout values. */
<>	156:95d6b41a828b	636	/* Timeout values for ADC operations are dependent to device clock */
<>	156:95d6b41a828b	637	/* configuration (system clock versus ADC clock), */
<>	156:95d6b41a828b	638	/* and therefore must be defined in user application. */
<>	156:95d6b41a828b	639	/* Indications for estimation of ADC timeout delays, for this */
<>	156:95d6b41a828b	640	/* STM32 serie: */
<>	156:95d6b41a828b	641	/* - ADC calibration time: maximum delay is 83/fADC. */
<>	156:95d6b41a828b	642	/* (refer to device datasheet, parameter "tCAL") */
<>	156:95d6b41a828b	643	/* - ADC enable time: maximum delay is 1 conversion cycle. */
<>	156:95d6b41a828b	644	/* (refer to device datasheet, parameter "tSTAB") */
<>	156:95d6b41a828b	645	/* - ADC disable time: maximum delay should be a few ADC clock cycles */
<>	156:95d6b41a828b	646	/* - ADC stop conversion time: maximum delay should be a few ADC clock */
<>	156:95d6b41a828b	647	/* cycles */
<>	156:95d6b41a828b	648	/* - ADC conversion time: duration depending on ADC clock and ADC */
<>	156:95d6b41a828b	649	/* configuration. */
<>	156:95d6b41a828b	650	/* (refer to device reference manual, section "Timing") */
<>	156:95d6b41a828b	651
<>	156:95d6b41a828b	652
<>	156:95d6b41a828b	653	/* Delay for internal voltage reference stabilization time. */
<>	156:95d6b41a828b	654	/* Delay set to maximum value (refer to device datasheet, */
<>	156:95d6b41a828b	655	/* parameter "tSTART"). */
<>	156:95d6b41a828b	656	/* Unit: us */
<>	156:95d6b41a828b	657	#define LL_ADC_DELAY_VREFINT_STAB_US ((uint32_t) 10U) /!< Delay for internal voltage reference stabilization time /
<>	156:95d6b41a828b	658
<>	156:95d6b41a828b	659	/* Delay for temperature sensor stabilization time. */
<>	156:95d6b41a828b	660	/* Literal set to maximum value (refer to device datasheet, */
<>	156:95d6b41a828b	661	/* parameter "tSTART"). */
<>	156:95d6b41a828b	662	/* Unit: us */
<>	156:95d6b41a828b	663	#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ((uint32_t) 10U) /!< Delay for temperature sensor stabilization time /
<>	156:95d6b41a828b	664
<>	156:95d6b41a828b	665	/* Delay required between ADC end of calibration and ADC enable. */
<>	156:95d6b41a828b	666	/* Note: On this STM32 serie, a minimum number of ADC clock cycles */
<>	156:95d6b41a828b	667	/* are required between ADC end of calibration and ADC enable. */
<>	156:95d6b41a828b	668	/* Wait time can be computed in user application by waiting for the */
<>	156:95d6b41a828b	669	/* equivalent number of CPU cycles, by taking into account */
<>	156:95d6b41a828b	670	/* ratio of CPU clock versus ADC clock prescalers. */
<>	156:95d6b41a828b	671	/* Unit: ADC clock cycles. */
<>	156:95d6b41a828b	672	#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ((uint32_t) 2U) /!< Delay required between ADC end of calibration and ADC enable /
<>	156:95d6b41a828b	673
<>	156:95d6b41a828b	674	/**
<>	156:95d6b41a828b	675	* @}
<>	156:95d6b41a828b	676	*/
<>	156:95d6b41a828b	677
<>	156:95d6b41a828b	678	/**
<>	156:95d6b41a828b	679	* @}
<>	156:95d6b41a828b	680	*/
<>	156:95d6b41a828b	681
<>	156:95d6b41a828b	682
<>	156:95d6b41a828b	683	/* Exported macro ------------------------------------------------------------*/
<>	156:95d6b41a828b	684	/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
<>	156:95d6b41a828b	685	* @{
<>	156:95d6b41a828b	686	*/
<>	156:95d6b41a828b	687
<>	156:95d6b41a828b	688	/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
<>	156:95d6b41a828b	689	* @{
<>	156:95d6b41a828b	690	*/
<>	156:95d6b41a828b	691
<>	156:95d6b41a828b	692	/**
<>	156:95d6b41a828b	693	* @brief Write a value in ADC register
<>	156:95d6b41a828b	694	* @param __INSTANCE__ ADC Instance
<>	156:95d6b41a828b	695	* @param __REG__ Register to be written
<>	156:95d6b41a828b	696	* @param __VALUE__ Value to be written in the register
<>	156:95d6b41a828b	697	* @retval None
<>	156:95d6b41a828b	698	*/
<>	156:95d6b41a828b	699	#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<>	156:95d6b41a828b	700
<>	156:95d6b41a828b	701	/**
<>	156:95d6b41a828b	702	* @brief Read a value in ADC register
<>	156:95d6b41a828b	703	* @param __INSTANCE__ ADC Instance
<>	156:95d6b41a828b	704	* @param __REG__ Register to be read
<>	156:95d6b41a828b	705	* @retval Register value
<>	156:95d6b41a828b	706	*/
<>	156:95d6b41a828b	707	#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<>	156:95d6b41a828b	708	/**
<>	156:95d6b41a828b	709	* @}
<>	156:95d6b41a828b	710	*/
<>	156:95d6b41a828b	711
<>	156:95d6b41a828b	712	/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
<>	156:95d6b41a828b	713	* @{
<>	156:95d6b41a828b	714	*/
<>	156:95d6b41a828b	715
<>	156:95d6b41a828b	716	/**
<>	156:95d6b41a828b	717	* @brief Helper macro to get ADC channel number in decimal format
<>	156:95d6b41a828b	718	* from literals LL_ADC_CHANNEL_x.
<>	156:95d6b41a828b	719	* @note Example:
<>	156:95d6b41a828b	720	* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
<>	156:95d6b41a828b	721	* will return decimal number "4".
<>	156:95d6b41a828b	722	* @note The input can be a value from functions where a channel
<>	156:95d6b41a828b	723	* number is returned, either defined with number
<>	156:95d6b41a828b	724	* or with bitfield (only one bit must be set).
<>	156:95d6b41a828b	725	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	726	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	727	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	728	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	729	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	730	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	731	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	732	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	733	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	734	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	735	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	736	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	737	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	738	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	739	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	740	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	741	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	742	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	743	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	744	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	745	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	746	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	747	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	748	*
<>	156:95d6b41a828b	749	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	750	* @retval Value between Min_Data=0 and Max_Data=18
<>	156:95d6b41a828b	751	*/
<>	156:95d6b41a828b	752	#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
<>	156:95d6b41a828b	753	((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \
<>	156:95d6b41a828b	754	? ( \
<>	156:95d6b41a828b	755	((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
<>	156:95d6b41a828b	756	) \
<>	156:95d6b41a828b	757	: \
<>	156:95d6b41a828b	758	( \
<>	156:95d6b41a828b	759	(((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \
<>	156:95d6b41a828b	760	( \
<>	156:95d6b41a828b	761	(((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \
<>	156:95d6b41a828b	762	( \
<>	156:95d6b41a828b	763	(((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \
<>	156:95d6b41a828b	764	( \
<>	156:95d6b41a828b	765	(((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \
<>	156:95d6b41a828b	766	( \
<>	156:95d6b41a828b	767	(((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \
<>	156:95d6b41a828b	768	( \
<>	156:95d6b41a828b	769	(((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \
<>	156:95d6b41a828b	770	( \
<>	156:95d6b41a828b	771	(((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \
<>	156:95d6b41a828b	772	( \
<>	156:95d6b41a828b	773	(((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \
<>	156:95d6b41a828b	774	( \
<>	156:95d6b41a828b	775	(((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \
<>	156:95d6b41a828b	776	( \
<>	156:95d6b41a828b	777	(((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \
<>	156:95d6b41a828b	778	( \
<>	156:95d6b41a828b	779	(((__CHANNEL__) & ADC_CHSELR_CHSEL10) == ADC_CHSELR_CHSEL10) ? (10U) : \
<>	156:95d6b41a828b	780	( \
<>	156:95d6b41a828b	781	(((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \
<>	156:95d6b41a828b	782	( \
<>	156:95d6b41a828b	783	(((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \
<>	156:95d6b41a828b	784	( \
<>	156:95d6b41a828b	785	(((__CHANNEL__) & ADC_CHSELR_CHSEL13) == ADC_CHSELR_CHSEL13) ? (13U) : \
<>	156:95d6b41a828b	786	( \
<>	156:95d6b41a828b	787	(((__CHANNEL__) & ADC_CHSELR_CHSEL14) == ADC_CHSELR_CHSEL14) ? (14U) : \
<>	156:95d6b41a828b	788	( \
<>	156:95d6b41a828b	789	(((__CHANNEL__) & ADC_CHSELR_CHSEL15) == ADC_CHSELR_CHSEL15) ? (15U) : \
<>	156:95d6b41a828b	790	( \
<>	156:95d6b41a828b	791	(((__CHANNEL__) & ADC_CHSELR_CHSEL16) == ADC_CHSELR_CHSEL16) ? (16U) : \
<>	156:95d6b41a828b	792	( \
<>	156:95d6b41a828b	793	(((__CHANNEL__) & ADC_CHSELR_CHSEL17) == ADC_CHSELR_CHSEL17) ? (17U) : \
<>	156:95d6b41a828b	794	( \
<>	156:95d6b41a828b	795	(((__CHANNEL__) & ADC_CHSELR_CHSEL18) == ADC_CHSELR_CHSEL18) ? (18U) : \
<>	156:95d6b41a828b	796	(0U) \
<>	156:95d6b41a828b	797	) \
<>	156:95d6b41a828b	798	) \
<>	156:95d6b41a828b	799	) \
<>	156:95d6b41a828b	800	) \
<>	156:95d6b41a828b	801	) \
<>	156:95d6b41a828b	802	) \
<>	156:95d6b41a828b	803	) \
<>	156:95d6b41a828b	804	) \
<>	156:95d6b41a828b	805	) \
<>	156:95d6b41a828b	806	) \
<>	156:95d6b41a828b	807	) \
<>	156:95d6b41a828b	808	) \
<>	156:95d6b41a828b	809	) \
<>	156:95d6b41a828b	810	) \
<>	156:95d6b41a828b	811	) \
<>	156:95d6b41a828b	812	) \
<>	156:95d6b41a828b	813	) \
<>	156:95d6b41a828b	814	) \
<>	156:95d6b41a828b	815	) \
<>	156:95d6b41a828b	816	)
<>	156:95d6b41a828b	817
<>	156:95d6b41a828b	818	/**
<>	156:95d6b41a828b	819	* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
<>	156:95d6b41a828b	820	* from number in decimal format.
<>	156:95d6b41a828b	821	* @note Example:
<>	156:95d6b41a828b	822	* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
<>	156:95d6b41a828b	823	* will return a data equivalent to "LL_ADC_CHANNEL_4".
<>	156:95d6b41a828b	824	* @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
<>	156:95d6b41a828b	825	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	826	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	827	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	828	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	829	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	830	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	831	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	832	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	833	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	834	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	835	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	836	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	837	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	838	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	839	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	840	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	841	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	842	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	843	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	844	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	845	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
<>	156:95d6b41a828b	846	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
<>	156:95d6b41a828b	847	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
<>	156:95d6b41a828b	848	*
<>	156:95d6b41a828b	849	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
<>	156:95d6b41a828b	850	* (2) For ADC channel read back from ADC register,
<>	156:95d6b41a828b	851	* comparison with internal channel parameter to be done
<>	156:95d6b41a828b	852	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	156:95d6b41a828b	853	*/
<>	156:95d6b41a828b	854	#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
<>	156:95d6b41a828b	855	( \
<>	156:95d6b41a828b	856	((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \| \
<>	156:95d6b41a828b	857	(ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \
<>	156:95d6b41a828b	858	)
<>	156:95d6b41a828b	859
<>	156:95d6b41a828b	860	/**
<>	156:95d6b41a828b	861	* @brief Helper macro to determine whether the selected channel
<>	156:95d6b41a828b	862	* corresponds to literal definitions of driver.
<>	156:95d6b41a828b	863	* @note The different literal definitions of ADC channels are:
<>	156:95d6b41a828b	864	* - ADC internal channel:
<>	156:95d6b41a828b	865	* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
<>	156:95d6b41a828b	866	* - ADC external channel (channel connected to a GPIO pin):
<>	156:95d6b41a828b	867	* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
<>	156:95d6b41a828b	868	* @note The channel parameter must be a value defined from literal
<>	156:95d6b41a828b	869	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	156:95d6b41a828b	870	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	156:95d6b41a828b	871	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
<>	156:95d6b41a828b	872	* must not be a value from functions where a channel number is
<>	156:95d6b41a828b	873	* returned from ADC registers,
<>	156:95d6b41a828b	874	* because internal and external channels share the same channel
<>	156:95d6b41a828b	875	* number in ADC registers. The differentiation is made only with
<>	156:95d6b41a828b	876	* parameters definitions of driver.
<>	156:95d6b41a828b	877	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	878	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	879	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	880	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	881	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	882	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	883	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	884	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	885	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	886	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	887	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	888	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	889	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	890	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	891	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	892	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	893	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	894	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	895	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	896	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	897	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	898	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	899	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	900	*
<>	156:95d6b41a828b	901	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	902	* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
<>	156:95d6b41a828b	903	* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
<>	156:95d6b41a828b	904	*/
<>	156:95d6b41a828b	905	#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
<>	156:95d6b41a828b	906	(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
<>	156:95d6b41a828b	907
<>	156:95d6b41a828b	908	/**
<>	156:95d6b41a828b	909	* @brief Helper macro to convert a channel defined from parameter
<>	156:95d6b41a828b	910	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	156:95d6b41a828b	911	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	156:95d6b41a828b	912	* to its equivalent parameter definition of a ADC external channel
<>	156:95d6b41a828b	913	* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
<>	156:95d6b41a828b	914	* @note The channel parameter can be, additionally to a value
<>	156:95d6b41a828b	915	* defined from parameter definition of a ADC internal channel
<>	156:95d6b41a828b	916	* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	156:95d6b41a828b	917	* a value defined from parameter definition of
<>	156:95d6b41a828b	918	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	156:95d6b41a828b	919	* or a value from functions where a channel number is returned
<>	156:95d6b41a828b	920	* from ADC registers.
<>	156:95d6b41a828b	921	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	922	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	923	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	924	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	925	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	926	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	927	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	928	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	929	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	930	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	931	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	932	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	933	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	934	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	935	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	936	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	937	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	938	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	939	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	940	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	941	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	942	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	943	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	944	*
<>	156:95d6b41a828b	945	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	946	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	947	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	948	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	949	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	950	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	951	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	952	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	953	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	954	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	955	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	956	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	957	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	958	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	959	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	960	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	961	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	962	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	963	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	964	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	965	* @arg @ref LL_ADC_CHANNEL_18
<>	156:95d6b41a828b	966	*/
<>	156:95d6b41a828b	967	#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
<>	156:95d6b41a828b	968	((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
<>	156:95d6b41a828b	969
<>	156:95d6b41a828b	970	/**
<>	156:95d6b41a828b	971	* @brief Helper macro to determine whether the internal channel
<>	156:95d6b41a828b	972	* selected is available on the ADC instance selected.
<>	156:95d6b41a828b	973	* @note The channel parameter must be a value defined from parameter
<>	156:95d6b41a828b	974	* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
<>	156:95d6b41a828b	975	* LL_ADC_CHANNEL_TEMPSENSOR, ...),
<>	156:95d6b41a828b	976	* must not be a value defined from parameter definition of
<>	156:95d6b41a828b	977	* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
<>	156:95d6b41a828b	978	* or a value from functions where a channel number is
<>	156:95d6b41a828b	979	* returned from ADC registers,
<>	156:95d6b41a828b	980	* because internal and external channels share the same channel
<>	156:95d6b41a828b	981	* number in ADC registers. The differentiation is made only with
<>	156:95d6b41a828b	982	* parameters definitions of driver.
<>	156:95d6b41a828b	983	* @param __ADC_INSTANCE__ ADC instance
<>	156:95d6b41a828b	984	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	985	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	986	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	987	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	988	*
<>	156:95d6b41a828b	989	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	990	* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
<>	156:95d6b41a828b	991	* Value "1" if the internal channel selected is available on the ADC instance selected.
<>	156:95d6b41a828b	992	*/
<>	156:95d6b41a828b	993	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	994	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	156:95d6b41a828b	995	( \
<>	156:95d6b41a828b	996	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	156:95d6b41a828b	997	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	156:95d6b41a828b	998	((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
<>	156:95d6b41a828b	999	)
<>	156:95d6b41a828b	1000	#else
<>	156:95d6b41a828b	1001	#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
<>	156:95d6b41a828b	1002	( \
<>	156:95d6b41a828b	1003	((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \|\| \
<>	156:95d6b41a828b	1004	((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
<>	156:95d6b41a828b	1005	)
<>	156:95d6b41a828b	1006	#endif
<>	156:95d6b41a828b	1007
<>	156:95d6b41a828b	1008	/**
<>	156:95d6b41a828b	1009	* @brief Helper macro to define ADC analog watchdog parameter:
<>	156:95d6b41a828b	1010	* define a single channel to monitor with analog watchdog
<>	156:95d6b41a828b	1011	* from sequencer channel and groups definition.
<>	156:95d6b41a828b	1012	* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
<>	156:95d6b41a828b	1013	* Example:
<>	156:95d6b41a828b	1014	* LL_ADC_SetAnalogWDMonitChannels(
<>	156:95d6b41a828b	1015	* ADC1, LL_ADC_AWD1,
<>	156:95d6b41a828b	1016	* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
<>	156:95d6b41a828b	1017	* @param __CHANNEL__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1018	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	1019	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	1020	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	1021	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	1022	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	1023	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	1024	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	1025	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	1026	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	1027	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	1028	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	1029	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	1030	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	1031	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	1032	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	1033	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	1034	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	1035	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	1036	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	1037	* @arg @ref LL_ADC_CHANNEL_VREFINT (2)
<>	156:95d6b41a828b	1038	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (2)
<>	156:95d6b41a828b	1039	* @arg @ref LL_ADC_CHANNEL_VBAT (1)(2)
<>	156:95d6b41a828b	1040	*
<>	156:95d6b41a828b	1041	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.\n
<>	156:95d6b41a828b	1042	* (2) For ADC channel read back from ADC register,
<>	156:95d6b41a828b	1043	* comparison with internal channel parameter to be done
<>	156:95d6b41a828b	1044	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
<>	156:95d6b41a828b	1045	* @param __GROUP__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1046	* @arg @ref LL_ADC_GROUP_REGULAR
<>	156:95d6b41a828b	1047	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1048	* @arg @ref LL_ADC_AWD_DISABLE
<>	156:95d6b41a828b	1049	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	156:95d6b41a828b	1050	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	156:95d6b41a828b	1051	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	156:95d6b41a828b	1052	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	156:95d6b41a828b	1053	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	156:95d6b41a828b	1054	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	156:95d6b41a828b	1055	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	156:95d6b41a828b	1056	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	156:95d6b41a828b	1057	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	156:95d6b41a828b	1058	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	156:95d6b41a828b	1059	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	156:95d6b41a828b	1060	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	156:95d6b41a828b	1061	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	156:95d6b41a828b	1062	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	156:95d6b41a828b	1063	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	156:95d6b41a828b	1064	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	156:95d6b41a828b	1065	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	156:95d6b41a828b	1066	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	156:95d6b41a828b	1067	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	156:95d6b41a828b	1068	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
<>	156:95d6b41a828b	1069	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
<>	156:95d6b41a828b	1070	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
<>	156:95d6b41a828b	1071	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	156:95d6b41a828b	1072	*
<>	156:95d6b41a828b	1073	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	1074	*/
<>	156:95d6b41a828b	1075	#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
<>	156:95d6b41a828b	1076	(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) \| ADC_CFGR1_AWDEN \| ADC_CFGR1_AWDSGL)
<>	156:95d6b41a828b	1077
<>	156:95d6b41a828b	1078	/**
<>	156:95d6b41a828b	1079	* @brief Helper macro to set the value of ADC analog watchdog threshold high
<>	156:95d6b41a828b	1080	* or low in function of ADC resolution, when ADC resolution is
<>	156:95d6b41a828b	1081	* different of 12 bits.
<>	156:95d6b41a828b	1082	* @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
<>	156:95d6b41a828b	1083	* or @ref LL_ADC_SetAnalogWDThresholds().
<>	156:95d6b41a828b	1084	* Example, with a ADC resolution of 8 bits, to set the value of
<>	156:95d6b41a828b	1085	* analog watchdog threshold high (on 8 bits):
<>	156:95d6b41a828b	1086	* LL_ADC_SetAnalogWDThresholds
<>	156:95d6b41a828b	1087	* (< ADCx param >,
<>	156:95d6b41a828b	1088	* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
<>	156:95d6b41a828b	1089	* );
<>	156:95d6b41a828b	1090	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1091	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1092	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1093	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1094	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1095	* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1096	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1097	*/
<>	156:95d6b41a828b	1098	#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
<>	156:95d6b41a828b	1099	((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
<>	156:95d6b41a828b	1100
<>	156:95d6b41a828b	1101	/**
<>	156:95d6b41a828b	1102	* @brief Helper macro to get the value of ADC analog watchdog threshold high
<>	156:95d6b41a828b	1103	* or low in function of ADC resolution, when ADC resolution is
<>	156:95d6b41a828b	1104	* different of 12 bits.
<>	156:95d6b41a828b	1105	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	156:95d6b41a828b	1106	* Example, with a ADC resolution of 8 bits, to get the value of
<>	156:95d6b41a828b	1107	* analog watchdog threshold high (on 8 bits):
<>	156:95d6b41a828b	1108	* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
<>	156:95d6b41a828b	1109	* (LL_ADC_RESOLUTION_8B,
<>	156:95d6b41a828b	1110	* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
<>	156:95d6b41a828b	1111	* );
<>	156:95d6b41a828b	1112	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1113	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1114	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1115	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1116	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1117	* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1118	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1119	*/
<>	156:95d6b41a828b	1120	#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
<>	156:95d6b41a828b	1121	((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
<>	156:95d6b41a828b	1122
<>	156:95d6b41a828b	1123	/**
<>	156:95d6b41a828b	1124	* @brief Helper macro to get the ADC analog watchdog threshold high
<>	156:95d6b41a828b	1125	* or low from raw value containing both thresholds concatenated.
<>	156:95d6b41a828b	1126	* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
<>	156:95d6b41a828b	1127	* Example, to get analog watchdog threshold high from the register raw value:
<>	156:95d6b41a828b	1128	* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
<>	156:95d6b41a828b	1129	* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1130	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	156:95d6b41a828b	1131	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	156:95d6b41a828b	1132	* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	156:95d6b41a828b	1133	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	1134	*/
<>	156:95d6b41a828b	1135	#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
<>	156:95d6b41a828b	1136	(((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \
<>	156:95d6b41a828b	1137	? ( \
<>	156:95d6b41a828b	1138	(__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \
<>	156:95d6b41a828b	1139	) \
<>	156:95d6b41a828b	1140	: \
<>	156:95d6b41a828b	1141	( \
<>	156:95d6b41a828b	1142	((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \
<>	156:95d6b41a828b	1143	) \
<>	156:95d6b41a828b	1144	)
<>	156:95d6b41a828b	1145
<>	156:95d6b41a828b	1146	/**
<>	156:95d6b41a828b	1147	* @brief Helper macro to select the ADC common instance
<>	156:95d6b41a828b	1148	* to which is belonging the selected ADC instance.
<>	156:95d6b41a828b	1149	* @note ADC common register instance can be used for:
<>	156:95d6b41a828b	1150	* - Set parameters common to several ADC instances
<>	156:95d6b41a828b	1151	* - Multimode (for devices with several ADC instances)
<>	156:95d6b41a828b	1152	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	156:95d6b41a828b	1153	* @param __ADCx__ ADC instance
<>	156:95d6b41a828b	1154	* @retval ADC common register instance
<>	156:95d6b41a828b	1155	*/
<>	156:95d6b41a828b	1156	#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
<>	156:95d6b41a828b	1157	(ADC1_COMMON)
<>	156:95d6b41a828b	1158
<>	156:95d6b41a828b	1159	/**
<>	156:95d6b41a828b	1160	* @brief Helper macro to check if all ADC instances sharing the same
<>	156:95d6b41a828b	1161	* ADC common instance are disabled.
<>	156:95d6b41a828b	1162	* @note This check is required by functions with setting conditioned to
<>	156:95d6b41a828b	1163	* ADC state:
<>	156:95d6b41a828b	1164	* All ADC instances of the ADC common group must be disabled.
<>	156:95d6b41a828b	1165	* Refer to functions having argument "ADCxy_COMMON" as parameter.
<>	156:95d6b41a828b	1166	* @note On devices with only 1 ADC common instance, parameter of this macro
<>	156:95d6b41a828b	1167	* is useless and can be ignored (parameter kept for compatibility
<>	156:95d6b41a828b	1168	* with devices featuring several ADC common instances).
<>	156:95d6b41a828b	1169	* @param __ADCXY_COMMON__ ADC common instance
<>	156:95d6b41a828b	1170	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	156:95d6b41a828b	1171	* @retval Value "0" if all ADC instances sharing the same ADC common instance
<>	156:95d6b41a828b	1172	* are disabled.
<>	156:95d6b41a828b	1173	* Value "1" if at least one ADC instance sharing the same ADC common instance
<>	156:95d6b41a828b	1174	* is enabled.
<>	156:95d6b41a828b	1175	*/
<>	156:95d6b41a828b	1176	#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
<>	156:95d6b41a828b	1177	LL_ADC_IsEnabled(ADC1)
<>	156:95d6b41a828b	1178
<>	156:95d6b41a828b	1179	/**
<>	156:95d6b41a828b	1180	* @brief Helper macro to define the ADC conversion data full-scale digital
<>	156:95d6b41a828b	1181	* value corresponding to the selected ADC resolution.
<>	156:95d6b41a828b	1182	* @note ADC conversion data full-scale corresponds to voltage range
<>	156:95d6b41a828b	1183	* determined by analog voltage references Vref+ and Vref-
<>	156:95d6b41a828b	1184	* (refer to reference manual).
<>	156:95d6b41a828b	1185	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1186	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1187	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1188	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1189	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1190	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	156:95d6b41a828b	1191	*/
<>	156:95d6b41a828b	1192	#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1193	(((uint32_t)0xFFFU) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)))
<>	156:95d6b41a828b	1194
<>	156:95d6b41a828b	1195	/**
<>	156:95d6b41a828b	1196	* @brief Helper macro to convert the ADC conversion data from
<>	156:95d6b41a828b	1197	* a resolution to another resolution.
<>	156:95d6b41a828b	1198	* @param __DATA__ ADC conversion data to be converted
<>	156:95d6b41a828b	1199	* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
<>	156:95d6b41a828b	1200	* This parameter can be one of the following values:
<>	156:95d6b41a828b	1201	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1202	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1203	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1204	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1205	* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
<>	156:95d6b41a828b	1206	* This parameter can be one of the following values:
<>	156:95d6b41a828b	1207	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1208	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1209	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1210	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1211	* @retval ADC conversion data to the requested resolution
<>	156:95d6b41a828b	1212	*/
<>	156:95d6b41a828b	1213	#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
<>	156:95d6b41a828b	1214	(((__DATA__) \
<>	156:95d6b41a828b	1215	<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \
<>	156:95d6b41a828b	1216	>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \
<>	156:95d6b41a828b	1217	)
<>	156:95d6b41a828b	1218
<>	156:95d6b41a828b	1219	/**
<>	156:95d6b41a828b	1220	* @brief Helper macro to calculate the voltage (unit: mVolt)
<>	156:95d6b41a828b	1221	* corresponding to a ADC conversion data (unit: digital value).
<>	156:95d6b41a828b	1222	* @note Analog reference voltage (Vref+) must be either known from
<>	156:95d6b41a828b	1223	* user board environment or can be calculated using ADC measurement
<>	156:95d6b41a828b	1224	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	156:95d6b41a828b	1225	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	156:95d6b41a828b	1226	* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
<>	156:95d6b41a828b	1227	* (unit: digital value).
<>	156:95d6b41a828b	1228	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1229	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1230	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1231	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1232	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1233	* @retval ADC conversion data equivalent voltage value (unit: mVolt)
<>	156:95d6b41a828b	1234	*/
<>	156:95d6b41a828b	1235	#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
<>	156:95d6b41a828b	1236	__ADC_DATA__,\
<>	156:95d6b41a828b	1237	__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1238	((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
<>	156:95d6b41a828b	1239	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1240	)
<>	156:95d6b41a828b	1241
<>	156:95d6b41a828b	1242	/**
<>	156:95d6b41a828b	1243	* @brief Helper macro to calculate analog reference voltage (Vref+)
<>	156:95d6b41a828b	1244	* (unit: mVolt) from ADC conversion data of internal voltage
<>	156:95d6b41a828b	1245	* reference VrefInt.
<>	156:95d6b41a828b	1246	* @note Computation is using VrefInt calibration value
<>	156:95d6b41a828b	1247	* stored in system memory for each device during production.
<>	156:95d6b41a828b	1248	* @note This voltage depends on user board environment: voltage level
<>	156:95d6b41a828b	1249	* connected to pin Vref+.
<>	156:95d6b41a828b	1250	* On devices with small package, the pin Vref+ is not present
<>	156:95d6b41a828b	1251	* and internally bonded to pin Vdda.
<>	156:95d6b41a828b	1252	* @note On this STM32 serie, calibration data of internal voltage reference
<>	156:95d6b41a828b	1253	* VrefInt corresponds to a resolution of 12 bits,
<>	156:95d6b41a828b	1254	* this is the recommended ADC resolution to convert voltage of
<>	156:95d6b41a828b	1255	* internal voltage reference VrefInt.
<>	156:95d6b41a828b	1256	* Otherwise, this macro performs the processing to scale
<>	156:95d6b41a828b	1257	* ADC conversion data to 12 bits.
<>	156:95d6b41a828b	1258	* @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)
<>	156:95d6b41a828b	1259	* of internal voltage reference VrefInt (unit: digital value).
<>	156:95d6b41a828b	1260	* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
<>	156:95d6b41a828b	1261	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1262	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1263	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1264	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1265	* @retval Analog reference voltage (unit: mV)
<>	156:95d6b41a828b	1266	*/
<>	156:95d6b41a828b	1267	#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
<>	156:95d6b41a828b	1268	__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1269	(((uint32_t)(VREFINT_CAL_ADDR) VREFINT_CAL_VREF) \
<>	156:95d6b41a828b	1270	/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
<>	156:95d6b41a828b	1271	(__ADC_RESOLUTION__), \
<>	156:95d6b41a828b	1272	LL_ADC_RESOLUTION_12B) \
<>	156:95d6b41a828b	1273	)
<>	156:95d6b41a828b	1274
<>	156:95d6b41a828b	1275	/**
<>	156:95d6b41a828b	1276	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	156:95d6b41a828b	1277	* from ADC conversion data of internal temperature sensor.
<>	156:95d6b41a828b	1278	* @note Computation is using temperature sensor calibration values
<>	156:95d6b41a828b	1279	* stored in system memory for each device during production.
<>	156:95d6b41a828b	1280	* @note Calculation formula:
<>	156:95d6b41a828b	1281	* Temperature = ((TS_ADC_DATA - TS_CAL1)
<>	156:95d6b41a828b	1282	* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
<>	156:95d6b41a828b	1283	* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
<>	156:95d6b41a828b	1284	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	156:95d6b41a828b	1285	* Avg_Slope = (TS_CAL2 - TS_CAL1)
<>	156:95d6b41a828b	1286	* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
<>	156:95d6b41a828b	1287	* TS_CAL1 = equivalent TS_ADC_DATA at temperature
<>	156:95d6b41a828b	1288	* TEMP_DEGC_CAL1 (calibrated in factory)
<>	156:95d6b41a828b	1289	* TS_CAL2 = equivalent TS_ADC_DATA at temperature
<>	156:95d6b41a828b	1290	* TEMP_DEGC_CAL2 (calibrated in factory)
<>	156:95d6b41a828b	1291	* Caution: Calculation relevancy under reserve that calibration
<>	156:95d6b41a828b	1292	* parameters are correct (address and data).
<>	156:95d6b41a828b	1293	* To calculate temperature using temperature sensor
<>	156:95d6b41a828b	1294	* datasheet typical values (generic values less, therefore
<>	156:95d6b41a828b	1295	* less accurate than calibrated values),
<>	156:95d6b41a828b	1296	* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
<>	156:95d6b41a828b	1297	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	156:95d6b41a828b	1298	* defined as it impacts the ADC LSB equivalent voltage.
<>	156:95d6b41a828b	1299	* @note Analog reference voltage (Vref+) must be either known from
<>	156:95d6b41a828b	1300	* user board environment or can be calculated using ADC measurement
<>	156:95d6b41a828b	1301	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	156:95d6b41a828b	1302	* @note On this STM32 serie, calibration data of temperature sensor
<>	156:95d6b41a828b	1303	* corresponds to a resolution of 12 bits,
<>	156:95d6b41a828b	1304	* this is the recommended ADC resolution to convert voltage of
<>	156:95d6b41a828b	1305	* temperature sensor.
<>	156:95d6b41a828b	1306	* Otherwise, this macro performs the processing to scale
<>	156:95d6b41a828b	1307	* ADC conversion data to 12 bits.
<>	156:95d6b41a828b	1308	* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
<>	156:95d6b41a828b	1309	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
<>	156:95d6b41a828b	1310	* temperature sensor (unit: digital value).
<>	156:95d6b41a828b	1311	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
<>	156:95d6b41a828b	1312	* sensor voltage has been measured.
<>	156:95d6b41a828b	1313	* This parameter can be one of the following values:
<>	156:95d6b41a828b	1314	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1315	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1316	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1317	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1318	* @retval Temperature (unit: degree Celsius)
<>	156:95d6b41a828b	1319	*/
<>	156:95d6b41a828b	1320	#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
<>	156:95d6b41a828b	1321	__TEMPSENSOR_ADC_DATA__,\
<>	156:95d6b41a828b	1322	__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1323	(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
<>	156:95d6b41a828b	1324	(__ADC_RESOLUTION__), \
<>	156:95d6b41a828b	1325	LL_ADC_RESOLUTION_12B) \
<>	156:95d6b41a828b	1326	* (__VREFANALOG_VOLTAGE__)) \
<>	156:95d6b41a828b	1327	/ TEMPSENSOR_CAL_VREFANALOG) \
<>	156:95d6b41a828b	1328	- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
<>	156:95d6b41a828b	1329	) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
<>	156:95d6b41a828b	1330	) / (int32_t)((int32_t)TEMPSENSOR_CAL2_ADDR - (int32_t)TEMPSENSOR_CAL1_ADDR) \
<>	156:95d6b41a828b	1331	) + TEMPSENSOR_CAL1_TEMP \
<>	156:95d6b41a828b	1332	)
<>	156:95d6b41a828b	1333
<>	156:95d6b41a828b	1334	/**
<>	156:95d6b41a828b	1335	* @brief Helper macro to calculate the temperature (unit: degree Celsius)
<>	156:95d6b41a828b	1336	* from ADC conversion data of internal temperature sensor.
<>	156:95d6b41a828b	1337	* @note Computation is using temperature sensor typical values
<>	156:95d6b41a828b	1338	* (refer to device datasheet).
<>	156:95d6b41a828b	1339	* @note Calculation formula:
<>	156:95d6b41a828b	1340	* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
<>	156:95d6b41a828b	1341	* / Avg_Slope + CALx_TEMP
<>	156:95d6b41a828b	1342	* with TS_ADC_DATA = temperature sensor raw data measured by ADC
<>	156:95d6b41a828b	1343	* (unit: digital value)
<>	156:95d6b41a828b	1344	* Avg_Slope = temperature sensor slope
<>	156:95d6b41a828b	1345	* (unit: uV/Degree Celsius)
<>	156:95d6b41a828b	1346	* TS_TYP_CALx_VOLT = temperature sensor digital value at
<>	156:95d6b41a828b	1347	* temperature CALx_TEMP (unit: mV)
<>	156:95d6b41a828b	1348	* Caution: Calculation relevancy under reserve the temperature sensor
<>	156:95d6b41a828b	1349	* of the current device has characteristics in line with
<>	156:95d6b41a828b	1350	* datasheet typical values.
<>	156:95d6b41a828b	1351	* If temperature sensor calibration values are available on
<>	156:95d6b41a828b	1352	* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
<>	156:95d6b41a828b	1353	* temperature calculation will be more accurate using
<>	156:95d6b41a828b	1354	* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
<>	156:95d6b41a828b	1355	* @note As calculation input, the analog reference voltage (Vref+) must be
<>	156:95d6b41a828b	1356	* defined as it impacts the ADC LSB equivalent voltage.
<>	156:95d6b41a828b	1357	* @note Analog reference voltage (Vref+) must be either known from
<>	156:95d6b41a828b	1358	* user board environment or can be calculated using ADC measurement
<>	156:95d6b41a828b	1359	* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
<>	156:95d6b41a828b	1360	* @note ADC measurement data must correspond to a resolution of 12bits
<>	156:95d6b41a828b	1361	* (full scale digital value 4095). If not the case, the data must be
<>	156:95d6b41a828b	1362	* preliminarily rescaled to an equivalent resolution of 12 bits.
<>	156:95d6b41a828b	1363	* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
<>	156:95d6b41a828b	1364	* On STM32F0, refer to device datasheet parameter "Avg_Slope".
<>	156:95d6b41a828b	1365	* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
<>	156:95d6b41a828b	1366	* On STM32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
<>	156:95d6b41a828b	1367	* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
<>	156:95d6b41a828b	1368	* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
<>	156:95d6b41a828b	1369	* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
<>	156:95d6b41a828b	1370	* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
<>	156:95d6b41a828b	1371	* This parameter can be one of the following values:
<>	156:95d6b41a828b	1372	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1373	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1374	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1375	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1376	* @retval Temperature (unit: degree Celsius)
<>	156:95d6b41a828b	1377	*/
<>	156:95d6b41a828b	1378	#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
<>	156:95d6b41a828b	1379	__TEMPSENSOR_TYP_CALX_V__,\
<>	156:95d6b41a828b	1380	__TEMPSENSOR_CALX_TEMP__,\
<>	156:95d6b41a828b	1381	__VREFANALOG_VOLTAGE__,\
<>	156:95d6b41a828b	1382	__TEMPSENSOR_ADC_DATA__,\
<>	156:95d6b41a828b	1383	__ADC_RESOLUTION__) \
<>	156:95d6b41a828b	1384	((( ( \
<>	156:95d6b41a828b	1385	(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
<>	156:95d6b41a828b	1386	* 1000) \
<>	156:95d6b41a828b	1387	- \
<>	156:95d6b41a828b	1388	(int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
<>	156:95d6b41a828b	1389	/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
<>	156:95d6b41a828b	1390	* 1000) \
<>	156:95d6b41a828b	1391	) \
<>	156:95d6b41a828b	1392	) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
<>	156:95d6b41a828b	1393	) + (__TEMPSENSOR_CALX_TEMP__) \
<>	156:95d6b41a828b	1394	)
<>	156:95d6b41a828b	1395
<>	156:95d6b41a828b	1396	/**
<>	156:95d6b41a828b	1397	* @}
<>	156:95d6b41a828b	1398	*/
<>	156:95d6b41a828b	1399
<>	156:95d6b41a828b	1400	/**
<>	156:95d6b41a828b	1401	* @}
<>	156:95d6b41a828b	1402	*/
<>	156:95d6b41a828b	1403
<>	156:95d6b41a828b	1404
<>	156:95d6b41a828b	1405	/* Exported functions --------------------------------------------------------*/
<>	156:95d6b41a828b	1406	/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
<>	156:95d6b41a828b	1407	* @{
<>	156:95d6b41a828b	1408	*/
<>	156:95d6b41a828b	1409
<>	156:95d6b41a828b	1410	/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
<>	156:95d6b41a828b	1411	* @{
<>	156:95d6b41a828b	1412	*/
<>	156:95d6b41a828b	1413	/* Note: LL ADC functions to set DMA transfer are located into sections of */
<>	156:95d6b41a828b	1414	/* configuration of ADC instance, groups and multimode (if available): */
<>	156:95d6b41a828b	1415	/* @ref LL_ADC_REG_SetDMATransfer(), ... */
<>	156:95d6b41a828b	1416
<>	156:95d6b41a828b	1417	/**
<>	156:95d6b41a828b	1418	* @brief Function to help to configure DMA transfer from ADC: retrieve the
<>	156:95d6b41a828b	1419	* ADC register address from ADC instance and a list of ADC registers
<>	156:95d6b41a828b	1420	* intended to be used (most commonly) with DMA transfer.
<>	156:95d6b41a828b	1421	* @note These ADC registers are data registers:
<>	156:95d6b41a828b	1422	* when ADC conversion data is available in ADC data registers,
<>	156:95d6b41a828b	1423	* ADC generates a DMA transfer request.
<>	156:95d6b41a828b	1424	* @note This macro is intended to be used with LL DMA driver, refer to
<>	156:95d6b41a828b	1425	* function "LL_DMA_ConfigAddresses()".
<>	156:95d6b41a828b	1426	* Example:
<>	156:95d6b41a828b	1427	* LL_DMA_ConfigAddresses(DMA1,
<>	156:95d6b41a828b	1428	* LL_DMA_CHANNEL_1,
<>	156:95d6b41a828b	1429	* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
<>	156:95d6b41a828b	1430	* (uint32_t)&< array or variable >,
<>	156:95d6b41a828b	1431	* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
<>	156:95d6b41a828b	1432	* @note For devices with several ADC: in multimode, some devices
<>	156:95d6b41a828b	1433	* use a different data register outside of ADC instance scope
<>	156:95d6b41a828b	1434	* (common data register). This macro manages this register difference,
<>	156:95d6b41a828b	1435	* only ADC instance has to be set as parameter.
<>	156:95d6b41a828b	1436	* @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
<>	156:95d6b41a828b	1437	* @param ADCx ADC instance
<>	156:95d6b41a828b	1438	* @param Register This parameter can be one of the following values:
<>	156:95d6b41a828b	1439	* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
<>	156:95d6b41a828b	1440	* @retval ADC register address
<>	156:95d6b41a828b	1441	*/
<>	156:95d6b41a828b	1442	__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
<>	156:95d6b41a828b	1443	{
<>	156:95d6b41a828b	1444	/* Retrieve address of register DR */
<>	156:95d6b41a828b	1445	return (uint32_t)&(ADCx->DR);
<>	156:95d6b41a828b	1446	}
<>	156:95d6b41a828b	1447
<>	156:95d6b41a828b	1448	/**
<>	156:95d6b41a828b	1449	* @}
<>	156:95d6b41a828b	1450	*/
<>	156:95d6b41a828b	1451
<>	156:95d6b41a828b	1452	/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
<>	156:95d6b41a828b	1453	* @{
<>	156:95d6b41a828b	1454	*/
<>	156:95d6b41a828b	1455
<>	156:95d6b41a828b	1456	/**
<>	156:95d6b41a828b	1457	* @brief Set parameter common to several ADC: measurement path to internal
<>	156:95d6b41a828b	1458	* channels (VrefInt, temperature sensor, ...).
<>	156:95d6b41a828b	1459	* @note One or several values can be selected.
<>	156:95d6b41a828b	1460	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	156:95d6b41a828b	1461	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	156:95d6b41a828b	1462	* @note Stabilization time of measurement path to internal channel:
<>	156:95d6b41a828b	1463	* After enabling internal paths, before starting ADC conversion,
<>	156:95d6b41a828b	1464	* a delay is required for internal voltage reference and
<>	156:95d6b41a828b	1465	* temperature sensor stabilization time.
<>	156:95d6b41a828b	1466	* Refer to device datasheet.
<>	156:95d6b41a828b	1467	* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
<>	156:95d6b41a828b	1468	* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
<>	156:95d6b41a828b	1469	* @note ADC internal channel sampling time constraint:
<>	156:95d6b41a828b	1470	* For ADC conversion of internal channels,
<>	156:95d6b41a828b	1471	* a sampling time minimum value is required.
<>	156:95d6b41a828b	1472	* Refer to device datasheet.
<>	156:95d6b41a828b	1473	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1474	* ADC state:
<>	156:95d6b41a828b	1475	* All ADC instances of the ADC common group must be disabled.
<>	156:95d6b41a828b	1476	* This check can be done with function @ref LL_ADC_IsEnabled() for each
<>	156:95d6b41a828b	1477	* ADC instance or by using helper macro helper macro
<>	156:95d6b41a828b	1478	* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
<>	156:95d6b41a828b	1479	* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
<>	156:95d6b41a828b	1480	* CCR TSEN LL_ADC_SetCommonPathInternalCh\n
<>	156:95d6b41a828b	1481	* CCR VBATEN LL_ADC_SetCommonPathInternalCh
<>	156:95d6b41a828b	1482	* @param ADCxy_COMMON ADC common instance
<>	156:95d6b41a828b	1483	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	156:95d6b41a828b	1484	* @param PathInternal This parameter can be a combination of the following values:
<>	156:95d6b41a828b	1485	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	156:95d6b41a828b	1486	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	156:95d6b41a828b	1487	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	156:95d6b41a828b	1488	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
<>	156:95d6b41a828b	1489	*
<>	156:95d6b41a828b	1490	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	1491	* @retval None
<>	156:95d6b41a828b	1492	*/
<>	156:95d6b41a828b	1493	__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
<>	156:95d6b41a828b	1494	{
<>	156:95d6b41a828b	1495	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	1496	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN, PathInternal);
<>	156:95d6b41a828b	1497	#else
<>	156:95d6b41a828b	1498	MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN, PathInternal);
<>	156:95d6b41a828b	1499	#endif
<>	156:95d6b41a828b	1500	}
<>	156:95d6b41a828b	1501
<>	156:95d6b41a828b	1502	/**
<>	156:95d6b41a828b	1503	* @brief Get parameter common to several ADC: measurement path to internal
<>	156:95d6b41a828b	1504	* channels (VrefInt, temperature sensor, ...).
<>	156:95d6b41a828b	1505	* @note One or several values can be selected.
<>	156:95d6b41a828b	1506	* Example: (LL_ADC_PATH_INTERNAL_VREFINT \|
<>	156:95d6b41a828b	1507	* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
<>	156:95d6b41a828b	1508	* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
<>	156:95d6b41a828b	1509	* CCR TSEN LL_ADC_GetCommonPathInternalCh\n
<>	156:95d6b41a828b	1510	* CCR VBATEN LL_ADC_GetCommonPathInternalCh
<>	156:95d6b41a828b	1511	* @param ADCxy_COMMON ADC common instance
<>	156:95d6b41a828b	1512	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
<>	156:95d6b41a828b	1513	* @retval Returned value can be a combination of the following values:
<>	156:95d6b41a828b	1514	* @arg @ref LL_ADC_PATH_INTERNAL_NONE
<>	156:95d6b41a828b	1515	* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
<>	156:95d6b41a828b	1516	* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
<>	156:95d6b41a828b	1517	* @arg @ref LL_ADC_PATH_INTERNAL_VBAT (1)
<>	156:95d6b41a828b	1518	*
<>	156:95d6b41a828b	1519	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	1520	*/
<>	156:95d6b41a828b	1521	__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
<>	156:95d6b41a828b	1522	{
<>	156:95d6b41a828b	1523	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	1524	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN \| ADC_CCR_VBATEN));
<>	156:95d6b41a828b	1525	#else
<>	156:95d6b41a828b	1526	return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN \| ADC_CCR_TSEN));
<>	156:95d6b41a828b	1527	#endif
<>	156:95d6b41a828b	1528	}
<>	156:95d6b41a828b	1529
<>	156:95d6b41a828b	1530	/**
<>	156:95d6b41a828b	1531	* @}
<>	156:95d6b41a828b	1532	*/
<>	156:95d6b41a828b	1533
<>	156:95d6b41a828b	1534	/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
<>	156:95d6b41a828b	1535	* @{
<>	156:95d6b41a828b	1536	*/
<>	156:95d6b41a828b	1537
<>	156:95d6b41a828b	1538	/**
<>	156:95d6b41a828b	1539	* @brief Set ADC instance clock source and prescaler.
<>	156:95d6b41a828b	1540	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1541	* ADC state:
<>	156:95d6b41a828b	1542	* ADC must be disabled.
<>	156:95d6b41a828b	1543	* @rmtoll CFGR2 CKMODE LL_ADC_SetClock
<>	156:95d6b41a828b	1544	* @param ADCx ADC instance
<>	156:95d6b41a828b	1545	* @param ClockSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1546	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	156:95d6b41a828b	1547	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	156:95d6b41a828b	1548	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
<>	156:95d6b41a828b	1549	*
<>	156:95d6b41a828b	1550	* (1) On this STM32 serie, synchronous clock has no prescaler.
<>	156:95d6b41a828b	1551	* @retval None
<>	156:95d6b41a828b	1552	*/
<>	156:95d6b41a828b	1553	__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
<>	156:95d6b41a828b	1554	{
<>	156:95d6b41a828b	1555	MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
<>	156:95d6b41a828b	1556	}
<>	156:95d6b41a828b	1557
<>	156:95d6b41a828b	1558	/**
<>	156:95d6b41a828b	1559	* @brief Get ADC instance clock source and prescaler.
<>	156:95d6b41a828b	1560	* @rmtoll CFGR2 CKMODE LL_ADC_GetClock
<>	156:95d6b41a828b	1561	* @param ADCx ADC instance
<>	156:95d6b41a828b	1562	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1563	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
<>	156:95d6b41a828b	1564	* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
<>	156:95d6b41a828b	1565	* @arg @ref LL_ADC_CLOCK_ASYNC (1)
<>	156:95d6b41a828b	1566	*
<>	156:95d6b41a828b	1567	* (1) On this STM32 serie, synchronous clock has no prescaler.
<>	156:95d6b41a828b	1568	*/
<>	156:95d6b41a828b	1569	__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1570	{
<>	156:95d6b41a828b	1571	return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
<>	156:95d6b41a828b	1572	}
<>	156:95d6b41a828b	1573
<>	156:95d6b41a828b	1574	/**
<>	156:95d6b41a828b	1575	* @brief Set ADC resolution.
<>	156:95d6b41a828b	1576	* Refer to reference manual for alignments formats
<>	156:95d6b41a828b	1577	* dependencies to ADC resolutions.
<>	156:95d6b41a828b	1578	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1579	* ADC state:
<>	156:95d6b41a828b	1580	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1581	* on group regular.
<>	156:95d6b41a828b	1582	* @rmtoll CFGR1 RES LL_ADC_SetResolution
<>	156:95d6b41a828b	1583	* @param ADCx ADC instance
<>	156:95d6b41a828b	1584	* @param Resolution This parameter can be one of the following values:
<>	156:95d6b41a828b	1585	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1586	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1587	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1588	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1589	* @retval None
<>	156:95d6b41a828b	1590	*/
<>	156:95d6b41a828b	1591	__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
<>	156:95d6b41a828b	1592	{
<>	156:95d6b41a828b	1593	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
<>	156:95d6b41a828b	1594	}
<>	156:95d6b41a828b	1595
<>	156:95d6b41a828b	1596	/**
<>	156:95d6b41a828b	1597	* @brief Get ADC resolution.
<>	156:95d6b41a828b	1598	* Refer to reference manual for alignments formats
<>	156:95d6b41a828b	1599	* dependencies to ADC resolutions.
<>	156:95d6b41a828b	1600	* @rmtoll CFGR1 RES LL_ADC_GetResolution
<>	156:95d6b41a828b	1601	* @param ADCx ADC instance
<>	156:95d6b41a828b	1602	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1603	* @arg @ref LL_ADC_RESOLUTION_12B
<>	156:95d6b41a828b	1604	* @arg @ref LL_ADC_RESOLUTION_10B
<>	156:95d6b41a828b	1605	* @arg @ref LL_ADC_RESOLUTION_8B
<>	156:95d6b41a828b	1606	* @arg @ref LL_ADC_RESOLUTION_6B
<>	156:95d6b41a828b	1607	*/
<>	156:95d6b41a828b	1608	__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1609	{
<>	156:95d6b41a828b	1610	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
<>	156:95d6b41a828b	1611	}
<>	156:95d6b41a828b	1612
<>	156:95d6b41a828b	1613	/**
<>	156:95d6b41a828b	1614	* @brief Set ADC conversion data alignment.
<>	156:95d6b41a828b	1615	* @note Refer to reference manual for alignments formats
<>	156:95d6b41a828b	1616	* dependencies to ADC resolutions.
<>	156:95d6b41a828b	1617	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1618	* ADC state:
<>	156:95d6b41a828b	1619	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1620	* on group regular.
<>	156:95d6b41a828b	1621	* @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment
<>	156:95d6b41a828b	1622	* @param ADCx ADC instance
<>	156:95d6b41a828b	1623	* @param DataAlignment This parameter can be one of the following values:
<>	156:95d6b41a828b	1624	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	156:95d6b41a828b	1625	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	156:95d6b41a828b	1626	* @retval None
<>	156:95d6b41a828b	1627	*/
<>	156:95d6b41a828b	1628	__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
<>	156:95d6b41a828b	1629	{
<>	156:95d6b41a828b	1630	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
<>	156:95d6b41a828b	1631	}
<>	156:95d6b41a828b	1632
<>	156:95d6b41a828b	1633	/**
<>	156:95d6b41a828b	1634	* @brief Get ADC conversion data alignment.
<>	156:95d6b41a828b	1635	* @note Refer to reference manual for alignments formats
<>	156:95d6b41a828b	1636	* dependencies to ADC resolutions.
<>	156:95d6b41a828b	1637	* @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment
<>	156:95d6b41a828b	1638	* @param ADCx ADC instance
<>	156:95d6b41a828b	1639	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1640	* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
<>	156:95d6b41a828b	1641	* @arg @ref LL_ADC_DATA_ALIGN_LEFT
<>	156:95d6b41a828b	1642	*/
<>	156:95d6b41a828b	1643	__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1644	{
<>	156:95d6b41a828b	1645	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
<>	156:95d6b41a828b	1646	}
<>	156:95d6b41a828b	1647
<>	156:95d6b41a828b	1648	/**
<>	156:95d6b41a828b	1649	* @brief Set ADC low power mode.
<>	156:95d6b41a828b	1650	* @note Description of ADC low power modes:
<>	156:95d6b41a828b	1651	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	156:95d6b41a828b	1652	* ADC conversions occurrences are limited to the minimum necessary
<>	156:95d6b41a828b	1653	* in order to reduce power consumption.
<>	156:95d6b41a828b	1654	* New ADC conversion starts only when the previous
<>	156:95d6b41a828b	1655	* unitary conversion data (for ADC group regular)
<>	156:95d6b41a828b	1656	* has been retrieved by user software.
<>	156:95d6b41a828b	1657	* In the meantime, ADC remains idle: does not performs any
<>	156:95d6b41a828b	1658	* other conversion.
<>	156:95d6b41a828b	1659	* This mode allows to automatically adapt the ADC conversions
<>	156:95d6b41a828b	1660	* triggers to the speed of the software that reads the data.
<>	156:95d6b41a828b	1661	* Moreover, this avoids risk of overrun for low frequency
<>	156:95d6b41a828b	1662	* applications.
<>	156:95d6b41a828b	1663	* How to use this low power mode:
<>	156:95d6b41a828b	1664	* - Do not use with interruption or DMA since these modes
<>	156:95d6b41a828b	1665	* have to clear immediately the EOC flag to free the
<>	156:95d6b41a828b	1666	* IRQ vector sequencer.
<>	156:95d6b41a828b	1667	* - Do use with polling: 1. Start conversion,
<>	156:95d6b41a828b	1668	* 2. Later on, when conversion data is needed: poll for end of
<>	156:95d6b41a828b	1669	* conversion to ensure that conversion is completed and
<>	156:95d6b41a828b	1670	* retrieve ADC conversion data. This will trig another
<>	156:95d6b41a828b	1671	* ADC conversion start.
<>	156:95d6b41a828b	1672	* - ADC low power mode "auto power-off" (feature available on
<>	156:95d6b41a828b	1673	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<>	156:95d6b41a828b	1674	* the ADC automatically powers-off after a conversion and
<>	156:95d6b41a828b	1675	* automatically wakes up when a new conversion is triggered
<>	156:95d6b41a828b	1676	* (with startup time between trigger and start of sampling).
<>	156:95d6b41a828b	1677	* This feature can be combined with low power mode "auto wait".
<>	156:95d6b41a828b	1678	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	156:95d6b41a828b	1679	* is corresponding to previous ADC conversion start, independently
<>	156:95d6b41a828b	1680	* of delay during which ADC was idle.
<>	156:95d6b41a828b	1681	* Therefore, the ADC conversion data may be outdated: does not
<>	156:95d6b41a828b	1682	* correspond to the current voltage level on the selected
<>	156:95d6b41a828b	1683	* ADC channel.
<>	156:95d6b41a828b	1684	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1685	* ADC state:
<>	156:95d6b41a828b	1686	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1687	* on group regular.
<>	156:95d6b41a828b	1688	* @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n
<>	156:95d6b41a828b	1689	* CFGR1 AUTOFF LL_ADC_SetLowPowerMode
<>	156:95d6b41a828b	1690	* @param ADCx ADC instance
<>	156:95d6b41a828b	1691	* @param LowPowerMode This parameter can be one of the following values:
<>	156:95d6b41a828b	1692	* @arg @ref LL_ADC_LP_MODE_NONE
<>	156:95d6b41a828b	1693	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	156:95d6b41a828b	1694	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
<>	156:95d6b41a828b	1695	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
<>	156:95d6b41a828b	1696	* @retval None
<>	156:95d6b41a828b	1697	*/
<>	156:95d6b41a828b	1698	__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
<>	156:95d6b41a828b	1699	{
<>	156:95d6b41a828b	1700	MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF), LowPowerMode);
<>	156:95d6b41a828b	1701	}
<>	156:95d6b41a828b	1702
<>	156:95d6b41a828b	1703	/**
<>	156:95d6b41a828b	1704	* @brief Get ADC low power mode:
<>	156:95d6b41a828b	1705	* @note Description of ADC low power modes:
<>	156:95d6b41a828b	1706	* - ADC low power mode "auto wait": Dynamic low power mode,
<>	156:95d6b41a828b	1707	* ADC conversions occurrences are limited to the minimum necessary
<>	156:95d6b41a828b	1708	* in order to reduce power consumption.
<>	156:95d6b41a828b	1709	* New ADC conversion starts only when the previous
<>	156:95d6b41a828b	1710	* unitary conversion data (for ADC group regular)
<>	156:95d6b41a828b	1711	* has been retrieved by user software.
<>	156:95d6b41a828b	1712	* In the meantime, ADC remains idle: does not performs any
<>	156:95d6b41a828b	1713	* other conversion.
<>	156:95d6b41a828b	1714	* This mode allows to automatically adapt the ADC conversions
<>	156:95d6b41a828b	1715	* triggers to the speed of the software that reads the data.
<>	156:95d6b41a828b	1716	* Moreover, this avoids risk of overrun for low frequency
<>	156:95d6b41a828b	1717	* applications.
<>	156:95d6b41a828b	1718	* How to use this low power mode:
<>	156:95d6b41a828b	1719	* - Do not use with interruption or DMA since these modes
<>	156:95d6b41a828b	1720	* have to clear immediately the EOC flag to free the
<>	156:95d6b41a828b	1721	* IRQ vector sequencer.
<>	156:95d6b41a828b	1722	* - Do use with polling: 1. Start conversion,
<>	156:95d6b41a828b	1723	* 2. Later on, when conversion data is needed: poll for end of
<>	156:95d6b41a828b	1724	* conversion to ensure that conversion is completed and
<>	156:95d6b41a828b	1725	* retrieve ADC conversion data. This will trig another
<>	156:95d6b41a828b	1726	* ADC conversion start.
<>	156:95d6b41a828b	1727	* - ADC low power mode "auto power-off" (feature available on
<>	156:95d6b41a828b	1728	* this device if parameter LL_ADC_LP_MODE_AUTOOFF is available):
<>	156:95d6b41a828b	1729	* the ADC automatically powers-off after a conversion and
<>	156:95d6b41a828b	1730	* automatically wakes up when a new conversion is triggered
<>	156:95d6b41a828b	1731	* (with startup time between trigger and start of sampling).
<>	156:95d6b41a828b	1732	* This feature can be combined with low power mode "auto wait".
<>	156:95d6b41a828b	1733	* @note With ADC low power mode "auto wait", the ADC conversion data read
<>	156:95d6b41a828b	1734	* is corresponding to previous ADC conversion start, independently
<>	156:95d6b41a828b	1735	* of delay during which ADC was idle.
<>	156:95d6b41a828b	1736	* Therefore, the ADC conversion data may be outdated: does not
<>	156:95d6b41a828b	1737	* correspond to the current voltage level on the selected
<>	156:95d6b41a828b	1738	* ADC channel.
<>	156:95d6b41a828b	1739	* @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n
<>	156:95d6b41a828b	1740	* CFGR1 AUTOFF LL_ADC_GetLowPowerMode
<>	156:95d6b41a828b	1741	* @param ADCx ADC instance
<>	156:95d6b41a828b	1742	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1743	* @arg @ref LL_ADC_LP_MODE_NONE
<>	156:95d6b41a828b	1744	* @arg @ref LL_ADC_LP_AUTOWAIT
<>	156:95d6b41a828b	1745	* @arg @ref LL_ADC_LP_AUTOPOWEROFF
<>	156:95d6b41a828b	1746	* @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
<>	156:95d6b41a828b	1747	*/
<>	156:95d6b41a828b	1748	__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1749	{
<>	156:95d6b41a828b	1750	return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT \| ADC_CFGR1_AUTOFF)));
<>	156:95d6b41a828b	1751	}
<>	156:95d6b41a828b	1752
<>	156:95d6b41a828b	1753	/**
<>	156:95d6b41a828b	1754	* @brief Set sampling time common to a group of channels.
<>	156:95d6b41a828b	1755	* @note Unit: ADC clock cycles.
<>	156:95d6b41a828b	1756	* @note On this STM32 serie, sampling time scope is on ADC instance:
<>	156:95d6b41a828b	1757	* Sampling time common to all channels.
<>	156:95d6b41a828b	1758	* (on some other STM32 families, sampling time is channel wise)
<>	156:95d6b41a828b	1759	* @note In case of internal channel (VrefInt, TempSensor, ...) to be
<>	156:95d6b41a828b	1760	* converted:
<>	156:95d6b41a828b	1761	* sampling time constraints must be respected (sampling time can be
<>	156:95d6b41a828b	1762	* adjusted in function of ADC clock frequency and sampling time
<>	156:95d6b41a828b	1763	* setting).
<>	156:95d6b41a828b	1764	* Refer to device datasheet for timings values (parameters TS_vrefint,
<>	156:95d6b41a828b	1765	* TS_temp, ...).
<>	156:95d6b41a828b	1766	* @note Conversion time is the addition of sampling time and processing time.
<>	156:95d6b41a828b	1767	* On this STM32 serie, ADC processing time is:
<>	156:95d6b41a828b	1768	* - 12.5 ADC clock cycles at ADC resolution 12 bits
<>	156:95d6b41a828b	1769	* - 10.5 ADC clock cycles at ADC resolution 10 bits
<>	156:95d6b41a828b	1770	* - 8.5 ADC clock cycles at ADC resolution 8 bits
<>	156:95d6b41a828b	1771	* - 6.5 ADC clock cycles at ADC resolution 6 bits
<>	156:95d6b41a828b	1772	* @note In case of ADC conversion of internal channel (VrefInt,
<>	156:95d6b41a828b	1773	* temperature sensor, ...), a sampling time minimum value
<>	156:95d6b41a828b	1774	* is required.
<>	156:95d6b41a828b	1775	* Refer to device datasheet.
<>	156:95d6b41a828b	1776	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1777	* ADC state:
<>	156:95d6b41a828b	1778	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1779	* on group regular.
<>	156:95d6b41a828b	1780	* @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels
<>	156:95d6b41a828b	1781	* @param ADCx ADC instance
<>	156:95d6b41a828b	1782	* @param SamplingTime This parameter can be one of the following values:
<>	156:95d6b41a828b	1783	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
<>	156:95d6b41a828b	1784	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
<>	156:95d6b41a828b	1785	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
<>	156:95d6b41a828b	1786	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
<>	156:95d6b41a828b	1787	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
<>	156:95d6b41a828b	1788	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
<>	156:95d6b41a828b	1789	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
<>	156:95d6b41a828b	1790	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
<>	156:95d6b41a828b	1791	* @retval None
<>	156:95d6b41a828b	1792	*/
<>	156:95d6b41a828b	1793	__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime)
<>	156:95d6b41a828b	1794	{
<>	156:95d6b41a828b	1795	MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime);
<>	156:95d6b41a828b	1796	}
<>	156:95d6b41a828b	1797
<>	156:95d6b41a828b	1798	/**
<>	156:95d6b41a828b	1799	* @brief Get sampling time common to a group of channels.
<>	156:95d6b41a828b	1800	* @note Unit: ADC clock cycles.
<>	156:95d6b41a828b	1801	* @note On this STM32 serie, sampling time scope is on ADC instance:
<>	156:95d6b41a828b	1802	* Sampling time common to all channels.
<>	156:95d6b41a828b	1803	* (on some other STM32 families, sampling time is channel wise)
<>	156:95d6b41a828b	1804	* @note Conversion time is the addition of sampling time and processing time.
<>	156:95d6b41a828b	1805	* Refer to reference manual for ADC processing time of
<>	156:95d6b41a828b	1806	* this STM32 serie.
<>	156:95d6b41a828b	1807	* @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels
<>	156:95d6b41a828b	1808	* @param ADCx ADC instance
<>	156:95d6b41a828b	1809	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1810	* @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
<>	156:95d6b41a828b	1811	* @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
<>	156:95d6b41a828b	1812	* @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
<>	156:95d6b41a828b	1813	* @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
<>	156:95d6b41a828b	1814	* @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
<>	156:95d6b41a828b	1815	* @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
<>	156:95d6b41a828b	1816	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
<>	156:95d6b41a828b	1817	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
<>	156:95d6b41a828b	1818	*/
<>	156:95d6b41a828b	1819	__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1820	{
<>	156:95d6b41a828b	1821	return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP));
<>	156:95d6b41a828b	1822	}
<>	156:95d6b41a828b	1823
<>	156:95d6b41a828b	1824	/**
<>	156:95d6b41a828b	1825	* @}
<>	156:95d6b41a828b	1826	*/
<>	156:95d6b41a828b	1827
<>	156:95d6b41a828b	1828	/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
<>	156:95d6b41a828b	1829	* @{
<>	156:95d6b41a828b	1830	*/
<>	156:95d6b41a828b	1831
<>	156:95d6b41a828b	1832	/**
<>	156:95d6b41a828b	1833	* @brief Set ADC group regular conversion trigger source:
<>	156:95d6b41a828b	1834	* internal (SW start) or from external IP (timer event,
<>	156:95d6b41a828b	1835	* external interrupt line).
<>	156:95d6b41a828b	1836	* @note On this STM32 serie, setting trigger source to external trigger
<>	156:95d6b41a828b	1837	* also set trigger polarity to rising edge
<>	156:95d6b41a828b	1838	* (default setting for compatibility with some ADC on other
<>	156:95d6b41a828b	1839	* STM32 families having this setting set by HW default value).
<>	156:95d6b41a828b	1840	* In case of need to modify trigger edge, use
<>	156:95d6b41a828b	1841	* function @ref LL_ADC_REG_SetTriggerEdge().
<>	156:95d6b41a828b	1842	* @note Availability of parameters of trigger sources from timer
<>	156:95d6b41a828b	1843	* depends on timers availability on the selected device.
<>	156:95d6b41a828b	1844	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1845	* ADC state:
<>	156:95d6b41a828b	1846	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1847	* on group regular.
<>	156:95d6b41a828b	1848	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n
<>	156:95d6b41a828b	1849	* CFGR1 EXTEN LL_ADC_REG_SetTriggerSource
<>	156:95d6b41a828b	1850	* @param ADCx ADC instance
<>	156:95d6b41a828b	1851	* @param TriggerSource This parameter can be one of the following values:
<>	156:95d6b41a828b	1852	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	156:95d6b41a828b	1853	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	156:95d6b41a828b	1854	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
<>	156:95d6b41a828b	1855	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
<>	156:95d6b41a828b	1856	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	156:95d6b41a828b	1857	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
<>	156:95d6b41a828b	1858	*
<>	156:95d6b41a828b	1859	* (1) On STM32F0, parameter not available on all devices
<>	156:95d6b41a828b	1860	* @retval None
<>	156:95d6b41a828b	1861	*/
<>	156:95d6b41a828b	1862	__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
<>	156:95d6b41a828b	1863	{
<>	156:95d6b41a828b	1864	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN \| ADC_CFGR1_EXTSEL, TriggerSource);
<>	156:95d6b41a828b	1865	}
<>	156:95d6b41a828b	1866
<>	156:95d6b41a828b	1867	/**
<>	156:95d6b41a828b	1868	* @brief Get ADC group regular conversion trigger source:
<>	156:95d6b41a828b	1869	* internal (SW start) or from external IP (timer event,
<>	156:95d6b41a828b	1870	* external interrupt line).
<>	156:95d6b41a828b	1871	* @note To determine whether group regular trigger source is
<>	156:95d6b41a828b	1872	* internal (SW start) or external, without detail
<>	156:95d6b41a828b	1873	* of which peripheral is selected as external trigger,
<>	156:95d6b41a828b	1874	* (equivalent to
<>	156:95d6b41a828b	1875	* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
<>	156:95d6b41a828b	1876	* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
<>	156:95d6b41a828b	1877	* @note Availability of parameters of trigger sources from timer
<>	156:95d6b41a828b	1878	* depends on timers availability on the selected device.
<>	156:95d6b41a828b	1879	* @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n
<>	156:95d6b41a828b	1880	* CFGR1 EXTEN LL_ADC_REG_GetTriggerSource
<>	156:95d6b41a828b	1881	* @param ADCx ADC instance
<>	156:95d6b41a828b	1882	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1883	* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
<>	156:95d6b41a828b	1884	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
<>	156:95d6b41a828b	1885	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
<>	156:95d6b41a828b	1886	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
<>	156:95d6b41a828b	1887	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
<>	156:95d6b41a828b	1888	* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO (1)
<>	156:95d6b41a828b	1889	*
<>	156:95d6b41a828b	1890	* (1) On STM32F0, parameter not available on all devices
<>	156:95d6b41a828b	1891	*/
<>	156:95d6b41a828b	1892	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1893	{
<>	156:95d6b41a828b	1894	register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL \| ADC_CFGR1_EXTEN);
<>	156:95d6b41a828b	1895
<>	156:95d6b41a828b	1896	/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
<>	156:95d6b41a828b	1897	/* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */
<>	156:95d6b41a828b	1898	register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));
<>	156:95d6b41a828b	1899
<>	156:95d6b41a828b	1900	/* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */
<>	156:95d6b41a828b	1901	/* to match with triggers literals definition. */
<>	156:95d6b41a828b	1902	return ((TriggerSource
<>	156:95d6b41a828b	1903	& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
<>	156:95d6b41a828b	1904	\| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
<>	156:95d6b41a828b	1905	);
<>	156:95d6b41a828b	1906	}
<>	156:95d6b41a828b	1907
<>	156:95d6b41a828b	1908	/**
<>	156:95d6b41a828b	1909	* @brief Get ADC group regular conversion trigger source internal (SW start)
<>	156:95d6b41a828b	1910	or external.
<>	156:95d6b41a828b	1911	* @note In case of group regular trigger source set to external trigger,
<>	156:95d6b41a828b	1912	* to determine which peripheral is selected as external trigger,
<>	156:95d6b41a828b	1913	* use function @ref LL_ADC_REG_GetTriggerSource().
<>	156:95d6b41a828b	1914	* @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart
<>	156:95d6b41a828b	1915	* @param ADCx ADC instance
<>	156:95d6b41a828b	1916	* @retval Value "0" if trigger source external trigger
<>	156:95d6b41a828b	1917	* Value "1" if trigger source SW start.
<>	156:95d6b41a828b	1918	*/
<>	156:95d6b41a828b	1919	__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1920	{
<>	156:95d6b41a828b	1921	return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN));
<>	156:95d6b41a828b	1922	}
<>	156:95d6b41a828b	1923
<>	156:95d6b41a828b	1924	/**
<>	156:95d6b41a828b	1925	* @brief Set ADC group regular conversion trigger polarity.
<>	156:95d6b41a828b	1926	* @note Applicable only for trigger source set to external trigger.
<>	156:95d6b41a828b	1927	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1928	* ADC state:
<>	156:95d6b41a828b	1929	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1930	* on group regular.
<>	156:95d6b41a828b	1931	* @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge
<>	156:95d6b41a828b	1932	* @param ADCx ADC instance
<>	156:95d6b41a828b	1933	* @param ExternalTriggerEdge This parameter can be one of the following values:
<>	156:95d6b41a828b	1934	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	156:95d6b41a828b	1935	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	156:95d6b41a828b	1936	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	156:95d6b41a828b	1937	* @retval None
<>	156:95d6b41a828b	1938	*/
<>	156:95d6b41a828b	1939	__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
<>	156:95d6b41a828b	1940	{
<>	156:95d6b41a828b	1941	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
<>	156:95d6b41a828b	1942	}
<>	156:95d6b41a828b	1943
<>	156:95d6b41a828b	1944	/**
<>	156:95d6b41a828b	1945	* @brief Get ADC group regular conversion trigger polarity.
<>	156:95d6b41a828b	1946	* @note Applicable only for trigger source set to external trigger.
<>	156:95d6b41a828b	1947	* @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge
<>	156:95d6b41a828b	1948	* @param ADCx ADC instance
<>	156:95d6b41a828b	1949	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1950	* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
<>	156:95d6b41a828b	1951	* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
<>	156:95d6b41a828b	1952	* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
<>	156:95d6b41a828b	1953	*/
<>	156:95d6b41a828b	1954	__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1955	{
<>	156:95d6b41a828b	1956	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
<>	156:95d6b41a828b	1957	}
<>	156:95d6b41a828b	1958
<>	156:95d6b41a828b	1959
<>	156:95d6b41a828b	1960	/**
<>	156:95d6b41a828b	1961	* @brief Set ADC group regular sequencer scan direction.
<>	156:95d6b41a828b	1962	* @note On some other STM32 families, this setting is not available and
<>	156:95d6b41a828b	1963	* the default scan direction is forward.
<>	156:95d6b41a828b	1964	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	1965	* ADC state:
<>	156:95d6b41a828b	1966	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	1967	* on group regular.
<>	156:95d6b41a828b	1968	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection
<>	156:95d6b41a828b	1969	* @param ADCx ADC instance
<>	156:95d6b41a828b	1970	* @param ScanDirection This parameter can be one of the following values:
<>	156:95d6b41a828b	1971	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
<>	156:95d6b41a828b	1972	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
<>	156:95d6b41a828b	1973	* @retval None
<>	156:95d6b41a828b	1974	*/
<>	156:95d6b41a828b	1975	__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
<>	156:95d6b41a828b	1976	{
<>	156:95d6b41a828b	1977	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
<>	156:95d6b41a828b	1978	}
<>	156:95d6b41a828b	1979
<>	156:95d6b41a828b	1980	/**
<>	156:95d6b41a828b	1981	* @brief Get ADC group regular sequencer scan direction.
<>	156:95d6b41a828b	1982	* @note On some other STM32 families, this setting is not available and
<>	156:95d6b41a828b	1983	* the default scan direction is forward.
<>	156:95d6b41a828b	1984	* @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection
<>	156:95d6b41a828b	1985	* @param ADCx ADC instance
<>	156:95d6b41a828b	1986	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	1987	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
<>	156:95d6b41a828b	1988	* @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
<>	156:95d6b41a828b	1989	*/
<>	156:95d6b41a828b	1990	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	1991	{
<>	156:95d6b41a828b	1992	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
<>	156:95d6b41a828b	1993	}
<>	156:95d6b41a828b	1994
<>	156:95d6b41a828b	1995	/**
<>	156:95d6b41a828b	1996	* @brief Set ADC group regular sequencer discontinuous mode:
<>	156:95d6b41a828b	1997	* sequence subdivided and scan conversions interrupted every selected
<>	156:95d6b41a828b	1998	* number of ranks.
<>	156:95d6b41a828b	1999	* @note It is not possible to enable both ADC group regular
<>	156:95d6b41a828b	2000	* continuous mode and sequencer discontinuous mode.
<>	156:95d6b41a828b	2001	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2002	* ADC state:
<>	156:95d6b41a828b	2003	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2004	* on group regular.
<>	156:95d6b41a828b	2005	* @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
<>	156:95d6b41a828b	2006	* @param ADCx ADC instance
<>	156:95d6b41a828b	2007	* @param SeqDiscont This parameter can be one of the following values:
<>	156:95d6b41a828b	2008	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	156:95d6b41a828b	2009	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	156:95d6b41a828b	2010	* @retval None
<>	156:95d6b41a828b	2011	*/
<>	156:95d6b41a828b	2012	__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
<>	156:95d6b41a828b	2013	{
<>	156:95d6b41a828b	2014	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
<>	156:95d6b41a828b	2015	}
<>	156:95d6b41a828b	2016
<>	156:95d6b41a828b	2017	/**
<>	156:95d6b41a828b	2018	* @brief Get ADC group regular sequencer discontinuous mode:
<>	156:95d6b41a828b	2019	* sequence subdivided and scan conversions interrupted every selected
<>	156:95d6b41a828b	2020	* number of ranks.
<>	156:95d6b41a828b	2021	* @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
<>	156:95d6b41a828b	2022	* @param ADCx ADC instance
<>	156:95d6b41a828b	2023	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2024	* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
<>	156:95d6b41a828b	2025	* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
<>	156:95d6b41a828b	2026	*/
<>	156:95d6b41a828b	2027	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2028	{
<>	156:95d6b41a828b	2029	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
<>	156:95d6b41a828b	2030	}
<>	156:95d6b41a828b	2031
<>	156:95d6b41a828b	2032	/**
<>	156:95d6b41a828b	2033	* @brief Set ADC group regular sequence: channel on rank corresponding to
<>	156:95d6b41a828b	2034	* channel number.
<>	156:95d6b41a828b	2035	* @note This function performs:
<>	156:95d6b41a828b	2036	* - Channels ordering into each rank of scan sequence:
<>	156:95d6b41a828b	2037	* rank of each channel is fixed by channel HW number
<>	156:95d6b41a828b	2038	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	156:95d6b41a828b	2039	* - Set channels selected by overwriting the current sequencer
<>	156:95d6b41a828b	2040	* configuration.
<>	156:95d6b41a828b	2041	* @note On this STM32 serie, ADC group regular sequencer is
<>	156:95d6b41a828b	2042	* not fully configurable: sequencer length and each rank
<>	156:95d6b41a828b	2043	* affectation to a channel are fixed by channel HW number.
<>	156:95d6b41a828b	2044	* @note Depending on devices and packages, some channels may not be available.
<>	156:95d6b41a828b	2045	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	2046	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	156:95d6b41a828b	2047	* TempSensor, ...), measurement paths to internal channels must be
<>	156:95d6b41a828b	2048	* enabled separately.
<>	156:95d6b41a828b	2049	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	156:95d6b41a828b	2050	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2051	* ADC state:
<>	156:95d6b41a828b	2052	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2053	* on group regular.
<>	156:95d6b41a828b	2054	* @note One or several values can be selected.
<>	156:95d6b41a828b	2055	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	156:95d6b41a828b	2056	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2057	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2058	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2059	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2060	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2061	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2062	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2063	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2064	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2065	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2066	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2067	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2068	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2069	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2070	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2071	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2072	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2073	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n
<>	156:95d6b41a828b	2074	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels
<>	156:95d6b41a828b	2075	* @param ADCx ADC instance
<>	156:95d6b41a828b	2076	* @param Channel This parameter can be a combination of the following values:
<>	156:95d6b41a828b	2077	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	2078	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	2079	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	2080	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	2081	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	2082	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	2083	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	2084	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	2085	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	2086	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	2087	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	2088	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	2089	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	2090	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	2091	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	2092	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	2093	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	2094	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	2095	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	2096	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	2097	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	2098	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	2099	*
<>	156:95d6b41a828b	2100	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	2101	* @retval None
<>	156:95d6b41a828b	2102	*/
<>	156:95d6b41a828b	2103	__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
<>	156:95d6b41a828b	2104	{
<>	156:95d6b41a828b	2105	/* Parameter "Channel" is used with masks because containing */
<>	156:95d6b41a828b	2106	/* other bits reserved for other purpose. */
<>	156:95d6b41a828b	2107	WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<>	156:95d6b41a828b	2108	}
<>	156:95d6b41a828b	2109
<>	156:95d6b41a828b	2110	/**
<>	156:95d6b41a828b	2111	* @brief Add channel to ADC group regular sequence: channel on rank corresponding to
<>	156:95d6b41a828b	2112	* channel number.
<>	156:95d6b41a828b	2113	* @note This function performs:
<>	156:95d6b41a828b	2114	* - Channels ordering into each rank of scan sequence:
<>	156:95d6b41a828b	2115	* rank of each channel is fixed by channel HW number
<>	156:95d6b41a828b	2116	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	156:95d6b41a828b	2117	* - Set channels selected by adding them to the current sequencer
<>	156:95d6b41a828b	2118	* configuration.
<>	156:95d6b41a828b	2119	* @note On this STM32 serie, ADC group regular sequencer is
<>	156:95d6b41a828b	2120	* not fully configurable: sequencer length and each rank
<>	156:95d6b41a828b	2121	* affectation to a channel are fixed by channel HW number.
<>	156:95d6b41a828b	2122	* @note Depending on devices and packages, some channels may not be available.
<>	156:95d6b41a828b	2123	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	2124	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	156:95d6b41a828b	2125	* TempSensor, ...), measurement paths to internal channels must be
<>	156:95d6b41a828b	2126	* enabled separately.
<>	156:95d6b41a828b	2127	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	156:95d6b41a828b	2128	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2129	* ADC state:
<>	156:95d6b41a828b	2130	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2131	* on group regular.
<>	156:95d6b41a828b	2132	* @note One or several values can be selected.
<>	156:95d6b41a828b	2133	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	156:95d6b41a828b	2134	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2135	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2136	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2137	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2138	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2139	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2140	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2141	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2142	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2143	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2144	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2145	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2146	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2147	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2148	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2149	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2150	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2151	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n
<>	156:95d6b41a828b	2152	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd
<>	156:95d6b41a828b	2153	* @param ADCx ADC instance
<>	156:95d6b41a828b	2154	* @param Channel This parameter can be a combination of the following values:
<>	156:95d6b41a828b	2155	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	2156	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	2157	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	2158	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	2159	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	2160	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	2161	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	2162	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	2163	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	2164	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	2165	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	2166	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	2167	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	2168	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	2169	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	2170	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	2171	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	2172	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	2173	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	2174	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	2175	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	2176	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	2177	*
<>	156:95d6b41a828b	2178	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	2179	* @retval None
<>	156:95d6b41a828b	2180	*/
<>	156:95d6b41a828b	2181	__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
<>	156:95d6b41a828b	2182	{
<>	156:95d6b41a828b	2183	/* Parameter "Channel" is used with masks because containing */
<>	156:95d6b41a828b	2184	/* other bits reserved for other purpose. */
<>	156:95d6b41a828b	2185	SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<>	156:95d6b41a828b	2186	}
<>	156:95d6b41a828b	2187
<>	156:95d6b41a828b	2188	/**
<>	156:95d6b41a828b	2189	* @brief Remove channel to ADC group regular sequence: channel on rank corresponding to
<>	156:95d6b41a828b	2190	* channel number.
<>	156:95d6b41a828b	2191	* @note This function performs:
<>	156:95d6b41a828b	2192	* - Channels ordering into each rank of scan sequence:
<>	156:95d6b41a828b	2193	* rank of each channel is fixed by channel HW number
<>	156:95d6b41a828b	2194	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	156:95d6b41a828b	2195	* - Set channels selected by removing them to the current sequencer
<>	156:95d6b41a828b	2196	* configuration.
<>	156:95d6b41a828b	2197	* @note On this STM32 serie, ADC group regular sequencer is
<>	156:95d6b41a828b	2198	* not fully configurable: sequencer length and each rank
<>	156:95d6b41a828b	2199	* affectation to a channel are fixed by channel HW number.
<>	156:95d6b41a828b	2200	* @note Depending on devices and packages, some channels may not be available.
<>	156:95d6b41a828b	2201	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	2202	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	156:95d6b41a828b	2203	* TempSensor, ...), measurement paths to internal channels must be
<>	156:95d6b41a828b	2204	* enabled separately.
<>	156:95d6b41a828b	2205	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	156:95d6b41a828b	2206	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2207	* ADC state:
<>	156:95d6b41a828b	2208	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2209	* on group regular.
<>	156:95d6b41a828b	2210	* @note One or several values can be selected.
<>	156:95d6b41a828b	2211	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	156:95d6b41a828b	2212	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2213	* CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2214	* CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2215	* CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2216	* CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2217	* CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2218	* CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2219	* CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2220	* CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2221	* CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2222	* CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2223	* CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2224	* CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2225	* CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2226	* CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2227	* CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2228	* CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2229	* CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n
<>	156:95d6b41a828b	2230	* CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem
<>	156:95d6b41a828b	2231	* @param ADCx ADC instance
<>	156:95d6b41a828b	2232	* @param Channel This parameter can be a combination of the following values:
<>	156:95d6b41a828b	2233	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	2234	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	2235	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	2236	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	2237	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	2238	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	2239	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	2240	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	2241	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	2242	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	2243	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	2244	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	2245	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	2246	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	2247	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	2248	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	2249	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	2250	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	2251	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	2252	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	2253	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	2254	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	2255	*
<>	156:95d6b41a828b	2256	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	2257	* @retval None
<>	156:95d6b41a828b	2258	*/
<>	156:95d6b41a828b	2259	__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
<>	156:95d6b41a828b	2260	{
<>	156:95d6b41a828b	2261	/* Parameter "Channel" is used with masks because containing */
<>	156:95d6b41a828b	2262	/* other bits reserved for other purpose. */
<>	156:95d6b41a828b	2263	CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
<>	156:95d6b41a828b	2264	}
<>	156:95d6b41a828b	2265
<>	156:95d6b41a828b	2266	/**
<>	156:95d6b41a828b	2267	* @brief Get ADC group regular sequence: channel on rank corresponding to
<>	156:95d6b41a828b	2268	* channel number.
<>	156:95d6b41a828b	2269	* @note This function performs:
<>	156:95d6b41a828b	2270	* - Channels order reading into each rank of scan sequence:
<>	156:95d6b41a828b	2271	* rank of each channel is fixed by channel HW number
<>	156:95d6b41a828b	2272	* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	156:95d6b41a828b	2273	* @note On this STM32 serie, ADC group regular sequencer is
<>	156:95d6b41a828b	2274	* not fully configurable: sequencer length and each rank
<>	156:95d6b41a828b	2275	* affectation to a channel are fixed by channel HW number.
<>	156:95d6b41a828b	2276	* @note Depending on devices and packages, some channels may not be available.
<>	156:95d6b41a828b	2277	* Refer to device datasheet for channels availability.
<>	156:95d6b41a828b	2278	* @note On this STM32 serie, to measure internal channels (VrefInt,
<>	156:95d6b41a828b	2279	* TempSensor, ...), measurement paths to internal channels must be
<>	156:95d6b41a828b	2280	* enabled separately.
<>	156:95d6b41a828b	2281	* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
<>	156:95d6b41a828b	2282	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2283	* ADC state:
<>	156:95d6b41a828b	2284	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2285	* on group regular.
<>	156:95d6b41a828b	2286	* @note One or several values can be retrieved.
<>	156:95d6b41a828b	2287	* Example: (LL_ADC_CHANNEL_4 \| LL_ADC_CHANNEL_12 \| ...)
<>	156:95d6b41a828b	2288	* @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2289	* CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2290	* CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2291	* CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2292	* CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2293	* CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2294	* CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2295	* CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2296	* CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2297	* CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2298	* CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2299	* CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2300	* CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2301	* CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2302	* CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2303	* CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2304	* CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2305	* CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n
<>	156:95d6b41a828b	2306	* CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels
<>	156:95d6b41a828b	2307	* @param ADCx ADC instance
<>	156:95d6b41a828b	2308	* @retval Returned value can be a combination of the following values:
<>	156:95d6b41a828b	2309	* @arg @ref LL_ADC_CHANNEL_0
<>	156:95d6b41a828b	2310	* @arg @ref LL_ADC_CHANNEL_1
<>	156:95d6b41a828b	2311	* @arg @ref LL_ADC_CHANNEL_2
<>	156:95d6b41a828b	2312	* @arg @ref LL_ADC_CHANNEL_3
<>	156:95d6b41a828b	2313	* @arg @ref LL_ADC_CHANNEL_4
<>	156:95d6b41a828b	2314	* @arg @ref LL_ADC_CHANNEL_5
<>	156:95d6b41a828b	2315	* @arg @ref LL_ADC_CHANNEL_6
<>	156:95d6b41a828b	2316	* @arg @ref LL_ADC_CHANNEL_7
<>	156:95d6b41a828b	2317	* @arg @ref LL_ADC_CHANNEL_8
<>	156:95d6b41a828b	2318	* @arg @ref LL_ADC_CHANNEL_9
<>	156:95d6b41a828b	2319	* @arg @ref LL_ADC_CHANNEL_10
<>	156:95d6b41a828b	2320	* @arg @ref LL_ADC_CHANNEL_11
<>	156:95d6b41a828b	2321	* @arg @ref LL_ADC_CHANNEL_12
<>	156:95d6b41a828b	2322	* @arg @ref LL_ADC_CHANNEL_13
<>	156:95d6b41a828b	2323	* @arg @ref LL_ADC_CHANNEL_14
<>	156:95d6b41a828b	2324	* @arg @ref LL_ADC_CHANNEL_15
<>	156:95d6b41a828b	2325	* @arg @ref LL_ADC_CHANNEL_16
<>	156:95d6b41a828b	2326	* @arg @ref LL_ADC_CHANNEL_17
<>	156:95d6b41a828b	2327	* @arg @ref LL_ADC_CHANNEL_18 (1)
<>	156:95d6b41a828b	2328	* @arg @ref LL_ADC_CHANNEL_VREFINT
<>	156:95d6b41a828b	2329	* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR
<>	156:95d6b41a828b	2330	* @arg @ref LL_ADC_CHANNEL_VBAT (1)
<>	156:95d6b41a828b	2331	*
<>	156:95d6b41a828b	2332	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	2333	*/
<>	156:95d6b41a828b	2334	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2335	{
<>	156:95d6b41a828b	2336	register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
<>	156:95d6b41a828b	2337
<>	156:95d6b41a828b	2338	return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
<>	156:95d6b41a828b	2339	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
<>	156:95d6b41a828b	2340	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
<>	156:95d6b41a828b	2341	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
<>	156:95d6b41a828b	2342	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
<>	156:95d6b41a828b	2343	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
<>	156:95d6b41a828b	2344	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
<>	156:95d6b41a828b	2345	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
<>	156:95d6b41a828b	2346	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
<>	156:95d6b41a828b	2347	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
<>	156:95d6b41a828b	2348	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
<>	156:95d6b41a828b	2349	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
<>	156:95d6b41a828b	2350	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
<>	156:95d6b41a828b	2351	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
<>	156:95d6b41a828b	2352	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
<>	156:95d6b41a828b	2353	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
<>	156:95d6b41a828b	2354	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
<>	156:95d6b41a828b	2355	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
<>	156:95d6b41a828b	2356	#if defined(ADC_CCR_VBATEN)
<>	156:95d6b41a828b	2357	\| (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
<>	156:95d6b41a828b	2358	#endif
<>	156:95d6b41a828b	2359	);
<>	156:95d6b41a828b	2360	}
<>	156:95d6b41a828b	2361	/**
<>	156:95d6b41a828b	2362	* @brief Set ADC continuous conversion mode on ADC group regular.
<>	156:95d6b41a828b	2363	* @note Description of ADC continuous conversion mode:
<>	156:95d6b41a828b	2364	* - single mode: one conversion per trigger
<>	156:95d6b41a828b	2365	* - continuous mode: after the first trigger, following
<>	156:95d6b41a828b	2366	* conversions launched successively automatically.
<>	156:95d6b41a828b	2367	* @note It is not possible to enable both ADC group regular
<>	156:95d6b41a828b	2368	* continuous mode and sequencer discontinuous mode.
<>	156:95d6b41a828b	2369	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2370	* ADC state:
<>	156:95d6b41a828b	2371	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2372	* on group regular.
<>	156:95d6b41a828b	2373	* @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode
<>	156:95d6b41a828b	2374	* @param ADCx ADC instance
<>	156:95d6b41a828b	2375	* @param Continuous This parameter can be one of the following values:
<>	156:95d6b41a828b	2376	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	156:95d6b41a828b	2377	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	156:95d6b41a828b	2378	* @retval None
<>	156:95d6b41a828b	2379	*/
<>	156:95d6b41a828b	2380	__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
<>	156:95d6b41a828b	2381	{
<>	156:95d6b41a828b	2382	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
<>	156:95d6b41a828b	2383	}
<>	156:95d6b41a828b	2384
<>	156:95d6b41a828b	2385	/**
<>	156:95d6b41a828b	2386	* @brief Get ADC continuous conversion mode on ADC group regular.
<>	156:95d6b41a828b	2387	* @note Description of ADC continuous conversion mode:
<>	156:95d6b41a828b	2388	* - single mode: one conversion per trigger
<>	156:95d6b41a828b	2389	* - continuous mode: after the first trigger, following
<>	156:95d6b41a828b	2390	* conversions launched successively automatically.
<>	156:95d6b41a828b	2391	* @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode
<>	156:95d6b41a828b	2392	* @param ADCx ADC instance
<>	156:95d6b41a828b	2393	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2394	* @arg @ref LL_ADC_REG_CONV_SINGLE
<>	156:95d6b41a828b	2395	* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
<>	156:95d6b41a828b	2396	*/
<>	156:95d6b41a828b	2397	__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2398	{
<>	156:95d6b41a828b	2399	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
<>	156:95d6b41a828b	2400	}
<>	156:95d6b41a828b	2401
<>	156:95d6b41a828b	2402	/**
<>	156:95d6b41a828b	2403	* @brief Set ADC group regular conversion data transfer: no transfer or
<>	156:95d6b41a828b	2404	* transfer by DMA, and DMA requests mode.
<>	156:95d6b41a828b	2405	* @note If transfer by DMA selected, specifies the DMA requests
<>	156:95d6b41a828b	2406	* mode:
<>	156:95d6b41a828b	2407	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	156:95d6b41a828b	2408	* when number of DMA data transfers (number of
<>	156:95d6b41a828b	2409	* ADC conversions) is reached.
<>	156:95d6b41a828b	2410	* This ADC mode is intended to be used with DMA mode non-circular.
<>	156:95d6b41a828b	2411	* - Unlimited mode: DMA transfer requests are unlimited,
<>	156:95d6b41a828b	2412	* whatever number of DMA data transfers (number of
<>	156:95d6b41a828b	2413	* ADC conversions).
<>	156:95d6b41a828b	2414	* This ADC mode is intended to be used with DMA mode circular.
<>	156:95d6b41a828b	2415	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	156:95d6b41a828b	2416	* mode non-circular:
<>	156:95d6b41a828b	2417	* when DMA transfers size will be reached, DMA will stop transfers of
<>	156:95d6b41a828b	2418	* ADC conversions data ADC will raise an overrun error
<>	156:95d6b41a828b	2419	* (overrun flag and interruption if enabled).
<>	156:95d6b41a828b	2420	* @note To configure DMA source address (peripheral address),
<>	156:95d6b41a828b	2421	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	156:95d6b41a828b	2422	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2423	* ADC state:
<>	156:95d6b41a828b	2424	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2425	* on group regular.
<>	156:95d6b41a828b	2426	* @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n
<>	156:95d6b41a828b	2427	* CFGR1 DMACFG LL_ADC_REG_SetDMATransfer
<>	156:95d6b41a828b	2428	* @param ADCx ADC instance
<>	156:95d6b41a828b	2429	* @param DMATransfer This parameter can be one of the following values:
<>	156:95d6b41a828b	2430	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	156:95d6b41a828b	2431	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	156:95d6b41a828b	2432	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	156:95d6b41a828b	2433	* @retval None
<>	156:95d6b41a828b	2434	*/
<>	156:95d6b41a828b	2435	__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
<>	156:95d6b41a828b	2436	{
<>	156:95d6b41a828b	2437	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG, DMATransfer);
<>	156:95d6b41a828b	2438	}
<>	156:95d6b41a828b	2439
<>	156:95d6b41a828b	2440	/**
<>	156:95d6b41a828b	2441	* @brief Get ADC group regular conversion data transfer: no transfer or
<>	156:95d6b41a828b	2442	* transfer by DMA, and DMA requests mode.
<>	156:95d6b41a828b	2443	* @note If transfer by DMA selected, specifies the DMA requests
<>	156:95d6b41a828b	2444	* mode:
<>	156:95d6b41a828b	2445	* - Limited mode (One shot mode): DMA transfer requests are stopped
<>	156:95d6b41a828b	2446	* when number of DMA data transfers (number of
<>	156:95d6b41a828b	2447	* ADC conversions) is reached.
<>	156:95d6b41a828b	2448	* This ADC mode is intended to be used with DMA mode non-circular.
<>	156:95d6b41a828b	2449	* - Unlimited mode: DMA transfer requests are unlimited,
<>	156:95d6b41a828b	2450	* whatever number of DMA data transfers (number of
<>	156:95d6b41a828b	2451	* ADC conversions).
<>	156:95d6b41a828b	2452	* This ADC mode is intended to be used with DMA mode circular.
<>	156:95d6b41a828b	2453	* @note If ADC DMA requests mode is set to unlimited and DMA is set to
<>	156:95d6b41a828b	2454	* mode non-circular:
<>	156:95d6b41a828b	2455	* when DMA transfers size will be reached, DMA will stop transfers of
<>	156:95d6b41a828b	2456	* ADC conversions data ADC will raise an overrun error
<>	156:95d6b41a828b	2457	* (overrun flag and interruption if enabled).
<>	156:95d6b41a828b	2458	* @note To configure DMA source address (peripheral address),
<>	156:95d6b41a828b	2459	* use function @ref LL_ADC_DMA_GetRegAddr().
<>	156:95d6b41a828b	2460	* @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n
<>	156:95d6b41a828b	2461	* CFGR1 DMACFG LL_ADC_REG_GetDMATransfer
<>	156:95d6b41a828b	2462	* @param ADCx ADC instance
<>	156:95d6b41a828b	2463	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2464	* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
<>	156:95d6b41a828b	2465	* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
<>	156:95d6b41a828b	2466	* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
<>	156:95d6b41a828b	2467	*/
<>	156:95d6b41a828b	2468	__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2469	{
<>	156:95d6b41a828b	2470	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN \| ADC_CFGR1_DMACFG));
<>	156:95d6b41a828b	2471	}
<>	156:95d6b41a828b	2472
<>	156:95d6b41a828b	2473	/**
<>	156:95d6b41a828b	2474	* @brief Set ADC group regular behavior in case of overrun:
<>	156:95d6b41a828b	2475	* data preserved or overwritten.
<>	156:95d6b41a828b	2476	* @note Compatibility with devices without feature overrun:
<>	156:95d6b41a828b	2477	* other devices without this feature have a behavior
<>	156:95d6b41a828b	2478	* equivalent to data overwritten.
<>	156:95d6b41a828b	2479	* The default setting of overrun is data preserved.
<>	156:95d6b41a828b	2480	* Therefore, for compatibility with all devices, parameter
<>	156:95d6b41a828b	2481	* overrun should be set to data overwritten.
<>	156:95d6b41a828b	2482	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2483	* ADC state:
<>	156:95d6b41a828b	2484	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2485	* on group regular.
<>	156:95d6b41a828b	2486	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun
<>	156:95d6b41a828b	2487	* @param ADCx ADC instance
<>	156:95d6b41a828b	2488	* @param Overrun This parameter can be one of the following values:
<>	156:95d6b41a828b	2489	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<>	156:95d6b41a828b	2490	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<>	156:95d6b41a828b	2491	* @retval None
<>	156:95d6b41a828b	2492	*/
<>	156:95d6b41a828b	2493	__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
<>	156:95d6b41a828b	2494	{
<>	156:95d6b41a828b	2495	MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
<>	156:95d6b41a828b	2496	}
<>	156:95d6b41a828b	2497
<>	156:95d6b41a828b	2498	/**
<>	156:95d6b41a828b	2499	* @brief Get ADC group regular behavior in case of overrun:
<>	156:95d6b41a828b	2500	* data preserved or overwritten.
<>	156:95d6b41a828b	2501	* @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun
<>	156:95d6b41a828b	2502	* @param ADCx ADC instance
<>	156:95d6b41a828b	2503	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2504	* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
<>	156:95d6b41a828b	2505	* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
<>	156:95d6b41a828b	2506	*/
<>	156:95d6b41a828b	2507	__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2508	{
<>	156:95d6b41a828b	2509	return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
<>	156:95d6b41a828b	2510	}
<>	156:95d6b41a828b	2511
<>	156:95d6b41a828b	2512	/**
<>	156:95d6b41a828b	2513	* @}
<>	156:95d6b41a828b	2514	*/
<>	156:95d6b41a828b	2515
<>	156:95d6b41a828b	2516
<>	156:95d6b41a828b	2517	/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
<>	156:95d6b41a828b	2518	* @{
<>	156:95d6b41a828b	2519	*/
<>	156:95d6b41a828b	2520
<>	156:95d6b41a828b	2521	/**
<>	156:95d6b41a828b	2522	* @brief Set ADC analog watchdog monitored channels:
<>	156:95d6b41a828b	2523	* a single channel or all channels,
<>	156:95d6b41a828b	2524	* on ADC group regular.
<>	156:95d6b41a828b	2525	* @note Once monitored channels are selected, analog watchdog
<>	156:95d6b41a828b	2526	* is enabled.
<>	156:95d6b41a828b	2527	* @note In case of need to define a single channel to monitor
<>	156:95d6b41a828b	2528	* with analog watchdog from sequencer channel definition,
<>	156:95d6b41a828b	2529	* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
<>	156:95d6b41a828b	2530	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	156:95d6b41a828b	2531	* instance:
<>	156:95d6b41a828b	2532	* - AWD standard (instance AWD1):
<>	156:95d6b41a828b	2533	* - channels monitored: can monitor 1 channel or all channels.
<>	156:95d6b41a828b	2534	* - groups monitored: ADC group regular.
<>	156:95d6b41a828b	2535	* - resolution: resolution is not limited (corresponds to
<>	156:95d6b41a828b	2536	* ADC resolution configured).
<>	156:95d6b41a828b	2537	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2538	* ADC state:
<>	156:95d6b41a828b	2539	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2540	* on group regular.
<>	156:95d6b41a828b	2541	* @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n
<>	156:95d6b41a828b	2542	* CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n
<>	156:95d6b41a828b	2543	* CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels
<>	156:95d6b41a828b	2544	* @param ADCx ADC instance
<>	156:95d6b41a828b	2545	* @param AWDChannelGroup This parameter can be one of the following values:
<>	156:95d6b41a828b	2546	* @arg @ref LL_ADC_AWD_DISABLE
<>	156:95d6b41a828b	2547	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	156:95d6b41a828b	2548	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	156:95d6b41a828b	2549	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	156:95d6b41a828b	2550	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	156:95d6b41a828b	2551	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	156:95d6b41a828b	2552	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	156:95d6b41a828b	2553	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	156:95d6b41a828b	2554	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	156:95d6b41a828b	2555	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	156:95d6b41a828b	2556	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	156:95d6b41a828b	2557	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	156:95d6b41a828b	2558	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	156:95d6b41a828b	2559	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	156:95d6b41a828b	2560	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	156:95d6b41a828b	2561	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	156:95d6b41a828b	2562	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	156:95d6b41a828b	2563	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	156:95d6b41a828b	2564	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	156:95d6b41a828b	2565	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	156:95d6b41a828b	2566	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1)
<>	156:95d6b41a828b	2567	* @arg @ref LL_ADC_AWD_CH_VREFINT_REG
<>	156:95d6b41a828b	2568	* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
<>	156:95d6b41a828b	2569	* @arg @ref LL_ADC_AWD_CH_VBAT_REG (1)
<>	156:95d6b41a828b	2570	*
<>	156:95d6b41a828b	2571	* (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB.
<>	156:95d6b41a828b	2572	* @retval None
<>	156:95d6b41a828b	2573	*/
<>	156:95d6b41a828b	2574	__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
<>	156:95d6b41a828b	2575	{
<>	156:95d6b41a828b	2576	MODIFY_REG(ADCx->CFGR1,
<>	156:95d6b41a828b	2577	(ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN),
<>	156:95d6b41a828b	2578	(AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK));
<>	156:95d6b41a828b	2579	}
<>	156:95d6b41a828b	2580
<>	156:95d6b41a828b	2581	/**
<>	156:95d6b41a828b	2582	* @brief Get ADC analog watchdog monitored channel.
<>	156:95d6b41a828b	2583	* @note Usage of the returned channel number:
<>	156:95d6b41a828b	2584	* - To reinject this channel into another function LL_ADC_xxx:
<>	156:95d6b41a828b	2585	* the returned channel number is only partly formatted on definition
<>	156:95d6b41a828b	2586	* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
<>	156:95d6b41a828b	2587	* with parts of literals LL_ADC_CHANNEL_x or using
<>	156:95d6b41a828b	2588	* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	156:95d6b41a828b	2589	* Then the selected literal LL_ADC_CHANNEL_x can be used
<>	156:95d6b41a828b	2590	* as parameter for another function.
<>	156:95d6b41a828b	2591	* - To get the channel number in decimal format:
<>	156:95d6b41a828b	2592	* process the returned value with the helper macro
<>	156:95d6b41a828b	2593	* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
<>	156:95d6b41a828b	2594	* Applicable only when the analog watchdog is set to monitor
<>	156:95d6b41a828b	2595	* one channel.
<>	156:95d6b41a828b	2596	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	156:95d6b41a828b	2597	* instance:
<>	156:95d6b41a828b	2598	* - AWD standard (instance AWD1):
<>	156:95d6b41a828b	2599	* - channels monitored: can monitor 1 channel or all channels.
<>	156:95d6b41a828b	2600	* - groups monitored: ADC group regular.
<>	156:95d6b41a828b	2601	* - resolution: resolution is not limited (corresponds to
<>	156:95d6b41a828b	2602	* ADC resolution configured).
<>	156:95d6b41a828b	2603	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2604	* ADC state:
<>	156:95d6b41a828b	2605	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2606	* on group regular.
<>	156:95d6b41a828b	2607	* @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n
<>	156:95d6b41a828b	2608	* CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n
<>	156:95d6b41a828b	2609	* CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels
<>	156:95d6b41a828b	2610	* @param ADCx ADC instance
<>	156:95d6b41a828b	2611	* @retval Returned value can be one of the following values:
<>	156:95d6b41a828b	2612	* @arg @ref LL_ADC_AWD_DISABLE
<>	156:95d6b41a828b	2613	* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
<>	156:95d6b41a828b	2614	* @arg @ref LL_ADC_AWD_CHANNEL_0_REG
<>	156:95d6b41a828b	2615	* @arg @ref LL_ADC_AWD_CHANNEL_1_REG
<>	156:95d6b41a828b	2616	* @arg @ref LL_ADC_AWD_CHANNEL_2_REG
<>	156:95d6b41a828b	2617	* @arg @ref LL_ADC_AWD_CHANNEL_3_REG
<>	156:95d6b41a828b	2618	* @arg @ref LL_ADC_AWD_CHANNEL_4_REG
<>	156:95d6b41a828b	2619	* @arg @ref LL_ADC_AWD_CHANNEL_5_REG
<>	156:95d6b41a828b	2620	* @arg @ref LL_ADC_AWD_CHANNEL_6_REG
<>	156:95d6b41a828b	2621	* @arg @ref LL_ADC_AWD_CHANNEL_7_REG
<>	156:95d6b41a828b	2622	* @arg @ref LL_ADC_AWD_CHANNEL_8_REG
<>	156:95d6b41a828b	2623	* @arg @ref LL_ADC_AWD_CHANNEL_9_REG
<>	156:95d6b41a828b	2624	* @arg @ref LL_ADC_AWD_CHANNEL_10_REG
<>	156:95d6b41a828b	2625	* @arg @ref LL_ADC_AWD_CHANNEL_11_REG
<>	156:95d6b41a828b	2626	* @arg @ref LL_ADC_AWD_CHANNEL_12_REG
<>	156:95d6b41a828b	2627	* @arg @ref LL_ADC_AWD_CHANNEL_13_REG
<>	156:95d6b41a828b	2628	* @arg @ref LL_ADC_AWD_CHANNEL_14_REG
<>	156:95d6b41a828b	2629	* @arg @ref LL_ADC_AWD_CHANNEL_15_REG
<>	156:95d6b41a828b	2630	* @arg @ref LL_ADC_AWD_CHANNEL_16_REG
<>	156:95d6b41a828b	2631	* @arg @ref LL_ADC_AWD_CHANNEL_17_REG
<>	156:95d6b41a828b	2632	* @arg @ref LL_ADC_AWD_CHANNEL_18_REG
<>	156:95d6b41a828b	2633	*/
<>	156:95d6b41a828b	2634	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2635	{
<>	156:95d6b41a828b	2636	register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH \| ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN));
<>	156:95d6b41a828b	2637
<>	156:95d6b41a828b	2638	/* Note: Set variable according to channel definition including channel ID */
<>	156:95d6b41a828b	2639	/* with bitfield. */
<>	156:95d6b41a828b	2640	register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS);
<>	156:95d6b41a828b	2641	register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS));
<>	156:95d6b41a828b	2642
<>	156:95d6b41a828b	2643	return (AWDChannelGroup \| (AWDChannelBitField * AWDChannelSingle));
<>	156:95d6b41a828b	2644	}
<>	156:95d6b41a828b	2645
<>	156:95d6b41a828b	2646	/**
<>	156:95d6b41a828b	2647	* @brief Set ADC analog watchdog thresholds value of both thresholds
<>	156:95d6b41a828b	2648	* high and low.
<>	156:95d6b41a828b	2649	* @note If value of only one threshold high or low must be set,
<>	156:95d6b41a828b	2650	* use function @ref LL_ADC_SetAnalogWDThresholds().
<>	156:95d6b41a828b	2651	* @note In case of ADC resolution different of 12 bits,
<>	156:95d6b41a828b	2652	* analog watchdog thresholds data require a specific shift.
<>	156:95d6b41a828b	2653	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	156:95d6b41a828b	2654	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	156:95d6b41a828b	2655	* instance:
<>	156:95d6b41a828b	2656	* - AWD standard (instance AWD1):
<>	156:95d6b41a828b	2657	* - channels monitored: can monitor 1 channel or all channels.
<>	156:95d6b41a828b	2658	* - groups monitored: ADC group regular.
<>	156:95d6b41a828b	2659	* - resolution: resolution is not limited (corresponds to
<>	156:95d6b41a828b	2660	* ADC resolution configured).
<>	156:95d6b41a828b	2661	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2662	* ADC state:
<>	156:95d6b41a828b	2663	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2664	* on group regular.
<>	156:95d6b41a828b	2665	* @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n
<>	156:95d6b41a828b	2666	* TR LT LL_ADC_ConfigAnalogWDThresholds
<>	156:95d6b41a828b	2667	* @param ADCx ADC instance
<>	156:95d6b41a828b	2668	* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	2669	* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	2670	* @retval None
<>	156:95d6b41a828b	2671	*/
<>	156:95d6b41a828b	2672	__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
<>	156:95d6b41a828b	2673	{
<>	156:95d6b41a828b	2674	MODIFY_REG(ADCx->TR,
<>	156:95d6b41a828b	2675	ADC_TR_HT \| ADC_TR_LT,
<>	156:95d6b41a828b	2676	(AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) \| AWDThresholdLowValue);
<>	156:95d6b41a828b	2677	}
<>	156:95d6b41a828b	2678
<>	156:95d6b41a828b	2679	/**
<>	156:95d6b41a828b	2680	* @brief Set ADC analog watchdog threshold value of threshold
<>	156:95d6b41a828b	2681	* high or low.
<>	156:95d6b41a828b	2682	* @note If values of both thresholds high or low must be set,
<>	156:95d6b41a828b	2683	* use function @ref LL_ADC_ConfigAnalogWDThresholds().
<>	156:95d6b41a828b	2684	* @note In case of ADC resolution different of 12 bits,
<>	156:95d6b41a828b	2685	* analog watchdog thresholds data require a specific shift.
<>	156:95d6b41a828b	2686	* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
<>	156:95d6b41a828b	2687	* @note On this STM32 serie, there is only 1 kind of analog watchdog
<>	156:95d6b41a828b	2688	* instance:
<>	156:95d6b41a828b	2689	* - AWD standard (instance AWD1):
<>	156:95d6b41a828b	2690	* - channels monitored: can monitor 1 channel or all channels.
<>	156:95d6b41a828b	2691	* - groups monitored: ADC group regular.
<>	156:95d6b41a828b	2692	* - resolution: resolution is not limited (corresponds to
<>	156:95d6b41a828b	2693	* ADC resolution configured).
<>	156:95d6b41a828b	2694	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2695	* ADC state:
<>	156:95d6b41a828b	2696	* ADC must be disabled or enabled without conversion on going
<>	156:95d6b41a828b	2697	* on group regular.
<>	156:95d6b41a828b	2698	* @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n
<>	156:95d6b41a828b	2699	* TR LT LL_ADC_SetAnalogWDThresholds
<>	156:95d6b41a828b	2700	* @param ADCx ADC instance
<>	156:95d6b41a828b	2701	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	156:95d6b41a828b	2702	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	156:95d6b41a828b	2703	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	156:95d6b41a828b	2704	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	2705	* @retval None
<>	156:95d6b41a828b	2706	*/
<>	156:95d6b41a828b	2707	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
<>	156:95d6b41a828b	2708	{
<>	156:95d6b41a828b	2709	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
<>	156:95d6b41a828b	2710	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
<>	156:95d6b41a828b	2711	/* high is selected, then data is shifted to LSB. Else(threshold low), */
<>	156:95d6b41a828b	2712	/* data is not shifted. */
<>	156:95d6b41a828b	2713	MODIFY_REG(ADCx->TR,
<>	156:95d6b41a828b	2714	AWDThresholdsHighLow,
<>	156:95d6b41a828b	2715	AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & ((uint32_t)0x00000010U)));
<>	156:95d6b41a828b	2716	}
<>	156:95d6b41a828b	2717
<>	156:95d6b41a828b	2718	/**
<>	156:95d6b41a828b	2719	* @brief Get ADC analog watchdog threshold value of threshold high,
<>	156:95d6b41a828b	2720	* threshold low or raw data with ADC thresholds high and low
<>	156:95d6b41a828b	2721	* concatenated.
<>	156:95d6b41a828b	2722	* @note If raw data with ADC thresholds high and low is retrieved,
<>	156:95d6b41a828b	2723	* the data of each threshold high or low can be isolated
<>	156:95d6b41a828b	2724	* using helper macro:
<>	156:95d6b41a828b	2725	* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
<>	156:95d6b41a828b	2726	* @note In case of ADC resolution different of 12 bits,
<>	156:95d6b41a828b	2727	* analog watchdog thresholds data require a specific shift.
<>	156:95d6b41a828b	2728	* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
<>	156:95d6b41a828b	2729	* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
<>	156:95d6b41a828b	2730	* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
<>	156:95d6b41a828b	2731	* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
<>	156:95d6b41a828b	2732	* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
<>	156:95d6b41a828b	2733	* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
<>	156:95d6b41a828b	2734	* TR3 LT3 LL_ADC_GetAnalogWDThresholds
<>	156:95d6b41a828b	2735	* @param ADCx ADC instance
<>	156:95d6b41a828b	2736	* @param AWDThresholdsHighLow This parameter can be one of the following values:
<>	156:95d6b41a828b	2737	* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
<>	156:95d6b41a828b	2738	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
<>	156:95d6b41a828b	2739	* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
<>	156:95d6b41a828b	2740	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	2741	*/
<>	156:95d6b41a828b	2742	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
<>	156:95d6b41a828b	2743	{
<>	156:95d6b41a828b	2744	/* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */
<>	156:95d6b41a828b	2745	/* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */
<>	156:95d6b41a828b	2746	/* high is selected, then data is shifted to LSB. Else(threshold low or */
<>	156:95d6b41a828b	2747	/* both thresholds), data is not shifted. */
<>	156:95d6b41a828b	2748	return (uint32_t)(READ_BIT(ADCx->TR,
<>	156:95d6b41a828b	2749	(AWDThresholdsHighLow \| ADC_TR_LT))
<>	156:95d6b41a828b	2750	>> ((~AWDThresholdsHighLow) & ((uint32_t)0x00000010U))
<>	156:95d6b41a828b	2751	);
<>	156:95d6b41a828b	2752	}
<>	156:95d6b41a828b	2753
<>	156:95d6b41a828b	2754	/**
<>	156:95d6b41a828b	2755	* @}
<>	156:95d6b41a828b	2756	*/
<>	156:95d6b41a828b	2757
<>	156:95d6b41a828b	2758	/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
<>	156:95d6b41a828b	2759	* @{
<>	156:95d6b41a828b	2760	*/
<>	156:95d6b41a828b	2761
<>	156:95d6b41a828b	2762	/**
<>	156:95d6b41a828b	2763	* @brief Enable the selected ADC instance.
<>	156:95d6b41a828b	2764	* @note On this STM32 serie, after ADC enable, a delay for
<>	156:95d6b41a828b	2765	* ADC internal analog stabilization is required before performing a
<>	156:95d6b41a828b	2766	* ADC conversion start.
<>	156:95d6b41a828b	2767	* Refer to device datasheet, parameter tSTAB.
<>	156:95d6b41a828b	2768	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	156:95d6b41a828b	2769	* is enabled and when conversion clock is active.
<>	156:95d6b41a828b	2770	* (not only core clock: this ADC has a dual clock domain)
<>	156:95d6b41a828b	2771	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2772	* ADC state:
<>	156:95d6b41a828b	2773	* ADC must be ADC disabled and ADC internal voltage regulator enabled.
<>	156:95d6b41a828b	2774	* @rmtoll CR ADEN LL_ADC_Enable
<>	156:95d6b41a828b	2775	* @param ADCx ADC instance
<>	156:95d6b41a828b	2776	* @retval None
<>	156:95d6b41a828b	2777	*/
<>	156:95d6b41a828b	2778	__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2779	{
<>	156:95d6b41a828b	2780	/* Note: Write register with some additional bits forced to state reset */
<>	156:95d6b41a828b	2781	/* instead of modifying only the selected bit for this function, */
<>	156:95d6b41a828b	2782	/* to not interfere with bits with HW property "rs". */
<>	156:95d6b41a828b	2783	MODIFY_REG(ADCx->CR,
<>	156:95d6b41a828b	2784	ADC_CR_BITS_PROPERTY_RS,
<>	156:95d6b41a828b	2785	ADC_CR_ADEN);
<>	156:95d6b41a828b	2786	}
<>	156:95d6b41a828b	2787
<>	156:95d6b41a828b	2788	/**
<>	156:95d6b41a828b	2789	* @brief Disable the selected ADC instance.
<>	156:95d6b41a828b	2790	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2791	* ADC state:
<>	156:95d6b41a828b	2792	* ADC must be not disabled. Must be enabled without conversion on going
<>	156:95d6b41a828b	2793	* on group regular.
<>	156:95d6b41a828b	2794	* @rmtoll CR ADDIS LL_ADC_Disable
<>	156:95d6b41a828b	2795	* @param ADCx ADC instance
<>	156:95d6b41a828b	2796	* @retval None
<>	156:95d6b41a828b	2797	*/
<>	156:95d6b41a828b	2798	__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2799	{
<>	156:95d6b41a828b	2800	/* Note: Write register with some additional bits forced to state reset */
<>	156:95d6b41a828b	2801	/* instead of modifying only the selected bit for this function, */
<>	156:95d6b41a828b	2802	/* to not interfere with bits with HW property "rs". */
<>	156:95d6b41a828b	2803	MODIFY_REG(ADCx->CR,
<>	156:95d6b41a828b	2804	ADC_CR_BITS_PROPERTY_RS,
<>	156:95d6b41a828b	2805	ADC_CR_ADDIS);
<>	156:95d6b41a828b	2806	}
<>	156:95d6b41a828b	2807
<>	156:95d6b41a828b	2808	/**
<>	156:95d6b41a828b	2809	* @brief Get the selected ADC instance enable state.
<>	156:95d6b41a828b	2810	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	156:95d6b41a828b	2811	* is enabled and when conversion clock is active.
<>	156:95d6b41a828b	2812	* (not only core clock: this ADC has a dual clock domain)
<>	156:95d6b41a828b	2813	* @rmtoll CR ADEN LL_ADC_IsEnabled
<>	156:95d6b41a828b	2814	* @param ADCx ADC instance
<>	156:95d6b41a828b	2815	* @retval 0: ADC is disabled, 1: ADC is enabled.
<>	156:95d6b41a828b	2816	*/
<>	156:95d6b41a828b	2817	__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2818	{
<>	156:95d6b41a828b	2819	return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN));
<>	156:95d6b41a828b	2820	}
<>	156:95d6b41a828b	2821
<>	156:95d6b41a828b	2822	/**
<>	156:95d6b41a828b	2823	* @brief Get the selected ADC instance disable state.
<>	156:95d6b41a828b	2824	* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
<>	156:95d6b41a828b	2825	* @param ADCx ADC instance
<>	156:95d6b41a828b	2826	* @retval 0: no ADC disable command on going.
<>	156:95d6b41a828b	2827	*/
<>	156:95d6b41a828b	2828	__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2829	{
<>	156:95d6b41a828b	2830	return (READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS));
<>	156:95d6b41a828b	2831	}
<>	156:95d6b41a828b	2832
<>	156:95d6b41a828b	2833	/**
<>	156:95d6b41a828b	2834	* @brief Start ADC calibration in the mode single-ended
<>	156:95d6b41a828b	2835	* or differential (for devices with differential mode available).
<>	156:95d6b41a828b	2836	* @note On this STM32 serie, a minimum number of ADC clock cycles
<>	156:95d6b41a828b	2837	* are required between ADC end of calibration and ADC enable.
<>	156:95d6b41a828b	2838	* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
<>	156:95d6b41a828b	2839	* @note In case of usage of ADC with DMA transfer:
<>	156:95d6b41a828b	2840	* On this STM32 serie, ADC DMA transfer request should be disabled
<>	156:95d6b41a828b	2841	* during calibration:
<>	156:95d6b41a828b	2842	* Calibration factor is available in data register
<>	156:95d6b41a828b	2843	* and also transfered by DMA.
<>	156:95d6b41a828b	2844	* To not insert ADC calibration factor among ADC conversion data
<>	156:95d6b41a828b	2845	* in array variable, DMA transfer must be disabled during
<>	156:95d6b41a828b	2846	* calibration.
<>	156:95d6b41a828b	2847	* (DMA transfer setting backup and disable before calibration,
<>	156:95d6b41a828b	2848	* DMA transfer setting restore after calibration.
<>	156:95d6b41a828b	2849	* Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
<>	156:95d6b41a828b	2850	* @ref LL_ADC_REG_SetDMATransfer() ).
<>	156:95d6b41a828b	2851	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2852	* ADC state:
<>	156:95d6b41a828b	2853	* ADC must be ADC disabled.
<>	156:95d6b41a828b	2854	* @rmtoll CR ADCAL LL_ADC_StartCalibration
<>	156:95d6b41a828b	2855	* @param ADCx ADC instance
<>	156:95d6b41a828b	2856	* @retval None
<>	156:95d6b41a828b	2857	*/
<>	156:95d6b41a828b	2858	__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2859	{
<>	156:95d6b41a828b	2860	/* Note: Write register with some additional bits forced to state reset */
<>	156:95d6b41a828b	2861	/* instead of modifying only the selected bit for this function, */
<>	156:95d6b41a828b	2862	/* to not interfere with bits with HW property "rs". */
<>	156:95d6b41a828b	2863	MODIFY_REG(ADCx->CR,
<>	156:95d6b41a828b	2864	ADC_CR_BITS_PROPERTY_RS,
<>	156:95d6b41a828b	2865	ADC_CR_ADCAL);
<>	156:95d6b41a828b	2866	}
<>	156:95d6b41a828b	2867
<>	156:95d6b41a828b	2868	/**
<>	156:95d6b41a828b	2869	* @brief Get ADC calibration state.
<>	156:95d6b41a828b	2870	* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
<>	156:95d6b41a828b	2871	* @param ADCx ADC instance
<>	156:95d6b41a828b	2872	* @retval 0: calibration complete, 1: calibration in progress.
<>	156:95d6b41a828b	2873	*/
<>	156:95d6b41a828b	2874	__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2875	{
<>	156:95d6b41a828b	2876	return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL));
<>	156:95d6b41a828b	2877	}
<>	156:95d6b41a828b	2878
<>	156:95d6b41a828b	2879	/**
<>	156:95d6b41a828b	2880	* @}
<>	156:95d6b41a828b	2881	*/
<>	156:95d6b41a828b	2882
<>	156:95d6b41a828b	2883	/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
<>	156:95d6b41a828b	2884	* @{
<>	156:95d6b41a828b	2885	*/
<>	156:95d6b41a828b	2886
<>	156:95d6b41a828b	2887	/**
<>	156:95d6b41a828b	2888	* @brief Start ADC group regular conversion.
<>	156:95d6b41a828b	2889	* @note On this STM32 serie, this function is relevant for both
<>	156:95d6b41a828b	2890	* internal trigger (SW start) and external trigger:
<>	156:95d6b41a828b	2891	* - If ADC trigger has been set to software start, ADC conversion
<>	156:95d6b41a828b	2892	* starts immediately.
<>	156:95d6b41a828b	2893	* - If ADC trigger has been set to external trigger, ADC conversion
<>	156:95d6b41a828b	2894	* will start at next trigger event (on the selected trigger edge)
<>	156:95d6b41a828b	2895	* following the ADC start conversion command.
<>	156:95d6b41a828b	2896	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2897	* ADC state:
<>	156:95d6b41a828b	2898	* ADC must be enabled without conversion on going on group regular,
<>	156:95d6b41a828b	2899	* without conversion stop command on going on group regular.
<>	156:95d6b41a828b	2900	* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
<>	156:95d6b41a828b	2901	* @param ADCx ADC instance
<>	156:95d6b41a828b	2902	* @retval None
<>	156:95d6b41a828b	2903	*/
<>	156:95d6b41a828b	2904	__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2905	{
<>	156:95d6b41a828b	2906	/* Note: Write register with some additional bits forced to state reset */
<>	156:95d6b41a828b	2907	/* instead of modifying only the selected bit for this function, */
<>	156:95d6b41a828b	2908	/* to not interfere with bits with HW property "rs". */
<>	156:95d6b41a828b	2909	MODIFY_REG(ADCx->CR,
<>	156:95d6b41a828b	2910	ADC_CR_BITS_PROPERTY_RS,
<>	156:95d6b41a828b	2911	ADC_CR_ADSTART);
<>	156:95d6b41a828b	2912	}
<>	156:95d6b41a828b	2913
<>	156:95d6b41a828b	2914	/**
<>	156:95d6b41a828b	2915	* @brief Stop ADC group regular conversion.
<>	156:95d6b41a828b	2916	* @note On this STM32 serie, setting of this feature is conditioned to
<>	156:95d6b41a828b	2917	* ADC state:
<>	156:95d6b41a828b	2918	* ADC must be enabled with conversion on going on group regular,
<>	156:95d6b41a828b	2919	* without ADC disable command on going.
<>	156:95d6b41a828b	2920	* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
<>	156:95d6b41a828b	2921	* @param ADCx ADC instance
<>	156:95d6b41a828b	2922	* @retval None
<>	156:95d6b41a828b	2923	*/
<>	156:95d6b41a828b	2924	__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2925	{
<>	156:95d6b41a828b	2926	/* Note: Write register with some additional bits forced to state reset */
<>	156:95d6b41a828b	2927	/* instead of modifying only the selected bit for this function, */
<>	156:95d6b41a828b	2928	/* to not interfere with bits with HW property "rs". */
<>	156:95d6b41a828b	2929	MODIFY_REG(ADCx->CR,
<>	156:95d6b41a828b	2930	ADC_CR_BITS_PROPERTY_RS,
<>	156:95d6b41a828b	2931	ADC_CR_ADSTP);
<>	156:95d6b41a828b	2932	}
<>	156:95d6b41a828b	2933
<>	156:95d6b41a828b	2934	/**
<>	156:95d6b41a828b	2935	* @brief Get ADC group regular conversion state.
<>	156:95d6b41a828b	2936	* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
<>	156:95d6b41a828b	2937	* @param ADCx ADC instance
<>	156:95d6b41a828b	2938	* @retval 0: no conversion is on going on ADC group regular.
<>	156:95d6b41a828b	2939	*/
<>	156:95d6b41a828b	2940	__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2941	{
<>	156:95d6b41a828b	2942	return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART));
<>	156:95d6b41a828b	2943	}
<>	156:95d6b41a828b	2944
<>	156:95d6b41a828b	2945	/**
<>	156:95d6b41a828b	2946	* @brief Get ADC group regular command of conversion stop state
<>	156:95d6b41a828b	2947	* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
<>	156:95d6b41a828b	2948	* @param ADCx ADC instance
<>	156:95d6b41a828b	2949	* @retval 0: no command of conversion stop is on going on ADC group regular.
<>	156:95d6b41a828b	2950	*/
<>	156:95d6b41a828b	2951	__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2952	{
<>	156:95d6b41a828b	2953	return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP));
<>	156:95d6b41a828b	2954	}
<>	156:95d6b41a828b	2955
<>	156:95d6b41a828b	2956	/**
<>	156:95d6b41a828b	2957	* @brief Get ADC group regular conversion data, range fit for
<>	156:95d6b41a828b	2958	* all ADC configurations: all ADC resolutions and
<>	156:95d6b41a828b	2959	* all oversampling increased data width (for devices
<>	156:95d6b41a828b	2960	* with feature oversampling).
<>	156:95d6b41a828b	2961	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData32
<>	156:95d6b41a828b	2962	* @param ADCx ADC instance
<>	156:95d6b41a828b	2963	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
<>	156:95d6b41a828b	2964	*/
<>	156:95d6b41a828b	2965	__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2966	{
<>	156:95d6b41a828b	2967	return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	156:95d6b41a828b	2968	}
<>	156:95d6b41a828b	2969
<>	156:95d6b41a828b	2970	/**
<>	156:95d6b41a828b	2971	* @brief Get ADC group regular conversion data, range fit for
<>	156:95d6b41a828b	2972	* ADC resolution 12 bits.
<>	156:95d6b41a828b	2973	* @note For devices with feature oversampling: Oversampling
<>	156:95d6b41a828b	2974	* can increase data width, function for extended range
<>	156:95d6b41a828b	2975	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	156:95d6b41a828b	2976	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData12
<>	156:95d6b41a828b	2977	* @param ADCx ADC instance
<>	156:95d6b41a828b	2978	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
<>	156:95d6b41a828b	2979	*/
<>	156:95d6b41a828b	2980	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2981	{
<>	156:95d6b41a828b	2982	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	156:95d6b41a828b	2983	}
<>	156:95d6b41a828b	2984
<>	156:95d6b41a828b	2985	/**
<>	156:95d6b41a828b	2986	* @brief Get ADC group regular conversion data, range fit for
<>	156:95d6b41a828b	2987	* ADC resolution 10 bits.
<>	156:95d6b41a828b	2988	* @note For devices with feature oversampling: Oversampling
<>	156:95d6b41a828b	2989	* can increase data width, function for extended range
<>	156:95d6b41a828b	2990	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	156:95d6b41a828b	2991	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData10
<>	156:95d6b41a828b	2992	* @param ADCx ADC instance
<>	156:95d6b41a828b	2993	* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
<>	156:95d6b41a828b	2994	*/
<>	156:95d6b41a828b	2995	__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	2996	{
<>	156:95d6b41a828b	2997	return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	156:95d6b41a828b	2998	}
<>	156:95d6b41a828b	2999
<>	156:95d6b41a828b	3000	/**
<>	156:95d6b41a828b	3001	* @brief Get ADC group regular conversion data, range fit for
<>	156:95d6b41a828b	3002	* ADC resolution 8 bits.
<>	156:95d6b41a828b	3003	* @note For devices with feature oversampling: Oversampling
<>	156:95d6b41a828b	3004	* can increase data width, function for extended range
<>	156:95d6b41a828b	3005	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	156:95d6b41a828b	3006	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData8
<>	156:95d6b41a828b	3007	* @param ADCx ADC instance
<>	156:95d6b41a828b	3008	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
<>	156:95d6b41a828b	3009	*/
<>	156:95d6b41a828b	3010	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3011	{
<>	156:95d6b41a828b	3012	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	156:95d6b41a828b	3013	}
<>	156:95d6b41a828b	3014
<>	156:95d6b41a828b	3015	/**
<>	156:95d6b41a828b	3016	* @brief Get ADC group regular conversion data, range fit for
<>	156:95d6b41a828b	3017	* ADC resolution 6 bits.
<>	156:95d6b41a828b	3018	* @note For devices with feature oversampling: Oversampling
<>	156:95d6b41a828b	3019	* can increase data width, function for extended range
<>	156:95d6b41a828b	3020	* may be needed: @ref LL_ADC_REG_ReadConversionData32.
<>	156:95d6b41a828b	3021	* @rmtoll DR DATA LL_ADC_REG_ReadConversionData6
<>	156:95d6b41a828b	3022	* @param ADCx ADC instance
<>	156:95d6b41a828b	3023	* @retval Value between Min_Data=0x00 and Max_Data=0x3F
<>	156:95d6b41a828b	3024	*/
<>	156:95d6b41a828b	3025	__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3026	{
<>	156:95d6b41a828b	3027	return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
<>	156:95d6b41a828b	3028	}
<>	156:95d6b41a828b	3029
<>	156:95d6b41a828b	3030	/**
<>	156:95d6b41a828b	3031	* @}
<>	156:95d6b41a828b	3032	*/
<>	156:95d6b41a828b	3033
<>	156:95d6b41a828b	3034	/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
<>	156:95d6b41a828b	3035	* @{
<>	156:95d6b41a828b	3036	*/
<>	156:95d6b41a828b	3037
<>	156:95d6b41a828b	3038	/**
<>	156:95d6b41a828b	3039	* @brief Get flag ADC ready.
<>	156:95d6b41a828b	3040	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	156:95d6b41a828b	3041	* is enabled and when conversion clock is active.
<>	156:95d6b41a828b	3042	* (not only core clock: this ADC has a dual clock domain)
<>	156:95d6b41a828b	3043	* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
<>	156:95d6b41a828b	3044	* @param ADCx ADC instance
<>	156:95d6b41a828b	3045	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3046	*/
<>	156:95d6b41a828b	3047	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3048	{
<>	156:95d6b41a828b	3049	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY));
<>	156:95d6b41a828b	3050	}
<>	156:95d6b41a828b	3051
<>	156:95d6b41a828b	3052	/**
<>	156:95d6b41a828b	3053	* @brief Get flag ADC group regular end of unitary conversion.
<>	156:95d6b41a828b	3054	* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
<>	156:95d6b41a828b	3055	* @param ADCx ADC instance
<>	156:95d6b41a828b	3056	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3057	*/
<>	156:95d6b41a828b	3058	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3059	{
<>	156:95d6b41a828b	3060	return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC));
<>	156:95d6b41a828b	3061	}
<>	156:95d6b41a828b	3062
<>	156:95d6b41a828b	3063	/**
<>	156:95d6b41a828b	3064	* @brief Get flag ADC group regular end of sequence conversions.
<>	156:95d6b41a828b	3065	* @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS
<>	156:95d6b41a828b	3066	* @param ADCx ADC instance
<>	156:95d6b41a828b	3067	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3068	*/
<>	156:95d6b41a828b	3069	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3070	{
<>	156:95d6b41a828b	3071	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
<>	156:95d6b41a828b	3072	}
<>	156:95d6b41a828b	3073
<>	156:95d6b41a828b	3074	/**
<>	156:95d6b41a828b	3075	* @brief Get flag ADC group regular overrun.
<>	156:95d6b41a828b	3076	* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
<>	156:95d6b41a828b	3077	* @param ADCx ADC instance
<>	156:95d6b41a828b	3078	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3079	*/
<>	156:95d6b41a828b	3080	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3081	{
<>	156:95d6b41a828b	3082	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
<>	156:95d6b41a828b	3083	}
<>	156:95d6b41a828b	3084
<>	156:95d6b41a828b	3085	/**
<>	156:95d6b41a828b	3086	* @brief Get flag ADC group regular end of sampling phase.
<>	156:95d6b41a828b	3087	* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
<>	156:95d6b41a828b	3088	* @param ADCx ADC instance
<>	156:95d6b41a828b	3089	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3090	*/
<>	156:95d6b41a828b	3091	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3092	{
<>	156:95d6b41a828b	3093	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP));
<>	156:95d6b41a828b	3094	}
<>	156:95d6b41a828b	3095
<>	156:95d6b41a828b	3096	/**
<>	156:95d6b41a828b	3097	* @brief Get flag ADC analog watchdog 1 flag
<>	156:95d6b41a828b	3098	* @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD1
<>	156:95d6b41a828b	3099	* @param ADCx ADC instance
<>	156:95d6b41a828b	3100	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3101	*/
<>	156:95d6b41a828b	3102	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3103	{
<>	156:95d6b41a828b	3104	return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
<>	156:95d6b41a828b	3105	}
<>	156:95d6b41a828b	3106
<>	156:95d6b41a828b	3107	/**
<>	156:95d6b41a828b	3108	* @brief Clear flag ADC ready.
<>	156:95d6b41a828b	3109	* @note On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC
<>	156:95d6b41a828b	3110	* is enabled and when conversion clock is active.
<>	156:95d6b41a828b	3111	* (not only core clock: this ADC has a dual clock domain)
<>	156:95d6b41a828b	3112	* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
<>	156:95d6b41a828b	3113	* @param ADCx ADC instance
<>	156:95d6b41a828b	3114	* @retval None
<>	156:95d6b41a828b	3115	*/
<>	156:95d6b41a828b	3116	__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3117	{
<>	156:95d6b41a828b	3118	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
<>	156:95d6b41a828b	3119	}
<>	156:95d6b41a828b	3120
<>	156:95d6b41a828b	3121	/**
<>	156:95d6b41a828b	3122	* @brief Clear flag ADC group regular end of unitary conversion.
<>	156:95d6b41a828b	3123	* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
<>	156:95d6b41a828b	3124	* @param ADCx ADC instance
<>	156:95d6b41a828b	3125	* @retval None
<>	156:95d6b41a828b	3126	*/
<>	156:95d6b41a828b	3127	__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3128	{
<>	156:95d6b41a828b	3129	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
<>	156:95d6b41a828b	3130	}
<>	156:95d6b41a828b	3131
<>	156:95d6b41a828b	3132	/**
<>	156:95d6b41a828b	3133	* @brief Clear flag ADC group regular end of sequence conversions.
<>	156:95d6b41a828b	3134	* @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS
<>	156:95d6b41a828b	3135	* @param ADCx ADC instance
<>	156:95d6b41a828b	3136	* @retval None
<>	156:95d6b41a828b	3137	*/
<>	156:95d6b41a828b	3138	__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3139	{
<>	156:95d6b41a828b	3140	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
<>	156:95d6b41a828b	3141	}
<>	156:95d6b41a828b	3142
<>	156:95d6b41a828b	3143	/**
<>	156:95d6b41a828b	3144	* @brief Clear flag ADC group regular overrun.
<>	156:95d6b41a828b	3145	* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
<>	156:95d6b41a828b	3146	* @param ADCx ADC instance
<>	156:95d6b41a828b	3147	* @retval None
<>	156:95d6b41a828b	3148	*/
<>	156:95d6b41a828b	3149	__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3150	{
<>	156:95d6b41a828b	3151	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
<>	156:95d6b41a828b	3152	}
<>	156:95d6b41a828b	3153
<>	156:95d6b41a828b	3154	/**
<>	156:95d6b41a828b	3155	* @brief Clear flag ADC group regular end of sampling phase.
<>	156:95d6b41a828b	3156	* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
<>	156:95d6b41a828b	3157	* @param ADCx ADC instance
<>	156:95d6b41a828b	3158	* @retval None
<>	156:95d6b41a828b	3159	*/
<>	156:95d6b41a828b	3160	__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3161	{
<>	156:95d6b41a828b	3162	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
<>	156:95d6b41a828b	3163	}
<>	156:95d6b41a828b	3164
<>	156:95d6b41a828b	3165	/**
<>	156:95d6b41a828b	3166	* @brief Clear flag ADC analog watchdog 1.
<>	156:95d6b41a828b	3167	* @rmtoll ISR AWD LL_ADC_ClearFlag_AWD1
<>	156:95d6b41a828b	3168	* @param ADCx ADC instance
<>	156:95d6b41a828b	3169	* @retval None
<>	156:95d6b41a828b	3170	*/
<>	156:95d6b41a828b	3171	__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3172	{
<>	156:95d6b41a828b	3173	WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
<>	156:95d6b41a828b	3174	}
<>	156:95d6b41a828b	3175
<>	156:95d6b41a828b	3176	/**
<>	156:95d6b41a828b	3177	* @}
<>	156:95d6b41a828b	3178	*/
<>	156:95d6b41a828b	3179
<>	156:95d6b41a828b	3180	/** @defgroup ADC_LL_EF_IT_Management ADC IT management
<>	156:95d6b41a828b	3181	* @{
<>	156:95d6b41a828b	3182	*/
<>	156:95d6b41a828b	3183
<>	156:95d6b41a828b	3184	/**
<>	156:95d6b41a828b	3185	* @brief Enable ADC ready.
<>	156:95d6b41a828b	3186	* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
<>	156:95d6b41a828b	3187	* @param ADCx ADC instance
<>	156:95d6b41a828b	3188	* @retval None
<>	156:95d6b41a828b	3189	*/
<>	156:95d6b41a828b	3190	__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3191	{
<>	156:95d6b41a828b	3192	SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<>	156:95d6b41a828b	3193	}
<>	156:95d6b41a828b	3194
<>	156:95d6b41a828b	3195	/**
<>	156:95d6b41a828b	3196	* @brief Enable interruption ADC group regular end of unitary conversion.
<>	156:95d6b41a828b	3197	* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
<>	156:95d6b41a828b	3198	* @param ADCx ADC instance
<>	156:95d6b41a828b	3199	* @retval None
<>	156:95d6b41a828b	3200	*/
<>	156:95d6b41a828b	3201	__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3202	{
<>	156:95d6b41a828b	3203	SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
<>	156:95d6b41a828b	3204	}
<>	156:95d6b41a828b	3205
<>	156:95d6b41a828b	3206	/**
<>	156:95d6b41a828b	3207	* @brief Enable interruption ADC group regular end of sequence conversions.
<>	156:95d6b41a828b	3208	* @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS
<>	156:95d6b41a828b	3209	* @param ADCx ADC instance
<>	156:95d6b41a828b	3210	* @retval None
<>	156:95d6b41a828b	3211	*/
<>	156:95d6b41a828b	3212	__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3213	{
<>	156:95d6b41a828b	3214	SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
<>	156:95d6b41a828b	3215	}
<>	156:95d6b41a828b	3216
<>	156:95d6b41a828b	3217	/**
<>	156:95d6b41a828b	3218	* @brief Enable ADC group regular interruption overrun.
<>	156:95d6b41a828b	3219	* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
<>	156:95d6b41a828b	3220	* @param ADCx ADC instance
<>	156:95d6b41a828b	3221	* @retval None
<>	156:95d6b41a828b	3222	*/
<>	156:95d6b41a828b	3223	__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3224	{
<>	156:95d6b41a828b	3225	SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
<>	156:95d6b41a828b	3226	}
<>	156:95d6b41a828b	3227
<>	156:95d6b41a828b	3228	/**
<>	156:95d6b41a828b	3229	* @brief Enable interruption ADC group regular end of sampling.
<>	156:95d6b41a828b	3230	* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
<>	156:95d6b41a828b	3231	* @param ADCx ADC instance
<>	156:95d6b41a828b	3232	* @retval None
<>	156:95d6b41a828b	3233	*/
<>	156:95d6b41a828b	3234	__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3235	{
<>	156:95d6b41a828b	3236	SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<>	156:95d6b41a828b	3237	}
<>	156:95d6b41a828b	3238
<>	156:95d6b41a828b	3239	/**
<>	156:95d6b41a828b	3240	* @brief Enable interruption ADC analog watchdog 1.
<>	156:95d6b41a828b	3241	* @rmtoll IER AWDIE LL_ADC_EnableIT_AWD1
<>	156:95d6b41a828b	3242	* @param ADCx ADC instance
<>	156:95d6b41a828b	3243	* @retval None
<>	156:95d6b41a828b	3244	*/
<>	156:95d6b41a828b	3245	__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3246	{
<>	156:95d6b41a828b	3247	SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<>	156:95d6b41a828b	3248	}
<>	156:95d6b41a828b	3249
<>	156:95d6b41a828b	3250	/**
<>	156:95d6b41a828b	3251	* @brief Disable interruption ADC ready.
<>	156:95d6b41a828b	3252	* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
<>	156:95d6b41a828b	3253	* @param ADCx ADC instance
<>	156:95d6b41a828b	3254	* @retval None
<>	156:95d6b41a828b	3255	*/
<>	156:95d6b41a828b	3256	__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3257	{
<>	156:95d6b41a828b	3258	CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
<>	156:95d6b41a828b	3259	}
<>	156:95d6b41a828b	3260
<>	156:95d6b41a828b	3261	/**
<>	156:95d6b41a828b	3262	* @brief Disable interruption ADC group regular end of unitary conversion.
<>	156:95d6b41a828b	3263	* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
<>	156:95d6b41a828b	3264	* @param ADCx ADC instance
<>	156:95d6b41a828b	3265	* @retval None
<>	156:95d6b41a828b	3266	*/
<>	156:95d6b41a828b	3267	__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3268	{
<>	156:95d6b41a828b	3269	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
<>	156:95d6b41a828b	3270	}
<>	156:95d6b41a828b	3271
<>	156:95d6b41a828b	3272	/**
<>	156:95d6b41a828b	3273	* @brief Disable interruption ADC group regular end of sequence conversions.
<>	156:95d6b41a828b	3274	* @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS
<>	156:95d6b41a828b	3275	* @param ADCx ADC instance
<>	156:95d6b41a828b	3276	* @retval None
<>	156:95d6b41a828b	3277	*/
<>	156:95d6b41a828b	3278	__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3279	{
<>	156:95d6b41a828b	3280	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
<>	156:95d6b41a828b	3281	}
<>	156:95d6b41a828b	3282
<>	156:95d6b41a828b	3283	/**
<>	156:95d6b41a828b	3284	* @brief Disable interruption ADC group regular overrun.
<>	156:95d6b41a828b	3285	* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
<>	156:95d6b41a828b	3286	* @param ADCx ADC instance
<>	156:95d6b41a828b	3287	* @retval None
<>	156:95d6b41a828b	3288	*/
<>	156:95d6b41a828b	3289	__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3290	{
<>	156:95d6b41a828b	3291	CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
<>	156:95d6b41a828b	3292	}
<>	156:95d6b41a828b	3293
<>	156:95d6b41a828b	3294	/**
<>	156:95d6b41a828b	3295	* @brief Disable interruption ADC group regular end of sampling.
<>	156:95d6b41a828b	3296	* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
<>	156:95d6b41a828b	3297	* @param ADCx ADC instance
<>	156:95d6b41a828b	3298	* @retval None
<>	156:95d6b41a828b	3299	*/
<>	156:95d6b41a828b	3300	__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3301	{
<>	156:95d6b41a828b	3302	CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
<>	156:95d6b41a828b	3303	}
<>	156:95d6b41a828b	3304
<>	156:95d6b41a828b	3305	/**
<>	156:95d6b41a828b	3306	* @brief Disable interruption ADC analog watchdog 1.
<>	156:95d6b41a828b	3307	* @rmtoll IER AWDIE LL_ADC_DisableIT_AWD1
<>	156:95d6b41a828b	3308	* @param ADCx ADC instance
<>	156:95d6b41a828b	3309	* @retval None
<>	156:95d6b41a828b	3310	*/
<>	156:95d6b41a828b	3311	__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3312	{
<>	156:95d6b41a828b	3313	CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
<>	156:95d6b41a828b	3314	}
<>	156:95d6b41a828b	3315
<>	156:95d6b41a828b	3316	/**
<>	156:95d6b41a828b	3317	* @brief Get state of interruption ADC ready
<>	156:95d6b41a828b	3318	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3319	* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
<>	156:95d6b41a828b	3320	* @param ADCx ADC instance
<>	156:95d6b41a828b	3321	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3322	*/
<>	156:95d6b41a828b	3323	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3324	{
<>	156:95d6b41a828b	3325	return (READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY));
<>	156:95d6b41a828b	3326	}
<>	156:95d6b41a828b	3327
<>	156:95d6b41a828b	3328	/**
<>	156:95d6b41a828b	3329	* @brief Get state of interruption ADC group regular end of unitary conversion
<>	156:95d6b41a828b	3330	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3331	* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
<>	156:95d6b41a828b	3332	* @param ADCx ADC instance
<>	156:95d6b41a828b	3333	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3334	*/
<>	156:95d6b41a828b	3335	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3336	{
<>	156:95d6b41a828b	3337	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC));
<>	156:95d6b41a828b	3338	}
<>	156:95d6b41a828b	3339
<>	156:95d6b41a828b	3340	/**
<>	156:95d6b41a828b	3341	* @brief Get state of interruption ADC group regular end of sequence conversions
<>	156:95d6b41a828b	3342	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3343	* @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS
<>	156:95d6b41a828b	3344	* @param ADCx ADC instance
<>	156:95d6b41a828b	3345	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3346	*/
<>	156:95d6b41a828b	3347	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3348	{
<>	156:95d6b41a828b	3349	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
<>	156:95d6b41a828b	3350	}
<>	156:95d6b41a828b	3351
<>	156:95d6b41a828b	3352	/**
<>	156:95d6b41a828b	3353	* @brief Get state of interruption ADC group regular overrun
<>	156:95d6b41a828b	3354	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3355	* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
<>	156:95d6b41a828b	3356	* @param ADCx ADC instance
<>	156:95d6b41a828b	3357	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3358	*/
<>	156:95d6b41a828b	3359	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3360	{
<>	156:95d6b41a828b	3361	return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
<>	156:95d6b41a828b	3362	}
<>	156:95d6b41a828b	3363
<>	156:95d6b41a828b	3364	/**
<>	156:95d6b41a828b	3365	* @brief Get state of interruption ADC group regular end of sampling
<>	156:95d6b41a828b	3366	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3367	* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
<>	156:95d6b41a828b	3368	* @param ADCx ADC instance
<>	156:95d6b41a828b	3369	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3370	*/
<>	156:95d6b41a828b	3371	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3372	{
<>	156:95d6b41a828b	3373	return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP));
<>	156:95d6b41a828b	3374	}
<>	156:95d6b41a828b	3375
<>	156:95d6b41a828b	3376	/**
<>	156:95d6b41a828b	3377	* @brief Get state of interruption ADC analog watchdog 1
<>	156:95d6b41a828b	3378	* (0: interrupt disabled, 1: interrupt enabled).
<>	156:95d6b41a828b	3379	* @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD1
<>	156:95d6b41a828b	3380	* @param ADCx ADC instance
<>	156:95d6b41a828b	3381	* @retval State of bit (1 or 0).
<>	156:95d6b41a828b	3382	*/
<>	156:95d6b41a828b	3383	__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
<>	156:95d6b41a828b	3384	{
<>	156:95d6b41a828b	3385	return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
<>	156:95d6b41a828b	3386	}
<>	156:95d6b41a828b	3387
<>	156:95d6b41a828b	3388	/**
<>	156:95d6b41a828b	3389	* @}
<>	156:95d6b41a828b	3390	*/
<>	156:95d6b41a828b	3391
<>	156:95d6b41a828b	3392	#if defined(USE_FULL_LL_DRIVER)
<>	156:95d6b41a828b	3393	/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
<>	156:95d6b41a828b	3394	* @{
<>	156:95d6b41a828b	3395	*/
<>	156:95d6b41a828b	3396
<>	156:95d6b41a828b	3397	/* Initialization of some features of ADC common parameters and multimode */
<>	156:95d6b41a828b	3398	/* Note: On this STM32 serie, there is no ADC common initialization */
<>	156:95d6b41a828b	3399	/* function. */
<>	156:95d6b41a828b	3400	ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
<>	156:95d6b41a828b	3401
<>	156:95d6b41a828b	3402	/* De-initialization of ADC instance */
<>	156:95d6b41a828b	3403	ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
<>	156:95d6b41a828b	3404
<>	156:95d6b41a828b	3405	/* Initialization of some features of ADC instance */
<>	156:95d6b41a828b	3406	ErrorStatus LL_ADC_Init(ADC_TypeDef ADCx, LL_ADC_InitTypeDef ADC_InitStruct);
<>	156:95d6b41a828b	3407	void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
<>	156:95d6b41a828b	3408
<>	156:95d6b41a828b	3409	/* Initialization of some features of ADC instance and ADC group regular */
<>	156:95d6b41a828b	3410	ErrorStatus LL_ADC_REG_Init(ADC_TypeDef ADCx, LL_ADC_REG_InitTypeDef ADC_REG_InitStruct);
<>	156:95d6b41a828b	3411	void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
<>	156:95d6b41a828b	3412
<>	156:95d6b41a828b	3413	/**
<>	156:95d6b41a828b	3414	* @}
<>	156:95d6b41a828b	3415	*/
<>	156:95d6b41a828b	3416	#endif /* USE_FULL_LL_DRIVER */
<>	156:95d6b41a828b	3417
<>	156:95d6b41a828b	3418	/**
<>	156:95d6b41a828b	3419	* @}
<>	156:95d6b41a828b	3420	*/
<>	156:95d6b41a828b	3421
<>	156:95d6b41a828b	3422	/**
<>	156:95d6b41a828b	3423	* @}
<>	156:95d6b41a828b	3424	*/
<>	156:95d6b41a828b	3425
<>	156:95d6b41a828b	3426	#endif /* ADC1 */
<>	156:95d6b41a828b	3427
<>	156:95d6b41a828b	3428	/**
<>	156:95d6b41a828b	3429	* @}
<>	156:95d6b41a828b	3430	*/
<>	156:95d6b41a828b	3431
<>	156:95d6b41a828b	3432	#ifdef __cplusplus
<>	156:95d6b41a828b	3433	}
<>	156:95d6b41a828b	3434	#endif
<>	156:95d6b41a828b	3435
<>	156:95d6b41a828b	3436	#endif /* __STM32F0xx_LL_ADC_H */
<>	156:95d6b41a828b	3437
<>	156:95d6b41a828b	3438	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/