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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_tim_ex.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer Extended peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 * + Timer remapping capabilities configuration
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..]
<> 144:ef7eb2e8f9f7 20 The Timer Extended features include:
<> 144:ef7eb2e8f9f7 21 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 22 (++) Output Compare
<> 144:ef7eb2e8f9f7 23 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 26 interconnect several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 28 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 29 positioning purposes
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 32 ==============================================================================
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 35 depending from feature used :
<> 144:ef7eb2e8f9f7 36 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 38 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 39 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 42 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 43 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 44 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 45 __HAL_RCC_GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 49 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 50 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 51 any start function.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 54 initialization function of this driver:
<> 144:ef7eb2e8f9f7 55 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 56 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 57 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 58 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 59 the commutation event).
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 62 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 65 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 * @attention
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 75 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 76 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 80 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 82 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 83 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 107 * @brief TIM Extended HAL module driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @}
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 134 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 135 *
<> 144:ef7eb2e8f9f7 136 @verbatim
<> 144:ef7eb2e8f9f7 137 ==============================================================================
<> 144:ef7eb2e8f9f7 138 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 139 ==============================================================================
<> 144:ef7eb2e8f9f7 140 [..]
<> 144:ef7eb2e8f9f7 141 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 142 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 143 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 144 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 145 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 146 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 147 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 148 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 149 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 @endverbatim
<> 144:ef7eb2e8f9f7 152 * @{
<> 144:ef7eb2e8f9f7 153 */
<> 144:ef7eb2e8f9f7 154 /**
<> 144:ef7eb2e8f9f7 155 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 156 * @param htim : TIM Encoder Interface handle
<> 144:ef7eb2e8f9f7 157 * @param sConfig : TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 158 * @retval HAL status
<> 144:ef7eb2e8f9f7 159 */
<> 144:ef7eb2e8f9f7 160 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 161 {
<> 144:ef7eb2e8f9f7 162 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 165 if(htim == NULL)
<> 144:ef7eb2e8f9f7 166 {
<> 144:ef7eb2e8f9f7 167 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 168 }
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 175 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 156:95d6b41a828b 176 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 if(htim->State == HAL_TIM_STATE_RESET)
<> 144:ef7eb2e8f9f7 179 {
<> 144:ef7eb2e8f9f7 180 /* Allocate lock resource and initialize it */
<> 144:ef7eb2e8f9f7 181 htim->Lock = HAL_UNLOCKED;
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 184 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 188 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 191 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 194 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 197 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 198 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 199 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 202 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 205 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 206 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 209 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 210 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 213 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 214 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 215 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 216 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 217 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 218 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 219 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 224 register to 101 */
<> 144:ef7eb2e8f9f7 225 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 226 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 229 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 return HAL_OK;
<> 144:ef7eb2e8f9f7 232 }
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 /**
<> 144:ef7eb2e8f9f7 235 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 236 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 237 * @retval HAL status
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 /* Check the parameters */
<> 144:ef7eb2e8f9f7 242 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 247 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 250 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Change TIM state */
<> 144:ef7eb2e8f9f7 253 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 /* Release Lock */
<> 144:ef7eb2e8f9f7 256 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 return HAL_OK;
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 263 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 264 * @retval None
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 267 {
<> 144:ef7eb2e8f9f7 268 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 269 UNUSED(htim);
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 272 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 278 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 279 * @retval None
<> 144:ef7eb2e8f9f7 280 */
<> 144:ef7eb2e8f9f7 281 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 282 {
<> 144:ef7eb2e8f9f7 283 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 284 UNUSED(htim);
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 287 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 293 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 294 * @retval HAL status
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 /* Check the parameters */
<> 144:ef7eb2e8f9f7 299 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 302 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 303 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 306 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Return function status */
<> 144:ef7eb2e8f9f7 309 return HAL_OK;
<> 144:ef7eb2e8f9f7 310 }
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /**
<> 144:ef7eb2e8f9f7 313 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 314 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 315 * @retval HAL status
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Check the parameters */
<> 144:ef7eb2e8f9f7 320 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 323 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 324 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 327 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 /* Return function status */
<> 144:ef7eb2e8f9f7 330 return HAL_OK;
<> 144:ef7eb2e8f9f7 331 }
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /**
<> 144:ef7eb2e8f9f7 334 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 335 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 336 * @retval HAL status
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 339 {
<> 144:ef7eb2e8f9f7 340 /* Check the parameters */
<> 144:ef7eb2e8f9f7 341 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 344 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 347 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 351 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* Return function status */
<> 144:ef7eb2e8f9f7 354 return HAL_OK;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 /**
<> 144:ef7eb2e8f9f7 358 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 359 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 360 * @retval HAL status
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 363 {
<> 144:ef7eb2e8f9f7 364 /* Check the parameters */
<> 144:ef7eb2e8f9f7 365 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 368 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 369 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 372 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 375 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 /* Return function status */
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 383 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 384 * @param pData : The destination Buffer address.
<> 144:ef7eb2e8f9f7 385 * @param Length : The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 386 * @retval HAL status
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 /* Check the parameters */
<> 144:ef7eb2e8f9f7 391 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 396 }
<> 144:ef7eb2e8f9f7 397 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 398 {
<> 156:95d6b41a828b 399 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 else
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408 /* Enable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 409 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 410 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 413 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 414 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 415 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 /* Enable the DMA channel for Capture 1*/
<> 144:ef7eb2e8f9f7 418 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 421 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 424 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /* Return function status */
<> 144:ef7eb2e8f9f7 427 return HAL_OK;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /**
<> 144:ef7eb2e8f9f7 431 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 432 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 433 * @retval HAL status
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 /* Disable the Input Capture channel 1
<> 144:ef7eb2e8f9f7 441 (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 442 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 446 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 449 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /* Return function status */
<> 144:ef7eb2e8f9f7 452 return HAL_OK;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /**
<> 144:ef7eb2e8f9f7 456 * @}
<> 144:ef7eb2e8f9f7 457 */
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 460 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 461 *
<> 144:ef7eb2e8f9f7 462 @verbatim
<> 144:ef7eb2e8f9f7 463 ==============================================================================
<> 144:ef7eb2e8f9f7 464 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 465 ==============================================================================
<> 144:ef7eb2e8f9f7 466 [..]
<> 144:ef7eb2e8f9f7 467 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 468 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 469 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 470 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 471 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 472 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 473 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 @endverbatim
<> 144:ef7eb2e8f9f7 476 * @{
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /**
<> 144:ef7eb2e8f9f7 480 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 481 * output.
<> 144:ef7eb2e8f9f7 482 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 483 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 484 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 485 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 486 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 487 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 488 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 489 * @retval HAL status
<> 144:ef7eb2e8f9f7 490 */
<> 144:ef7eb2e8f9f7 491 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 /* Check the parameters */
<> 144:ef7eb2e8f9f7 494 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 497 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 500 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 503 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 /* Return function status */
<> 144:ef7eb2e8f9f7 506 return HAL_OK;
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 511 * output.
<> 144:ef7eb2e8f9f7 512 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 513 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 514 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 515 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 516 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 517 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 518 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 519 * @retval HAL status
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 527 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 530 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 533 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Return function status */
<> 144:ef7eb2e8f9f7 536 return HAL_OK;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 541 * on the complementary output.
<> 144:ef7eb2e8f9f7 542 * @param htim : TIM OC handle
<> 144:ef7eb2e8f9f7 543 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 544 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 545 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 546 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 547 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 548 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 549 * @retval HAL status
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 /* Check the parameters */
<> 144:ef7eb2e8f9f7 554 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 switch (Channel)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 559 {
<> 144:ef7eb2e8f9f7 560 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 561 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 562 }
<> 144:ef7eb2e8f9f7 563 break;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 566 {
<> 144:ef7eb2e8f9f7 567 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 568 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570 break;
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 575 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 break;
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 582 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 583 }
<> 144:ef7eb2e8f9f7 584 break;
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 default:
<> 144:ef7eb2e8f9f7 587 break;
<> 144:ef7eb2e8f9f7 588 }
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 591 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 594 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 595
<> 144:ef7eb2e8f9f7 596 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 597 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 600 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 /* Return function status */
<> 144:ef7eb2e8f9f7 603 return HAL_OK;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 608 * on the complementary output.
<> 144:ef7eb2e8f9f7 609 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 610 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 611 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 616 * @retval HAL status
<> 144:ef7eb2e8f9f7 617 */
<> 144:ef7eb2e8f9f7 618 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 619 {
<> 156:95d6b41a828b 620 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Check the parameters */
<> 144:ef7eb2e8f9f7 623 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 switch (Channel)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 630 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 break;
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 637 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 break;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 644 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 break;
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 651 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 break;
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 default:
<> 144:ef7eb2e8f9f7 656 break;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 660 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 663 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 664 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 665 {
<> 144:ef7eb2e8f9f7 666 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 670 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 673 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 674
<> 144:ef7eb2e8f9f7 675 /* Return function status */
<> 144:ef7eb2e8f9f7 676 return HAL_OK;
<> 144:ef7eb2e8f9f7 677 }
<> 144:ef7eb2e8f9f7 678
<> 144:ef7eb2e8f9f7 679 /**
<> 144:ef7eb2e8f9f7 680 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 681 * on the complementary output.
<> 144:ef7eb2e8f9f7 682 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 683 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 684 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 685 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 686 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 687 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 688 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 689 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 690 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 691 * @retval HAL status
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Check the parameters */
<> 144:ef7eb2e8f9f7 696 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 703 {
<> 156:95d6b41a828b 704 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 else
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 switch (Channel)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 718 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 721 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 724 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 727 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 break;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 734 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 737 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 740 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 743 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 break;
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 750 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 753 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 756 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 759 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 break;
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 766 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 769 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 772 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 break;
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 default:
<> 144:ef7eb2e8f9f7 780 break;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 784 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 787 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 790 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Return function status */
<> 144:ef7eb2e8f9f7 793 return HAL_OK;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 798 * on the complementary output.
<> 144:ef7eb2e8f9f7 799 * @param htim : TIM Output Compare handle
<> 144:ef7eb2e8f9f7 800 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 801 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 802 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 803 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 804 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 805 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 806 * @retval HAL status
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 809 {
<> 144:ef7eb2e8f9f7 810 /* Check the parameters */
<> 144:ef7eb2e8f9f7 811 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 812
<> 144:ef7eb2e8f9f7 813 switch (Channel)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 816 {
<> 144:ef7eb2e8f9f7 817 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 818 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820 break;
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 825 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 break;
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 830 {
<> 144:ef7eb2e8f9f7 831 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 832 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 833 }
<> 144:ef7eb2e8f9f7 834 break;
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 837 {
<> 144:ef7eb2e8f9f7 838 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 839 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 840 }
<> 144:ef7eb2e8f9f7 841 break;
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 default:
<> 144:ef7eb2e8f9f7 844 break;
<> 144:ef7eb2e8f9f7 845 }
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 848 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 851 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 854 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 /* Change the htim state */
<> 144:ef7eb2e8f9f7 857 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 858
<> 144:ef7eb2e8f9f7 859 /* Return function status */
<> 144:ef7eb2e8f9f7 860 return HAL_OK;
<> 144:ef7eb2e8f9f7 861 }
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 /**
<> 144:ef7eb2e8f9f7 864 * @}
<> 144:ef7eb2e8f9f7 865 */
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 868 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 869 *
<> 144:ef7eb2e8f9f7 870 @verbatim
<> 144:ef7eb2e8f9f7 871 ==============================================================================
<> 144:ef7eb2e8f9f7 872 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 873 ==============================================================================
<> 144:ef7eb2e8f9f7 874 [..]
<> 144:ef7eb2e8f9f7 875 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 876 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 877 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 878 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 879 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 880 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 881 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 882 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 883 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 884 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 885 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 886 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 887 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 888 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 889 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 890 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 891 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 @endverbatim
<> 144:ef7eb2e8f9f7 894 * @{
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 899 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 900 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 901 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 902 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 905 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 906 * @retval HAL status
<> 144:ef7eb2e8f9f7 907 */
<> 144:ef7eb2e8f9f7 908 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* Check the parameters */
<> 144:ef7eb2e8f9f7 911 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 914 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 917 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 920 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 921
<> 144:ef7eb2e8f9f7 922 /* Return function status */
<> 144:ef7eb2e8f9f7 923 return HAL_OK;
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 /**
<> 144:ef7eb2e8f9f7 927 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 928 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 929 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 930 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 931 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 932 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 933 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 934 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 935 * @retval HAL status
<> 144:ef7eb2e8f9f7 936 */
<> 144:ef7eb2e8f9f7 937 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 938 {
<> 144:ef7eb2e8f9f7 939 /* Check the parameters */
<> 144:ef7eb2e8f9f7 940 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 941
<> 144:ef7eb2e8f9f7 942 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 943 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 946 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 949 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Return function status */
<> 144:ef7eb2e8f9f7 952 return HAL_OK;
<> 144:ef7eb2e8f9f7 953 }
<> 144:ef7eb2e8f9f7 954
<> 144:ef7eb2e8f9f7 955 /**
<> 144:ef7eb2e8f9f7 956 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 957 * complementary output.
<> 144:ef7eb2e8f9f7 958 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 959 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 960 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 961 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 962 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 963 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 964 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 965 * @retval HAL status
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 968 {
<> 144:ef7eb2e8f9f7 969 /* Check the parameters */
<> 144:ef7eb2e8f9f7 970 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 971
<> 144:ef7eb2e8f9f7 972 switch (Channel)
<> 144:ef7eb2e8f9f7 973 {
<> 144:ef7eb2e8f9f7 974 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 975 {
<> 144:ef7eb2e8f9f7 976 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 977 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979 break;
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 982 {
<> 144:ef7eb2e8f9f7 983 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 984 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 985 }
<> 144:ef7eb2e8f9f7 986 break;
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 989 {
<> 144:ef7eb2e8f9f7 990 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 991 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 992 }
<> 144:ef7eb2e8f9f7 993 break;
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 996 {
<> 144:ef7eb2e8f9f7 997 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 998 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 break;
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 default:
<> 144:ef7eb2e8f9f7 1003 break;
<> 144:ef7eb2e8f9f7 1004 }
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1007 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1010 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1013 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1016 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Return function status */
<> 144:ef7eb2e8f9f7 1019 return HAL_OK;
<> 144:ef7eb2e8f9f7 1020 }
<> 144:ef7eb2e8f9f7 1021
<> 144:ef7eb2e8f9f7 1022 /**
<> 144:ef7eb2e8f9f7 1023 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1024 * complementary output.
<> 144:ef7eb2e8f9f7 1025 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1026 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1027 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1028 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1029 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1030 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1031 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1032 * @retval HAL status
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1035 {
<> 156:95d6b41a828b 1036 uint32_t tmpccer = 0U;
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1039 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 switch (Channel)
<> 144:ef7eb2e8f9f7 1042 {
<> 144:ef7eb2e8f9f7 1043 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1046 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1047 }
<> 144:ef7eb2e8f9f7 1048 break;
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1053 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1054 }
<> 144:ef7eb2e8f9f7 1055 break;
<> 144:ef7eb2e8f9f7 1056
<> 144:ef7eb2e8f9f7 1057 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1058 {
<> 144:ef7eb2e8f9f7 1059 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1060 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062 break;
<> 144:ef7eb2e8f9f7 1063
<> 144:ef7eb2e8f9f7 1064 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1065 {
<> 144:ef7eb2e8f9f7 1066 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1067 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069 break;
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 default:
<> 144:ef7eb2e8f9f7 1072 break;
<> 144:ef7eb2e8f9f7 1073 }
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1076 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1079 tmpccer = htim->Instance->CCER;
<> 144:ef7eb2e8f9f7 1080 if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1081 {
<> 144:ef7eb2e8f9f7 1082 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1086 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1089 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 /* Return function status */
<> 144:ef7eb2e8f9f7 1092 return HAL_OK;
<> 144:ef7eb2e8f9f7 1093 }
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /**
<> 144:ef7eb2e8f9f7 1096 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1097 * complementary output
<> 144:ef7eb2e8f9f7 1098 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1099 * @param Channel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1100 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1101 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1102 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1103 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1104 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1105 * @param pData : The source Buffer address.
<> 144:ef7eb2e8f9f7 1106 * @param Length : The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1107 * @retval HAL status
<> 144:ef7eb2e8f9f7 1108 */
<> 144:ef7eb2e8f9f7 1109 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1110 {
<> 144:ef7eb2e8f9f7 1111 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1112 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1115 {
<> 144:ef7eb2e8f9f7 1116 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1119 {
<> 156:95d6b41a828b 1120 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124 else
<> 144:ef7eb2e8f9f7 1125 {
<> 144:ef7eb2e8f9f7 1126 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129 switch (Channel)
<> 144:ef7eb2e8f9f7 1130 {
<> 144:ef7eb2e8f9f7 1131 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1134 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1137 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1140 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1143 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1144 }
<> 144:ef7eb2e8f9f7 1145 break;
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1148 {
<> 144:ef7eb2e8f9f7 1149 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1150 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1153 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1156 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1159 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1160 }
<> 144:ef7eb2e8f9f7 1161 break;
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1164 {
<> 144:ef7eb2e8f9f7 1165 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1166 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1169 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1170
<> 144:ef7eb2e8f9f7 1171 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1172 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1175 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1176 }
<> 144:ef7eb2e8f9f7 1177 break;
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1182 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1185 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 1188 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1191 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1192 }
<> 144:ef7eb2e8f9f7 1193 break;
<> 144:ef7eb2e8f9f7 1194
<> 144:ef7eb2e8f9f7 1195 default:
<> 144:ef7eb2e8f9f7 1196 break;
<> 144:ef7eb2e8f9f7 1197 }
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1200 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1203 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1206 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /* Return function status */
<> 144:ef7eb2e8f9f7 1209 return HAL_OK;
<> 144:ef7eb2e8f9f7 1210 }
<> 144:ef7eb2e8f9f7 1211
<> 144:ef7eb2e8f9f7 1212 /**
<> 144:ef7eb2e8f9f7 1213 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1214 * output
<> 144:ef7eb2e8f9f7 1215 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1216 * @param Channel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1217 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1218 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1219 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1220 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1221 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1222 * @retval HAL status
<> 144:ef7eb2e8f9f7 1223 */
<> 144:ef7eb2e8f9f7 1224 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1225 {
<> 144:ef7eb2e8f9f7 1226 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1227 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 switch (Channel)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1232 {
<> 144:ef7eb2e8f9f7 1233 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1234 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1235 }
<> 144:ef7eb2e8f9f7 1236 break;
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1239 {
<> 144:ef7eb2e8f9f7 1240 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1241 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1242 }
<> 144:ef7eb2e8f9f7 1243 break;
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1246 {
<> 144:ef7eb2e8f9f7 1247 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1248 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250 break;
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1253 {
<> 144:ef7eb2e8f9f7 1254 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1255 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1256 }
<> 144:ef7eb2e8f9f7 1257 break;
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 default:
<> 144:ef7eb2e8f9f7 1260 break;
<> 144:ef7eb2e8f9f7 1261 }
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1264 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1267 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1270 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1273 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Return function status */
<> 144:ef7eb2e8f9f7 1276 return HAL_OK;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @}
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1284 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1285 *
<> 144:ef7eb2e8f9f7 1286 @verbatim
<> 144:ef7eb2e8f9f7 1287 ==============================================================================
<> 144:ef7eb2e8f9f7 1288 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1289 ==============================================================================
<> 144:ef7eb2e8f9f7 1290 [..]
<> 144:ef7eb2e8f9f7 1291 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1292 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1293 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1294 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1295 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297 @endverbatim
<> 144:ef7eb2e8f9f7 1298 * @{
<> 144:ef7eb2e8f9f7 1299 */
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /**
<> 144:ef7eb2e8f9f7 1302 * @brief Starts the TIM One Pulse signal generation on the complemetary
<> 144:ef7eb2e8f9f7 1303 * output.
<> 144:ef7eb2e8f9f7 1304 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1305 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1306 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1307 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1308 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1309 * @retval HAL status
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1312 {
<> 144:ef7eb2e8f9f7 1313 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1314 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1315
<> 144:ef7eb2e8f9f7 1316 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1317 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1320 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 /* Return function status */
<> 144:ef7eb2e8f9f7 1323 return HAL_OK;
<> 144:ef7eb2e8f9f7 1324 }
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1328 * output.
<> 144:ef7eb2e8f9f7 1329 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1330 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1331 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1332 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1333 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1334 * @retval HAL status
<> 144:ef7eb2e8f9f7 1335 */
<> 144:ef7eb2e8f9f7 1336 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1337 {
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1340 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1341
<> 144:ef7eb2e8f9f7 1342 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1343 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1344
<> 144:ef7eb2e8f9f7 1345 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1346 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1347
<> 144:ef7eb2e8f9f7 1348 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1349 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1350
<> 144:ef7eb2e8f9f7 1351 /* Return function status */
<> 144:ef7eb2e8f9f7 1352 return HAL_OK;
<> 144:ef7eb2e8f9f7 1353 }
<> 144:ef7eb2e8f9f7 1354
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1357 * complementary channel.
<> 144:ef7eb2e8f9f7 1358 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1359 * @param OutputChannel : TIM Channel to be enabled
<> 144:ef7eb2e8f9f7 1360 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1361 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1362 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1363 * @retval HAL status
<> 144:ef7eb2e8f9f7 1364 */
<> 144:ef7eb2e8f9f7 1365 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1366 {
<> 144:ef7eb2e8f9f7 1367 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1368 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1371 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1372
<> 144:ef7eb2e8f9f7 1373 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1374 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1377 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /* Enable the Main Ouput */
<> 144:ef7eb2e8f9f7 1380 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /* Return function status */
<> 144:ef7eb2e8f9f7 1383 return HAL_OK;
<> 144:ef7eb2e8f9f7 1384 }
<> 144:ef7eb2e8f9f7 1385
<> 144:ef7eb2e8f9f7 1386 /**
<> 144:ef7eb2e8f9f7 1387 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1388 * complementary channel.
<> 144:ef7eb2e8f9f7 1389 * @param htim : TIM One Pulse handle
<> 144:ef7eb2e8f9f7 1390 * @param OutputChannel : TIM Channel to be disabled
<> 144:ef7eb2e8f9f7 1391 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1392 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1393 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1394 * @retval HAL status
<> 144:ef7eb2e8f9f7 1395 */
<> 144:ef7eb2e8f9f7 1396 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1397 {
<> 144:ef7eb2e8f9f7 1398 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1399 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1402 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1403
<> 144:ef7eb2e8f9f7 1404 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1405 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1406
<> 144:ef7eb2e8f9f7 1407 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1408 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1409
<> 144:ef7eb2e8f9f7 1410 /* Disable the Main Ouput */
<> 144:ef7eb2e8f9f7 1411 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1414 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /* Return function status */
<> 144:ef7eb2e8f9f7 1417 return HAL_OK;
<> 144:ef7eb2e8f9f7 1418 }
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /**
<> 144:ef7eb2e8f9f7 1421 * @}
<> 144:ef7eb2e8f9f7 1422 */
<> 144:ef7eb2e8f9f7 1423 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1424 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1425 *
<> 144:ef7eb2e8f9f7 1426 @verbatim
<> 144:ef7eb2e8f9f7 1427 ==============================================================================
<> 144:ef7eb2e8f9f7 1428 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1429 ==============================================================================
<> 144:ef7eb2e8f9f7 1430 [..]
<> 144:ef7eb2e8f9f7 1431 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1432 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1433 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1434 (+) Configure Master synchronization.
<> 144:ef7eb2e8f9f7 1435 (+) Configure timer remapping capabilities.
<> 144:ef7eb2e8f9f7 1436
<> 144:ef7eb2e8f9f7 1437 @endverbatim
<> 144:ef7eb2e8f9f7 1438 * @{
<> 144:ef7eb2e8f9f7 1439 */
<> 144:ef7eb2e8f9f7 1440 /**
<> 144:ef7eb2e8f9f7 1441 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1442 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1443 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1444 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1445 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1446 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1447 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1448 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1449 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1450 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1451 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1452 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1453 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1454 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1455 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1456 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1457 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1458 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1459 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1460 * @retval HAL status
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1463 {
<> 144:ef7eb2e8f9f7 1464 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1465 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1466 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1467
<> 144:ef7eb2e8f9f7 1468 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1469
<> 144:ef7eb2e8f9f7 1470 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1471 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1472 {
<> 144:ef7eb2e8f9f7 1473 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1474 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1475 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1476 }
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1479 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1480 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1481 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1482 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1483
<> 144:ef7eb2e8f9f7 1484 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 return HAL_OK;
<> 144:ef7eb2e8f9f7 1487 }
<> 144:ef7eb2e8f9f7 1488
<> 144:ef7eb2e8f9f7 1489 /**
<> 144:ef7eb2e8f9f7 1490 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1491 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1492 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1493 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1494 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1495 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1496 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1497 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1498 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1499 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1500 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1501 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1502 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1503 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1504 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1505 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1506 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1507 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1508 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1509 * @retval HAL status
<> 144:ef7eb2e8f9f7 1510 */
<> 144:ef7eb2e8f9f7 1511 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1512 {
<> 144:ef7eb2e8f9f7 1513 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1514 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1515 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1520 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1521 {
<> 144:ef7eb2e8f9f7 1522 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1523 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1524 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1525 }
<> 144:ef7eb2e8f9f7 1526
<> 144:ef7eb2e8f9f7 1527 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1528 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1529 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1530 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1531 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1532
<> 144:ef7eb2e8f9f7 1533 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1534 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 return HAL_OK;
<> 144:ef7eb2e8f9f7 1539 }
<> 144:ef7eb2e8f9f7 1540
<> 144:ef7eb2e8f9f7 1541 /**
<> 144:ef7eb2e8f9f7 1542 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1543 * @note: this function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1544 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1545 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1546 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1547 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1548 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1549 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1550 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1551 * @param InputTrigger : the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<> 144:ef7eb2e8f9f7 1552 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1553 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1554 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1555 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1556 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1557 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1558 * @param CommutationSource : the Commutation Event source
<> 144:ef7eb2e8f9f7 1559 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1560 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1561 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1562 * @retval HAL status
<> 144:ef7eb2e8f9f7 1563 */
<> 144:ef7eb2e8f9f7 1564 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1565 {
<> 144:ef7eb2e8f9f7 1566 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1567 assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1568 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1571
<> 144:ef7eb2e8f9f7 1572 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1573 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1574 {
<> 144:ef7eb2e8f9f7 1575 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1576 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1577 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1578 }
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1581 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1582 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1583 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1584 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1587 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1588 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1589 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1590 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1593 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 return HAL_OK;
<> 144:ef7eb2e8f9f7 1598 }
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 /**
<> 144:ef7eb2e8f9f7 1601 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1602 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1603 * @param sMasterConfig : pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1604 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1605 * mode.
<> 144:ef7eb2e8f9f7 1606 * @retval HAL status
<> 144:ef7eb2e8f9f7 1607 */
<> 144:ef7eb2e8f9f7 1608 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1609 {
<> 144:ef7eb2e8f9f7 1610 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1611 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1612 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1613 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1616
<> 144:ef7eb2e8f9f7 1617 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1618
<> 144:ef7eb2e8f9f7 1619 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1620 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1621 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1622 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1625 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1626 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1627 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1628
<> 144:ef7eb2e8f9f7 1629 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 return HAL_OK;
<> 144:ef7eb2e8f9f7 1634 }
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /**
<> 144:ef7eb2e8f9f7 1637 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1638 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1639 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1640 * @param sBreakDeadTimeConfig : pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1641 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1642 * @retval HAL status
<> 144:ef7eb2e8f9f7 1643 */
<> 144:ef7eb2e8f9f7 1644 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1645 TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1646 {
<> 156:95d6b41a828b 1647 uint32_t tmpbdtr = 0;
<> 156:95d6b41a828b 1648
<> 144:ef7eb2e8f9f7 1649 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1650 assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1651 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1652 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1653 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1654 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1655 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1656 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1657 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /* Process Locked */
<> 144:ef7eb2e8f9f7 1660 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1661
<> 144:ef7eb2e8f9f7 1662 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1665 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 156:95d6b41a828b 1666
<> 156:95d6b41a828b 1667 /* Set the BDTR bits */
<> 156:95d6b41a828b 1668 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
<> 156:95d6b41a828b 1669 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
<> 156:95d6b41a828b 1670 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
<> 156:95d6b41a828b 1671 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
<> 156:95d6b41a828b 1672 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
<> 156:95d6b41a828b 1673 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
<> 156:95d6b41a828b 1674 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 156:95d6b41a828b 1675 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, sBreakDeadTimeConfig->AutomaticOutput);
<> 156:95d6b41a828b 1676
<> 156:95d6b41a828b 1677 /* Set TIMx_BDTR */
<> 156:95d6b41a828b 1678 htim->Instance->BDTR = tmpbdtr;
<> 156:95d6b41a828b 1679
<> 144:ef7eb2e8f9f7 1680 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1681
<> 144:ef7eb2e8f9f7 1682 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 return HAL_OK;
<> 144:ef7eb2e8f9f7 1685 }
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /**
<> 144:ef7eb2e8f9f7 1688 * @brief Configures the TIM14 Remapping input capabilities.
<> 144:ef7eb2e8f9f7 1689 * @param htim : TIM handle.
<> 144:ef7eb2e8f9f7 1690 * @param Remap : specifies the TIM remapping source.
<> 144:ef7eb2e8f9f7 1691 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1692 * @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
<> 144:ef7eb2e8f9f7 1693 * @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
<> 144:ef7eb2e8f9f7 1694 * @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
<> 144:ef7eb2e8f9f7 1695 * @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
<> 144:ef7eb2e8f9f7 1696 * @retval HAL status
<> 144:ef7eb2e8f9f7 1697 */
<> 144:ef7eb2e8f9f7 1698 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 1699 {
<> 144:ef7eb2e8f9f7 1700 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /* Check parameters */
<> 144:ef7eb2e8f9f7 1703 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1704 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 1707 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 return HAL_OK;
<> 144:ef7eb2e8f9f7 1714 }
<> 144:ef7eb2e8f9f7 1715
<> 144:ef7eb2e8f9f7 1716 /**
<> 144:ef7eb2e8f9f7 1717 * @}
<> 144:ef7eb2e8f9f7 1718 */
<> 144:ef7eb2e8f9f7 1719
<> 156:95d6b41a828b 1720 /** @addtogroup TIM_Exported_Functions_Group8
<> 144:ef7eb2e8f9f7 1721 * @{
<> 144:ef7eb2e8f9f7 1722 */
<> 156:95d6b41a828b 1723 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 1724 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1725 defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 1726 /**
<> 144:ef7eb2e8f9f7 1727 * @brief Configures the OCRef clear feature
<> 144:ef7eb2e8f9f7 1728 * @param htim: TIM handle
<> 144:ef7eb2e8f9f7 1729 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1730 * contains the OCREF clear feature and parameters for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1731 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1732 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1733 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1734 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1735 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1736 * @arg TIM_CHANNEL_4: TIM Channel 4
<> 144:ef7eb2e8f9f7 1737 * @arg TIM_Channel_5: TIM Channel 5
<> 144:ef7eb2e8f9f7 1738 * @retval None
<> 144:ef7eb2e8f9f7 1739 */
<> 144:ef7eb2e8f9f7 1740 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1741 TIM_ClearInputConfigTypeDef *sClearInputConfig,
<> 144:ef7eb2e8f9f7 1742 uint32_t Channel)
<> 144:ef7eb2e8f9f7 1743 {
<> 156:95d6b41a828b 1744 uint32_t tmpsmcr = 0U;
<> 144:ef7eb2e8f9f7 1745
<> 144:ef7eb2e8f9f7 1746 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1747 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1748 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<> 144:ef7eb2e8f9f7 1749
<> 144:ef7eb2e8f9f7 1750 /* Check input state */
<> 144:ef7eb2e8f9f7 1751 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1752
<> 144:ef7eb2e8f9f7 1753 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 switch (sClearInputConfig->ClearInputSource)
<> 144:ef7eb2e8f9f7 1756 {
<> 144:ef7eb2e8f9f7 1757 case TIM_CLEARINPUTSOURCE_NONE:
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 /* Get the TIMx SMCR register value */
<> 144:ef7eb2e8f9f7 1760 tmpsmcr = htim->Instance->SMCR;
<> 144:ef7eb2e8f9f7 1761
<> 144:ef7eb2e8f9f7 1762 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1763 tmpsmcr &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1764
<> 144:ef7eb2e8f9f7 1765 /* Clear the ETR Bits */
<> 144:ef7eb2e8f9f7 1766 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
<> 144:ef7eb2e8f9f7 1767
<> 144:ef7eb2e8f9f7 1768 /* Set TIMx_SMCR */
<> 144:ef7eb2e8f9f7 1769 htim->Instance->SMCR = tmpsmcr;
<> 144:ef7eb2e8f9f7 1770 }
<> 144:ef7eb2e8f9f7 1771 break;
<> 144:ef7eb2e8f9f7 1772
<> 144:ef7eb2e8f9f7 1773 case TIM_CLEARINPUTSOURCE_OCREFCLR:
<> 144:ef7eb2e8f9f7 1774 {
<> 144:ef7eb2e8f9f7 1775 /* Clear the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1776 htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1777 }
<> 144:ef7eb2e8f9f7 1778 break;
<> 144:ef7eb2e8f9f7 1779
<> 144:ef7eb2e8f9f7 1780 case TIM_CLEARINPUTSOURCE_ETR:
<> 144:ef7eb2e8f9f7 1781 {
<> 144:ef7eb2e8f9f7 1782 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1783 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<> 144:ef7eb2e8f9f7 1784 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<> 144:ef7eb2e8f9f7 1785 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<> 144:ef7eb2e8f9f7 1786
<> 144:ef7eb2e8f9f7 1787 TIM_ETR_SetConfig(htim->Instance,
<> 144:ef7eb2e8f9f7 1788 sClearInputConfig->ClearInputPrescaler,
<> 144:ef7eb2e8f9f7 1789 sClearInputConfig->ClearInputPolarity,
<> 144:ef7eb2e8f9f7 1790 sClearInputConfig->ClearInputFilter);
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 /* Set the OCREF clear selection bit */
<> 144:ef7eb2e8f9f7 1793 htim->Instance->SMCR |= TIM_SMCR_OCCS;
<> 144:ef7eb2e8f9f7 1794 }
<> 144:ef7eb2e8f9f7 1795 break;
<> 144:ef7eb2e8f9f7 1796 default:
<> 144:ef7eb2e8f9f7 1797 break;
<> 144:ef7eb2e8f9f7 1798 }
<> 144:ef7eb2e8f9f7 1799
<> 144:ef7eb2e8f9f7 1800 switch (Channel)
<> 144:ef7eb2e8f9f7 1801 {
<> 144:ef7eb2e8f9f7 1802 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1803 {
<> 144:ef7eb2e8f9f7 1804 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1805 {
<> 144:ef7eb2e8f9f7 1806 /* Enable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1807 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1808 }
<> 144:ef7eb2e8f9f7 1809 else
<> 144:ef7eb2e8f9f7 1810 {
<> 144:ef7eb2e8f9f7 1811 /* Disable the Ocref clear feature for Channel 1 */
<> 144:ef7eb2e8f9f7 1812 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<> 144:ef7eb2e8f9f7 1813 }
<> 144:ef7eb2e8f9f7 1814 }
<> 144:ef7eb2e8f9f7 1815 break;
<> 144:ef7eb2e8f9f7 1816 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1817 {
<> 144:ef7eb2e8f9f7 1818 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1819 {
<> 144:ef7eb2e8f9f7 1820 /* Enable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1821 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1822 }
<> 144:ef7eb2e8f9f7 1823 else
<> 144:ef7eb2e8f9f7 1824 {
<> 144:ef7eb2e8f9f7 1825 /* Disable the Ocref clear feature for Channel 2 */
<> 144:ef7eb2e8f9f7 1826 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<> 144:ef7eb2e8f9f7 1827 }
<> 144:ef7eb2e8f9f7 1828 }
<> 144:ef7eb2e8f9f7 1829 break;
<> 144:ef7eb2e8f9f7 1830 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1831 {
<> 144:ef7eb2e8f9f7 1832 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1833 {
<> 144:ef7eb2e8f9f7 1834 /* Enable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1835 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1836 }
<> 144:ef7eb2e8f9f7 1837 else
<> 144:ef7eb2e8f9f7 1838 {
<> 144:ef7eb2e8f9f7 1839 /* Disable the Ocref clear feature for Channel 3 */
<> 144:ef7eb2e8f9f7 1840 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<> 144:ef7eb2e8f9f7 1841 }
<> 144:ef7eb2e8f9f7 1842 }
<> 144:ef7eb2e8f9f7 1843 break;
<> 144:ef7eb2e8f9f7 1844 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1845 {
<> 144:ef7eb2e8f9f7 1846 if(sClearInputConfig->ClearInputState != RESET)
<> 144:ef7eb2e8f9f7 1847 {
<> 144:ef7eb2e8f9f7 1848 /* Enable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1849 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1850 }
<> 144:ef7eb2e8f9f7 1851 else
<> 144:ef7eb2e8f9f7 1852 {
<> 144:ef7eb2e8f9f7 1853 /* Disable the Ocref clear feature for Channel 4 */
<> 144:ef7eb2e8f9f7 1854 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<> 144:ef7eb2e8f9f7 1855 }
<> 144:ef7eb2e8f9f7 1856 }
<> 144:ef7eb2e8f9f7 1857 break;
<> 144:ef7eb2e8f9f7 1858 default:
<> 144:ef7eb2e8f9f7 1859 break;
<> 144:ef7eb2e8f9f7 1860 }
<> 144:ef7eb2e8f9f7 1861
<> 144:ef7eb2e8f9f7 1862 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1863
<> 144:ef7eb2e8f9f7 1864 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 return HAL_OK;
<> 144:ef7eb2e8f9f7 1867 }
<> 156:95d6b41a828b 1868 #endif /* STM32F051x8 || STM32F058xx || */
<> 144:ef7eb2e8f9f7 1869 /* STM32F071xB || STM32F072xB || STM32F078xx || */
<> 156:95d6b41a828b 1870 /* STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 1871 /**
<> 144:ef7eb2e8f9f7 1872 * @}
<> 144:ef7eb2e8f9f7 1873 */
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1876 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1877 *
<> 144:ef7eb2e8f9f7 1878 @verbatim
<> 144:ef7eb2e8f9f7 1879 ==============================================================================
<> 144:ef7eb2e8f9f7 1880 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1881 ==============================================================================
<> 144:ef7eb2e8f9f7 1882 [..]
<> 144:ef7eb2e8f9f7 1883 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1884 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1885 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1886
<> 144:ef7eb2e8f9f7 1887 @endverbatim
<> 144:ef7eb2e8f9f7 1888 * @{
<> 144:ef7eb2e8f9f7 1889 */
<> 144:ef7eb2e8f9f7 1890
<> 144:ef7eb2e8f9f7 1891 /**
<> 144:ef7eb2e8f9f7 1892 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1893 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1894 * @retval None
<> 144:ef7eb2e8f9f7 1895 */
<> 144:ef7eb2e8f9f7 1896 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1897 {
<> 144:ef7eb2e8f9f7 1898 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1899 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1902 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1903 */
<> 144:ef7eb2e8f9f7 1904 }
<> 144:ef7eb2e8f9f7 1905
<> 144:ef7eb2e8f9f7 1906 /**
<> 144:ef7eb2e8f9f7 1907 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1908 * @param htim : TIM handle
<> 144:ef7eb2e8f9f7 1909 * @retval None
<> 144:ef7eb2e8f9f7 1910 */
<> 144:ef7eb2e8f9f7 1911 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1912 {
<> 144:ef7eb2e8f9f7 1913 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1914 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1915
<> 144:ef7eb2e8f9f7 1916 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1917 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1918 */
<> 144:ef7eb2e8f9f7 1919 }
<> 144:ef7eb2e8f9f7 1920
<> 144:ef7eb2e8f9f7 1921 /**
<> 144:ef7eb2e8f9f7 1922 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1923 * @param hdma : pointer to DMA handle.
<> 144:ef7eb2e8f9f7 1924 * @retval None
<> 144:ef7eb2e8f9f7 1925 */
<> 144:ef7eb2e8f9f7 1926 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1927 {
<> 144:ef7eb2e8f9f7 1928 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1931
<> 144:ef7eb2e8f9f7 1932 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1933 }
<> 144:ef7eb2e8f9f7 1934
<> 144:ef7eb2e8f9f7 1935 /**
<> 144:ef7eb2e8f9f7 1936 * @}
<> 144:ef7eb2e8f9f7 1937 */
<> 144:ef7eb2e8f9f7 1938
<> 144:ef7eb2e8f9f7 1939 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1940 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1941 *
<> 144:ef7eb2e8f9f7 1942 @verbatim
<> 144:ef7eb2e8f9f7 1943 ==============================================================================
<> 144:ef7eb2e8f9f7 1944 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1945 ==============================================================================
<> 144:ef7eb2e8f9f7 1946 [..]
<> 144:ef7eb2e8f9f7 1947 This subsection permit to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1948 and the data flow.
<> 144:ef7eb2e8f9f7 1949
<> 144:ef7eb2e8f9f7 1950 @endverbatim
<> 144:ef7eb2e8f9f7 1951 * @{
<> 144:ef7eb2e8f9f7 1952 */
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /**
<> 144:ef7eb2e8f9f7 1955 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1956 * @param htim : TIM Hall Sensor handle
<> 144:ef7eb2e8f9f7 1957 * @retval HAL state
<> 144:ef7eb2e8f9f7 1958 */
<> 144:ef7eb2e8f9f7 1959 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1960 {
<> 144:ef7eb2e8f9f7 1961 return htim->State;
<> 144:ef7eb2e8f9f7 1962 }
<> 144:ef7eb2e8f9f7 1963
<> 144:ef7eb2e8f9f7 1964 /**
<> 144:ef7eb2e8f9f7 1965 * @}
<> 144:ef7eb2e8f9f7 1966 */
<> 144:ef7eb2e8f9f7 1967
<> 144:ef7eb2e8f9f7 1968 /**
<> 144:ef7eb2e8f9f7 1969 * @}
<> 144:ef7eb2e8f9f7 1970 */
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 1973 * @{
<> 144:ef7eb2e8f9f7 1974 */
<> 144:ef7eb2e8f9f7 1975
<> 144:ef7eb2e8f9f7 1976 /**
<> 144:ef7eb2e8f9f7 1977 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1978 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1979 * @param Channel : specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1980 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1981 * @arg TIM_CHANNEL_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1982 * @arg TIM_CHANNEL_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1983 * @arg TIM_CHANNEL_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1984 * @param ChannelNState : specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1985 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1986 * @retval None
<> 144:ef7eb2e8f9f7 1987 */
<> 144:ef7eb2e8f9f7 1988 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1989 {
<> 156:95d6b41a828b 1990 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 1991
<> 144:ef7eb2e8f9f7 1992 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1993
<> 144:ef7eb2e8f9f7 1994 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1995 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1996
<> 144:ef7eb2e8f9f7 1997 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1998 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1999 }
<> 144:ef7eb2e8f9f7 2000
<> 144:ef7eb2e8f9f7 2001 /**
<> 144:ef7eb2e8f9f7 2002 * @}
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004
<> 144:ef7eb2e8f9f7 2005 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 2006 /**
<> 144:ef7eb2e8f9f7 2007 * @}
<> 144:ef7eb2e8f9f7 2008 */
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /**
<> 144:ef7eb2e8f9f7 2011 * @}
<> 144:ef7eb2e8f9f7 2012 */
<> 144:ef7eb2e8f9f7 2013
<> 144:ef7eb2e8f9f7 2014 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/