mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_spi.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_spi.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of SPI HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_SPI_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 156:95d6b41a828b 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup SPI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup SPI_Exported_Types SPI Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /**
<> 144:ef7eb2e8f9f7 63 * @brief SPI Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 */
<> 144:ef7eb2e8f9f7 65 typedef struct
<> 144:ef7eb2e8f9f7 66 {
<> 144:ef7eb2e8f9f7 67 uint32_t Mode; /*!< Specifies the SPI operating mode.
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref SPI_Mode */
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
<> 144:ef7eb2e8f9f7 71 This parameter can be a value of @ref SPI_Direction */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint32_t DataSize; /*!< Specifies the SPI data size.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref SPI_Data_Size */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref SPI_Clock_Polarity */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref SPI_Clock_Phase */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
<> 144:ef7eb2e8f9f7 83 hardware (NSS pin) or by software using the SSI bit.
<> 144:ef7eb2e8f9f7 84 This parameter can be a value of @ref SPI_Slave_Select_management */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
<> 144:ef7eb2e8f9f7 87 used to configure the transmit and receive SCK clock.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref SPI_BaudRate_Prescaler
<> 144:ef7eb2e8f9f7 89 @note The communication clock is derived from the master
<> 144:ef7eb2e8f9f7 90 clock. The slave clock does not need to be set. */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
<> 144:ef7eb2e8f9f7 94
<> 156:95d6b41a828b 95 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref SPI_TI_mode */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref SPI_CRC_Calculation */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
<> 144:ef7eb2e8f9f7 102 This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
<> 144:ef7eb2e8f9f7 105 CRC Length is only used with Data8 and Data16, not other data size
<> 144:ef7eb2e8f9f7 106 This parameter can be a value of @ref SPI_CRC_length */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
<> 144:ef7eb2e8f9f7 109 This parameter can be a value of @ref SPI_NSSP_Mode
<> 144:ef7eb2e8f9f7 110 This mode is activated by the NSSP bit in the SPIx_CR2 register and
<> 144:ef7eb2e8f9f7 111 it takes effect only if the SPI interface is configured as Motorola SPI
<> 144:ef7eb2e8f9f7 112 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
<> 144:ef7eb2e8f9f7 113 CPOL setting is ignored).. */
<> 144:ef7eb2e8f9f7 114 } SPI_InitTypeDef;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 /**
<> 156:95d6b41a828b 117 * @brief HAL SPI State structure definition
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 typedef enum
<> 144:ef7eb2e8f9f7 120 {
<> 156:95d6b41a828b 121 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
<> 156:95d6b41a828b 122 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
<> 156:95d6b41a828b 123 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
<> 156:95d6b41a828b 124 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 156:95d6b41a828b 125 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 156:95d6b41a828b 126 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
<> 156:95d6b41a828b 127 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
<> 156:95d6b41a828b 128 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
<> 156:95d6b41a828b 129 } HAL_SPI_StateTypeDef;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief SPI handle Structure definition
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134 typedef struct __SPI_HandleTypeDef
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 SPI_TypeDef *Instance; /*!< SPI registers base address */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 SPI_InitTypeDef Init; /*!< SPI communication parameters */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 uint16_t TxXferSize; /*!< SPI Tx Transfer size */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 uint16_t RxXferSize; /*!< SPI Rx Transfer size */
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
<> 144:ef7eb2e8f9f7 153
<> 156:95d6b41a828b 154 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
<> 144:ef7eb2e8f9f7 155
<> 156:95d6b41a828b 156 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 HAL_LockTypeDef Lock; /*!< Locking object */
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 __IO uint32_t ErrorCode; /*!< SPI Error code */
<> 144:ef7eb2e8f9f7 167
<> 156:95d6b41a828b 168 } SPI_HandleTypeDef;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 175 /** @defgroup SPI_Exported_Constants SPI Exported Constants
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup SPI_Error_Code SPI Error Code
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 156:95d6b41a828b 182 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 183 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
<> 156:95d6b41a828b 184 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
<> 156:95d6b41a828b 185 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
<> 156:95d6b41a828b 186 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
<> 156:95d6b41a828b 187 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
<> 156:95d6b41a828b 188 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
<> 156:95d6b41a828b 189 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @}
<> 144:ef7eb2e8f9f7 192 */
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /** @defgroup SPI_Mode SPI Mode
<> 144:ef7eb2e8f9f7 195 * @{
<> 144:ef7eb2e8f9f7 196 */
<> 156:95d6b41a828b 197 #define SPI_MODE_SLAVE (0x00000000U)
<> 144:ef7eb2e8f9f7 198 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /** @defgroup SPI_Direction SPI Direction Mode
<> 144:ef7eb2e8f9f7 204 * @{
<> 144:ef7eb2e8f9f7 205 */
<> 156:95d6b41a828b 206 #define SPI_DIRECTION_2LINES (0x00000000U)
<> 144:ef7eb2e8f9f7 207 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
<> 144:ef7eb2e8f9f7 208 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
<> 144:ef7eb2e8f9f7 209 /**
<> 144:ef7eb2e8f9f7 210 * @}
<> 144:ef7eb2e8f9f7 211 */
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** @defgroup SPI_Data_Size SPI Data Size
<> 144:ef7eb2e8f9f7 214 * @{
<> 144:ef7eb2e8f9f7 215 */
<> 156:95d6b41a828b 216 #define SPI_DATASIZE_4BIT (0x00000300U)
<> 156:95d6b41a828b 217 #define SPI_DATASIZE_5BIT (0x00000400U)
<> 156:95d6b41a828b 218 #define SPI_DATASIZE_6BIT (0x00000500U)
<> 156:95d6b41a828b 219 #define SPI_DATASIZE_7BIT (0x00000600U)
<> 156:95d6b41a828b 220 #define SPI_DATASIZE_8BIT (0x00000700U)
<> 156:95d6b41a828b 221 #define SPI_DATASIZE_9BIT (0x00000800U)
<> 156:95d6b41a828b 222 #define SPI_DATASIZE_10BIT (0x00000900U)
<> 156:95d6b41a828b 223 #define SPI_DATASIZE_11BIT (0x00000A00U)
<> 156:95d6b41a828b 224 #define SPI_DATASIZE_12BIT (0x00000B00U)
<> 156:95d6b41a828b 225 #define SPI_DATASIZE_13BIT (0x00000C00U)
<> 156:95d6b41a828b 226 #define SPI_DATASIZE_14BIT (0x00000D00U)
<> 156:95d6b41a828b 227 #define SPI_DATASIZE_15BIT (0x00000E00U)
<> 156:95d6b41a828b 228 #define SPI_DATASIZE_16BIT (0x00000F00U)
<> 144:ef7eb2e8f9f7 229 /**
<> 144:ef7eb2e8f9f7 230 * @}
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
<> 144:ef7eb2e8f9f7 234 * @{
<> 144:ef7eb2e8f9f7 235 */
<> 156:95d6b41a828b 236 #define SPI_POLARITY_LOW (0x00000000U)
<> 156:95d6b41a828b 237 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @}
<> 144:ef7eb2e8f9f7 240 */
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /** @defgroup SPI_Clock_Phase SPI Clock Phase
<> 144:ef7eb2e8f9f7 243 * @{
<> 144:ef7eb2e8f9f7 244 */
<> 156:95d6b41a828b 245 #define SPI_PHASE_1EDGE (0x00000000U)
<> 156:95d6b41a828b 246 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
<> 144:ef7eb2e8f9f7 247 /**
<> 144:ef7eb2e8f9f7 248 * @}
<> 144:ef7eb2e8f9f7 249 */
<> 144:ef7eb2e8f9f7 250
<> 156:95d6b41a828b 251 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
<> 144:ef7eb2e8f9f7 252 * @{
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254 #define SPI_NSS_SOFT SPI_CR1_SSM
<> 156:95d6b41a828b 255 #define SPI_NSS_HARD_INPUT (0x00000000U)
<> 156:95d6b41a828b 256 #define SPI_NSS_HARD_OUTPUT (0x00040000U)
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
<> 144:ef7eb2e8f9f7 262 * @{
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
<> 156:95d6b41a828b 265 #define SPI_NSS_PULSE_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 156:95d6b41a828b 273 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
<> 156:95d6b41a828b 274 #define SPI_BAUDRATEPRESCALER_4 (0x00000008U)
<> 156:95d6b41a828b 275 #define SPI_BAUDRATEPRESCALER_8 (0x00000010U)
<> 156:95d6b41a828b 276 #define SPI_BAUDRATEPRESCALER_16 (0x00000018U)
<> 156:95d6b41a828b 277 #define SPI_BAUDRATEPRESCALER_32 (0x00000020U)
<> 156:95d6b41a828b 278 #define SPI_BAUDRATEPRESCALER_64 (0x00000028U)
<> 156:95d6b41a828b 279 #define SPI_BAUDRATEPRESCALER_128 (0x00000030U)
<> 156:95d6b41a828b 280 #define SPI_BAUDRATEPRESCALER_256 (0x00000038U)
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 156:95d6b41a828b 285 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
<> 144:ef7eb2e8f9f7 286 * @{
<> 144:ef7eb2e8f9f7 287 */
<> 156:95d6b41a828b 288 #define SPI_FIRSTBIT_MSB (0x00000000U)
<> 144:ef7eb2e8f9f7 289 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @}
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 156:95d6b41a828b 294 /** @defgroup SPI_TI_mode SPI TI Mode
<> 144:ef7eb2e8f9f7 295 * @{
<> 144:ef7eb2e8f9f7 296 */
<> 156:95d6b41a828b 297 #define SPI_TIMODE_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 298 #define SPI_TIMODE_ENABLE SPI_CR2_FRF
<> 144:ef7eb2e8f9f7 299 /**
<> 144:ef7eb2e8f9f7 300 * @}
<> 144:ef7eb2e8f9f7 301 */
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
<> 144:ef7eb2e8f9f7 304 * @{
<> 144:ef7eb2e8f9f7 305 */
<> 156:95d6b41a828b 306 #define SPI_CRCCALCULATION_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 307 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @}
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 /** @defgroup SPI_CRC_length SPI CRC Length
<> 144:ef7eb2e8f9f7 313 * @{
<> 144:ef7eb2e8f9f7 314 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 315 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size
<> 144:ef7eb2e8f9f7 316 * SPI_CRC_LENGTH_8BIT : CRC 8bit
<> 144:ef7eb2e8f9f7 317 * SPI_CRC_LENGTH_16BIT : CRC 16bit
<> 144:ef7eb2e8f9f7 318 */
<> 156:95d6b41a828b 319 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
<> 156:95d6b41a828b 320 #define SPI_CRC_LENGTH_8BIT (0x00000001U)
<> 156:95d6b41a828b 321 #define SPI_CRC_LENGTH_16BIT (0x00000002U)
<> 144:ef7eb2e8f9f7 322 /**
<> 144:ef7eb2e8f9f7 323 * @}
<> 144:ef7eb2e8f9f7 324 */
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
<> 144:ef7eb2e8f9f7 327 * @{
<> 144:ef7eb2e8f9f7 328 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 329 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
<> 144:ef7eb2e8f9f7 330 * RXNE event is generated if the FIFO
<> 144:ef7eb2e8f9f7 331 * level is greater or equal to 1/2(16-bits).
<> 144:ef7eb2e8f9f7 332 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
<> 144:ef7eb2e8f9f7 333 * level is greater or equal to 1/4(8 bits). */
<> 144:ef7eb2e8f9f7 334 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
<> 144:ef7eb2e8f9f7 335 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
<> 156:95d6b41a828b 336 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 156:95d6b41a828b 342 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
<> 144:ef7eb2e8f9f7 343 * @{
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define SPI_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 346 #define SPI_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 347 #define SPI_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 348 /**
<> 144:ef7eb2e8f9f7 349 * @}
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351
<> 156:95d6b41a828b 352 /** @defgroup SPI_Flags_definition SPI Flags Definition
<> 144:ef7eb2e8f9f7 353 * @{
<> 144:ef7eb2e8f9f7 354 */
<> 156:95d6b41a828b 355 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
<> 156:95d6b41a828b 356 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
<> 156:95d6b41a828b 357 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
<> 156:95d6b41a828b 358 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
<> 156:95d6b41a828b 359 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
<> 156:95d6b41a828b 360 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
<> 144:ef7eb2e8f9f7 361 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
<> 156:95d6b41a828b 362 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
<> 156:95d6b41a828b 363 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
<> 144:ef7eb2e8f9f7 364 /**
<> 144:ef7eb2e8f9f7 365 * @}
<> 144:ef7eb2e8f9f7 366 */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
<> 144:ef7eb2e8f9f7 369 * @{
<> 144:ef7eb2e8f9f7 370 */
<> 156:95d6b41a828b 371 #define SPI_FTLVL_EMPTY (0x00000000U)
<> 156:95d6b41a828b 372 #define SPI_FTLVL_QUARTER_FULL (0x00000800U)
<> 156:95d6b41a828b 373 #define SPI_FTLVL_HALF_FULL (0x00001000U)
<> 156:95d6b41a828b 374 #define SPI_FTLVL_FULL (0x00001800U)
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 * @}
<> 144:ef7eb2e8f9f7 378 */
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 156:95d6b41a828b 383 #define SPI_FRLVL_EMPTY (0x00000000U)
<> 156:95d6b41a828b 384 #define SPI_FRLVL_QUARTER_FULL (0x00000200U)
<> 156:95d6b41a828b 385 #define SPI_FRLVL_HALF_FULL (0x00000400U)
<> 156:95d6b41a828b 386 #define SPI_FRLVL_FULL (0x00000600U)
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @}
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /**
<> 144:ef7eb2e8f9f7 392 * @}
<> 144:ef7eb2e8f9f7 393 */
<> 156:95d6b41a828b 394
<> 156:95d6b41a828b 395 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 396 /** @defgroup SPI_Exported_Macros SPI Exported Macros
<> 144:ef7eb2e8f9f7 397 * @{
<> 144:ef7eb2e8f9f7 398 */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /** @brief Reset SPI handle state.
<> 156:95d6b41a828b 401 * @param __HANDLE__: specifies the SPI Handle.
<> 156:95d6b41a828b 402 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /** @brief Enable or disable the specified SPI interrupts.
<> 144:ef7eb2e8f9f7 408 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 409 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 410 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 156:95d6b41a828b 411 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 412 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 413 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 414 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 415 * @retval None
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 418 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 /** @brief Check whether the specified SPI interrupt source is enabled or not.
<> 144:ef7eb2e8f9f7 421 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 422 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 423 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
<> 144:ef7eb2e8f9f7 424 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 425 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 426 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 427 * @arg SPI_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 428 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 429 */
<> 144:ef7eb2e8f9f7 430 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /** @brief Check whether the specified SPI flag is set or not.
<> 144:ef7eb2e8f9f7 433 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 434 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 435 * @param __FLAG__: specifies the flag to check.
<> 156:95d6b41a828b 436 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 437 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 438 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 439 * @arg SPI_FLAG_CRCERR: CRC error flag
<> 144:ef7eb2e8f9f7 440 * @arg SPI_FLAG_MODF: Mode fault flag
<> 144:ef7eb2e8f9f7 441 * @arg SPI_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 442 * @arg SPI_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 443 * @arg SPI_FLAG_FRE: Frame format error flag
<> 144:ef7eb2e8f9f7 444 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level
<> 144:ef7eb2e8f9f7 445 * @arg SPI_FLAG_FRLVL: SPI fifo reception level
<> 144:ef7eb2e8f9f7 446 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /** @brief Clear the SPI CRCERR pending flag.
<> 144:ef7eb2e8f9f7 451 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 452 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 453 * @retval None
<> 144:ef7eb2e8f9f7 454 */
<> 144:ef7eb2e8f9f7 455 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @brief Clear the SPI MODF pending flag.
<> 144:ef7eb2e8f9f7 458 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 459 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 460 * @retval None
<> 144:ef7eb2e8f9f7 461 */
<> 156:95d6b41a828b 462 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
<> 156:95d6b41a828b 463 do{ \
<> 156:95d6b41a828b 464 __IO uint32_t tmpreg_modf = 0x00U; \
<> 156:95d6b41a828b 465 tmpreg_modf = (__HANDLE__)->Instance->SR; \
<> 156:95d6b41a828b 466 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
<> 156:95d6b41a828b 467 UNUSED(tmpreg_modf); \
<> 156:95d6b41a828b 468 } while(0)
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /** @brief Clear the SPI OVR pending flag.
<> 144:ef7eb2e8f9f7 471 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 472 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 473 * @retval None
<> 144:ef7eb2e8f9f7 474 */
<> 156:95d6b41a828b 475 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
<> 156:95d6b41a828b 476 do{ \
<> 156:95d6b41a828b 477 __IO uint32_t tmpreg_ovr = 0x00U; \
<> 156:95d6b41a828b 478 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
<> 156:95d6b41a828b 479 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
<> 156:95d6b41a828b 480 UNUSED(tmpreg_ovr); \
<> 156:95d6b41a828b 481 } while(0)
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 /** @brief Clear the SPI FRE pending flag.
<> 144:ef7eb2e8f9f7 484 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 485 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 486 * @retval None
<> 144:ef7eb2e8f9f7 487 */
<> 156:95d6b41a828b 488 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
<> 156:95d6b41a828b 489 do{ \
<> 156:95d6b41a828b 490 __IO uint32_t tmpreg_fre = 0x00U; \
<> 156:95d6b41a828b 491 tmpreg_fre = (__HANDLE__)->Instance->SR; \
<> 156:95d6b41a828b 492 UNUSED(tmpreg_fre); \
<> 156:95d6b41a828b 493 }while(0)
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /** @brief Enable the SPI peripheral.
<> 144:ef7eb2e8f9f7 496 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 497 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 498 * @retval None
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502 /** @brief Disable the SPI peripheral.
<> 144:ef7eb2e8f9f7 503 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 504 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 505 * @retval None
<> 144:ef7eb2e8f9f7 506 */
<> 144:ef7eb2e8f9f7 507 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /**
<> 144:ef7eb2e8f9f7 510 * @}
<> 144:ef7eb2e8f9f7 511 */
<> 144:ef7eb2e8f9f7 512
<> 156:95d6b41a828b 513 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 514 /** @defgroup SPI_Private_Macros SPI Private Macros
<> 144:ef7eb2e8f9f7 515 * @{
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /** @brief Set the SPI transmit-only mode.
<> 144:ef7eb2e8f9f7 519 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 520 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 521 * @retval None
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 /** @brief Set the SPI receive-only mode.
<> 144:ef7eb2e8f9f7 526 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 527 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 528 * @retval None
<> 144:ef7eb2e8f9f7 529 */
<> 144:ef7eb2e8f9f7 530 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /** @brief Reset the CRC calculation of the SPI.
<> 144:ef7eb2e8f9f7 533 * @param __HANDLE__: specifies the SPI Handle.
<> 144:ef7eb2e8f9f7 534 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
<> 144:ef7eb2e8f9f7 535 * @retval None
<> 144:ef7eb2e8f9f7 536 */
<> 144:ef7eb2e8f9f7 537 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
<> 144:ef7eb2e8f9f7 538 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
<> 144:ef7eb2e8f9f7 541 ((MODE) == SPI_MODE_MASTER))
<> 144:ef7eb2e8f9f7 542
<> 156:95d6b41a828b 543 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 156:95d6b41a828b 544 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
<> 156:95d6b41a828b 545 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
<> 144:ef7eb2e8f9f7 548
<> 156:95d6b41a828b 549 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
<> 156:95d6b41a828b 550 ((MODE) == SPI_DIRECTION_1LINE))
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
<> 144:ef7eb2e8f9f7 553 ((DATASIZE) == SPI_DATASIZE_15BIT) || \
<> 144:ef7eb2e8f9f7 554 ((DATASIZE) == SPI_DATASIZE_14BIT) || \
<> 144:ef7eb2e8f9f7 555 ((DATASIZE) == SPI_DATASIZE_13BIT) || \
<> 144:ef7eb2e8f9f7 556 ((DATASIZE) == SPI_DATASIZE_12BIT) || \
<> 144:ef7eb2e8f9f7 557 ((DATASIZE) == SPI_DATASIZE_11BIT) || \
<> 144:ef7eb2e8f9f7 558 ((DATASIZE) == SPI_DATASIZE_10BIT) || \
<> 144:ef7eb2e8f9f7 559 ((DATASIZE) == SPI_DATASIZE_9BIT) || \
<> 144:ef7eb2e8f9f7 560 ((DATASIZE) == SPI_DATASIZE_8BIT) || \
<> 144:ef7eb2e8f9f7 561 ((DATASIZE) == SPI_DATASIZE_7BIT) || \
<> 144:ef7eb2e8f9f7 562 ((DATASIZE) == SPI_DATASIZE_6BIT) || \
<> 144:ef7eb2e8f9f7 563 ((DATASIZE) == SPI_DATASIZE_5BIT) || \
<> 144:ef7eb2e8f9f7 564 ((DATASIZE) == SPI_DATASIZE_4BIT))
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
<> 144:ef7eb2e8f9f7 567 ((CPOL) == SPI_POLARITY_HIGH))
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
<> 144:ef7eb2e8f9f7 570 ((CPHA) == SPI_PHASE_2EDGE))
<> 144:ef7eb2e8f9f7 571
<> 156:95d6b41a828b 572 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
<> 144:ef7eb2e8f9f7 573 ((NSS) == SPI_NSS_HARD_INPUT) || \
<> 144:ef7eb2e8f9f7 574 ((NSS) == SPI_NSS_HARD_OUTPUT))
<> 144:ef7eb2e8f9f7 575
<> 144:ef7eb2e8f9f7 576 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 577 ((NSSP) == SPI_NSS_PULSE_DISABLE))
<> 144:ef7eb2e8f9f7 578
<> 156:95d6b41a828b 579 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
<> 156:95d6b41a828b 580 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
<> 156:95d6b41a828b 581 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
<> 156:95d6b41a828b 582 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
<> 156:95d6b41a828b 583 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
<> 156:95d6b41a828b 584 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
<> 144:ef7eb2e8f9f7 585 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
<> 144:ef7eb2e8f9f7 586 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
<> 144:ef7eb2e8f9f7 589 ((BIT) == SPI_FIRSTBIT_LSB))
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 592 ((MODE) == SPI_TIMODE_ENABLE))
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
<> 144:ef7eb2e8f9f7 595 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
<> 144:ef7eb2e8f9f7 598 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \
<> 144:ef7eb2e8f9f7 599 ((LENGTH) == SPI_CRC_LENGTH_16BIT))
<> 144:ef7eb2e8f9f7 600
<> 156:95d6b41a828b 601 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1U) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0U))
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @}
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /* Include SPI HAL Extended module */
<> 144:ef7eb2e8f9f7 608 #include "stm32f0xx_hal_spi_ex.h"
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 611 /** @addtogroup SPI_Exported_Functions
<> 144:ef7eb2e8f9f7 612 * @{
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /** @addtogroup SPI_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 616 * @{
<> 144:ef7eb2e8f9f7 617 */
<> 156:95d6b41a828b 618 /* Initialization/de-initialization functions ********************************/
<> 144:ef7eb2e8f9f7 619 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 620 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 621 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 622 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @}
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /** @addtogroup SPI_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 628 * @{
<> 144:ef7eb2e8f9f7 629 */
<> 156:95d6b41a828b 630 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 631 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 632 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 156:95d6b41a828b 633 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
<> 156:95d6b41a828b 634 uint32_t Timeout);
<> 144:ef7eb2e8f9f7 635 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 636 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 156:95d6b41a828b 637 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 638 uint16_t Size);
<> 144:ef7eb2e8f9f7 639 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 640 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
<> 156:95d6b41a828b 641 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
<> 156:95d6b41a828b 642 uint16_t Size);
<> 144:ef7eb2e8f9f7 643 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 644 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 645 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 646 /* Transfer Abort functions */
<> 156:95d6b41a828b 647 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 648 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 649
<> 144:ef7eb2e8f9f7 650 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 651 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 652 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 653 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 654 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 655 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 656 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 657 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
<> 156:95d6b41a828b 658 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 659 /**
<> 144:ef7eb2e8f9f7 660 * @}
<> 144:ef7eb2e8f9f7 661 */
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 /** @addtogroup SPI_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 664 * @{
<> 144:ef7eb2e8f9f7 665 */
<> 156:95d6b41a828b 666 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 667 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 668 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @}
<> 144:ef7eb2e8f9f7 671 */
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 /**
<> 144:ef7eb2e8f9f7 674 * @}
<> 144:ef7eb2e8f9f7 675 */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /**
<> 144:ef7eb2e8f9f7 678 * @}
<> 144:ef7eb2e8f9f7 679 */
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @}
<> 144:ef7eb2e8f9f7 683 */
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 #endif
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #endif /* __STM32F0xx_HAL_SPI_H */
<> 144:ef7eb2e8f9f7 690
<> 144:ef7eb2e8f9f7 691 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/