mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_rcc.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
<> 144:ef7eb2e8f9f7 20 and all peripherals are off except internal SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
<> 144:ef7eb2e8f9f7 22 all peripherals mapped on these buses are running at HSI speed.
<> 144:ef7eb2e8f9f7 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 24 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 25 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 26 [..] Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 27 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 28 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 29 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 30 (+) Configure the AHB and APB buses prescalers
<> 144:ef7eb2e8f9f7 31 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 32 (+) Configure the clock source(s) for peripherals whose clocks are not
<> 144:ef7eb2e8f9f7 33 derived from the System clock (RTC, ADC, I2C, USART, TIM, USB FS, etc..)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 39 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 40 from/to registers.
<> 144:ef7eb2e8f9f7 41 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 42 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 Workarounds:
<> 144:ef7eb2e8f9f7 46 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 144:ef7eb2e8f9f7 47 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 @endverbatim
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 * @attention
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 56 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 57 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 58 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 60 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 61 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 63 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 64 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 */
<> 156:95d6b41a828b 79
<> 144:ef7eb2e8f9f7 80 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 88 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /** @defgroup RCC_Private_Constants RCC Private Constants
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 108 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 109 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /**
<> 144:ef7eb2e8f9f7 112 * @}
<> 144:ef7eb2e8f9f7 113 */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 117 * @{
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @}
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 124 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 127 * @{
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 131 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 132 *
<> 144:ef7eb2e8f9f7 133 @verbatim
<> 144:ef7eb2e8f9f7 134 ===============================================================================
<> 144:ef7eb2e8f9f7 135 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 136 ===============================================================================
<> 144:ef7eb2e8f9f7 137 [..]
<> 144:ef7eb2e8f9f7 138 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 139 (HSE, HSI, HSI14, HSI48, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK,
<> 144:ef7eb2e8f9f7 140 AHB and APB1).
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 143 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 144 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 145 The HSI clock can be used also to clock the USART and I2C peripherals.
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 (#) HSI14 (high-speed internal), 14 MHz factory-trimmed RC used directly to clock
<> 144:ef7eb2e8f9f7 148 the ADC peripheral.
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 151 clock source.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 154 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 (#) PLL (clocked by HSI, HSI48 or HSE), featuring different output clocks:
<> 144:ef7eb2e8f9f7 159 (++) The first output is used to generate the high speed system clock (up to 48 MHz)
<> 144:ef7eb2e8f9f7 160 (++) The second output is used to generate the clock for the USB FS (48 MHz)
<> 144:ef7eb2e8f9f7 161 (++) The third output may be used to generate the clock for the TIM, I2C and USART
<> 144:ef7eb2e8f9f7 162 peripherals (up to 48 MHz)
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<> 144:ef7eb2e8f9f7 165 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 166 clock source), the System clocks automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 167 is generated if enabled. The interrupt is linked to the Cortex-M0 NMI
<> 144:ef7eb2e8f9f7 168 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
<> 144:ef7eb2e8f9f7 171 clock (divided by 2) output on pin (such as PA8 pin).
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 [..] System, AHB and APB buses clocks configuration
<> 144:ef7eb2e8f9f7 174 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 175 HSE and PLL.
<> 144:ef7eb2e8f9f7 176 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 177 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 178 on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
<> 144:ef7eb2e8f9f7 179 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 180 the peripherals mapped on these buses. You can use
<> 144:ef7eb2e8f9f7 181 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 184 (++) The FLASH program/erase clock which is always HSI 8MHz clock.
<> 144:ef7eb2e8f9f7 185 (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
<> 144:ef7eb2e8f9f7 186 (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
<> 144:ef7eb2e8f9f7 187 (++) The I2C clock which can be derived as well from HSI 8MHz clock.
<> 144:ef7eb2e8f9f7 188 (++) The ADC clock which is derived from PLL output.
<> 144:ef7eb2e8f9f7 189 (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
<> 144:ef7eb2e8f9f7 190 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
<> 144:ef7eb2e8f9f7 191 frequency must be higher or equal to the RTC clock frequency.
<> 144:ef7eb2e8f9f7 192 (++) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 (#) For the STM32F0xx devices, the maximum frequency of the SYSCLK, HCLK and PCLK1 is 48 MHz,
<> 144:ef7eb2e8f9f7 195 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
<> 144:ef7eb2e8f9f7 198 prefetch is disabled.
<> 144:ef7eb2e8f9f7 199 @endverbatim
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /*
<> 144:ef7eb2e8f9f7 204 Additional consideration on the SYSCLK based on Latency settings:
<> 144:ef7eb2e8f9f7 205 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 206 | Latency | SYSCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 207 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 208 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
<> 144:ef7eb2e8f9f7 209 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 210 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
<> 144:ef7eb2e8f9f7 211 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /**
<> 144:ef7eb2e8f9f7 215 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 216 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 217 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 218 * - HSE and PLL OFF
<> 144:ef7eb2e8f9f7 219 * - AHB, APB1 prescaler set to 1.
<> 144:ef7eb2e8f9f7 220 * - CSS and MCO1 OFF
<> 144:ef7eb2e8f9f7 221 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 222 * @note This function does not modify the configuration of the
<> 144:ef7eb2e8f9f7 223 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 224 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 225 * @retval None
<> 144:ef7eb2e8f9f7 226 */
<> 144:ef7eb2e8f9f7 227 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
<> 144:ef7eb2e8f9f7 230 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
<> 144:ef7eb2e8f9f7 233 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE | RCC_CFGR_MCO);
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /* Reset HSEON, CSSON, PLLON bits */
<> 144:ef7eb2e8f9f7 236 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 239 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 156:95d6b41a828b 240
<> 144:ef7eb2e8f9f7 241 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 242 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Reset CFGR2 register */
<> 144:ef7eb2e8f9f7 245 CLEAR_REG(RCC->CFGR2);
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247 /* Reset CFGR3 register */
<> 144:ef7eb2e8f9f7 248 CLEAR_REG(RCC->CFGR3);
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 251 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 254 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 255 }
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 259 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 260 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 261 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 262 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 263 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 264 * supported by this macro. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 265 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 266 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 267 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 268 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 269 * @retval HAL status
<> 144:ef7eb2e8f9f7 270 */
<> 144:ef7eb2e8f9f7 271 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 272 {
<> 156:95d6b41a828b 273 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 274
<> 144:ef7eb2e8f9f7 275 /* Check the parameters */
<> 144:ef7eb2e8f9f7 276 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 277 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 156:95d6b41a828b 278
<> 144:ef7eb2e8f9f7 279 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 280 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 /* Check the parameters */
<> 144:ef7eb2e8f9f7 283 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 156:95d6b41a828b 284
<> 144:ef7eb2e8f9f7 285 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
<> 144:ef7eb2e8f9f7 286 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 287 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 290 {
<> 144:ef7eb2e8f9f7 291 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 292 }
<> 144:ef7eb2e8f9f7 293 }
<> 144:ef7eb2e8f9f7 294 else
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 297 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 301 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 304 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 307 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 308 {
<> 144:ef7eb2e8f9f7 309 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315 else
<> 144:ef7eb2e8f9f7 316 {
<> 144:ef7eb2e8f9f7 317 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 318 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /* Wait till HSE is disabled */
<> 144:ef7eb2e8f9f7 321 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 322 {
<> 144:ef7eb2e8f9f7 323 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 324 {
<> 144:ef7eb2e8f9f7 325 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328 }
<> 144:ef7eb2e8f9f7 329 }
<> 144:ef7eb2e8f9f7 330 }
<> 144:ef7eb2e8f9f7 331 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 332 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 /* Check the parameters */
<> 144:ef7eb2e8f9f7 335 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 336 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 339 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 340 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
<> 144:ef7eb2e8f9f7 341 {
<> 144:ef7eb2e8f9f7 342 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 343 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 346 }
<> 144:ef7eb2e8f9f7 347 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 348 else
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 351 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353 }
<> 144:ef7eb2e8f9f7 354 else
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 357 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 358 {
<> 144:ef7eb2e8f9f7 359 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 360 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 363 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 366 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 367 {
<> 144:ef7eb2e8f9f7 368 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 371 }
<> 144:ef7eb2e8f9f7 372 }
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 375 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377 else
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 380 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 383 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Wait till HSI is disabled */
<> 144:ef7eb2e8f9f7 386 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 391 }
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 }
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 }
<> 144:ef7eb2e8f9f7 396 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 397 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 /* Check the parameters */
<> 144:ef7eb2e8f9f7 400 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 403 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 404 {
<> 144:ef7eb2e8f9f7 405 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 406 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 409 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 412 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 413 {
<> 144:ef7eb2e8f9f7 414 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 417 }
<> 144:ef7eb2e8f9f7 418 }
<> 144:ef7eb2e8f9f7 419 }
<> 144:ef7eb2e8f9f7 420 else
<> 144:ef7eb2e8f9f7 421 {
<> 144:ef7eb2e8f9f7 422 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 423 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 426 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /* Wait till LSI is disabled */
<> 144:ef7eb2e8f9f7 429 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 434 }
<> 144:ef7eb2e8f9f7 435 }
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 439 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 /* Check the parameters */
<> 144:ef7eb2e8f9f7 444 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Update LSE configuration in Backup Domain control register */
<> 144:ef7eb2e8f9f7 447 /* Requires to enable write access to Backup Domain of necessary */
<> 144:ef7eb2e8f9f7 448 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 449 {
<> 144:ef7eb2e8f9f7 450 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 451 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 457 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 460 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 463 {
<> 144:ef7eb2e8f9f7 464 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468 }
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 472 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 473 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 474 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 477 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 480 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 483 {
<> 144:ef7eb2e8f9f7 484 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 485 }
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488 else
<> 144:ef7eb2e8f9f7 489 {
<> 144:ef7eb2e8f9f7 490 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 491 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /* Wait till LSE is disabled */
<> 144:ef7eb2e8f9f7 494 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 499 }
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 504 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 505 {
<> 144:ef7eb2e8f9f7 506 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 507 }
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509
<> 144:ef7eb2e8f9f7 510 /*----------------------------- HSI14 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 511 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14)
<> 144:ef7eb2e8f9f7 512 {
<> 144:ef7eb2e8f9f7 513 /* Check the parameters */
<> 144:ef7eb2e8f9f7 514 assert_param(IS_RCC_HSI14(RCC_OscInitStruct->HSI14State));
<> 144:ef7eb2e8f9f7 515 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSI14CalibrationValue));
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 /* Check the HSI14 State */
<> 144:ef7eb2e8f9f7 518 if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ON)
<> 144:ef7eb2e8f9f7 519 {
<> 144:ef7eb2e8f9f7 520 /* Disable ADC control of the Internal High Speed oscillator HSI14 */
<> 144:ef7eb2e8f9f7 521 __HAL_RCC_HSI14ADC_DISABLE();
<> 144:ef7eb2e8f9f7 522
<> 144:ef7eb2e8f9f7 523 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 524 __HAL_RCC_HSI14_ENABLE();
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 527 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) == RESET)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 533 {
<> 144:ef7eb2e8f9f7 534 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 535 }
<> 144:ef7eb2e8f9f7 536 }
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
<> 144:ef7eb2e8f9f7 539 __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541 else if(RCC_OscInitStruct->HSI14State == RCC_HSI14_ADC_CONTROL)
<> 144:ef7eb2e8f9f7 542 {
<> 144:ef7eb2e8f9f7 543 /* Enable ADC control of the Internal High Speed oscillator HSI14 */
<> 144:ef7eb2e8f9f7 544 __HAL_RCC_HSI14ADC_ENABLE();
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Adjusts the Internal High Speed oscillator 14Mhz (HSI14) calibration value. */
<> 144:ef7eb2e8f9f7 547 __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSI14CalibrationValue);
<> 144:ef7eb2e8f9f7 548 }
<> 144:ef7eb2e8f9f7 549 else
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 /* Disable ADC control of the Internal High Speed oscillator HSI14 */
<> 144:ef7eb2e8f9f7 552 __HAL_RCC_HSI14ADC_DISABLE();
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 555 __HAL_RCC_HSI14_DISABLE();
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 558 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 561 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI14RDY) != RESET)
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 if((HAL_GetTick() - tickstart) > HSI14_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 564 {
<> 144:ef7eb2e8f9f7 565 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 566 }
<> 144:ef7eb2e8f9f7 567 }
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569 }
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 572 /*----------------------------- HSI48 Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 573 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Check the parameters */
<> 144:ef7eb2e8f9f7 576 assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* When the HSI48 is used as system clock it is not allowed to be disabled */
<> 144:ef7eb2e8f9f7 579 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI48) ||
<> 144:ef7eb2e8f9f7 580 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI48)))
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) && (RCC_OscInitStruct->HSI48State != RCC_HSI48_ON))
<> 144:ef7eb2e8f9f7 583 {
<> 144:ef7eb2e8f9f7 584 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 585 }
<> 144:ef7eb2e8f9f7 586 }
<> 144:ef7eb2e8f9f7 587 else
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 /* Check the HSI48 State */
<> 144:ef7eb2e8f9f7 590 if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Enable the Internal High Speed oscillator (HSI48). */
<> 144:ef7eb2e8f9f7 593 __HAL_RCC_HSI48_ENABLE();
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 596 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Wait till HSI48 is ready */
<> 144:ef7eb2e8f9f7 599 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 602 {
<> 144:ef7eb2e8f9f7 603 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 604 }
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607 else
<> 144:ef7eb2e8f9f7 608 {
<> 144:ef7eb2e8f9f7 609 /* Disable the Internal High Speed oscillator (HSI48). */
<> 144:ef7eb2e8f9f7 610 __HAL_RCC_HSI48_DISABLE();
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 613 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615 /* Wait till HSI48 is ready */
<> 144:ef7eb2e8f9f7 616 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET)
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 619 {
<> 144:ef7eb2e8f9f7 620 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 621 }
<> 144:ef7eb2e8f9f7 622 }
<> 144:ef7eb2e8f9f7 623 }
<> 144:ef7eb2e8f9f7 624 }
<> 144:ef7eb2e8f9f7 625 }
<> 144:ef7eb2e8f9f7 626 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 629 /* Check the parameters */
<> 144:ef7eb2e8f9f7 630 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 631 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 632 {
<> 144:ef7eb2e8f9f7 633 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 634 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 637 {
<> 144:ef7eb2e8f9f7 638 /* Check the parameters */
<> 144:ef7eb2e8f9f7 639 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 640 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<> 144:ef7eb2e8f9f7 641 assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 644 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 647 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 650 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 653 {
<> 144:ef7eb2e8f9f7 654 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 655 }
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 /* Configure the main PLL clock source, predivider and multiplication factor. */
<> 144:ef7eb2e8f9f7 659 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 660 RCC_OscInitStruct->PLL.PREDIV,
<> 144:ef7eb2e8f9f7 661 RCC_OscInitStruct->PLL.PLLMUL);
<> 144:ef7eb2e8f9f7 662 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 663 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 666 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 669 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677 else
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 680 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 683 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 686 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 }
<> 144:ef7eb2e8f9f7 695 else
<> 144:ef7eb2e8f9f7 696 {
<> 144:ef7eb2e8f9f7 697 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 698 }
<> 144:ef7eb2e8f9f7 699 }
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 return HAL_OK;
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 /**
<> 144:ef7eb2e8f9f7 705 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<> 144:ef7eb2e8f9f7 706 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 707 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 708 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 709 * @param FLatency FLASH Latency
<> 144:ef7eb2e8f9f7 710 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 711 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 712 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 713 *
<> 144:ef7eb2e8f9f7 714 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 715 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 716 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 717 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 718 *
<> 144:ef7eb2e8f9f7 719 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 720 * clock source is ready (clock stable after start-up delay or PLL locked).
<> 144:ef7eb2e8f9f7 721 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 722 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 723 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
<> 144:ef7eb2e8f9f7 724 * currently used as system clock source.
<> 144:ef7eb2e8f9f7 725 * @retval HAL status
<> 144:ef7eb2e8f9f7 726 */
<> 144:ef7eb2e8f9f7 727 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 728 {
<> 156:95d6b41a828b 729 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /* Check the parameters */
<> 144:ef7eb2e8f9f7 732 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 733 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 734 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 737 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 738 (HCLK) of the device. */
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 741 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 742 {
<> 144:ef7eb2e8f9f7 743 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 744 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 747 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 748 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 755 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 756 {
<> 144:ef7eb2e8f9f7 757 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 758 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 759 }
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 762 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 763 {
<> 144:ef7eb2e8f9f7 764 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 767 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 768 {
<> 144:ef7eb2e8f9f7 769 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 770 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 771 {
<> 144:ef7eb2e8f9f7 772 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 773 }
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 776 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 779 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784 #if defined(RCC_CFGR_SWS_HSI48)
<> 144:ef7eb2e8f9f7 785 /* HSI48 is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 786 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 /* Check the HSI48 ready flag */
<> 144:ef7eb2e8f9f7 789 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET)
<> 144:ef7eb2e8f9f7 790 {
<> 144:ef7eb2e8f9f7 791 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 792 }
<> 144:ef7eb2e8f9f7 793 }
<> 144:ef7eb2e8f9f7 794 #endif /* RCC_CFGR_SWS_HSI48 */
<> 144:ef7eb2e8f9f7 795 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 796 else
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 799 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 807 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 814 {
<> 144:ef7eb2e8f9f7 815 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 }
<> 144:ef7eb2e8f9f7 818 }
<> 144:ef7eb2e8f9f7 819 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 820 {
<> 144:ef7eb2e8f9f7 821 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829 #if defined(RCC_CFGR_SWS_HSI48)
<> 144:ef7eb2e8f9f7 830 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI48)
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI48)
<> 144:ef7eb2e8f9f7 833 {
<> 144:ef7eb2e8f9f7 834 if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 #endif /* RCC_CFGR_SWS_HSI48 */
<> 144:ef7eb2e8f9f7 841 else
<> 144:ef7eb2e8f9f7 842 {
<> 144:ef7eb2e8f9f7 843 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 844 {
<> 144:ef7eb2e8f9f7 845 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 846 {
<> 144:ef7eb2e8f9f7 847 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 848 }
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 853 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 854 {
<> 144:ef7eb2e8f9f7 855 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 856 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 859 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 860 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 861 {
<> 144:ef7eb2e8f9f7 862 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 }
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 867 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 868 {
<> 144:ef7eb2e8f9f7 869 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 870 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 874 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 877 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 return HAL_OK;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /**
<> 144:ef7eb2e8f9f7 883 * @}
<> 144:ef7eb2e8f9f7 884 */
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 887 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 888 *
<> 144:ef7eb2e8f9f7 889 @verbatim
<> 144:ef7eb2e8f9f7 890 ===============================================================================
<> 144:ef7eb2e8f9f7 891 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 892 ===============================================================================
<> 144:ef7eb2e8f9f7 893 [..]
<> 144:ef7eb2e8f9f7 894 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 895 frequencies.
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 @endverbatim
<> 144:ef7eb2e8f9f7 898 * @{
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 902 /**
<> 144:ef7eb2e8f9f7 903 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 904 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 905 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 906 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 907 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 908 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 909 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 910 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
<> 144:ef7eb2e8f9f7 911 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
<> 144:ef7eb2e8f9f7 912 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 913 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 914 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 915 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 916 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
<> 144:ef7eb2e8f9f7 917 @if STM32F042x6
<> 144:ef7eb2e8f9f7 918 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 919 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 920 @elseif STM32F048xx
<> 144:ef7eb2e8f9f7 921 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 922 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 923 @elseif STM32F071xB
<> 144:ef7eb2e8f9f7 924 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 925 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 926 @elseif STM32F072xB
<> 144:ef7eb2e8f9f7 927 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 928 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 929 @elseif STM32F078xx
<> 144:ef7eb2e8f9f7 930 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 931 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 932 @elseif STM32F091xC
<> 144:ef7eb2e8f9f7 933 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 934 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 935 @elseif STM32F098xx
<> 144:ef7eb2e8f9f7 936 * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 selected as MCO clock
<> 144:ef7eb2e8f9f7 937 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 938 @elif STM32F030x6
<> 144:ef7eb2e8f9f7 939 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 940 @elif STM32F030xC
<> 144:ef7eb2e8f9f7 941 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 942 @elif STM32F031x6
<> 144:ef7eb2e8f9f7 943 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 944 @elif STM32F038xx
<> 144:ef7eb2e8f9f7 945 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 946 @elif STM32F070x6
<> 144:ef7eb2e8f9f7 947 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 948 @elif STM32F070xB
<> 144:ef7eb2e8f9f7 949 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 950 @endif
<> 144:ef7eb2e8f9f7 951 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 952 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 953 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 954 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 955 * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
<> 144:ef7eb2e8f9f7 956 * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
<> 144:ef7eb2e8f9f7 957 * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
<> 144:ef7eb2e8f9f7 958 * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
<> 144:ef7eb2e8f9f7 959 * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
<> 144:ef7eb2e8f9f7 960 * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
<> 144:ef7eb2e8f9f7 961 * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
<> 144:ef7eb2e8f9f7 962 * @retval None
<> 144:ef7eb2e8f9f7 963 */
<> 144:ef7eb2e8f9f7 964 #else
<> 144:ef7eb2e8f9f7 965 /**
<> 144:ef7eb2e8f9f7 966 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 967 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 968 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 969 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 970 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 971 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 972 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 973 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 974 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
<> 144:ef7eb2e8f9f7 975 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 976 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 977 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 978 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 979 * @arg @ref RCC_MCO1SOURCE_HSI14 HSI14 selected as MCO clock
<> 144:ef7eb2e8f9f7 980 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 981 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 982 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 983 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 984 * @retval None
<> 144:ef7eb2e8f9f7 985 */
<> 144:ef7eb2e8f9f7 986 #endif
<> 144:ef7eb2e8f9f7 987 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 988 {
<> 156:95d6b41a828b 989 GPIO_InitTypeDef gpio = {0U};
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /* Check the parameters */
<> 144:ef7eb2e8f9f7 992 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 993 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 994 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 997 gpio.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 998 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
<> 144:ef7eb2e8f9f7 999 gpio.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 1000 gpio.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 1001 gpio.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 1002
<> 144:ef7eb2e8f9f7 1003 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 1004 MCO1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Configure the MCO clock source */
<> 144:ef7eb2e8f9f7 1009 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /**
<> 144:ef7eb2e8f9f7 1013 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 1014 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 1015 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 1016 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 1017 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 1018 * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 1019 * @retval None
<> 144:ef7eb2e8f9f7 1020 */
<> 144:ef7eb2e8f9f7 1021 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 1022 {
<> 144:ef7eb2e8f9f7 1023 SET_BIT(RCC->CR, RCC_CR_CSSON) ;
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025
<> 144:ef7eb2e8f9f7 1026 /**
<> 144:ef7eb2e8f9f7 1027 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 1028 * @retval None
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 CLEAR_BIT(RCC->CR, RCC_CR_CSSON) ;
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /**
<> 144:ef7eb2e8f9f7 1036 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 1037 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 1038 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 1039 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 1040 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 1041 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 1042 * divided by PREDIV factor(**)
<> 144:ef7eb2e8f9f7 1043 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 1044 * divided by PREDIV factor(**) or depending on STM32F0xxxx devices either a value based
<> 144:ef7eb2e8f9f7 1045 * on HSI_VALUE divided by 2 or HSI_VALUE divided by PREDIV factor(*) multiplied by the
<> 144:ef7eb2e8f9f7 1046 * PLL factor.
<> 144:ef7eb2e8f9f7 1047 * @note (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 1048 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 1049 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 1050 * @note (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 1051 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 1052 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 1053 * have wrong result.
<> 144:ef7eb2e8f9f7 1054 *
<> 144:ef7eb2e8f9f7 1055 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 1056 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 1057 *
<> 144:ef7eb2e8f9f7 1058 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 1059 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 1060 *
<> 144:ef7eb2e8f9f7 1061 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1062 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1063 *
<> 144:ef7eb2e8f9f7 1064 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 1065 */
<> 144:ef7eb2e8f9f7 1066 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 1067 {
<> 156:95d6b41a828b 1068 const uint8_t aPLLMULFactorTable[16] = { 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
<> 156:95d6b41a828b 1069 10U, 11U, 12U, 13U, 14U, 15U, 16U, 16U};
<> 156:95d6b41a828b 1070 const uint8_t aPredivFactorTable[16] = { 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U,
<> 156:95d6b41a828b 1071 9U, 10U, 11U, 12U, 13U, 14U, 15U, 16U};
<> 144:ef7eb2e8f9f7 1072
<> 156:95d6b41a828b 1073 uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
<> 156:95d6b41a828b 1074 uint32_t sysclockfreq = 0U;
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 tmpreg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1079 switch (tmpreg & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 1084 break;
<> 144:ef7eb2e8f9f7 1085 }
<> 144:ef7eb2e8f9f7 1086 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 1087 {
<> 144:ef7eb2e8f9f7 1088 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> RCC_CFGR_PLLMUL_BITNUMBER];
<> 144:ef7eb2e8f9f7 1089 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> RCC_CFGR2_PREDIV_BITNUMBER];
<> 144:ef7eb2e8f9f7 1090 if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSE)
<> 144:ef7eb2e8f9f7 1091 {
<> 144:ef7eb2e8f9f7 1092 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1093 pllclk = (HSE_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1094 }
<> 144:ef7eb2e8f9f7 1095 #if defined(RCC_CFGR_PLLSRC_HSI48_PREDIV)
<> 144:ef7eb2e8f9f7 1096 else if ((tmpreg & RCC_CFGR_PLLSRC) == RCC_PLLSOURCE_HSI48)
<> 144:ef7eb2e8f9f7 1097 {
<> 144:ef7eb2e8f9f7 1098 /* HSI48 used as PLL clock source : PLLCLK = HSI48/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1099 pllclk = (HSI48_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1100 }
<> 144:ef7eb2e8f9f7 1101 #endif /* RCC_CFGR_PLLSRC_HSI48_PREDIV */
<> 144:ef7eb2e8f9f7 1102 else
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 #if (defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC))
<> 144:ef7eb2e8f9f7 1105 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 1106 pllclk = (HSI_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 1107 #else
<> 144:ef7eb2e8f9f7 1108 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 156:95d6b41a828b 1109 pllclk = (uint32_t)((HSI_VALUE >> 1U) * pllmul);
<> 144:ef7eb2e8f9f7 1110 #endif
<> 144:ef7eb2e8f9f7 1111 }
<> 144:ef7eb2e8f9f7 1112 sysclockfreq = pllclk;
<> 144:ef7eb2e8f9f7 1113 break;
<> 144:ef7eb2e8f9f7 1114 }
<> 144:ef7eb2e8f9f7 1115 #if defined(RCC_CFGR_SWS_HSI48)
<> 144:ef7eb2e8f9f7 1116 case RCC_SYSCLKSOURCE_STATUS_HSI48: /* HSI48 used as system clock source */
<> 144:ef7eb2e8f9f7 1117 {
<> 144:ef7eb2e8f9f7 1118 sysclockfreq = HSI48_VALUE;
<> 144:ef7eb2e8f9f7 1119 break;
<> 144:ef7eb2e8f9f7 1120 }
<> 144:ef7eb2e8f9f7 1121 #endif /* RCC_CFGR_SWS_HSI48 */
<> 144:ef7eb2e8f9f7 1122 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 1123 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 1124 {
<> 144:ef7eb2e8f9f7 1125 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 1126 break;
<> 144:ef7eb2e8f9f7 1127 }
<> 144:ef7eb2e8f9f7 1128 }
<> 144:ef7eb2e8f9f7 1129 return sysclockfreq;
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131
<> 144:ef7eb2e8f9f7 1132 /**
<> 144:ef7eb2e8f9f7 1133 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 1134 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1135 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1136 *
<> 144:ef7eb2e8f9f7 1137 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 1138 * and updated within this function
<> 144:ef7eb2e8f9f7 1139 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 1140 */
<> 144:ef7eb2e8f9f7 1141 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 1142 {
<> 144:ef7eb2e8f9f7 1143 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 1144 }
<> 144:ef7eb2e8f9f7 1145
<> 144:ef7eb2e8f9f7 1146 /**
<> 144:ef7eb2e8f9f7 1147 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 1148 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 1149 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 1150 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 1151 */
<> 144:ef7eb2e8f9f7 1152 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 1153 {
<> 144:ef7eb2e8f9f7 1154 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 1155 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1156 }
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /**
<> 144:ef7eb2e8f9f7 1159 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1160 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1161 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1162 * will be configured.
<> 144:ef7eb2e8f9f7 1163 * @retval None
<> 144:ef7eb2e8f9f7 1164 */
<> 144:ef7eb2e8f9f7 1165 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1168 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 1171 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
<> 144:ef7eb2e8f9f7 1172 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI14;
<> 144:ef7eb2e8f9f7 1173 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 1174 RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
<> 144:ef7eb2e8f9f7 1175 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177
<> 144:ef7eb2e8f9f7 1178 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1179 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 1180 {
<> 144:ef7eb2e8f9f7 1181 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 1182 }
<> 144:ef7eb2e8f9f7 1183 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 1184 {
<> 144:ef7eb2e8f9f7 1185 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 1186 }
<> 144:ef7eb2e8f9f7 1187 else
<> 144:ef7eb2e8f9f7 1188 {
<> 144:ef7eb2e8f9f7 1189 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1190 }
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1193 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1194 {
<> 144:ef7eb2e8f9f7 1195 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1196 }
<> 144:ef7eb2e8f9f7 1197 else
<> 144:ef7eb2e8f9f7 1198 {
<> 144:ef7eb2e8f9f7 1199 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1200 }
<> 144:ef7eb2e8f9f7 1201
<> 144:ef7eb2e8f9f7 1202 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_BitNumber);
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1205 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1206 {
<> 144:ef7eb2e8f9f7 1207 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1208 }
<> 144:ef7eb2e8f9f7 1209 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1210 {
<> 144:ef7eb2e8f9f7 1211 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213 else
<> 144:ef7eb2e8f9f7 1214 {
<> 144:ef7eb2e8f9f7 1215 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1216 }
<> 144:ef7eb2e8f9f7 1217
<> 144:ef7eb2e8f9f7 1218 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1219 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1220 {
<> 144:ef7eb2e8f9f7 1221 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1222 }
<> 144:ef7eb2e8f9f7 1223 else
<> 144:ef7eb2e8f9f7 1224 {
<> 144:ef7eb2e8f9f7 1225 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1226 }
<> 144:ef7eb2e8f9f7 1227
<> 144:ef7eb2e8f9f7 1228 /* Get the HSI14 configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1229 if((RCC->CR2 & RCC_CR2_HSI14ON) == RCC_CR2_HSI14ON)
<> 144:ef7eb2e8f9f7 1230 {
<> 144:ef7eb2e8f9f7 1231 RCC_OscInitStruct->HSI14State = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1232 }
<> 144:ef7eb2e8f9f7 1233 else
<> 144:ef7eb2e8f9f7 1234 {
<> 144:ef7eb2e8f9f7 1235 RCC_OscInitStruct->HSI14State = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1236 }
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 RCC_OscInitStruct->HSI14CalibrationValue = (uint32_t)((RCC->CR2 & RCC_CR2_HSI14TRIM) >> RCC_HSI14TRIM_BIT_NUMBER);
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 #if defined(RCC_HSI48_SUPPORT)
<> 144:ef7eb2e8f9f7 1241 /* Get the HSI48 configuration if any-----------------------------------------*/
<> 144:ef7eb2e8f9f7 1242 RCC_OscInitStruct->HSI48State = __HAL_RCC_GET_HSI48_STATE();
<> 144:ef7eb2e8f9f7 1243 #endif /* RCC_HSI48_SUPPORT */
<> 144:ef7eb2e8f9f7 1244
<> 144:ef7eb2e8f9f7 1245 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1246 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1247 {
<> 144:ef7eb2e8f9f7 1248 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1249 }
<> 144:ef7eb2e8f9f7 1250 else
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1253 }
<> 144:ef7eb2e8f9f7 1254 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1255 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
<> 144:ef7eb2e8f9f7 1256 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
<> 144:ef7eb2e8f9f7 1257 }
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /**
<> 144:ef7eb2e8f9f7 1260 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1261 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1262 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1263 * contains the current clock configuration.
<> 144:ef7eb2e8f9f7 1264 * @param pFLatency Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1265 * @retval None
<> 144:ef7eb2e8f9f7 1266 */
<> 144:ef7eb2e8f9f7 1267 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1268 {
<> 144:ef7eb2e8f9f7 1269 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1270 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1271 assert_param(pFLatency != NULL);
<> 144:ef7eb2e8f9f7 1272
<> 144:ef7eb2e8f9f7 1273 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1274 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1277 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1280 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1283 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE);
<> 144:ef7eb2e8f9f7 1284 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1285 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1286 }
<> 144:ef7eb2e8f9f7 1287
<> 144:ef7eb2e8f9f7 1288 /**
<> 144:ef7eb2e8f9f7 1289 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1290 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1291 * @retval None
<> 144:ef7eb2e8f9f7 1292 */
<> 144:ef7eb2e8f9f7 1293 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1294 {
<> 144:ef7eb2e8f9f7 1295 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1296 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1297 {
<> 144:ef7eb2e8f9f7 1298 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1299 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1302 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304 }
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /**
<> 144:ef7eb2e8f9f7 1307 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1308 * @retval none
<> 144:ef7eb2e8f9f7 1309 */
<> 144:ef7eb2e8f9f7 1310 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1311 {
<> 144:ef7eb2e8f9f7 1312 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1313 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315 }
<> 144:ef7eb2e8f9f7 1316
<> 144:ef7eb2e8f9f7 1317 /**
<> 144:ef7eb2e8f9f7 1318 * @}
<> 144:ef7eb2e8f9f7 1319 */
<> 144:ef7eb2e8f9f7 1320
<> 144:ef7eb2e8f9f7 1321 /**
<> 144:ef7eb2e8f9f7 1322 * @}
<> 144:ef7eb2e8f9f7 1323 */
<> 144:ef7eb2e8f9f7 1324
<> 144:ef7eb2e8f9f7 1325 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @}
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @}
<> 144:ef7eb2e8f9f7 1332 */
<> 144:ef7eb2e8f9f7 1333
<> 144:ef7eb2e8f9f7 1334 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/