mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_pwr.c@156:95d6b41a828b, 2017-01-16 (annotated)
- Committer:
- <>
- Date:
- Mon Jan 16 15:03:32 2017 +0000
- Revision:
- 156:95d6b41a828b
- Parent:
- 149:156823d33999
- Child:
- 180:96ed750bd169
This updates the lib to the mbed lib v134
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f0xx_hal_pwr.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 156:95d6b41a828b | 5 | * @version V1.5.0 |
<> | 156:95d6b41a828b | 6 | * @date 04-November-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief PWR HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Power Controller (PWR) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization/de-initialization function |
<> | 144:ef7eb2e8f9f7 | 11 | * + Peripheral Control function |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 15 | * @attention |
<> | 144:ef7eb2e8f9f7 | 16 | * |
<> | 144:ef7eb2e8f9f7 | 17 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 18 | * |
<> | 144:ef7eb2e8f9f7 | 19 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 20 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 21 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 22 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 23 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 24 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 25 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 26 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 27 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 28 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 29 | * |
<> | 144:ef7eb2e8f9f7 | 30 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 31 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 32 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 33 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 34 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 35 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 36 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 38 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 39 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 40 | * |
<> | 144:ef7eb2e8f9f7 | 41 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 42 | */ |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 45 | #include "stm32f0xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | /** @addtogroup STM32F0xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 48 | * @{ |
<> | 144:ef7eb2e8f9f7 | 49 | */ |
<> | 144:ef7eb2e8f9f7 | 50 | |
<> | 144:ef7eb2e8f9f7 | 51 | /** @defgroup PWR PWR |
<> | 144:ef7eb2e8f9f7 | 52 | * @brief PWR HAL module driver |
<> | 144:ef7eb2e8f9f7 | 53 | * @{ |
<> | 144:ef7eb2e8f9f7 | 54 | */ |
<> | 144:ef7eb2e8f9f7 | 55 | |
<> | 144:ef7eb2e8f9f7 | 56 | #ifdef HAL_PWR_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 57 | |
<> | 144:ef7eb2e8f9f7 | 58 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 59 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 60 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 61 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 62 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 63 | /* Private functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 64 | |
<> | 144:ef7eb2e8f9f7 | 65 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
<> | 144:ef7eb2e8f9f7 | 66 | * @{ |
<> | 144:ef7eb2e8f9f7 | 67 | */ |
<> | 144:ef7eb2e8f9f7 | 68 | |
<> | 144:ef7eb2e8f9f7 | 69 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 70 | * @brief Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 73 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 74 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 75 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 76 | [..] |
<> | 144:ef7eb2e8f9f7 | 77 | After reset, the backup domain (RTC registers, RTC backup data |
<> | 144:ef7eb2e8f9f7 | 78 | registers) is protected against possible unwanted |
<> | 144:ef7eb2e8f9f7 | 79 | write accesses. |
<> | 144:ef7eb2e8f9f7 | 80 | To enable access to the RTC Domain and RTC registers, proceed as follows: |
<> | 144:ef7eb2e8f9f7 | 81 | (+) Enable the Power Controller (PWR) APB1 interface clock using the |
<> | 144:ef7eb2e8f9f7 | 82 | __HAL_RCC_PWR_CLK_ENABLE() macro. |
<> | 144:ef7eb2e8f9f7 | 83 | (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. |
<> | 144:ef7eb2e8f9f7 | 84 | |
<> | 144:ef7eb2e8f9f7 | 85 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 86 | * @{ |
<> | 144:ef7eb2e8f9f7 | 87 | */ |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | /** |
<> | 144:ef7eb2e8f9f7 | 90 | * @brief Deinitializes the PWR peripheral registers to their default reset values. |
<> | 144:ef7eb2e8f9f7 | 91 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 92 | */ |
<> | 144:ef7eb2e8f9f7 | 93 | void HAL_PWR_DeInit(void) |
<> | 144:ef7eb2e8f9f7 | 94 | { |
<> | 144:ef7eb2e8f9f7 | 95 | __HAL_RCC_PWR_FORCE_RESET(); |
<> | 144:ef7eb2e8f9f7 | 96 | __HAL_RCC_PWR_RELEASE_RESET(); |
<> | 144:ef7eb2e8f9f7 | 97 | } |
<> | 144:ef7eb2e8f9f7 | 98 | |
<> | 144:ef7eb2e8f9f7 | 99 | /** |
<> | 144:ef7eb2e8f9f7 | 100 | * @brief Enables access to the backup domain (RTC registers, RTC |
<> | 144:ef7eb2e8f9f7 | 101 | * backup data registers when present). |
<> | 144:ef7eb2e8f9f7 | 102 | * @note If the HSE divided by 32 is used as the RTC clock, the |
<> | 144:ef7eb2e8f9f7 | 103 | * Backup Domain Access should be kept enabled. |
<> | 144:ef7eb2e8f9f7 | 104 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 105 | */ |
<> | 144:ef7eb2e8f9f7 | 106 | void HAL_PWR_EnableBkUpAccess(void) |
<> | 144:ef7eb2e8f9f7 | 107 | { |
<> | 144:ef7eb2e8f9f7 | 108 | PWR->CR |= (uint32_t)PWR_CR_DBP; |
<> | 144:ef7eb2e8f9f7 | 109 | } |
<> | 144:ef7eb2e8f9f7 | 110 | |
<> | 144:ef7eb2e8f9f7 | 111 | /** |
<> | 144:ef7eb2e8f9f7 | 112 | * @brief Disables access to the backup domain (RTC registers, RTC |
<> | 144:ef7eb2e8f9f7 | 113 | * backup data registers when present). |
<> | 144:ef7eb2e8f9f7 | 114 | * @note If the HSE divided by 32 is used as the RTC clock, the |
<> | 144:ef7eb2e8f9f7 | 115 | * Backup Domain Access should be kept enabled. |
<> | 144:ef7eb2e8f9f7 | 116 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 117 | */ |
<> | 144:ef7eb2e8f9f7 | 118 | void HAL_PWR_DisableBkUpAccess(void) |
<> | 144:ef7eb2e8f9f7 | 119 | { |
<> | 144:ef7eb2e8f9f7 | 120 | PWR->CR &= ~((uint32_t)PWR_CR_DBP); |
<> | 144:ef7eb2e8f9f7 | 121 | } |
<> | 144:ef7eb2e8f9f7 | 122 | |
<> | 144:ef7eb2e8f9f7 | 123 | /** |
<> | 144:ef7eb2e8f9f7 | 124 | * @} |
<> | 144:ef7eb2e8f9f7 | 125 | */ |
<> | 144:ef7eb2e8f9f7 | 126 | |
<> | 144:ef7eb2e8f9f7 | 127 | /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 128 | * @brief Low Power modes configuration functions |
<> | 144:ef7eb2e8f9f7 | 129 | * |
<> | 144:ef7eb2e8f9f7 | 130 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 131 | |
<> | 144:ef7eb2e8f9f7 | 132 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 133 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 134 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | *** WakeUp pin configuration *** |
<> | 144:ef7eb2e8f9f7 | 137 | ================================ |
<> | 144:ef7eb2e8f9f7 | 138 | [..] |
<> | 144:ef7eb2e8f9f7 | 139 | (+) WakeUp pin is used to wakeup the system from Standby mode. This pin is |
<> | 144:ef7eb2e8f9f7 | 140 | forced in input pull down configuration and is active on rising edges. |
<> | 144:ef7eb2e8f9f7 | 141 | (+) There are two WakeUp pins, and up to eight Wakeup pins on STM32F07x & STM32F09x devices. |
<> | 144:ef7eb2e8f9f7 | 142 | (++)WakeUp Pin 1 on PA.00. |
<> | 144:ef7eb2e8f9f7 | 143 | (++)WakeUp Pin 2 on PC.13. |
<> | 144:ef7eb2e8f9f7 | 144 | (++)WakeUp Pin 3 on PE.06.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 145 | (++)WakeUp Pin 4 on PA.02.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 146 | (++)WakeUp Pin 5 on PC.05.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 147 | (++)WakeUp Pin 6 on PB.05.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 148 | (++)WakeUp Pin 7 on PB.15.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 149 | (++)WakeUp Pin 8 on PF.02.(STM32F07x/STM32F09x) |
<> | 144:ef7eb2e8f9f7 | 150 | |
<> | 144:ef7eb2e8f9f7 | 151 | *** Low Power modes configuration *** |
<> | 144:ef7eb2e8f9f7 | 152 | ===================================== |
<> | 144:ef7eb2e8f9f7 | 153 | [..] |
<> | 144:ef7eb2e8f9f7 | 154 | The devices feature 3 low-power modes: |
<> | 144:ef7eb2e8f9f7 | 155 | (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running. |
<> | 144:ef7eb2e8f9f7 | 156 | (+) Stop mode: all clocks are stopped, regulator running, regulator |
<> | 144:ef7eb2e8f9f7 | 157 | in low power mode |
<> | 144:ef7eb2e8f9f7 | 158 | (+) Standby mode: 1.2V domain powered off (mode not available on STM32F0x8 devices). |
<> | 144:ef7eb2e8f9f7 | 159 | |
<> | 144:ef7eb2e8f9f7 | 160 | *** Sleep mode *** |
<> | 144:ef7eb2e8f9f7 | 161 | ================== |
<> | 144:ef7eb2e8f9f7 | 162 | [..] |
<> | 144:ef7eb2e8f9f7 | 163 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 164 | The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx) |
<> | 144:ef7eb2e8f9f7 | 165 | functions with |
<> | 144:ef7eb2e8f9f7 | 166 | (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 167 | (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 170 | (++) Any peripheral interrupt acknowledged by the nested vectored interrupt |
<> | 144:ef7eb2e8f9f7 | 171 | controller (NVIC) can wake up the device from Sleep mode. |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | *** Stop mode *** |
<> | 144:ef7eb2e8f9f7 | 174 | ================= |
<> | 144:ef7eb2e8f9f7 | 175 | [..] |
<> | 144:ef7eb2e8f9f7 | 176 | In Stop mode, all clocks in the 1.8V domain are stopped, the PLL, the HSI, |
<> | 144:ef7eb2e8f9f7 | 177 | and the HSE RC oscillators are disabled. Internal SRAM and register contents |
<> | 144:ef7eb2e8f9f7 | 178 | are preserved. |
<> | 144:ef7eb2e8f9f7 | 179 | The voltage regulator can be configured either in normal or low-power mode. |
<> | 144:ef7eb2e8f9f7 | 180 | To minimize the consumption. |
<> | 144:ef7eb2e8f9f7 | 181 | |
<> | 144:ef7eb2e8f9f7 | 182 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 183 | The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_STOPENTRY_WFI ) |
<> | 144:ef7eb2e8f9f7 | 184 | function with: |
<> | 144:ef7eb2e8f9f7 | 185 | (++) Main regulator ON. |
<> | 144:ef7eb2e8f9f7 | 186 | (++) Low Power regulator ON. |
<> | 144:ef7eb2e8f9f7 | 187 | (++) PWR_STOPENTRY_WFI: enter STOP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 188 | (++) PWR_STOPENTRY_WFE: enter STOP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 189 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 190 | (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode. |
<> | 144:ef7eb2e8f9f7 | 191 | (++) Some specific communication peripherals (CEC, USART, I2C) interrupts, |
<> | 144:ef7eb2e8f9f7 | 192 | when programmed in wakeup mode (the peripheral must be |
<> | 144:ef7eb2e8f9f7 | 193 | programmed in wakeup mode and the corresponding interrupt vector |
<> | 144:ef7eb2e8f9f7 | 194 | must be enabled in the NVIC) |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | *** Standby mode *** |
<> | 144:ef7eb2e8f9f7 | 197 | ==================== |
<> | 144:ef7eb2e8f9f7 | 198 | [..] |
<> | 144:ef7eb2e8f9f7 | 199 | The Standby mode allows to achieve the lowest power consumption. It is based |
<> | 144:ef7eb2e8f9f7 | 200 | on the Cortex-M0 deep sleep mode, with the voltage regulator disabled. |
<> | 144:ef7eb2e8f9f7 | 201 | The 1.8V domain is consequently powered off. The PLL, the HSI oscillator and |
<> | 144:ef7eb2e8f9f7 | 202 | the HSE oscillator are also switched off. SRAM and register contents are lost |
<> | 144:ef7eb2e8f9f7 | 203 | except for the RTC registers, RTC backup registers and Standby circuitry. |
<> | 144:ef7eb2e8f9f7 | 204 | The voltage regulator is OFF. |
<> | 144:ef7eb2e8f9f7 | 205 | |
<> | 144:ef7eb2e8f9f7 | 206 | (+) Entry: |
<> | 144:ef7eb2e8f9f7 | 207 | (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. |
<> | 144:ef7eb2e8f9f7 | 208 | (+) Exit: |
<> | 144:ef7eb2e8f9f7 | 209 | (++) WKUP pin rising edge, RTC alarm (Alarm A), RTC wakeup, |
<> | 144:ef7eb2e8f9f7 | 210 | tamper event, time-stamp event, external reset in NRST pin, IWDG reset. |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | *** Auto-wakeup (AWU) from low-power mode *** |
<> | 144:ef7eb2e8f9f7 | 213 | ============================================= |
<> | 144:ef7eb2e8f9f7 | 214 | [..] |
<> | 144:ef7eb2e8f9f7 | 215 | The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC |
<> | 144:ef7eb2e8f9f7 | 216 | Wakeup event, a tamper event, a time-stamp event, or a comparator event, |
<> | 144:ef7eb2e8f9f7 | 217 | without depending on an external interrupt (Auto-wakeup mode). |
<> | 144:ef7eb2e8f9f7 | 218 | |
<> | 144:ef7eb2e8f9f7 | 219 | (+) RTC auto-wakeup (AWU) from the Stop and Standby modes |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to |
<> | 144:ef7eb2e8f9f7 | 222 | configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. |
<> | 144:ef7eb2e8f9f7 | 223 | |
<> | 144:ef7eb2e8f9f7 | 224 | (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it |
<> | 144:ef7eb2e8f9f7 | 225 | is necessary to configure the RTC to detect the tamper or time stamp event using the |
<> | 144:ef7eb2e8f9f7 | 226 | HAL_RTC_SetTimeStamp_IT() or HAL_RTC_SetTamper_IT() functions. |
<> | 144:ef7eb2e8f9f7 | 227 | |
<> | 144:ef7eb2e8f9f7 | 228 | (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to |
<> | 144:ef7eb2e8f9f7 | 229 | configure the RTC to generate the RTC WakeUp event using the HAL_RTC_SetWakeUpTimer_IT() function. |
<> | 144:ef7eb2e8f9f7 | 230 | |
<> | 144:ef7eb2e8f9f7 | 231 | (+) Comparator auto-wakeup (AWU) from the Stop mode |
<> | 144:ef7eb2e8f9f7 | 232 | |
<> | 144:ef7eb2e8f9f7 | 233 | (++) To wake up from the Stop mode with a comparator wakeup event, it is necessary to: |
<> | 144:ef7eb2e8f9f7 | 234 | (+++) Configure the EXTI Line associated with the comparator (example EXTI Line 22 for comparator 2) |
<> | 144:ef7eb2e8f9f7 | 235 | to be sensitive to to the selected edges (falling, rising or falling |
<> | 144:ef7eb2e8f9f7 | 236 | and rising) (Interrupt or Event modes) using the EXTI_Init() function. |
<> | 144:ef7eb2e8f9f7 | 237 | (+++) Configure the comparator to generate the event. |
<> | 144:ef7eb2e8f9f7 | 238 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 239 | * @{ |
<> | 144:ef7eb2e8f9f7 | 240 | */ |
<> | 144:ef7eb2e8f9f7 | 241 | |
<> | 144:ef7eb2e8f9f7 | 242 | /** |
<> | 144:ef7eb2e8f9f7 | 243 | * @brief Enables the WakeUp PINx functionality. |
<> | 144:ef7eb2e8f9f7 | 244 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable. |
<> | 144:ef7eb2e8f9f7 | 245 | * This parameter can be value of : |
<> | 144:ef7eb2e8f9f7 | 246 | * @ref PWREx_WakeUp_Pins |
<> | 144:ef7eb2e8f9f7 | 247 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 248 | */ |
<> | 144:ef7eb2e8f9f7 | 249 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) |
<> | 144:ef7eb2e8f9f7 | 250 | { |
<> | 144:ef7eb2e8f9f7 | 251 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 252 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
<> | 144:ef7eb2e8f9f7 | 253 | /* Enable the EWUPx pin */ |
<> | 144:ef7eb2e8f9f7 | 254 | SET_BIT(PWR->CSR, WakeUpPinx); |
<> | 144:ef7eb2e8f9f7 | 255 | } |
<> | 144:ef7eb2e8f9f7 | 256 | |
<> | 144:ef7eb2e8f9f7 | 257 | /** |
<> | 144:ef7eb2e8f9f7 | 258 | * @brief Disables the WakeUp PINx functionality. |
<> | 144:ef7eb2e8f9f7 | 259 | * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable. |
<> | 144:ef7eb2e8f9f7 | 260 | * This parameter can be values of : |
<> | 144:ef7eb2e8f9f7 | 261 | * @ref PWREx_WakeUp_Pins |
<> | 144:ef7eb2e8f9f7 | 262 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 263 | */ |
<> | 144:ef7eb2e8f9f7 | 264 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) |
<> | 144:ef7eb2e8f9f7 | 265 | { |
<> | 144:ef7eb2e8f9f7 | 266 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 267 | assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); |
<> | 144:ef7eb2e8f9f7 | 268 | /* Disable the EWUPx pin */ |
<> | 144:ef7eb2e8f9f7 | 269 | CLEAR_BIT(PWR->CSR, WakeUpPinx); |
<> | 144:ef7eb2e8f9f7 | 270 | } |
<> | 144:ef7eb2e8f9f7 | 271 | |
<> | 144:ef7eb2e8f9f7 | 272 | /** |
<> | 144:ef7eb2e8f9f7 | 273 | * @brief Enters Sleep mode. |
<> | 144:ef7eb2e8f9f7 | 274 | * @note In Sleep mode, all I/O pins keep the same state as in Run mode. |
<> | 144:ef7eb2e8f9f7 | 275 | * @param Regulator: Specifies the regulator state in SLEEP mode. |
<> | 144:ef7eb2e8f9f7 | 276 | * On STM32F0 devices, this parameter is a dummy value and it is ignored |
<> | 144:ef7eb2e8f9f7 | 277 | * as regulator can't be modified in this mode. Parameter is kept for platform |
<> | 144:ef7eb2e8f9f7 | 278 | * compatibility. |
<> | 144:ef7eb2e8f9f7 | 279 | * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction. |
<> | 144:ef7eb2e8f9f7 | 280 | * When WFI entry is used, tick interrupt have to be disabled if not desired as |
<> | 144:ef7eb2e8f9f7 | 281 | * the interrupt wake up source. |
<> | 144:ef7eb2e8f9f7 | 282 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 283 | * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 284 | * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 285 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 286 | */ |
<> | 144:ef7eb2e8f9f7 | 287 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) |
<> | 144:ef7eb2e8f9f7 | 288 | { |
<> | 144:ef7eb2e8f9f7 | 289 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 290 | assert_param(IS_PWR_REGULATOR(Regulator)); |
<> | 144:ef7eb2e8f9f7 | 291 | assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /* Clear SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 294 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
<> | 144:ef7eb2e8f9f7 | 295 | |
<> | 144:ef7eb2e8f9f7 | 296 | /* Select SLEEP mode entry -------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 297 | if(SLEEPEntry == PWR_SLEEPENTRY_WFI) |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 300 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 301 | } |
<> | 144:ef7eb2e8f9f7 | 302 | else |
<> | 144:ef7eb2e8f9f7 | 303 | { |
<> | 144:ef7eb2e8f9f7 | 304 | /* Request Wait For Event */ |
<> | 144:ef7eb2e8f9f7 | 305 | __SEV(); |
<> | 144:ef7eb2e8f9f7 | 306 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 307 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 308 | } |
<> | 144:ef7eb2e8f9f7 | 309 | } |
<> | 144:ef7eb2e8f9f7 | 310 | |
<> | 144:ef7eb2e8f9f7 | 311 | /** |
<> | 144:ef7eb2e8f9f7 | 312 | * @brief Enters STOP mode. |
<> | 144:ef7eb2e8f9f7 | 313 | * @note In Stop mode, all I/O pins keep the same state as in Run mode. |
<> | 144:ef7eb2e8f9f7 | 314 | * @note When exiting Stop mode by issuing an interrupt or a wakeup event, |
<> | 144:ef7eb2e8f9f7 | 315 | * the HSI RC oscillator is selected as system clock. |
<> | 144:ef7eb2e8f9f7 | 316 | * @note When the voltage regulator operates in low power mode, an additional |
<> | 144:ef7eb2e8f9f7 | 317 | * startup delay is incurred when waking up from Stop mode. |
<> | 144:ef7eb2e8f9f7 | 318 | * By keeping the internal regulator ON during Stop mode, the consumption |
<> | 144:ef7eb2e8f9f7 | 319 | * is higher although the startup time is reduced. |
<> | 144:ef7eb2e8f9f7 | 320 | * @param Regulator: Specifies the regulator state in STOP mode. |
<> | 144:ef7eb2e8f9f7 | 321 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 322 | * @arg PWR_MAINREGULATOR_ON: STOP mode with regulator ON |
<> | 144:ef7eb2e8f9f7 | 323 | * @arg PWR_LOWPOWERREGULATOR_ON: STOP mode with low power regulator ON |
<> | 144:ef7eb2e8f9f7 | 324 | * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. |
<> | 144:ef7eb2e8f9f7 | 325 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 326 | * @arg PWR_STOPENTRY_WFI:Enter STOP mode with WFI instruction |
<> | 144:ef7eb2e8f9f7 | 327 | * @arg PWR_STOPENTRY_WFE: Enter STOP mode with WFE instruction |
<> | 144:ef7eb2e8f9f7 | 328 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 329 | */ |
<> | 144:ef7eb2e8f9f7 | 330 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) |
<> | 144:ef7eb2e8f9f7 | 331 | { |
<> | 144:ef7eb2e8f9f7 | 332 | uint32_t tmpreg = 0; |
<> | 144:ef7eb2e8f9f7 | 333 | |
<> | 144:ef7eb2e8f9f7 | 334 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 335 | assert_param(IS_PWR_REGULATOR(Regulator)); |
<> | 144:ef7eb2e8f9f7 | 336 | assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); |
<> | 144:ef7eb2e8f9f7 | 337 | |
<> | 144:ef7eb2e8f9f7 | 338 | /* Select the regulator state in STOP mode ---------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 339 | tmpreg = PWR->CR; |
<> | 144:ef7eb2e8f9f7 | 340 | |
<> | 144:ef7eb2e8f9f7 | 341 | /* Clear PDDS and LPDS bits */ |
<> | 144:ef7eb2e8f9f7 | 342 | tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS); |
<> | 144:ef7eb2e8f9f7 | 343 | |
<> | 144:ef7eb2e8f9f7 | 344 | /* Set LPDS bit according to Regulator value */ |
<> | 144:ef7eb2e8f9f7 | 345 | tmpreg |= Regulator; |
<> | 144:ef7eb2e8f9f7 | 346 | |
<> | 144:ef7eb2e8f9f7 | 347 | /* Store the new value */ |
<> | 144:ef7eb2e8f9f7 | 348 | PWR->CR = tmpreg; |
<> | 144:ef7eb2e8f9f7 | 349 | |
<> | 144:ef7eb2e8f9f7 | 350 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 351 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | /* Select STOP mode entry --------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 354 | if(STOPEntry == PWR_STOPENTRY_WFI) |
<> | 144:ef7eb2e8f9f7 | 355 | { |
<> | 144:ef7eb2e8f9f7 | 356 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 357 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 358 | } |
<> | 144:ef7eb2e8f9f7 | 359 | else |
<> | 144:ef7eb2e8f9f7 | 360 | { |
<> | 144:ef7eb2e8f9f7 | 361 | /* Request Wait For Event */ |
<> | 144:ef7eb2e8f9f7 | 362 | __SEV(); |
<> | 144:ef7eb2e8f9f7 | 363 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 364 | __WFE(); |
<> | 144:ef7eb2e8f9f7 | 365 | } |
<> | 144:ef7eb2e8f9f7 | 366 | |
<> | 144:ef7eb2e8f9f7 | 367 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 368 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); |
<> | 144:ef7eb2e8f9f7 | 369 | } |
<> | 144:ef7eb2e8f9f7 | 370 | |
<> | 144:ef7eb2e8f9f7 | 371 | /** |
<> | 144:ef7eb2e8f9f7 | 372 | * @brief Enters STANDBY mode. |
<> | 144:ef7eb2e8f9f7 | 373 | * @note In Standby mode, all I/O pins are high impedance except for: |
<> | 144:ef7eb2e8f9f7 | 374 | * - Reset pad (still available) |
<> | 144:ef7eb2e8f9f7 | 375 | * - RTC alternate function pins if configured for tamper, time-stamp, RTC |
<> | 144:ef7eb2e8f9f7 | 376 | * Alarm out, or RTC clock calibration out. |
<> | 144:ef7eb2e8f9f7 | 377 | * - WKUP pins if enabled. |
<> | 144:ef7eb2e8f9f7 | 378 | * STM32F0x8 devices, the Stop mode is available, but it is |
<> | 144:ef7eb2e8f9f7 | 379 | * aningless to distinguish between voltage regulator in Low power |
<> | 144:ef7eb2e8f9f7 | 380 | * mode and voltage regulator in Run mode because the regulator |
<> | 144:ef7eb2e8f9f7 | 381 | * not used and the core is supplied directly from an external source. |
<> | 144:ef7eb2e8f9f7 | 382 | * Consequently, the Standby mode is not available on those devices. |
<> | 144:ef7eb2e8f9f7 | 383 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 384 | */ |
<> | 144:ef7eb2e8f9f7 | 385 | void HAL_PWR_EnterSTANDBYMode(void) |
<> | 144:ef7eb2e8f9f7 | 386 | { |
<> | 144:ef7eb2e8f9f7 | 387 | /* Select STANDBY mode */ |
<> | 144:ef7eb2e8f9f7 | 388 | PWR->CR |= (uint32_t)PWR_CR_PDDS; |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | /* Set SLEEPDEEP bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 391 | SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; |
<> | 144:ef7eb2e8f9f7 | 392 | |
<> | 144:ef7eb2e8f9f7 | 393 | /* This option is used to ensure that store operations are completed */ |
<> | 144:ef7eb2e8f9f7 | 394 | #if defined ( __CC_ARM) |
<> | 144:ef7eb2e8f9f7 | 395 | __force_stores(); |
<> | 144:ef7eb2e8f9f7 | 396 | #endif |
<> | 144:ef7eb2e8f9f7 | 397 | /* Request Wait For Interrupt */ |
<> | 144:ef7eb2e8f9f7 | 398 | __WFI(); |
<> | 144:ef7eb2e8f9f7 | 399 | } |
<> | 144:ef7eb2e8f9f7 | 400 | |
<> | 144:ef7eb2e8f9f7 | 401 | /** |
<> | 144:ef7eb2e8f9f7 | 402 | * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. |
<> | 144:ef7eb2e8f9f7 | 403 | * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
<> | 144:ef7eb2e8f9f7 | 404 | * re-enters SLEEP mode when an interruption handling is over. |
<> | 144:ef7eb2e8f9f7 | 405 | * Setting this bit is useful when the processor is expected to run only on |
<> | 144:ef7eb2e8f9f7 | 406 | * interruptions handling. |
<> | 144:ef7eb2e8f9f7 | 407 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 408 | */ |
<> | 144:ef7eb2e8f9f7 | 409 | void HAL_PWR_EnableSleepOnExit(void) |
<> | 144:ef7eb2e8f9f7 | 410 | { |
<> | 144:ef7eb2e8f9f7 | 411 | /* Set SLEEPONEXIT bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 412 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
<> | 144:ef7eb2e8f9f7 | 413 | } |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | |
<> | 144:ef7eb2e8f9f7 | 416 | /** |
<> | 144:ef7eb2e8f9f7 | 417 | * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. |
<> | 144:ef7eb2e8f9f7 | 418 | * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor |
<> | 144:ef7eb2e8f9f7 | 419 | * re-enters SLEEP mode when an interruption handling is over. |
<> | 144:ef7eb2e8f9f7 | 420 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 421 | */ |
<> | 144:ef7eb2e8f9f7 | 422 | void HAL_PWR_DisableSleepOnExit(void) |
<> | 144:ef7eb2e8f9f7 | 423 | { |
<> | 144:ef7eb2e8f9f7 | 424 | /* Clear SLEEPONEXIT bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 425 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | |
<> | 144:ef7eb2e8f9f7 | 428 | |
<> | 144:ef7eb2e8f9f7 | 429 | |
<> | 144:ef7eb2e8f9f7 | 430 | /** |
<> | 144:ef7eb2e8f9f7 | 431 | * @brief Enables CORTEX M4 SEVONPEND bit. |
<> | 144:ef7eb2e8f9f7 | 432 | * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes |
<> | 144:ef7eb2e8f9f7 | 433 | * WFE to wake up when an interrupt moves from inactive to pended. |
<> | 144:ef7eb2e8f9f7 | 434 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 435 | */ |
<> | 144:ef7eb2e8f9f7 | 436 | void HAL_PWR_EnableSEVOnPend(void) |
<> | 144:ef7eb2e8f9f7 | 437 | { |
<> | 144:ef7eb2e8f9f7 | 438 | /* Set SEVONPEND bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 439 | SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
<> | 144:ef7eb2e8f9f7 | 440 | } |
<> | 144:ef7eb2e8f9f7 | 441 | |
<> | 144:ef7eb2e8f9f7 | 442 | |
<> | 144:ef7eb2e8f9f7 | 443 | /** |
<> | 144:ef7eb2e8f9f7 | 444 | * @brief Disables CORTEX M4 SEVONPEND bit. |
<> | 144:ef7eb2e8f9f7 | 445 | * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes |
<> | 144:ef7eb2e8f9f7 | 446 | * WFE to wake up when an interrupt moves from inactive to pended. |
<> | 144:ef7eb2e8f9f7 | 447 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 448 | */ |
<> | 144:ef7eb2e8f9f7 | 449 | void HAL_PWR_DisableSEVOnPend(void) |
<> | 144:ef7eb2e8f9f7 | 450 | { |
<> | 144:ef7eb2e8f9f7 | 451 | /* Clear SEVONPEND bit of Cortex System Control Register */ |
<> | 144:ef7eb2e8f9f7 | 452 | CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); |
<> | 144:ef7eb2e8f9f7 | 453 | } |
<> | 144:ef7eb2e8f9f7 | 454 | |
<> | 144:ef7eb2e8f9f7 | 455 | /** |
<> | 144:ef7eb2e8f9f7 | 456 | * @} |
<> | 144:ef7eb2e8f9f7 | 457 | */ |
<> | 144:ef7eb2e8f9f7 | 458 | |
<> | 144:ef7eb2e8f9f7 | 459 | /** |
<> | 144:ef7eb2e8f9f7 | 460 | * @} |
<> | 144:ef7eb2e8f9f7 | 461 | */ |
<> | 144:ef7eb2e8f9f7 | 462 | |
<> | 144:ef7eb2e8f9f7 | 463 | #endif /* HAL_PWR_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 464 | /** |
<> | 144:ef7eb2e8f9f7 | 465 | * @} |
<> | 144:ef7eb2e8f9f7 | 466 | */ |
<> | 144:ef7eb2e8f9f7 | 467 | |
<> | 144:ef7eb2e8f9f7 | 468 | /** |
<> | 144:ef7eb2e8f9f7 | 469 | * @} |
<> | 144:ef7eb2e8f9f7 | 470 | */ |
<> | 144:ef7eb2e8f9f7 | 471 | |
<> | 144:ef7eb2e8f9f7 | 472 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |