mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2s.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_i2s.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of I2S HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_I2S_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined(STM32F031x6) || defined(STM32F038xx) || \
<> 144:ef7eb2e8f9f7 47 defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 48 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 49 defined(STM32F042x6) || defined(STM32F048xx) || \
<> 144:ef7eb2e8f9f7 50 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 53 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @addtogroup I2S
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 64 /** @defgroup I2S_Exported_Types I2S Exported Types
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /**
<> 144:ef7eb2e8f9f7 69 * @brief I2S Init structure definition
<> 144:ef7eb2e8f9f7 70 */
<> 144:ef7eb2e8f9f7 71 typedef struct
<> 144:ef7eb2e8f9f7 72 {
<> 144:ef7eb2e8f9f7 73 uint32_t Mode; /*!< Specifies the I2S operating mode.
<> 144:ef7eb2e8f9f7 74 This parameter can be a value of @ref I2S_Mode */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
<> 144:ef7eb2e8f9f7 77 This parameter can be a value of @ref I2S_Standard */
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
<> 144:ef7eb2e8f9f7 80 This parameter can be a value of @ref I2S_Data_Format */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
<> 144:ef7eb2e8f9f7 83 This parameter can be a value of @ref I2S_MCLK_Output */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
<> 144:ef7eb2e8f9f7 86 This parameter can be a value of @ref I2S_Audio_Frequency */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
<> 144:ef7eb2e8f9f7 89 This parameter can be a value of @ref I2S_Clock_Polarity */
<> 144:ef7eb2e8f9f7 90 }I2S_InitTypeDef;
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95 typedef enum
<> 144:ef7eb2e8f9f7 96 {
<> 156:95d6b41a828b 97 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
<> 156:95d6b41a828b 98 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
<> 156:95d6b41a828b 99 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
<> 156:95d6b41a828b 100 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
<> 156:95d6b41a828b 101 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
<> 156:95d6b41a828b 102 HAL_I2S_STATE_PAUSE = 0x06U, /*!< I2S pause state: used in case of DMA */
<> 156:95d6b41a828b 103 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
<> 144:ef7eb2e8f9f7 104 }HAL_I2S_StateTypeDef;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @brief I2S handle Structure definition
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109 typedef struct
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 SPI_TypeDef *Instance; /*!< I2S registers base address */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 I2S_InitTypeDef Init; /*!< I2S communication parameters */
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
<> 144:ef7eb2e8f9f7 126 (This field is initialized at the
<> 144:ef7eb2e8f9f7 127 same value as transfer size at the
<> 144:ef7eb2e8f9f7 128 beginning of the transfer and
<> 144:ef7eb2e8f9f7 129 decremented when a sample is received.
<> 144:ef7eb2e8f9f7 130 NbSamplesReceived = RxBufferSize-RxBufferCount) */
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 __IO uint32_t ErrorCode; /*!< I2S Error code
<> 144:ef7eb2e8f9f7 141 This parameter can be a value of @ref I2S_Error */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 }I2S_HandleTypeDef;
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @}
<> 144:ef7eb2e8f9f7 146 */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup I2S_Exported_Constants I2S Exported Constants
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /** @defgroup I2S_Error I2S Error
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 156:95d6b41a828b 155 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 156 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
<> 156:95d6b41a828b 157 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
<> 156:95d6b41a828b 158 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
<> 156:95d6b41a828b 159 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
<> 156:95d6b41a828b 160 #define HAL_I2S_ERROR_UNKNOW (0x00000010U) /*!< Unknow Error error */
<> 144:ef7eb2e8f9f7 161 /**
<> 144:ef7eb2e8f9f7 162 * @}
<> 144:ef7eb2e8f9f7 163 */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /** @defgroup I2S_Mode I2S Mode
<> 144:ef7eb2e8f9f7 166 * @{
<> 144:ef7eb2e8f9f7 167 */
<> 156:95d6b41a828b 168 #define I2S_MODE_SLAVE_TX (0x00000000U)
<> 156:95d6b41a828b 169 #define I2S_MODE_SLAVE_RX (0x00000100U)
<> 156:95d6b41a828b 170 #define I2S_MODE_MASTER_TX (0x00000200U)
<> 156:95d6b41a828b 171 #define I2S_MODE_MASTER_RX (0x00000300U)
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 #define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
<> 144:ef7eb2e8f9f7 174 ((MODE) == I2S_MODE_SLAVE_RX) || \
<> 144:ef7eb2e8f9f7 175 ((MODE) == I2S_MODE_MASTER_TX)|| \
<> 144:ef7eb2e8f9f7 176 ((MODE) == I2S_MODE_MASTER_RX))
<> 144:ef7eb2e8f9f7 177 /**
<> 144:ef7eb2e8f9f7 178 * @}
<> 144:ef7eb2e8f9f7 179 */
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 /** @defgroup I2S_Standard I2S Standard
<> 144:ef7eb2e8f9f7 182 * @{
<> 144:ef7eb2e8f9f7 183 */
<> 156:95d6b41a828b 184 #define I2S_STANDARD_PHILIPS (0x00000000U)
<> 156:95d6b41a828b 185 #define I2S_STANDARD_MSB (0x00000010U)
<> 156:95d6b41a828b 186 #define I2S_STANDARD_LSB (0x00000020U)
<> 156:95d6b41a828b 187 #define I2S_STANDARD_PCM_SHORT (0x00000030U)
<> 156:95d6b41a828b 188 #define I2S_STANDARD_PCM_LONG (0x000000B0U)
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \
<> 144:ef7eb2e8f9f7 191 ((STANDARD) == I2S_STANDARD_MSB) || \
<> 144:ef7eb2e8f9f7 192 ((STANDARD) == I2S_STANDARD_LSB) || \
<> 144:ef7eb2e8f9f7 193 ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
<> 144:ef7eb2e8f9f7 194 ((STANDARD) == I2S_STANDARD_PCM_LONG))
<> 144:ef7eb2e8f9f7 195 /**
<> 144:ef7eb2e8f9f7 196 * @}
<> 144:ef7eb2e8f9f7 197 */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /** @defgroup I2S_Data_Format I2S Data Format
<> 144:ef7eb2e8f9f7 200 * @{
<> 144:ef7eb2e8f9f7 201 */
<> 156:95d6b41a828b 202 #define I2S_DATAFORMAT_16B (0x00000000U)
<> 156:95d6b41a828b 203 #define I2S_DATAFORMAT_16B_EXTENDED (0x00000001U)
<> 156:95d6b41a828b 204 #define I2S_DATAFORMAT_24B (0x00000003U)
<> 156:95d6b41a828b 205 #define I2S_DATAFORMAT_32B (0x00000005U)
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \
<> 144:ef7eb2e8f9f7 208 ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
<> 144:ef7eb2e8f9f7 209 ((FORMAT) == I2S_DATAFORMAT_24B) || \
<> 144:ef7eb2e8f9f7 210 ((FORMAT) == I2S_DATAFORMAT_32B))
<> 144:ef7eb2e8f9f7 211 /**
<> 144:ef7eb2e8f9f7 212 * @}
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup I2S_MCLK_Output I2S MCLK Output
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 144:ef7eb2e8f9f7 218 #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
<> 156:95d6b41a828b 219 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
<> 144:ef7eb2e8f9f7 222 ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @}
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency
<> 144:ef7eb2e8f9f7 228 * @{
<> 144:ef7eb2e8f9f7 229 */
<> 156:95d6b41a828b 230 #define I2S_AUDIOFREQ_192K (192000U)
<> 156:95d6b41a828b 231 #define I2S_AUDIOFREQ_96K (96000U)
<> 156:95d6b41a828b 232 #define I2S_AUDIOFREQ_48K (48000U)
<> 156:95d6b41a828b 233 #define I2S_AUDIOFREQ_44K (44100U)
<> 156:95d6b41a828b 234 #define I2S_AUDIOFREQ_32K (32000U)
<> 156:95d6b41a828b 235 #define I2S_AUDIOFREQ_22K (22050U)
<> 156:95d6b41a828b 236 #define I2S_AUDIOFREQ_16K (16000U)
<> 156:95d6b41a828b 237 #define I2S_AUDIOFREQ_11K (11025U)
<> 156:95d6b41a828b 238 #define I2S_AUDIOFREQ_8K (8000U)
<> 156:95d6b41a828b 239 #define I2S_AUDIOFREQ_DEFAULT (2U)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \
<> 144:ef7eb2e8f9f7 242 ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
<> 144:ef7eb2e8f9f7 243 ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
<> 144:ef7eb2e8f9f7 244 /**
<> 144:ef7eb2e8f9f7 245 * @}
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity
<> 144:ef7eb2e8f9f7 249 * @{
<> 144:ef7eb2e8f9f7 250 */
<> 156:95d6b41a828b 251 #define I2S_CPOL_LOW (0x00000000U)
<> 144:ef7eb2e8f9f7 252 #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
<> 144:ef7eb2e8f9f7 255 ((CPOL) == I2S_CPOL_HIGH))
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
<> 144:ef7eb2e8f9f7 261 * @{
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 #define I2S_IT_TXE SPI_CR2_TXEIE
<> 144:ef7eb2e8f9f7 264 #define I2S_IT_RXNE SPI_CR2_RXNEIE
<> 144:ef7eb2e8f9f7 265 #define I2S_IT_ERR SPI_CR2_ERRIE
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @}
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /** @defgroup I2S_Flag_definition I2S Flag definition
<> 144:ef7eb2e8f9f7 271 * @{
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 #define I2S_FLAG_TXE SPI_SR_TXE
<> 144:ef7eb2e8f9f7 274 #define I2S_FLAG_RXNE SPI_SR_RXNE
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #define I2S_FLAG_UDR SPI_SR_UDR
<> 144:ef7eb2e8f9f7 277 #define I2S_FLAG_OVR SPI_SR_OVR
<> 144:ef7eb2e8f9f7 278 #define I2S_FLAG_FRE SPI_SR_FRE
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
<> 144:ef7eb2e8f9f7 281 #define I2S_FLAG_BSY SPI_SR_BSY
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /**
<> 144:ef7eb2e8f9f7 287 * @}
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 291 /** @defgroup I2S_Exported_macros I2S Exported Macros
<> 144:ef7eb2e8f9f7 292 * @{
<> 144:ef7eb2e8f9f7 293 */
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /** @brief Reset I2S handle state
<> 144:ef7eb2e8f9f7 296 * @param __HANDLE__: I2S handle.
<> 144:ef7eb2e8f9f7 297 * @retval None
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 /** @brief Enable or disable the specified SPI peripheral (in I2S mode).
<> 144:ef7eb2e8f9f7 302 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 303 * @retval None
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
<> 144:ef7eb2e8f9f7 306 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @brief Enable or disable the specified I2S interrupts.
<> 144:ef7eb2e8f9f7 309 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 310 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
<> 144:ef7eb2e8f9f7 311 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 312 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 313 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 314 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 315 * @retval None
<> 144:ef7eb2e8f9f7 316 */
<> 144:ef7eb2e8f9f7 317 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 318 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 /** @brief Checks if the specified I2S interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 321 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 322 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
<> 144:ef7eb2e8f9f7 323 * @param __INTERRUPT__: specifies the I2S interrupt source to check.
<> 144:ef7eb2e8f9f7 324 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 325 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable
<> 144:ef7eb2e8f9f7 326 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
<> 144:ef7eb2e8f9f7 327 * @arg I2S_IT_ERR: Error interrupt enable
<> 144:ef7eb2e8f9f7 328 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 329 */
<> 144:ef7eb2e8f9f7 330 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 /** @brief Checks whether the specified I2S flag is set or not.
<> 144:ef7eb2e8f9f7 333 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 334 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 335 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 336 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag
<> 144:ef7eb2e8f9f7 337 * @arg I2S_FLAG_TXE: Transmit buffer empty flag
<> 144:ef7eb2e8f9f7 338 * @arg I2S_FLAG_UDR: Underrun flag
<> 144:ef7eb2e8f9f7 339 * @arg I2S_FLAG_OVR: Overrun flag
<> 144:ef7eb2e8f9f7 340 * @arg I2S_FLAG_FRE: Frame error flag
<> 144:ef7eb2e8f9f7 341 * @arg I2S_FLAG_CHSIDE: Channel Side flag
<> 144:ef7eb2e8f9f7 342 * @arg I2S_FLAG_BSY: Busy flag
<> 144:ef7eb2e8f9f7 343 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @brief Clears the I2S OVR pending flag.
<> 144:ef7eb2e8f9f7 348 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 349 * @retval None
<> 144:ef7eb2e8f9f7 350 */
<> 144:ef7eb2e8f9f7 351 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
<> 144:ef7eb2e8f9f7 352 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 353 tmpreg = (__HANDLE__)->Instance->DR; \
<> 144:ef7eb2e8f9f7 354 tmpreg = (__HANDLE__)->Instance->SR; \
<> 144:ef7eb2e8f9f7 355 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 356 }while(0)
<> 144:ef7eb2e8f9f7 357 /** @brief Clears the I2S UDR pending flag.
<> 144:ef7eb2e8f9f7 358 * @param __HANDLE__: specifies the I2S Handle.
<> 144:ef7eb2e8f9f7 359 * @retval None
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
<> 144:ef7eb2e8f9f7 362 __IO uint32_t tmpreg;\
<> 144:ef7eb2e8f9f7 363 tmpreg = ((__HANDLE__)->Instance->SR);\
<> 144:ef7eb2e8f9f7 364 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 365 }while(0)
<> 144:ef7eb2e8f9f7 366 /**
<> 144:ef7eb2e8f9f7 367 * @}
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369
<> 144:ef7eb2e8f9f7 370 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 371 /** @addtogroup I2S_Exported_Functions
<> 144:ef7eb2e8f9f7 372 * @{
<> 144:ef7eb2e8f9f7 373 */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /** @addtogroup I2S_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 376 * @{
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 379 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 380 HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 381 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 382 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @}
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /** @addtogroup I2S_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 388 * @{
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 391 /* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 392 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 393 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 396 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 397 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 398 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 401 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 402 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 405 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 406 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
<> 144:ef7eb2e8f9f7 409 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 410 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 411 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 412 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 413 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 414 /**
<> 144:ef7eb2e8f9f7 415 * @}
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /** @addtogroup I2S_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 419 * @{
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421 /* Peripheral Control and State functions ************************************/
<> 144:ef7eb2e8f9f7 422 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 423 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @}
<> 144:ef7eb2e8f9f7 426 */
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @}
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /**
<> 144:ef7eb2e8f9f7 434 * @}
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 /**
<> 144:ef7eb2e8f9f7 438 * @}
<> 144:ef7eb2e8f9f7 439 */
<> 144:ef7eb2e8f9f7 440 #endif /* defined(STM32F031x6) || defined(STM32F038xx) || */
<> 144:ef7eb2e8f9f7 441 /* defined(STM32F051x8) || defined(STM32F058xx) || */
<> 144:ef7eb2e8f9f7 442 /* defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) ||*/
<> 144:ef7eb2e8f9f7 443 /* defined(STM32F042x6) || defined(STM32F048xx) || */
<> 144:ef7eb2e8f9f7 444 /* defined(STM32F091xC) || defined(STM32F098xx) */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 #endif
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 #endif /* __STM32F0xx_HAL_I2S_H */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/