mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_dac_ex.c@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_dac_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief DAC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the extended
<> 144:ef7eb2e8f9f7 9 * functionalities of the DAC peripheral.
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 *
<> 144:ef7eb2e8f9f7 12 @verbatim
<> 144:ef7eb2e8f9f7 13 ==============================================================================
<> 144:ef7eb2e8f9f7 14 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 [..]
<> 144:ef7eb2e8f9f7 17 (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
<> 144:ef7eb2e8f9f7 18 Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
<> 144:ef7eb2e8f9f7 19 HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.
<> 144:ef7eb2e8f9f7 20 (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
<> 144:ef7eb2e8f9f7 21 (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 @endverbatim
<> 144:ef7eb2e8f9f7 24 ******************************************************************************
<> 144:ef7eb2e8f9f7 25 * @attention
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 30 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 31 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 32 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 33 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 34 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 35 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 36 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 37 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 38 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 39 *
<> 144:ef7eb2e8f9f7 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 41 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 43 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 46 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 47 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 49 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 50 *
<> 144:ef7eb2e8f9f7 51 ******************************************************************************
<> 144:ef7eb2e8f9f7 52 */
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 56 #include "stm32f0xx_hal.h"
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 #ifdef HAL_DAC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 /** @addtogroup DAC
<> 144:ef7eb2e8f9f7 65 * @{
<> 144:ef7eb2e8f9f7 66 */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 69 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 70 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 73 * @{
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 76 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 77 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 83 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 84 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 87 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 /* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
<> 144:ef7eb2e8f9f7 94 /* are set by HAL_DAC_Start_DMA */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 97 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 98 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
<> 144:ef7eb2e8f9f7 99 /**
<> 144:ef7eb2e8f9f7 100 * @}
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 104 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @addtogroup DAC_Exported_Functions
<> 144:ef7eb2e8f9f7 107 * @{
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /** @addtogroup DAC_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 111 * @{
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 115 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 119 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 120 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 121 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 122 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 123 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 124 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 125 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 126 * @retval HAL status
<> 144:ef7eb2e8f9f7 127 */
<> 144:ef7eb2e8f9f7 128 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 129 {
<> 156:95d6b41a828b 130 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 133 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 134 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 135 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 136 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /* Process locked */
<> 144:ef7eb2e8f9f7 139 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /* Change DAC state */
<> 144:ef7eb2e8f9f7 142 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 145 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 146 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 147 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
<> 144:ef7eb2e8f9f7 148 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 149 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 150 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 151 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
<> 144:ef7eb2e8f9f7 152 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 153 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 154 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 155 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /* Change DAC state */
<> 144:ef7eb2e8f9f7 158 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /* Process unlocked */
<> 144:ef7eb2e8f9f7 161 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Return function status */
<> 144:ef7eb2e8f9f7 164 return HAL_OK;
<> 144:ef7eb2e8f9f7 165 }
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 168 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 /**
<> 144:ef7eb2e8f9f7 173 * @brief Configures the selected DAC channel.
<> 144:ef7eb2e8f9f7 174 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 175 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 176 * @param sConfig: DAC configuration structure.
<> 144:ef7eb2e8f9f7 177 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 178 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 179 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 180 * @retval HAL status
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
<> 144:ef7eb2e8f9f7 183 {
<> 156:95d6b41a828b 184 uint32_t tmpreg1 = 0U, tmpreg2 = 0U;
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 /* Check the DAC parameters */
<> 144:ef7eb2e8f9f7 187 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 188 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
<> 144:ef7eb2e8f9f7 189 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
<> 144:ef7eb2e8f9f7 190 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Process locked */
<> 144:ef7eb2e8f9f7 193 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 /* Change DAC state */
<> 144:ef7eb2e8f9f7 196 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* Get the DAC CR value */
<> 144:ef7eb2e8f9f7 199 tmpreg1 = hdac->Instance->CR;
<> 144:ef7eb2e8f9f7 200 /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
<> 144:ef7eb2e8f9f7 201 tmpreg1 &= ~(((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
<> 144:ef7eb2e8f9f7 202 /* Configure for the selected DAC channel: buffer output, trigger */
<> 144:ef7eb2e8f9f7 203 /* Set TSELx and TENx bits according to DAC_Trigger value */
<> 144:ef7eb2e8f9f7 204 /* Set BOFFx bit according to DAC_OutputBuffer value */
<> 144:ef7eb2e8f9f7 205 tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
<> 144:ef7eb2e8f9f7 206 /* Calculate CR register value depending on DAC_Channel */
<> 144:ef7eb2e8f9f7 207 tmpreg1 |= tmpreg2 << Channel;
<> 144:ef7eb2e8f9f7 208 /* Write to DAC CR */
<> 144:ef7eb2e8f9f7 209 hdac->Instance->CR = tmpreg1;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 /* Change DAC state */
<> 144:ef7eb2e8f9f7 212 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /* Process unlocked */
<> 144:ef7eb2e8f9f7 215 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /* Return function status */
<> 144:ef7eb2e8f9f7 218 return HAL_OK;
<> 144:ef7eb2e8f9f7 219 }
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 224 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 225 /* DAC 1 has 2 channels 1 & 2 */
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 /**
<> 144:ef7eb2e8f9f7 228 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 229 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 230 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 231 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 232 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 233 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 234 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 235 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 236 */
<> 144:ef7eb2e8f9f7 237 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 238 {
<> 144:ef7eb2e8f9f7 239 /* Check the parameters */
<> 144:ef7eb2e8f9f7 240 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 243 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 else
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 return hdac->Instance->DOR2;
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 254 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* DAC 1 has 1 channels */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /**
<> 144:ef7eb2e8f9f7 261 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 262 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 263 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 264 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 265 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 266 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 267 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 268 */
<> 144:ef7eb2e8f9f7 269 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 /* Check the parameters */
<> 144:ef7eb2e8f9f7 272 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 275 return hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @}
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /** @addtogroup DAC_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 291 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 /**
<> 144:ef7eb2e8f9f7 294 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 295 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 296 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 297 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 298 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 299 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 300 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 301 * @retval HAL status
<> 144:ef7eb2e8f9f7 302 */
<> 144:ef7eb2e8f9f7 303 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 /* Check the parameters */
<> 144:ef7eb2e8f9f7 306 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /* Process locked */
<> 144:ef7eb2e8f9f7 309 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Change DAC state */
<> 144:ef7eb2e8f9f7 312 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 315 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 318 {
<> 144:ef7eb2e8f9f7 319 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 320 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 323 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 else
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 329 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2))
<> 144:ef7eb2e8f9f7 330 {
<> 144:ef7eb2e8f9f7 331 /* Enable the selected DAC software conversion*/
<> 144:ef7eb2e8f9f7 332 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
<> 144:ef7eb2e8f9f7 333 }
<> 144:ef7eb2e8f9f7 334 }
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /* Change DAC state */
<> 144:ef7eb2e8f9f7 337 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Process unlocked */
<> 144:ef7eb2e8f9f7 340 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Return function status */
<> 144:ef7eb2e8f9f7 343 return HAL_OK;
<> 144:ef7eb2e8f9f7 344 }
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /**
<> 144:ef7eb2e8f9f7 347 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 348 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 349 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 350 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 351 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 352 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 353 * @arg DAC_CHANNEL_2: DAC Channel2 selected
<> 144:ef7eb2e8f9f7 354 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 355 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 356 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 357 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 358 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 359 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 360 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 361 * @retval HAL status
<> 144:ef7eb2e8f9f7 362 */
<> 144:ef7eb2e8f9f7 363 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 364 {
<> 156:95d6b41a828b 365 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* Check the parameters */
<> 144:ef7eb2e8f9f7 368 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 369 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Process locked */
<> 144:ef7eb2e8f9f7 372 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Change DAC state */
<> 144:ef7eb2e8f9f7 375 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 380 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 383 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 386 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 389 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 392 switch(Alignment)
<> 144:ef7eb2e8f9f7 393 {
<> 144:ef7eb2e8f9f7 394 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 395 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 396 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 397 break;
<> 144:ef7eb2e8f9f7 398 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 399 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 400 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 401 break;
<> 144:ef7eb2e8f9f7 402 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 403 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 404 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 405 break;
<> 144:ef7eb2e8f9f7 406 default:
<> 144:ef7eb2e8f9f7 407 break;
<> 144:ef7eb2e8f9f7 408 }
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410 else
<> 144:ef7eb2e8f9f7 411 {
<> 144:ef7eb2e8f9f7 412 /* Set the DMA transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 413 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Set the DMA half transfer complete callback for channel2 */
<> 144:ef7eb2e8f9f7 416 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Set the DMA error callback for channel2 */
<> 144:ef7eb2e8f9f7 419 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the selected DAC channel2 DMA request */
<> 144:ef7eb2e8f9f7 422 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Case of use of channel 2 */
<> 144:ef7eb2e8f9f7 425 switch(Alignment)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 428 /* Get DHR12R2 address */
<> 144:ef7eb2e8f9f7 429 tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
<> 144:ef7eb2e8f9f7 430 break;
<> 144:ef7eb2e8f9f7 431 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 432 /* Get DHR12L2 address */
<> 144:ef7eb2e8f9f7 433 tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
<> 144:ef7eb2e8f9f7 434 break;
<> 144:ef7eb2e8f9f7 435 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 436 /* Get DHR8R2 address */
<> 144:ef7eb2e8f9f7 437 tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
<> 144:ef7eb2e8f9f7 438 break;
<> 144:ef7eb2e8f9f7 439 default:
<> 144:ef7eb2e8f9f7 440 break;
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 445 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 446 {
<> 144:ef7eb2e8f9f7 447 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 448 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 451 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 else
<> 144:ef7eb2e8f9f7 454 {
<> 144:ef7eb2e8f9f7 455 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 456 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 459 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 460 }
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 463 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 466 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Return function status */
<> 144:ef7eb2e8f9f7 469 return HAL_OK;
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 475 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 /* Check the parameters */
<> 144:ef7eb2e8f9f7 482 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Process locked */
<> 144:ef7eb2e8f9f7 485 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 486
<> 144:ef7eb2e8f9f7 487 /* Change DAC state */
<> 144:ef7eb2e8f9f7 488 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 491 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 if(Channel == DAC_CHANNEL_1)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 /* Check if software trigger enabled */
<> 144:ef7eb2e8f9f7 496 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1))
<> 144:ef7eb2e8f9f7 497 {
<> 144:ef7eb2e8f9f7 498 /* Enable the selected DAC software conversion */
<> 144:ef7eb2e8f9f7 499 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /* Change DAC state */
<> 144:ef7eb2e8f9f7 504 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 505
<> 144:ef7eb2e8f9f7 506 /* Process unlocked */
<> 144:ef7eb2e8f9f7 507 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Return function status */
<> 144:ef7eb2e8f9f7 510 return HAL_OK;
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /**
<> 144:ef7eb2e8f9f7 514 * @brief Enables DAC and starts conversion of channel.
<> 144:ef7eb2e8f9f7 515 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 516 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 517 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 518 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 519 * @arg DAC_CHANNEL_1: DAC Channel1 selected
<> 144:ef7eb2e8f9f7 520 * @param pData: The destination peripheral Buffer address.
<> 144:ef7eb2e8f9f7 521 * @param Length: The length of data to be transferred from memory to DAC peripheral
<> 144:ef7eb2e8f9f7 522 * @param Alignment: Specifies the data alignment for DAC channel.
<> 144:ef7eb2e8f9f7 523 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 524 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 525 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 526 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 527 * @retval HAL status
<> 144:ef7eb2e8f9f7 528 */
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
<> 144:ef7eb2e8f9f7 530 {
<> 156:95d6b41a828b 531 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /* Check the parameters */
<> 144:ef7eb2e8f9f7 534 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 535 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* Process locked */
<> 144:ef7eb2e8f9f7 538 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 /* Change DAC state */
<> 144:ef7eb2e8f9f7 541 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 542
<> 144:ef7eb2e8f9f7 543 /* Set the DMA transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 544 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 /* Set the DMA half transfer complete callback for channel1 */
<> 144:ef7eb2e8f9f7 547 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 /* Set the DMA error callback for channel1 */
<> 144:ef7eb2e8f9f7 550 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Enable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 553 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 /* Case of use of channel 1 */
<> 144:ef7eb2e8f9f7 556 switch(Alignment)
<> 144:ef7eb2e8f9f7 557 {
<> 144:ef7eb2e8f9f7 558 case DAC_ALIGN_12B_R:
<> 144:ef7eb2e8f9f7 559 /* Get DHR12R1 address */
<> 144:ef7eb2e8f9f7 560 tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
<> 144:ef7eb2e8f9f7 561 break;
<> 144:ef7eb2e8f9f7 562 case DAC_ALIGN_12B_L:
<> 144:ef7eb2e8f9f7 563 /* Get DHR12L1 address */
<> 144:ef7eb2e8f9f7 564 tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
<> 144:ef7eb2e8f9f7 565 break;
<> 144:ef7eb2e8f9f7 566 case DAC_ALIGN_8B_R:
<> 144:ef7eb2e8f9f7 567 /* Get DHR8R1 address */
<> 144:ef7eb2e8f9f7 568 tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
<> 144:ef7eb2e8f9f7 569 break;
<> 144:ef7eb2e8f9f7 570 default:
<> 144:ef7eb2e8f9f7 571 break;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 575 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 576 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 579 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 /* Enable the DAC DMA underrun interrupt */
<> 144:ef7eb2e8f9f7 582 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /* Enable the DMA channel */
<> 144:ef7eb2e8f9f7 585 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /* Enable the Peripharal */
<> 144:ef7eb2e8f9f7 588 __HAL_DAC_ENABLE(hdac, Channel);
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590 /* Process Unlocked */
<> 144:ef7eb2e8f9f7 591 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /* Return function status */
<> 144:ef7eb2e8f9f7 594 return HAL_OK;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 600 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 601 /* DAC channel 2 is available on top of DAC channel 1 */
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /**
<> 144:ef7eb2e8f9f7 604 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 605 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 606 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 607 * @retval None
<> 144:ef7eb2e8f9f7 608 */
<> 144:ef7eb2e8f9f7 609 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 610 {
<> 144:ef7eb2e8f9f7 611 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 612 {
<> 144:ef7eb2e8f9f7 613 /* Check underrun channel 1 flag */
<> 144:ef7eb2e8f9f7 614 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 617 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 /* Set DAC error code to channel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 620 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 623 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 626 hdac->Instance->CR &= ~DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 /* Error callback */
<> 144:ef7eb2e8f9f7 629 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
<> 144:ef7eb2e8f9f7 633 {
<> 144:ef7eb2e8f9f7 634 /* Check underrun channel 2 flag */
<> 144:ef7eb2e8f9f7 635 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 638 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Set DAC error code to channel2 DMA underrun error */
<> 144:ef7eb2e8f9f7 641 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 644 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 647 hdac->Instance->CR &= ~DAC_CR_DMAEN2;
<> 144:ef7eb2e8f9f7 648
<> 144:ef7eb2e8f9f7 649 /* Error callback */
<> 144:ef7eb2e8f9f7 650 HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 656 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 659 /* DAC channel 2 is NOT available. Only DAC channel 1 is available */
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /**
<> 144:ef7eb2e8f9f7 662 * @brief Handles DAC interrupt request
<> 144:ef7eb2e8f9f7 663 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 664 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 665 * @retval None
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 668 {
<> 144:ef7eb2e8f9f7 669 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1))
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 /* Check Overrun flag */
<> 144:ef7eb2e8f9f7 672 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 /* Change DAC state to error state */
<> 144:ef7eb2e8f9f7 675 hdac->State = HAL_DAC_STATE_ERROR;
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 /* Set DAC error code to chanel1 DMA underrun error */
<> 144:ef7eb2e8f9f7 678 hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 /* Clear the underrun flag */
<> 144:ef7eb2e8f9f7 681 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 /* Disable the selected DAC channel1 DMA request */
<> 144:ef7eb2e8f9f7 684 hdac->Instance->CR &= ~DAC_CR_DMAEN1;
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 /* Error callback */
<> 144:ef7eb2e8f9f7 687 HAL_DAC_DMAUnderrunCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 688 }
<> 144:ef7eb2e8f9f7 689 }
<> 144:ef7eb2e8f9f7 690 }
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @}
<> 144:ef7eb2e8f9f7 696 */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 /**
<> 144:ef7eb2e8f9f7 699 * @}
<> 144:ef7eb2e8f9f7 700 */
<> 144:ef7eb2e8f9f7 701
<> 144:ef7eb2e8f9f7 702 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 703 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 704 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 707 * @{
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 712 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 713 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 714 * @retval None
<> 144:ef7eb2e8f9f7 715 */
<> 144:ef7eb2e8f9f7 716 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 717 {
<> 144:ef7eb2e8f9f7 718 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 HAL_DAC_ConvCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 723 }
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /**
<> 144:ef7eb2e8f9f7 726 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 727 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 728 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 729 * @retval None
<> 144:ef7eb2e8f9f7 730 */
<> 144:ef7eb2e8f9f7 731 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 734 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 735 HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 740 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 741 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 742 * @retval None
<> 144:ef7eb2e8f9f7 743 */
<> 144:ef7eb2e8f9f7 744 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 745 {
<> 144:ef7eb2e8f9f7 746 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 749 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 HAL_DAC_ErrorCallbackCh1(hdac);
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 754 }
<> 144:ef7eb2e8f9f7 755 /**
<> 144:ef7eb2e8f9f7 756 * @}
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 759 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 760 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 763 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /** @addtogroup DAC_Private_Functions
<> 144:ef7eb2e8f9f7 766 * @{
<> 144:ef7eb2e8f9f7 767 */
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief DMA conversion complete callback.
<> 144:ef7eb2e8f9f7 771 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 772 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 773 * @retval None
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775 void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 776 {
<> 144:ef7eb2e8f9f7 777 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 HAL_DACEx_ConvCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 782 }
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 /**
<> 144:ef7eb2e8f9f7 785 * @brief DMA half transfer complete callback.
<> 144:ef7eb2e8f9f7 786 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 787 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 788 * @retval None
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790 void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 791 {
<> 144:ef7eb2e8f9f7 792 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 793 /* Conversion complete callback */
<> 144:ef7eb2e8f9f7 794 HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /**
<> 144:ef7eb2e8f9f7 798 * @brief DMA error callback
<> 144:ef7eb2e8f9f7 799 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 800 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 801 * @retval None
<> 144:ef7eb2e8f9f7 802 */
<> 144:ef7eb2e8f9f7 803 void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 804 {
<> 144:ef7eb2e8f9f7 805 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 /* Set DAC error code to DMA error */
<> 144:ef7eb2e8f9f7 808 hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 HAL_DACEx_ErrorCallbackCh2(hdac);
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 hdac->State= HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 813 }
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /**
<> 144:ef7eb2e8f9f7 816 * @}
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818
<> 144:ef7eb2e8f9f7 819 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 820 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /**
<> 144:ef7eb2e8f9f7 823 * @}
<> 144:ef7eb2e8f9f7 824 */
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /** @defgroup DACEx DACEx
<> 144:ef7eb2e8f9f7 827 * @brief DACEx driver module
<> 144:ef7eb2e8f9f7 828 * @{
<> 144:ef7eb2e8f9f7 829 */
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 832 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 833 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 834 /** @defgroup DACEx_Private_Macros DACEx Private Macros
<> 144:ef7eb2e8f9f7 835 * @{
<> 144:ef7eb2e8f9f7 836 */
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @}
<> 144:ef7eb2e8f9f7 839 */
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 842 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 843 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /** @defgroup DACEx_Exported_Functions DACEx Exported Functions
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 /** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
<> 144:ef7eb2e8f9f7 850 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 851 *
<> 144:ef7eb2e8f9f7 852 @verbatim
<> 144:ef7eb2e8f9f7 853 ==============================================================================
<> 144:ef7eb2e8f9f7 854 ##### Extended features functions #####
<> 144:ef7eb2e8f9f7 855 ==============================================================================
<> 144:ef7eb2e8f9f7 856 [..] This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 857 (+) Start conversion.
<> 144:ef7eb2e8f9f7 858 (+) Stop conversion.
<> 144:ef7eb2e8f9f7 859 (+) Start conversion and enable DMA transfer.
<> 144:ef7eb2e8f9f7 860 (+) Stop conversion and disable DMA transfer.
<> 144:ef7eb2e8f9f7 861 (+) Get result of conversion.
<> 144:ef7eb2e8f9f7 862 (+) Get result of dual mode conversion.
<> 144:ef7eb2e8f9f7 863
<> 144:ef7eb2e8f9f7 864 @endverbatim
<> 144:ef7eb2e8f9f7 865 * @{
<> 144:ef7eb2e8f9f7 866 */
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 869 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /**
<> 144:ef7eb2e8f9f7 872 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 873 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 874 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 875 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 876 */
<> 144:ef7eb2e8f9f7 877 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 878 {
<> 156:95d6b41a828b 879 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /* DAC channel 2 is present in DAC 1 */
<> 156:95d6b41a828b 884 tmp |= hdac->Instance->DOR2 << 16U;
<> 144:ef7eb2e8f9f7 885
<> 144:ef7eb2e8f9f7 886 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 887 return tmp;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 891 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 #if defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @brief Returns the last data output value of the selected DAC channel.
<> 144:ef7eb2e8f9f7 897 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 898 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 899 * @retval The selected DAC channel data output value.
<> 144:ef7eb2e8f9f7 900 */
<> 144:ef7eb2e8f9f7 901 uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 902 {
<> 156:95d6b41a828b 903 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 tmp |= hdac->Instance->DOR1;
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /* Returns the DAC channel data output register value */
<> 144:ef7eb2e8f9f7 908 return tmp;
<> 144:ef7eb2e8f9f7 909 }
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 914 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 915
<> 144:ef7eb2e8f9f7 916 /**
<> 144:ef7eb2e8f9f7 917 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 918 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 919 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 920 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 921 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 922 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 923 * @param Amplitude: Select max triangle amplitude.
<> 144:ef7eb2e8f9f7 924 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 925 * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
<> 144:ef7eb2e8f9f7 926 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
<> 144:ef7eb2e8f9f7 927 * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
<> 144:ef7eb2e8f9f7 928 * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
<> 144:ef7eb2e8f9f7 929 * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
<> 144:ef7eb2e8f9f7 930 * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
<> 144:ef7eb2e8f9f7 931 * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
<> 144:ef7eb2e8f9f7 932 * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
<> 144:ef7eb2e8f9f7 933 * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
<> 144:ef7eb2e8f9f7 934 * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
<> 144:ef7eb2e8f9f7 935 * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
<> 144:ef7eb2e8f9f7 936 * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
<> 144:ef7eb2e8f9f7 937 * @retval HAL status
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 /* Check the parameters */
<> 144:ef7eb2e8f9f7 942 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 943 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 944
<> 144:ef7eb2e8f9f7 945 /* Process locked */
<> 144:ef7eb2e8f9f7 946 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 /* Change DAC state */
<> 144:ef7eb2e8f9f7 949 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 952 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 953
<> 144:ef7eb2e8f9f7 954 /* Change DAC state */
<> 144:ef7eb2e8f9f7 955 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /* Process unlocked */
<> 144:ef7eb2e8f9f7 958 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /* Return function status */
<> 144:ef7eb2e8f9f7 961 return HAL_OK;
<> 144:ef7eb2e8f9f7 962 }
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @brief Enables or disables the selected DAC channel wave generation.
<> 144:ef7eb2e8f9f7 966 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 967 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 968 * @param Channel: The selected DAC channel.
<> 144:ef7eb2e8f9f7 969 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 970 * DAC_CHANNEL_1 / DAC_CHANNEL_2
<> 144:ef7eb2e8f9f7 971 * @param Amplitude: Unmask DAC channel LFSR for noise wave generation.
<> 144:ef7eb2e8f9f7 972 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 973 * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
<> 144:ef7eb2e8f9f7 974 * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
<> 144:ef7eb2e8f9f7 975 * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
<> 144:ef7eb2e8f9f7 976 * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
<> 144:ef7eb2e8f9f7 977 * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
<> 144:ef7eb2e8f9f7 978 * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
<> 144:ef7eb2e8f9f7 979 * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
<> 144:ef7eb2e8f9f7 980 * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
<> 144:ef7eb2e8f9f7 981 * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
<> 144:ef7eb2e8f9f7 982 * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
<> 144:ef7eb2e8f9f7 983 * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
<> 144:ef7eb2e8f9f7 984 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
<> 144:ef7eb2e8f9f7 985 * @retval HAL status
<> 144:ef7eb2e8f9f7 986 */
<> 144:ef7eb2e8f9f7 987 HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
<> 144:ef7eb2e8f9f7 988 {
<> 144:ef7eb2e8f9f7 989 /* Check the parameters */
<> 144:ef7eb2e8f9f7 990 assert_param(IS_DAC_CHANNEL(Channel));
<> 144:ef7eb2e8f9f7 991 assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
<> 144:ef7eb2e8f9f7 992
<> 144:ef7eb2e8f9f7 993 /* Process locked */
<> 144:ef7eb2e8f9f7 994 __HAL_LOCK(hdac);
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /* Change DAC state */
<> 144:ef7eb2e8f9f7 997 hdac->State = HAL_DAC_STATE_BUSY;
<> 144:ef7eb2e8f9f7 998
<> 144:ef7eb2e8f9f7 999 /* Enable the selected wave generation for the selected DAC channel */
<> 144:ef7eb2e8f9f7 1000 MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 /* Change DAC state */
<> 144:ef7eb2e8f9f7 1003 hdac->State = HAL_DAC_STATE_READY;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /* Process unlocked */
<> 144:ef7eb2e8f9f7 1006 __HAL_UNLOCK(hdac);
<> 144:ef7eb2e8f9f7 1007
<> 144:ef7eb2e8f9f7 1008 /* Return function status */
<> 144:ef7eb2e8f9f7 1009 return HAL_OK;
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1013 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /**
<> 144:ef7eb2e8f9f7 1016 * @}
<> 144:ef7eb2e8f9f7 1017 */
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /**
<> 144:ef7eb2e8f9f7 1020 * @}
<> 144:ef7eb2e8f9f7 1021 */
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023 #if defined(STM32F051x8) || defined(STM32F058xx) || \
<> 144:ef7eb2e8f9f7 1024 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1025 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1028 * @{
<> 144:ef7eb2e8f9f7 1029 */
<> 144:ef7eb2e8f9f7 1030
<> 144:ef7eb2e8f9f7 1031 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1032 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 1033 * @{
<> 144:ef7eb2e8f9f7 1034 */
<> 144:ef7eb2e8f9f7 1035
<> 144:ef7eb2e8f9f7 1036 /**
<> 144:ef7eb2e8f9f7 1037 * @brief Set the specified data holding register value for dual DAC channel.
<> 144:ef7eb2e8f9f7 1038 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1039 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1040 * @param Alignment: Specifies the data alignment for dual channel DAC.
<> 144:ef7eb2e8f9f7 1041 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1042 * DAC_ALIGN_8B_R: 8bit right data alignment selected
<> 144:ef7eb2e8f9f7 1043 * DAC_ALIGN_12B_L: 12bit left data alignment selected
<> 144:ef7eb2e8f9f7 1044 * DAC_ALIGN_12B_R: 12bit right data alignment selected
<> 144:ef7eb2e8f9f7 1045 * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 1046 * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register.
<> 144:ef7eb2e8f9f7 1047 * @note In dual mode, a unique register access is required to write in both
<> 144:ef7eb2e8f9f7 1048 * DAC channels at the same time.
<> 144:ef7eb2e8f9f7 1049 * @retval HAL status
<> 144:ef7eb2e8f9f7 1050 */
<> 144:ef7eb2e8f9f7 1051 HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
<> 144:ef7eb2e8f9f7 1052 {
<> 156:95d6b41a828b 1053 uint32_t data = 0U, tmp = 0U;
<> 144:ef7eb2e8f9f7 1054
<> 144:ef7eb2e8f9f7 1055 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_DAC_ALIGN(Alignment));
<> 144:ef7eb2e8f9f7 1057 assert_param(IS_DAC_DATA(Data1));
<> 144:ef7eb2e8f9f7 1058 assert_param(IS_DAC_DATA(Data2));
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /* Calculate and set dual DAC data holding register value */
<> 144:ef7eb2e8f9f7 1061 if (Alignment == DAC_ALIGN_8B_R)
<> 144:ef7eb2e8f9f7 1062 {
<> 156:95d6b41a828b 1063 data = ((uint32_t)Data2 << 8U) | Data1;
<> 144:ef7eb2e8f9f7 1064 }
<> 144:ef7eb2e8f9f7 1065 else
<> 144:ef7eb2e8f9f7 1066 {
<> 156:95d6b41a828b 1067 data = ((uint32_t)Data2 << 16U) | Data1;
<> 144:ef7eb2e8f9f7 1068 }
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 tmp = (uint32_t)hdac->Instance;
<> 144:ef7eb2e8f9f7 1071 tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /* Set the dual DAC selected data holding register */
<> 144:ef7eb2e8f9f7 1074 *(__IO uint32_t *)tmp = data;
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /* Return function status */
<> 144:ef7eb2e8f9f7 1077 return HAL_OK;
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /**
<> 144:ef7eb2e8f9f7 1081 * @}
<> 144:ef7eb2e8f9f7 1082 */
<> 144:ef7eb2e8f9f7 1083
<> 144:ef7eb2e8f9f7 1084 /**
<> 144:ef7eb2e8f9f7 1085 * @}
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 #endif /* STM32F051x8 STM32F058xx */
<> 144:ef7eb2e8f9f7 1089 /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1090 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
<> 144:ef7eb2e8f9f7 1093 defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /** @addtogroup DACEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1096 * @{
<> 144:ef7eb2e8f9f7 1097 */
<> 144:ef7eb2e8f9f7 1098
<> 144:ef7eb2e8f9f7 1099 /** @addtogroup DACEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1100 * @brief Extended features functions
<> 144:ef7eb2e8f9f7 1101 * @{
<> 144:ef7eb2e8f9f7 1102 */
<> 144:ef7eb2e8f9f7 1103
<> 144:ef7eb2e8f9f7 1104 /**
<> 144:ef7eb2e8f9f7 1105 * @brief Conversion complete callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 1106 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1107 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1108 * @retval None
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110 __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 1111 {
<> 144:ef7eb2e8f9f7 1112 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1113 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1116 the HAL_DAC_ConvCpltCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1117 */
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @brief Conversion half DMA transfer callback in non blocking mode for Channel2
<> 144:ef7eb2e8f9f7 1122 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1123 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1124 * @retval None
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126 __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1129 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1132 the HAL_DAC_ConvHalfCpltCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134 }
<> 144:ef7eb2e8f9f7 1135
<> 144:ef7eb2e8f9f7 1136 /**
<> 144:ef7eb2e8f9f7 1137 * @brief Error DAC callback for Channel2.
<> 144:ef7eb2e8f9f7 1138 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1139 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1140 * @retval None
<> 144:ef7eb2e8f9f7 1141 */
<> 144:ef7eb2e8f9f7 1142 __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 1143 {
<> 144:ef7eb2e8f9f7 1144 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1145 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1146
<> 144:ef7eb2e8f9f7 1147 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1148 the HAL_DAC_ErrorCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1149 */
<> 144:ef7eb2e8f9f7 1150 }
<> 144:ef7eb2e8f9f7 1151
<> 144:ef7eb2e8f9f7 1152 /**
<> 144:ef7eb2e8f9f7 1153 * @brief DMA underrun DAC callback for channel2.
<> 144:ef7eb2e8f9f7 1154 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1155 * the configuration information for the specified DAC.
<> 144:ef7eb2e8f9f7 1156 * @retval None
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
<> 144:ef7eb2e8f9f7 1159 {
<> 144:ef7eb2e8f9f7 1160 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1161 UNUSED(hdac);
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1164 the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
<> 144:ef7eb2e8f9f7 1165 */
<> 144:ef7eb2e8f9f7 1166 }
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 /**
<> 144:ef7eb2e8f9f7 1169 * @}
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /**
<> 144:ef7eb2e8f9f7 1173 * @}
<> 144:ef7eb2e8f9f7 1174 */
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 #endif /* STM32F071xB STM32F072xB STM32F078xx */
<> 144:ef7eb2e8f9f7 1177 /* STM32F091xC STM32F098xx */
<> 144:ef7eb2e8f9f7 1178
<> 144:ef7eb2e8f9f7 1179 /**
<> 144:ef7eb2e8f9f7 1180 * @}
<> 144:ef7eb2e8f9f7 1181 */
<> 144:ef7eb2e8f9f7 1182
<> 144:ef7eb2e8f9f7 1183 #endif /* HAL_DAC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1184
<> 144:ef7eb2e8f9f7 1185 /**
<> 144:ef7eb2e8f9f7 1186 * @}
<> 144:ef7eb2e8f9f7 1187 */
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/