mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_can.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_can.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of CAN HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_CAN_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_CAN_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 #if defined(STM32F072xB) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 49 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 */
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @addtogroup CAN
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /** @defgroup CAN_Exported_Types CAN Exported Types
<> 144:ef7eb2e8f9f7 61 * @{
<> 144:ef7eb2e8f9f7 62 */
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef enum
<> 144:ef7eb2e8f9f7 67 {
<> 156:95d6b41a828b 68 HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
<> 156:95d6b41a828b 69 HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
<> 156:95d6b41a828b 70 HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
<> 156:95d6b41a828b 71 HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
<> 156:95d6b41a828b 72 HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
<> 156:95d6b41a828b 73 HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
<> 156:95d6b41a828b 74 HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
<> 156:95d6b41a828b 75 HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 }HAL_CAN_StateTypeDef;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @brief CAN init structure definition
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 typedef struct
<> 144:ef7eb2e8f9f7 83 {
<> 144:ef7eb2e8f9f7 84 uint32_t Prescaler; /*!< Specifies the length of a time quantum.
<> 144:ef7eb2e8f9f7 85 This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t Mode; /*!< Specifies the CAN operating mode.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref CAN_operating_mode */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t SJW; /*!< Specifies the maximum number of time quanta
<> 144:ef7eb2e8f9f7 91 the CAN hardware is allowed to lengthen or
<> 144:ef7eb2e8f9f7 92 shorten a bit to perform resynchronization.
<> 144:ef7eb2e8f9f7 93 This parameter can be a value of @ref CAN_synchronisation_jump_width */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
<> 144:ef7eb2e8f9f7 96 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
<> 144:ef7eb2e8f9f7 99 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
<> 144:ef7eb2e8f9f7 102 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
<> 144:ef7eb2e8f9f7 105 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
<> 144:ef7eb2e8f9f7 108 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
<> 144:ef7eb2e8f9f7 111 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 uint32_t RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
<> 144:ef7eb2e8f9f7 114 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
<> 144:ef7eb2e8f9f7 117 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 118 }CAN_InitTypeDef;
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /**
<> 144:ef7eb2e8f9f7 121 * @brief CAN filter configuration structure definition
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 typedef struct
<> 144:ef7eb2e8f9f7 124 {
<> 144:ef7eb2e8f9f7 125 uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
<> 144:ef7eb2e8f9f7 126 configuration, first one for a 16-bit configuration).
<> 144:ef7eb2e8f9f7 127 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
<> 144:ef7eb2e8f9f7 130 configuration, second one for a 16-bit configuration).
<> 144:ef7eb2e8f9f7 131 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
<> 144:ef7eb2e8f9f7 134 according to the mode (MSBs for a 32-bit configuration,
<> 144:ef7eb2e8f9f7 135 first one for a 16-bit configuration).
<> 144:ef7eb2e8f9f7 136 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
<> 144:ef7eb2e8f9f7 139 according to the mode (LSBs for a 32-bit configuration,
<> 144:ef7eb2e8f9f7 140 second one for a 16-bit configuration).
<> 144:ef7eb2e8f9f7 141 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
<> 144:ef7eb2e8f9f7 144 This parameter can be a value of @ref CAN_filter_FIFO */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
<> 144:ef7eb2e8f9f7 147 This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
<> 144:ef7eb2e8f9f7 150 This parameter can be a value of @ref CAN_filter_mode */
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 uint32_t FilterScale; /*!< Specifies the filter scale.
<> 144:ef7eb2e8f9f7 153 This parameter can be a value of @ref CAN_filter_scale */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 uint32_t FilterActivation; /*!< Enable or disable the filter.
<> 144:ef7eb2e8f9f7 156 This parameter can be set to ENABLE or DISABLE. */
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 uint32_t BankNumber; /*!< Select the start slave bank filter
<> 144:ef7eb2e8f9f7 159 This parameter must be a number between Min_Data = 0 and Max_Data = 28. */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 }CAN_FilterConfTypeDef;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /**
<> 144:ef7eb2e8f9f7 164 * @brief CAN Tx message structure definition
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166 typedef struct
<> 144:ef7eb2e8f9f7 167 {
<> 144:ef7eb2e8f9f7 168 uint32_t StdId; /*!< Specifies the standard identifier.
<> 144:ef7eb2e8f9f7 169 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 uint32_t ExtId; /*!< Specifies the extended identifier.
<> 144:ef7eb2e8f9f7 172 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
<> 144:ef7eb2e8f9f7 175 This parameter can be a value of @ref CAN_identifier_type */
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
<> 144:ef7eb2e8f9f7 178 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
<> 144:ef7eb2e8f9f7 181 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 uint8_t Data[8]; /*!< Contains the data to be transmitted.
<> 144:ef7eb2e8f9f7 184 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186 }CanTxMsgTypeDef;
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /**
<> 144:ef7eb2e8f9f7 189 * @brief CAN Rx message structure definition
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 typedef struct
<> 144:ef7eb2e8f9f7 192 {
<> 144:ef7eb2e8f9f7 193 uint32_t StdId; /*!< Specifies the standard identifier.
<> 144:ef7eb2e8f9f7 194 This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 uint32_t ExtId; /*!< Specifies the extended identifier.
<> 144:ef7eb2e8f9f7 197 This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
<> 144:ef7eb2e8f9f7 200 This parameter can be a value of @ref CAN_identifier_type */
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 uint32_t RTR; /*!< Specifies the type of frame for the received message.
<> 144:ef7eb2e8f9f7 203 This parameter can be a value of @ref CAN_remote_transmission_request */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 uint32_t DLC; /*!< Specifies the length of the frame that will be received.
<> 144:ef7eb2e8f9f7 206 This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 uint8_t Data[8]; /*!< Contains the data to be received.
<> 144:ef7eb2e8f9f7 209 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
<> 144:ef7eb2e8f9f7 212 This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
<> 144:ef7eb2e8f9f7 215 This parameter can be CAN_FIFO0 or CAN_FIFO1 */
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 }CanRxMsgTypeDef;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 /**
<> 144:ef7eb2e8f9f7 220 * @brief CAN handle Structure definition
<> 144:ef7eb2e8f9f7 221 */
<> 144:ef7eb2e8f9f7 222 typedef struct
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 CAN_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 CAN_InitTypeDef Init; /*!< CAN required parameters */
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure */
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 HAL_LockTypeDef Lock; /*!< CAN locking object */
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 __IO uint32_t ErrorCode; /*!< CAN Error code
<> 144:ef7eb2e8f9f7 237 This parameter can be a value of @ref CAN_Error_Code */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 }CAN_HandleTypeDef;
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @}
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 /** @defgroup CAN_Exported_Constants CAN Exported Constants
<> 144:ef7eb2e8f9f7 247 * @{
<> 144:ef7eb2e8f9f7 248 */
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /** @defgroup CAN_Error_Code CAN Error Code
<> 144:ef7eb2e8f9f7 251 * @{
<> 144:ef7eb2e8f9f7 252 */
<> 156:95d6b41a828b 253 #define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
<> 156:95d6b41a828b 254 #define HAL_CAN_ERROR_EWG (0x00000001U) /*!< EWG error */
<> 156:95d6b41a828b 255 #define HAL_CAN_ERROR_EPV (0x00000002U) /*!< EPV error */
<> 156:95d6b41a828b 256 #define HAL_CAN_ERROR_BOF (0x00000004U) /*!< BOF error */
<> 156:95d6b41a828b 257 #define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
<> 156:95d6b41a828b 258 #define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
<> 156:95d6b41a828b 259 #define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
<> 156:95d6b41a828b 260 #define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive */
<> 156:95d6b41a828b 261 #define HAL_CAN_ERROR_BD (0x00000080U) /*!< LEC dominant */
<> 156:95d6b41a828b 262 #define HAL_CAN_ERROR_CRC (0x00000100U) /*!< LEC transfer error */
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @}
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /** @defgroup CAN_InitStatus CAN InitStatus
<> 144:ef7eb2e8f9f7 268 * @{
<> 144:ef7eb2e8f9f7 269 */
<> 156:95d6b41a828b 270 #define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
<> 156:95d6b41a828b 271 #define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @}
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /** @defgroup CAN_operating_mode CAN operating mode
<> 144:ef7eb2e8f9f7 277 * @{
<> 144:ef7eb2e8f9f7 278 */
<> 156:95d6b41a828b 279 #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
<> 144:ef7eb2e8f9f7 280 #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
<> 144:ef7eb2e8f9f7 281 #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
<> 144:ef7eb2e8f9f7 282 #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @}
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @defgroup CAN_synchronisation_jump_width CAN synchronisation jump width
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 156:95d6b41a828b 291 #define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 292 #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 293 #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 294 #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 295 /**
<> 144:ef7eb2e8f9f7 296 * @}
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN time quantum in bit segment 1
<> 144:ef7eb2e8f9f7 300 * @{
<> 144:ef7eb2e8f9f7 301 */
<> 156:95d6b41a828b 302 #define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 303 #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 304 #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 305 #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 306 #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 307 #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 308 #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 309 #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 310 #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
<> 144:ef7eb2e8f9f7 311 #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
<> 144:ef7eb2e8f9f7 312 #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
<> 144:ef7eb2e8f9f7 313 #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
<> 144:ef7eb2e8f9f7 314 #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
<> 144:ef7eb2e8f9f7 315 #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
<> 144:ef7eb2e8f9f7 316 #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
<> 144:ef7eb2e8f9f7 317 #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
<> 144:ef7eb2e8f9f7 318
<> 144:ef7eb2e8f9f7 319 /**
<> 144:ef7eb2e8f9f7 320 * @}
<> 144:ef7eb2e8f9f7 321 */
<> 144:ef7eb2e8f9f7 322
<> 144:ef7eb2e8f9f7 323 /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN time quantum in bit segment 2
<> 144:ef7eb2e8f9f7 324 * @{
<> 144:ef7eb2e8f9f7 325 */
<> 156:95d6b41a828b 326 #define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
<> 144:ef7eb2e8f9f7 327 #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
<> 144:ef7eb2e8f9f7 328 #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
<> 144:ef7eb2e8f9f7 329 #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
<> 144:ef7eb2e8f9f7 330 #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
<> 144:ef7eb2e8f9f7 331 #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
<> 144:ef7eb2e8f9f7 332 #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
<> 144:ef7eb2e8f9f7 333 #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 /**
<> 144:ef7eb2e8f9f7 336 * @}
<> 144:ef7eb2e8f9f7 337 */
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /** @defgroup CAN_filter_mode CAN filter mode
<> 144:ef7eb2e8f9f7 340 * @{
<> 144:ef7eb2e8f9f7 341 */
<> 156:95d6b41a828b 342 #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
<> 156:95d6b41a828b 343 #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 /**
<> 144:ef7eb2e8f9f7 346 * @}
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /** @defgroup CAN_filter_scale CAN filter scale
<> 144:ef7eb2e8f9f7 350 * @{
<> 144:ef7eb2e8f9f7 351 */
<> 156:95d6b41a828b 352 #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
<> 156:95d6b41a828b 353 #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
<> 144:ef7eb2e8f9f7 354
<> 144:ef7eb2e8f9f7 355 /**
<> 144:ef7eb2e8f9f7 356 * @}
<> 144:ef7eb2e8f9f7 357 */
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /** @defgroup CAN_filter_FIFO CAN filter FIFO
<> 144:ef7eb2e8f9f7 360 * @{
<> 144:ef7eb2e8f9f7 361 */
<> 156:95d6b41a828b 362 #define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
<> 156:95d6b41a828b 363 #define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 /**
<> 144:ef7eb2e8f9f7 366 * @}
<> 144:ef7eb2e8f9f7 367 */
<> 144:ef7eb2e8f9f7 368
<> 144:ef7eb2e8f9f7 369 /** @defgroup CAN_identifier_type CAN identifier type
<> 144:ef7eb2e8f9f7 370 * @{
<> 144:ef7eb2e8f9f7 371 */
<> 156:95d6b41a828b 372 #define CAN_ID_STD (0x00000000U) /*!< Standard Id */
<> 156:95d6b41a828b 373 #define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /**
<> 144:ef7eb2e8f9f7 376 * @}
<> 144:ef7eb2e8f9f7 377 */
<> 144:ef7eb2e8f9f7 378
<> 144:ef7eb2e8f9f7 379 /** @defgroup CAN_remote_transmission_request CAN remote transmission request
<> 144:ef7eb2e8f9f7 380 * @{
<> 144:ef7eb2e8f9f7 381 */
<> 156:95d6b41a828b 382 #define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
<> 156:95d6b41a828b 383 #define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /**
<> 144:ef7eb2e8f9f7 386 * @}
<> 144:ef7eb2e8f9f7 387 */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /** @defgroup CAN_receive_FIFO_number_constants CAN receive FIFO number constants
<> 144:ef7eb2e8f9f7 390 * @{
<> 144:ef7eb2e8f9f7 391 */
<> 156:95d6b41a828b 392 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
<> 156:95d6b41a828b 393 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 /**
<> 144:ef7eb2e8f9f7 396 * @}
<> 144:ef7eb2e8f9f7 397 */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 /** @defgroup CAN_flags CAN flags
<> 144:ef7eb2e8f9f7 400 * @{
<> 144:ef7eb2e8f9f7 401 */
<> 144:ef7eb2e8f9f7 402 /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
<> 144:ef7eb2e8f9f7 403 and CAN_ClearFlag() functions. */
<> 144:ef7eb2e8f9f7 404 /* If the flag is 0x1XXXXXXX, it means that it can only be used with
<> 144:ef7eb2e8f9f7 405 CAN_GetFlagStatus() function. */
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /* Transmit Flags */
<> 156:95d6b41a828b 408 #define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request MailBox0 flag */
<> 156:95d6b41a828b 409 #define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request MailBox1 flag */
<> 156:95d6b41a828b 410 #define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request MailBox2 flag */
<> 156:95d6b41a828b 411 #define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox0 flag */
<> 156:95d6b41a828b 412 #define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox1 flag */
<> 156:95d6b41a828b 413 #define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox2 flag */
<> 156:95d6b41a828b 414 #define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
<> 156:95d6b41a828b 415 #define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 0 empty flag */
<> 156:95d6b41a828b 416 #define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 0 empty flag */
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Receive Flags */
<> 156:95d6b41a828b 419 #define CAN_FLAG_FF0 (0x00000203U) /*!< FIFO 0 Full flag */
<> 156:95d6b41a828b 420 #define CAN_FLAG_FOV0 (0x00000204U) /*!< FIFO 0 Overrun flag */
<> 144:ef7eb2e8f9f7 421
<> 156:95d6b41a828b 422 #define CAN_FLAG_FF1 (0x00000403U) /*!< FIFO 1 Full flag */
<> 156:95d6b41a828b 423 #define CAN_FLAG_FOV1 (0x00000404U) /*!< FIFO 1 Overrun flag */
<> 144:ef7eb2e8f9f7 424
<> 144:ef7eb2e8f9f7 425 /* Operating Mode Flags */
<> 156:95d6b41a828b 426 #define CAN_FLAG_WKU (0x00000103U) /*!< Wake up flag */
<> 156:95d6b41a828b 427 #define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
<> 156:95d6b41a828b 428 #define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge flag */
<> 144:ef7eb2e8f9f7 429 /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
<> 144:ef7eb2e8f9f7 430 In this case the SLAK bit can be polled.*/
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /* Error Flags */
<> 156:95d6b41a828b 433 #define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
<> 156:95d6b41a828b 434 #define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
<> 156:95d6b41a828b 435 #define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
<> 144:ef7eb2e8f9f7 436 /**
<> 144:ef7eb2e8f9f7 437 * @}
<> 144:ef7eb2e8f9f7 438 */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /** @defgroup CAN_interrupts CAN interrupts
<> 144:ef7eb2e8f9f7 442 * @{
<> 144:ef7eb2e8f9f7 443 */
<> 144:ef7eb2e8f9f7 444 #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
<> 144:ef7eb2e8f9f7 445
<> 144:ef7eb2e8f9f7 446 /* Receive Interrupts */
<> 144:ef7eb2e8f9f7 447 #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
<> 144:ef7eb2e8f9f7 448 #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
<> 144:ef7eb2e8f9f7 449 #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
<> 144:ef7eb2e8f9f7 450 #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
<> 144:ef7eb2e8f9f7 451 #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
<> 144:ef7eb2e8f9f7 452 #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Operating Mode Interrupts */
<> 144:ef7eb2e8f9f7 455 #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
<> 144:ef7eb2e8f9f7 456 #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Error Interrupts */
<> 144:ef7eb2e8f9f7 459 #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
<> 144:ef7eb2e8f9f7 460 #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
<> 144:ef7eb2e8f9f7 461 #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
<> 144:ef7eb2e8f9f7 462 #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
<> 144:ef7eb2e8f9f7 463 #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /**
<> 144:ef7eb2e8f9f7 466 * @}
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /** @defgroup CAN_Mailboxes CAN Mailboxes
<> 144:ef7eb2e8f9f7 470 * @{
<> 144:ef7eb2e8f9f7 471 */
<> 144:ef7eb2e8f9f7 472 /* Mailboxes definition */
<> 156:95d6b41a828b 473 #define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
<> 156:95d6b41a828b 474 #define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
<> 156:95d6b41a828b 475 #define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @}
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 485 /** @defgroup CAN_Exported_Macros CAN Exported Macros
<> 144:ef7eb2e8f9f7 486 * @{
<> 144:ef7eb2e8f9f7 487 */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 /** @brief Reset CAN handle state
<> 144:ef7eb2e8f9f7 490 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 491 * @retval None
<> 144:ef7eb2e8f9f7 492 */
<> 144:ef7eb2e8f9f7 493 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief Enable the specified CAN interrupts.
<> 144:ef7eb2e8f9f7 497 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 498 * @param __INTERRUPT__: CAN Interrupt
<> 144:ef7eb2e8f9f7 499 * @retval None
<> 144:ef7eb2e8f9f7 500 */
<> 144:ef7eb2e8f9f7 501 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief Disable the specified CAN interrupts.
<> 144:ef7eb2e8f9f7 505 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 506 * @param __INTERRUPT__: CAN Interrupt
<> 144:ef7eb2e8f9f7 507 * @retval None
<> 144:ef7eb2e8f9f7 508 */
<> 144:ef7eb2e8f9f7 509 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 /**
<> 144:ef7eb2e8f9f7 512 * @brief Return the number of pending received messages.
<> 144:ef7eb2e8f9f7 513 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 514 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 515 * @retval The number of pending message.
<> 144:ef7eb2e8f9f7 516 */
<> 144:ef7eb2e8f9f7 517 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
<> 156:95d6b41a828b 518 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /** @brief Check whether the specified CAN flag is set or not.
<> 144:ef7eb2e8f9f7 521 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 522 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 523 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 524 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
<> 144:ef7eb2e8f9f7 525 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
<> 144:ef7eb2e8f9f7 526 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 527 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 528 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 529 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 530 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 531 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 532 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 533 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 534 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 535 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 536 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 537 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 538 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 539 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 540 * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 541 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 542 * @arg CAN_FLAG_EWG: Error Warning Flag
<> 144:ef7eb2e8f9f7 543 * @arg CAN_FLAG_EPV: Error Passive Flag
<> 144:ef7eb2e8f9f7 544 * @arg CAN_FLAG_BOF: Bus-Off Flag
<> 144:ef7eb2e8f9f7 545 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 546 */
<> 144:ef7eb2e8f9f7 547 #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
<> 156:95d6b41a828b 548 ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 549 (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 550 (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 551 (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 552 ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /** @brief Clear the specified CAN pending flag.
<> 144:ef7eb2e8f9f7 555 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 556 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 557 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 558 * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
<> 144:ef7eb2e8f9f7 559 * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
<> 144:ef7eb2e8f9f7 560 * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
<> 144:ef7eb2e8f9f7 561 * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
<> 144:ef7eb2e8f9f7 562 * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
<> 144:ef7eb2e8f9f7 563 * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
<> 144:ef7eb2e8f9f7 564 * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
<> 144:ef7eb2e8f9f7 565 * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
<> 144:ef7eb2e8f9f7 566 * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
<> 144:ef7eb2e8f9f7 567 * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
<> 144:ef7eb2e8f9f7 568 * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
<> 144:ef7eb2e8f9f7 569 * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
<> 144:ef7eb2e8f9f7 570 * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
<> 144:ef7eb2e8f9f7 571 * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
<> 144:ef7eb2e8f9f7 572 * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
<> 144:ef7eb2e8f9f7 573 * @arg CAN_FLAG_WKU: Wake up Flag
<> 144:ef7eb2e8f9f7 574 * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
<> 144:ef7eb2e8f9f7 575 * @arg CAN_FLAG_EWG: Error Warning Flag
<> 144:ef7eb2e8f9f7 576 * @arg CAN_FLAG_EPV: Error Passive Flag
<> 144:ef7eb2e8f9f7 577 * @arg CAN_FLAG_BOF: Bus-Off Flag
<> 144:ef7eb2e8f9f7 578 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<> 156:95d6b41a828b 581 ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 582 (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 583 (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
<> 156:95d6b41a828b 584 (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 /** @brief Check if the specified CAN interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 588 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 589 * @param __INTERRUPT__: specifies the CAN interrupt source to check.
<> 144:ef7eb2e8f9f7 590 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 591 * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
<> 144:ef7eb2e8f9f7 592 * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
<> 144:ef7eb2e8f9f7 593 * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
<> 144:ef7eb2e8f9f7 594 * @retval The new state of __IT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 595 */
<> 144:ef7eb2e8f9f7 596 #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @brief Check the transmission status of a CAN Frame.
<> 144:ef7eb2e8f9f7 600 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 601 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 602 * @retval The new status of transmission (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
<> 144:ef7eb2e8f9f7 605 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
<> 144:ef7eb2e8f9f7 606 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
<> 144:ef7eb2e8f9f7 607 ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @brief Release the specified receive FIFO.
<> 144:ef7eb2e8f9f7 613 * @param __HANDLE__: CAN handle.
<> 144:ef7eb2e8f9f7 614 * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
<> 144:ef7eb2e8f9f7 615 * @retval None
<> 144:ef7eb2e8f9f7 616 */
<> 144:ef7eb2e8f9f7 617 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
<> 144:ef7eb2e8f9f7 618 ((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1))
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /**
<> 144:ef7eb2e8f9f7 621 * @brief Cancel a transmit request.
<> 144:ef7eb2e8f9f7 622 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 623 * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
<> 144:ef7eb2e8f9f7 624 * @retval None
<> 144:ef7eb2e8f9f7 625 */
<> 144:ef7eb2e8f9f7 626 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
<> 144:ef7eb2e8f9f7 627 (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
<> 144:ef7eb2e8f9f7 628 ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
<> 144:ef7eb2e8f9f7 629 ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @brief Enable or disables the DBG Freeze for CAN.
<> 144:ef7eb2e8f9f7 633 * @param __HANDLE__: specifies the CAN Handle.
<> 144:ef7eb2e8f9f7 634 * @param __NEWSTATE__: new state of the CAN peripheral.
<> 144:ef7eb2e8f9f7 635 * This parameter can be: ENABLE (CAN reception/transmission is frozen
<> 144:ef7eb2e8f9f7 636 * during debug. Reception FIFOs can still be accessed/controlled normally)
<> 144:ef7eb2e8f9f7 637 * or DISABLE (CAN is working during debug).
<> 144:ef7eb2e8f9f7 638 * @retval None
<> 144:ef7eb2e8f9f7 639 */
<> 144:ef7eb2e8f9f7 640 #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
<> 144:ef7eb2e8f9f7 641 ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /**
<> 144:ef7eb2e8f9f7 644 * @}
<> 144:ef7eb2e8f9f7 645 */
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 648 /** @addtogroup CAN_Exported_Functions CAN Exported Functions
<> 144:ef7eb2e8f9f7 649 * @{
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 /** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 653 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 654 * @{
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Initialization and de-initialization functions *****************************/
<> 144:ef7eb2e8f9f7 658 HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 659 HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
<> 144:ef7eb2e8f9f7 660 HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 661 void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 662 void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 663 /**
<> 144:ef7eb2e8f9f7 664 * @}
<> 144:ef7eb2e8f9f7 665 */
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 668 * @brief I/O operation functions
<> 144:ef7eb2e8f9f7 669 * @{
<> 144:ef7eb2e8f9f7 670 */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* IO operation functions *****************************************************/
<> 144:ef7eb2e8f9f7 673 HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 674 HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 675 HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 676 HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
<> 144:ef7eb2e8f9f7 677 HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 678 HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 681
<> 144:ef7eb2e8f9f7 682 void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 683 void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 684 void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 685 /**
<> 144:ef7eb2e8f9f7 686 * @}
<> 144:ef7eb2e8f9f7 687 */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 /** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
<> 144:ef7eb2e8f9f7 690 * @brief CAN Peripheral State functions
<> 144:ef7eb2e8f9f7 691 * @{
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 /* Peripheral State and Error functions ***************************************/
<> 144:ef7eb2e8f9f7 694 uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
<> 144:ef7eb2e8f9f7 695 HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /**
<> 144:ef7eb2e8f9f7 698 * @}
<> 144:ef7eb2e8f9f7 699 */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @}
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 706 /** @defgroup CAN_Private_Types CAN Private Types
<> 144:ef7eb2e8f9f7 707 * @{
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @}
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 715 /** @defgroup CAN_Private_Variables CAN Private Variables
<> 144:ef7eb2e8f9f7 716 * @{
<> 144:ef7eb2e8f9f7 717 */
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 /**
<> 144:ef7eb2e8f9f7 720 * @}
<> 144:ef7eb2e8f9f7 721 */
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 724 /** @defgroup CAN_Private_Constants CAN Private Constants
<> 144:ef7eb2e8f9f7 725 * @{
<> 144:ef7eb2e8f9f7 726 */
<> 156:95d6b41a828b 727 #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
<> 156:95d6b41a828b 728 #define CAN_FLAG_MASK (0x000000FFU)
<> 144:ef7eb2e8f9f7 729 /**
<> 144:ef7eb2e8f9f7 730 * @}
<> 144:ef7eb2e8f9f7 731 */
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 734 /** @defgroup CAN_Private_Macros CAN Private Macros
<> 144:ef7eb2e8f9f7 735 * @{
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
<> 144:ef7eb2e8f9f7 738 ((MODE) == CAN_MODE_LOOPBACK)|| \
<> 144:ef7eb2e8f9f7 739 ((MODE) == CAN_MODE_SILENT) || \
<> 144:ef7eb2e8f9f7 740 ((MODE) == CAN_MODE_SILENT_LOOPBACK))
<> 144:ef7eb2e8f9f7 741 #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
<> 144:ef7eb2e8f9f7 742 ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
<> 144:ef7eb2e8f9f7 743 #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
<> 144:ef7eb2e8f9f7 744 #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
<> 144:ef7eb2e8f9f7 745 #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
<> 144:ef7eb2e8f9f7 746 #define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
<> 144:ef7eb2e8f9f7 747 #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
<> 144:ef7eb2e8f9f7 748 ((MODE) == CAN_FILTERMODE_IDLIST))
<> 144:ef7eb2e8f9f7 749 #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
<> 144:ef7eb2e8f9f7 750 ((SCALE) == CAN_FILTERSCALE_32BIT))
<> 144:ef7eb2e8f9f7 751 #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
<> 144:ef7eb2e8f9f7 752 ((FIFO) == CAN_FILTER_FIFO1))
<> 144:ef7eb2e8f9f7 753 #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
<> 144:ef7eb2e8f9f7 754
<> 156:95d6b41a828b 755 #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02U))
<> 156:95d6b41a828b 756 #define IS_CAN_STDID(STDID) ((STDID) <= (0x7FFU))
<> 156:95d6b41a828b 757 #define IS_CAN_EXTID(EXTID) ((EXTID) <= (0x1FFFFFFFU))
<> 156:95d6b41a828b 758 #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08U))
<> 144:ef7eb2e8f9f7 759
<> 144:ef7eb2e8f9f7 760 #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
<> 144:ef7eb2e8f9f7 761 ((IDTYPE) == CAN_ID_EXT))
<> 144:ef7eb2e8f9f7 762 #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
<> 144:ef7eb2e8f9f7 763 #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @}
<> 144:ef7eb2e8f9f7 767 */
<> 144:ef7eb2e8f9f7 768
<> 144:ef7eb2e8f9f7 769 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 770 /** @defgroup CAN_Private_Functions CAN Private Functions
<> 144:ef7eb2e8f9f7 771 * @{
<> 144:ef7eb2e8f9f7 772 */
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /**
<> 144:ef7eb2e8f9f7 775 * @}
<> 144:ef7eb2e8f9f7 776 */
<> 144:ef7eb2e8f9f7 777
<> 144:ef7eb2e8f9f7 778 /**
<> 144:ef7eb2e8f9f7 779 * @}
<> 144:ef7eb2e8f9f7 780 */
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /**
<> 144:ef7eb2e8f9f7 783 * @}
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 #endif /* STM32F072xB || STM32F042x6 || STM32F048xx || STM32F078xx || STM32F091xC || STM32F098xx */
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 789 }
<> 144:ef7eb2e8f9f7 790 #endif
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 #endif /* __STM32F0xx_HAL_CAN_H */
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794
<> 144:ef7eb2e8f9f7 795 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 796