mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_M480/gpio_irq_api.c@172:7d866c31b3c5, 2017-08-31 (annotated)

Committer:
AnnaBridge
Date:
Thu Aug 31 17:27:04 2017 +0100
Revision:
172:7d866c31b3c5
This updates the lib to the mbed lib v 150

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /* mbed Microcontroller Library
AnnaBridge 172:7d866c31b3c5 2 * Copyright (c) 2015-2016 Nuvoton
AnnaBridge 172:7d866c31b3c5 3 *
AnnaBridge 172:7d866c31b3c5 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 172:7d866c31b3c5 5 * you may not use this file except in compliance with the License.
AnnaBridge 172:7d866c31b3c5 6 * You may obtain a copy of the License at
AnnaBridge 172:7d866c31b3c5 7 *
AnnaBridge 172:7d866c31b3c5 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 172:7d866c31b3c5 9 *
AnnaBridge 172:7d866c31b3c5 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 172:7d866c31b3c5 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 172:7d866c31b3c5 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 172:7d866c31b3c5 13 * See the License for the specific language governing permissions and
AnnaBridge 172:7d866c31b3c5 14 * limitations under the License.
AnnaBridge 172:7d866c31b3c5 15 */
AnnaBridge 172:7d866c31b3c5 16
AnnaBridge 172:7d866c31b3c5 17 #include "gpio_irq_api.h"
AnnaBridge 172:7d866c31b3c5 18
AnnaBridge 172:7d866c31b3c5 19 #if DEVICE_INTERRUPTIN
AnnaBridge 172:7d866c31b3c5 20
AnnaBridge 172:7d866c31b3c5 21 #include "gpio_api.h"
AnnaBridge 172:7d866c31b3c5 22 #include "cmsis.h"
AnnaBridge 172:7d866c31b3c5 23 #include "pinmap.h"
AnnaBridge 172:7d866c31b3c5 24 #include "PeripheralPins.h"
AnnaBridge 172:7d866c31b3c5 25 #include "nu_bitutil.h"
AnnaBridge 172:7d866c31b3c5 26
AnnaBridge 172:7d866c31b3c5 27 #define NU_MAX_PIN_PER_PORT 16
AnnaBridge 172:7d866c31b3c5 28
AnnaBridge 172:7d866c31b3c5 29 struct nu_gpio_irq_var {
AnnaBridge 172:7d866c31b3c5 30 gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
AnnaBridge 172:7d866c31b3c5 31 IRQn_Type irq_n;
AnnaBridge 172:7d866c31b3c5 32 void (*vec)(void);
AnnaBridge 172:7d866c31b3c5 33 uint32_t port_index;
AnnaBridge 172:7d866c31b3c5 34 };
AnnaBridge 172:7d866c31b3c5 35
AnnaBridge 172:7d866c31b3c5 36 static void gpio_irq_0_vec(void);
AnnaBridge 172:7d866c31b3c5 37 static void gpio_irq_1_vec(void);
AnnaBridge 172:7d866c31b3c5 38 static void gpio_irq_2_vec(void);
AnnaBridge 172:7d866c31b3c5 39 static void gpio_irq_3_vec(void);
AnnaBridge 172:7d866c31b3c5 40 static void gpio_irq_4_vec(void);
AnnaBridge 172:7d866c31b3c5 41 static void gpio_irq_5_vec(void);
AnnaBridge 172:7d866c31b3c5 42 static void gpio_irq_6_vec(void);
AnnaBridge 172:7d866c31b3c5 43 static void gpio_irq_7_vec(void);
AnnaBridge 172:7d866c31b3c5 44 static void gpio_irq(struct nu_gpio_irq_var *var);
AnnaBridge 172:7d866c31b3c5 45
AnnaBridge 172:7d866c31b3c5 46 //EINT0_IRQn
AnnaBridge 172:7d866c31b3c5 47 static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
AnnaBridge 172:7d866c31b3c5 48 {{NULL}, GPA_IRQn, gpio_irq_0_vec, 0},
AnnaBridge 172:7d866c31b3c5 49 {{NULL}, GPB_IRQn, gpio_irq_1_vec, 1},
AnnaBridge 172:7d866c31b3c5 50 {{NULL}, GPC_IRQn, gpio_irq_2_vec, 2},
AnnaBridge 172:7d866c31b3c5 51 {{NULL}, GPD_IRQn, gpio_irq_3_vec, 3},
AnnaBridge 172:7d866c31b3c5 52 {{NULL}, GPE_IRQn, gpio_irq_4_vec, 4},
AnnaBridge 172:7d866c31b3c5 53 {{NULL}, GPF_IRQn, gpio_irq_5_vec, 5},
AnnaBridge 172:7d866c31b3c5 54 {{NULL}, GPG_IRQn, gpio_irq_6_vec, 6},
AnnaBridge 172:7d866c31b3c5 55 {{NULL}, GPH_IRQn, gpio_irq_7_vec, 7},
AnnaBridge 172:7d866c31b3c5 56 };
AnnaBridge 172:7d866c31b3c5 57
AnnaBridge 172:7d866c31b3c5 58 #define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
AnnaBridge 172:7d866c31b3c5 59
AnnaBridge 172:7d866c31b3c5 60 #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
AnnaBridge 172:7d866c31b3c5 61 #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE 0
AnnaBridge 172:7d866c31b3c5 62 #endif
AnnaBridge 172:7d866c31b3c5 63
AnnaBridge 172:7d866c31b3c5 64 #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
AnnaBridge 172:7d866c31b3c5 65 #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
AnnaBridge 172:7d866c31b3c5 66 #endif
AnnaBridge 172:7d866c31b3c5 67 static PinName gpio_irq_debounce_arr[] = {
AnnaBridge 172:7d866c31b3c5 68 MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
AnnaBridge 172:7d866c31b3c5 69 };
AnnaBridge 172:7d866c31b3c5 70
AnnaBridge 172:7d866c31b3c5 71 #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
AnnaBridge 172:7d866c31b3c5 72 #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
AnnaBridge 172:7d866c31b3c5 73 #endif
AnnaBridge 172:7d866c31b3c5 74
AnnaBridge 172:7d866c31b3c5 75 #ifndef MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
AnnaBridge 172:7d866c31b3c5 76 #define MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
AnnaBridge 172:7d866c31b3c5 77 #endif
AnnaBridge 172:7d866c31b3c5 78
AnnaBridge 172:7d866c31b3c5 79 int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
AnnaBridge 172:7d866c31b3c5 80 {
AnnaBridge 172:7d866c31b3c5 81 if (pin == NC) {
AnnaBridge 172:7d866c31b3c5 82 return -1;
AnnaBridge 172:7d866c31b3c5 83 }
AnnaBridge 172:7d866c31b3c5 84
AnnaBridge 172:7d866c31b3c5 85 uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
AnnaBridge 172:7d866c31b3c5 86 uint32_t port_index = NU_PINNAME_TO_PORT(pin);
AnnaBridge 172:7d866c31b3c5 87 if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
AnnaBridge 172:7d866c31b3c5 88 return -1;
AnnaBridge 172:7d866c31b3c5 89 }
AnnaBridge 172:7d866c31b3c5 90
AnnaBridge 172:7d866c31b3c5 91 obj->pin = pin;
AnnaBridge 172:7d866c31b3c5 92 obj->irq_handler = (uint32_t) handler;
AnnaBridge 172:7d866c31b3c5 93 obj->irq_id = id;
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
AnnaBridge 172:7d866c31b3c5 96 // NOTE: In InterruptIn constructor, gpio_irq_init() is called with gpio_init_in() which is responsible for multi-function pin setting.
AnnaBridge 172:7d866c31b3c5 97 // There is no need to call gpio_set() redundantly.
AnnaBridge 172:7d866c31b3c5 98
AnnaBridge 172:7d866c31b3c5 99 {
AnnaBridge 172:7d866c31b3c5 100 #if MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_ENABLE
AnnaBridge 172:7d866c31b3c5 101 // Suppress compiler warning
AnnaBridge 172:7d866c31b3c5 102 (void) gpio_irq_debounce_arr;
AnnaBridge 172:7d866c31b3c5 103
AnnaBridge 172:7d866c31b3c5 104 // Configure de-bounce clock source and sampling cycle time
AnnaBridge 172:7d866c31b3c5 105 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
AnnaBridge 172:7d866c31b3c5 106 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
AnnaBridge 172:7d866c31b3c5 107 #else
AnnaBridge 172:7d866c31b3c5 108 // Enable de-bounce if the pin is in the de-bounce enable list
AnnaBridge 172:7d866c31b3c5 109
AnnaBridge 172:7d866c31b3c5 110 // De-bounce defaults to disabled.
AnnaBridge 172:7d866c31b3c5 111 GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
AnnaBridge 172:7d866c31b3c5 112
AnnaBridge 172:7d866c31b3c5 113 PinName *debounce_pos = gpio_irq_debounce_arr;
AnnaBridge 172:7d866c31b3c5 114 PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
AnnaBridge 172:7d866c31b3c5 115 for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
AnnaBridge 172:7d866c31b3c5 116 uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
AnnaBridge 172:7d866c31b3c5 117 uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
AnnaBridge 172:7d866c31b3c5 118
AnnaBridge 172:7d866c31b3c5 119 if (pin_index == pin_index_debunce &&
AnnaBridge 172:7d866c31b3c5 120 port_index == port_index_debounce) {
AnnaBridge 172:7d866c31b3c5 121 // Configure de-bounce clock source and sampling cycle time
AnnaBridge 172:7d866c31b3c5 122 GPIO_SET_DEBOUNCE_TIME(MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_TARGET_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
AnnaBridge 172:7d866c31b3c5 123 GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
AnnaBridge 172:7d866c31b3c5 124 break;
AnnaBridge 172:7d866c31b3c5 125 }
AnnaBridge 172:7d866c31b3c5 126 }
AnnaBridge 172:7d866c31b3c5 127 #endif
AnnaBridge 172:7d866c31b3c5 128 }
AnnaBridge 172:7d866c31b3c5 129
AnnaBridge 172:7d866c31b3c5 130 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
AnnaBridge 172:7d866c31b3c5 131
AnnaBridge 172:7d866c31b3c5 132 var->obj_arr[pin_index] = obj;
AnnaBridge 172:7d866c31b3c5 133
AnnaBridge 172:7d866c31b3c5 134 // NOTE: InterruptIn requires IRQ enabled by default.
AnnaBridge 172:7d866c31b3c5 135 gpio_irq_enable(obj);
AnnaBridge 172:7d866c31b3c5 136
AnnaBridge 172:7d866c31b3c5 137 return 0;
AnnaBridge 172:7d866c31b3c5 138 }
AnnaBridge 172:7d866c31b3c5 139
AnnaBridge 172:7d866c31b3c5 140 void gpio_irq_free(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 141 {
AnnaBridge 172:7d866c31b3c5 142 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
AnnaBridge 172:7d866c31b3c5 143 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
AnnaBridge 172:7d866c31b3c5 144 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
AnnaBridge 172:7d866c31b3c5 145
AnnaBridge 172:7d866c31b3c5 146 NVIC_DisableIRQ(var->irq_n);
AnnaBridge 172:7d866c31b3c5 147 NU_PORT_BASE(port_index)->INTEN = 0;
AnnaBridge 172:7d866c31b3c5 148
AnnaBridge 172:7d866c31b3c5 149 MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
AnnaBridge 172:7d866c31b3c5 150 var->obj_arr[pin_index] = NULL;
AnnaBridge 172:7d866c31b3c5 151 }
AnnaBridge 172:7d866c31b3c5 152
AnnaBridge 172:7d866c31b3c5 153 void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
AnnaBridge 172:7d866c31b3c5 154 {
AnnaBridge 172:7d866c31b3c5 155 uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
AnnaBridge 172:7d866c31b3c5 156 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
AnnaBridge 172:7d866c31b3c5 157 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
AnnaBridge 172:7d866c31b3c5 158
AnnaBridge 172:7d866c31b3c5 159 switch (event) {
AnnaBridge 172:7d866c31b3c5 160 case IRQ_RISE:
AnnaBridge 172:7d866c31b3c5 161 if (enable) {
AnnaBridge 172:7d866c31b3c5 162 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
AnnaBridge 172:7d866c31b3c5 163 } else {
AnnaBridge 172:7d866c31b3c5 164 gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
AnnaBridge 172:7d866c31b3c5 165 }
AnnaBridge 172:7d866c31b3c5 166 break;
AnnaBridge 172:7d866c31b3c5 167
AnnaBridge 172:7d866c31b3c5 168 case IRQ_FALL:
AnnaBridge 172:7d866c31b3c5 169 if (enable) {
AnnaBridge 172:7d866c31b3c5 170 GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
AnnaBridge 172:7d866c31b3c5 171 } else {
AnnaBridge 172:7d866c31b3c5 172 gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
AnnaBridge 172:7d866c31b3c5 173 }
AnnaBridge 172:7d866c31b3c5 174 break;
AnnaBridge 172:7d866c31b3c5 175
AnnaBridge 172:7d866c31b3c5 176 case IRQ_NONE:
AnnaBridge 172:7d866c31b3c5 177 default:
AnnaBridge 172:7d866c31b3c5 178 break;
AnnaBridge 172:7d866c31b3c5 179 }
AnnaBridge 172:7d866c31b3c5 180 }
AnnaBridge 172:7d866c31b3c5 181
AnnaBridge 172:7d866c31b3c5 182 void gpio_irq_enable(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 183 {
AnnaBridge 172:7d866c31b3c5 184 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
AnnaBridge 172:7d866c31b3c5 185 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
AnnaBridge 172:7d866c31b3c5 186
AnnaBridge 172:7d866c31b3c5 187 NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
AnnaBridge 172:7d866c31b3c5 188 NVIC_EnableIRQ(var->irq_n);
AnnaBridge 172:7d866c31b3c5 189 }
AnnaBridge 172:7d866c31b3c5 190
AnnaBridge 172:7d866c31b3c5 191 void gpio_irq_disable(gpio_irq_t *obj)
AnnaBridge 172:7d866c31b3c5 192 {
AnnaBridge 172:7d866c31b3c5 193 uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
AnnaBridge 172:7d866c31b3c5 194 struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
AnnaBridge 172:7d866c31b3c5 195
AnnaBridge 172:7d866c31b3c5 196 NVIC_DisableIRQ(var->irq_n);
AnnaBridge 172:7d866c31b3c5 197 }
AnnaBridge 172:7d866c31b3c5 198
AnnaBridge 172:7d866c31b3c5 199 static void gpio_irq_0_vec(void)
AnnaBridge 172:7d866c31b3c5 200 {
AnnaBridge 172:7d866c31b3c5 201 gpio_irq(gpio_irq_var_arr + 0);
AnnaBridge 172:7d866c31b3c5 202 }
AnnaBridge 172:7d866c31b3c5 203 static void gpio_irq_1_vec(void)
AnnaBridge 172:7d866c31b3c5 204 {
AnnaBridge 172:7d866c31b3c5 205 gpio_irq(gpio_irq_var_arr + 1);
AnnaBridge 172:7d866c31b3c5 206 }
AnnaBridge 172:7d866c31b3c5 207 static void gpio_irq_2_vec(void)
AnnaBridge 172:7d866c31b3c5 208 {
AnnaBridge 172:7d866c31b3c5 209 gpio_irq(gpio_irq_var_arr + 2);
AnnaBridge 172:7d866c31b3c5 210 }
AnnaBridge 172:7d866c31b3c5 211 static void gpio_irq_3_vec(void)
AnnaBridge 172:7d866c31b3c5 212 {
AnnaBridge 172:7d866c31b3c5 213 gpio_irq(gpio_irq_var_arr + 3);
AnnaBridge 172:7d866c31b3c5 214 }
AnnaBridge 172:7d866c31b3c5 215 static void gpio_irq_4_vec(void)
AnnaBridge 172:7d866c31b3c5 216 {
AnnaBridge 172:7d866c31b3c5 217 gpio_irq(gpio_irq_var_arr + 4);
AnnaBridge 172:7d866c31b3c5 218 }
AnnaBridge 172:7d866c31b3c5 219 static void gpio_irq_5_vec(void)
AnnaBridge 172:7d866c31b3c5 220 {
AnnaBridge 172:7d866c31b3c5 221 gpio_irq(gpio_irq_var_arr + 5);
AnnaBridge 172:7d866c31b3c5 222 }
AnnaBridge 172:7d866c31b3c5 223 static void gpio_irq_6_vec(void)
AnnaBridge 172:7d866c31b3c5 224 {
AnnaBridge 172:7d866c31b3c5 225 gpio_irq(gpio_irq_var_arr + 6);
AnnaBridge 172:7d866c31b3c5 226 }
AnnaBridge 172:7d866c31b3c5 227 static void gpio_irq_7_vec(void)
AnnaBridge 172:7d866c31b3c5 228 {
AnnaBridge 172:7d866c31b3c5 229 gpio_irq(gpio_irq_var_arr + 7);
AnnaBridge 172:7d866c31b3c5 230 }
AnnaBridge 172:7d866c31b3c5 231
AnnaBridge 172:7d866c31b3c5 232 static void gpio_irq(struct nu_gpio_irq_var *var)
AnnaBridge 172:7d866c31b3c5 233 {
AnnaBridge 172:7d866c31b3c5 234 // NOTE: GPA_IRQn, GPB_IRQn, ... are not arranged sequentially, so we cannot calculate out port_index through offset from GPA_IRQn.
AnnaBridge 172:7d866c31b3c5 235 // Instead, we add port_index into gpio_irq_var_arr table.
AnnaBridge 172:7d866c31b3c5 236 uint32_t port_index = var->port_index;
AnnaBridge 172:7d866c31b3c5 237 GPIO_T *gpio_base = NU_PORT_BASE(port_index);
AnnaBridge 172:7d866c31b3c5 238
AnnaBridge 172:7d866c31b3c5 239 uint32_t intsrc = gpio_base->INTSRC;
AnnaBridge 172:7d866c31b3c5 240 uint32_t inten = gpio_base->INTEN;
AnnaBridge 172:7d866c31b3c5 241 while (intsrc) {
AnnaBridge 172:7d866c31b3c5 242 int pin_index = nu_ctz(intsrc);
AnnaBridge 172:7d866c31b3c5 243 gpio_irq_t *obj = var->obj_arr[pin_index];
AnnaBridge 172:7d866c31b3c5 244 if (inten & (GPIO_INT_RISING << pin_index)) {
AnnaBridge 172:7d866c31b3c5 245 if (GPIO_PIN_DATA(port_index, pin_index)) {
AnnaBridge 172:7d866c31b3c5 246 if (obj->irq_handler) {
AnnaBridge 172:7d866c31b3c5 247 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
AnnaBridge 172:7d866c31b3c5 248 }
AnnaBridge 172:7d866c31b3c5 249 }
AnnaBridge 172:7d866c31b3c5 250 }
AnnaBridge 172:7d866c31b3c5 251
AnnaBridge 172:7d866c31b3c5 252 if (inten & (GPIO_INT_FALLING << pin_index)) {
AnnaBridge 172:7d866c31b3c5 253 if (! GPIO_PIN_DATA(port_index, pin_index)) {
AnnaBridge 172:7d866c31b3c5 254 if (obj->irq_handler) {
AnnaBridge 172:7d866c31b3c5 255 ((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
AnnaBridge 172:7d866c31b3c5 256 }
AnnaBridge 172:7d866c31b3c5 257 }
AnnaBridge 172:7d866c31b3c5 258 }
AnnaBridge 172:7d866c31b3c5 259
AnnaBridge 172:7d866c31b3c5 260 intsrc &= ~(1 << pin_index);
AnnaBridge 172:7d866c31b3c5 261 }
AnnaBridge 172:7d866c31b3c5 262 // Clear all interrupt flags
AnnaBridge 172:7d866c31b3c5 263 gpio_base->INTSRC = gpio_base->INTSRC;
AnnaBridge 172:7d866c31b3c5 264 }
AnnaBridge 172:7d866c31b3c5 265
AnnaBridge 172:7d866c31b3c5 266 #endif