mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_clk.c@172:7d866c31b3c5, 2017-08-31 (annotated)

Committer:
AnnaBridge
Date:
Thu Aug 31 17:27:04 2017 +0100
Revision:
172:7d866c31b3c5
This updates the lib to the mbed lib v 150

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 172:7d866c31b3c5 1 /**************************************************************************//**
AnnaBridge 172:7d866c31b3c5 2 * @file clk.c
AnnaBridge 172:7d866c31b3c5 3 * @version V3.00
AnnaBridge 172:7d866c31b3c5 4 * @brief M480 series CLK driver source file
AnnaBridge 172:7d866c31b3c5 5 *
AnnaBridge 172:7d866c31b3c5 6 * @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
AnnaBridge 172:7d866c31b3c5 7 *****************************************************************************/
AnnaBridge 172:7d866c31b3c5 8
AnnaBridge 172:7d866c31b3c5 9 #include "M480.h"
AnnaBridge 172:7d866c31b3c5 10
AnnaBridge 172:7d866c31b3c5 11 /** @addtogroup M480_Device_Driver M480 Device Driver
AnnaBridge 172:7d866c31b3c5 12 @{
AnnaBridge 172:7d866c31b3c5 13 */
AnnaBridge 172:7d866c31b3c5 14
AnnaBridge 172:7d866c31b3c5 15 /** @addtogroup M480_CLK_Driver CLK Driver
AnnaBridge 172:7d866c31b3c5 16 @{
AnnaBridge 172:7d866c31b3c5 17 */
AnnaBridge 172:7d866c31b3c5 18
AnnaBridge 172:7d866c31b3c5 19 /** @addtogroup M480_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
AnnaBridge 172:7d866c31b3c5 20 @{
AnnaBridge 172:7d866c31b3c5 21 */
AnnaBridge 172:7d866c31b3c5 22
AnnaBridge 172:7d866c31b3c5 23 /**
AnnaBridge 172:7d866c31b3c5 24 * @brief Disable clock divider output function
AnnaBridge 172:7d866c31b3c5 25 * @param None
AnnaBridge 172:7d866c31b3c5 26 * @return None
AnnaBridge 172:7d866c31b3c5 27 * @details This function disable clock divider output function.
AnnaBridge 172:7d866c31b3c5 28 */
AnnaBridge 172:7d866c31b3c5 29 void CLK_DisableCKO(void)
AnnaBridge 172:7d866c31b3c5 30 {
AnnaBridge 172:7d866c31b3c5 31 /* Disable CKO clock source */
AnnaBridge 172:7d866c31b3c5 32 CLK_DisableModuleClock(CLKO_MODULE);
AnnaBridge 172:7d866c31b3c5 33 }
AnnaBridge 172:7d866c31b3c5 34
AnnaBridge 172:7d866c31b3c5 35 /**
AnnaBridge 172:7d866c31b3c5 36 * @brief This function enable clock divider output module clock,
AnnaBridge 172:7d866c31b3c5 37 * enable clock divider output function and set frequency selection.
AnnaBridge 172:7d866c31b3c5 38 * @param[in] u32ClkSrc is frequency divider function clock source. Including :
AnnaBridge 172:7d866c31b3c5 39 * - \ref CLK_CLKSEL1_CLKOSEL_HXT
AnnaBridge 172:7d866c31b3c5 40 * - \ref CLK_CLKSEL1_CLKOSEL_LXT
AnnaBridge 172:7d866c31b3c5 41 * - \ref CLK_CLKSEL1_CLKOSEL_HCLK
AnnaBridge 172:7d866c31b3c5 42 * - \ref CLK_CLKSEL1_CLKOSEL_HIRC
AnnaBridge 172:7d866c31b3c5 43 * @param[in] u32ClkDiv is divider output frequency selection. It could be 0~15.
AnnaBridge 172:7d866c31b3c5 44 * @param[in] u32ClkDivBy1En is clock divided by one enabled.
AnnaBridge 172:7d866c31b3c5 45 * @return None
AnnaBridge 172:7d866c31b3c5 46 * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. \n
AnnaBridge 172:7d866c31b3c5 47 * The formula is: \n
AnnaBridge 172:7d866c31b3c5 48 * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) \n
AnnaBridge 172:7d866c31b3c5 49 * This function is just used to set CKO clock.
AnnaBridge 172:7d866c31b3c5 50 * User must enable I/O for CKO clock output pin by themselves. \n
AnnaBridge 172:7d866c31b3c5 51 */
AnnaBridge 172:7d866c31b3c5 52 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
AnnaBridge 172:7d866c31b3c5 53 {
AnnaBridge 172:7d866c31b3c5 54 /* CKO = clock source / 2^(u32ClkDiv + 1) */
AnnaBridge 172:7d866c31b3c5 55 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | (u32ClkDiv) | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos);
AnnaBridge 172:7d866c31b3c5 56
AnnaBridge 172:7d866c31b3c5 57 /* Enable CKO clock source */
AnnaBridge 172:7d866c31b3c5 58 CLK_EnableModuleClock(CLKO_MODULE);
AnnaBridge 172:7d866c31b3c5 59
AnnaBridge 172:7d866c31b3c5 60 /* Select CKO clock source */
AnnaBridge 172:7d866c31b3c5 61 CLK_SetModuleClock(CLKO_MODULE, u32ClkSrc, 0UL);
AnnaBridge 172:7d866c31b3c5 62 }
AnnaBridge 172:7d866c31b3c5 63
AnnaBridge 172:7d866c31b3c5 64 /**
AnnaBridge 172:7d866c31b3c5 65 * @brief Enter to Power-down mode
AnnaBridge 172:7d866c31b3c5 66 * @param None
AnnaBridge 172:7d866c31b3c5 67 * @return None
AnnaBridge 172:7d866c31b3c5 68 * @details This function is used to let system enter to Power-down mode. \n
AnnaBridge 172:7d866c31b3c5 69 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 70 */
AnnaBridge 172:7d866c31b3c5 71 void CLK_PowerDown(void)
AnnaBridge 172:7d866c31b3c5 72 {
AnnaBridge 172:7d866c31b3c5 73 /* Set the processor uses deep sleep as its low power mode */
AnnaBridge 172:7d866c31b3c5 74 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 172:7d866c31b3c5 75
AnnaBridge 172:7d866c31b3c5 76 /* Set system Power-down enabled and Power-down entry condition */
AnnaBridge 172:7d866c31b3c5 77 CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk;
AnnaBridge 172:7d866c31b3c5 78
AnnaBridge 172:7d866c31b3c5 79 /* Chip enter Power-down mode after CPU run WFI instruction */
AnnaBridge 172:7d866c31b3c5 80 __WFI();
AnnaBridge 172:7d866c31b3c5 81 }
AnnaBridge 172:7d866c31b3c5 82
AnnaBridge 172:7d866c31b3c5 83 /**
AnnaBridge 172:7d866c31b3c5 84 * @brief Enter to Idle mode
AnnaBridge 172:7d866c31b3c5 85 * @param None
AnnaBridge 172:7d866c31b3c5 86 * @return None
AnnaBridge 172:7d866c31b3c5 87 * @details This function let system enter to Idle mode. \n
AnnaBridge 172:7d866c31b3c5 88 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 89 */
AnnaBridge 172:7d866c31b3c5 90 void CLK_Idle(void)
AnnaBridge 172:7d866c31b3c5 91 {
AnnaBridge 172:7d866c31b3c5 92 /* Set the processor uses sleep as its low power mode */
AnnaBridge 172:7d866c31b3c5 93 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
AnnaBridge 172:7d866c31b3c5 94
AnnaBridge 172:7d866c31b3c5 95 /* Set chip in idle mode because of WFI command */
AnnaBridge 172:7d866c31b3c5 96 CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk;
AnnaBridge 172:7d866c31b3c5 97
AnnaBridge 172:7d866c31b3c5 98 /* Chip enter idle mode after CPU run WFI instruction */
AnnaBridge 172:7d866c31b3c5 99 __WFI();
AnnaBridge 172:7d866c31b3c5 100 }
AnnaBridge 172:7d866c31b3c5 101
AnnaBridge 172:7d866c31b3c5 102 /**
AnnaBridge 172:7d866c31b3c5 103 * @brief Get external high speed crystal clock frequency
AnnaBridge 172:7d866c31b3c5 104 * @param None
AnnaBridge 172:7d866c31b3c5 105 * @return External high frequency crystal frequency
AnnaBridge 172:7d866c31b3c5 106 * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 107 */
AnnaBridge 172:7d866c31b3c5 108 uint32_t CLK_GetHXTFreq(void)
AnnaBridge 172:7d866c31b3c5 109 {
AnnaBridge 172:7d866c31b3c5 110 uint32_t u32Freq;
AnnaBridge 172:7d866c31b3c5 111
AnnaBridge 172:7d866c31b3c5 112 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
AnnaBridge 172:7d866c31b3c5 113 u32Freq = __HXT;
AnnaBridge 172:7d866c31b3c5 114 } else {
AnnaBridge 172:7d866c31b3c5 115 u32Freq = 0UL;
AnnaBridge 172:7d866c31b3c5 116 }
AnnaBridge 172:7d866c31b3c5 117
AnnaBridge 172:7d866c31b3c5 118 return u32Freq;
AnnaBridge 172:7d866c31b3c5 119 }
AnnaBridge 172:7d866c31b3c5 120
AnnaBridge 172:7d866c31b3c5 121
AnnaBridge 172:7d866c31b3c5 122 /**
AnnaBridge 172:7d866c31b3c5 123 * @brief Get external low speed crystal clock frequency
AnnaBridge 172:7d866c31b3c5 124 * @param None
AnnaBridge 172:7d866c31b3c5 125 * @return External low speed crystal clock frequency
AnnaBridge 172:7d866c31b3c5 126 * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 127 */
AnnaBridge 172:7d866c31b3c5 128 uint32_t CLK_GetLXTFreq(void)
AnnaBridge 172:7d866c31b3c5 129 {
AnnaBridge 172:7d866c31b3c5 130 uint32_t u32Freq;
AnnaBridge 172:7d866c31b3c5 131 if((CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk) == CLK_PWRCTL_LXTEN_Msk) {
AnnaBridge 172:7d866c31b3c5 132 u32Freq = __LXT;
AnnaBridge 172:7d866c31b3c5 133 } else {
AnnaBridge 172:7d866c31b3c5 134 u32Freq = 0UL;
AnnaBridge 172:7d866c31b3c5 135 }
AnnaBridge 172:7d866c31b3c5 136
AnnaBridge 172:7d866c31b3c5 137 return u32Freq;
AnnaBridge 172:7d866c31b3c5 138 }
AnnaBridge 172:7d866c31b3c5 139
AnnaBridge 172:7d866c31b3c5 140 /**
AnnaBridge 172:7d866c31b3c5 141 * @brief Get PCLK0 frequency
AnnaBridge 172:7d866c31b3c5 142 * @param None
AnnaBridge 172:7d866c31b3c5 143 * @return PCLK0 frequency
AnnaBridge 172:7d866c31b3c5 144 * @details This function get PCLK0 frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 145 */
AnnaBridge 172:7d866c31b3c5 146 uint32_t CLK_GetPCLK0Freq(void)
AnnaBridge 172:7d866c31b3c5 147 {
AnnaBridge 172:7d866c31b3c5 148 uint32_t u32Freq;
AnnaBridge 172:7d866c31b3c5 149 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 150
AnnaBridge 172:7d866c31b3c5 151 #if(1)
AnnaBridge 172:7d866c31b3c5 152 if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV1) {
AnnaBridge 172:7d866c31b3c5 153 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 154 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV2) {
AnnaBridge 172:7d866c31b3c5 155 u32Freq = SystemCoreClock / 2UL;
AnnaBridge 172:7d866c31b3c5 156 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV4) {
AnnaBridge 172:7d866c31b3c5 157 u32Freq = SystemCoreClock / 4UL;
AnnaBridge 172:7d866c31b3c5 158 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV8) {
AnnaBridge 172:7d866c31b3c5 159 u32Freq = SystemCoreClock / 8UL;
AnnaBridge 172:7d866c31b3c5 160 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) == CLK_PCLKDIV_PCLK0DIV16) {
AnnaBridge 172:7d866c31b3c5 161 u32Freq = SystemCoreClock / 16UL;
AnnaBridge 172:7d866c31b3c5 162 } else {
AnnaBridge 172:7d866c31b3c5 163 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 164 }
AnnaBridge 172:7d866c31b3c5 165
AnnaBridge 172:7d866c31b3c5 166
AnnaBridge 172:7d866c31b3c5 167 #else
AnnaBridge 172:7d866c31b3c5 168 if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV1) {
AnnaBridge 172:7d866c31b3c5 169 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 170 } else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK0SEL_Msk) == CLK_CLKSEL0_PCLK0DIV2) {
AnnaBridge 172:7d866c31b3c5 171 u32Freq = SystemCoreClock / 2UL;
AnnaBridge 172:7d866c31b3c5 172 } else {
AnnaBridge 172:7d866c31b3c5 173 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 174 }
AnnaBridge 172:7d866c31b3c5 175 #endif
AnnaBridge 172:7d866c31b3c5 176
AnnaBridge 172:7d866c31b3c5 177 return u32Freq;
AnnaBridge 172:7d866c31b3c5 178 }
AnnaBridge 172:7d866c31b3c5 179
AnnaBridge 172:7d866c31b3c5 180
AnnaBridge 172:7d866c31b3c5 181 /**
AnnaBridge 172:7d866c31b3c5 182 * @brief Get PCLK1 frequency
AnnaBridge 172:7d866c31b3c5 183 * @param None
AnnaBridge 172:7d866c31b3c5 184 * @return PCLK1 frequency
AnnaBridge 172:7d866c31b3c5 185 * @details This function get PCLK1 frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 186 */
AnnaBridge 172:7d866c31b3c5 187 uint32_t CLK_GetPCLK1Freq(void)
AnnaBridge 172:7d866c31b3c5 188 {
AnnaBridge 172:7d866c31b3c5 189 uint32_t u32Freq;
AnnaBridge 172:7d866c31b3c5 190 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 191
AnnaBridge 172:7d866c31b3c5 192 #if(1)
AnnaBridge 172:7d866c31b3c5 193 if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV1) {
AnnaBridge 172:7d866c31b3c5 194 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 195 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV2) {
AnnaBridge 172:7d866c31b3c5 196 u32Freq = SystemCoreClock / 2UL;
AnnaBridge 172:7d866c31b3c5 197 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV4) {
AnnaBridge 172:7d866c31b3c5 198 u32Freq = SystemCoreClock / 4UL;
AnnaBridge 172:7d866c31b3c5 199 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV8) {
AnnaBridge 172:7d866c31b3c5 200 u32Freq = SystemCoreClock / 8UL;
AnnaBridge 172:7d866c31b3c5 201 } else if((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) == CLK_PCLKDIV_PCLK1DIV16) {
AnnaBridge 172:7d866c31b3c5 202 u32Freq = SystemCoreClock / 16UL;
AnnaBridge 172:7d866c31b3c5 203 } else {
AnnaBridge 172:7d866c31b3c5 204 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 205 }
AnnaBridge 172:7d866c31b3c5 206
AnnaBridge 172:7d866c31b3c5 207
AnnaBridge 172:7d866c31b3c5 208 #else
AnnaBridge 172:7d866c31b3c5 209 if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV1) {
AnnaBridge 172:7d866c31b3c5 210 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 211 } else if((CLK->CLKSEL0 & CLK_CLKSEL0_PCLK1SEL_Msk) == CLK_CLKSEL0_PCLK1DIV2) {
AnnaBridge 172:7d866c31b3c5 212 u32Freq = SystemCoreClock / 2UL;
AnnaBridge 172:7d866c31b3c5 213 } else {
AnnaBridge 172:7d866c31b3c5 214 u32Freq = SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 215 }
AnnaBridge 172:7d866c31b3c5 216 #endif
AnnaBridge 172:7d866c31b3c5 217
AnnaBridge 172:7d866c31b3c5 218 return u32Freq;
AnnaBridge 172:7d866c31b3c5 219 }
AnnaBridge 172:7d866c31b3c5 220
AnnaBridge 172:7d866c31b3c5 221
AnnaBridge 172:7d866c31b3c5 222 /**
AnnaBridge 172:7d866c31b3c5 223 * @brief Get HCLK frequency
AnnaBridge 172:7d866c31b3c5 224 * @param None
AnnaBridge 172:7d866c31b3c5 225 * @return HCLK frequency
AnnaBridge 172:7d866c31b3c5 226 * @details This function get HCLK frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 227 */
AnnaBridge 172:7d866c31b3c5 228 uint32_t CLK_GetHCLKFreq(void)
AnnaBridge 172:7d866c31b3c5 229 {
AnnaBridge 172:7d866c31b3c5 230 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 231 return SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 232 }
AnnaBridge 172:7d866c31b3c5 233
AnnaBridge 172:7d866c31b3c5 234
AnnaBridge 172:7d866c31b3c5 235 /**
AnnaBridge 172:7d866c31b3c5 236 * @brief Get CPU frequency
AnnaBridge 172:7d866c31b3c5 237 * @param None
AnnaBridge 172:7d866c31b3c5 238 * @return CPU frequency
AnnaBridge 172:7d866c31b3c5 239 * @details This function get CPU frequency. The frequency unit is Hz.
AnnaBridge 172:7d866c31b3c5 240 */
AnnaBridge 172:7d866c31b3c5 241 uint32_t CLK_GetCPUFreq(void)
AnnaBridge 172:7d866c31b3c5 242 {
AnnaBridge 172:7d866c31b3c5 243 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 244 return SystemCoreClock;
AnnaBridge 172:7d866c31b3c5 245 }
AnnaBridge 172:7d866c31b3c5 246
AnnaBridge 172:7d866c31b3c5 247
AnnaBridge 172:7d866c31b3c5 248 /**
AnnaBridge 172:7d866c31b3c5 249 * @brief Set HCLK frequency
AnnaBridge 172:7d866c31b3c5 250 * @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is running up to 192MHz.
AnnaBridge 172:7d866c31b3c5 251 * @return HCLK frequency
AnnaBridge 172:7d866c31b3c5 252 * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n
AnnaBridge 172:7d866c31b3c5 253 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 254 */
AnnaBridge 172:7d866c31b3c5 255 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
AnnaBridge 172:7d866c31b3c5 256 {
AnnaBridge 172:7d866c31b3c5 257 uint32_t u32HIRCSTB;
AnnaBridge 172:7d866c31b3c5 258
AnnaBridge 172:7d866c31b3c5 259 /* Read HIRC clock source stable flag */
AnnaBridge 172:7d866c31b3c5 260 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
AnnaBridge 172:7d866c31b3c5 261
AnnaBridge 172:7d866c31b3c5 262 /* The range of u32Hclk is running up to 192 MHz */
AnnaBridge 172:7d866c31b3c5 263 if(u32Hclk > FREQ_192MHZ) {
AnnaBridge 172:7d866c31b3c5 264 u32Hclk = FREQ_192MHZ;
AnnaBridge 172:7d866c31b3c5 265 }
AnnaBridge 172:7d866c31b3c5 266
AnnaBridge 172:7d866c31b3c5 267 /* Switch HCLK clock source to HIRC clock for safe */
AnnaBridge 172:7d866c31b3c5 268 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 269 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 270 CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
AnnaBridge 172:7d866c31b3c5 271 CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
AnnaBridge 172:7d866c31b3c5 272
AnnaBridge 172:7d866c31b3c5 273 /* Configure PLL setting if HXT clock is enabled */
AnnaBridge 172:7d866c31b3c5 274 if((CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk) == CLK_PWRCTL_HXTEN_Msk) {
AnnaBridge 172:7d866c31b3c5 275 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk);
AnnaBridge 172:7d866c31b3c5 276 }
AnnaBridge 172:7d866c31b3c5 277 /* Configure PLL setting if HXT clock is not enabled */
AnnaBridge 172:7d866c31b3c5 278 else {
AnnaBridge 172:7d866c31b3c5 279 u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk);
AnnaBridge 172:7d866c31b3c5 280
AnnaBridge 172:7d866c31b3c5 281 /* Read HIRC clock source stable flag */
AnnaBridge 172:7d866c31b3c5 282 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
AnnaBridge 172:7d866c31b3c5 283 }
AnnaBridge 172:7d866c31b3c5 284
AnnaBridge 172:7d866c31b3c5 285 /* Select HCLK clock source to PLL,
AnnaBridge 172:7d866c31b3c5 286 and update system core clock
AnnaBridge 172:7d866c31b3c5 287 */
AnnaBridge 172:7d866c31b3c5 288 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
AnnaBridge 172:7d866c31b3c5 289
AnnaBridge 172:7d866c31b3c5 290 /* Disable HIRC if HIRC is disabled before setting core clock */
AnnaBridge 172:7d866c31b3c5 291 if(u32HIRCSTB == 0UL) {
AnnaBridge 172:7d866c31b3c5 292 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 293 }
AnnaBridge 172:7d866c31b3c5 294
AnnaBridge 172:7d866c31b3c5 295 /* Return actually HCLK frequency is PLL frequency divide 1 */
AnnaBridge 172:7d866c31b3c5 296 return u32Hclk;
AnnaBridge 172:7d866c31b3c5 297 }
AnnaBridge 172:7d866c31b3c5 298
AnnaBridge 172:7d866c31b3c5 299 /**
AnnaBridge 172:7d866c31b3c5 300 * @brief This function set HCLK clock source and HCLK clock divider
AnnaBridge 172:7d866c31b3c5 301 * @param[in] u32ClkSrc is HCLK clock source. Including :
AnnaBridge 172:7d866c31b3c5 302 * - \ref CLK_CLKSEL0_HCLKSEL_HXT
AnnaBridge 172:7d866c31b3c5 303 * - \ref CLK_CLKSEL0_HCLKSEL_LXT
AnnaBridge 172:7d866c31b3c5 304 * - \ref CLK_CLKSEL0_HCLKSEL_PLL
AnnaBridge 172:7d866c31b3c5 305 * - \ref CLK_CLKSEL0_HCLKSEL_LIRC
AnnaBridge 172:7d866c31b3c5 306 * - \ref CLK_CLKSEL0_HCLKSEL_HIRC
AnnaBridge 172:7d866c31b3c5 307 * @param[in] u32ClkDiv is HCLK clock divider. Including :
AnnaBridge 172:7d866c31b3c5 308 * - \ref CLK_CLKDIV0_HCLK(x)
AnnaBridge 172:7d866c31b3c5 309 * @return None
AnnaBridge 172:7d866c31b3c5 310 * @details This function set HCLK clock source and HCLK clock divider. \n
AnnaBridge 172:7d866c31b3c5 311 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 312 */
AnnaBridge 172:7d866c31b3c5 313 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
AnnaBridge 172:7d866c31b3c5 314 {
AnnaBridge 172:7d866c31b3c5 315 uint32_t u32HIRCSTB;
AnnaBridge 172:7d866c31b3c5 316
AnnaBridge 172:7d866c31b3c5 317 /* Read HIRC clock source stable flag */
AnnaBridge 172:7d866c31b3c5 318 u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
AnnaBridge 172:7d866c31b3c5 319
AnnaBridge 172:7d866c31b3c5 320 /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */
AnnaBridge 172:7d866c31b3c5 321 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 322 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 323 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
AnnaBridge 172:7d866c31b3c5 324
AnnaBridge 172:7d866c31b3c5 325 /* Apply new Divider */
AnnaBridge 172:7d866c31b3c5 326 CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
AnnaBridge 172:7d866c31b3c5 327
AnnaBridge 172:7d866c31b3c5 328 /* Switch HCLK to new HCLK source */
AnnaBridge 172:7d866c31b3c5 329 CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
AnnaBridge 172:7d866c31b3c5 330
AnnaBridge 172:7d866c31b3c5 331 /* Update System Core Clock */
AnnaBridge 172:7d866c31b3c5 332 SystemCoreClockUpdate();
AnnaBridge 172:7d866c31b3c5 333
AnnaBridge 172:7d866c31b3c5 334 /* Disable HIRC if HIRC is disabled before switching HCLK source */
AnnaBridge 172:7d866c31b3c5 335 if(u32HIRCSTB == 0UL) {
AnnaBridge 172:7d866c31b3c5 336 CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 337 }
AnnaBridge 172:7d866c31b3c5 338 }
AnnaBridge 172:7d866c31b3c5 339
AnnaBridge 172:7d866c31b3c5 340 /**
AnnaBridge 172:7d866c31b3c5 341 * @brief This function set selected module clock source and module clock divider
AnnaBridge 172:7d866c31b3c5 342 * @param[in] u32ModuleIdx is module index.
AnnaBridge 172:7d866c31b3c5 343 * @param[in] u32ClkSrc is module clock source.
AnnaBridge 172:7d866c31b3c5 344 * @param[in] u32ClkDiv is module clock divider.
AnnaBridge 172:7d866c31b3c5 345 * @return None
AnnaBridge 172:7d866c31b3c5 346 * @details Valid parameter combinations listed in following table:
AnnaBridge 172:7d866c31b3c5 347 *
AnnaBridge 172:7d866c31b3c5 348 * |Module index |Clock source |Divider |
AnnaBridge 172:7d866c31b3c5 349 * | :---------------- | :----------------------------------- | :-------------------------- |
AnnaBridge 172:7d866c31b3c5 350 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) |
AnnaBridge 172:7d866c31b3c5 351 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) |
AnnaBridge 172:7d866c31b3c5 352 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) |
AnnaBridge 172:7d866c31b3c5 353 * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) |
AnnaBridge 172:7d866c31b3c5 354 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HXT |\ref CLK_CLKDIV3_SDH1(x) |
AnnaBridge 172:7d866c31b3c5 355 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_PLL |\ref CLK_CLKDIV3_SDH1(x) |
AnnaBridge 172:7d866c31b3c5 356 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HIRC |\ref CLK_CLKDIV3_SDH1(x) |
AnnaBridge 172:7d866c31b3c5 357 * |\ref SDH1_MODULE |\ref CLK_CLKSEL0_SDH1SEL_HCLK |\ref CLK_CLKDIV3_SDH1(x) |
AnnaBridge 172:7d866c31b3c5 358 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 359 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 360 * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
AnnaBridge 172:7d866c31b3c5 361 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 362 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 363 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 364 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 365 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 366 * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT | x |
AnnaBridge 172:7d866c31b3c5 367 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 368 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 369 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 370 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 371 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 372 * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT | x |
AnnaBridge 172:7d866c31b3c5 373 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 374 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 375 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 376 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 377 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 378 * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT | x |
AnnaBridge 172:7d866c31b3c5 379 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 380 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 381 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 382 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 383 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 384 * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT | x |
AnnaBridge 172:7d866c31b3c5 385 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) |
AnnaBridge 172:7d866c31b3c5 386 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) |
AnnaBridge 172:7d866c31b3c5 387 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) |
AnnaBridge 172:7d866c31b3c5 388 * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) |
AnnaBridge 172:7d866c31b3c5 389 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) |
AnnaBridge 172:7d866c31b3c5 390 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) |
AnnaBridge 172:7d866c31b3c5 391 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) |
AnnaBridge 172:7d866c31b3c5 392 * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) |
AnnaBridge 172:7d866c31b3c5 393 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 394 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 395 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 396 * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x |
AnnaBridge 172:7d866c31b3c5 397 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 398 * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x |
AnnaBridge 172:7d866c31b3c5 399 * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 400 * |\ref EPWM0_MODULE |\ref CLK_CLKSEL2_EPWM0SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 401 * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 402 * |\ref EPWM1_MODULE |\ref CLK_CLKSEL2_EPWM1SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 403 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 404 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 405 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 406 * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 407 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 408 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 409 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 410 * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 411 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 412 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 413 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 414 * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 415 * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 416 * |\ref BPWM0_MODULE |\ref CLK_CLKSEL2_BPWM0SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 417 * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 418 * |\ref BPWM1_MODULE |\ref CLK_CLKSEL2_BPWM1SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 419 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 420 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 421 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 422 * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK1 | x |
AnnaBridge 172:7d866c31b3c5 423 * |\ref SPI4_MODULE |\ref CLK_CLKSEL2_SPI4SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 424 * |\ref SPI4_MODULE |\ref CLK_CLKSEL2_SPI4SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 425 * |\ref SPI4_MODULE |\ref CLK_CLKSEL2_SPI4SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 426 * |\ref SPI4_MODULE |\ref CLK_CLKSEL2_SPI4SEL_PCLK0 | x |
AnnaBridge 172:7d866c31b3c5 427 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
AnnaBridge 172:7d866c31b3c5 428 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
AnnaBridge 172:7d866c31b3c5 429 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) |
AnnaBridge 172:7d866c31b3c5 430 * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
AnnaBridge 172:7d866c31b3c5 431 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) |
AnnaBridge 172:7d866c31b3c5 432 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) |
AnnaBridge 172:7d866c31b3c5 433 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
AnnaBridge 172:7d866c31b3c5 434 * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) |
AnnaBridge 172:7d866c31b3c5 435 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
AnnaBridge 172:7d866c31b3c5 436 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
AnnaBridge 172:7d866c31b3c5 437 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
AnnaBridge 172:7d866c31b3c5 438 * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
AnnaBridge 172:7d866c31b3c5 439 * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x |
AnnaBridge 172:7d866c31b3c5 440 * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x |
AnnaBridge 172:7d866c31b3c5 441 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x |
AnnaBridge 172:7d866c31b3c5 442 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x |
AnnaBridge 172:7d866c31b3c5 443 * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x |
AnnaBridge 172:7d866c31b3c5 444 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) |
AnnaBridge 172:7d866c31b3c5 445 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) |
AnnaBridge 172:7d866c31b3c5 446 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) |
AnnaBridge 172:7d866c31b3c5 447 * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) |
AnnaBridge 172:7d866c31b3c5 448 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) |
AnnaBridge 172:7d866c31b3c5 449 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) |
AnnaBridge 172:7d866c31b3c5 450 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) |
AnnaBridge 172:7d866c31b3c5 451 * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) |
AnnaBridge 172:7d866c31b3c5 452 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) |
AnnaBridge 172:7d866c31b3c5 453 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) |
AnnaBridge 172:7d866c31b3c5 454 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) |
AnnaBridge 172:7d866c31b3c5 455 * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) |
AnnaBridge 172:7d866c31b3c5 456 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) |
AnnaBridge 172:7d866c31b3c5 457 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) |
AnnaBridge 172:7d866c31b3c5 458 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) |
AnnaBridge 172:7d866c31b3c5 459 * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) |
AnnaBridge 172:7d866c31b3c5 460 *
AnnaBridge 172:7d866c31b3c5 461 */
AnnaBridge 172:7d866c31b3c5 462 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
AnnaBridge 172:7d866c31b3c5 463 {
AnnaBridge 172:7d866c31b3c5 464 uint32_t u32sel = 0U, u32div = 0U;
AnnaBridge 172:7d866c31b3c5 465
AnnaBridge 172:7d866c31b3c5 466 if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) {
AnnaBridge 172:7d866c31b3c5 467 /* Get clock divider control register address */
AnnaBridge 172:7d866c31b3c5 468 if(MODULE_CLKDIV(u32ModuleIdx) == 2U) {
AnnaBridge 172:7d866c31b3c5 469 u32div = (uint32_t)&CLK->CLKDIV3;
AnnaBridge 172:7d866c31b3c5 470 } else if (MODULE_CLKDIV(u32ModuleIdx) == 3U) {
AnnaBridge 172:7d866c31b3c5 471 u32div = (uint32_t)&CLK->CLKDIV4;
AnnaBridge 172:7d866c31b3c5 472 } else {
AnnaBridge 172:7d866c31b3c5 473 u32div = (uint32_t)&CLK->CLKDIV0 + ((MODULE_CLKDIV(u32ModuleIdx)) * 4U);
AnnaBridge 172:7d866c31b3c5 474 }
AnnaBridge 172:7d866c31b3c5 475
AnnaBridge 172:7d866c31b3c5 476 /* Apply new divider */
AnnaBridge 172:7d866c31b3c5 477 M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
AnnaBridge 172:7d866c31b3c5 478 }
AnnaBridge 172:7d866c31b3c5 479
AnnaBridge 172:7d866c31b3c5 480 if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) {
AnnaBridge 172:7d866c31b3c5 481 /* Get clock select control register address */
AnnaBridge 172:7d866c31b3c5 482 u32sel = (uint32_t)&CLK->CLKSEL0 + ((MODULE_CLKSEL(u32ModuleIdx)) * 4U);
AnnaBridge 172:7d866c31b3c5 483 /* Set new clock selection setting */
AnnaBridge 172:7d866c31b3c5 484 M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
AnnaBridge 172:7d866c31b3c5 485 }
AnnaBridge 172:7d866c31b3c5 486 }
AnnaBridge 172:7d866c31b3c5 487
AnnaBridge 172:7d866c31b3c5 488 /**
AnnaBridge 172:7d866c31b3c5 489 * @brief Set SysTick clock source
AnnaBridge 172:7d866c31b3c5 490 * @param[in] u32ClkSrc is module clock source. Including:
AnnaBridge 172:7d866c31b3c5 491 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
AnnaBridge 172:7d866c31b3c5 492 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
AnnaBridge 172:7d866c31b3c5 493 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
AnnaBridge 172:7d866c31b3c5 494 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
AnnaBridge 172:7d866c31b3c5 495 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
AnnaBridge 172:7d866c31b3c5 496 * @return None
AnnaBridge 172:7d866c31b3c5 497 * @details This function set SysTick clock source. \n
AnnaBridge 172:7d866c31b3c5 498 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 499 */
AnnaBridge 172:7d866c31b3c5 500 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
AnnaBridge 172:7d866c31b3c5 501 {
AnnaBridge 172:7d866c31b3c5 502 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
AnnaBridge 172:7d866c31b3c5 503
AnnaBridge 172:7d866c31b3c5 504 }
AnnaBridge 172:7d866c31b3c5 505
AnnaBridge 172:7d866c31b3c5 506 /**
AnnaBridge 172:7d866c31b3c5 507 * @brief Enable clock source
AnnaBridge 172:7d866c31b3c5 508 * @param[in] u32ClkMask is clock source mask. Including :
AnnaBridge 172:7d866c31b3c5 509 * - \ref CLK_PWRCTL_HXTEN_Msk
AnnaBridge 172:7d866c31b3c5 510 * - \ref CLK_PWRCTL_LXTEN_Msk
AnnaBridge 172:7d866c31b3c5 511 * - \ref CLK_PWRCTL_HIRCEN_Msk
AnnaBridge 172:7d866c31b3c5 512 * - \ref CLK_PWRCTL_LIRCEN_Msk
AnnaBridge 172:7d866c31b3c5 513 * @return None
AnnaBridge 172:7d866c31b3c5 514 * @details This function enable clock source. \n
AnnaBridge 172:7d866c31b3c5 515 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 516 */
AnnaBridge 172:7d866c31b3c5 517 void CLK_EnableXtalRC(uint32_t u32ClkMask)
AnnaBridge 172:7d866c31b3c5 518 {
AnnaBridge 172:7d866c31b3c5 519 CLK->PWRCTL |= u32ClkMask;
AnnaBridge 172:7d866c31b3c5 520 }
AnnaBridge 172:7d866c31b3c5 521
AnnaBridge 172:7d866c31b3c5 522 /**
AnnaBridge 172:7d866c31b3c5 523 * @brief Disable clock source
AnnaBridge 172:7d866c31b3c5 524 * @param[in] u32ClkMask is clock source mask. Including :
AnnaBridge 172:7d866c31b3c5 525 * - \ref CLK_PWRCTL_HXTEN_Msk
AnnaBridge 172:7d866c31b3c5 526 * - \ref CLK_PWRCTL_LXTEN_Msk
AnnaBridge 172:7d866c31b3c5 527 * - \ref CLK_PWRCTL_HIRCEN_Msk
AnnaBridge 172:7d866c31b3c5 528 * - \ref CLK_PWRCTL_LIRCEN_Msk
AnnaBridge 172:7d866c31b3c5 529 * @return None
AnnaBridge 172:7d866c31b3c5 530 * @details This function disable clock source. \n
AnnaBridge 172:7d866c31b3c5 531 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 532 */
AnnaBridge 172:7d866c31b3c5 533 void CLK_DisableXtalRC(uint32_t u32ClkMask)
AnnaBridge 172:7d866c31b3c5 534 {
AnnaBridge 172:7d866c31b3c5 535 CLK->PWRCTL &= ~u32ClkMask;
AnnaBridge 172:7d866c31b3c5 536 }
AnnaBridge 172:7d866c31b3c5 537
AnnaBridge 172:7d866c31b3c5 538 /**
AnnaBridge 172:7d866c31b3c5 539 * @brief Enable module clock
AnnaBridge 172:7d866c31b3c5 540 * @param[in] u32ModuleIdx is module index. Including :
AnnaBridge 172:7d866c31b3c5 541 * - \ref PDMA_MODULE
AnnaBridge 172:7d866c31b3c5 542 * - \ref ISP_MODULE
AnnaBridge 172:7d866c31b3c5 543 * - \ref EBI_MODULE
AnnaBridge 172:7d866c31b3c5 544 * - \ref EMAC_MODULE
AnnaBridge 172:7d866c31b3c5 545 * - \ref SDH0_MODULE
AnnaBridge 172:7d866c31b3c5 546 * - \ref CRC_MODULE
AnnaBridge 172:7d866c31b3c5 547 * - \ref HSUSBD_MODULE
AnnaBridge 172:7d866c31b3c5 548 * - \ref CRPT_MODULE
AnnaBridge 172:7d866c31b3c5 549 * - \ref SPIM_MODULE
AnnaBridge 172:7d866c31b3c5 550 * - \ref USBH_MODULE
AnnaBridge 172:7d866c31b3c5 551 * - \ref SDH1_MODULE
AnnaBridge 172:7d866c31b3c5 552 * - \ref WDT_MODULE
AnnaBridge 172:7d866c31b3c5 553 * - \ref RTC_MODULE
AnnaBridge 172:7d866c31b3c5 554 * - \ref TMR0_MODULE
AnnaBridge 172:7d866c31b3c5 555 * - \ref TMR1_MODULE
AnnaBridge 172:7d866c31b3c5 556 * - \ref TMR2_MODULE
AnnaBridge 172:7d866c31b3c5 557 * - \ref TMR3_MODULE
AnnaBridge 172:7d866c31b3c5 558 * - \ref CLKO_MODULE
AnnaBridge 172:7d866c31b3c5 559 * - \ref WWDT_MODULE
AnnaBridge 172:7d866c31b3c5 560 * - \ref ACMP01_MODULE
AnnaBridge 172:7d866c31b3c5 561 * - \ref I2C0_MODULE
AnnaBridge 172:7d866c31b3c5 562 * - \ref I2C1_MODULE
AnnaBridge 172:7d866c31b3c5 563 * - \ref I2C2_MODULE
AnnaBridge 172:7d866c31b3c5 564 * - \ref SPI0_MODULE
AnnaBridge 172:7d866c31b3c5 565 * - \ref SPI1_MODULE
AnnaBridge 172:7d866c31b3c5 566 * - \ref SPI2_MODULE
AnnaBridge 172:7d866c31b3c5 567 * - \ref SPI3_MODULE
AnnaBridge 172:7d866c31b3c5 568 * - \ref UART0_MODULE
AnnaBridge 172:7d866c31b3c5 569 * - \ref UART1_MODULE
AnnaBridge 172:7d866c31b3c5 570 * - \ref UART2_MODULE
AnnaBridge 172:7d866c31b3c5 571 * - \ref UART3_MODULE
AnnaBridge 172:7d866c31b3c5 572 * - \ref UART4_MODULE
AnnaBridge 172:7d866c31b3c5 573 * - \ref UART5_MODULE
AnnaBridge 172:7d866c31b3c5 574 * - \ref CAN0_MODULE
AnnaBridge 172:7d866c31b3c5 575 * - \ref CAN1_MODULE
AnnaBridge 172:7d866c31b3c5 576 * - \ref OTG_MODULE
AnnaBridge 172:7d866c31b3c5 577 * - \ref USBD_MODULE
AnnaBridge 172:7d866c31b3c5 578 * - \ref EADC_MODULE
AnnaBridge 172:7d866c31b3c5 579 * - \ref I2S0_MODULE
AnnaBridge 172:7d866c31b3c5 580 * - \ref HSOTG_MODULE
AnnaBridge 172:7d866c31b3c5 581 * - \ref SC0_MODULE
AnnaBridge 172:7d866c31b3c5 582 * - \ref SC1_MODULE
AnnaBridge 172:7d866c31b3c5 583 * - \ref SC2_MODULE
AnnaBridge 172:7d866c31b3c5 584 * - \ref SPI4_MODULE
AnnaBridge 172:7d866c31b3c5 585 * - \ref USCI0_MODULE
AnnaBridge 172:7d866c31b3c5 586 * - \ref USCI1_MODULE
AnnaBridge 172:7d866c31b3c5 587 * - \ref DAC_MODULE
AnnaBridge 172:7d866c31b3c5 588 * - \ref EPWM0_MODULE
AnnaBridge 172:7d866c31b3c5 589 * - \ref EPWM1_MODULE
AnnaBridge 172:7d866c31b3c5 590 * - \ref BPWM0_MODULE
AnnaBridge 172:7d866c31b3c5 591 * - \ref BPWM1_MODULE
AnnaBridge 172:7d866c31b3c5 592 * - \ref QEI0_MODULE
AnnaBridge 172:7d866c31b3c5 593 * - \ref QEI1_MODULE
AnnaBridge 172:7d866c31b3c5 594 * - \ref ECAP0_MODULE
AnnaBridge 172:7d866c31b3c5 595 * - \ref ECAP1_MODULE
AnnaBridge 172:7d866c31b3c5 596 * - \ref OPA_MODULE
AnnaBridge 172:7d866c31b3c5 597 * @return None
AnnaBridge 172:7d866c31b3c5 598 * @details This function is used to enable module clock.
AnnaBridge 172:7d866c31b3c5 599 */
AnnaBridge 172:7d866c31b3c5 600 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
AnnaBridge 172:7d866c31b3c5 601 {
AnnaBridge 172:7d866c31b3c5 602 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
AnnaBridge 172:7d866c31b3c5 603
AnnaBridge 172:7d866c31b3c5 604 u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
AnnaBridge 172:7d866c31b3c5 605 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
AnnaBridge 172:7d866c31b3c5 606 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
AnnaBridge 172:7d866c31b3c5 607
AnnaBridge 172:7d866c31b3c5 608 *(volatile uint32_t *)u32tmpAddr |= u32tmpVal;
AnnaBridge 172:7d866c31b3c5 609 }
AnnaBridge 172:7d866c31b3c5 610
AnnaBridge 172:7d866c31b3c5 611 /**
AnnaBridge 172:7d866c31b3c5 612 * @brief Disable module clock
AnnaBridge 172:7d866c31b3c5 613 * @param[in] u32ModuleIdx is module index. Including :
AnnaBridge 172:7d866c31b3c5 614 * - \ref PDMA_MODULE
AnnaBridge 172:7d866c31b3c5 615 * - \ref ISP_MODULE
AnnaBridge 172:7d866c31b3c5 616 * - \ref EBI_MODULE
AnnaBridge 172:7d866c31b3c5 617 * - \ref EMAC_MODULE
AnnaBridge 172:7d866c31b3c5 618 * - \ref SDH0_MODULE
AnnaBridge 172:7d866c31b3c5 619 * - \ref CRC_MODULE
AnnaBridge 172:7d866c31b3c5 620 * - \ref HSUSBD_MODULE
AnnaBridge 172:7d866c31b3c5 621 * - \ref CRPT_MODULE
AnnaBridge 172:7d866c31b3c5 622 * - \ref SPIM_MODULE
AnnaBridge 172:7d866c31b3c5 623 * - \ref USBH_MODULE
AnnaBridge 172:7d866c31b3c5 624 * - \ref SDH1_MODULE
AnnaBridge 172:7d866c31b3c5 625 * - \ref WDT_MODULE
AnnaBridge 172:7d866c31b3c5 626 * - \ref RTC_MODULE
AnnaBridge 172:7d866c31b3c5 627 * - \ref TMR0_MODULE
AnnaBridge 172:7d866c31b3c5 628 * - \ref TMR1_MODULE
AnnaBridge 172:7d866c31b3c5 629 * - \ref TMR2_MODULE
AnnaBridge 172:7d866c31b3c5 630 * - \ref TMR3_MODULE
AnnaBridge 172:7d866c31b3c5 631 * - \ref CLKO_MODULE
AnnaBridge 172:7d866c31b3c5 632 * - \ref WWDT_MODULE
AnnaBridge 172:7d866c31b3c5 633 * - \ref ACMP01_MODULE
AnnaBridge 172:7d866c31b3c5 634 * - \ref I2C0_MODULE
AnnaBridge 172:7d866c31b3c5 635 * - \ref I2C1_MODULE
AnnaBridge 172:7d866c31b3c5 636 * - \ref I2C2_MODULE
AnnaBridge 172:7d866c31b3c5 637 * - \ref SPI0_MODULE
AnnaBridge 172:7d866c31b3c5 638 * - \ref SPI1_MODULE
AnnaBridge 172:7d866c31b3c5 639 * - \ref SPI2_MODULE
AnnaBridge 172:7d866c31b3c5 640 * - \ref SPI3_MODULE
AnnaBridge 172:7d866c31b3c5 641 * - \ref UART0_MODULE
AnnaBridge 172:7d866c31b3c5 642 * - \ref UART1_MODULE
AnnaBridge 172:7d866c31b3c5 643 * - \ref UART2_MODULE
AnnaBridge 172:7d866c31b3c5 644 * - \ref UART3_MODULE
AnnaBridge 172:7d866c31b3c5 645 * - \ref UART4_MODULE
AnnaBridge 172:7d866c31b3c5 646 * - \ref UART5_MODULE
AnnaBridge 172:7d866c31b3c5 647 * - \ref CAN0_MODULE
AnnaBridge 172:7d866c31b3c5 648 * - \ref CAN1_MODULE
AnnaBridge 172:7d866c31b3c5 649 * - \ref OTG_MODULE
AnnaBridge 172:7d866c31b3c5 650 * - \ref USBD_MODULE
AnnaBridge 172:7d866c31b3c5 651 * - \ref EADC_MODULE
AnnaBridge 172:7d866c31b3c5 652 * - \ref I2S0_MODULE
AnnaBridge 172:7d866c31b3c5 653 * - \ref HSOTG_MODULE
AnnaBridge 172:7d866c31b3c5 654 * - \ref SC0_MODULE
AnnaBridge 172:7d866c31b3c5 655 * - \ref SC1_MODULE
AnnaBridge 172:7d866c31b3c5 656 * - \ref SC2_MODULE
AnnaBridge 172:7d866c31b3c5 657 * - \ref SPI4_MODULE
AnnaBridge 172:7d866c31b3c5 658 * - \ref USCI0_MODULE
AnnaBridge 172:7d866c31b3c5 659 * - \ref USCI1_MODULE
AnnaBridge 172:7d866c31b3c5 660 * - \ref DAC_MODULE
AnnaBridge 172:7d866c31b3c5 661 * - \ref EPWM0_MODULE
AnnaBridge 172:7d866c31b3c5 662 * - \ref EPWM1_MODULE
AnnaBridge 172:7d866c31b3c5 663 * - \ref BPWM0_MODULE
AnnaBridge 172:7d866c31b3c5 664 * - \ref BPWM1_MODULE
AnnaBridge 172:7d866c31b3c5 665 * - \ref QEI0_MODULE
AnnaBridge 172:7d866c31b3c5 666 * - \ref QEI1_MODULE
AnnaBridge 172:7d866c31b3c5 667 * - \ref ECAP0_MODULE
AnnaBridge 172:7d866c31b3c5 668 * - \ref ECAP1_MODULE
AnnaBridge 172:7d866c31b3c5 669 * - \ref OPA_MODULE
AnnaBridge 172:7d866c31b3c5 670 * @return None
AnnaBridge 172:7d866c31b3c5 671 * @details This function is used to disable module clock.
AnnaBridge 172:7d866c31b3c5 672 */
AnnaBridge 172:7d866c31b3c5 673 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
AnnaBridge 172:7d866c31b3c5 674 {
AnnaBridge 172:7d866c31b3c5 675 uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL;
AnnaBridge 172:7d866c31b3c5 676
AnnaBridge 172:7d866c31b3c5 677 u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
AnnaBridge 172:7d866c31b3c5 678 u32tmpAddr = (uint32_t)&CLK->AHBCLK;
AnnaBridge 172:7d866c31b3c5 679 u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
AnnaBridge 172:7d866c31b3c5 680
AnnaBridge 172:7d866c31b3c5 681 *(uint32_t *)u32tmpAddr &= u32tmpVal;
AnnaBridge 172:7d866c31b3c5 682 }
AnnaBridge 172:7d866c31b3c5 683
AnnaBridge 172:7d866c31b3c5 684
AnnaBridge 172:7d866c31b3c5 685 /**
AnnaBridge 172:7d866c31b3c5 686 * @brief Set PLL frequency
AnnaBridge 172:7d866c31b3c5 687 * @param[in] u32PllClkSrc is PLL clock source. Including :
AnnaBridge 172:7d866c31b3c5 688 * - \ref CLK_PLLCTL_PLLSRC_HXT
AnnaBridge 172:7d866c31b3c5 689 * - \ref CLK_PLLCTL_PLLSRC_HIRC
AnnaBridge 172:7d866c31b3c5 690 * @param[in] u32PllFreq is PLL frequency.
AnnaBridge 172:7d866c31b3c5 691 * @return PLL frequency
AnnaBridge 172:7d866c31b3c5 692 * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n
AnnaBridge 172:7d866c31b3c5 693 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 694 */
AnnaBridge 172:7d866c31b3c5 695 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
AnnaBridge 172:7d866c31b3c5 696 {
AnnaBridge 172:7d866c31b3c5 697 uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC, u32PllClk;
AnnaBridge 172:7d866c31b3c5 698 uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR, u32MinNO, u32basFreq;
AnnaBridge 172:7d866c31b3c5 699
AnnaBridge 172:7d866c31b3c5 700 /* Disable PLL first to avoid unstable when setting PLL */
AnnaBridge 172:7d866c31b3c5 701 CLK_DisablePLL();
AnnaBridge 172:7d866c31b3c5 702
AnnaBridge 172:7d866c31b3c5 703 /* PLL source clock is from HXT */
AnnaBridge 172:7d866c31b3c5 704 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
AnnaBridge 172:7d866c31b3c5 705 /* Enable HXT clock */
AnnaBridge 172:7d866c31b3c5 706 CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk;
AnnaBridge 172:7d866c31b3c5 707
AnnaBridge 172:7d866c31b3c5 708 /* Wait for HXT clock ready */
AnnaBridge 172:7d866c31b3c5 709 CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
AnnaBridge 172:7d866c31b3c5 710
AnnaBridge 172:7d866c31b3c5 711 /* Select PLL source clock from HXT */
AnnaBridge 172:7d866c31b3c5 712 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
AnnaBridge 172:7d866c31b3c5 713 u32PllSrcClk = __HXT;
AnnaBridge 172:7d866c31b3c5 714
AnnaBridge 172:7d866c31b3c5 715 /* u32NR start from 2 */
AnnaBridge 172:7d866c31b3c5 716 u32NR = 2UL;
AnnaBridge 172:7d866c31b3c5 717 }
AnnaBridge 172:7d866c31b3c5 718
AnnaBridge 172:7d866c31b3c5 719 /* PLL source clock is from HIRC */
AnnaBridge 172:7d866c31b3c5 720 else {
AnnaBridge 172:7d866c31b3c5 721 /* Enable HIRC clock */
AnnaBridge 172:7d866c31b3c5 722 CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 723
AnnaBridge 172:7d866c31b3c5 724 /* Wait for HIRC clock ready */
AnnaBridge 172:7d866c31b3c5 725 CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 726
AnnaBridge 172:7d866c31b3c5 727 /* Select PLL source clock from HIRC */
AnnaBridge 172:7d866c31b3c5 728 u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
AnnaBridge 172:7d866c31b3c5 729 u32PllSrcClk = __HIRC;
AnnaBridge 172:7d866c31b3c5 730
AnnaBridge 172:7d866c31b3c5 731 /* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
AnnaBridge 172:7d866c31b3c5 732 u32NR = 4UL;
AnnaBridge 172:7d866c31b3c5 733 }
AnnaBridge 172:7d866c31b3c5 734
AnnaBridge 172:7d866c31b3c5 735 if((u32PllFreq <= FREQ_500MHZ) && (u32PllFreq >= FREQ_50MHZ)) {
AnnaBridge 172:7d866c31b3c5 736
AnnaBridge 172:7d866c31b3c5 737 /* Find best solution */
AnnaBridge 172:7d866c31b3c5 738 u32Min = (uint32_t) - 1;
AnnaBridge 172:7d866c31b3c5 739 u32MinNR = 0UL;
AnnaBridge 172:7d866c31b3c5 740 u32MinNF = 0UL;
AnnaBridge 172:7d866c31b3c5 741 u32MinNO = 0UL;
AnnaBridge 172:7d866c31b3c5 742 u32basFreq = u32PllFreq;
AnnaBridge 172:7d866c31b3c5 743
AnnaBridge 172:7d866c31b3c5 744 for(u32NO = 1UL; u32NO <= 4UL; u32NO++) {
AnnaBridge 172:7d866c31b3c5 745 /* Break when get good results */
AnnaBridge 172:7d866c31b3c5 746 if (u32Min == 0UL) {
AnnaBridge 172:7d866c31b3c5 747 break;
AnnaBridge 172:7d866c31b3c5 748 }
AnnaBridge 172:7d866c31b3c5 749
AnnaBridge 172:7d866c31b3c5 750 if (u32NO != 3UL) {
AnnaBridge 172:7d866c31b3c5 751
AnnaBridge 172:7d866c31b3c5 752 if(u32NO == 4UL) {
AnnaBridge 172:7d866c31b3c5 753 u32PllFreq = u32basFreq << 2;
AnnaBridge 172:7d866c31b3c5 754 } else if(u32NO == 2UL) {
AnnaBridge 172:7d866c31b3c5 755 u32PllFreq = u32basFreq << 1;
AnnaBridge 172:7d866c31b3c5 756 } else {
AnnaBridge 172:7d866c31b3c5 757 }
AnnaBridge 172:7d866c31b3c5 758
AnnaBridge 172:7d866c31b3c5 759 for(u32NR = 2UL; u32NR <= 32UL; u32NR++) {
AnnaBridge 172:7d866c31b3c5 760 /* Break when get good results */
AnnaBridge 172:7d866c31b3c5 761 if (u32Min == 0UL) {
AnnaBridge 172:7d866c31b3c5 762 break;
AnnaBridge 172:7d866c31b3c5 763 }
AnnaBridge 172:7d866c31b3c5 764
AnnaBridge 172:7d866c31b3c5 765 u32Tmp = u32PllSrcClk / u32NR;
AnnaBridge 172:7d866c31b3c5 766 if((u32Tmp >= 4000000UL) && (u32Tmp <= 8000000UL)) {
AnnaBridge 172:7d866c31b3c5 767 for(u32NF = 2UL; u32NF <= 513UL; u32NF++) {
AnnaBridge 172:7d866c31b3c5 768 /* u32Tmp2 is shifted 2 bits to avoid overflow */
AnnaBridge 172:7d866c31b3c5 769 u32Tmp2 = (((u32Tmp * 2UL) >> 2) * u32NF);
AnnaBridge 172:7d866c31b3c5 770
AnnaBridge 172:7d866c31b3c5 771 if((u32Tmp2 >= FREQ_50MHZ) && (u32Tmp2 <= FREQ_125MHZ)) {
AnnaBridge 172:7d866c31b3c5 772 u32Tmp3 = (u32Tmp2 > (u32PllFreq>>2)) ? u32Tmp2 - (u32PllFreq>>2) : (u32PllFreq>>2) - u32Tmp2;
AnnaBridge 172:7d866c31b3c5 773 if(u32Tmp3 < u32Min) {
AnnaBridge 172:7d866c31b3c5 774 u32Min = u32Tmp3;
AnnaBridge 172:7d866c31b3c5 775 u32MinNR = u32NR;
AnnaBridge 172:7d866c31b3c5 776 u32MinNF = u32NF;
AnnaBridge 172:7d866c31b3c5 777 u32MinNO = u32NO;
AnnaBridge 172:7d866c31b3c5 778
AnnaBridge 172:7d866c31b3c5 779 /* Break when get good results */
AnnaBridge 172:7d866c31b3c5 780 if(u32Min == 0UL) {
AnnaBridge 172:7d866c31b3c5 781 break;
AnnaBridge 172:7d866c31b3c5 782 }
AnnaBridge 172:7d866c31b3c5 783 }
AnnaBridge 172:7d866c31b3c5 784 }
AnnaBridge 172:7d866c31b3c5 785 }
AnnaBridge 172:7d866c31b3c5 786 }
AnnaBridge 172:7d866c31b3c5 787 }
AnnaBridge 172:7d866c31b3c5 788 }
AnnaBridge 172:7d866c31b3c5 789 }
AnnaBridge 172:7d866c31b3c5 790
AnnaBridge 172:7d866c31b3c5 791 /* Enable and apply new PLL setting. */
AnnaBridge 172:7d866c31b3c5 792 CLK->PLLCTL = u32CLK_SRC | ((u32MinNO - 1UL) << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL);
AnnaBridge 172:7d866c31b3c5 793
AnnaBridge 172:7d866c31b3c5 794 /* Wait for PLL clock stable */
AnnaBridge 172:7d866c31b3c5 795 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
AnnaBridge 172:7d866c31b3c5 796
AnnaBridge 172:7d866c31b3c5 797 /* Actual PLL output clock frequency */
AnnaBridge 172:7d866c31b3c5 798 u32PllClk = u32PllSrcClk / (u32MinNO * (u32MinNR)) * (u32MinNF) * 2UL;
AnnaBridge 172:7d866c31b3c5 799 } else {
AnnaBridge 172:7d866c31b3c5 800 /* Wrong frequency request. Just return default setting. */
AnnaBridge 172:7d866c31b3c5 801 /* Apply default PLL setting and return */
AnnaBridge 172:7d866c31b3c5 802 if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
AnnaBridge 172:7d866c31b3c5 803 CLK->PLLCTL = CLK_PLLCTL_192MHz_HXT;
AnnaBridge 172:7d866c31b3c5 804 } else {
AnnaBridge 172:7d866c31b3c5 805 CLK->PLLCTL = CLK_PLLCTL_192MHz_HIRC;
AnnaBridge 172:7d866c31b3c5 806 }
AnnaBridge 172:7d866c31b3c5 807
AnnaBridge 172:7d866c31b3c5 808 /* Wait for PLL clock stable */
AnnaBridge 172:7d866c31b3c5 809 CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
AnnaBridge 172:7d866c31b3c5 810
AnnaBridge 172:7d866c31b3c5 811 /* Actual PLL output clock frequency */
AnnaBridge 172:7d866c31b3c5 812 u32PllClk = CLK_GetPLLClockFreq();
AnnaBridge 172:7d866c31b3c5 813 }
AnnaBridge 172:7d866c31b3c5 814
AnnaBridge 172:7d866c31b3c5 815 return u32PllClk;
AnnaBridge 172:7d866c31b3c5 816 }
AnnaBridge 172:7d866c31b3c5 817
AnnaBridge 172:7d866c31b3c5 818 /**
AnnaBridge 172:7d866c31b3c5 819 * @brief Disable PLL
AnnaBridge 172:7d866c31b3c5 820 * @param None
AnnaBridge 172:7d866c31b3c5 821 * @return None
AnnaBridge 172:7d866c31b3c5 822 * @details This function set PLL in Power-down mode. \n
AnnaBridge 172:7d866c31b3c5 823 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 824 */
AnnaBridge 172:7d866c31b3c5 825 void CLK_DisablePLL(void)
AnnaBridge 172:7d866c31b3c5 826 {
AnnaBridge 172:7d866c31b3c5 827 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
AnnaBridge 172:7d866c31b3c5 828 }
AnnaBridge 172:7d866c31b3c5 829
AnnaBridge 172:7d866c31b3c5 830
AnnaBridge 172:7d866c31b3c5 831 /**
AnnaBridge 172:7d866c31b3c5 832 * @brief This function check selected clock source status
AnnaBridge 172:7d866c31b3c5 833 * @param[in] u32ClkMask is selected clock source. Including :
AnnaBridge 172:7d866c31b3c5 834 * - \ref CLK_STATUS_HXTSTB_Msk
AnnaBridge 172:7d866c31b3c5 835 * - \ref CLK_STATUS_LXTSTB_Msk
AnnaBridge 172:7d866c31b3c5 836 * - \ref CLK_STATUS_HIRCSTB_Msk
AnnaBridge 172:7d866c31b3c5 837 * - \ref CLK_STATUS_LIRCSTB_Msk
AnnaBridge 172:7d866c31b3c5 838 * - \ref CLK_STATUS_PLLSTB_Msk
AnnaBridge 172:7d866c31b3c5 839 * @retval 0 clock is not stable
AnnaBridge 172:7d866c31b3c5 840 * @retval 1 clock is stable
AnnaBridge 172:7d866c31b3c5 841 * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms)
AnnaBridge 172:7d866c31b3c5 842 */
AnnaBridge 172:7d866c31b3c5 843 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
AnnaBridge 172:7d866c31b3c5 844 {
AnnaBridge 172:7d866c31b3c5 845 int32_t i32TimeOutCnt = 2160000;
AnnaBridge 172:7d866c31b3c5 846 uint32_t u32Ret = 1U;
AnnaBridge 172:7d866c31b3c5 847
AnnaBridge 172:7d866c31b3c5 848 while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
AnnaBridge 172:7d866c31b3c5 849 if(i32TimeOutCnt-- <= 0) {
AnnaBridge 172:7d866c31b3c5 850 u32Ret = 0U;
AnnaBridge 172:7d866c31b3c5 851 break;
AnnaBridge 172:7d866c31b3c5 852 }
AnnaBridge 172:7d866c31b3c5 853 }
AnnaBridge 172:7d866c31b3c5 854 return u32Ret;
AnnaBridge 172:7d866c31b3c5 855 }
AnnaBridge 172:7d866c31b3c5 856
AnnaBridge 172:7d866c31b3c5 857 /**
AnnaBridge 172:7d866c31b3c5 858 * @brief Enable System Tick counter
AnnaBridge 172:7d866c31b3c5 859 * @param[in] u32ClkSrc is System Tick clock source. Including:
AnnaBridge 172:7d866c31b3c5 860 * - \ref CLK_CLKSEL0_STCLKSEL_HXT
AnnaBridge 172:7d866c31b3c5 861 * - \ref CLK_CLKSEL0_STCLKSEL_LXT
AnnaBridge 172:7d866c31b3c5 862 * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2
AnnaBridge 172:7d866c31b3c5 863 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
AnnaBridge 172:7d866c31b3c5 864 * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
AnnaBridge 172:7d866c31b3c5 865 * - \ref CLK_CLKSEL0_STCLKSEL_HCLK
AnnaBridge 172:7d866c31b3c5 866 * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF.
AnnaBridge 172:7d866c31b3c5 867 * @return None
AnnaBridge 172:7d866c31b3c5 868 * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n
AnnaBridge 172:7d866c31b3c5 869 * The register write-protection function should be disabled before using this function.
AnnaBridge 172:7d866c31b3c5 870 */
AnnaBridge 172:7d866c31b3c5 871 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
AnnaBridge 172:7d866c31b3c5 872 {
AnnaBridge 172:7d866c31b3c5 873 /* Set System Tick counter disabled */
AnnaBridge 172:7d866c31b3c5 874 SysTick->CTRL = 0UL;
AnnaBridge 172:7d866c31b3c5 875
AnnaBridge 172:7d866c31b3c5 876 /* Set System Tick clock source */
AnnaBridge 172:7d866c31b3c5 877 if( u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK ) {
AnnaBridge 172:7d866c31b3c5 878 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
AnnaBridge 172:7d866c31b3c5 879 } else {
AnnaBridge 172:7d866c31b3c5 880 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
AnnaBridge 172:7d866c31b3c5 881 }
AnnaBridge 172:7d866c31b3c5 882
AnnaBridge 172:7d866c31b3c5 883 /* Set System Tick reload value */
AnnaBridge 172:7d866c31b3c5 884 SysTick->LOAD = u32Count;
AnnaBridge 172:7d866c31b3c5 885
AnnaBridge 172:7d866c31b3c5 886 /* Clear System Tick current value and counter flag */
AnnaBridge 172:7d866c31b3c5 887 SysTick->VAL = 0UL;
AnnaBridge 172:7d866c31b3c5 888
AnnaBridge 172:7d866c31b3c5 889 /* Set System Tick interrupt enabled and counter enabled */
AnnaBridge 172:7d866c31b3c5 890 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk;
AnnaBridge 172:7d866c31b3c5 891 }
AnnaBridge 172:7d866c31b3c5 892
AnnaBridge 172:7d866c31b3c5 893 /**
AnnaBridge 172:7d866c31b3c5 894 * @brief Disable System Tick counter
AnnaBridge 172:7d866c31b3c5 895 * @param None
AnnaBridge 172:7d866c31b3c5 896 * @return None
AnnaBridge 172:7d866c31b3c5 897 * @details This function disable System Tick counter.
AnnaBridge 172:7d866c31b3c5 898 */
AnnaBridge 172:7d866c31b3c5 899 void CLK_DisableSysTick(void)
AnnaBridge 172:7d866c31b3c5 900 {
AnnaBridge 172:7d866c31b3c5 901 /* Set System Tick counter disabled */
AnnaBridge 172:7d866c31b3c5 902 SysTick->CTRL = 0UL;
AnnaBridge 172:7d866c31b3c5 903 }
AnnaBridge 172:7d866c31b3c5 904
AnnaBridge 172:7d866c31b3c5 905
AnnaBridge 172:7d866c31b3c5 906 /**
AnnaBridge 172:7d866c31b3c5 907 * @brief Power-down mode selected
AnnaBridge 172:7d866c31b3c5 908 * @param[in] u32PDMode is power down mode index. Including :
AnnaBridge 172:7d866c31b3c5 909 * - \ref CLK_PMUCTL_PDMSEL_PD
AnnaBridge 172:7d866c31b3c5 910 * - \ref CLK_PMUCTL_PDMSEL_LLPD
AnnaBridge 172:7d866c31b3c5 911 * - \ref CLK_PMUCTL_PDMSEL_FWPD
AnnaBridge 172:7d866c31b3c5 912 * - \ref CLK_PMUCTL_PDMSEL_SPD0
AnnaBridge 172:7d866c31b3c5 913 * - \ref CLK_PMUCTL_PDMSEL_SPD1
AnnaBridge 172:7d866c31b3c5 914 * - \ref CLK_PMUCTL_PDMSEL_DPD
AnnaBridge 172:7d866c31b3c5 915 * @return None
AnnaBridge 172:7d866c31b3c5 916 * @details This function is used to set power-down mode.
AnnaBridge 172:7d866c31b3c5 917 * @note Must enable LIRC clock before entering to Standby Power-down Mode
AnnaBridge 172:7d866c31b3c5 918 */
AnnaBridge 172:7d866c31b3c5 919
AnnaBridge 172:7d866c31b3c5 920 void CLK_SetPowerDownMode(uint32_t u32PDMode)
AnnaBridge 172:7d866c31b3c5 921 {
AnnaBridge 172:7d866c31b3c5 922 /* Enable LIRC clock before entering to Standby Power-down Mode */
AnnaBridge 172:7d866c31b3c5 923 if((u32PDMode == CLK_PMUCTL_PDMSEL_SPD0) || (u32PDMode == CLK_PMUCTL_PDMSEL_SPD1)) {
AnnaBridge 172:7d866c31b3c5 924 /* Enable LIRC clock */
AnnaBridge 172:7d866c31b3c5 925 CLK->PWRCTL |= CLK_PWRCTL_LIRCEN_Msk;
AnnaBridge 172:7d866c31b3c5 926
AnnaBridge 172:7d866c31b3c5 927 /* Wait for LIRC clock stable */
AnnaBridge 172:7d866c31b3c5 928 CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
AnnaBridge 172:7d866c31b3c5 929 }
AnnaBridge 172:7d866c31b3c5 930
AnnaBridge 172:7d866c31b3c5 931 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_PDMSEL_Msk)) | u32PDMode;
AnnaBridge 172:7d866c31b3c5 932 }
AnnaBridge 172:7d866c31b3c5 933
AnnaBridge 172:7d866c31b3c5 934 /**
AnnaBridge 172:7d866c31b3c5 935 * @brief Set Wake-up pin trigger type at Deep Power down mode
AnnaBridge 172:7d866c31b3c5 936 *
AnnaBridge 172:7d866c31b3c5 937 * @param[in] u32TriggerType
AnnaBridge 172:7d866c31b3c5 938 * - \ref CLK_DPDWKPIN_RISING
AnnaBridge 172:7d866c31b3c5 939 * - \ref CLK_DPDWKPIN_FALLING
AnnaBridge 172:7d866c31b3c5 940 * - \ref CLK_DPDWKPIN_BOTHEDGE
AnnaBridge 172:7d866c31b3c5 941 * @return None
AnnaBridge 172:7d866c31b3c5 942 *
AnnaBridge 172:7d866c31b3c5 943 * @details This function is used to enable Wake-up pin trigger type.
AnnaBridge 172:7d866c31b3c5 944 */
AnnaBridge 172:7d866c31b3c5 945
AnnaBridge 172:7d866c31b3c5 946 void CLK_EnableDPDWKPin(uint32_t u32TriggerType)
AnnaBridge 172:7d866c31b3c5 947 {
AnnaBridge 172:7d866c31b3c5 948 CLK->PMUCTL = (CLK->PMUCTL & ~(CLK_PMUCTL_WKPINEN_Msk)) | u32TriggerType;
AnnaBridge 172:7d866c31b3c5 949 }
AnnaBridge 172:7d866c31b3c5 950
AnnaBridge 172:7d866c31b3c5 951 /**
AnnaBridge 172:7d866c31b3c5 952 * @brief Get power manager wake up source
AnnaBridge 172:7d866c31b3c5 953 *
AnnaBridge 172:7d866c31b3c5 954 * @param[in] None
AnnaBridge 172:7d866c31b3c5 955 * @return None
AnnaBridge 172:7d866c31b3c5 956 *
AnnaBridge 172:7d866c31b3c5 957 * @details This function get power manager wake up source.
AnnaBridge 172:7d866c31b3c5 958 */
AnnaBridge 172:7d866c31b3c5 959
AnnaBridge 172:7d866c31b3c5 960 uint32_t CLK_GetPMUWKSrc(void)
AnnaBridge 172:7d866c31b3c5 961 {
AnnaBridge 172:7d866c31b3c5 962 return (CLK->PMUSTS);
AnnaBridge 172:7d866c31b3c5 963 }
AnnaBridge 172:7d866c31b3c5 964
AnnaBridge 172:7d866c31b3c5 965 /**
AnnaBridge 172:7d866c31b3c5 966 * @brief Set specified GPIO as wake up source at Stand-by Power down mode
AnnaBridge 172:7d866c31b3c5 967 *
AnnaBridge 172:7d866c31b3c5 968 * @param[in] u32Port GPIO port. It could be 0~3.
AnnaBridge 172:7d866c31b3c5 969 * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
AnnaBridge 172:7d866c31b3c5 970 * @param[in] u32TriggerType
AnnaBridge 172:7d866c31b3c5 971 * - \ref CLK_SPDWKPIN_RISING
AnnaBridge 172:7d866c31b3c5 972 * - \ref CLK_SPDWKPIN_FALLING
AnnaBridge 172:7d866c31b3c5 973 * @param[in] u32DebounceEn
AnnaBridge 172:7d866c31b3c5 974 * - \ref CLK_SPDWKPIN_DEBOUNCEEN
AnnaBridge 172:7d866c31b3c5 975 * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
AnnaBridge 172:7d866c31b3c5 976 * @return None
AnnaBridge 172:7d866c31b3c5 977 *
AnnaBridge 172:7d866c31b3c5 978 * @details This function is used to set specified GPIO as wake up source
AnnaBridge 172:7d866c31b3c5 979 * at Stand-by Power down mode.
AnnaBridge 172:7d866c31b3c5 980 */
AnnaBridge 172:7d866c31b3c5 981 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
AnnaBridge 172:7d866c31b3c5 982 {
AnnaBridge 172:7d866c31b3c5 983 uint32_t u32tmpAddr = 0UL;
AnnaBridge 172:7d866c31b3c5 984 uint32_t u32tmpVal = 0UL;
AnnaBridge 172:7d866c31b3c5 985
AnnaBridge 172:7d866c31b3c5 986 /* GPx Stand-by Power-down Wake-up Pin Select */
AnnaBridge 172:7d866c31b3c5 987 u32tmpAddr = (uint32_t)&CLK->PASWKCTL;
AnnaBridge 172:7d866c31b3c5 988 u32tmpAddr += (0x4UL * u32Port);
AnnaBridge 172:7d866c31b3c5 989
AnnaBridge 172:7d866c31b3c5 990 u32tmpVal = inpw((uint32_t *)u32tmpAddr);
AnnaBridge 172:7d866c31b3c5 991 u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
AnnaBridge 172:7d866c31b3c5 992 (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
AnnaBridge 172:7d866c31b3c5 993 outpw((uint32_t *)u32tmpAddr, u32tmpVal);
AnnaBridge 172:7d866c31b3c5 994 }
AnnaBridge 172:7d866c31b3c5 995
AnnaBridge 172:7d866c31b3c5 996 /*@}*/ /* end of group M480_CLK_EXPORTED_FUNCTIONS */
AnnaBridge 172:7d866c31b3c5 997
AnnaBridge 172:7d866c31b3c5 998 /*@}*/ /* end of group M480_CLK_Driver */
AnnaBridge 172:7d866c31b3c5 999
AnnaBridge 172:7d866c31b3c5 1000 /*@}*/ /* end of group M480_Device_Driver */
AnnaBridge 172:7d866c31b3c5 1001
AnnaBridge 172:7d866c31b3c5 1002 /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/