mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/TARGET_NUCLEO_L496ZG/system_clock.c@178:79309dc6340a, 2017-11-23 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 23 11:57:25 2017 +0000
- Revision:
- 178:79309dc6340a
- Parent:
- 177:d650f5d4c87a
- Child:
- 187:0387e8f68319
mbed-dev library. Release version 156
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 177:d650f5d4c87a | 1 | /* mbed Microcontroller Library |
AnnaBridge | 177:d650f5d4c87a | 2 | * Copyright (c) 2006-2017 ARM Limited |
AnnaBridge | 177:d650f5d4c87a | 3 | * |
AnnaBridge | 177:d650f5d4c87a | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
AnnaBridge | 177:d650f5d4c87a | 5 | * you may not use this file except in compliance with the License. |
AnnaBridge | 177:d650f5d4c87a | 6 | * You may obtain a copy of the License at |
AnnaBridge | 177:d650f5d4c87a | 7 | * |
AnnaBridge | 177:d650f5d4c87a | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
AnnaBridge | 177:d650f5d4c87a | 9 | * |
AnnaBridge | 177:d650f5d4c87a | 10 | * Unless required by applicable law or agreed to in writing, software |
AnnaBridge | 177:d650f5d4c87a | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
AnnaBridge | 177:d650f5d4c87a | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
AnnaBridge | 177:d650f5d4c87a | 13 | * See the License for the specific language governing permissions and |
AnnaBridge | 177:d650f5d4c87a | 14 | * limitations under the License. |
AnnaBridge | 177:d650f5d4c87a | 15 | */ |
AnnaBridge | 177:d650f5d4c87a | 16 | |
AnnaBridge | 177:d650f5d4c87a | 17 | /** |
AnnaBridge | 177:d650f5d4c87a | 18 | * This file configures the system clock as follows: |
AnnaBridge | 177:d650f5d4c87a | 19 | *----------------------------------------------------------------------------- |
AnnaBridge | 177:d650f5d4c87a | 20 | * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) |
AnnaBridge | 177:d650f5d4c87a | 21 | * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) |
AnnaBridge | 177:d650f5d4c87a | 22 | * | 3- USE_PLL_HSI (internal 16 MHz) |
AnnaBridge | 177:d650f5d4c87a | 23 | * | 4- USE_PLL_MSI (internal 100kHz to 48 MHz) |
AnnaBridge | 177:d650f5d4c87a | 24 | *----------------------------------------------------------------------------- |
AnnaBridge | 177:d650f5d4c87a | 25 | * SYSCLK(MHz) | 80 |
AnnaBridge | 177:d650f5d4c87a | 26 | * AHBCLK (MHz) | 80 |
AnnaBridge | 177:d650f5d4c87a | 27 | * APB1CLK (MHz) | 80 |
AnnaBridge | 177:d650f5d4c87a | 28 | * APB2CLK (MHz) | 80 |
AnnaBridge | 177:d650f5d4c87a | 29 | * USB capable | YES |
AnnaBridge | 177:d650f5d4c87a | 30 | *----------------------------------------------------------------------------- |
AnnaBridge | 177:d650f5d4c87a | 31 | **/ |
AnnaBridge | 177:d650f5d4c87a | 32 | |
AnnaBridge | 177:d650f5d4c87a | 33 | #include "stm32l4xx.h" |
AnnaBridge | 177:d650f5d4c87a | 34 | #include "nvic_addr.h" |
AnnaBridge | 177:d650f5d4c87a | 35 | #include "mbed_assert.h" |
AnnaBridge | 177:d650f5d4c87a | 36 | |
AnnaBridge | 177:d650f5d4c87a | 37 | /*!< Uncomment the following line if you need to relocate your vector Table in |
AnnaBridge | 177:d650f5d4c87a | 38 | Internal SRAM. */ |
AnnaBridge | 177:d650f5d4c87a | 39 | /* #define VECT_TAB_SRAM */ |
AnnaBridge | 177:d650f5d4c87a | 40 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
AnnaBridge | 177:d650f5d4c87a | 41 | This value must be a multiple of 0x200. */ |
AnnaBridge | 177:d650f5d4c87a | 42 | |
AnnaBridge | 177:d650f5d4c87a | 43 | |
AnnaBridge | 177:d650f5d4c87a | 44 | // clock source is selected with CLOCK_SOURCE in json config |
AnnaBridge | 177:d650f5d4c87a | 45 | #define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO - not enabled by default) |
AnnaBridge | 177:d650f5d4c87a | 46 | #define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) |
AnnaBridge | 177:d650f5d4c87a | 47 | #define USE_PLL_HSI 0x2 // Use HSI internal clock |
AnnaBridge | 177:d650f5d4c87a | 48 | #define USE_PLL_MSI 0x1 // Use MSI internal clock |
AnnaBridge | 177:d650f5d4c87a | 49 | |
AnnaBridge | 177:d650f5d4c87a | 50 | #define DEBUG_MCO (0) // Output the MCO on PA8 for debugging (0=OFF, 1=SYSCLK, 2=HSE, 3=HSI, 4=MSI) |
AnnaBridge | 177:d650f5d4c87a | 51 | |
AnnaBridge | 177:d650f5d4c87a | 52 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
AnnaBridge | 177:d650f5d4c87a | 53 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
AnnaBridge | 177:d650f5d4c87a | 54 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
AnnaBridge | 177:d650f5d4c87a | 55 | |
AnnaBridge | 177:d650f5d4c87a | 56 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 177:d650f5d4c87a | 57 | uint8_t SetSysClock_PLL_HSI(void); |
AnnaBridge | 177:d650f5d4c87a | 58 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
AnnaBridge | 177:d650f5d4c87a | 59 | |
AnnaBridge | 177:d650f5d4c87a | 60 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 177:d650f5d4c87a | 61 | uint8_t SetSysClock_PLL_MSI(void); |
AnnaBridge | 177:d650f5d4c87a | 62 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |
AnnaBridge | 177:d650f5d4c87a | 63 | |
AnnaBridge | 177:d650f5d4c87a | 64 | |
AnnaBridge | 177:d650f5d4c87a | 65 | /** |
AnnaBridge | 177:d650f5d4c87a | 66 | * @brief Setup the microcontroller system. |
AnnaBridge | 177:d650f5d4c87a | 67 | * @param None |
AnnaBridge | 177:d650f5d4c87a | 68 | * @retval None |
AnnaBridge | 177:d650f5d4c87a | 69 | */ |
AnnaBridge | 177:d650f5d4c87a | 70 | |
AnnaBridge | 177:d650f5d4c87a | 71 | void SystemInit(void) |
AnnaBridge | 177:d650f5d4c87a | 72 | { |
AnnaBridge | 177:d650f5d4c87a | 73 | /* FPU settings ------------------------------------------------------------*/ |
AnnaBridge | 177:d650f5d4c87a | 74 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
AnnaBridge | 177:d650f5d4c87a | 75 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
AnnaBridge | 177:d650f5d4c87a | 76 | #endif |
AnnaBridge | 177:d650f5d4c87a | 77 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
AnnaBridge | 177:d650f5d4c87a | 78 | /* Set MSION bit */ |
AnnaBridge | 177:d650f5d4c87a | 79 | RCC->CR |= RCC_CR_MSION; |
AnnaBridge | 177:d650f5d4c87a | 80 | |
AnnaBridge | 177:d650f5d4c87a | 81 | /* Reset CFGR register */ |
AnnaBridge | 177:d650f5d4c87a | 82 | RCC->CFGR = 0x00000000; |
AnnaBridge | 177:d650f5d4c87a | 83 | |
AnnaBridge | 177:d650f5d4c87a | 84 | /* Reset HSEON, CSSON , HSION, and PLLON bits */ |
AnnaBridge | 177:d650f5d4c87a | 85 | RCC->CR &= (uint32_t)0xEAF6FFFF; |
AnnaBridge | 177:d650f5d4c87a | 86 | |
AnnaBridge | 177:d650f5d4c87a | 87 | /* Reset PLLCFGR register */ |
AnnaBridge | 177:d650f5d4c87a | 88 | RCC->PLLCFGR = 0x00001000; |
AnnaBridge | 177:d650f5d4c87a | 89 | |
AnnaBridge | 177:d650f5d4c87a | 90 | /* Reset HSEBYP bit */ |
AnnaBridge | 177:d650f5d4c87a | 91 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
AnnaBridge | 177:d650f5d4c87a | 92 | |
AnnaBridge | 177:d650f5d4c87a | 93 | /* Disable all interrupts */ |
AnnaBridge | 177:d650f5d4c87a | 94 | RCC->CIER = 0x00000000; |
AnnaBridge | 177:d650f5d4c87a | 95 | |
AnnaBridge | 177:d650f5d4c87a | 96 | /* Configure the Vector Table location add offset address ------------------*/ |
AnnaBridge | 177:d650f5d4c87a | 97 | #ifdef VECT_TAB_SRAM |
AnnaBridge | 177:d650f5d4c87a | 98 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
AnnaBridge | 177:d650f5d4c87a | 99 | #else |
AnnaBridge | 177:d650f5d4c87a | 100 | SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */ |
AnnaBridge | 177:d650f5d4c87a | 101 | #endif |
AnnaBridge | 177:d650f5d4c87a | 102 | |
AnnaBridge | 177:d650f5d4c87a | 103 | } |
AnnaBridge | 177:d650f5d4c87a | 104 | |
AnnaBridge | 177:d650f5d4c87a | 105 | |
AnnaBridge | 177:d650f5d4c87a | 106 | /** |
AnnaBridge | 177:d650f5d4c87a | 107 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
AnnaBridge | 177:d650f5d4c87a | 108 | * AHB/APBx prescalers and Flash settings |
AnnaBridge | 177:d650f5d4c87a | 109 | * @note This function should be called only once the RCC clock configuration |
AnnaBridge | 177:d650f5d4c87a | 110 | * is reset to the default reset state (done in SystemInit() function). |
AnnaBridge | 177:d650f5d4c87a | 111 | * @param None |
AnnaBridge | 177:d650f5d4c87a | 112 | * @retval None |
AnnaBridge | 177:d650f5d4c87a | 113 | */ |
AnnaBridge | 177:d650f5d4c87a | 114 | |
AnnaBridge | 177:d650f5d4c87a | 115 | void SetSysClock(void) |
AnnaBridge | 177:d650f5d4c87a | 116 | { |
AnnaBridge | 177:d650f5d4c87a | 117 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) |
AnnaBridge | 177:d650f5d4c87a | 118 | /* 1- Try to start with HSE and external clock */ |
AnnaBridge | 177:d650f5d4c87a | 119 | if (SetSysClock_PLL_HSE(1) == 0) |
AnnaBridge | 177:d650f5d4c87a | 120 | #endif |
AnnaBridge | 177:d650f5d4c87a | 121 | { |
AnnaBridge | 177:d650f5d4c87a | 122 | #if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) |
AnnaBridge | 177:d650f5d4c87a | 123 | /* 2- If fail try to start with HSE and external xtal */ |
AnnaBridge | 177:d650f5d4c87a | 124 | if (SetSysClock_PLL_HSE(0) == 0) |
AnnaBridge | 177:d650f5d4c87a | 125 | #endif |
AnnaBridge | 177:d650f5d4c87a | 126 | { |
AnnaBridge | 177:d650f5d4c87a | 127 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 177:d650f5d4c87a | 128 | /* 3- If fail start with HSI clock */ |
AnnaBridge | 177:d650f5d4c87a | 129 | if (SetSysClock_PLL_HSI()==0) |
AnnaBridge | 177:d650f5d4c87a | 130 | #endif |
AnnaBridge | 177:d650f5d4c87a | 131 | { |
AnnaBridge | 177:d650f5d4c87a | 132 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 177:d650f5d4c87a | 133 | /* 4- If fail start with MSI clock */ |
AnnaBridge | 177:d650f5d4c87a | 134 | if (SetSysClock_PLL_MSI() == 0) |
AnnaBridge | 177:d650f5d4c87a | 135 | #endif |
AnnaBridge | 177:d650f5d4c87a | 136 | { |
AnnaBridge | 177:d650f5d4c87a | 137 | while(1) { |
AnnaBridge | 177:d650f5d4c87a | 138 | MBED_ASSERT(1); |
AnnaBridge | 177:d650f5d4c87a | 139 | } |
AnnaBridge | 177:d650f5d4c87a | 140 | } |
AnnaBridge | 177:d650f5d4c87a | 141 | } |
AnnaBridge | 177:d650f5d4c87a | 142 | } |
AnnaBridge | 177:d650f5d4c87a | 143 | } |
AnnaBridge | 177:d650f5d4c87a | 144 | |
AnnaBridge | 177:d650f5d4c87a | 145 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 177:d650f5d4c87a | 146 | #if DEBUG_MCO == 1 |
AnnaBridge | 177:d650f5d4c87a | 147 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
AnnaBridge | 177:d650f5d4c87a | 148 | #endif |
AnnaBridge | 177:d650f5d4c87a | 149 | } |
AnnaBridge | 177:d650f5d4c87a | 150 | |
AnnaBridge | 177:d650f5d4c87a | 151 | #if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) |
AnnaBridge | 177:d650f5d4c87a | 152 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 153 | /* PLL (clocked by HSE) used as System clock source */ |
AnnaBridge | 177:d650f5d4c87a | 154 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 155 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
AnnaBridge | 177:d650f5d4c87a | 156 | { |
AnnaBridge | 177:d650f5d4c87a | 157 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 158 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 159 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
AnnaBridge | 177:d650f5d4c87a | 160 | |
AnnaBridge | 177:d650f5d4c87a | 161 | // Used to gain time after DeepSleep in case HSI is used |
AnnaBridge | 177:d650f5d4c87a | 162 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { |
AnnaBridge | 177:d650f5d4c87a | 163 | return 0; |
AnnaBridge | 177:d650f5d4c87a | 164 | } |
AnnaBridge | 177:d650f5d4c87a | 165 | |
AnnaBridge | 177:d650f5d4c87a | 166 | // Select MSI as system clock source to allow modification of the PLL configuration |
AnnaBridge | 177:d650f5d4c87a | 167 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
AnnaBridge | 177:d650f5d4c87a | 168 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
AnnaBridge | 177:d650f5d4c87a | 169 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
AnnaBridge | 177:d650f5d4c87a | 170 | |
AnnaBridge | 177:d650f5d4c87a | 171 | // Enable HSE oscillator and activate PLL with HSE as source |
AnnaBridge | 177:d650f5d4c87a | 172 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI; |
AnnaBridge | 177:d650f5d4c87a | 173 | if (bypass == 0) { |
AnnaBridge | 177:d650f5d4c87a | 174 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT |
AnnaBridge | 177:d650f5d4c87a | 175 | } else { |
AnnaBridge | 177:d650f5d4c87a | 176 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN |
AnnaBridge | 177:d650f5d4c87a | 177 | } |
AnnaBridge | 177:d650f5d4c87a | 178 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
AnnaBridge | 177:d650f5d4c87a | 179 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz |
AnnaBridge | 177:d650f5d4c87a | 180 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 177:d650f5d4c87a | 181 | RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 8 MHz (8 MHz / 1) |
AnnaBridge | 177:d650f5d4c87a | 182 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
AnnaBridge | 177:d650f5d4c87a | 183 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
AnnaBridge | 177:d650f5d4c87a | 184 | RCC_OscInitStruct.PLL.PLLQ = 2; |
AnnaBridge | 177:d650f5d4c87a | 185 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
AnnaBridge | 177:d650f5d4c87a | 186 | |
AnnaBridge | 177:d650f5d4c87a | 187 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 188 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 189 | } |
AnnaBridge | 177:d650f5d4c87a | 190 | |
AnnaBridge | 177:d650f5d4c87a | 191 | // Select PLL clock as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 177:d650f5d4c87a | 192 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 178:79309dc6340a | 193 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
AnnaBridge | 178:79309dc6340a | 194 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
AnnaBridge | 178:79309dc6340a | 195 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 178:79309dc6340a | 196 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 177:d650f5d4c87a | 197 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 198 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 199 | } |
AnnaBridge | 177:d650f5d4c87a | 200 | |
AnnaBridge | 177:d650f5d4c87a | 201 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 177:d650f5d4c87a | 202 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
AnnaBridge | 177:d650f5d4c87a | 203 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE; |
AnnaBridge | 177:d650f5d4c87a | 204 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1; |
AnnaBridge | 177:d650f5d4c87a | 205 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
AnnaBridge | 177:d650f5d4c87a | 206 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
AnnaBridge | 177:d650f5d4c87a | 207 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
AnnaBridge | 177:d650f5d4c87a | 208 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
AnnaBridge | 177:d650f5d4c87a | 209 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
AnnaBridge | 177:d650f5d4c87a | 210 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 211 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 212 | } |
AnnaBridge | 177:d650f5d4c87a | 213 | |
AnnaBridge | 177:d650f5d4c87a | 214 | // Disable MSI Oscillator |
AnnaBridge | 177:d650f5d4c87a | 215 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
AnnaBridge | 177:d650f5d4c87a | 216 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
AnnaBridge | 177:d650f5d4c87a | 217 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 177:d650f5d4c87a | 218 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
AnnaBridge | 177:d650f5d4c87a | 219 | |
AnnaBridge | 178:79309dc6340a | 220 | /* Select HSI as clock source for LPUART1 */ |
AnnaBridge | 178:79309dc6340a | 221 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 178:79309dc6340a | 222 | RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; |
AnnaBridge | 178:79309dc6340a | 223 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 178:79309dc6340a | 224 | return 0; // FAIL |
AnnaBridge | 178:79309dc6340a | 225 | } |
AnnaBridge | 178:79309dc6340a | 226 | |
AnnaBridge | 177:d650f5d4c87a | 227 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 177:d650f5d4c87a | 228 | #if DEBUG_MCO == 2 |
AnnaBridge | 177:d650f5d4c87a | 229 | if (bypass == 0) |
AnnaBridge | 177:d650f5d4c87a | 230 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
AnnaBridge | 177:d650f5d4c87a | 231 | else |
AnnaBridge | 177:d650f5d4c87a | 232 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
AnnaBridge | 177:d650f5d4c87a | 233 | #endif |
AnnaBridge | 177:d650f5d4c87a | 234 | |
AnnaBridge | 177:d650f5d4c87a | 235 | return 1; // OK |
AnnaBridge | 177:d650f5d4c87a | 236 | } |
AnnaBridge | 177:d650f5d4c87a | 237 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ |
AnnaBridge | 177:d650f5d4c87a | 238 | |
AnnaBridge | 177:d650f5d4c87a | 239 | #if ((CLOCK_SOURCE) & USE_PLL_HSI) |
AnnaBridge | 177:d650f5d4c87a | 240 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 241 | /* PLL (clocked by HSI) used as System clock source */ |
AnnaBridge | 177:d650f5d4c87a | 242 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 243 | uint8_t SetSysClock_PLL_HSI(void) |
AnnaBridge | 177:d650f5d4c87a | 244 | { |
AnnaBridge | 177:d650f5d4c87a | 245 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 246 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 247 | RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit = {0}; |
AnnaBridge | 177:d650f5d4c87a | 248 | |
AnnaBridge | 177:d650f5d4c87a | 249 | // Select MSI as system clock source to allow modification of the PLL configuration |
AnnaBridge | 177:d650f5d4c87a | 250 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; |
AnnaBridge | 177:d650f5d4c87a | 251 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; |
AnnaBridge | 177:d650f5d4c87a | 252 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0); |
AnnaBridge | 177:d650f5d4c87a | 253 | |
AnnaBridge | 177:d650f5d4c87a | 254 | // Enable HSI oscillator and activate PLL with HSI as source |
AnnaBridge | 177:d650f5d4c87a | 255 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
AnnaBridge | 177:d650f5d4c87a | 256 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
AnnaBridge | 177:d650f5d4c87a | 257 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
AnnaBridge | 177:d650f5d4c87a | 258 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; |
AnnaBridge | 177:d650f5d4c87a | 259 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 177:d650f5d4c87a | 260 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // 16 MHz |
AnnaBridge | 177:d650f5d4c87a | 261 | RCC_OscInitStruct.PLL.PLLM = 2; // VCO input clock = 8 MHz (16 MHz / 2) |
AnnaBridge | 177:d650f5d4c87a | 262 | RCC_OscInitStruct.PLL.PLLN = 20; // VCO output clock = 160 MHz (8 MHz * 20) |
AnnaBridge | 177:d650f5d4c87a | 263 | RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22 MHz (160 MHz / 7) |
AnnaBridge | 177:d650f5d4c87a | 264 | RCC_OscInitStruct.PLL.PLLQ = 2; |
AnnaBridge | 177:d650f5d4c87a | 265 | RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2) |
AnnaBridge | 177:d650f5d4c87a | 266 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 267 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 268 | } |
AnnaBridge | 177:d650f5d4c87a | 269 | |
AnnaBridge | 177:d650f5d4c87a | 270 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 177:d650f5d4c87a | 271 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 177:d650f5d4c87a | 272 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz |
AnnaBridge | 177:d650f5d4c87a | 273 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz |
AnnaBridge | 177:d650f5d4c87a | 274 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 177:d650f5d4c87a | 275 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz |
AnnaBridge | 177:d650f5d4c87a | 276 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 277 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 278 | } |
AnnaBridge | 177:d650f5d4c87a | 279 | |
AnnaBridge | 177:d650f5d4c87a | 280 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 177:d650f5d4c87a | 281 | RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1; |
AnnaBridge | 177:d650f5d4c87a | 282 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSI; |
AnnaBridge | 177:d650f5d4c87a | 283 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 2; |
AnnaBridge | 177:d650f5d4c87a | 284 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12; |
AnnaBridge | 177:d650f5d4c87a | 285 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; |
AnnaBridge | 177:d650f5d4c87a | 286 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; |
AnnaBridge | 177:d650f5d4c87a | 287 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; |
AnnaBridge | 177:d650f5d4c87a | 288 | RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK; |
AnnaBridge | 177:d650f5d4c87a | 289 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 290 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 291 | } |
AnnaBridge | 177:d650f5d4c87a | 292 | |
AnnaBridge | 177:d650f5d4c87a | 293 | // Disable MSI Oscillator |
AnnaBridge | 177:d650f5d4c87a | 294 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; |
AnnaBridge | 177:d650f5d4c87a | 295 | RCC_OscInitStruct.MSIState = RCC_MSI_OFF; |
AnnaBridge | 177:d650f5d4c87a | 296 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 177:d650f5d4c87a | 297 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
AnnaBridge | 177:d650f5d4c87a | 298 | |
AnnaBridge | 178:79309dc6340a | 299 | /* Select HSI as clock source for LPUART1 */ |
AnnaBridge | 178:79309dc6340a | 300 | RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 178:79309dc6340a | 301 | RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI; |
AnnaBridge | 178:79309dc6340a | 302 | if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) { |
AnnaBridge | 178:79309dc6340a | 303 | return 0; // FAIL |
AnnaBridge | 178:79309dc6340a | 304 | } |
AnnaBridge | 178:79309dc6340a | 305 | |
AnnaBridge | 177:d650f5d4c87a | 306 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 177:d650f5d4c87a | 307 | #if DEBUG_MCO == 3 |
AnnaBridge | 177:d650f5d4c87a | 308 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
AnnaBridge | 177:d650f5d4c87a | 309 | #endif |
AnnaBridge | 177:d650f5d4c87a | 310 | |
AnnaBridge | 177:d650f5d4c87a | 311 | return 1; // OK |
AnnaBridge | 177:d650f5d4c87a | 312 | } |
AnnaBridge | 177:d650f5d4c87a | 313 | #endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ |
AnnaBridge | 177:d650f5d4c87a | 314 | |
AnnaBridge | 177:d650f5d4c87a | 315 | #if ((CLOCK_SOURCE) & USE_PLL_MSI) |
AnnaBridge | 177:d650f5d4c87a | 316 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 317 | /* PLL (clocked by MSI) used as System clock source */ |
AnnaBridge | 177:d650f5d4c87a | 318 | /******************************************************************************/ |
AnnaBridge | 177:d650f5d4c87a | 319 | uint8_t SetSysClock_PLL_MSI(void) |
AnnaBridge | 177:d650f5d4c87a | 320 | { |
AnnaBridge | 177:d650f5d4c87a | 321 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 322 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 323 | RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; |
AnnaBridge | 177:d650f5d4c87a | 324 | |
AnnaBridge | 177:d650f5d4c87a | 325 | // Enable LSE Oscillator to automatically calibrate the MSI clock |
AnnaBridge | 177:d650f5d4c87a | 326 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE; |
AnnaBridge | 177:d650f5d4c87a | 327 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update |
AnnaBridge | 177:d650f5d4c87a | 328 | RCC_OscInitStruct.LSEState = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT |
AnnaBridge | 177:d650f5d4c87a | 329 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 330 | RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode |
AnnaBridge | 177:d650f5d4c87a | 331 | } |
AnnaBridge | 177:d650f5d4c87a | 332 | |
AnnaBridge | 177:d650f5d4c87a | 333 | HAL_RCCEx_DisableLSECSS(); |
AnnaBridge | 177:d650f5d4c87a | 334 | /* Enable MSI Oscillator and activate PLL with MSI as source */ |
AnnaBridge | 177:d650f5d4c87a | 335 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE; |
AnnaBridge | 177:d650f5d4c87a | 336 | RCC_OscInitStruct.MSIState = RCC_MSI_ON; |
AnnaBridge | 177:d650f5d4c87a | 337 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
AnnaBridge | 177:d650f5d4c87a | 338 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
AnnaBridge | 177:d650f5d4c87a | 339 | RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; |
AnnaBridge | 177:d650f5d4c87a | 340 | RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11; /* 48 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 341 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
AnnaBridge | 177:d650f5d4c87a | 342 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; |
AnnaBridge | 177:d650f5d4c87a | 343 | RCC_OscInitStruct.PLL.PLLM = 6; /* 8 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 344 | RCC_OscInitStruct.PLL.PLLN = 40; /* 320 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 345 | RCC_OscInitStruct.PLL.PLLP = 7; /* 45 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 346 | RCC_OscInitStruct.PLL.PLLQ = 4; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 347 | RCC_OscInitStruct.PLL.PLLR = 4; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 348 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 349 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 350 | } |
AnnaBridge | 177:d650f5d4c87a | 351 | /* Enable MSI Auto-calibration through LSE */ |
AnnaBridge | 177:d650f5d4c87a | 352 | HAL_RCCEx_EnableMSIPLLMode(); |
AnnaBridge | 177:d650f5d4c87a | 353 | /* Select MSI output as USB clock source */ |
AnnaBridge | 177:d650f5d4c87a | 354 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; |
AnnaBridge | 177:d650f5d4c87a | 355 | PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI; /* 48 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 356 | HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); |
AnnaBridge | 177:d650f5d4c87a | 357 | |
AnnaBridge | 177:d650f5d4c87a | 358 | // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers |
AnnaBridge | 177:d650f5d4c87a | 359 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
AnnaBridge | 177:d650f5d4c87a | 360 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 361 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 362 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 363 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; /* 80 MHz */ |
AnnaBridge | 177:d650f5d4c87a | 364 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { |
AnnaBridge | 177:d650f5d4c87a | 365 | return 0; // FAIL |
AnnaBridge | 177:d650f5d4c87a | 366 | } |
AnnaBridge | 177:d650f5d4c87a | 367 | |
AnnaBridge | 178:79309dc6340a | 368 | /* Select LSE as clock source for LPUART1 */ |
AnnaBridge | 178:79309dc6340a | 369 | PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; |
AnnaBridge | 178:79309dc6340a | 370 | PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; |
AnnaBridge | 178:79309dc6340a | 371 | if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
AnnaBridge | 178:79309dc6340a | 372 | return 0; // FAIL |
AnnaBridge | 178:79309dc6340a | 373 | } |
AnnaBridge | 178:79309dc6340a | 374 | |
AnnaBridge | 177:d650f5d4c87a | 375 | // Output clock on MCO1 pin(PA8) for debugging purpose |
AnnaBridge | 177:d650f5d4c87a | 376 | #if DEBUG_MCO == 4 |
AnnaBridge | 177:d650f5d4c87a | 377 | HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_MSI, RCC_MCODIV_2); // 2 MHz |
AnnaBridge | 177:d650f5d4c87a | 378 | #endif |
AnnaBridge | 177:d650f5d4c87a | 379 | |
AnnaBridge | 177:d650f5d4c87a | 380 | return 1; // OK |
AnnaBridge | 177:d650f5d4c87a | 381 | } |
AnnaBridge | 177:d650f5d4c87a | 382 | #endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */ |