mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/sleep.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
181:57724642e740
Child:
187:0387e8f68319
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /* mbed Microcontroller Library
<> 154:37f96f9d4de2 2 *******************************************************************************
Anna Bridge 186:707f6e361f3e 3 * Copyright (c) 2018, STMicroelectronics
<> 154:37f96f9d4de2 4 * All rights reserved.
<> 154:37f96f9d4de2 5 *
<> 154:37f96f9d4de2 6 * Redistribution and use in source and binary forms, with or without
<> 154:37f96f9d4de2 7 * modification, are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 8 *
<> 154:37f96f9d4de2 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 10 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 12 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 13 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 15 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 16 * without specific prior written permission.
<> 154:37f96f9d4de2 17 *
<> 154:37f96f9d4de2 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 28 *******************************************************************************
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30 #if DEVICE_SLEEP
<> 154:37f96f9d4de2 31
<> 160:d5399cc887bb 32 #include "sleep_api.h"
Anna Bridge 186:707f6e361f3e 33 #include "us_ticker_api.h"
Anna Bridge 186:707f6e361f3e 34 #include "hal_tick.h"
Anna Bridge 186:707f6e361f3e 35 #include "mbed_critical.h"
Anna Bridge 186:707f6e361f3e 36 #include "mbed_error.h"
Anna Bridge 186:707f6e361f3e 37
Anna Bridge 186:707f6e361f3e 38 extern void rtc_synchronize(void);
Anna Bridge 186:707f6e361f3e 39
Anna Bridge 186:707f6e361f3e 40 /* Wait loop - assuming tick is 1 us */
Anna Bridge 186:707f6e361f3e 41 static void wait_loop(uint32_t timeout)
Anna Bridge 186:707f6e361f3e 42 {
Anna Bridge 186:707f6e361f3e 43 uint32_t t1, t2, elapsed = 0;
Anna Bridge 186:707f6e361f3e 44 t1 = us_ticker_read();
Anna Bridge 186:707f6e361f3e 45 do {
Anna Bridge 186:707f6e361f3e 46 t2 = us_ticker_read();
Anna Bridge 186:707f6e361f3e 47 elapsed = (t2 > t1) ? (t2 - t1) : ((uint64_t)t2 + 0xFFFFFFFF - t1 + 1);
Anna Bridge 186:707f6e361f3e 48 } while (elapsed < timeout);
Anna Bridge 186:707f6e361f3e 49 return;
Anna Bridge 186:707f6e361f3e 50 }
Anna Bridge 186:707f6e361f3e 51
Anna Bridge 186:707f6e361f3e 52 // On L4 platforms we've seen unstable PLL CLK configuraiton
Anna Bridge 186:707f6e361f3e 53 // when DEEP SLEEP exits just few µs after being entered
Anna Bridge 186:707f6e361f3e 54 // So we need to force MSI usage before setting clocks again
Anna Bridge 186:707f6e361f3e 55 static void ForceClockOutofDeepSleep(void)
Anna Bridge 186:707f6e361f3e 56 {
Anna Bridge 186:707f6e361f3e 57 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
Anna Bridge 186:707f6e361f3e 58 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
Anna Bridge 186:707f6e361f3e 59 uint32_t pFLatency = 0;
Anna Bridge 186:707f6e361f3e 60
Anna Bridge 186:707f6e361f3e 61 /* Enable Power Control clock */
Anna Bridge 186:707f6e361f3e 62 __HAL_RCC_PWR_CLK_ENABLE();
Anna Bridge 186:707f6e361f3e 63
Anna Bridge 186:707f6e361f3e 64 #ifdef PWR_FLAG_VOS
Anna Bridge 186:707f6e361f3e 65 /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
Anna Bridge 186:707f6e361f3e 66 //while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
Anna Bridge 186:707f6e361f3e 67 #endif
Anna Bridge 186:707f6e361f3e 68
Anna Bridge 186:707f6e361f3e 69 /* Get the Oscillators configuration according to the internal RCC registers */
Anna Bridge 186:707f6e361f3e 70 HAL_RCC_GetOscConfig(&RCC_OscInitStruct);
Anna Bridge 186:707f6e361f3e 71
Anna Bridge 186:707f6e361f3e 72 #if (TARGET_STM32L4 || TARGET_STM32L1) /* MSI used for L4 */
Anna Bridge 186:707f6e361f3e 73 /**Initializes the CPU, AHB and APB busses clocks
Anna Bridge 186:707f6e361f3e 74 */
Anna Bridge 186:707f6e361f3e 75 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
Anna Bridge 186:707f6e361f3e 76 RCC_OscInitStruct.MSIState = RCC_MSI_ON;
Anna Bridge 186:707f6e361f3e 77 RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
Anna Bridge 186:707f6e361f3e 78 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; // Intermediate freq, 1MHz range
Anna Bridge 186:707f6e361f3e 79 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
Anna Bridge 186:707f6e361f3e 80 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Anna Bridge 186:707f6e361f3e 81 error("clock issue\r\n");
Anna Bridge 186:707f6e361f3e 82 }
<> 154:37f96f9d4de2 83
Anna Bridge 186:707f6e361f3e 84 /* Get the Clocks configuration according to the internal RCC registers */
Anna Bridge 186:707f6e361f3e 85 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
Anna Bridge 186:707f6e361f3e 86
Anna Bridge 186:707f6e361f3e 87 // Select HSI ss system clock source as a first step
Anna Bridge 186:707f6e361f3e 88 #ifdef RCC_CLOCKTYPE_PCLK2
Anna Bridge 186:707f6e361f3e 89 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
Anna Bridge 186:707f6e361f3e 90 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
Anna Bridge 186:707f6e361f3e 91 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Anna Bridge 186:707f6e361f3e 92 #else
Anna Bridge 186:707f6e361f3e 93 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK
Anna Bridge 186:707f6e361f3e 94 | RCC_CLOCKTYPE_PCLK1);
Anna Bridge 186:707f6e361f3e 95 #endif
Anna Bridge 186:707f6e361f3e 96 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
Anna Bridge 186:707f6e361f3e 97 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Anna Bridge 186:707f6e361f3e 98 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
Anna Bridge 186:707f6e361f3e 99 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
Anna Bridge 186:707f6e361f3e 100 error("clock issue\r\n");
Anna Bridge 186:707f6e361f3e 101 }
Anna Bridge 186:707f6e361f3e 102 #else /* HSI used on others */
Anna Bridge 186:707f6e361f3e 103 /**Initializes the CPU, AHB and APB busses clocks
Anna Bridge 186:707f6e361f3e 104 */
Anna Bridge 186:707f6e361f3e 105 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
Anna Bridge 186:707f6e361f3e 106 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
Anna Bridge 186:707f6e361f3e 107 RCC_OscInitStruct.HSICalibrationValue = 16;
Anna Bridge 186:707f6e361f3e 108 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
Anna Bridge 186:707f6e361f3e 109 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
Anna Bridge 186:707f6e361f3e 110 error("clock issue");
Anna Bridge 186:707f6e361f3e 111 }
Anna Bridge 186:707f6e361f3e 112
Anna Bridge 186:707f6e361f3e 113 /* Get the Clocks configuration according to the internal RCC registers */
Anna Bridge 186:707f6e361f3e 114 HAL_RCC_GetClockConfig(&RCC_ClkInitStruct, &pFLatency);
Anna Bridge 186:707f6e361f3e 115
Anna Bridge 186:707f6e361f3e 116 /**Initializes the CPU, AHB and APB busses clocks
Anna Bridge 186:707f6e361f3e 117 */
Anna Bridge 186:707f6e361f3e 118 #ifdef RCC_CLOCKTYPE_PCLK2
Anna Bridge 186:707f6e361f3e 119 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
Anna Bridge 186:707f6e361f3e 120 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2);
Anna Bridge 186:707f6e361f3e 121 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
Anna Bridge 186:707f6e361f3e 122 #else
Anna Bridge 186:707f6e361f3e 123 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
Anna Bridge 186:707f6e361f3e 124 |RCC_CLOCKTYPE_PCLK1);
Anna Bridge 186:707f6e361f3e 125 #endif
Anna Bridge 186:707f6e361f3e 126 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
Anna Bridge 186:707f6e361f3e 127 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
Anna Bridge 186:707f6e361f3e 128 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
Anna Bridge 186:707f6e361f3e 129 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, pFLatency) != HAL_OK) {
Anna Bridge 186:707f6e361f3e 130 error("clock issue");
Anna Bridge 186:707f6e361f3e 131 }
Anna Bridge 186:707f6e361f3e 132 #endif // TARGET_STM32L4
Anna Bridge 186:707f6e361f3e 133 }
<> 160:d5399cc887bb 134
<> 160:d5399cc887bb 135 void hal_sleep(void)
<> 154:37f96f9d4de2 136 {
AnnaBridge 172:7d866c31b3c5 137 // Disable IRQs
AnnaBridge 172:7d866c31b3c5 138 core_util_critical_section_enter();
AnnaBridge 172:7d866c31b3c5 139
<> 154:37f96f9d4de2 140 // Request to enter SLEEP mode
<> 154:37f96f9d4de2 141 HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
AnnaBridge 172:7d866c31b3c5 142
AnnaBridge 172:7d866c31b3c5 143 // Enable IRQs
AnnaBridge 172:7d866c31b3c5 144 core_util_critical_section_exit();
<> 154:37f96f9d4de2 145 }
<> 154:37f96f9d4de2 146
<> 160:d5399cc887bb 147 void hal_deepsleep(void)
<> 154:37f96f9d4de2 148 {
AnnaBridge 172:7d866c31b3c5 149 // Disable IRQs
AnnaBridge 172:7d866c31b3c5 150 core_util_critical_section_enter();
AnnaBridge 172:7d866c31b3c5 151
<> 160:d5399cc887bb 152 uint32_t EnterTimeUS = us_ticker_read();
<> 154:37f96f9d4de2 153
<> 154:37f96f9d4de2 154 // Request to enter STOP mode with regulator in low power mode
<> 154:37f96f9d4de2 155 #if TARGET_STM32L4
<> 160:d5399cc887bb 156 int pwrClockEnabled = __HAL_RCC_PWR_IS_CLK_ENABLED();
<> 160:d5399cc887bb 157 int lowPowerModeEnabled = PWR->CR1 & PWR_CR1_LPR;
Anna Bridge 180:96ed750bd169 158
<> 160:d5399cc887bb 159 if (!pwrClockEnabled) {
<> 160:d5399cc887bb 160 __HAL_RCC_PWR_CLK_ENABLE();
<> 160:d5399cc887bb 161 }
<> 160:d5399cc887bb 162 if (lowPowerModeEnabled) {
<> 156:95d6b41a828b 163 HAL_PWREx_DisableLowPowerRunMode();
<> 160:d5399cc887bb 164 }
Anna Bridge 180:96ed750bd169 165
<> 160:d5399cc887bb 166 HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI);
Anna Bridge 180:96ed750bd169 167
<> 160:d5399cc887bb 168 if (lowPowerModeEnabled) {
<> 156:95d6b41a828b 169 HAL_PWREx_EnableLowPowerRunMode();
<> 160:d5399cc887bb 170 }
<> 160:d5399cc887bb 171 if (!pwrClockEnabled) {
<> 156:95d6b41a828b 172 __HAL_RCC_PWR_CLK_DISABLE();
<> 156:95d6b41a828b 173 }
<> 154:37f96f9d4de2 174 #else /* TARGET_STM32L4 */
<> 154:37f96f9d4de2 175 HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
<> 154:37f96f9d4de2 176 #endif /* TARGET_STM32L4 */
Anna Bridge 186:707f6e361f3e 177 // Verify Clock Out of Deep Sleep
Anna Bridge 186:707f6e361f3e 178 ForceClockOutofDeepSleep();
AnnaBridge 172:7d866c31b3c5 179
<> 154:37f96f9d4de2 180 // After wake-up from STOP reconfigure the PLL
<> 154:37f96f9d4de2 181 SetSysClock();
<> 154:37f96f9d4de2 182
Anna Bridge 186:707f6e361f3e 183 /* Wait for clock to be stabilized.
Anna Bridge 186:707f6e361f3e 184 * TO DO: a better way of doing this, would be to rely on
Anna Bridge 186:707f6e361f3e 185 * HW Flag. At least this ensures proper operation out of
Anna Bridge 186:707f6e361f3e 186 * deep sleep */
Anna Bridge 186:707f6e361f3e 187 wait_loop(500);
Anna Bridge 186:707f6e361f3e 188
<> 160:d5399cc887bb 189 TIM_HandleTypeDef TimMasterHandle;
<> 160:d5399cc887bb 190 TimMasterHandle.Instance = TIM_MST;
<> 160:d5399cc887bb 191 __HAL_TIM_SET_COUNTER(&TimMasterHandle, EnterTimeUS);
<> 160:d5399cc887bb 192
Anna Bridge 180:96ed750bd169 193 #if DEVICE_RTC
Anna Bridge 180:96ed750bd169 194 /* Wait for RTC RSF bit synchro if RTC is configured */
Anna Bridge 180:96ed750bd169 195 #if (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7)
Anna Bridge 180:96ed750bd169 196 if (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) {
Anna Bridge 180:96ed750bd169 197 #else /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
Anna Bridge 180:96ed750bd169 198 if (__HAL_RCC_GET_RTC_SOURCE()) {
Anna Bridge 180:96ed750bd169 199 #endif /* (TARGET_STM32F2) || (TARGET_STM32F4) || (TARGET_STM32F7) */
Anna Bridge 180:96ed750bd169 200 rtc_synchronize();
Anna Bridge 180:96ed750bd169 201 }
<> 154:37f96f9d4de2 202 #endif
Anna Bridge 186:707f6e361f3e 203 // Enable IRQs
Anna Bridge 186:707f6e361f3e 204 core_util_critical_section_exit();
<> 154:37f96f9d4de2 205 }
<> 154:37f96f9d4de2 206
<> 154:37f96f9d4de2 207 #endif