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targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:: Anna Bridge
Date:: Fri Jun 22 16:45:37 2018 +0100
Revision:: 186:707f6e361f3e
Parent:: 151:5eaa88a5bcc7

mbed-dev library. Release version 162

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_tim.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @brief Header file of TIM HAL module.
<>	144:ef7eb2e8f9f7	6	******************************************************************************
<>	144:ef7eb2e8f9f7	7	* @attention
<>	144:ef7eb2e8f9f7	8	*
<>	144:ef7eb2e8f9f7	9	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	12	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	13	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	14	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	17	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	19	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	20	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	21	*
<>	144:ef7eb2e8f9f7	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	32	*
<>	144:ef7eb2e8f9f7	33	******************************************************************************
<>	144:ef7eb2e8f9f7	34	*/
<>	144:ef7eb2e8f9f7	35
<>	144:ef7eb2e8f9f7	36	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	37	#ifndef __STM32L0xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	38	#define __STM32L0xx_HAL_TIM_H
<>	144:ef7eb2e8f9f7	39
<>	144:ef7eb2e8f9f7	40	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	41	extern "C" {
<>	144:ef7eb2e8f9f7	42	#endif
<>	144:ef7eb2e8f9f7	43
<>	144:ef7eb2e8f9f7	44	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	45	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	48	* @{
<>	144:ef7eb2e8f9f7	49	*/
<>	144:ef7eb2e8f9f7	50
<>	144:ef7eb2e8f9f7	51	/** @defgroup TIM TIM (Timer)
<>	144:ef7eb2e8f9f7	52	* @{
<>	144:ef7eb2e8f9f7	53	*/
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/** @defgroup TIM_Exported_Types TIM Exported Types
<>	144:ef7eb2e8f9f7	58	* @{
<>	144:ef7eb2e8f9f7	59	*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/** @defgroup TIM_Base_Configuration TIM base configuration structure
<>	144:ef7eb2e8f9f7	62	* @{
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64	/**
<>	144:ef7eb2e8f9f7	65	* @brief TIM Time base Configuration Structure definition
<>	144:ef7eb2e8f9f7	66	*/
<>	144:ef7eb2e8f9f7	67	typedef struct
<>	144:ef7eb2e8f9f7	68	{
<>	144:ef7eb2e8f9f7	69	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
<>	144:ef7eb2e8f9f7	70	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	uint32_t CounterMode; /*!< Specifies the counter mode.
<>	144:ef7eb2e8f9f7	73	This parameter can be a value of @ref TIM_Counter_Mode */
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	uint32_t Period; /*!< Specifies the period value to be loaded into the active
<>	144:ef7eb2e8f9f7	76	Auto-Reload Register at the next update event.
<>	144:ef7eb2e8f9f7	77	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t ClockDivision; /*!< Specifies the clock division.
<>	144:ef7eb2e8f9f7	80	This parameter can be a value of @ref TIM_ClockDivision */
<>	144:ef7eb2e8f9f7	81	} TIM_Base_InitTypeDef;
<>	144:ef7eb2e8f9f7	82	/**
<>	144:ef7eb2e8f9f7	83	* @}
<>	144:ef7eb2e8f9f7	84	*/
<>	144:ef7eb2e8f9f7	85
<>	144:ef7eb2e8f9f7	86	/** @defgroup TIM_Output_Configuration TIM output compare configuration structure
<>	144:ef7eb2e8f9f7	87	* @{
<>	144:ef7eb2e8f9f7	88	*/
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	/**
<>	144:ef7eb2e8f9f7	91	* @brief TIM Output Compare Configuration Structure definition
<>	144:ef7eb2e8f9f7	92	*/
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	typedef struct
<>	144:ef7eb2e8f9f7	95	{
<>	144:ef7eb2e8f9f7	96	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	97	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	100	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	101
<>	144:ef7eb2e8f9f7	102	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	103	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	104
<>	144:ef7eb2e8f9f7	105	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
<>	144:ef7eb2e8f9f7	106	This parameter can be a value of @ref TIM_Output_Fast_State
<>	144:ef7eb2e8f9f7	107	@note This parameter is valid only in PWM1 and PWM2 mode. */
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	} TIM_OC_InitTypeDef;
<>	144:ef7eb2e8f9f7	110	/**
<>	144:ef7eb2e8f9f7	111	* @}
<>	144:ef7eb2e8f9f7	112	*/
<>	144:ef7eb2e8f9f7	113
<>	144:ef7eb2e8f9f7	114	/** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
<>	144:ef7eb2e8f9f7	115	* @{
<>	144:ef7eb2e8f9f7	116	*/
<>	144:ef7eb2e8f9f7	117	/**
<>	144:ef7eb2e8f9f7	118	* @brief TIM One Pulse Mode Configuration Structure definition
<>	144:ef7eb2e8f9f7	119	*/
<>	144:ef7eb2e8f9f7	120	typedef struct
<>	144:ef7eb2e8f9f7	121	{
<>	144:ef7eb2e8f9f7	122	uint32_t OCMode; /*!< Specifies the TIM mode.
<>	144:ef7eb2e8f9f7	123	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
<>	144:ef7eb2e8f9f7	124
<>	144:ef7eb2e8f9f7	125	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
<>	144:ef7eb2e8f9f7	126	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
<>	144:ef7eb2e8f9f7	127
<>	144:ef7eb2e8f9f7	128	uint32_t OCPolarity; /*!< Specifies the output polarity.
<>	144:ef7eb2e8f9f7	129	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
<>	144:ef7eb2e8f9f7	130
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	136	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	139	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	140	} TIM_OnePulse_InitTypeDef;
<>	144:ef7eb2e8f9f7	141	/**
<>	144:ef7eb2e8f9f7	142	* @}
<>	144:ef7eb2e8f9f7	143	*/
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/** @defgroup TIM_Input_Capture TIM input capture configuration structure
<>	144:ef7eb2e8f9f7	146	* @{
<>	144:ef7eb2e8f9f7	147	*/
<>	144:ef7eb2e8f9f7	148	/**
<>	144:ef7eb2e8f9f7	149	* @brief TIM Input Capture Configuration Structure definition
<>	144:ef7eb2e8f9f7	150	*/
<>	144:ef7eb2e8f9f7	151
<>	144:ef7eb2e8f9f7	152	typedef struct
<>	144:ef7eb2e8f9f7	153	{
<>	144:ef7eb2e8f9f7	154	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	155	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	156
<>	144:ef7eb2e8f9f7	157	uint32_t ICSelection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	158	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	159
<>	144:ef7eb2e8f9f7	160	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	161	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	uint32_t ICFilter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	164	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	165	} TIM_IC_InitTypeDef;
<>	144:ef7eb2e8f9f7	166	/**
<>	144:ef7eb2e8f9f7	167	* @}
<>	144:ef7eb2e8f9f7	168	*/
<>	144:ef7eb2e8f9f7	169
<>	144:ef7eb2e8f9f7	170	/** @defgroup TIM_Encoder TIM encoder configuration structure
<>	144:ef7eb2e8f9f7	171	* @{
<>	144:ef7eb2e8f9f7	172	*/
<>	144:ef7eb2e8f9f7	173	/**
<>	144:ef7eb2e8f9f7	174	* @brief TIM Encoder Configuration Structure definition
<>	144:ef7eb2e8f9f7	175	*/
<>	144:ef7eb2e8f9f7	176
<>	144:ef7eb2e8f9f7	177	typedef struct
<>	144:ef7eb2e8f9f7	178	{
<>	144:ef7eb2e8f9f7	179	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	180	This parameter can be a value of @ref TIM_Encoder_Mode */
<>	144:ef7eb2e8f9f7	181
<>	144:ef7eb2e8f9f7	182	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	183	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	184
<>	144:ef7eb2e8f9f7	185	uint32_t IC1Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	186	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	189	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	190
<>	144:ef7eb2e8f9f7	191	uint32_t IC1Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	192	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	193
<>	144:ef7eb2e8f9f7	194	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
<>	144:ef7eb2e8f9f7	195	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	uint32_t IC2Selection; /*!< Specifies the input.
<>	144:ef7eb2e8f9f7	198	This parameter can be a value of @ref TIM_Input_Capture_Selection */
<>	144:ef7eb2e8f9f7	199
<>	144:ef7eb2e8f9f7	200	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
<>	144:ef7eb2e8f9f7	201	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	uint32_t IC2Filter; /*!< Specifies the input capture filter.
<>	144:ef7eb2e8f9f7	204	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	205	} TIM_Encoder_InitTypeDef;
<>	144:ef7eb2e8f9f7	206	/**
<>	144:ef7eb2e8f9f7	207	* @}
<>	144:ef7eb2e8f9f7	208	*/
<>	144:ef7eb2e8f9f7	209
<>	144:ef7eb2e8f9f7	210	/** @defgroup TIM_Clock_Configuration TIM clock configuration structure
<>	144:ef7eb2e8f9f7	211	* @{
<>	144:ef7eb2e8f9f7	212	*/
<>	144:ef7eb2e8f9f7	213	/**
<>	144:ef7eb2e8f9f7	214	* @brief Clock Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	215	*/
<>	144:ef7eb2e8f9f7	216	typedef struct
<>	144:ef7eb2e8f9f7	217	{
<>	144:ef7eb2e8f9f7	218	uint32_t ClockSource; /*!< TIM clock sources.
<>	144:ef7eb2e8f9f7	219	This parameter can be a value of @ref TIM_Clock_Source */
<>	144:ef7eb2e8f9f7	220	uint32_t ClockPolarity; /*!< TIM clock polarity.
<>	144:ef7eb2e8f9f7	221	This parameter can be a value of @ref TIM_Clock_Polarity */
<>	144:ef7eb2e8f9f7	222	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
<>	144:ef7eb2e8f9f7	223	This parameter can be a value of @ref TIM_Clock_Prescaler */
<>	144:ef7eb2e8f9f7	224	uint32_t ClockFilter; /*!< TIM clock filter.
<>	144:ef7eb2e8f9f7	225	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	226	}TIM_ClockConfigTypeDef;
<>	144:ef7eb2e8f9f7	227	/**
<>	144:ef7eb2e8f9f7	228	* @}
<>	144:ef7eb2e8f9f7	229	*/
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	/** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
<>	144:ef7eb2e8f9f7	232	* @{
<>	144:ef7eb2e8f9f7	233	*/
<>	144:ef7eb2e8f9f7	234	/**
<>	144:ef7eb2e8f9f7	235	* @brief Clear Input Configuration Handle Structure definition
<>	144:ef7eb2e8f9f7	236	*/
<>	144:ef7eb2e8f9f7	237	typedef struct
<>	144:ef7eb2e8f9f7	238	{
<>	144:ef7eb2e8f9f7	239	uint32_t ClearInputState; /*!< TIM clear Input state.
<>	144:ef7eb2e8f9f7	240	This parameter can be ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	241	uint32_t ClearInputSource; /*!< TIM clear Input sources.
<>	144:ef7eb2e8f9f7	242	This parameter can be a value of @ref TIM_ClearInput_Source */
<>	144:ef7eb2e8f9f7	243	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
<>	144:ef7eb2e8f9f7	244	This parameter can be a value of @ref TIM_ClearInput_Polarity */
<>	144:ef7eb2e8f9f7	245	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
<>	144:ef7eb2e8f9f7	246	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
<>	144:ef7eb2e8f9f7	247	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
<>	144:ef7eb2e8f9f7	248	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	249	}TIM_ClearInputConfigTypeDef;
<>	144:ef7eb2e8f9f7	250	/**
<>	144:ef7eb2e8f9f7	251	* @}
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	/** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
<>	144:ef7eb2e8f9f7	255	* @{
<>	144:ef7eb2e8f9f7	256	*/
<>	144:ef7eb2e8f9f7	257	/**
<>	144:ef7eb2e8f9f7	258	* @brief TIM Slave configuration Structure definition
<>	144:ef7eb2e8f9f7	259	*/
<>	144:ef7eb2e8f9f7	260	typedef struct {
<>	144:ef7eb2e8f9f7	261	uint32_t SlaveMode; /*!< Slave mode selection.
<>	144:ef7eb2e8f9f7	262	This parameter can be a value of @ref TIM_Slave_Mode */
<>	144:ef7eb2e8f9f7	263	uint32_t InputTrigger; /*!< Input Trigger source.
<>	144:ef7eb2e8f9f7	264	This parameter can be a value of @ref TIM_Trigger_Selection */
<>	144:ef7eb2e8f9f7	265	uint32_t TriggerPolarity; /*!< Input Trigger polarity.
<>	144:ef7eb2e8f9f7	266	This parameter can be a value of @ref TIM_Trigger_Polarity */
<>	144:ef7eb2e8f9f7	267	uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
<>	144:ef7eb2e8f9f7	268	This parameter can be a value of @ref TIM_Trigger_Prescaler */
<>	144:ef7eb2e8f9f7	269	uint32_t TriggerFilter; /*!< Input trigger filter.
<>	144:ef7eb2e8f9f7	270	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	}TIM_SlaveConfigTypeDef;
<>	144:ef7eb2e8f9f7	273	/**
<>	144:ef7eb2e8f9f7	274	* @}
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/** @defgroup TIM_State_Definition TIM state definition
<>	144:ef7eb2e8f9f7	278	* @{
<>	144:ef7eb2e8f9f7	279	*/
<>	144:ef7eb2e8f9f7	280	/**
<>	144:ef7eb2e8f9f7	281	* @brief HAL State structures definition
<>	144:ef7eb2e8f9f7	282	*/
<>	144:ef7eb2e8f9f7	283	typedef enum
<>	144:ef7eb2e8f9f7	284	{
<>	151:5eaa88a5bcc7	285	HAL_TIM_STATE_RESET = 0x00U, /!< Peripheral not yet initialized or disabled /
<>	151:5eaa88a5bcc7	286	HAL_TIM_STATE_READY = 0x01U, /!< Peripheral Initialized and ready for use /
<>	151:5eaa88a5bcc7	287	HAL_TIM_STATE_BUSY = 0x02U, /!< An internal process is ongoing /
<>	151:5eaa88a5bcc7	288	HAL_TIM_STATE_TIMEOUT = 0x03U, /!< Timeout state /
<>	151:5eaa88a5bcc7	289	HAL_TIM_STATE_ERROR = 0x04U /!< Reception process is ongoing /
<>	144:ef7eb2e8f9f7	290	}HAL_TIM_StateTypeDef;
<>	144:ef7eb2e8f9f7	291	/**
<>	144:ef7eb2e8f9f7	292	* @}
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294
<>	144:ef7eb2e8f9f7	295	/** @defgroup TIM_Active_Channel TIM active channel definition
<>	144:ef7eb2e8f9f7	296	* @{
<>	144:ef7eb2e8f9f7	297	*/
<>	144:ef7eb2e8f9f7	298	/**
<>	144:ef7eb2e8f9f7	299	* @brief HAL Active channel structures definition
<>	144:ef7eb2e8f9f7	300	*/
<>	144:ef7eb2e8f9f7	301	typedef enum
<>	144:ef7eb2e8f9f7	302	{
<>	151:5eaa88a5bcc7	303	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /!< The active channel is 1 /
<>	151:5eaa88a5bcc7	304	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /!< The active channel is 2 /
<>	151:5eaa88a5bcc7	305	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /!< The active channel is 3 /
<>	151:5eaa88a5bcc7	306	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /!< The active channel is 4 /
<>	151:5eaa88a5bcc7	307	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /!< All active channels cleared /
<>	144:ef7eb2e8f9f7	308	}HAL_TIM_ActiveChannel;
<>	144:ef7eb2e8f9f7	309	/**
<>	144:ef7eb2e8f9f7	310	* @}
<>	144:ef7eb2e8f9f7	311	*/
<>	144:ef7eb2e8f9f7	312
<>	144:ef7eb2e8f9f7	313	/** @defgroup TIM_Handle TIM handler
<>	144:ef7eb2e8f9f7	314	* @{
<>	144:ef7eb2e8f9f7	315	*/
<>	144:ef7eb2e8f9f7	316	/**
<>	144:ef7eb2e8f9f7	317	* @brief TIM Time Base Handle Structure definition
<>	144:ef7eb2e8f9f7	318	*/
<>	144:ef7eb2e8f9f7	319	typedef struct
<>	144:ef7eb2e8f9f7	320	{
<>	144:ef7eb2e8f9f7	321	TIM_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	322	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
<>	144:ef7eb2e8f9f7	323	HAL_TIM_ActiveChannel Channel; /!< Active channel /
<>	144:ef7eb2e8f9f7	324	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
<>	144:ef7eb2e8f9f7	325	This array is accessed by a @ref DMA_Handle_index */
<>	144:ef7eb2e8f9f7	326	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	327	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
<>	144:ef7eb2e8f9f7	328	}TIM_HandleTypeDef;
<>	144:ef7eb2e8f9f7	329	/**
<>	144:ef7eb2e8f9f7	330	* @}
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/**
<>	144:ef7eb2e8f9f7	334	* @}
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	337	/** @defgroup TIM_Exported_Constants TIM Exported Constants
<>	144:ef7eb2e8f9f7	338	* @{
<>	144:ef7eb2e8f9f7	339	*/
<>	144:ef7eb2e8f9f7	340
<>	144:ef7eb2e8f9f7	341
<>	151:5eaa88a5bcc7	342	#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU)
<>	144:ef7eb2e8f9f7	343
<>	151:5eaa88a5bcc7	344	#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU)
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346
<>	144:ef7eb2e8f9f7	347	/** @defgroup TIM_Input_Channel_Polarity Input channel polarity
<>	144:ef7eb2e8f9f7	348	* @{
<>	144:ef7eb2e8f9f7	349	*/
<>	151:5eaa88a5bcc7	350	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	351	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	352	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
<>	144:ef7eb2e8f9f7	353	/**
<>	144:ef7eb2e8f9f7	354	* @}
<>	144:ef7eb2e8f9f7	355	*/
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/** @defgroup TIM_ETR_Polarity ETR polarity
<>	144:ef7eb2e8f9f7	358	* @{
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
<>	151:5eaa88a5bcc7	361	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /!< Polarity for ETR source /
<>	144:ef7eb2e8f9f7	362	/**
<>	144:ef7eb2e8f9f7	363	* @}
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/** @defgroup TIM_ETR_Prescaler ETR prescaler
<>	144:ef7eb2e8f9f7	367	* @{
<>	144:ef7eb2e8f9f7	368	*/
<>	151:5eaa88a5bcc7	369	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	370	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
<>	144:ef7eb2e8f9f7	371	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
<>	144:ef7eb2e8f9f7	372	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
<>	144:ef7eb2e8f9f7	373	/**
<>	144:ef7eb2e8f9f7	374	* @}
<>	144:ef7eb2e8f9f7	375	*/
<>	144:ef7eb2e8f9f7	376
<>	144:ef7eb2e8f9f7	377	/** @defgroup TIM_Counter_Mode Counter mode
<>	144:ef7eb2e8f9f7	378	* @{
<>	144:ef7eb2e8f9f7	379	*/
<>	151:5eaa88a5bcc7	380	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	381	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
<>	144:ef7eb2e8f9f7	382	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
<>	144:ef7eb2e8f9f7	383	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
<>	144:ef7eb2e8f9f7	384	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @}
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
<>	144:ef7eb2e8f9f7	389	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
<>	144:ef7eb2e8f9f7	390	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
<>	144:ef7eb2e8f9f7	391	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
<>	144:ef7eb2e8f9f7	392	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
<>	144:ef7eb2e8f9f7	393
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396
<>	144:ef7eb2e8f9f7	397	/** @defgroup TIM_ClockDivision Clock division
<>	144:ef7eb2e8f9f7	398	* @{
<>	144:ef7eb2e8f9f7	399	*/
<>	151:5eaa88a5bcc7	400	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	401	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
<>	144:ef7eb2e8f9f7	402	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
<>	144:ef7eb2e8f9f7	403	/**
<>	144:ef7eb2e8f9f7	404	* @}
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	407	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	408	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
<>	144:ef7eb2e8f9f7	409
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
<>	144:ef7eb2e8f9f7	412	* @{
<>	144:ef7eb2e8f9f7	413	*/
<>	151:5eaa88a5bcc7	414	#define TIM_OCMODE_TIMING ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	415	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
<>	144:ef7eb2e8f9f7	416	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	417	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
<>	144:ef7eb2e8f9f7	418	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	419	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
<>	144:ef7eb2e8f9f7	420	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	421	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
<>	144:ef7eb2e8f9f7	422	/**
<>	144:ef7eb2e8f9f7	423	* @}
<>	144:ef7eb2e8f9f7	424	*/
<>	144:ef7eb2e8f9f7	425
<>	144:ef7eb2e8f9f7	426	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
<>	144:ef7eb2e8f9f7	427	((__MODE__) == TIM_OCMODE_PWM2))
<>	144:ef7eb2e8f9f7	428
<>	144:ef7eb2e8f9f7	429	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
<>	144:ef7eb2e8f9f7	430	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	431	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	432	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
<>	144:ef7eb2e8f9f7	433	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
<>	144:ef7eb2e8f9f7	434	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	/** @defgroup TIM_Output_Compare_State Output compare state
<>	144:ef7eb2e8f9f7	438	* @{
<>	144:ef7eb2e8f9f7	439	*/
<>	151:5eaa88a5bcc7	440	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	441	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
<>	144:ef7eb2e8f9f7	442	/**
<>	144:ef7eb2e8f9f7	443	* @}
<>	144:ef7eb2e8f9f7	444	*/
<>	144:ef7eb2e8f9f7	445
<>	144:ef7eb2e8f9f7	446	/** @defgroup TIM_Output_Fast_State Output fast state
<>	144:ef7eb2e8f9f7	447	* @{
<>	144:ef7eb2e8f9f7	448	*/
<>	151:5eaa88a5bcc7	449	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	450	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
<>	144:ef7eb2e8f9f7	451	/**
<>	144:ef7eb2e8f9f7	452	* @}
<>	144:ef7eb2e8f9f7	453	*/
<>	144:ef7eb2e8f9f7	454	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	455	((__STATE__) == TIM_OCFAST_ENABLE))
<>	144:ef7eb2e8f9f7	456
<>	144:ef7eb2e8f9f7	457	/** @defgroup TIM_Output_Compare_N_State Output compare N state
<>	144:ef7eb2e8f9f7	458	* @{
<>	144:ef7eb2e8f9f7	459	*/
<>	151:5eaa88a5bcc7	460	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	461	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
<>	144:ef7eb2e8f9f7	462	/**
<>	144:ef7eb2e8f9f7	463	* @}
<>	144:ef7eb2e8f9f7	464	*/
<>	144:ef7eb2e8f9f7	465
<>	144:ef7eb2e8f9f7	466	/** @defgroup TIM_Output_Compare_Polarity Output compare polarity
<>	144:ef7eb2e8f9f7	467	* @{
<>	144:ef7eb2e8f9f7	468	*/
<>	151:5eaa88a5bcc7	469	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	470	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
<>	144:ef7eb2e8f9f7	471	/**
<>	144:ef7eb2e8f9f7	472	* @}
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	475	((__POLARITY__) == TIM_OCPOLARITY_LOW))
<>	144:ef7eb2e8f9f7	476
<>	144:ef7eb2e8f9f7	477	/** @defgroup TIM_Channel TIM channels
<>	144:ef7eb2e8f9f7	478	* @{
<>	144:ef7eb2e8f9f7	479	*/
<>	151:5eaa88a5bcc7	480	#define TIM_CHANNEL_1 ((uint32_t)0x0000U)
<>	151:5eaa88a5bcc7	481	#define TIM_CHANNEL_2 ((uint32_t)0x0004U)
<>	151:5eaa88a5bcc7	482	#define TIM_CHANNEL_3 ((uint32_t)0x0008U)
<>	151:5eaa88a5bcc7	483	#define TIM_CHANNEL_4 ((uint32_t)0x000CU)
<>	151:5eaa88a5bcc7	484	#define TIM_CHANNEL_ALL ((uint32_t)0x0018U)
<>	144:ef7eb2e8f9f7	485	/**
<>	144:ef7eb2e8f9f7	486	* @}
<>	144:ef7eb2e8f9f7	487	*/
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	490	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	491	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	492	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	493	((__CHANNEL__) == TIM_CHANNEL_ALL))
<>	144:ef7eb2e8f9f7	494
<>	144:ef7eb2e8f9f7	495	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	496	((__CHANNEL__) == TIM_CHANNEL_2))
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498
<>	144:ef7eb2e8f9f7	499	/** @defgroup TIM_Input_Capture_Polarity Input capture polarity
<>	144:ef7eb2e8f9f7	500	* @{
<>	144:ef7eb2e8f9f7	501	*/
<>	144:ef7eb2e8f9f7	502	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
<>	144:ef7eb2e8f9f7	503	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
<>	144:ef7eb2e8f9f7	504	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
<>	144:ef7eb2e8f9f7	505	/**
<>	144:ef7eb2e8f9f7	506	* @}
<>	144:ef7eb2e8f9f7	507	*/
<>	144:ef7eb2e8f9f7	508	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	509	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	510	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
<>	144:ef7eb2e8f9f7	511
<>	144:ef7eb2e8f9f7	512
<>	144:ef7eb2e8f9f7	513	/** @defgroup TIM_Input_Capture_Selection Input capture selection
<>	144:ef7eb2e8f9f7	514	* @{
<>	144:ef7eb2e8f9f7	515	*/
<>	144:ef7eb2e8f9f7	516	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	517	connected to IC1, IC2, IC3 or IC4, respectively */
<>	144:ef7eb2e8f9f7	518	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
<>	144:ef7eb2e8f9f7	519	connected to IC2, IC1, IC4 or IC3, respectively */
<>	144:ef7eb2e8f9f7	520	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	523	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
<>	144:ef7eb2e8f9f7	524	((__SELECTION__) == TIM_ICSELECTION_TRC))
<>	144:ef7eb2e8f9f7	525	/**
<>	144:ef7eb2e8f9f7	526	* @}
<>	144:ef7eb2e8f9f7	527	*/
<>	144:ef7eb2e8f9f7	528
<>	144:ef7eb2e8f9f7	529	/** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
<>	144:ef7eb2e8f9f7	530	* @{
<>	144:ef7eb2e8f9f7	531	*/
<>	151:5eaa88a5bcc7	532	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /!< Capture performed each time an edge is detected on the capture input /
<>	144:ef7eb2e8f9f7	533	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
<>	144:ef7eb2e8f9f7	534	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
<>	144:ef7eb2e8f9f7	535	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
<>	144:ef7eb2e8f9f7	536	/**
<>	144:ef7eb2e8f9f7	537	* @}
<>	144:ef7eb2e8f9f7	538	*/
<>	144:ef7eb2e8f9f7	539	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	540	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	541	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	542	((__PRESCALER__) == TIM_ICPSC_DIV8))
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/** @defgroup TIM_One_Pulse_Mode One pulse mode
<>	144:ef7eb2e8f9f7	545	* @{
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
<>	151:5eaa88a5bcc7	548	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	549	/**
<>	144:ef7eb2e8f9f7	550	* @}
<>	144:ef7eb2e8f9f7	551	*/
<>	144:ef7eb2e8f9f7	552	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
<>	144:ef7eb2e8f9f7	553	((__MODE__) == TIM_OPMODE_REPETITIVE))
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555	/** @defgroup TIM_Encoder_Mode Encoder_Mode
<>	144:ef7eb2e8f9f7	556	* @{
<>	144:ef7eb2e8f9f7	557	*/
<>	144:ef7eb2e8f9f7	558	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	559	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
<>	144:ef7eb2e8f9f7	560	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
<>	144:ef7eb2e8f9f7	561	/**
<>	144:ef7eb2e8f9f7	562	* @}
<>	144:ef7eb2e8f9f7	563	*/
<>	144:ef7eb2e8f9f7	564	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	565	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	566	((__MODE__) == TIM_ENCODERMODE_TI12))
<>	144:ef7eb2e8f9f7	567
<>	144:ef7eb2e8f9f7	568	/** @defgroup TIM_Interrupt_definition Interrupt definition
<>	144:ef7eb2e8f9f7	569	* @{
<>	144:ef7eb2e8f9f7	570	*/
<>	144:ef7eb2e8f9f7	571	#define TIM_IT_UPDATE (TIM_DIER_UIE)
<>	144:ef7eb2e8f9f7	572	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
<>	144:ef7eb2e8f9f7	573	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
<>	144:ef7eb2e8f9f7	574	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
<>	144:ef7eb2e8f9f7	575	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
<>	144:ef7eb2e8f9f7	576	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
<>	144:ef7eb2e8f9f7	577	/**
<>	144:ef7eb2e8f9f7	578	* @}
<>	144:ef7eb2e8f9f7	579	*/
<>	144:ef7eb2e8f9f7	580
<>	144:ef7eb2e8f9f7	581	/** @defgroup TIM_DMA_sources DMA sources
<>	144:ef7eb2e8f9f7	582	* @{
<>	144:ef7eb2e8f9f7	583	*/
<>	144:ef7eb2e8f9f7	584	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
<>	144:ef7eb2e8f9f7	585	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
<>	144:ef7eb2e8f9f7	586	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
<>	144:ef7eb2e8f9f7	587	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
<>	144:ef7eb2e8f9f7	588	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
<>	144:ef7eb2e8f9f7	589	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
<>	144:ef7eb2e8f9f7	590	/**
<>	144:ef7eb2e8f9f7	591	* @}
<>	144:ef7eb2e8f9f7	592	*/
<>	151:5eaa88a5bcc7	593	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595
<>	144:ef7eb2e8f9f7	596
<>	144:ef7eb2e8f9f7	597	/** @defgroup TIM_Event_Source Event sources
<>	144:ef7eb2e8f9f7	598	* @{
<>	144:ef7eb2e8f9f7	599	*/
<>	144:ef7eb2e8f9f7	600	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
<>	144:ef7eb2e8f9f7	601	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
<>	144:ef7eb2e8f9f7	602	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
<>	144:ef7eb2e8f9f7	603	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
<>	144:ef7eb2e8f9f7	604	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
<>	144:ef7eb2e8f9f7	605	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
<>	144:ef7eb2e8f9f7	606	/**
<>	144:ef7eb2e8f9f7	607	* @}
<>	144:ef7eb2e8f9f7	608	*/
<>	151:5eaa88a5bcc7	609	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
<>	144:ef7eb2e8f9f7	610
<>	144:ef7eb2e8f9f7	611
<>	144:ef7eb2e8f9f7	612	/** @defgroup TIM_Flag_definition Flag definition
<>	144:ef7eb2e8f9f7	613	* @{
<>	144:ef7eb2e8f9f7	614	*/
<>	144:ef7eb2e8f9f7	615	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
<>	144:ef7eb2e8f9f7	616	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
<>	144:ef7eb2e8f9f7	617	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
<>	144:ef7eb2e8f9f7	618	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
<>	144:ef7eb2e8f9f7	619	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
<>	144:ef7eb2e8f9f7	620	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
<>	144:ef7eb2e8f9f7	621	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
<>	144:ef7eb2e8f9f7	622	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
<>	144:ef7eb2e8f9f7	623	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
<>	144:ef7eb2e8f9f7	624	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
<>	144:ef7eb2e8f9f7	625	/**
<>	144:ef7eb2e8f9f7	626	* @}
<>	144:ef7eb2e8f9f7	627	*/
<>	144:ef7eb2e8f9f7	628
<>	144:ef7eb2e8f9f7	629	/** @defgroup TIM_Clock_Source Clock source
<>	144:ef7eb2e8f9f7	630	* @{
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
<>	144:ef7eb2e8f9f7	633	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
<>	151:5eaa88a5bcc7	634	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	635	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
<>	144:ef7eb2e8f9f7	636	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	637	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
<>	144:ef7eb2e8f9f7	638	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	639	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	640	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
<>	144:ef7eb2e8f9f7	641	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
<>	144:ef7eb2e8f9f7	642	/**
<>	144:ef7eb2e8f9f7	643	* @}
<>	144:ef7eb2e8f9f7	644	*/
<>	144:ef7eb2e8f9f7	645
<>	144:ef7eb2e8f9f7	646	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
<>	144:ef7eb2e8f9f7	647	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
<>	144:ef7eb2e8f9f7	648	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	649	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	650	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	651	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	652	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
<>	144:ef7eb2e8f9f7	653	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
<>	144:ef7eb2e8f9f7	654	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
<>	144:ef7eb2e8f9f7	655	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
<>	144:ef7eb2e8f9f7	656
<>	144:ef7eb2e8f9f7	657
<>	144:ef7eb2e8f9f7	658	/** @defgroup TIM_Clock_Polarity Clock polarity
<>	144:ef7eb2e8f9f7	659	* @{
<>	144:ef7eb2e8f9f7	660	*/
<>	144:ef7eb2e8f9f7	661	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
<>	144:ef7eb2e8f9f7	662	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
<>	144:ef7eb2e8f9f7	663	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	664	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	665	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
<>	144:ef7eb2e8f9f7	666	/**
<>	144:ef7eb2e8f9f7	667	* @}
<>	144:ef7eb2e8f9f7	668	*/
<>	144:ef7eb2e8f9f7	669	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	670	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	671	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
<>	144:ef7eb2e8f9f7	672	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	673	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
<>	144:ef7eb2e8f9f7	674
<>	144:ef7eb2e8f9f7	675	/** @defgroup TIM_Clock_Prescaler Clock prescaler
<>	144:ef7eb2e8f9f7	676	* @{
<>	144:ef7eb2e8f9f7	677	*/
<>	144:ef7eb2e8f9f7	678	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	679	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	680	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	681	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	682	/**
<>	144:ef7eb2e8f9f7	683	* @}
<>	144:ef7eb2e8f9f7	684	*/
<>	144:ef7eb2e8f9f7	685	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	686	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	687	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	688	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690
<>	144:ef7eb2e8f9f7	691	/* Check clock filter */
<>	151:5eaa88a5bcc7	692	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/** @defgroup TIM_ClearInput_Source Clear input source
<>	144:ef7eb2e8f9f7	695	* @{
<>	144:ef7eb2e8f9f7	696	*/
<>	151:5eaa88a5bcc7	697	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U)
<>	151:5eaa88a5bcc7	698	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	699	/**
<>	144:ef7eb2e8f9f7	700	* @}
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	#define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	704	((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
<>	144:ef7eb2e8f9f7	705
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/** @defgroup TIM_ClearInput_Polarity Clear input polarity
<>	144:ef7eb2e8f9f7	708	* @{
<>	144:ef7eb2e8f9f7	709	*/
<>	144:ef7eb2e8f9f7	710	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
<>	144:ef7eb2e8f9f7	711	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
<>	144:ef7eb2e8f9f7	712	/**
<>	144:ef7eb2e8f9f7	713	* @}
<>	144:ef7eb2e8f9f7	714	*/
<>	144:ef7eb2e8f9f7	715	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
<>	144:ef7eb2e8f9f7	716	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
<>	144:ef7eb2e8f9f7	717
<>	144:ef7eb2e8f9f7	718
<>	144:ef7eb2e8f9f7	719	/** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
<>	144:ef7eb2e8f9f7	720	* @{
<>	144:ef7eb2e8f9f7	721	*/
<>	144:ef7eb2e8f9f7	722	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	723	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	724	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	725	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	726	/**
<>	144:ef7eb2e8f9f7	727	* @}
<>	144:ef7eb2e8f9f7	728	*/
<>	144:ef7eb2e8f9f7	729	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	730	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	731	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	732	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734
<>	144:ef7eb2e8f9f7	735	/* Check IC filter */
<>	151:5eaa88a5bcc7	736	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU)
<>	144:ef7eb2e8f9f7	737
<>	144:ef7eb2e8f9f7	738
<>	144:ef7eb2e8f9f7	739	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
<>	144:ef7eb2e8f9f7	740	* @{
<>	144:ef7eb2e8f9f7	741	*/
<>	151:5eaa88a5bcc7	742	#define TIM_TRGO_RESET ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	743	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<>	144:ef7eb2e8f9f7	744	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<>	144:ef7eb2e8f9f7	745	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	746	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<>	144:ef7eb2e8f9f7	747	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	748	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
<>	144:ef7eb2e8f9f7	749	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
<>	144:ef7eb2e8f9f7	750	/**
<>	144:ef7eb2e8f9f7	751	* @}
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
<>	144:ef7eb2e8f9f7	754	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	755	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
<>	144:ef7eb2e8f9f7	756	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
<>	144:ef7eb2e8f9f7	757	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
<>	144:ef7eb2e8f9f7	758	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
<>	144:ef7eb2e8f9f7	759	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
<>	144:ef7eb2e8f9f7	760	((__SOURCE__) == TIM_TRGO_OC4REF))
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/** @defgroup TIM_Slave_Mode Slave mode
<>	144:ef7eb2e8f9f7	765	* @{
<>	144:ef7eb2e8f9f7	766	*/
<>	151:5eaa88a5bcc7	767	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U)
<>	151:5eaa88a5bcc7	768	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U)
<>	151:5eaa88a5bcc7	769	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U)
<>	151:5eaa88a5bcc7	770	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U)
<>	151:5eaa88a5bcc7	771	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U)
<>	144:ef7eb2e8f9f7	772	/**
<>	144:ef7eb2e8f9f7	773	* @}
<>	144:ef7eb2e8f9f7	774	*/
<>	144:ef7eb2e8f9f7	775	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	776	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
<>	144:ef7eb2e8f9f7	777	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
<>	144:ef7eb2e8f9f7	778	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	779	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
<>	144:ef7eb2e8f9f7	780
<>	144:ef7eb2e8f9f7	781	/** @defgroup TIM_Master_Slave_Mode Master slave mode
<>	144:ef7eb2e8f9f7	782	* @{
<>	144:ef7eb2e8f9f7	783	*/
<>	144:ef7eb2e8f9f7	784
<>	151:5eaa88a5bcc7	785	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U)
<>	151:5eaa88a5bcc7	786	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	787	/**
<>	144:ef7eb2e8f9f7	788	* @}
<>	144:ef7eb2e8f9f7	789	*/
<>	144:ef7eb2e8f9f7	790	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	791	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
<>	144:ef7eb2e8f9f7	792
<>	144:ef7eb2e8f9f7	793	/** @defgroup TIM_Trigger_Selection Trigger selection
<>	144:ef7eb2e8f9f7	794	* @{
<>	144:ef7eb2e8f9f7	795	*/
<>	151:5eaa88a5bcc7	796	#define TIM_TS_ITR0 ((uint32_t)0x0000U)
<>	151:5eaa88a5bcc7	797	#define TIM_TS_ITR1 ((uint32_t)0x0010U)
<>	151:5eaa88a5bcc7	798	#define TIM_TS_ITR2 ((uint32_t)0x0020U)
<>	151:5eaa88a5bcc7	799	#define TIM_TS_ITR3 ((uint32_t)0x0030U)
<>	151:5eaa88a5bcc7	800	#define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
<>	151:5eaa88a5bcc7	801	#define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
<>	151:5eaa88a5bcc7	802	#define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
<>	151:5eaa88a5bcc7	803	#define TIM_TS_ETRF ((uint32_t)0x0070U)
<>	151:5eaa88a5bcc7	804	#define TIM_TS_NONE ((uint32_t)0xFFFFU)
<>	144:ef7eb2e8f9f7	805	/**
<>	144:ef7eb2e8f9f7	806	* @}
<>	144:ef7eb2e8f9f7	807	*/
<>	144:ef7eb2e8f9f7	808	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	809	((__SELECTION__) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	810	((__SELECTION__) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	811	((__SELECTION__) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	812	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
<>	144:ef7eb2e8f9f7	813	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
<>	144:ef7eb2e8f9f7	814	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
<>	144:ef7eb2e8f9f7	815	((__SELECTION__) == TIM_TS_ETRF))
<>	144:ef7eb2e8f9f7	816	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
<>	144:ef7eb2e8f9f7	817	((__SELECTION__) == TIM_TS_ITR1) \|\| \
<>	144:ef7eb2e8f9f7	818	((__SELECTION__) == TIM_TS_ITR2) \|\| \
<>	144:ef7eb2e8f9f7	819	((__SELECTION__) == TIM_TS_ITR3) \|\| \
<>	144:ef7eb2e8f9f7	820	((__SELECTION__) == TIM_TS_NONE))
<>	144:ef7eb2e8f9f7	821
<>	144:ef7eb2e8f9f7	822
<>	144:ef7eb2e8f9f7	823	/** @defgroup TIM_Trigger_Polarity Trigger polarity
<>	144:ef7eb2e8f9f7	824	* @{
<>	144:ef7eb2e8f9f7	825	*/
<>	144:ef7eb2e8f9f7	826	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
<>	144:ef7eb2e8f9f7	827	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
<>	144:ef7eb2e8f9f7	828	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	829	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	830	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
<>	144:ef7eb2e8f9f7	831	/**
<>	144:ef7eb2e8f9f7	832	* @}
<>	144:ef7eb2e8f9f7	833	*/
<>	144:ef7eb2e8f9f7	834	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
<>	144:ef7eb2e8f9f7	835	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
<>	144:ef7eb2e8f9f7	836	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
<>	144:ef7eb2e8f9f7	837	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
<>	144:ef7eb2e8f9f7	838	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	/** @defgroup TIM_Trigger_Prescaler Trigger prescaler
<>	144:ef7eb2e8f9f7	842	* @{
<>	144:ef7eb2e8f9f7	843	*/
<>	144:ef7eb2e8f9f7	844	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
<>	144:ef7eb2e8f9f7	845	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
<>	144:ef7eb2e8f9f7	846	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
<>	144:ef7eb2e8f9f7	847	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
<>	144:ef7eb2e8f9f7	848	/**
<>	144:ef7eb2e8f9f7	849	* @}
<>	144:ef7eb2e8f9f7	850	*/
<>	144:ef7eb2e8f9f7	851	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	852	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	853	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	854	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
<>	144:ef7eb2e8f9f7	855
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/* Check trigger filter */
<>	151:5eaa88a5bcc7	858	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/** @defgroup TIM_TI1_Selection TI1 selection
<>	144:ef7eb2e8f9f7	862	* @{
<>	144:ef7eb2e8f9f7	863	*/
<>	151:5eaa88a5bcc7	864	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	865	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
<>	144:ef7eb2e8f9f7	866	/**
<>	144:ef7eb2e8f9f7	867	* @}
<>	144:ef7eb2e8f9f7	868	*/
<>	144:ef7eb2e8f9f7	869	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
<>	144:ef7eb2e8f9f7	870	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
<>	144:ef7eb2e8f9f7	871
<>	144:ef7eb2e8f9f7	872
<>	144:ef7eb2e8f9f7	873	/** @defgroup TIM_DMA_Base_address DMA base address
<>	144:ef7eb2e8f9f7	874	* @{
<>	144:ef7eb2e8f9f7	875	*/
<>	151:5eaa88a5bcc7	876	#define TIM_DMABASE_CR1 (0x00000000U)
<>	151:5eaa88a5bcc7	877	#define TIM_DMABASE_CR2 (0x00000001U)
<>	151:5eaa88a5bcc7	878	#define TIM_DMABASE_SMCR (0x00000002U)
<>	151:5eaa88a5bcc7	879	#define TIM_DMABASE_DIER (0x00000003U)
<>	151:5eaa88a5bcc7	880	#define TIM_DMABASE_SR (0x00000004U)
<>	151:5eaa88a5bcc7	881	#define TIM_DMABASE_EGR (0x00000005U)
<>	151:5eaa88a5bcc7	882	#define TIM_DMABASE_CCMR1 (0x00000006U)
<>	151:5eaa88a5bcc7	883	#define TIM_DMABASE_CCMR2 (0x00000007U)
<>	151:5eaa88a5bcc7	884	#define TIM_DMABASE_CCER (0x00000008U)
<>	151:5eaa88a5bcc7	885	#define TIM_DMABASE_CNT (0x00000009U)
<>	151:5eaa88a5bcc7	886	#define TIM_DMABASE_PSC (0x0000000AU)
<>	151:5eaa88a5bcc7	887	#define TIM_DMABASE_ARR (0x0000000BU)
<>	151:5eaa88a5bcc7	888	#define TIM_DMABASE_CCR1 (0x0000000DU)
<>	151:5eaa88a5bcc7	889	#define TIM_DMABASE_CCR2 (0x0000000EU)
<>	151:5eaa88a5bcc7	890	#define TIM_DMABASE_CCR3 (0x0000000FU)
<>	151:5eaa88a5bcc7	891	#define TIM_DMABASE_CCR4 (0x00000010U)
<>	151:5eaa88a5bcc7	892	#define TIM_DMABASE_DCR (0x00000012U)
<>	151:5eaa88a5bcc7	893	#define TIM_DMABASE_OR (0x00000013U)
<>	144:ef7eb2e8f9f7	894	/**
<>	144:ef7eb2e8f9f7	895	* @}
<>	144:ef7eb2e8f9f7	896	*/
<>	144:ef7eb2e8f9f7	897	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
<>	144:ef7eb2e8f9f7	898	((__BASE__) == TIM_DMABASE_CR2) \|\| \
<>	144:ef7eb2e8f9f7	899	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
<>	144:ef7eb2e8f9f7	900	((__BASE__) == TIM_DMABASE_DIER) \|\| \
<>	144:ef7eb2e8f9f7	901	((__BASE__) == TIM_DMABASE_SR) \|\| \
<>	144:ef7eb2e8f9f7	902	((__BASE__) == TIM_DMABASE_EGR) \|\| \
<>	144:ef7eb2e8f9f7	903	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
<>	144:ef7eb2e8f9f7	904	((__BASE__) == TIM_DMABASE_CCMR2 ) \|\| \
<>	144:ef7eb2e8f9f7	905	((__BASE__) == TIM_DMABASE_CCER) \|\| \
<>	144:ef7eb2e8f9f7	906	((__BASE__) == TIM_DMABASE_CNT) \|\| \
<>	144:ef7eb2e8f9f7	907	((__BASE__) == TIM_DMABASE_PSC) \|\| \
<>	144:ef7eb2e8f9f7	908	((__BASE__) == TIM_DMABASE_ARR) \|\| \
<>	144:ef7eb2e8f9f7	909	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
<>	144:ef7eb2e8f9f7	910	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
<>	144:ef7eb2e8f9f7	911	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
<>	144:ef7eb2e8f9f7	912	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
<>	144:ef7eb2e8f9f7	913	((__BASE__) == TIM_DMABASE_DCR) \|\| \
<>	144:ef7eb2e8f9f7	914	((__BASE__) == TIM_DMABASE_OR))
<>	144:ef7eb2e8f9f7	915
<>	144:ef7eb2e8f9f7	916
<>	144:ef7eb2e8f9f7	917	/** @defgroup TIM_DMA_Burst_Length DMA burst length
<>	144:ef7eb2e8f9f7	918	* @{
<>	144:ef7eb2e8f9f7	919	*/
<>	151:5eaa88a5bcc7	920	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
<>	151:5eaa88a5bcc7	921	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
<>	151:5eaa88a5bcc7	922	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
<>	151:5eaa88a5bcc7	923	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
<>	151:5eaa88a5bcc7	924	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
<>	151:5eaa88a5bcc7	925	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
<>	151:5eaa88a5bcc7	926	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
<>	151:5eaa88a5bcc7	927	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
<>	151:5eaa88a5bcc7	928	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
<>	151:5eaa88a5bcc7	929	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
<>	151:5eaa88a5bcc7	930	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
<>	151:5eaa88a5bcc7	931	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
<>	151:5eaa88a5bcc7	932	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
<>	151:5eaa88a5bcc7	933	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
<>	151:5eaa88a5bcc7	934	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
<>	151:5eaa88a5bcc7	935	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
<>	151:5eaa88a5bcc7	936	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
<>	151:5eaa88a5bcc7	937	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
<>	144:ef7eb2e8f9f7	938	/**
<>	144:ef7eb2e8f9f7	939	* @}
<>	144:ef7eb2e8f9f7	940	*/
<>	144:ef7eb2e8f9f7	941	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) \|\| \
<>	144:ef7eb2e8f9f7	942	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	943	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	944	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	945	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	946	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	947	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	948	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	949	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) \|\| \
<>	144:ef7eb2e8f9f7	950	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	951	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) \|\| \
<>	144:ef7eb2e8f9f7	952	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	953	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	954	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	955	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	956	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	957	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
<>	144:ef7eb2e8f9f7	958	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
<>	144:ef7eb2e8f9f7	959
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	/* Check IC filter */
<>	151:5eaa88a5bcc7	962	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
<>	144:ef7eb2e8f9f7	963
<>	144:ef7eb2e8f9f7	964	/** @defgroup DMA_Handle_index DMA handle index
<>	144:ef7eb2e8f9f7	965	* @{
<>	144:ef7eb2e8f9f7	966	*/
<>	151:5eaa88a5bcc7	967	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /!< Index of the DMA handle used for Update DMA requests /
<>	151:5eaa88a5bcc7	968	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
<>	151:5eaa88a5bcc7	969	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
<>	151:5eaa88a5bcc7	970	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
<>	151:5eaa88a5bcc7	971	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
<>	151:5eaa88a5bcc7	972	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /!< Index of the DMA handle used for Trigger DMA requests /
<>	144:ef7eb2e8f9f7	973	/**
<>	144:ef7eb2e8f9f7	974	* @}
<>	144:ef7eb2e8f9f7	975	*/
<>	144:ef7eb2e8f9f7	976
<>	144:ef7eb2e8f9f7	977	/** @defgroup Channel_CC_State Channel state
<>	144:ef7eb2e8f9f7	978	* @{
<>	144:ef7eb2e8f9f7	979	*/
<>	151:5eaa88a5bcc7	980	#define TIM_CCx_ENABLE ((uint32_t)0x0001U)
<>	151:5eaa88a5bcc7	981	#define TIM_CCx_DISABLE ((uint32_t)0x0000U)
<>	144:ef7eb2e8f9f7	982	/**
<>	144:ef7eb2e8f9f7	983	* @}
<>	144:ef7eb2e8f9f7	984	*/
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/**
<>	144:ef7eb2e8f9f7	987	* @}
<>	144:ef7eb2e8f9f7	988	*/
<>	144:ef7eb2e8f9f7	989
<>	144:ef7eb2e8f9f7	990	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	991	/** @defgroup TIM_Exported_Macro TIM Exported Macro
<>	144:ef7eb2e8f9f7	992	* @{
<>	144:ef7eb2e8f9f7	993	*/
<>	144:ef7eb2e8f9f7	994
<>	144:ef7eb2e8f9f7	995	/** @brief Reset UART handle state
<>	144:ef7eb2e8f9f7	996	* @param __HANDLE__ : TIM handle
<>	144:ef7eb2e8f9f7	997	* @retval None
<>	144:ef7eb2e8f9f7	998	*/
<>	144:ef7eb2e8f9f7	999	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	1000
<>	144:ef7eb2e8f9f7	1001	/**
<>	144:ef7eb2e8f9f7	1002	* @brief Enable the TIM peripheral.
<>	144:ef7eb2e8f9f7	1003	* @param __HANDLE__ : TIM handle
<>	144:ef7eb2e8f9f7	1004	* @retval None
<>	144:ef7eb2e8f9f7	1005	*/
<>	144:ef7eb2e8f9f7	1006	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/* The counter of a timer instance is disabled only if all the CCx channels have
<>	144:ef7eb2e8f9f7	1009	been disabled */
<>	144:ef7eb2e8f9f7	1010	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
<>	144:ef7eb2e8f9f7	1011
<>	144:ef7eb2e8f9f7	1012	/**
<>	144:ef7eb2e8f9f7	1013	* @brief Disable the TIM peripheral.
<>	144:ef7eb2e8f9f7	1014	* @param __HANDLE__ : TIM handle
<>	144:ef7eb2e8f9f7	1015	* @retval None
<>	144:ef7eb2e8f9f7	1016	*/
<>	144:ef7eb2e8f9f7	1017	#define __HAL_TIM_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1018	do { \
<>	151:5eaa88a5bcc7	1019	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \
<>	144:ef7eb2e8f9f7	1020	{ \
<>	144:ef7eb2e8f9f7	1021	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
<>	144:ef7eb2e8f9f7	1022	} \
<>	144:ef7eb2e8f9f7	1023	} while(0)
<>	144:ef7eb2e8f9f7	1024
<>	144:ef7eb2e8f9f7	1025	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1026	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
<>	144:ef7eb2e8f9f7	1027	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1028	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
<>	144:ef7eb2e8f9f7	1029	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	1030	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
<>	144:ef7eb2e8f9f7	1031
<>	144:ef7eb2e8f9f7	1032	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<>	144:ef7eb2e8f9f7	1033	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
<>	144:ef7eb2e8f9f7	1036	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
<>	144:ef7eb2e8f9f7	1037
<>	144:ef7eb2e8f9f7	1038	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1039	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
<>	151:5eaa88a5bcc7	1040	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8U)) :\
<>	144:ef7eb2e8f9f7	1041	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
<>	144:ef7eb2e8f9f7	1042	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
<>	144:ef7eb2e8f9f7	1043
<>	144:ef7eb2e8f9f7	1044	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1045	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
<>	144:ef7eb2e8f9f7	1046	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
<>	144:ef7eb2e8f9f7	1047	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
<>	144:ef7eb2e8f9f7	1048	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1051	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
<>	151:5eaa88a5bcc7	1052	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4U)) :\
<>	151:5eaa88a5bcc7	1053	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8U)) :\
<>	151:5eaa88a5bcc7	1054	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12U) & TIM_CCER_CC4P)))
<>	144:ef7eb2e8f9f7	1055
<>	144:ef7eb2e8f9f7	1056	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1057	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
<>	144:ef7eb2e8f9f7	1058	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
<>	144:ef7eb2e8f9f7	1059	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
<>	144:ef7eb2e8f9f7	1060	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
<>	144:ef7eb2e8f9f7	1061
<>	144:ef7eb2e8f9f7	1062	/**
<>	144:ef7eb2e8f9f7	1063	* @brief Sets the TIM Capture Compare Register value on runtime without
<>	144:ef7eb2e8f9f7	1064	* calling another time ConfigChannel function.
<>	144:ef7eb2e8f9f7	1065	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1066	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1067	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1068	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1069	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1070	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1071	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1072	* @param __COMPARE__: specifies the Capture Compare register new value.
<>	144:ef7eb2e8f9f7	1073	* @retval None
<>	144:ef7eb2e8f9f7	1074	*/
<>	144:ef7eb2e8f9f7	1075	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
<>	151:5eaa88a5bcc7	1076	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__))
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	/**
<>	144:ef7eb2e8f9f7	1079	* @brief Gets the TIM Capture Compare Register value on runtime
<>	144:ef7eb2e8f9f7	1080	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1081	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
<>	144:ef7eb2e8f9f7	1082	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1083	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
<>	144:ef7eb2e8f9f7	1084	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
<>	144:ef7eb2e8f9f7	1085	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
<>	144:ef7eb2e8f9f7	1086	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
<>	144:ef7eb2e8f9f7	1087	* @retval None
<>	144:ef7eb2e8f9f7	1088	*/
<>	144:ef7eb2e8f9f7	1089	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
<>	151:5eaa88a5bcc7	1090	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)))
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	/**
<>	144:ef7eb2e8f9f7	1093	* @brief Sets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1094	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1095	* @param __COUNTER__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1096	* @retval None
<>	144:ef7eb2e8f9f7	1097	*/
<>	144:ef7eb2e8f9f7	1098	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
<>	144:ef7eb2e8f9f7	1099
<>	144:ef7eb2e8f9f7	1100	/**
<>	144:ef7eb2e8f9f7	1101	* @brief Gets the TIM Counter Register value on runtime.
<>	144:ef7eb2e8f9f7	1102	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1103	* @retval None
<>	144:ef7eb2e8f9f7	1104	*/
<>	144:ef7eb2e8f9f7	1105	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
<>	144:ef7eb2e8f9f7	1106
<>	144:ef7eb2e8f9f7	1107	/**
<>	144:ef7eb2e8f9f7	1108	* @brief Sets the TIM Autoreload Register value on runtime without calling
<>	144:ef7eb2e8f9f7	1109	* another time any Init function.
<>	144:ef7eb2e8f9f7	1110	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1111	* @param __AUTORELOAD__: specifies the Counter register new value.
<>	144:ef7eb2e8f9f7	1112	* @retval None
<>	144:ef7eb2e8f9f7	1113	*/
<>	144:ef7eb2e8f9f7	1114	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
<>	144:ef7eb2e8f9f7	1115	do{ \
<>	144:ef7eb2e8f9f7	1116	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
<>	144:ef7eb2e8f9f7	1117	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
<>	144:ef7eb2e8f9f7	1118	} while(0)
<>	144:ef7eb2e8f9f7	1119	/**
<>	144:ef7eb2e8f9f7	1120	* @brief Gets the TIM Autoreload Register value on runtime
<>	144:ef7eb2e8f9f7	1121	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1122	* @retval None
<>	144:ef7eb2e8f9f7	1123	*/
<>	144:ef7eb2e8f9f7	1124	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
<>	144:ef7eb2e8f9f7	1125
<>	144:ef7eb2e8f9f7	1126	/**
<>	144:ef7eb2e8f9f7	1127	* @brief Sets the TIM Clock Division value on runtime without calling
<>	144:ef7eb2e8f9f7	1128	* another time any Init function.
<>	144:ef7eb2e8f9f7	1129	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1130	* @param __CKD__: specifies the clock division value.
<>	144:ef7eb2e8f9f7	1131	* This parameter can be one of the following value:
<>	144:ef7eb2e8f9f7	1132	* @arg TIM_CLOCKDIVISION_DIV1
<>	144:ef7eb2e8f9f7	1133	* @arg TIM_CLOCKDIVISION_DIV2
<>	144:ef7eb2e8f9f7	1134	* @arg TIM_CLOCKDIVISION_DIV4
<>	144:ef7eb2e8f9f7	1135	* @retval None
<>	144:ef7eb2e8f9f7	1136	*/
<>	144:ef7eb2e8f9f7	1137	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
<>	144:ef7eb2e8f9f7	1138	do{ \
<>	144:ef7eb2e8f9f7	1139	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
<>	144:ef7eb2e8f9f7	1140	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
<>	144:ef7eb2e8f9f7	1141	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
<>	144:ef7eb2e8f9f7	1142	} while(0)
<>	144:ef7eb2e8f9f7	1143	/**
<>	144:ef7eb2e8f9f7	1144	* @brief Gets the TIM Clock Division value on runtime
<>	144:ef7eb2e8f9f7	1145	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1146	* @retval None
<>	144:ef7eb2e8f9f7	1147	*/
<>	144:ef7eb2e8f9f7	1148	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
<>	144:ef7eb2e8f9f7	1149
<>	144:ef7eb2e8f9f7	1150	/**
<>	144:ef7eb2e8f9f7	1151	* @brief Sets the TIM Input Capture prescaler on runtime without calling
<>	144:ef7eb2e8f9f7	1152	* another time HAL_TIM_IC_ConfigChannel() function.
<>	144:ef7eb2e8f9f7	1153	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1154	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1155	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1156	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1157	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1158	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1159	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1160	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
<>	144:ef7eb2e8f9f7	1161	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1162	* @arg TIM_ICPSC_DIV1: no prescaler
<>	144:ef7eb2e8f9f7	1163	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
<>	144:ef7eb2e8f9f7	1164	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
<>	144:ef7eb2e8f9f7	1165	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
<>	144:ef7eb2e8f9f7	1166	* @retval None
<>	144:ef7eb2e8f9f7	1167	*/
<>	144:ef7eb2e8f9f7	1168	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
<>	144:ef7eb2e8f9f7	1169	do{ \
<>	144:ef7eb2e8f9f7	1170	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1171	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
<>	144:ef7eb2e8f9f7	1172	} while(0)
<>	144:ef7eb2e8f9f7	1173
<>	144:ef7eb2e8f9f7	1174	/**
<>	144:ef7eb2e8f9f7	1175	* @brief Gets the TIM Input Capture prescaler on runtime
<>	144:ef7eb2e8f9f7	1176	* @param __HANDLE__ : TIM handle.
<>	144:ef7eb2e8f9f7	1177	* @param __CHANNEL__ : TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1178	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1179	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
<>	144:ef7eb2e8f9f7	1180	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
<>	144:ef7eb2e8f9f7	1181	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
<>	144:ef7eb2e8f9f7	1182	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
<>	144:ef7eb2e8f9f7	1183	* @retval None
<>	144:ef7eb2e8f9f7	1184	*/
<>	144:ef7eb2e8f9f7	1185	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
<>	144:ef7eb2e8f9f7	1186	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
<>	144:ef7eb2e8f9f7	1187	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
<>	144:ef7eb2e8f9f7	1188	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
<>	151:5eaa88a5bcc7	1189	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191
<>	144:ef7eb2e8f9f7	1192	/**
<>	144:ef7eb2e8f9f7	1193	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1194	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1195	* @note When the URS bit of the TIMx_CR1 register is set, only counter
<>	144:ef7eb2e8f9f7	1196	* overflow/underflow generates an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1197	* enabled)
<>	144:ef7eb2e8f9f7	1198	* @retval None
<>	144:ef7eb2e8f9f7	1199	*/
<>	144:ef7eb2e8f9f7	1200	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1201	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1202
<>	144:ef7eb2e8f9f7	1203	/**
<>	144:ef7eb2e8f9f7	1204	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
<>	144:ef7eb2e8f9f7	1205	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1206	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
<>	144:ef7eb2e8f9f7	1207	* following events generate an update interrupt or DMA request (if
<>	144:ef7eb2e8f9f7	1208	* enabled):
<>	144:ef7eb2e8f9f7	1209	* Counter overflow/underflow
<>	144:ef7eb2e8f9f7	1210	* Setting the UG bit
<>	144:ef7eb2e8f9f7	1211	* Update generation through the slave mode controller
<>	144:ef7eb2e8f9f7	1212	* @retval None
<>	144:ef7eb2e8f9f7	1213	*/
<>	144:ef7eb2e8f9f7	1214	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	1215	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
<>	144:ef7eb2e8f9f7	1216
<>	144:ef7eb2e8f9f7	1217	/**
<>	144:ef7eb2e8f9f7	1218	* @brief Sets the TIM Capture x input polarity on runtime.
<>	144:ef7eb2e8f9f7	1219	* @param __HANDLE__: TIM handle.
<>	144:ef7eb2e8f9f7	1220	* @param __CHANNEL__: TIM Channels to be configured.
<>	144:ef7eb2e8f9f7	1221	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1222	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1223	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1224	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1225	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1226	* @param __POLARITY__: Polarity for TIx source
<>	144:ef7eb2e8f9f7	1227	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
<>	144:ef7eb2e8f9f7	1228	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
<>	144:ef7eb2e8f9f7	1229	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
<>	144:ef7eb2e8f9f7	1230	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
<>	144:ef7eb2e8f9f7	1231	* @retval None
<>	144:ef7eb2e8f9f7	1232	*/
<>	144:ef7eb2e8f9f7	1233	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
<>	144:ef7eb2e8f9f7	1234	do{ \
<>	144:ef7eb2e8f9f7	1235	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
<>	144:ef7eb2e8f9f7	1236	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
<>	144:ef7eb2e8f9f7	1237	}while(0)
<>	144:ef7eb2e8f9f7	1238
<>	144:ef7eb2e8f9f7	1239	/**
<>	144:ef7eb2e8f9f7	1240	* @}
<>	144:ef7eb2e8f9f7	1241	*/
<>	144:ef7eb2e8f9f7	1242
<>	144:ef7eb2e8f9f7	1243	/* Include TIM HAL Extension module */
<>	144:ef7eb2e8f9f7	1244	#include "stm32l0xx_hal_tim_ex.h"
<>	144:ef7eb2e8f9f7	1245
<>	144:ef7eb2e8f9f7	1246	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1247	/** @defgroup TIM_Exported_Functions TIM Exported Functions
<>	144:ef7eb2e8f9f7	1248	* @{
<>	144:ef7eb2e8f9f7	1249	*/
<>	144:ef7eb2e8f9f7	1250
<>	144:ef7eb2e8f9f7	1251	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1252	/* Time Base functions ********************************************************/
<>	144:ef7eb2e8f9f7	1253
<>	144:ef7eb2e8f9f7	1254	/** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
<>	144:ef7eb2e8f9f7	1255	* @brief Time Base functions
<>	144:ef7eb2e8f9f7	1256	* @{
<>	144:ef7eb2e8f9f7	1257	*/
<>	144:ef7eb2e8f9f7	1258	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1259	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1260	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1261	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1262	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1263	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1264	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1265	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1266	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1267	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1268	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1269	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1270	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1271
<>	144:ef7eb2e8f9f7	1272	/**
<>	144:ef7eb2e8f9f7	1273	* @}
<>	144:ef7eb2e8f9f7	1274	*/
<>	144:ef7eb2e8f9f7	1275
<>	144:ef7eb2e8f9f7	1276
<>	144:ef7eb2e8f9f7	1277	/* Timer Output Compare functions **********************************************/
<>	144:ef7eb2e8f9f7	1278
<>	144:ef7eb2e8f9f7	1279	/** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
<>	144:ef7eb2e8f9f7	1280	* @brief Timer Output Compare functions
<>	144:ef7eb2e8f9f7	1281	* @{
<>	144:ef7eb2e8f9f7	1282	*/
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1285	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1286	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1287	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1288	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1289	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1290	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1291	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1292	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1293	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1294	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1295	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1296	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1297	/**
<>	144:ef7eb2e8f9f7	1298	* @}
<>	144:ef7eb2e8f9f7	1299	*/
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	/* Timer PWM functions *********************************************************/
<>	144:ef7eb2e8f9f7	1303
<>	144:ef7eb2e8f9f7	1304	/** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
<>	144:ef7eb2e8f9f7	1305	* @brief Timer PWM functions
<>	144:ef7eb2e8f9f7	1306	* @{
<>	144:ef7eb2e8f9f7	1307	*/
<>	144:ef7eb2e8f9f7	1308	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1309	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1310	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1311	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1312	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1313	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1314	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1315	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1316	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1317	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1318	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1319	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1320	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1321	/**
<>	144:ef7eb2e8f9f7	1322	* @}
<>	144:ef7eb2e8f9f7	1323	*/
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	/* Timer Input Capture functions ***********************************************/
<>	144:ef7eb2e8f9f7	1326
<>	144:ef7eb2e8f9f7	1327	/** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
<>	144:ef7eb2e8f9f7	1328	* @brief Timer Input Capture functions
<>	144:ef7eb2e8f9f7	1329	* @{
<>	144:ef7eb2e8f9f7	1330	*/
<>	144:ef7eb2e8f9f7	1331	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1332	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1333	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1334	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1335	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1336	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1337	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1338	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1339	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1340	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1341	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1342	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
<>	144:ef7eb2e8f9f7	1343	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1344	/**
<>	144:ef7eb2e8f9f7	1345	* @}
<>	144:ef7eb2e8f9f7	1346	*/
<>	144:ef7eb2e8f9f7	1347
<>	144:ef7eb2e8f9f7	1348	/* Timer One Pulse functions ***************************************************/
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
<>	144:ef7eb2e8f9f7	1351	* @brief Timer One Pulse functions
<>	144:ef7eb2e8f9f7	1352	* @{
<>	144:ef7eb2e8f9f7	1353	*/
<>	144:ef7eb2e8f9f7	1354	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
<>	144:ef7eb2e8f9f7	1355	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1356	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1357	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1358	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1359	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1360	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1361
<>	144:ef7eb2e8f9f7	1362	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1363	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1364	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
<>	144:ef7eb2e8f9f7	1365
<>	144:ef7eb2e8f9f7	1366	/**
<>	144:ef7eb2e8f9f7	1367	* @}
<>	144:ef7eb2e8f9f7	1368	*/
<>	144:ef7eb2e8f9f7	1369
<>	144:ef7eb2e8f9f7	1370	/* Timer Encoder functions *****************************************************/
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
<>	144:ef7eb2e8f9f7	1373	* @brief Timer Encoder functions
<>	144:ef7eb2e8f9f7	1374	* @{
<>	144:ef7eb2e8f9f7	1375	*/
<>	144:ef7eb2e8f9f7	1376	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
<>	144:ef7eb2e8f9f7	1377	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1378	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1379	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1380	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1381	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1382	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1383	/* Non-Blocking mode: Interrupt */
<>	144:ef7eb2e8f9f7	1384	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1385	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1386	/* Non-Blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1387	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
<>	144:ef7eb2e8f9f7	1388	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1389
<>	144:ef7eb2e8f9f7	1390	/**
<>	144:ef7eb2e8f9f7	1391	* @}
<>	144:ef7eb2e8f9f7	1392	*/
<>	144:ef7eb2e8f9f7	1393
<>	144:ef7eb2e8f9f7	1394	/* Interrupt Handler functions **********************************************/
<>	144:ef7eb2e8f9f7	1395
<>	144:ef7eb2e8f9f7	1396	/** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
<>	144:ef7eb2e8f9f7	1397	* @brief Interrupt Handler functions
<>	144:ef7eb2e8f9f7	1398	* @{
<>	144:ef7eb2e8f9f7	1399	*/
<>	144:ef7eb2e8f9f7	1400	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1401	/**
<>	144:ef7eb2e8f9f7	1402	* @}
<>	144:ef7eb2e8f9f7	1403	*/
<>	144:ef7eb2e8f9f7	1404
<>	144:ef7eb2e8f9f7	1405	/* Control functions *********************************************************/
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1408	* @brief Control functions
<>	144:ef7eb2e8f9f7	1409	* @{
<>	144:ef7eb2e8f9f7	1410	*/
<>	144:ef7eb2e8f9f7	1411	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1412	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1413	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1414	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
<>	144:ef7eb2e8f9f7	1415	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1416	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
<>	144:ef7eb2e8f9f7	1417	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
<>	144:ef7eb2e8f9f7	1418	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1419	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
<>	144:ef7eb2e8f9f7	1420	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1421	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1422	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1423	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
<>	144:ef7eb2e8f9f7	1424	uint32_t *BurstBuffer, uint32_t BurstLength);
<>	144:ef7eb2e8f9f7	1425	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
<>	144:ef7eb2e8f9f7	1426	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
<>	144:ef7eb2e8f9f7	1427	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	/**
<>	144:ef7eb2e8f9f7	1430	* @}
<>	144:ef7eb2e8f9f7	1431	*/
<>	144:ef7eb2e8f9f7	1432
<>	144:ef7eb2e8f9f7	1433	/* Callback in non blocking modes (Interrupt and DMA) *************************/
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
<>	144:ef7eb2e8f9f7	1436	* @brief Callback functions
<>	144:ef7eb2e8f9f7	1437	* @{
<>	144:ef7eb2e8f9f7	1438	*/
<>	144:ef7eb2e8f9f7	1439	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1440	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1441	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1442	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1443	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1444	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1445	/**
<>	144:ef7eb2e8f9f7	1446	* @}
<>	144:ef7eb2e8f9f7	1447	*/
<>	144:ef7eb2e8f9f7	1448
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/* Peripheral State functions **************************************************/
<>	144:ef7eb2e8f9f7	1451
<>	144:ef7eb2e8f9f7	1452	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
<>	144:ef7eb2e8f9f7	1453	* @brief Peripheral State functions
<>	144:ef7eb2e8f9f7	1454	* @{
<>	144:ef7eb2e8f9f7	1455	*/
<>	144:ef7eb2e8f9f7	1456	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1457	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1458	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1459	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1460	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1461	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
<>	144:ef7eb2e8f9f7	1462	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1463	void TIM_DMAError(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1464	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
<>	144:ef7eb2e8f9f7	1465
<>	144:ef7eb2e8f9f7	1466	/**
<>	144:ef7eb2e8f9f7	1467	* @}
<>	144:ef7eb2e8f9f7	1468	*/
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	/**
<>	144:ef7eb2e8f9f7	1471	* @}
<>	144:ef7eb2e8f9f7	1472	*/
<>	144:ef7eb2e8f9f7	1473
<>	144:ef7eb2e8f9f7	1474	/* Define the private group ***********************************/
<>	144:ef7eb2e8f9f7	1475	/**************************************************************/
<>	144:ef7eb2e8f9f7	1476	/** @defgroup TIM_Private TIM Private
<>	144:ef7eb2e8f9f7	1477	* @{
<>	144:ef7eb2e8f9f7	1478	*/
<>	144:ef7eb2e8f9f7	1479	/**
<>	144:ef7eb2e8f9f7	1480	* @}
<>	144:ef7eb2e8f9f7	1481	*/
<>	144:ef7eb2e8f9f7	1482	/**************************************************************/
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	/**
<>	144:ef7eb2e8f9f7	1485	* @}
<>	144:ef7eb2e8f9f7	1486	*/
<>	144:ef7eb2e8f9f7	1487
<>	144:ef7eb2e8f9f7	1488	/**
<>	144:ef7eb2e8f9f7	1489	* @}
<>	144:ef7eb2e8f9f7	1490	*/
<>	144:ef7eb2e8f9f7	1491
<>	144:ef7eb2e8f9f7	1492	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1493	}
<>	144:ef7eb2e8f9f7	1494	#endif
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	#endif /* __STM32L0xx_HAL_TIM_H */
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	1499