mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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cmsis/TARGET_CORTEX_A/irq_ctrl_gic.c@186:707f6e361f3e, 2018-06-22 (annotated)

Committer:
Anna Bridge
Date:
Fri Jun 22 16:45:37 2018 +0100
Revision:
186:707f6e361f3e
Parent:
180:96ed750bd169 
mbed-dev library. Release version 162

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 180:96ed750bd169 1 /**************************************************************************//**
Anna Bridge 180:96ed750bd169 2 * @file irq_ctrl_gic.c
Anna Bridge 180:96ed750bd169 3 * @brief Interrupt controller handling implementation for GIC
Anna Bridge 186:707f6e361f3e 4 * @version V1.0.1
Anna Bridge 186:707f6e361f3e 5 * @date 9. April 2018
Anna Bridge 180:96ed750bd169 6 ******************************************************************************/
Anna Bridge 180:96ed750bd169 7 /*
Anna Bridge 180:96ed750bd169 8 * Copyright (c) 2017 ARM Limited. All rights reserved.
Anna Bridge 180:96ed750bd169 9 *
Anna Bridge 180:96ed750bd169 10 * SPDX-License-Identifier: Apache-2.0
Anna Bridge 180:96ed750bd169 11 *
Anna Bridge 180:96ed750bd169 12 * Licensed under the Apache License, Version 2.0 (the License); you may
Anna Bridge 180:96ed750bd169 13 * not use this file except in compliance with the License.
Anna Bridge 180:96ed750bd169 14 * You may obtain a copy of the License at
Anna Bridge 180:96ed750bd169 15 *
Anna Bridge 180:96ed750bd169 16 * www.apache.org/licenses/LICENSE-2.0
Anna Bridge 180:96ed750bd169 17 *
Anna Bridge 180:96ed750bd169 18 * Unless required by applicable law or agreed to in writing, software
Anna Bridge 180:96ed750bd169 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
Anna Bridge 180:96ed750bd169 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
Anna Bridge 180:96ed750bd169 21 * See the License for the specific language governing permissions and
Anna Bridge 180:96ed750bd169 22 * limitations under the License.
Anna Bridge 180:96ed750bd169 23 */
Anna Bridge 180:96ed750bd169 24
Anna Bridge 180:96ed750bd169 25 #include <stddef.h>
Anna Bridge 180:96ed750bd169 26
Anna Bridge 186:707f6e361f3e 27 #include "RTE_Components.h"
Anna Bridge 186:707f6e361f3e 28 #include CMSIS_device_header
Anna Bridge 180:96ed750bd169 29
Anna Bridge 180:96ed750bd169 30 #include "irq_ctrl.h"
Anna Bridge 180:96ed750bd169 31
Anna Bridge 180:96ed750bd169 32 #if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
Anna Bridge 180:96ed750bd169 33
Anna Bridge 180:96ed750bd169 34 /// Number of implemented interrupt lines
Anna Bridge 180:96ed750bd169 35 #ifndef IRQ_GIC_LINE_COUNT
Anna Bridge 180:96ed750bd169 36 #define IRQ_GIC_LINE_COUNT (1020U)
Anna Bridge 180:96ed750bd169 37 #endif
Anna Bridge 180:96ed750bd169 38
Anna Bridge 180:96ed750bd169 39 static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
Anna Bridge 186:707f6e361f3e 40 static uint32_t IRQ_ID0;
Anna Bridge 180:96ed750bd169 41
Anna Bridge 180:96ed750bd169 42 /// Initialize interrupt controller.
Anna Bridge 180:96ed750bd169 43 __WEAK int32_t IRQ_Initialize (void) {
Anna Bridge 180:96ed750bd169 44 uint32_t i;
Anna Bridge 180:96ed750bd169 45
Anna Bridge 180:96ed750bd169 46 for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
Anna Bridge 180:96ed750bd169 47 IRQTable[i] = (IRQHandler_t)NULL;
Anna Bridge 180:96ed750bd169 48 }
Anna Bridge 180:96ed750bd169 49 GIC_Enable();
Anna Bridge 180:96ed750bd169 50 return (0);
Anna Bridge 180:96ed750bd169 51 }
Anna Bridge 180:96ed750bd169 52
Anna Bridge 180:96ed750bd169 53
Anna Bridge 180:96ed750bd169 54 /// Register interrupt handler.
Anna Bridge 180:96ed750bd169 55 __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
Anna Bridge 180:96ed750bd169 56 int32_t status;
Anna Bridge 180:96ed750bd169 57
Anna Bridge 180:96ed750bd169 58 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 59 IRQTable[irqn] = handler;
Anna Bridge 180:96ed750bd169 60 status = 0;
Anna Bridge 180:96ed750bd169 61 } else {
Anna Bridge 180:96ed750bd169 62 status = -1;
Anna Bridge 180:96ed750bd169 63 }
Anna Bridge 180:96ed750bd169 64
Anna Bridge 180:96ed750bd169 65 return (status);
Anna Bridge 180:96ed750bd169 66 }
Anna Bridge 180:96ed750bd169 67
Anna Bridge 180:96ed750bd169 68
Anna Bridge 180:96ed750bd169 69 /// Get the registered interrupt handler.
Anna Bridge 180:96ed750bd169 70 __WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 71 IRQHandler_t h;
Anna Bridge 180:96ed750bd169 72
Anna Bridge 186:707f6e361f3e 73 // Ignore CPUID field (software generated interrupts)
Anna Bridge 186:707f6e361f3e 74 irqn &= 0x3FFU;
Anna Bridge 186:707f6e361f3e 75
Anna Bridge 180:96ed750bd169 76 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 77 h = IRQTable[irqn];
Anna Bridge 180:96ed750bd169 78 } else {
Anna Bridge 180:96ed750bd169 79 h = (IRQHandler_t)0;
Anna Bridge 180:96ed750bd169 80 }
Anna Bridge 180:96ed750bd169 81
Anna Bridge 180:96ed750bd169 82 return (h);
Anna Bridge 180:96ed750bd169 83 }
Anna Bridge 180:96ed750bd169 84
Anna Bridge 180:96ed750bd169 85
Anna Bridge 180:96ed750bd169 86 /// Enable interrupt.
Anna Bridge 180:96ed750bd169 87 __WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 88 int32_t status;
Anna Bridge 180:96ed750bd169 89
Anna Bridge 180:96ed750bd169 90 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 91 GIC_EnableIRQ ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 92 status = 0;
Anna Bridge 180:96ed750bd169 93 } else {
Anna Bridge 180:96ed750bd169 94 status = -1;
Anna Bridge 180:96ed750bd169 95 }
Anna Bridge 180:96ed750bd169 96
Anna Bridge 180:96ed750bd169 97 return (status);
Anna Bridge 180:96ed750bd169 98 }
Anna Bridge 180:96ed750bd169 99
Anna Bridge 180:96ed750bd169 100
Anna Bridge 180:96ed750bd169 101 /// Disable interrupt.
Anna Bridge 180:96ed750bd169 102 __WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 103 int32_t status;
Anna Bridge 180:96ed750bd169 104
Anna Bridge 180:96ed750bd169 105 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 106 GIC_DisableIRQ ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 107 status = 0;
Anna Bridge 180:96ed750bd169 108 } else {
Anna Bridge 180:96ed750bd169 109 status = -1;
Anna Bridge 180:96ed750bd169 110 }
Anna Bridge 180:96ed750bd169 111
Anna Bridge 180:96ed750bd169 112 return (status);
Anna Bridge 180:96ed750bd169 113 }
Anna Bridge 180:96ed750bd169 114
Anna Bridge 180:96ed750bd169 115
Anna Bridge 180:96ed750bd169 116 /// Get interrupt enable state.
Anna Bridge 180:96ed750bd169 117 __WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 118 uint32_t enable;
Anna Bridge 180:96ed750bd169 119
Anna Bridge 180:96ed750bd169 120 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 121 enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 122 } else {
Anna Bridge 180:96ed750bd169 123 enable = 0U;
Anna Bridge 180:96ed750bd169 124 }
Anna Bridge 180:96ed750bd169 125
Anna Bridge 180:96ed750bd169 126 return (enable);
Anna Bridge 180:96ed750bd169 127 }
Anna Bridge 180:96ed750bd169 128
Anna Bridge 180:96ed750bd169 129
Anna Bridge 180:96ed750bd169 130 /// Configure interrupt request mode.
Anna Bridge 180:96ed750bd169 131 __WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
Anna Bridge 180:96ed750bd169 132 uint32_t val;
Anna Bridge 180:96ed750bd169 133 uint8_t cfg;
Anna Bridge 180:96ed750bd169 134 uint8_t secure;
Anna Bridge 180:96ed750bd169 135 uint8_t cpu;
Anna Bridge 186:707f6e361f3e 136 int32_t status = 0;
Anna Bridge 180:96ed750bd169 137
Anna Bridge 180:96ed750bd169 138 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 139 // Check triggering mode
Anna Bridge 180:96ed750bd169 140 val = (mode & IRQ_MODE_TRIG_Msk);
Anna Bridge 180:96ed750bd169 141
Anna Bridge 180:96ed750bd169 142 if (val == IRQ_MODE_TRIG_LEVEL) {
Anna Bridge 180:96ed750bd169 143 cfg = 0x00U;
Anna Bridge 180:96ed750bd169 144 } else if (val == IRQ_MODE_TRIG_EDGE) {
Anna Bridge 180:96ed750bd169 145 cfg = 0x02U;
Anna Bridge 180:96ed750bd169 146 } else {
Anna Bridge 186:707f6e361f3e 147 cfg = 0x00U;
Anna Bridge 180:96ed750bd169 148 status = -1;
Anna Bridge 180:96ed750bd169 149 }
Anna Bridge 180:96ed750bd169 150
Anna Bridge 180:96ed750bd169 151 // Check interrupt type
Anna Bridge 180:96ed750bd169 152 val = mode & IRQ_MODE_TYPE_Msk;
Anna Bridge 180:96ed750bd169 153
Anna Bridge 180:96ed750bd169 154 if (val != IRQ_MODE_TYPE_IRQ) {
Anna Bridge 180:96ed750bd169 155 status = -1;
Anna Bridge 180:96ed750bd169 156 }
Anna Bridge 180:96ed750bd169 157
Anna Bridge 180:96ed750bd169 158 // Check interrupt domain
Anna Bridge 180:96ed750bd169 159 val = mode & IRQ_MODE_DOMAIN_Msk;
Anna Bridge 180:96ed750bd169 160
Anna Bridge 180:96ed750bd169 161 if (val == IRQ_MODE_DOMAIN_NONSECURE) {
Anna Bridge 186:707f6e361f3e 162 secure = 0U;
Anna Bridge 180:96ed750bd169 163 } else {
Anna Bridge 180:96ed750bd169 164 // Check security extensions support
Anna Bridge 180:96ed750bd169 165 val = GIC_DistributorInfo() & (1UL << 10U);
Anna Bridge 180:96ed750bd169 166
Anna Bridge 180:96ed750bd169 167 if (val != 0U) {
Anna Bridge 180:96ed750bd169 168 // Security extensions are supported
Anna Bridge 186:707f6e361f3e 169 secure = 1U;
Anna Bridge 180:96ed750bd169 170 } else {
Anna Bridge 186:707f6e361f3e 171 secure = 0U;
Anna Bridge 180:96ed750bd169 172 status = -1;
Anna Bridge 180:96ed750bd169 173 }
Anna Bridge 180:96ed750bd169 174 }
Anna Bridge 180:96ed750bd169 175
Anna Bridge 180:96ed750bd169 176 // Check interrupt CPU targets
Anna Bridge 180:96ed750bd169 177 val = mode & IRQ_MODE_CPU_Msk;
Anna Bridge 180:96ed750bd169 178
Anna Bridge 180:96ed750bd169 179 if (val == IRQ_MODE_CPU_ALL) {
Anna Bridge 186:707f6e361f3e 180 cpu = 0xFFU;
Anna Bridge 180:96ed750bd169 181 } else {
Anna Bridge 180:96ed750bd169 182 cpu = val >> IRQ_MODE_CPU_Pos;
Anna Bridge 180:96ed750bd169 183 }
Anna Bridge 180:96ed750bd169 184
Anna Bridge 180:96ed750bd169 185 // Apply configuration if no mode error
Anna Bridge 180:96ed750bd169 186 if (status == 0) {
Anna Bridge 180:96ed750bd169 187 GIC_SetConfiguration((IRQn_Type)irqn, cfg);
Anna Bridge 180:96ed750bd169 188 GIC_SetTarget ((IRQn_Type)irqn, cpu);
Anna Bridge 180:96ed750bd169 189
Anna Bridge 180:96ed750bd169 190 if (secure != 0U) {
Anna Bridge 180:96ed750bd169 191 GIC_SetGroup ((IRQn_Type)irqn, secure);
Anna Bridge 180:96ed750bd169 192 }
Anna Bridge 180:96ed750bd169 193 }
Anna Bridge 180:96ed750bd169 194 }
Anna Bridge 180:96ed750bd169 195
Anna Bridge 180:96ed750bd169 196 return (status);
Anna Bridge 180:96ed750bd169 197 }
Anna Bridge 180:96ed750bd169 198
Anna Bridge 180:96ed750bd169 199
Anna Bridge 180:96ed750bd169 200 /// Get interrupt mode configuration.
Anna Bridge 180:96ed750bd169 201 __WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 202 uint32_t mode;
Anna Bridge 180:96ed750bd169 203 uint32_t val;
Anna Bridge 180:96ed750bd169 204
Anna Bridge 180:96ed750bd169 205 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 206 mode = IRQ_MODE_TYPE_IRQ;
Anna Bridge 180:96ed750bd169 207
Anna Bridge 180:96ed750bd169 208 // Get trigger mode
Anna Bridge 180:96ed750bd169 209 val = GIC_GetConfiguration((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 210
Anna Bridge 180:96ed750bd169 211 if ((val & 2U) != 0U) {
Anna Bridge 180:96ed750bd169 212 // Corresponding interrupt is edge triggered
Anna Bridge 180:96ed750bd169 213 mode |= IRQ_MODE_TRIG_EDGE;
Anna Bridge 180:96ed750bd169 214 } else {
Anna Bridge 180:96ed750bd169 215 // Corresponding interrupt is level triggered
Anna Bridge 180:96ed750bd169 216 mode |= IRQ_MODE_TRIG_LEVEL;
Anna Bridge 180:96ed750bd169 217 }
Anna Bridge 180:96ed750bd169 218
Anna Bridge 180:96ed750bd169 219 // Get interrupt CPU targets
Anna Bridge 180:96ed750bd169 220 mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
Anna Bridge 180:96ed750bd169 221
Anna Bridge 180:96ed750bd169 222 } else {
Anna Bridge 180:96ed750bd169 223 mode = IRQ_MODE_ERROR;
Anna Bridge 180:96ed750bd169 224 }
Anna Bridge 180:96ed750bd169 225
Anna Bridge 180:96ed750bd169 226 return (mode);
Anna Bridge 180:96ed750bd169 227 }
Anna Bridge 180:96ed750bd169 228
Anna Bridge 180:96ed750bd169 229
Anna Bridge 180:96ed750bd169 230 /// Get ID number of current interrupt request (IRQ).
Anna Bridge 180:96ed750bd169 231 __WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
Anna Bridge 180:96ed750bd169 232 IRQn_ID_t irqn;
Anna Bridge 180:96ed750bd169 233 uint32_t prio;
Anna Bridge 180:96ed750bd169 234
Anna Bridge 180:96ed750bd169 235 /* Dummy read to avoid GIC 390 errata 801120 */
Anna Bridge 180:96ed750bd169 236 GIC_GetHighPendingIRQ();
Anna Bridge 180:96ed750bd169 237
Anna Bridge 180:96ed750bd169 238 irqn = GIC_AcknowledgePending();
Anna Bridge 180:96ed750bd169 239
Anna Bridge 180:96ed750bd169 240 __DSB();
Anna Bridge 180:96ed750bd169 241
Anna Bridge 180:96ed750bd169 242 /* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
Anna Bridge 180:96ed750bd169 243 /* The following workaround code is for a single-core system. It would be */
Anna Bridge 180:96ed750bd169 244 /* different in a multi-core system. */
Anna Bridge 180:96ed750bd169 245 /* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
Anna Bridge 180:96ed750bd169 246 /* so unlock it, otherwise service the interrupt as normal. */
Anna Bridge 180:96ed750bd169 247 /* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
Anna Bridge 180:96ed750bd169 248 /* so will not occur here. */
Anna Bridge 180:96ed750bd169 249
Anna Bridge 180:96ed750bd169 250 if ((irqn == 0) || (irqn >= 0x3FE)) {
Anna Bridge 180:96ed750bd169 251 /* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
Anna Bridge 180:96ed750bd169 252 prio = GIC_GetPriority((IRQn_Type)0);
Anna Bridge 180:96ed750bd169 253 GIC_SetPriority ((IRQn_Type)0, prio);
Anna Bridge 180:96ed750bd169 254
Anna Bridge 180:96ed750bd169 255 __DSB();
Anna Bridge 180:96ed750bd169 256
Anna Bridge 180:96ed750bd169 257 if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
Anna Bridge 180:96ed750bd169 258 /* If the ID is 0, is active and has not been seen before */
Anna Bridge 180:96ed750bd169 259 IRQ_ID0 = 1U;
Anna Bridge 180:96ed750bd169 260 }
Anna Bridge 180:96ed750bd169 261 /* End of Workaround GIC 390 errata 733075 */
Anna Bridge 180:96ed750bd169 262 }
Anna Bridge 180:96ed750bd169 263
Anna Bridge 180:96ed750bd169 264 return (irqn);
Anna Bridge 180:96ed750bd169 265 }
Anna Bridge 180:96ed750bd169 266
Anna Bridge 180:96ed750bd169 267
Anna Bridge 180:96ed750bd169 268 /// Get ID number of current fast interrupt request (FIQ).
Anna Bridge 180:96ed750bd169 269 __WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
Anna Bridge 180:96ed750bd169 270 return ((IRQn_ID_t)-1);
Anna Bridge 180:96ed750bd169 271 }
Anna Bridge 180:96ed750bd169 272
Anna Bridge 180:96ed750bd169 273
Anna Bridge 180:96ed750bd169 274 /// Signal end of interrupt processing.
Anna Bridge 180:96ed750bd169 275 __WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 276 int32_t status;
Anna Bridge 186:707f6e361f3e 277 IRQn_Type irq = (IRQn_Type)irqn;
Anna Bridge 186:707f6e361f3e 278
Anna Bridge 186:707f6e361f3e 279 irqn &= 0x3FFU;
Anna Bridge 180:96ed750bd169 280
Anna Bridge 180:96ed750bd169 281 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 186:707f6e361f3e 282 GIC_EndInterrupt (irq);
Anna Bridge 180:96ed750bd169 283
Anna Bridge 180:96ed750bd169 284 if (irqn == 0) {
Anna Bridge 180:96ed750bd169 285 IRQ_ID0 = 0U;
Anna Bridge 180:96ed750bd169 286 }
Anna Bridge 180:96ed750bd169 287
Anna Bridge 180:96ed750bd169 288 status = 0;
Anna Bridge 180:96ed750bd169 289 } else {
Anna Bridge 180:96ed750bd169 290 status = -1;
Anna Bridge 180:96ed750bd169 291 }
Anna Bridge 180:96ed750bd169 292
Anna Bridge 180:96ed750bd169 293 return (status);
Anna Bridge 180:96ed750bd169 294 }
Anna Bridge 180:96ed750bd169 295
Anna Bridge 180:96ed750bd169 296
Anna Bridge 180:96ed750bd169 297 /// Set interrupt pending flag.
Anna Bridge 180:96ed750bd169 298 __WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 299 int32_t status;
Anna Bridge 180:96ed750bd169 300
Anna Bridge 180:96ed750bd169 301 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 302 GIC_SetPendingIRQ ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 303 status = 0;
Anna Bridge 180:96ed750bd169 304 } else {
Anna Bridge 180:96ed750bd169 305 status = -1;
Anna Bridge 180:96ed750bd169 306 }
Anna Bridge 180:96ed750bd169 307
Anna Bridge 180:96ed750bd169 308 return (status);
Anna Bridge 180:96ed750bd169 309 }
Anna Bridge 180:96ed750bd169 310
Anna Bridge 180:96ed750bd169 311 /// Get interrupt pending flag.
Anna Bridge 180:96ed750bd169 312 __WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 313 uint32_t pending;
Anna Bridge 180:96ed750bd169 314
Anna Bridge 180:96ed750bd169 315 if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 316 pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 317 } else {
Anna Bridge 180:96ed750bd169 318 pending = 0U;
Anna Bridge 180:96ed750bd169 319 }
Anna Bridge 180:96ed750bd169 320
Anna Bridge 180:96ed750bd169 321 return (pending & 1U);
Anna Bridge 180:96ed750bd169 322 }
Anna Bridge 180:96ed750bd169 323
Anna Bridge 180:96ed750bd169 324
Anna Bridge 180:96ed750bd169 325 /// Clear interrupt pending flag.
Anna Bridge 180:96ed750bd169 326 __WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 327 int32_t status;
Anna Bridge 180:96ed750bd169 328
Anna Bridge 180:96ed750bd169 329 if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 330 GIC_ClearPendingIRQ ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 331 status = 0;
Anna Bridge 180:96ed750bd169 332 } else {
Anna Bridge 180:96ed750bd169 333 status = -1;
Anna Bridge 180:96ed750bd169 334 }
Anna Bridge 180:96ed750bd169 335
Anna Bridge 180:96ed750bd169 336 return (status);
Anna Bridge 180:96ed750bd169 337 }
Anna Bridge 180:96ed750bd169 338
Anna Bridge 180:96ed750bd169 339
Anna Bridge 180:96ed750bd169 340 /// Set interrupt priority value.
Anna Bridge 180:96ed750bd169 341 __WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
Anna Bridge 180:96ed750bd169 342 int32_t status;
Anna Bridge 180:96ed750bd169 343
Anna Bridge 180:96ed750bd169 344 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 345 GIC_SetPriority ((IRQn_Type)irqn, priority);
Anna Bridge 180:96ed750bd169 346 status = 0;
Anna Bridge 180:96ed750bd169 347 } else {
Anna Bridge 180:96ed750bd169 348 status = -1;
Anna Bridge 180:96ed750bd169 349 }
Anna Bridge 180:96ed750bd169 350
Anna Bridge 180:96ed750bd169 351 return (status);
Anna Bridge 180:96ed750bd169 352 }
Anna Bridge 180:96ed750bd169 353
Anna Bridge 180:96ed750bd169 354
Anna Bridge 180:96ed750bd169 355 /// Get interrupt priority.
Anna Bridge 180:96ed750bd169 356 __WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
Anna Bridge 180:96ed750bd169 357 uint32_t priority;
Anna Bridge 180:96ed750bd169 358
Anna Bridge 180:96ed750bd169 359 if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
Anna Bridge 180:96ed750bd169 360 priority = GIC_GetPriority ((IRQn_Type)irqn);
Anna Bridge 180:96ed750bd169 361 } else {
Anna Bridge 180:96ed750bd169 362 priority = IRQ_PRIORITY_ERROR;
Anna Bridge 180:96ed750bd169 363 }
Anna Bridge 180:96ed750bd169 364
Anna Bridge 180:96ed750bd169 365 return (priority);
Anna Bridge 180:96ed750bd169 366 }
Anna Bridge 180:96ed750bd169 367
Anna Bridge 180:96ed750bd169 368
Anna Bridge 180:96ed750bd169 369 /// Set priority masking threshold.
Anna Bridge 180:96ed750bd169 370 __WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
Anna Bridge 180:96ed750bd169 371 GIC_SetInterfacePriorityMask (priority);
Anna Bridge 180:96ed750bd169 372 return (0);
Anna Bridge 180:96ed750bd169 373 }
Anna Bridge 180:96ed750bd169 374
Anna Bridge 180:96ed750bd169 375
Anna Bridge 180:96ed750bd169 376 /// Get priority masking threshold
Anna Bridge 180:96ed750bd169 377 __WEAK uint32_t IRQ_GetPriorityMask (void) {
Anna Bridge 180:96ed750bd169 378 return GIC_GetInterfacePriorityMask();
Anna Bridge 180:96ed750bd169 379 }
Anna Bridge 180:96ed750bd169 380
Anna Bridge 180:96ed750bd169 381
Anna Bridge 180:96ed750bd169 382 /// Set priority grouping field split point
Anna Bridge 180:96ed750bd169 383 __WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
Anna Bridge 180:96ed750bd169 384 int32_t status;
Anna Bridge 180:96ed750bd169 385
Anna Bridge 180:96ed750bd169 386 if (bits == IRQ_PRIORITY_Msk) {
Anna Bridge 180:96ed750bd169 387 bits = 7U;
Anna Bridge 180:96ed750bd169 388 }
Anna Bridge 180:96ed750bd169 389
Anna Bridge 180:96ed750bd169 390 if (bits < 8U) {
Anna Bridge 180:96ed750bd169 391 GIC_SetBinaryPoint (7U - bits);
Anna Bridge 180:96ed750bd169 392 status = 0;
Anna Bridge 180:96ed750bd169 393 } else {
Anna Bridge 180:96ed750bd169 394 status = -1;
Anna Bridge 180:96ed750bd169 395 }
Anna Bridge 180:96ed750bd169 396
Anna Bridge 180:96ed750bd169 397 return (status);
Anna Bridge 180:96ed750bd169 398 }
Anna Bridge 180:96ed750bd169 399
Anna Bridge 180:96ed750bd169 400
Anna Bridge 180:96ed750bd169 401 /// Get priority grouping field split point
Anna Bridge 180:96ed750bd169 402 __WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
Anna Bridge 180:96ed750bd169 403 uint32_t bp;
Anna Bridge 180:96ed750bd169 404
Anna Bridge 180:96ed750bd169 405 bp = GIC_GetBinaryPoint() & 0x07U;
Anna Bridge 180:96ed750bd169 406
Anna Bridge 180:96ed750bd169 407 return (7U - bp);
Anna Bridge 180:96ed750bd169 408 }
Anna Bridge 180:96ed750bd169 409
Anna Bridge 180:96ed750bd169 410 #endif