mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/lp_ticker.c@181:57724642e740, 2018-02-16 (annotated)

Committer:
AnnaBridge
Date:
Fri Feb 16 16:09:33 2018 +0000
Revision:
181:57724642e740
Parent:
180:96ed750bd169
Child:
186:707f6e361f3e
mbed-dev library. Release version 159.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /* mbed Microcontroller Library
<> 154:37f96f9d4de2 2 *******************************************************************************
Anna Bridge 180:96ed750bd169 3 * Copyright (c) 2017, STMicroelectronics
<> 154:37f96f9d4de2 4 * All rights reserved.
<> 154:37f96f9d4de2 5 *
<> 154:37f96f9d4de2 6 * Redistribution and use in source and binary forms, with or without
<> 154:37f96f9d4de2 7 * modification, are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 8 *
<> 154:37f96f9d4de2 9 * 1. Redistributions of source code must retain the above copyright notice,
<> 154:37f96f9d4de2 10 * this list of conditions and the following disclaimer.
<> 154:37f96f9d4de2 11 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 154:37f96f9d4de2 12 * this list of conditions and the following disclaimer in the documentation
<> 154:37f96f9d4de2 13 * and/or other materials provided with the distribution.
<> 154:37f96f9d4de2 14 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 154:37f96f9d4de2 15 * may be used to endorse or promote products derived from this software
<> 154:37f96f9d4de2 16 * without specific prior written permission.
<> 154:37f96f9d4de2 17 *
<> 154:37f96f9d4de2 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 154:37f96f9d4de2 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 154:37f96f9d4de2 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 154:37f96f9d4de2 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 154:37f96f9d4de2 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 154:37f96f9d4de2 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 154:37f96f9d4de2 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 154:37f96f9d4de2 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 154:37f96f9d4de2 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 28 *******************************************************************************
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #if DEVICE_LOWPOWERTIMER
<> 154:37f96f9d4de2 32
<> 154:37f96f9d4de2 33 #include "rtc_api_hal.h"
<> 154:37f96f9d4de2 34
AnnaBridge 181:57724642e740 35 #if MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM
AnnaBridge 181:57724642e740 36
AnnaBridge 181:57724642e740 37 LPTIM_HandleTypeDef LptimHandle;
AnnaBridge 181:57724642e740 38
AnnaBridge 181:57724642e740 39 volatile uint32_t lp_SlaveCounter = 0;
AnnaBridge 181:57724642e740 40 volatile uint32_t lp_oc_int_part = 0;
AnnaBridge 181:57724642e740 41 volatile uint16_t lp_TickPeriod_us;
AnnaBridge 181:57724642e740 42 volatile uint8_t lp_Fired = 0;
AnnaBridge 181:57724642e740 43
AnnaBridge 181:57724642e740 44 static void LPTIM1_IRQHandler(void);
AnnaBridge 181:57724642e740 45 static void (*irq_handler)(void);
AnnaBridge 181:57724642e740 46
AnnaBridge 181:57724642e740 47
AnnaBridge 181:57724642e740 48 void lp_ticker_init(void)
AnnaBridge 181:57724642e740 49 {
AnnaBridge 181:57724642e740 50 /* Check if LPTIM is already configured */
AnnaBridge 181:57724642e740 51 #if (TARGET_STM32L0)
AnnaBridge 181:57724642e740 52 if (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN) != RESET) {
AnnaBridge 181:57724642e740 53 return;
AnnaBridge 181:57724642e740 54 }
AnnaBridge 181:57724642e740 55 #else
AnnaBridge 181:57724642e740 56 if (__HAL_RCC_LPTIM1_IS_CLK_ENABLED()) {
AnnaBridge 181:57724642e740 57 return;
AnnaBridge 181:57724642e740 58 }
AnnaBridge 181:57724642e740 59 #endif
AnnaBridge 181:57724642e740 60
AnnaBridge 181:57724642e740 61 RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
AnnaBridge 181:57724642e740 62 RCC_OscInitTypeDef RCC_OscInitStruct = {0};
AnnaBridge 181:57724642e740 63
AnnaBridge 181:57724642e740 64 #if MBED_CONF_TARGET_LSE_AVAILABLE
AnnaBridge 181:57724642e740 65
AnnaBridge 181:57724642e740 66 /* Enable LSE clock */
AnnaBridge 181:57724642e740 67 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
AnnaBridge 181:57724642e740 68 RCC_OscInitStruct.LSEState = RCC_LSE_ON;
AnnaBridge 181:57724642e740 69 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
AnnaBridge 181:57724642e740 70
AnnaBridge 181:57724642e740 71 /* Select the LSE clock as LPTIM peripheral clock */
AnnaBridge 181:57724642e740 72 RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
AnnaBridge 181:57724642e740 73 #if (TARGET_STM32L0)
AnnaBridge 181:57724642e740 74 RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
AnnaBridge 181:57724642e740 75 #else
AnnaBridge 181:57724642e740 76 RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSE;
AnnaBridge 181:57724642e740 77 #endif
AnnaBridge 181:57724642e740 78
AnnaBridge 181:57724642e740 79 #else /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 181:57724642e740 80
AnnaBridge 181:57724642e740 81 /* Enable LSI clock */
AnnaBridge 181:57724642e740 82 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
AnnaBridge 181:57724642e740 83 RCC_OscInitStruct.LSIState = RCC_LSI_ON;
AnnaBridge 181:57724642e740 84 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
AnnaBridge 181:57724642e740 85
AnnaBridge 181:57724642e740 86 /* Select the LSI clock as LPTIM peripheral clock */
AnnaBridge 181:57724642e740 87 RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM1;
AnnaBridge 181:57724642e740 88 #if (TARGET_STM32L0)
AnnaBridge 181:57724642e740 89 RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
AnnaBridge 181:57724642e740 90 #else
AnnaBridge 181:57724642e740 91 RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIM1CLKSOURCE_LSI;
AnnaBridge 181:57724642e740 92 #endif
AnnaBridge 181:57724642e740 93
AnnaBridge 181:57724642e740 94 #endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
AnnaBridge 181:57724642e740 95
AnnaBridge 181:57724642e740 96 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
AnnaBridge 181:57724642e740 97 error("HAL_RCC_OscConfig ERROR\n");
AnnaBridge 181:57724642e740 98 return;
AnnaBridge 181:57724642e740 99 }
AnnaBridge 181:57724642e740 100
AnnaBridge 181:57724642e740 101 if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) {
AnnaBridge 181:57724642e740 102 error("HAL_RCCEx_PeriphCLKConfig ERROR\n");
AnnaBridge 181:57724642e740 103 return;
AnnaBridge 181:57724642e740 104 }
AnnaBridge 181:57724642e740 105
AnnaBridge 181:57724642e740 106 __HAL_RCC_LPTIM1_CLK_ENABLE();
AnnaBridge 181:57724642e740 107 __HAL_RCC_LPTIM1_FORCE_RESET();
AnnaBridge 181:57724642e740 108 __HAL_RCC_LPTIM1_RELEASE_RESET();
AnnaBridge 181:57724642e740 109
AnnaBridge 181:57724642e740 110 /* Initialize the LPTIM peripheral */
AnnaBridge 181:57724642e740 111 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 112 LptimHandle.State = HAL_LPTIM_STATE_RESET;
AnnaBridge 181:57724642e740 113 LptimHandle.Init.Clock.Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC;
AnnaBridge 181:57724642e740 114
AnnaBridge 181:57724642e740 115 /* Prescaler impact:
AnnaBridge 181:57724642e740 116 tick period = Prescaler division factor / LPTIM clock
AnnaBridge 181:57724642e740 117 Example with LPTIM clock = 32768 Hz LSE
AnnaBridge 181:57724642e740 118 Prescaler = LPTIM_PRESCALER_DIV1 => lp_TickPeriod_us = 31us => 2s with 16b timer
AnnaBridge 181:57724642e740 119 Prescaler = LPTIM_PRESCALER_DIV2 => lp_TickPeriod_us = 61us => 4s with 16b timer
AnnaBridge 181:57724642e740 120 Prescaler = LPTIM_PRESCALER_DIV4 => lp_TickPeriod_us = 122us => 8s with 16b timer
AnnaBridge 181:57724642e740 121 Prescaler = LPTIM_PRESCALER_DIV8 => lp_TickPeriod_us = 244us => 16s with 16b timer
AnnaBridge 181:57724642e740 122 Prescaler = LPTIM_PRESCALER_DIV16 => lp_TickPeriod_us = 488us => 32s with 16b timer
AnnaBridge 181:57724642e740 123 Prescaler = LPTIM_PRESCALER_DIV32 => lp_TickPeriod_us = 976us => 64s with 16b timer
AnnaBridge 181:57724642e740 124 Prescaler = LPTIM_PRESCALER_DIV64 => lp_TickPeriod_us = 1.9ms => 128s with 16b timer
AnnaBridge 181:57724642e740 125 Prescaler = LPTIM_PRESCALER_DIV128 => lp_TickPeriod_us = 3.9ms => 256s with 16b timer
AnnaBridge 181:57724642e740 126 */
AnnaBridge 181:57724642e740 127 LptimHandle.Init.Clock.Prescaler = LPTIM_PRESCALER_DIV2;
AnnaBridge 181:57724642e740 128 lp_TickPeriod_us = 2 * 1000000 / RTC_CLOCK;
AnnaBridge 181:57724642e740 129
AnnaBridge 181:57724642e740 130 LptimHandle.Init.Trigger.Source = LPTIM_TRIGSOURCE_SOFTWARE;
AnnaBridge 181:57724642e740 131 LptimHandle.Init.OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH;
AnnaBridge 181:57724642e740 132 LptimHandle.Init.UpdateMode = LPTIM_UPDATE_IMMEDIATE;
AnnaBridge 181:57724642e740 133 LptimHandle.Init.CounterSource = LPTIM_COUNTERSOURCE_INTERNAL;
AnnaBridge 181:57724642e740 134 #if (TARGET_STM32L4)
AnnaBridge 181:57724642e740 135 LptimHandle.Init.Input1Source = LPTIM_INPUT1SOURCE_GPIO;
AnnaBridge 181:57724642e740 136 LptimHandle.Init.Input2Source = LPTIM_INPUT2SOURCE_GPIO;
AnnaBridge 181:57724642e740 137 #endif /* TARGET_STM32L4 */
AnnaBridge 181:57724642e740 138
AnnaBridge 181:57724642e740 139 if (HAL_LPTIM_Init(&LptimHandle) != HAL_OK) {
AnnaBridge 181:57724642e740 140 error("HAL_LPTIM_Init ERROR\n");
AnnaBridge 181:57724642e740 141 return;
AnnaBridge 181:57724642e740 142 }
AnnaBridge 181:57724642e740 143
AnnaBridge 181:57724642e740 144 NVIC_SetVector(LPTIM1_IRQn, (uint32_t)LPTIM1_IRQHandler);
AnnaBridge 181:57724642e740 145 NVIC_EnableIRQ(LPTIM1_IRQn);
AnnaBridge 181:57724642e740 146
AnnaBridge 181:57724642e740 147 #if !(TARGET_STM32L4)
AnnaBridge 181:57724642e740 148 /* EXTI lines are not configured by default */
AnnaBridge 181:57724642e740 149 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
AnnaBridge 181:57724642e740 150 __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
AnnaBridge 181:57724642e740 151 #endif
AnnaBridge 181:57724642e740 152
AnnaBridge 181:57724642e740 153 __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_ARRM);
AnnaBridge 181:57724642e740 154 __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPM);
AnnaBridge 181:57724642e740 155 __HAL_LPTIM_ENABLE_IT(&LptimHandle, LPTIM_IT_CMPOK);
AnnaBridge 181:57724642e740 156 HAL_LPTIM_Counter_Start(&LptimHandle, 0xFFFF);
AnnaBridge 181:57724642e740 157 }
AnnaBridge 181:57724642e740 158
AnnaBridge 181:57724642e740 159 static void LPTIM1_IRQHandler(void)
AnnaBridge 181:57724642e740 160 {
AnnaBridge 181:57724642e740 161 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 162
AnnaBridge 181:57724642e740 163 if (lp_Fired) {
AnnaBridge 181:57724642e740 164 lp_Fired = 0;
AnnaBridge 181:57724642e740 165 if (irq_handler) {
AnnaBridge 181:57724642e740 166 irq_handler();
AnnaBridge 181:57724642e740 167 }
AnnaBridge 181:57724642e740 168 }
AnnaBridge 181:57724642e740 169
AnnaBridge 181:57724642e740 170 /* Compare match interrupt */
AnnaBridge 181:57724642e740 171 if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) != RESET) {
AnnaBridge 181:57724642e740 172 if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPM) != RESET) {
AnnaBridge 181:57724642e740 173 /* Clear Compare match flag */
AnnaBridge 181:57724642e740 174 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
AnnaBridge 181:57724642e740 175
AnnaBridge 181:57724642e740 176 if (lp_oc_int_part > 0) {
AnnaBridge 181:57724642e740 177 lp_oc_int_part--;
AnnaBridge 181:57724642e740 178 } else {
AnnaBridge 181:57724642e740 179 if (irq_handler) {
AnnaBridge 181:57724642e740 180 irq_handler();
AnnaBridge 181:57724642e740 181 }
AnnaBridge 181:57724642e740 182 }
AnnaBridge 181:57724642e740 183 }
AnnaBridge 181:57724642e740 184 }
AnnaBridge 181:57724642e740 185
AnnaBridge 181:57724642e740 186 /* Compare write interrupt */
AnnaBridge 181:57724642e740 187 if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) != RESET) {
AnnaBridge 181:57724642e740 188 if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_CMPOK) != RESET) {
AnnaBridge 181:57724642e740 189 /* Clear Compare write flag */
AnnaBridge 181:57724642e740 190 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK);
AnnaBridge 181:57724642e740 191 }
AnnaBridge 181:57724642e740 192 }
AnnaBridge 181:57724642e740 193
AnnaBridge 181:57724642e740 194 /* Autoreload match interrupt */
AnnaBridge 181:57724642e740 195 if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) != RESET) {
AnnaBridge 181:57724642e740 196 if (__HAL_LPTIM_GET_IT_SOURCE(&LptimHandle, LPTIM_IT_ARRM) != RESET) {
AnnaBridge 181:57724642e740 197 /* Clear Autoreload match flag */
AnnaBridge 181:57724642e740 198 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_ARRM);
AnnaBridge 181:57724642e740 199 lp_SlaveCounter++;
AnnaBridge 181:57724642e740 200 }
AnnaBridge 181:57724642e740 201 }
AnnaBridge 181:57724642e740 202
AnnaBridge 181:57724642e740 203 #if !(TARGET_STM32L4)
AnnaBridge 181:57724642e740 204 __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
AnnaBridge 181:57724642e740 205 #endif
AnnaBridge 181:57724642e740 206 }
AnnaBridge 181:57724642e740 207
AnnaBridge 181:57724642e740 208
AnnaBridge 181:57724642e740 209 uint32_t lp_ticker_read_TickCounter(void)
AnnaBridge 181:57724642e740 210 {
AnnaBridge 181:57724642e740 211 uint16_t cntH_old, cntH, cntL;
AnnaBridge 181:57724642e740 212
AnnaBridge 181:57724642e740 213 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 214
AnnaBridge 181:57724642e740 215 /* same algo as us_ticker_read in us_ticker_16b.c */
AnnaBridge 181:57724642e740 216 do {
AnnaBridge 181:57724642e740 217 cntH_old = lp_SlaveCounter;
AnnaBridge 181:57724642e740 218 if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) {
AnnaBridge 181:57724642e740 219 cntH_old += 1;
AnnaBridge 181:57724642e740 220 }
AnnaBridge 181:57724642e740 221 cntL = LPTIM1->CNT;
AnnaBridge 181:57724642e740 222 cntH = lp_SlaveCounter;
AnnaBridge 181:57724642e740 223 if (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_ARRM) == SET) {
AnnaBridge 181:57724642e740 224 cntH += 1;
AnnaBridge 181:57724642e740 225 }
AnnaBridge 181:57724642e740 226 } while (cntH_old != cntH);
AnnaBridge 181:57724642e740 227 uint32_t lp_time = (uint32_t)(cntH << 16 | cntL);
AnnaBridge 181:57724642e740 228 return lp_time;
AnnaBridge 181:57724642e740 229 }
AnnaBridge 181:57724642e740 230
AnnaBridge 181:57724642e740 231 uint32_t lp_ticker_read(void)
AnnaBridge 181:57724642e740 232 {
AnnaBridge 181:57724642e740 233 lp_ticker_init();
AnnaBridge 181:57724642e740 234 return lp_ticker_read_TickCounter() * (uint32_t)lp_TickPeriod_us;
AnnaBridge 181:57724642e740 235 }
AnnaBridge 181:57724642e740 236
AnnaBridge 181:57724642e740 237 void lp_ticker_set_interrupt(timestamp_t timestamp)
AnnaBridge 181:57724642e740 238 {
AnnaBridge 181:57724642e740 239 // Disable IRQs
AnnaBridge 181:57724642e740 240 core_util_critical_section_enter();
AnnaBridge 181:57724642e740 241
AnnaBridge 181:57724642e740 242 uint32_t timestamp_TickCounter = timestamp / (uint32_t)lp_TickPeriod_us;
AnnaBridge 181:57724642e740 243
AnnaBridge 181:57724642e740 244 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 245 irq_handler = (void (*)(void))lp_ticker_irq_handler;
AnnaBridge 181:57724642e740 246
AnnaBridge 181:57724642e740 247 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK);
AnnaBridge 181:57724642e740 248 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
AnnaBridge 181:57724642e740 249 __HAL_LPTIM_COMPARE_SET(&LptimHandle, timestamp_TickCounter & 0xFFFF);
AnnaBridge 181:57724642e740 250
AnnaBridge 181:57724642e740 251 /* CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIM_CMP register has been successfully completed */
AnnaBridge 181:57724642e740 252 while (__HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPOK) == RESET) {
AnnaBridge 181:57724642e740 253 }
AnnaBridge 181:57724642e740 254
AnnaBridge 181:57724642e740 255 /* same algo as us_ticker_set_interrupt in us_ticker_16b.c */
AnnaBridge 181:57724642e740 256 uint32_t current_time_TickCounter = lp_ticker_read_TickCounter();
AnnaBridge 181:57724642e740 257 uint32_t delta = timestamp_TickCounter - current_time_TickCounter;
AnnaBridge 181:57724642e740 258 lp_oc_int_part = (delta - 1) >> 16;
AnnaBridge 181:57724642e740 259 if ( ((delta - 1) & 0xFFFF) >= 0x8000 &&
AnnaBridge 181:57724642e740 260 __HAL_LPTIM_GET_FLAG(&LptimHandle, LPTIM_FLAG_CMPM) == SET ) {
AnnaBridge 181:57724642e740 261 ++lp_oc_int_part;
AnnaBridge 181:57724642e740 262 }
AnnaBridge 181:57724642e740 263
AnnaBridge 181:57724642e740 264 // Enable IRQs
AnnaBridge 181:57724642e740 265 core_util_critical_section_exit();
AnnaBridge 181:57724642e740 266 }
AnnaBridge 181:57724642e740 267
AnnaBridge 181:57724642e740 268 void lp_ticker_fire_interrupt(void)
AnnaBridge 181:57724642e740 269 {
AnnaBridge 181:57724642e740 270 lp_Fired = 1;
AnnaBridge 181:57724642e740 271 NVIC_SetPendingIRQ(LPTIM1_IRQn);
AnnaBridge 181:57724642e740 272 }
AnnaBridge 181:57724642e740 273
AnnaBridge 181:57724642e740 274 void lp_ticker_disable_interrupt(void)
AnnaBridge 181:57724642e740 275 {
AnnaBridge 181:57724642e740 276 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 277 __HAL_LPTIM_DISABLE_IT(&LptimHandle, LPTIM_IT_CMPM);
AnnaBridge 181:57724642e740 278 }
AnnaBridge 181:57724642e740 279
AnnaBridge 181:57724642e740 280 void lp_ticker_clear_interrupt(void)
AnnaBridge 181:57724642e740 281 {
AnnaBridge 181:57724642e740 282 LptimHandle.Instance = LPTIM1;
AnnaBridge 181:57724642e740 283 __HAL_LPTIM_CLEAR_FLAG(&LptimHandle, LPTIM_FLAG_CMPM);
AnnaBridge 181:57724642e740 284 }
AnnaBridge 181:57724642e740 285
AnnaBridge 181:57724642e740 286 #else /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */
AnnaBridge 181:57724642e740 287
<> 154:37f96f9d4de2 288 void lp_ticker_init(void)
<> 154:37f96f9d4de2 289 {
<> 154:37f96f9d4de2 290 rtc_init();
<> 154:37f96f9d4de2 291 }
<> 154:37f96f9d4de2 292
<> 154:37f96f9d4de2 293 uint32_t lp_ticker_read(void)
<> 154:37f96f9d4de2 294 {
AnnaBridge 181:57724642e740 295 uint32_t usecs = rtc_read_us();
AnnaBridge 181:57724642e740 296 return usecs;
<> 154:37f96f9d4de2 297 }
<> 154:37f96f9d4de2 298
<> 154:37f96f9d4de2 299 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 154:37f96f9d4de2 300 {
<> 154:37f96f9d4de2 301 uint32_t delta;
<> 154:37f96f9d4de2 302
<> 154:37f96f9d4de2 303 delta = timestamp - lp_ticker_read();
<> 154:37f96f9d4de2 304 rtc_set_wake_up_timer(delta);
<> 154:37f96f9d4de2 305 }
<> 154:37f96f9d4de2 306
AnnaBridge 174:b96e65c34a4d 307 void lp_ticker_fire_interrupt(void)
AnnaBridge 174:b96e65c34a4d 308 {
AnnaBridge 174:b96e65c34a4d 309 NVIC_SetPendingIRQ(RTC_WKUP_IRQn);
AnnaBridge 174:b96e65c34a4d 310 }
AnnaBridge 174:b96e65c34a4d 311
<> 154:37f96f9d4de2 312 void lp_ticker_disable_interrupt(void)
<> 154:37f96f9d4de2 313 {
<> 154:37f96f9d4de2 314 rtc_deactivate_wake_up_timer();
<> 154:37f96f9d4de2 315 }
<> 154:37f96f9d4de2 316
<> 154:37f96f9d4de2 317 void lp_ticker_clear_interrupt(void)
<> 154:37f96f9d4de2 318 {
Anna Bridge 180:96ed750bd169 319 NVIC_ClearPendingIRQ(RTC_WKUP_IRQn);
<> 154:37f96f9d4de2 320 }
<> 154:37f96f9d4de2 321
AnnaBridge 181:57724642e740 322 #endif /* MBED_CONF_TARGET_LOWPOWERTIMER_LPTIM */
AnnaBridge 181:57724642e740 323
Anna Bridge 180:96ed750bd169 324 #endif /* DEVICE_LOWPOWERTIMER */