mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_rcc_ex.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_rcc_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of RCC HAL Extension module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_RCC_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup RCCEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /** @addtogroup RCCEx_Private_Constants
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /* Alias word address of PLLI2SON bit */
<> 144:ef7eb2e8f9f7 64 #define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
<> 144:ef7eb2e8f9f7 65 #define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
<> 144:ef7eb2e8f9f7 66 /* Alias word address of PLL2ON bit */
<> 144:ef7eb2e8f9f7 67 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
<> 144:ef7eb2e8f9f7 68 #define RCC_CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
<> 144:ef7eb2e8f9f7 71 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 #define CR_REG_INDEX ((uint8_t)1)
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /**
<> 144:ef7eb2e8f9f7 79 * @}
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /** @addtogroup RCCEx_Private_Macros
<> 144:ef7eb2e8f9f7 83 * @{
<> 144:ef7eb2e8f9f7 84 */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 87 #define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) || \
<> 144:ef7eb2e8f9f7 88 ((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
<> 144:ef7eb2e8f9f7 89 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 92 || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 93 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2) || \
<> 144:ef7eb2e8f9f7 94 ((__DIV__) == RCC_HSE_PREDIV_DIV3) || ((__DIV__) == RCC_HSE_PREDIV_DIV4) || \
<> 144:ef7eb2e8f9f7 95 ((__DIV__) == RCC_HSE_PREDIV_DIV5) || ((__DIV__) == RCC_HSE_PREDIV_DIV6) || \
<> 144:ef7eb2e8f9f7 96 ((__DIV__) == RCC_HSE_PREDIV_DIV7) || ((__DIV__) == RCC_HSE_PREDIV_DIV8) || \
<> 144:ef7eb2e8f9f7 97 ((__DIV__) == RCC_HSE_PREDIV_DIV9) || ((__DIV__) == RCC_HSE_PREDIV_DIV10) || \
<> 144:ef7eb2e8f9f7 98 ((__DIV__) == RCC_HSE_PREDIV_DIV11) || ((__DIV__) == RCC_HSE_PREDIV_DIV12) || \
<> 144:ef7eb2e8f9f7 99 ((__DIV__) == RCC_HSE_PREDIV_DIV13) || ((__DIV__) == RCC_HSE_PREDIV_DIV14) || \
<> 144:ef7eb2e8f9f7 100 ((__DIV__) == RCC_HSE_PREDIV_DIV15) || ((__DIV__) == RCC_HSE_PREDIV_DIV16))
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #else
<> 144:ef7eb2e8f9f7 103 #define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) || ((__DIV__) == RCC_HSE_PREDIV_DIV2))
<> 144:ef7eb2e8f9f7 104 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 107 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
<> 144:ef7eb2e8f9f7 108 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
<> 144:ef7eb2e8f9f7 109 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
<> 144:ef7eb2e8f9f7 110 ((__MUL__) == RCC_PLL_MUL6_5))
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
<> 144:ef7eb2e8f9f7 113 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
<> 144:ef7eb2e8f9f7 114 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
<> 144:ef7eb2e8f9f7 115 || ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) || ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
<> 144:ef7eb2e8f9f7 116 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #else
<> 144:ef7eb2e8f9f7 119 #define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) || ((__MUL__) == RCC_PLL_MUL3) || \
<> 144:ef7eb2e8f9f7 120 ((__MUL__) == RCC_PLL_MUL4) || ((__MUL__) == RCC_PLL_MUL5) || \
<> 144:ef7eb2e8f9f7 121 ((__MUL__) == RCC_PLL_MUL6) || ((__MUL__) == RCC_PLL_MUL7) || \
<> 144:ef7eb2e8f9f7 122 ((__MUL__) == RCC_PLL_MUL8) || ((__MUL__) == RCC_PLL_MUL9) || \
<> 144:ef7eb2e8f9f7 123 ((__MUL__) == RCC_PLL_MUL10) || ((__MUL__) == RCC_PLL_MUL11) || \
<> 144:ef7eb2e8f9f7 124 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL13) || \
<> 144:ef7eb2e8f9f7 125 ((__MUL__) == RCC_PLL_MUL14) || ((__MUL__) == RCC_PLL_MUL15) || \
<> 144:ef7eb2e8f9f7 126 ((__MUL__) == RCC_PLL_MUL16))
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
<> 144:ef7eb2e8f9f7 129 || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
<> 144:ef7eb2e8f9f7 130 || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 #endif /* STM32F105xC || STM32F107xC*/
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) || \
<> 144:ef7eb2e8f9f7 135 ((__ADCCLK__) == RCC_ADCPCLK2_DIV6) || ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 138 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) || ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV2) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV3))
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) || ((__MUL__) == RCC_PLLI2S_MUL9) || \
<> 144:ef7eb2e8f9f7 145 ((__MUL__) == RCC_PLLI2S_MUL10) || ((__MUL__) == RCC_PLLI2S_MUL11) || \
<> 144:ef7eb2e8f9f7 146 ((__MUL__) == RCC_PLLI2S_MUL12) || ((__MUL__) == RCC_PLLI2S_MUL13) || \
<> 144:ef7eb2e8f9f7 147 ((__MUL__) == RCC_PLLI2S_MUL14) || ((__MUL__) == RCC_PLLI2S_MUL16) || \
<> 144:ef7eb2e8f9f7 148 ((__MUL__) == RCC_PLLI2S_MUL20))
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 #define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) || ((__DIV__) == RCC_HSE_PREDIV2_DIV2) || \
<> 144:ef7eb2e8f9f7 151 ((__DIV__) == RCC_HSE_PREDIV2_DIV3) || ((__DIV__) == RCC_HSE_PREDIV2_DIV4) || \
<> 144:ef7eb2e8f9f7 152 ((__DIV__) == RCC_HSE_PREDIV2_DIV5) || ((__DIV__) == RCC_HSE_PREDIV2_DIV6) || \
<> 144:ef7eb2e8f9f7 153 ((__DIV__) == RCC_HSE_PREDIV2_DIV7) || ((__DIV__) == RCC_HSE_PREDIV2_DIV8) || \
<> 144:ef7eb2e8f9f7 154 ((__DIV__) == RCC_HSE_PREDIV2_DIV9) || ((__DIV__) == RCC_HSE_PREDIV2_DIV10) || \
<> 144:ef7eb2e8f9f7 155 ((__DIV__) == RCC_HSE_PREDIV2_DIV11) || ((__DIV__) == RCC_HSE_PREDIV2_DIV12) || \
<> 144:ef7eb2e8f9f7 156 ((__DIV__) == RCC_HSE_PREDIV2_DIV13) || ((__DIV__) == RCC_HSE_PREDIV2_DIV14) || \
<> 144:ef7eb2e8f9f7 157 ((__DIV__) == RCC_HSE_PREDIV2_DIV15) || ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 #define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) || ((__PLL__) == RCC_PLL2_OFF) || \
<> 144:ef7eb2e8f9f7 160 ((__PLL__) == RCC_PLL2_ON))
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 #define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) || ((__MUL__) == RCC_PLL2_MUL9) || \
<> 144:ef7eb2e8f9f7 163 ((__MUL__) == RCC_PLL2_MUL10) || ((__MUL__) == RCC_PLL2_MUL11) || \
<> 144:ef7eb2e8f9f7 164 ((__MUL__) == RCC_PLL2_MUL12) || ((__MUL__) == RCC_PLL2_MUL13) || \
<> 144:ef7eb2e8f9f7 165 ((__MUL__) == RCC_PLL2_MUL14) || ((__MUL__) == RCC_PLL2_MUL16) || \
<> 144:ef7eb2e8f9f7 166 ((__MUL__) == RCC_PLL2_MUL20))
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
<> 144:ef7eb2e8f9f7 169 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
<> 144:ef7eb2e8f9f7 170 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
<> 144:ef7eb2e8f9f7 171 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
<> 144:ef7eb2e8f9f7 172 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
<> 144:ef7eb2e8f9f7 173 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 #elif defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 #define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 #define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
<> 144:ef7eb2e8f9f7 182 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
<> 144:ef7eb2e8f9f7 183 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
<> 144:ef7eb2e8f9f7 184 (((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) || \
<> 144:ef7eb2e8f9f7 185 (((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) || \
<> 144:ef7eb2e8f9f7 186 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 #elif defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 190 || defined(STM32F103xB)
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
<> 144:ef7eb2e8f9f7 193 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
<> 144:ef7eb2e8f9f7 194 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
<> 144:ef7eb2e8f9f7 195 (((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 #else
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
<> 144:ef7eb2e8f9f7 200 ((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
<> 144:ef7eb2e8f9f7 201 (((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 206 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBCLKSOURCE_PLL) || ((__USBCLK__) == RCC_USBCLKSOURCE_PLL_DIV1_5))
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
<> 144:ef7eb2e8f9f7 213 * @}
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 217
<> 144:ef7eb2e8f9f7 218 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
<> 144:ef7eb2e8f9f7 219 * @{
<> 144:ef7eb2e8f9f7 220 */
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 223 /**
<> 144:ef7eb2e8f9f7 224 * @brief RCC PLL2 configuration structure definition
<> 144:ef7eb2e8f9f7 225 */
<> 144:ef7eb2e8f9f7 226 typedef struct
<> 144:ef7eb2e8f9f7 227 {
<> 144:ef7eb2e8f9f7 228 uint32_t PLL2State; /*!< The new state of the PLL2.
<> 144:ef7eb2e8f9f7 229 This parameter can be a value of @ref RCCEx_PLL2_Config */
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
<> 144:ef7eb2e8f9f7 232 This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
<> 144:ef7eb2e8f9f7 233
<> 144:ef7eb2e8f9f7 234 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 235 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
<> 144:ef7eb2e8f9f7 236 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 239 } RCC_PLL2InitTypeDef;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 242
<> 144:ef7eb2e8f9f7 243 /**
<> 144:ef7eb2e8f9f7 244 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<> 144:ef7eb2e8f9f7 245 */
<> 144:ef7eb2e8f9f7 246 typedef struct
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 uint32_t OscillatorType; /*!< The oscillators to be configured.
<> 144:ef7eb2e8f9f7 249 This parameter can be a value of @ref RCC_Oscillator_Type */
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 252 uint32_t Prediv1Source; /*!< The Prediv1 source value.
<> 144:ef7eb2e8f9f7 253 This parameter can be a value of @ref RCCEx_Prediv1_Source */
<> 144:ef7eb2e8f9f7 254 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 uint32_t HSEState; /*!< The new state of the HSE.
<> 144:ef7eb2e8f9f7 257 This parameter can be a value of @ref RCC_HSE_Config */
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
<> 144:ef7eb2e8f9f7 260 This parameter can be a value of @ref RCCEx_Prediv1_Factor */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 uint32_t LSEState; /*!< The new state of the LSE.
<> 144:ef7eb2e8f9f7 263 This parameter can be a value of @ref RCC_LSE_Config */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 uint32_t HSIState; /*!< The new state of the HSI.
<> 144:ef7eb2e8f9f7 266 This parameter can be a value of @ref RCC_HSI_Config */
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
<> 144:ef7eb2e8f9f7 269 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 uint32_t LSIState; /*!< The new state of the LSI.
<> 144:ef7eb2e8f9f7 272 This parameter can be a value of @ref RCC_LSI_Config */
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 277 RCC_PLL2InitTypeDef PLL2; /*!< PLL2 structure parameters */
<> 144:ef7eb2e8f9f7 278 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 279 } RCC_OscInitTypeDef;
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 282 /**
<> 144:ef7eb2e8f9f7 283 * @brief RCC PLLI2S configuration structure definition
<> 144:ef7eb2e8f9f7 284 */
<> 144:ef7eb2e8f9f7 285 typedef struct
<> 144:ef7eb2e8f9f7 286 {
<> 144:ef7eb2e8f9f7 287 uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
<> 144:ef7eb2e8f9f7 288 This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 291 uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
<> 144:ef7eb2e8f9f7 292 This parameter can be a value of @ref RCCEx_Prediv2_Factor */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 295 } RCC_PLLI2SInitTypeDef;
<> 144:ef7eb2e8f9f7 296 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief RCC extended clocks structure definition
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301 typedef struct
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
<> 144:ef7eb2e8f9f7 304 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
<> 144:ef7eb2e8f9f7 307 This parameter can be a value of @ref RCC_RTC_Clock_Source */
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 uint32_t AdcClockSelection; /*!< ADC clock source
<> 144:ef7eb2e8f9f7 310 This parameter can be a value of @ref RCCEx_ADC_Prescaler */
<> 144:ef7eb2e8f9f7 311
<> 144:ef7eb2e8f9f7 312 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 313 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 314 uint32_t I2s2ClockSelection; /*!< I2S2 clock source
<> 144:ef7eb2e8f9f7 315 This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 uint32_t I2s3ClockSelection; /*!< I2S3 clock source
<> 144:ef7eb2e8f9f7 318 This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
<> 144:ef7eb2e8f9f7 319
<> 144:ef7eb2e8f9f7 320 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 321 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
<> 144:ef7eb2e8f9f7 322 This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 325 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 328 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 329 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 330 uint32_t UsbClockSelection; /*!< USB clock source
<> 144:ef7eb2e8f9f7 331 This parameter can be a value of @ref RCCEx_USB_Prescaler */
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 334 } RCC_PeriphCLKInitTypeDef;
<> 144:ef7eb2e8f9f7 335
<> 144:ef7eb2e8f9f7 336 /**
<> 144:ef7eb2e8f9f7 337 * @}
<> 144:ef7eb2e8f9f7 338 */
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
<> 144:ef7eb2e8f9f7 343 * @{
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
<> 144:ef7eb2e8f9f7 347 * @{
<> 144:ef7eb2e8f9f7 348 */
<> 144:ef7eb2e8f9f7 349 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 350 #define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 351 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 352 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 353 #define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 354 #define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 355 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 356 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 357 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 358 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 359 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 360 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /**
<> 144:ef7eb2e8f9f7 363 * @}
<> 144:ef7eb2e8f9f7 364 */
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 /** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
<> 144:ef7eb2e8f9f7 367 * @{
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 #define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
<> 144:ef7eb2e8f9f7 370 #define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
<> 144:ef7eb2e8f9f7 371 #define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
<> 144:ef7eb2e8f9f7 372 #define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /**
<> 144:ef7eb2e8f9f7 375 * @}
<> 144:ef7eb2e8f9f7 376 */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 379 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 380 /** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
<> 144:ef7eb2e8f9f7 381 * @{
<> 144:ef7eb2e8f9f7 382 */
<> 144:ef7eb2e8f9f7 383 #define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 384 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 385 #define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
<> 144:ef7eb2e8f9f7 386 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /**
<> 144:ef7eb2e8f9f7 389 * @}
<> 144:ef7eb2e8f9f7 390 */
<> 144:ef7eb2e8f9f7 391
<> 144:ef7eb2e8f9f7 392 /** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
<> 144:ef7eb2e8f9f7 393 * @{
<> 144:ef7eb2e8f9f7 394 */
<> 144:ef7eb2e8f9f7 395 #define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 396 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 397 #define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
<> 144:ef7eb2e8f9f7 398 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 399
<> 144:ef7eb2e8f9f7 400 /**
<> 144:ef7eb2e8f9f7 401 * @}
<> 144:ef7eb2e8f9f7 402 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 407 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
<> 144:ef7eb2e8f9f7 410 * @{
<> 144:ef7eb2e8f9f7 411 */
<> 144:ef7eb2e8f9f7 412 #define RCC_USBCLKSOURCE_PLL RCC_CFGR_USBPRE
<> 144:ef7eb2e8f9f7 413 #define RCC_USBCLKSOURCE_PLL_DIV1_5 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /**
<> 144:ef7eb2e8f9f7 416 * @}
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 423 /** @defgroup RCCEx_USB_Prescaler USB Prescaler
<> 144:ef7eb2e8f9f7 424 * @{
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426 #define RCC_USBCLKSOURCE_PLL_DIV2 RCC_CFGR_OTGFSPRE
<> 144:ef7eb2e8f9f7 427 #define RCC_USBCLKSOURCE_PLL_DIV3 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @}
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432
<> 144:ef7eb2e8f9f7 433 /** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
<> 144:ef7eb2e8f9f7 434 * @{
<> 144:ef7eb2e8f9f7 435 */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 #define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /*!< PLLI2S input clock * 8 */
<> 144:ef7eb2e8f9f7 438 #define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /*!< PLLI2S input clock * 9 */
<> 144:ef7eb2e8f9f7 439 #define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /*!< PLLI2S input clock * 10 */
<> 144:ef7eb2e8f9f7 440 #define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /*!< PLLI2S input clock * 11 */
<> 144:ef7eb2e8f9f7 441 #define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /*!< PLLI2S input clock * 12 */
<> 144:ef7eb2e8f9f7 442 #define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /*!< PLLI2S input clock * 13 */
<> 144:ef7eb2e8f9f7 443 #define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /*!< PLLI2S input clock * 14 */
<> 144:ef7eb2e8f9f7 444 #define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /*!< PLLI2S input clock * 16 */
<> 144:ef7eb2e8f9f7 445 #define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /*!< PLLI2S input clock * 20 */
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 453 /** @defgroup RCCEx_Prediv1_Source Prediv1 Source
<> 144:ef7eb2e8f9f7 454 * @{
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 #define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
<> 144:ef7eb2e8f9f7 458 #define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @}
<> 144:ef7eb2e8f9f7 462 */
<> 144:ef7eb2e8f9f7 463 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 /** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
<> 144:ef7eb2e8f9f7 466 * @{
<> 144:ef7eb2e8f9f7 467 */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 #define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 472 || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 473 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
<> 144:ef7eb2e8f9f7 474 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
<> 144:ef7eb2e8f9f7 475 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
<> 144:ef7eb2e8f9f7 476 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
<> 144:ef7eb2e8f9f7 477 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
<> 144:ef7eb2e8f9f7 478 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
<> 144:ef7eb2e8f9f7 479 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
<> 144:ef7eb2e8f9f7 480 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
<> 144:ef7eb2e8f9f7 481 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
<> 144:ef7eb2e8f9f7 482 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
<> 144:ef7eb2e8f9f7 483 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
<> 144:ef7eb2e8f9f7 484 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
<> 144:ef7eb2e8f9f7 485 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
<> 144:ef7eb2e8f9f7 486 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
<> 144:ef7eb2e8f9f7 487 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
<> 144:ef7eb2e8f9f7 488 #else
<> 144:ef7eb2e8f9f7 489 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
<> 144:ef7eb2e8f9f7 490 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 /**
<> 144:ef7eb2e8f9f7 493 * @}
<> 144:ef7eb2e8f9f7 494 */
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 497 /** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
<> 144:ef7eb2e8f9f7 498 * @{
<> 144:ef7eb2e8f9f7 499 */
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 #define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /*!< PREDIV2 input clock not divided */
<> 144:ef7eb2e8f9f7 502 #define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /*!< PREDIV2 input clock divided by 2 */
<> 144:ef7eb2e8f9f7 503 #define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /*!< PREDIV2 input clock divided by 3 */
<> 144:ef7eb2e8f9f7 504 #define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /*!< PREDIV2 input clock divided by 4 */
<> 144:ef7eb2e8f9f7 505 #define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /*!< PREDIV2 input clock divided by 5 */
<> 144:ef7eb2e8f9f7 506 #define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /*!< PREDIV2 input clock divided by 6 */
<> 144:ef7eb2e8f9f7 507 #define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /*!< PREDIV2 input clock divided by 7 */
<> 144:ef7eb2e8f9f7 508 #define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /*!< PREDIV2 input clock divided by 8 */
<> 144:ef7eb2e8f9f7 509 #define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /*!< PREDIV2 input clock divided by 9 */
<> 144:ef7eb2e8f9f7 510 #define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /*!< PREDIV2 input clock divided by 10 */
<> 144:ef7eb2e8f9f7 511 #define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /*!< PREDIV2 input clock divided by 11 */
<> 144:ef7eb2e8f9f7 512 #define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /*!< PREDIV2 input clock divided by 12 */
<> 144:ef7eb2e8f9f7 513 #define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /*!< PREDIV2 input clock divided by 13 */
<> 144:ef7eb2e8f9f7 514 #define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /*!< PREDIV2 input clock divided by 14 */
<> 144:ef7eb2e8f9f7 515 #define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /*!< PREDIV2 input clock divided by 15 */
<> 144:ef7eb2e8f9f7 516 #define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /*!< PREDIV2 input clock divided by 16 */
<> 144:ef7eb2e8f9f7 517
<> 144:ef7eb2e8f9f7 518 /**
<> 144:ef7eb2e8f9f7 519 * @}
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /** @defgroup RCCEx_PLL2_Config PLL Config
<> 144:ef7eb2e8f9f7 523 * @{
<> 144:ef7eb2e8f9f7 524 */
<> 144:ef7eb2e8f9f7 525 #define RCC_PLL2_NONE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 526 #define RCC_PLL2_OFF ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 527 #define RCC_PLL2_ON ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /**
<> 144:ef7eb2e8f9f7 530 * @}
<> 144:ef7eb2e8f9f7 531 */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 /** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
<> 144:ef7eb2e8f9f7 534 * @{
<> 144:ef7eb2e8f9f7 535 */
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 #define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /*!< PLL2 input clock * 8 */
<> 144:ef7eb2e8f9f7 538 #define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /*!< PLL2 input clock * 9 */
<> 144:ef7eb2e8f9f7 539 #define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /*!< PLL2 input clock * 10 */
<> 144:ef7eb2e8f9f7 540 #define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /*!< PLL2 input clock * 11 */
<> 144:ef7eb2e8f9f7 541 #define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /*!< PLL2 input clock * 12 */
<> 144:ef7eb2e8f9f7 542 #define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /*!< PLL2 input clock * 13 */
<> 144:ef7eb2e8f9f7 543 #define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /*!< PLL2 input clock * 14 */
<> 144:ef7eb2e8f9f7 544 #define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /*!< PLL2 input clock * 16 */
<> 144:ef7eb2e8f9f7 545 #define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /*!< PLL2 input clock * 20 */
<> 144:ef7eb2e8f9f7 546
<> 144:ef7eb2e8f9f7 547 /**
<> 144:ef7eb2e8f9f7 548 * @}
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550
<> 144:ef7eb2e8f9f7 551 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 /** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
<> 144:ef7eb2e8f9f7 554 * @{
<> 144:ef7eb2e8f9f7 555 */
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 558 #else
<> 144:ef7eb2e8f9f7 559 #define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
<> 144:ef7eb2e8f9f7 560 #define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
<> 144:ef7eb2e8f9f7 561 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 562 #define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
<> 144:ef7eb2e8f9f7 563 #define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
<> 144:ef7eb2e8f9f7 564 #define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
<> 144:ef7eb2e8f9f7 565 #define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
<> 144:ef7eb2e8f9f7 566 #define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
<> 144:ef7eb2e8f9f7 567 #define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
<> 144:ef7eb2e8f9f7 568 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 569 #define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
<> 144:ef7eb2e8f9f7 570 #else
<> 144:ef7eb2e8f9f7 571 #define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
<> 144:ef7eb2e8f9f7 572 #define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
<> 144:ef7eb2e8f9f7 573 #define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
<> 144:ef7eb2e8f9f7 574 #define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
<> 144:ef7eb2e8f9f7 575 #define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
<> 144:ef7eb2e8f9f7 576 #define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
<> 144:ef7eb2e8f9f7 577 #define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
<> 144:ef7eb2e8f9f7 578 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 /**
<> 144:ef7eb2e8f9f7 581 * @}
<> 144:ef7eb2e8f9f7 582 */
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 /** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
<> 144:ef7eb2e8f9f7 585 * @{
<> 144:ef7eb2e8f9f7 586 */
<> 144:ef7eb2e8f9f7 587 #define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
<> 144:ef7eb2e8f9f7 588 #define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
<> 144:ef7eb2e8f9f7 589 #define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
<> 144:ef7eb2e8f9f7 590 #define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
<> 144:ef7eb2e8f9f7 591 #define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
<> 144:ef7eb2e8f9f7 592 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 593 #define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
<> 144:ef7eb2e8f9f7 594 #define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
<> 144:ef7eb2e8f9f7 595 #define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
<> 144:ef7eb2e8f9f7 596 #define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
<> 144:ef7eb2e8f9f7 597 #endif /* STM32F105xC || STM32F107xC*/
<> 144:ef7eb2e8f9f7 598 /**
<> 144:ef7eb2e8f9f7 599 * @}
<> 144:ef7eb2e8f9f7 600 */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 603 /** @defgroup RCCEx_Interrupt RCCEx Interrupt
<> 144:ef7eb2e8f9f7 604 * @{
<> 144:ef7eb2e8f9f7 605 */
<> 144:ef7eb2e8f9f7 606 #define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
<> 144:ef7eb2e8f9f7 607 #define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
<> 144:ef7eb2e8f9f7 608 /**
<> 144:ef7eb2e8f9f7 609 * @}
<> 144:ef7eb2e8f9f7 610 */
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /** @defgroup RCCEx_Flag RCCEx Flag
<> 144:ef7eb2e8f9f7 613 * Elements values convention: 0XXYYYYYb
<> 144:ef7eb2e8f9f7 614 * - YYYYY : Flag position in the register
<> 144:ef7eb2e8f9f7 615 * - XX : Register index
<> 144:ef7eb2e8f9f7 616 * - 01: CR register
<> 144:ef7eb2e8f9f7 617 * @{
<> 144:ef7eb2e8f9f7 618 */
<> 144:ef7eb2e8f9f7 619 /* Flags in the CR register */
<> 144:ef7eb2e8f9f7 620 #define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL2RDY)))
<> 144:ef7eb2e8f9f7 621 #define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLL3RDY)))
<> 144:ef7eb2e8f9f7 622 /**
<> 144:ef7eb2e8f9f7 623 * @}
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 #endif /* STM32F105xC || STM32F107xC*/
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 /**
<> 144:ef7eb2e8f9f7 628 * @}
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 632 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
<> 144:ef7eb2e8f9f7 633 * @{
<> 144:ef7eb2e8f9f7 634 */
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
<> 144:ef7eb2e8f9f7 637 * @brief Enable or disable the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 638 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 639 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 640 * using it.
<> 144:ef7eb2e8f9f7 641 * @{
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 645 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
<> 144:ef7eb2e8f9f7 646 || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 647 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 648 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 649 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 650 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 651 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
<> 144:ef7eb2e8f9f7 652 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 653 } while(0)
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
<> 144:ef7eb2e8f9f7 656 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 659 || defined(STM32F103xG) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 660 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 661 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 662 SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
<> 144:ef7eb2e8f9f7 663 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 664 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
<> 144:ef7eb2e8f9f7 665 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 666 } while(0)
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
<> 144:ef7eb2e8f9f7 669 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 672 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 673 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 674 SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
<> 144:ef7eb2e8f9f7 675 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 676 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
<> 144:ef7eb2e8f9f7 677 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 678 } while(0)
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
<> 144:ef7eb2e8f9f7 682 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 685 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 686 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 687 SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
<> 144:ef7eb2e8f9f7 688 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 689 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
<> 144:ef7eb2e8f9f7 690 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 691 } while(0)
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
<> 144:ef7eb2e8f9f7 695 #endif /* STM32F105xC || STM32F107xC*/
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 #if defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 698 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 699 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 700 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 701 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 702 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
<> 144:ef7eb2e8f9f7 703 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 704 } while(0)
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 707 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 708 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 709 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 710 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
<> 144:ef7eb2e8f9f7 711 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 712 } while(0)
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 715 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 716 SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 717 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 718 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
<> 144:ef7eb2e8f9f7 719 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 720 } while(0)
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
<> 144:ef7eb2e8f9f7 723 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
<> 144:ef7eb2e8f9f7 724 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @brief Enable ETHERNET clock.
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 730 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 731 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 732 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
<> 144:ef7eb2e8f9f7 733 } while(0)
<> 144:ef7eb2e8f9f7 734 /**
<> 144:ef7eb2e8f9f7 735 * @brief Disable ETHERNET clock.
<> 144:ef7eb2e8f9f7 736 */
<> 144:ef7eb2e8f9f7 737 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
<> 144:ef7eb2e8f9f7 738 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 739 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 740 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
<> 144:ef7eb2e8f9f7 741 } while(0)
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 #endif /* STM32F107xC*/
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 /**
<> 144:ef7eb2e8f9f7 746 * @}
<> 144:ef7eb2e8f9f7 747 */
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 750 * @brief Get the enable or disable status of the AHB1 peripheral clock.
<> 144:ef7eb2e8f9f7 751 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 752 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 753 * using it.
<> 144:ef7eb2e8f9f7 754 * @{
<> 144:ef7eb2e8f9f7 755 */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 758 || defined(STM32F103xG) || defined(STM32F105xC) || defined (STM32F107xC)\
<> 144:ef7eb2e8f9f7 759 || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 760 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
<> 144:ef7eb2e8f9f7 761 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
<> 144:ef7eb2e8f9f7 762 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F105xC || STM32F107xC || STM32F100xE */
<> 144:ef7eb2e8f9f7 763 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 764 || defined(STM32F103xG) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 765 #define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
<> 144:ef7eb2e8f9f7 766 #define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
<> 144:ef7eb2e8f9f7 767 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 768 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 769 #define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
<> 144:ef7eb2e8f9f7 770 #define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
<> 144:ef7eb2e8f9f7 771 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 772 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 773 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
<> 144:ef7eb2e8f9f7 774 #define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
<> 144:ef7eb2e8f9f7 775 #endif /* STM32F105xC || STM32F107xC*/
<> 144:ef7eb2e8f9f7 776 #if defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 777 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
<> 144:ef7eb2e8f9f7 778 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
<> 144:ef7eb2e8f9f7 779 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
<> 144:ef7eb2e8f9f7 780 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
<> 144:ef7eb2e8f9f7 781 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
<> 144:ef7eb2e8f9f7 782 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
<> 144:ef7eb2e8f9f7 783 #endif /* STM32F107xC*/
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 /**
<> 144:ef7eb2e8f9f7 786 * @}
<> 144:ef7eb2e8f9f7 787 */
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
<> 144:ef7eb2e8f9f7 790 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<> 144:ef7eb2e8f9f7 791 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 792 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 793 * using it.
<> 144:ef7eb2e8f9f7 794 * @{
<> 144:ef7eb2e8f9f7 795 */
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 798 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 799 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 800 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 801 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<> 144:ef7eb2e8f9f7 802 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 803 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
<> 144:ef7eb2e8f9f7 804 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 805 } while(0)
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
<> 144:ef7eb2e8f9f7 808 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
<> 144:ef7eb2e8f9f7 811 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
<> 144:ef7eb2e8f9f7 812 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 813 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 814 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 815 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 816 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 144:ef7eb2e8f9f7 817 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 818 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
<> 144:ef7eb2e8f9f7 819 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 820 } while(0)
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 823 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 824 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 825 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 826 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
<> 144:ef7eb2e8f9f7 827 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 828 } while(0)
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 831 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 832 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 833 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 834 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
<> 144:ef7eb2e8f9f7 835 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 836 } while(0)
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 839 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 840 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 841 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 842 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
<> 144:ef7eb2e8f9f7 843 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 844 } while(0)
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
<> 144:ef7eb2e8f9f7 847 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
<> 144:ef7eb2e8f9f7 848 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
<> 144:ef7eb2e8f9f7 849 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
<> 144:ef7eb2e8f9f7 850 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 851
<> 144:ef7eb2e8f9f7 852 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 853 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 854 #define __HAL_RCC_USB_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 855 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 856 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 857 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 858 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
<> 144:ef7eb2e8f9f7 859 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 860 } while(0)
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
<> 144:ef7eb2e8f9f7 863 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 866 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 867 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 868 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 869 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 870 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 871 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 872 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 873 } while(0)
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 876 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 877 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 878 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 879 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 880 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 881 } while(0)
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 884 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 885 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 886 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 887 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 888 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 889 } while(0)
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 892 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 894 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 896 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 897 } while(0)
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 900 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 902 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 904 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 905 } while(0)
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 908 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 910 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 912 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 913 } while(0)
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 916 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 918 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 920 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 921 } while(0)
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<> 144:ef7eb2e8f9f7 924 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 144:ef7eb2e8f9f7 925 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 144:ef7eb2e8f9f7 926 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<> 144:ef7eb2e8f9f7 927 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<> 144:ef7eb2e8f9f7 928 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<> 144:ef7eb2e8f9f7 929 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 144:ef7eb2e8f9f7 930 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 #if defined(STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 933 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 934 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 935 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 936 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 937 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
<> 144:ef7eb2e8f9f7 938 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 939 } while(0)
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 942 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 943 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 944 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 945 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
<> 144:ef7eb2e8f9f7 946 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 947 } while(0)
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 950 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 951 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 952 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 953 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
<> 144:ef7eb2e8f9f7 954 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 955 } while(0)
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 958 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 959 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 960 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 961 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
<> 144:ef7eb2e8f9f7 962 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 963 } while(0)
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
<> 144:ef7eb2e8f9f7 966 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
<> 144:ef7eb2e8f9f7 967 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
<> 144:ef7eb2e8f9f7 968 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
<> 144:ef7eb2e8f9f7 969 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 #ifdef STM32F100xE
<> 144:ef7eb2e8f9f7 972 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 973 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 975 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
<> 144:ef7eb2e8f9f7 977 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 978 } while(0)
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 981 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 983 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 985 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 986 } while(0)
<> 144:ef7eb2e8f9f7 987
<> 144:ef7eb2e8f9f7 988 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 989 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 990 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 991 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 992 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 993 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 994 } while(0)
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 997 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 998 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 999 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1000 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 1001 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1002 } while(0)
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1005 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1006 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 1007 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1008 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
<> 144:ef7eb2e8f9f7 1009 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1010 } while(0)
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1013 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1014 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 1015 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1016 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
<> 144:ef7eb2e8f9f7 1017 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1018 } while(0)
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1021 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1022 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 1023 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1024 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
<> 144:ef7eb2e8f9f7 1025 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1026 } while(0)
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
<> 144:ef7eb2e8f9f7 1029 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<> 144:ef7eb2e8f9f7 1030 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<> 144:ef7eb2e8f9f7 1031 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<> 144:ef7eb2e8f9f7 1032 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
<> 144:ef7eb2e8f9f7 1033 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
<> 144:ef7eb2e8f9f7 1034 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
<> 144:ef7eb2e8f9f7 1035 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1038 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1039 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1040 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 144:ef7eb2e8f9f7 1041 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1042 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
<> 144:ef7eb2e8f9f7 1043 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1044 } while(0)
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
<> 144:ef7eb2e8f9f7 1047 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1048
<> 144:ef7eb2e8f9f7 1049 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1050 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1051 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1052 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 1053 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1054 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
<> 144:ef7eb2e8f9f7 1055 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1056 } while(0)
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1059 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1060 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 1061 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1062 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
<> 144:ef7eb2e8f9f7 1063 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1064 } while(0)
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1067 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1068 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 1069 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1070 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
<> 144:ef7eb2e8f9f7 1071 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1072 } while(0)
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
<> 144:ef7eb2e8f9f7 1075 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
<> 144:ef7eb2e8f9f7 1076 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
<> 144:ef7eb2e8f9f7 1077 #endif /* STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1078
<> 144:ef7eb2e8f9f7 1079 /**
<> 144:ef7eb2e8f9f7 1080 * @}
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082
<> 144:ef7eb2e8f9f7 1083 /** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1084 * @brief Get the enable or disable status of the APB1 peripheral clock.
<> 144:ef7eb2e8f9f7 1085 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1086 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1087 * using it.
<> 144:ef7eb2e8f9f7 1088 * @{
<> 144:ef7eb2e8f9f7 1089 */
<> 144:ef7eb2e8f9f7 1090
<> 144:ef7eb2e8f9f7 1091 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 1092 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1093 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
<> 144:ef7eb2e8f9f7 1094 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
<> 144:ef7eb2e8f9f7 1095 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1096 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
<> 144:ef7eb2e8f9f7 1097 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
<> 144:ef7eb2e8f9f7 1098 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 1099 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1100 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1101 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1102 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1103 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1104 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1105 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1106 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1107 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1108 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1109 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 1110 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1111 #define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
<> 144:ef7eb2e8f9f7 1112 #define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
<> 144:ef7eb2e8f9f7 1113 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1114 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 1115 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1116 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1117 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1118 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1119 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1120 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1121 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1122 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1123 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1124 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1125 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1126 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1127 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1128 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<> 144:ef7eb2e8f9f7 1129 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
<> 144:ef7eb2e8f9f7 1130 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1131 #if defined(STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 1132 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
<> 144:ef7eb2e8f9f7 1133 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
<> 144:ef7eb2e8f9f7 1134 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
<> 144:ef7eb2e8f9f7 1135 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
<> 144:ef7eb2e8f9f7 1136 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
<> 144:ef7eb2e8f9f7 1137 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
<> 144:ef7eb2e8f9f7 1138 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
<> 144:ef7eb2e8f9f7 1139 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
<> 144:ef7eb2e8f9f7 1140 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1141 #ifdef STM32F100xE
<> 144:ef7eb2e8f9f7 1142 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1143 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1144 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<> 144:ef7eb2e8f9f7 1145 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
<> 144:ef7eb2e8f9f7 1146 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<> 144:ef7eb2e8f9f7 1147 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
<> 144:ef7eb2e8f9f7 1148 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<> 144:ef7eb2e8f9f7 1149 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
<> 144:ef7eb2e8f9f7 1150 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1151 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1152 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
<> 144:ef7eb2e8f9f7 1153 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
<> 144:ef7eb2e8f9f7 1154 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
<> 144:ef7eb2e8f9f7 1155 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
<> 144:ef7eb2e8f9f7 1156 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1157 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1158 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1159 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1160 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
<> 144:ef7eb2e8f9f7 1161 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
<> 144:ef7eb2e8f9f7 1162 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1163 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1164 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
<> 144:ef7eb2e8f9f7 1165 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
<> 144:ef7eb2e8f9f7 1166 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
<> 144:ef7eb2e8f9f7 1167 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
<> 144:ef7eb2e8f9f7 1168 #endif /* STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * @}
<> 144:ef7eb2e8f9f7 1172 */
<> 144:ef7eb2e8f9f7 1173
<> 144:ef7eb2e8f9f7 1174 /** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
<> 144:ef7eb2e8f9f7 1175 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<> 144:ef7eb2e8f9f7 1176 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1177 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1178 * using it.
<> 144:ef7eb2e8f9f7 1179 * @{
<> 144:ef7eb2e8f9f7 1180 */
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1183 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 1184 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1185 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1186 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1187 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<> 144:ef7eb2e8f9f7 1188 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1189 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
<> 144:ef7eb2e8f9f7 1190 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1191 } while(0)
<> 144:ef7eb2e8f9f7 1192
<> 144:ef7eb2e8f9f7 1193 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
<> 144:ef7eb2e8f9f7 1194 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1195
<> 144:ef7eb2e8f9f7 1196 #if defined(STM32F100xB) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1197 #define __HAL_RCC_TIM15_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1198 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1199 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1200 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1201 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
<> 144:ef7eb2e8f9f7 1202 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1203 } while(0)
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 #define __HAL_RCC_TIM16_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1206 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1207 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
<> 144:ef7eb2e8f9f7 1208 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1209 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
<> 144:ef7eb2e8f9f7 1210 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1211 } while(0)
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 #define __HAL_RCC_TIM17_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1214 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1215 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
<> 144:ef7eb2e8f9f7 1216 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1217 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
<> 144:ef7eb2e8f9f7 1218 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1219 } while(0)
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 #define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
<> 144:ef7eb2e8f9f7 1222 #define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
<> 144:ef7eb2e8f9f7 1223 #define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
<> 144:ef7eb2e8f9f7 1224 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
<> 144:ef7eb2e8f9f7 1227 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1228 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 1229 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1230 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1231 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1232 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
<> 144:ef7eb2e8f9f7 1233 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1234 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
<> 144:ef7eb2e8f9f7 1235 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1236 } while(0)
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
<> 144:ef7eb2e8f9f7 1239 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 1242 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1243 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1244 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1245 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
<> 144:ef7eb2e8f9f7 1246 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1247 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
<> 144:ef7eb2e8f9f7 1248 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1249 } while(0)
<> 144:ef7eb2e8f9f7 1250
<> 144:ef7eb2e8f9f7 1251 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1252 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1253 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
<> 144:ef7eb2e8f9f7 1254 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1255 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
<> 144:ef7eb2e8f9f7 1256 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1257 } while(0)
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
<> 144:ef7eb2e8f9f7 1260 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
<> 144:ef7eb2e8f9f7 1261 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1264 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1265 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1266 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<> 144:ef7eb2e8f9f7 1267 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1268 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
<> 144:ef7eb2e8f9f7 1269 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1270 } while(0)
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1273 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1274 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<> 144:ef7eb2e8f9f7 1275 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1276 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
<> 144:ef7eb2e8f9f7 1277 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1278 } while(0)
<> 144:ef7eb2e8f9f7 1279
<> 144:ef7eb2e8f9f7 1280 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
<> 144:ef7eb2e8f9f7 1281 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
<> 144:ef7eb2e8f9f7 1282 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1283
<> 144:ef7eb2e8f9f7 1284 #if defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1285 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1286 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1287 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
<> 144:ef7eb2e8f9f7 1288 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1289 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
<> 144:ef7eb2e8f9f7 1290 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1291 } while(0)
<> 144:ef7eb2e8f9f7 1292
<> 144:ef7eb2e8f9f7 1293 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1294 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1295 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
<> 144:ef7eb2e8f9f7 1296 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1297 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
<> 144:ef7eb2e8f9f7 1298 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1299 } while(0)
<> 144:ef7eb2e8f9f7 1300
<> 144:ef7eb2e8f9f7 1301 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
<> 144:ef7eb2e8f9f7 1302 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
<> 144:ef7eb2e8f9f7 1303 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1304
<> 144:ef7eb2e8f9f7 1305 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1306 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1307 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1308 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 144:ef7eb2e8f9f7 1309 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1310 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
<> 144:ef7eb2e8f9f7 1311 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1312 } while(0)
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1315 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1316 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 144:ef7eb2e8f9f7 1317 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1318 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
<> 144:ef7eb2e8f9f7 1319 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1320 } while(0)
<> 144:ef7eb2e8f9f7 1321
<> 144:ef7eb2e8f9f7 1322 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
<> 144:ef7eb2e8f9f7 1323 __IO uint32_t tmpreg; \
<> 144:ef7eb2e8f9f7 1324 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 144:ef7eb2e8f9f7 1325 /* Delay after an RCC peripheral clock enabling */ \
<> 144:ef7eb2e8f9f7 1326 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
<> 144:ef7eb2e8f9f7 1327 UNUSED(tmpreg); \
<> 144:ef7eb2e8f9f7 1328 } while(0)
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
<> 144:ef7eb2e8f9f7 1331 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
<> 144:ef7eb2e8f9f7 1332 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
<> 144:ef7eb2e8f9f7 1333 #endif /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335 /**
<> 144:ef7eb2e8f9f7 1336 * @}
<> 144:ef7eb2e8f9f7 1337 */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
<> 144:ef7eb2e8f9f7 1340 * @brief Get the enable or disable status of the APB2 peripheral clock.
<> 144:ef7eb2e8f9f7 1341 * @note After reset, the peripheral clock (used for registers read/write access)
<> 144:ef7eb2e8f9f7 1342 * is disabled and the application software has to enable this clock before
<> 144:ef7eb2e8f9f7 1343 * using it.
<> 144:ef7eb2e8f9f7 1344 * @{
<> 144:ef7eb2e8f9f7 1345 */
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1348 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 1349 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1350 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
<> 144:ef7eb2e8f9f7 1351 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
<> 144:ef7eb2e8f9f7 1352 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1353 #if defined(STM32F100xB) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1354 #define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
<> 144:ef7eb2e8f9f7 1355 #define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
<> 144:ef7eb2e8f9f7 1356 #define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
<> 144:ef7eb2e8f9f7 1357 #define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
<> 144:ef7eb2e8f9f7 1358 #define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
<> 144:ef7eb2e8f9f7 1359 #define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
<> 144:ef7eb2e8f9f7 1360 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1361 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
<> 144:ef7eb2e8f9f7 1362 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1363 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 1364 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1365 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
<> 144:ef7eb2e8f9f7 1366 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
<> 144:ef7eb2e8f9f7 1367 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1368 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 1369 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1370 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
<> 144:ef7eb2e8f9f7 1371 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
<> 144:ef7eb2e8f9f7 1372 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
<> 144:ef7eb2e8f9f7 1373 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
<> 144:ef7eb2e8f9f7 1374 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1375 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1376 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
<> 144:ef7eb2e8f9f7 1377 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
<> 144:ef7eb2e8f9f7 1378 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
<> 144:ef7eb2e8f9f7 1379 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
<> 144:ef7eb2e8f9f7 1380 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1381 #if defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1382 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
<> 144:ef7eb2e8f9f7 1383 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
<> 144:ef7eb2e8f9f7 1384 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
<> 144:ef7eb2e8f9f7 1385 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
<> 144:ef7eb2e8f9f7 1386 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1387 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1388 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
<> 144:ef7eb2e8f9f7 1389 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
<> 144:ef7eb2e8f9f7 1390 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
<> 144:ef7eb2e8f9f7 1391 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
<> 144:ef7eb2e8f9f7 1392 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
<> 144:ef7eb2e8f9f7 1393 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
<> 144:ef7eb2e8f9f7 1394 #endif /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 1395
<> 144:ef7eb2e8f9f7 1396 /**
<> 144:ef7eb2e8f9f7 1397 * @}
<> 144:ef7eb2e8f9f7 1398 */
<> 144:ef7eb2e8f9f7 1399
<> 144:ef7eb2e8f9f7 1400 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1401 /** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
<> 144:ef7eb2e8f9f7 1402 * @brief Force or release AHB peripheral reset.
<> 144:ef7eb2e8f9f7 1403 * @{
<> 144:ef7eb2e8f9f7 1404 */
<> 144:ef7eb2e8f9f7 1405 #define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFFU)
<> 144:ef7eb2e8f9f7 1406 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_OTGFSRST))
<> 144:ef7eb2e8f9f7 1407 #if defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1408 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ETHMACRST))
<> 144:ef7eb2e8f9f7 1409 #endif /* STM32F107xC */
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 #define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
<> 144:ef7eb2e8f9f7 1412 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
<> 144:ef7eb2e8f9f7 1413 #if defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1414 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
<> 144:ef7eb2e8f9f7 1415 #endif /* STM32F107xC */
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /**
<> 144:ef7eb2e8f9f7 1418 * @}
<> 144:ef7eb2e8f9f7 1419 */
<> 144:ef7eb2e8f9f7 1420 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1421
<> 144:ef7eb2e8f9f7 1422 /** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
<> 144:ef7eb2e8f9f7 1423 * @brief Force or release APB1 peripheral reset.
<> 144:ef7eb2e8f9f7 1424 * @{
<> 144:ef7eb2e8f9f7 1425 */
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 1428 || defined(STM32F103xG) || defined(STM32F105xC) ||defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1429 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
<> 144:ef7eb2e8f9f7 1430
<> 144:ef7eb2e8f9f7 1431 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
<> 144:ef7eb2e8f9f7 1432 #endif /* STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1433
<> 144:ef7eb2e8f9f7 1434 #if defined(STM32F100xB) || defined(STM32F100xE) || defined(STM32F101xB)\
<> 144:ef7eb2e8f9f7 1435 || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F102xB)\
<> 144:ef7eb2e8f9f7 1436 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)\
<> 144:ef7eb2e8f9f7 1437 || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1438 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
<> 144:ef7eb2e8f9f7 1439 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1440 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1441 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1442
<> 144:ef7eb2e8f9f7 1443 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
<> 144:ef7eb2e8f9f7 1444 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
<> 144:ef7eb2e8f9f7 1445 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
<> 144:ef7eb2e8f9f7 1446 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
<> 144:ef7eb2e8f9f7 1447 #endif /* STM32F100xB || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1448
<> 144:ef7eb2e8f9f7 1449 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 1450 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1451 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1452 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
<> 144:ef7eb2e8f9f7 1453 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1454
<> 144:ef7eb2e8f9f7 1455 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 1456 || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1457 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1458 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1459 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1460 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1461 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1462 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1463 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1464
<> 144:ef7eb2e8f9f7 1465 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1466 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1467 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1468 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1469 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1470 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1471 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1472 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 #if defined(STM32F100xB) || defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 1475 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1476 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1477 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1478 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
<> 144:ef7eb2e8f9f7 1481 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
<> 144:ef7eb2e8f9f7 1482 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
<> 144:ef7eb2e8f9f7 1483 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
<> 144:ef7eb2e8f9f7 1484 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 #if defined (STM32F100xE)
<> 144:ef7eb2e8f9f7 1487 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1488 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1489 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1490 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1491 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1492 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1493 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
<> 144:ef7eb2e8f9f7 1496 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1497 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1498 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1499 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
<> 144:ef7eb2e8f9f7 1500 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
<> 144:ef7eb2e8f9f7 1501 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
<> 144:ef7eb2e8f9f7 1502 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1503
<> 144:ef7eb2e8f9f7 1504 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1505 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
<> 144:ef7eb2e8f9f7 1506
<> 144:ef7eb2e8f9f7 1507 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
<> 144:ef7eb2e8f9f7 1508 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1511 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1512 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1513 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1514
<> 144:ef7eb2e8f9f7 1515 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
<> 144:ef7eb2e8f9f7 1516 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
<> 144:ef7eb2e8f9f7 1517 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
<> 144:ef7eb2e8f9f7 1518 #endif /* STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 /**
<> 144:ef7eb2e8f9f7 1521 * @}
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
<> 144:ef7eb2e8f9f7 1525 * @brief Force or release APB2 peripheral reset.
<> 144:ef7eb2e8f9f7 1526 * @{
<> 144:ef7eb2e8f9f7 1527 */
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 #if defined(STM32F101xG) || defined(STM32F103x6) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1530 || defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F103xE)\
<> 144:ef7eb2e8f9f7 1531 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1532 #define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC2RST))
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 #define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
<> 144:ef7eb2e8f9f7 1535 #endif /* STM32F101xG || STM32F103x6 || STM32F103xB || STM32F105xC || STM32F107xC || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 #if defined(STM32F100xB) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1538 #define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1539 #define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM16RST))
<> 144:ef7eb2e8f9f7 1540 #define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM17RST))
<> 144:ef7eb2e8f9f7 1541
<> 144:ef7eb2e8f9f7 1542 #define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
<> 144:ef7eb2e8f9f7 1543 #define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
<> 144:ef7eb2e8f9f7 1544 #define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
<> 144:ef7eb2e8f9f7 1545 #endif /* STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 #if defined(STM32F100xE) || defined(STM32F101xB) || defined(STM32F101xE)\
<> 144:ef7eb2e8f9f7 1548 || defined(STM32F101xG) || defined(STM32F100xB) || defined(STM32F103xB)\
<> 144:ef7eb2e8f9f7 1549 || defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC)\
<> 144:ef7eb2e8f9f7 1550 || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1551 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPERST))
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
<> 144:ef7eb2e8f9f7 1554 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG)\
<> 144:ef7eb2e8f9f7 1557 || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1558 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
<> 144:ef7eb2e8f9f7 1559 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
<> 144:ef7eb2e8f9f7 1562 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
<> 144:ef7eb2e8f9f7 1563 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1564
<> 144:ef7eb2e8f9f7 1565 #if defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1566 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
<> 144:ef7eb2e8f9f7 1567 #define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC3RST))
<> 144:ef7eb2e8f9f7 1568
<> 144:ef7eb2e8f9f7 1569 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
<> 144:ef7eb2e8f9f7 1570 #define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
<> 144:ef7eb2e8f9f7 1571 #endif /* STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 #if defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1574 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPFRST))
<> 144:ef7eb2e8f9f7 1575 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPGRST))
<> 144:ef7eb2e8f9f7 1576
<> 144:ef7eb2e8f9f7 1577 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
<> 144:ef7eb2e8f9f7 1578 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
<> 144:ef7eb2e8f9f7 1579 #endif /* STM32F100xE */
<> 144:ef7eb2e8f9f7 1580
<> 144:ef7eb2e8f9f7 1581 #if defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1582 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
<> 144:ef7eb2e8f9f7 1583 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
<> 144:ef7eb2e8f9f7 1584 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
<> 144:ef7eb2e8f9f7 1587 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
<> 144:ef7eb2e8f9f7 1588 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
<> 144:ef7eb2e8f9f7 1589 #endif /* STM32F101xG || STM32F103xG*/
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /**
<> 144:ef7eb2e8f9f7 1592 * @}
<> 144:ef7eb2e8f9f7 1593 */
<> 144:ef7eb2e8f9f7 1594
<> 144:ef7eb2e8f9f7 1595 /** @defgroup RCCEx_HSE_Configuration HSE Configuration
<> 144:ef7eb2e8f9f7 1596 * @{
<> 144:ef7eb2e8f9f7 1597 */
<> 144:ef7eb2e8f9f7 1598
<> 144:ef7eb2e8f9f7 1599 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 1600 || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1601 /**
<> 144:ef7eb2e8f9f7 1602 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
<> 144:ef7eb2e8f9f7 1603 * @note Predivision factor can not be changed if PLL is used as system clock
<> 144:ef7eb2e8f9f7 1604 * In this case, you have to select another source of the system clock, disable the PLL and
<> 144:ef7eb2e8f9f7 1605 * then change the HSE predivision factor.
<> 144:ef7eb2e8f9f7 1606 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
<> 144:ef7eb2e8f9f7 1607 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
<> 144:ef7eb2e8f9f7 1608 */
<> 144:ef7eb2e8f9f7 1609 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
<> 144:ef7eb2e8f9f7 1610 #else
<> 144:ef7eb2e8f9f7 1611 /**
<> 144:ef7eb2e8f9f7 1612 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
<> 144:ef7eb2e8f9f7 1613 * @note Predivision factor can not be changed if PLL is used as system clock
<> 144:ef7eb2e8f9f7 1614 * In this case, you have to select another source of the system clock, disable the PLL and
<> 144:ef7eb2e8f9f7 1615 * then change the HSE predivision factor.
<> 144:ef7eb2e8f9f7 1616 * @param __HSE_PREDIV_VALUE__ specifies the division value applied to HSE.
<> 144:ef7eb2e8f9f7 1617 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
<> 144:ef7eb2e8f9f7 1618 */
<> 144:ef7eb2e8f9f7 1619 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
<> 144:ef7eb2e8f9f7 1620 MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
<> 144:ef7eb2e8f9f7 1621
<> 144:ef7eb2e8f9f7 1622 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 #if defined(STM32F105xC) || defined(STM32F107xC) || defined(STM32F100xB)\
<> 144:ef7eb2e8f9f7 1625 || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 1626 /**
<> 144:ef7eb2e8f9f7 1627 * @brief Macro to get prediv1 factor for PLL.
<> 144:ef7eb2e8f9f7 1628 */
<> 144:ef7eb2e8f9f7 1629 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
<> 144:ef7eb2e8f9f7 1630
<> 144:ef7eb2e8f9f7 1631 #else
<> 144:ef7eb2e8f9f7 1632 /**
<> 144:ef7eb2e8f9f7 1633 * @brief Macro to get prediv1 factor for PLL.
<> 144:ef7eb2e8f9f7 1634 */
<> 144:ef7eb2e8f9f7 1635 #define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 /**
<> 144:ef7eb2e8f9f7 1640 * @}
<> 144:ef7eb2e8f9f7 1641 */
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1644 /** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
<> 144:ef7eb2e8f9f7 1645 * @{
<> 144:ef7eb2e8f9f7 1646 */
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 /** @brief Macros to enable the main PLLI2S.
<> 144:ef7eb2e8f9f7 1649 * @note After enabling the main PLLI2S, the application software should wait on
<> 144:ef7eb2e8f9f7 1650 * PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
<> 144:ef7eb2e8f9f7 1651 * be used as system clock source.
<> 144:ef7eb2e8f9f7 1652 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1653 */
<> 144:ef7eb2e8f9f7 1654 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
<> 144:ef7eb2e8f9f7 1655
<> 144:ef7eb2e8f9f7 1656 /** @brief Macros to disable the main PLLI2S.
<> 144:ef7eb2e8f9f7 1657 * @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1658 */
<> 144:ef7eb2e8f9f7 1659 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
<> 144:ef7eb2e8f9f7 1660
<> 144:ef7eb2e8f9f7 1661 /** @brief macros to configure the main PLLI2S multiplication factor.
<> 144:ef7eb2e8f9f7 1662 * @note This function must be used only when the main PLLI2S is disabled.
<> 144:ef7eb2e8f9f7 1663 *
<> 144:ef7eb2e8f9f7 1664 * @param __PLLI2SMUL__ specifies the multiplication factor for PLLI2S VCO output clock
<> 144:ef7eb2e8f9f7 1665 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1666 * @arg @ref RCC_PLLI2S_MUL8 PLLI2SVCO = PLLI2S clock entry x 8
<> 144:ef7eb2e8f9f7 1667 * @arg @ref RCC_PLLI2S_MUL9 PLLI2SVCO = PLLI2S clock entry x 9
<> 144:ef7eb2e8f9f7 1668 * @arg @ref RCC_PLLI2S_MUL10 PLLI2SVCO = PLLI2S clock entry x 10
<> 144:ef7eb2e8f9f7 1669 * @arg @ref RCC_PLLI2S_MUL11 PLLI2SVCO = PLLI2S clock entry x 11
<> 144:ef7eb2e8f9f7 1670 * @arg @ref RCC_PLLI2S_MUL12 PLLI2SVCO = PLLI2S clock entry x 12
<> 144:ef7eb2e8f9f7 1671 * @arg @ref RCC_PLLI2S_MUL13 PLLI2SVCO = PLLI2S clock entry x 13
<> 144:ef7eb2e8f9f7 1672 * @arg @ref RCC_PLLI2S_MUL14 PLLI2SVCO = PLLI2S clock entry x 14
<> 144:ef7eb2e8f9f7 1673 * @arg @ref RCC_PLLI2S_MUL16 PLLI2SVCO = PLLI2S clock entry x 16
<> 144:ef7eb2e8f9f7 1674 * @arg @ref RCC_PLLI2S_MUL20 PLLI2SVCO = PLLI2S clock entry x 20
<> 144:ef7eb2e8f9f7 1675 *
<> 144:ef7eb2e8f9f7 1676 */
<> 144:ef7eb2e8f9f7 1677 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
<> 144:ef7eb2e8f9f7 1678 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 /**
<> 144:ef7eb2e8f9f7 1681 * @}
<> 144:ef7eb2e8f9f7 1682 */
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686 /** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
<> 144:ef7eb2e8f9f7 1687 * @brief Macros to configure clock source of different peripherals.
<> 144:ef7eb2e8f9f7 1688 * @{
<> 144:ef7eb2e8f9f7 1689 */
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6)\
<> 144:ef7eb2e8f9f7 1692 || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 1693 /** @brief Macro to configure the USB clock.
<> 144:ef7eb2e8f9f7 1694 * @param __USBCLKSOURCE__ specifies the USB clock source.
<> 144:ef7eb2e8f9f7 1695 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1696 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
<> 144:ef7eb2e8f9f7 1697 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
<> 144:ef7eb2e8f9f7 1698 */
<> 144:ef7eb2e8f9f7 1699 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1700 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /** @brief Macro to get the USB clock (USBCLK).
<> 144:ef7eb2e8f9f7 1703 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1704 * @arg @ref RCC_USBCLKSOURCE_PLL PLL clock divided by 1 selected as USB clock
<> 144:ef7eb2e8f9f7 1705 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV1_5 PLL clock divided by 1.5 selected as USB clock
<> 144:ef7eb2e8f9f7 1706 */
<> 144:ef7eb2e8f9f7 1707 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
<> 144:ef7eb2e8f9f7 1708
<> 144:ef7eb2e8f9f7 1709 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG */
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1712
<> 144:ef7eb2e8f9f7 1713 /** @brief Macro to configure the USB OTSclock.
<> 144:ef7eb2e8f9f7 1714 * @param __USBCLKSOURCE__ specifies the USB clock source.
<> 144:ef7eb2e8f9f7 1715 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1716 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
<> 144:ef7eb2e8f9f7 1717 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
<> 144:ef7eb2e8f9f7 1718 */
<> 144:ef7eb2e8f9f7 1719 #define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1720 MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1721
<> 144:ef7eb2e8f9f7 1722 /** @brief Macro to get the USB clock (USBCLK).
<> 144:ef7eb2e8f9f7 1723 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1724 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV2 PLL clock divided by 2 selected as USB OTG FS clock
<> 144:ef7eb2e8f9f7 1725 * @arg @ref RCC_USBCLKSOURCE_PLL_DIV3 PLL clock divided by 3 selected as USB OTG FS clock
<> 144:ef7eb2e8f9f7 1726 */
<> 144:ef7eb2e8f9f7 1727 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
<> 144:ef7eb2e8f9f7 1732 * @param __ADCCLKSOURCE__ specifies the ADC clock source.
<> 144:ef7eb2e8f9f7 1733 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1734 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
<> 144:ef7eb2e8f9f7 1735 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
<> 144:ef7eb2e8f9f7 1736 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
<> 144:ef7eb2e8f9f7 1737 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
<> 144:ef7eb2e8f9f7 1738 */
<> 144:ef7eb2e8f9f7 1739 #define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1740 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
<> 144:ef7eb2e8f9f7 1741
<> 144:ef7eb2e8f9f7 1742 /** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
<> 144:ef7eb2e8f9f7 1743 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1744 * @arg @ref RCC_ADCPCLK2_DIV2 PCLK2 clock divided by 2 selected as ADC clock
<> 144:ef7eb2e8f9f7 1745 * @arg @ref RCC_ADCPCLK2_DIV4 PCLK2 clock divided by 4 selected as ADC clock
<> 144:ef7eb2e8f9f7 1746 * @arg @ref RCC_ADCPCLK2_DIV6 PCLK2 clock divided by 6 selected as ADC clock
<> 144:ef7eb2e8f9f7 1747 * @arg @ref RCC_ADCPCLK2_DIV8 PCLK2 clock divided by 8 selected as ADC clock
<> 144:ef7eb2e8f9f7 1748 */
<> 144:ef7eb2e8f9f7 1749 #define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /**
<> 144:ef7eb2e8f9f7 1752 * @}
<> 144:ef7eb2e8f9f7 1753 */
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1756
<> 144:ef7eb2e8f9f7 1757 /** @addtogroup RCCEx_HSE_Configuration
<> 144:ef7eb2e8f9f7 1758 * @{
<> 144:ef7eb2e8f9f7 1759 */
<> 144:ef7eb2e8f9f7 1760
<> 144:ef7eb2e8f9f7 1761 /**
<> 144:ef7eb2e8f9f7 1762 * @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
<> 144:ef7eb2e8f9f7 1763 * @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
<> 144:ef7eb2e8f9f7 1764 * In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
<> 144:ef7eb2e8f9f7 1765 * then change the PREDIV2 factor.
<> 144:ef7eb2e8f9f7 1766 * @param __HSE_PREDIV2_VALUE__ specifies the PREDIV2 value applied to PLL2 & PLLI2S.
<> 144:ef7eb2e8f9f7 1767 * This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
<> 144:ef7eb2e8f9f7 1768 */
<> 144:ef7eb2e8f9f7 1769 #define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
<> 144:ef7eb2e8f9f7 1770 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
<> 144:ef7eb2e8f9f7 1771
<> 144:ef7eb2e8f9f7 1772 /**
<> 144:ef7eb2e8f9f7 1773 * @brief Macro to get prediv2 factor for PLL2 & PLL3.
<> 144:ef7eb2e8f9f7 1774 */
<> 144:ef7eb2e8f9f7 1775 #define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
<> 144:ef7eb2e8f9f7 1776
<> 144:ef7eb2e8f9f7 1777 /**
<> 144:ef7eb2e8f9f7 1778 * @}
<> 144:ef7eb2e8f9f7 1779 */
<> 144:ef7eb2e8f9f7 1780
<> 144:ef7eb2e8f9f7 1781 /** @addtogroup RCCEx_PLLI2S_Configuration
<> 144:ef7eb2e8f9f7 1782 * @{
<> 144:ef7eb2e8f9f7 1783 */
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /** @brief Macros to enable the main PLL2.
<> 144:ef7eb2e8f9f7 1786 * @note After enabling the main PLL2, the application software should wait on
<> 144:ef7eb2e8f9f7 1787 * PLL2RDY flag to be set indicating that PLL2 clock is stable and can
<> 144:ef7eb2e8f9f7 1788 * be used as system clock source.
<> 144:ef7eb2e8f9f7 1789 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1790 */
<> 144:ef7eb2e8f9f7 1791 #define __HAL_RCC_PLL2_ENABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = ENABLE)
<> 144:ef7eb2e8f9f7 1792
<> 144:ef7eb2e8f9f7 1793 /** @brief Macros to disable the main PLL2.
<> 144:ef7eb2e8f9f7 1794 * @note The main PLL2 can not be disabled if it is used indirectly as system clock source
<> 144:ef7eb2e8f9f7 1795 * @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
<> 144:ef7eb2e8f9f7 1796 */
<> 144:ef7eb2e8f9f7 1797 #define __HAL_RCC_PLL2_DISABLE() (*(__IO uint32_t *) RCC_CR_PLL2ON_BB = DISABLE)
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /** @brief macros to configure the main PLL2 multiplication factor.
<> 144:ef7eb2e8f9f7 1800 * @note This function must be used only when the main PLL2 is disabled.
<> 144:ef7eb2e8f9f7 1801 *
<> 144:ef7eb2e8f9f7 1802 * @param __PLL2MUL__ specifies the multiplication factor for PLL2 VCO output clock
<> 144:ef7eb2e8f9f7 1803 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1804 * @arg @ref RCC_PLL2_MUL8 PLL2VCO = PLL2 clock entry x 8
<> 144:ef7eb2e8f9f7 1805 * @arg @ref RCC_PLL2_MUL9 PLL2VCO = PLL2 clock entry x 9
<> 144:ef7eb2e8f9f7 1806 * @arg @ref RCC_PLL2_MUL10 PLL2VCO = PLL2 clock entry x 10
<> 144:ef7eb2e8f9f7 1807 * @arg @ref RCC_PLL2_MUL11 PLL2VCO = PLL2 clock entry x 11
<> 144:ef7eb2e8f9f7 1808 * @arg @ref RCC_PLL2_MUL12 PLL2VCO = PLL2 clock entry x 12
<> 144:ef7eb2e8f9f7 1809 * @arg @ref RCC_PLL2_MUL13 PLL2VCO = PLL2 clock entry x 13
<> 144:ef7eb2e8f9f7 1810 * @arg @ref RCC_PLL2_MUL14 PLL2VCO = PLL2 clock entry x 14
<> 144:ef7eb2e8f9f7 1811 * @arg @ref RCC_PLL2_MUL16 PLL2VCO = PLL2 clock entry x 16
<> 144:ef7eb2e8f9f7 1812 * @arg @ref RCC_PLL2_MUL20 PLL2VCO = PLL2 clock entry x 20
<> 144:ef7eb2e8f9f7 1813 *
<> 144:ef7eb2e8f9f7 1814 */
<> 144:ef7eb2e8f9f7 1815 #define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
<> 144:ef7eb2e8f9f7 1816 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
<> 144:ef7eb2e8f9f7 1817
<> 144:ef7eb2e8f9f7 1818 /**
<> 144:ef7eb2e8f9f7 1819 * @}
<> 144:ef7eb2e8f9f7 1820 */
<> 144:ef7eb2e8f9f7 1821
<> 144:ef7eb2e8f9f7 1822 /** @defgroup RCCEx_I2S_Configuration I2S Configuration
<> 144:ef7eb2e8f9f7 1823 * @brief Macros to configure clock source of I2S peripherals.
<> 144:ef7eb2e8f9f7 1824 * @{
<> 144:ef7eb2e8f9f7 1825 */
<> 144:ef7eb2e8f9f7 1826
<> 144:ef7eb2e8f9f7 1827 /** @brief Macro to configure the I2S2 clock.
<> 144:ef7eb2e8f9f7 1828 * @param __I2S2CLKSOURCE__ specifies the I2S2 clock source.
<> 144:ef7eb2e8f9f7 1829 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1830 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1831 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1832 */
<> 144:ef7eb2e8f9f7 1833 #define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1834 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1835
<> 144:ef7eb2e8f9f7 1836 /** @brief Macro to get the I2S2 clock (I2S2CLK).
<> 144:ef7eb2e8f9f7 1837 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1838 * @arg @ref RCC_I2S2CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1839 * @arg @ref RCC_I2S2CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1840 */
<> 144:ef7eb2e8f9f7 1841 #define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
<> 144:ef7eb2e8f9f7 1842
<> 144:ef7eb2e8f9f7 1843 /** @brief Macro to configure the I2S3 clock.
<> 144:ef7eb2e8f9f7 1844 * @param __I2S2CLKSOURCE__ specifies the I2S3 clock source.
<> 144:ef7eb2e8f9f7 1845 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1846 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1847 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1848 */
<> 144:ef7eb2e8f9f7 1849 #define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
<> 144:ef7eb2e8f9f7 1850 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /** @brief Macro to get the I2S3 clock (I2S3CLK).
<> 144:ef7eb2e8f9f7 1853 * @retval The clock source can be one of the following values:
<> 144:ef7eb2e8f9f7 1854 * @arg @ref RCC_I2S3CLKSOURCE_SYSCLK system clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1855 * @arg @ref RCC_I2S3CLKSOURCE_PLLI2S_VCO PLLI2S VCO clock selected as I2S3 clock entry
<> 144:ef7eb2e8f9f7 1856 */
<> 144:ef7eb2e8f9f7 1857 #define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /**
<> 144:ef7eb2e8f9f7 1860 * @}
<> 144:ef7eb2e8f9f7 1861 */
<> 144:ef7eb2e8f9f7 1862
<> 144:ef7eb2e8f9f7 1863 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1864 /**
<> 144:ef7eb2e8f9f7 1865 * @}
<> 144:ef7eb2e8f9f7 1866 */
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1869 /** @addtogroup RCCEx_Exported_Functions
<> 144:ef7eb2e8f9f7 1870 * @{
<> 144:ef7eb2e8f9f7 1871 */
<> 144:ef7eb2e8f9f7 1872
<> 144:ef7eb2e8f9f7 1873 /** @addtogroup RCCEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 1874 * @{
<> 144:ef7eb2e8f9f7 1875 */
<> 144:ef7eb2e8f9f7 1876
<> 144:ef7eb2e8f9f7 1877 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 1878 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
<> 144:ef7eb2e8f9f7 1879 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
<> 144:ef7eb2e8f9f7 1880
<> 144:ef7eb2e8f9f7 1881 /**
<> 144:ef7eb2e8f9f7 1882 * @}
<> 144:ef7eb2e8f9f7 1883 */
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 #if defined(STM32F105xC) || defined(STM32F107xC)
<> 144:ef7eb2e8f9f7 1886 /** @addtogroup RCCEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 1887 * @{
<> 144:ef7eb2e8f9f7 1888 */
<> 144:ef7eb2e8f9f7 1889 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
<> 144:ef7eb2e8f9f7 1890 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
<> 144:ef7eb2e8f9f7 1891
<> 144:ef7eb2e8f9f7 1892 /**
<> 144:ef7eb2e8f9f7 1893 * @}
<> 144:ef7eb2e8f9f7 1894 */
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /** @addtogroup RCCEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 1897 * @{
<> 144:ef7eb2e8f9f7 1898 */
<> 144:ef7eb2e8f9f7 1899 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
<> 144:ef7eb2e8f9f7 1900 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
<> 144:ef7eb2e8f9f7 1901
<> 144:ef7eb2e8f9f7 1902 /**
<> 144:ef7eb2e8f9f7 1903 * @}
<> 144:ef7eb2e8f9f7 1904 */
<> 144:ef7eb2e8f9f7 1905 #endif /* STM32F105xC || STM32F107xC */
<> 144:ef7eb2e8f9f7 1906
<> 144:ef7eb2e8f9f7 1907 /**
<> 144:ef7eb2e8f9f7 1908 * @}
<> 144:ef7eb2e8f9f7 1909 */
<> 144:ef7eb2e8f9f7 1910
<> 144:ef7eb2e8f9f7 1911 /**
<> 144:ef7eb2e8f9f7 1912 * @}
<> 144:ef7eb2e8f9f7 1913 */
<> 144:ef7eb2e8f9f7 1914
<> 144:ef7eb2e8f9f7 1915 /**
<> 144:ef7eb2e8f9f7 1916 * @}
<> 144:ef7eb2e8f9f7 1917 */
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1920 }
<> 144:ef7eb2e8f9f7 1921 #endif
<> 144:ef7eb2e8f9f7 1922
<> 144:ef7eb2e8f9f7 1923 #endif /* __STM32F1xx_HAL_RCC_EX_H */
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 1926