mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_nor.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_nor.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of NOR HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_NOR_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_NOR_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_ll_fsmc.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE)
<> 144:ef7eb2e8f9f7 54 /** @addtogroup NOR
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup NOR_Private_Constants
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* NOR device IDs addresses */
<> 144:ef7eb2e8f9f7 63 #define MC_ADDRESS ((uint16_t)0x0000)
<> 144:ef7eb2e8f9f7 64 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
<> 144:ef7eb2e8f9f7 65 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
<> 144:ef7eb2e8f9f7 66 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 /* NOR CFI IDs addresses */
<> 144:ef7eb2e8f9f7 69 #define CFI1_ADDRESS ((uint16_t)0x10)
<> 144:ef7eb2e8f9f7 70 #define CFI2_ADDRESS ((uint16_t)0x11)
<> 144:ef7eb2e8f9f7 71 #define CFI3_ADDRESS ((uint16_t)0x12)
<> 144:ef7eb2e8f9f7 72 #define CFI4_ADDRESS ((uint16_t)0x13)
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* NOR operation wait timeout */
<> 144:ef7eb2e8f9f7 75 #define NOR_TMEOUT ((uint16_t)0xFFFF)
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /* NOR memory data width */
<> 144:ef7eb2e8f9f7 78 #define NOR_MEMORY_8B ((uint8_t)0x0)
<> 144:ef7eb2e8f9f7 79 #define NOR_MEMORY_16B ((uint8_t)0x1)
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 /* NOR memory device read/write start address */
<> 144:ef7eb2e8f9f7 82 #define NOR_MEMORY_ADRESS1 FSMC_BANK1_1
<> 144:ef7eb2e8f9f7 83 #define NOR_MEMORY_ADRESS2 FSMC_BANK1_2
<> 144:ef7eb2e8f9f7 84 #define NOR_MEMORY_ADRESS3 FSMC_BANK1_3
<> 144:ef7eb2e8f9f7 85 #define NOR_MEMORY_ADRESS4 FSMC_BANK1_4
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /**
<> 144:ef7eb2e8f9f7 88 * @}
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @addtogroup NOR_Private_Macros
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @brief NOR memory address shifting.
<> 144:ef7eb2e8f9f7 97 * @param __NOR_ADDRESS: NOR base address
<> 144:ef7eb2e8f9f7 98 * @param __NOR_MEMORY_WIDTH_: NOR memory width
<> 144:ef7eb2e8f9f7 99 * @param __ADDRESS__: NOR memory address
<> 144:ef7eb2e8f9f7 100 * @retval NOR shifted address value
<> 144:ef7eb2e8f9f7 101 */
<> 144:ef7eb2e8f9f7 102 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
<> 144:ef7eb2e8f9f7 103 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
<> 144:ef7eb2e8f9f7 104 ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
<> 144:ef7eb2e8f9f7 105 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /**
<> 144:ef7eb2e8f9f7 108 * @brief NOR memory write data to specified address.
<> 144:ef7eb2e8f9f7 109 * @param __ADDRESS__: NOR memory address
<> 144:ef7eb2e8f9f7 110 * @param __DATA__: Data to write
<> 144:ef7eb2e8f9f7 111 * @retval None
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113 #define NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Exported typedef ----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /** @defgroup NOR_Exported_Types NOR Exported Types
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @brief HAL SRAM State structures definition
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 typedef enum
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 130 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
<> 144:ef7eb2e8f9f7 131 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
<> 144:ef7eb2e8f9f7 132 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
<> 144:ef7eb2e8f9f7 133 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
<> 144:ef7eb2e8f9f7 134 }HAL_NOR_StateTypeDef;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /**
<> 144:ef7eb2e8f9f7 137 * @brief FSMC NOR Status typedef
<> 144:ef7eb2e8f9f7 138 */
<> 144:ef7eb2e8f9f7 139 typedef enum
<> 144:ef7eb2e8f9f7 140 {
<> 144:ef7eb2e8f9f7 141 HAL_NOR_STATUS_SUCCESS = 0,
<> 144:ef7eb2e8f9f7 142 HAL_NOR_STATUS_ONGOING,
<> 144:ef7eb2e8f9f7 143 HAL_NOR_STATUS_ERROR,
<> 144:ef7eb2e8f9f7 144 HAL_NOR_STATUS_TIMEOUT
<> 144:ef7eb2e8f9f7 145 }HAL_NOR_StatusTypeDef;
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /**
<> 144:ef7eb2e8f9f7 148 * @brief FSMC NOR ID typedef
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 typedef struct
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 uint16_t Device_Code1;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 uint16_t Device_Code2;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
<> 144:ef7eb2e8f9f7 159 These codes can be accessed by performing read operations with specific
<> 144:ef7eb2e8f9f7 160 control signals and addresses set.They can also be accessed by issuing
<> 144:ef7eb2e8f9f7 161 an Auto Select command */
<> 144:ef7eb2e8f9f7 162 }NOR_IDTypeDef;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /**
<> 144:ef7eb2e8f9f7 165 * @brief FSMC NOR CFI typedef
<> 144:ef7eb2e8f9f7 166 */
<> 144:ef7eb2e8f9f7 167 typedef struct
<> 144:ef7eb2e8f9f7 168 {
<> 144:ef7eb2e8f9f7 169 /*!< Defines the information stored in the memory's Common flash interface
<> 144:ef7eb2e8f9f7 170 which contains a description of various electrical and timing parameters,
<> 144:ef7eb2e8f9f7 171 density information and functions supported by the memory */
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 uint16_t CFI_1;
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 uint16_t CFI_2;
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 uint16_t CFI_3;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 uint16_t CFI_4;
<> 144:ef7eb2e8f9f7 180 }NOR_CFITypeDef;
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief NOR handle Structure definition
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 typedef struct
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 FSMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 FSMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 FSMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 HAL_LockTypeDef Lock; /*!< NOR locking object */
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 }NOR_HandleTypeDef;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /**
<> 144:ef7eb2e8f9f7 200 * @}
<> 144:ef7eb2e8f9f7 201 */
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 204 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 /** @defgroup NOR_Exported_macro NOR Exported Macros
<> 144:ef7eb2e8f9f7 207 * @{
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /** @brief Reset NOR handle state
<> 144:ef7eb2e8f9f7 211 * @param __HANDLE__: NOR handle
<> 144:ef7eb2e8f9f7 212 * @retval None
<> 144:ef7eb2e8f9f7 213 */
<> 144:ef7eb2e8f9f7 214 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /**
<> 144:ef7eb2e8f9f7 217 * @}
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 221 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 /** @addtogroup NOR_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 226 * @{
<> 144:ef7eb2e8f9f7 227 */
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* Initialization/de-initialization functions **********************************/
<> 144:ef7eb2e8f9f7 230 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
<> 144:ef7eb2e8f9f7 231 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 232 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 233 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 234 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 144:ef7eb2e8f9f7 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @addtogroup NOR_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243
<> 144:ef7eb2e8f9f7 244 /* I/O operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 245 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
<> 144:ef7eb2e8f9f7 246 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 247 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
<> 144:ef7eb2e8f9f7 248 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
<> 144:ef7eb2e8f9f7 251 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
<> 144:ef7eb2e8f9f7 254 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
<> 144:ef7eb2e8f9f7 255 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /**
<> 144:ef7eb2e8f9f7 258 * @}
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /** @addtogroup NOR_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 262 * @{
<> 144:ef7eb2e8f9f7 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* NOR Control functions *****************************************************/
<> 144:ef7eb2e8f9f7 266 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 267 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /** @addtogroup NOR_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 274 * @{
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /* NOR State functions ********************************************************/
<> 144:ef7eb2e8f9f7 278 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
<> 144:ef7eb2e8f9f7 279 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /**
<> 144:ef7eb2e8f9f7 286 * @}
<> 144:ef7eb2e8f9f7 287 */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @}
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293
<> 144:ef7eb2e8f9f7 294 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */
<> 144:ef7eb2e8f9f7 295
<> 144:ef7eb2e8f9f7 296 /**
<> 144:ef7eb2e8f9f7 297 * @}
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302 #endif
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 #endif /* __STM32F1xx_HAL_NOR_H */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/