mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_gpio.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
150:02e0a0aed4ec
Child:
179:b0033dcd6934
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_gpio.c
<> 144:ef7eb2e8f9f7 3 * @brief General Purpose IO (GPIO) peripheral API
<> 144:ef7eb2e8f9f7 4 * devices.
<> 161:2cc1468da177 5 * @version 5.1.2
<> 144:ef7eb2e8f9f7 6 *******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 9 *******************************************************************************
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 12 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 13 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 16 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 18 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 19 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 22 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 23 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 24 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 25 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 26 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 29 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 30 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 ******************************************************************************/
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 #include "em_gpio.h"
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #if defined(GPIO_COUNT) && (GPIO_COUNT > 0)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 /***************************************************************************//**
<> 150:02e0a0aed4ec 40 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 41 * @{
<> 144:ef7eb2e8f9f7 42 ******************************************************************************/
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 45 * @addtogroup GPIO
<> 144:ef7eb2e8f9f7 46 * @brief General Purpose Input/Output (GPIO) API
<> 150:02e0a0aed4ec 47 * @details
<> 150:02e0a0aed4ec 48 * This module contains functions to control the GPIO peripheral of Silicon
<> 150:02e0a0aed4ec 49 * Labs 32-bit MCUs and SoCs. The GPIO peripheral is used for pin configuration
<> 150:02e0a0aed4ec 50 * and direct pin manipulation and sensing as well as routing for peripheral
<> 150:02e0a0aed4ec 51 * pin connections.
<> 144:ef7eb2e8f9f7 52 * @{
<> 144:ef7eb2e8f9f7 53 ******************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /*******************************************************************************
<> 144:ef7eb2e8f9f7 56 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 57 ******************************************************************************/
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** Validation of pin typically usable in assert statements. */
<> 144:ef7eb2e8f9f7 62 #define GPIO_DRIVEMODE_VALID(mode) ((mode) <= 3)
<> 144:ef7eb2e8f9f7 63 #define GPIO_STRENGHT_VALID(strenght) (!((strenght) & \
<> 144:ef7eb2e8f9f7 64 ~(_GPIO_P_CTRL_DRIVESTRENGTH_MASK \
<> 144:ef7eb2e8f9f7 65 | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK)))
<> 144:ef7eb2e8f9f7 66 /** @endcond */
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /*******************************************************************************
<> 144:ef7eb2e8f9f7 70 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 71 ******************************************************************************/
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 74 * @brief
<> 144:ef7eb2e8f9f7 75 * Sets the pin location of the debug pins (Serial Wire interface).
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * @note
<> 144:ef7eb2e8f9f7 78 * Changing the pins used for debugging uncontrolled, may result in a lockout.
<> 144:ef7eb2e8f9f7 79 *
<> 144:ef7eb2e8f9f7 80 * @param[in] location
<> 144:ef7eb2e8f9f7 81 * The debug pin location to use (0-3).
<> 144:ef7eb2e8f9f7 82 ******************************************************************************/
<> 144:ef7eb2e8f9f7 83 void GPIO_DbgLocationSet(unsigned int location)
<> 144:ef7eb2e8f9f7 84 {
<> 144:ef7eb2e8f9f7 85 #if defined ( _GPIO_ROUTE_SWLOCATION_MASK )
<> 144:ef7eb2e8f9f7 86 EFM_ASSERT(location < AFCHANLOC_MAX);
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 GPIO->ROUTE = (GPIO->ROUTE & ~_GPIO_ROUTE_SWLOCATION_MASK) |
<> 144:ef7eb2e8f9f7 89 (location << _GPIO_ROUTE_SWLOCATION_SHIFT);
<> 144:ef7eb2e8f9f7 90 #else
<> 144:ef7eb2e8f9f7 91 (void)location;
<> 144:ef7eb2e8f9f7 92 #endif
<> 144:ef7eb2e8f9f7 93 }
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 #if defined (_GPIO_P_CTRL_DRIVEMODE_MASK)
<> 144:ef7eb2e8f9f7 96 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 97 * @brief
<> 144:ef7eb2e8f9f7 98 * Sets the drive mode for a GPIO port.
<> 144:ef7eb2e8f9f7 99 *
<> 144:ef7eb2e8f9f7 100 * @param[in] port
<> 144:ef7eb2e8f9f7 101 * The GPIO port to access.
<> 144:ef7eb2e8f9f7 102 *
<> 144:ef7eb2e8f9f7 103 * @param[in] mode
<> 144:ef7eb2e8f9f7 104 * Drive mode to use for port.
<> 144:ef7eb2e8f9f7 105 ******************************************************************************/
<> 144:ef7eb2e8f9f7 106 void GPIO_DriveModeSet(GPIO_Port_TypeDef port, GPIO_DriveMode_TypeDef mode)
<> 144:ef7eb2e8f9f7 107 {
<> 144:ef7eb2e8f9f7 108 EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_DRIVEMODE_VALID(mode));
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 GPIO->P[port].CTRL = (GPIO->P[port].CTRL & ~(_GPIO_P_CTRL_DRIVEMODE_MASK))
<> 144:ef7eb2e8f9f7 111 | (mode << _GPIO_P_CTRL_DRIVEMODE_SHIFT);
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113 #endif
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 #if defined (_GPIO_P_CTRL_DRIVESTRENGTH_MASK)
<> 144:ef7eb2e8f9f7 116 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 117 * @brief
<> 144:ef7eb2e8f9f7 118 * Sets the drive strength for a GPIO port.
<> 144:ef7eb2e8f9f7 119 *
<> 144:ef7eb2e8f9f7 120 * @param[in] port
<> 144:ef7eb2e8f9f7 121 * The GPIO port to access.
<> 144:ef7eb2e8f9f7 122 *
<> 144:ef7eb2e8f9f7 123 * @param[in] strength
<> 144:ef7eb2e8f9f7 124 * Drive strength to use for port.
<> 144:ef7eb2e8f9f7 125 ******************************************************************************/
<> 144:ef7eb2e8f9f7 126 void GPIO_DriveStrengthSet(GPIO_Port_TypeDef port,
<> 144:ef7eb2e8f9f7 127 GPIO_DriveStrength_TypeDef strength)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 EFM_ASSERT(GPIO_PORT_VALID(port) && GPIO_STRENGHT_VALID(strength));
<> 144:ef7eb2e8f9f7 130 BUS_RegMaskedWrite(&GPIO->P[port].CTRL,
<> 144:ef7eb2e8f9f7 131 _GPIO_P_CTRL_DRIVESTRENGTH_MASK | _GPIO_P_CTRL_DRIVESTRENGTHALT_MASK,
<> 144:ef7eb2e8f9f7 132 strength);
<> 144:ef7eb2e8f9f7 133 }
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 137 * @brief
<> 150:02e0a0aed4ec 138 * Configure GPIO external pin interrupt.
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 * @details
<> 144:ef7eb2e8f9f7 141 * If reconfiguring a GPIO interrupt that is already enabled, it is generally
<> 144:ef7eb2e8f9f7 142 * recommended to disable it first, see GPIO_Disable().
<> 144:ef7eb2e8f9f7 143 *
<> 144:ef7eb2e8f9f7 144 * The actual GPIO interrupt handler must be in place before enabling the
<> 144:ef7eb2e8f9f7 145 * interrupt.
<> 144:ef7eb2e8f9f7 146 *
<> 150:02e0a0aed4ec 147 * Notice that any pending interrupt for the selected interrupt is cleared
<> 150:02e0a0aed4ec 148 * by this function.
<> 144:ef7eb2e8f9f7 149 *
<> 144:ef7eb2e8f9f7 150 * @note
<> 161:2cc1468da177 151 * On series 0 devices the pin number parameter is not used. The
<> 150:02e0a0aed4ec 152 * pin number used on these devices is hardwired to the interrupt with the
<> 150:02e0a0aed4ec 153 * same number. @n
<> 161:2cc1468da177 154 * On series 1 devices, pin number can be selected freely within a group.
<> 150:02e0a0aed4ec 155 * Interrupt numbers are divided into 4 groups (intNo / 4) and valid pin
<> 150:02e0a0aed4ec 156 * number within the interrupt groups are:
<> 150:02e0a0aed4ec 157 * 0: pins 0-3
<> 150:02e0a0aed4ec 158 * 1: pins 4-7
<> 150:02e0a0aed4ec 159 * 2: pins 8-11
<> 150:02e0a0aed4ec 160 * 3: pins 12-15
<> 144:ef7eb2e8f9f7 161 *
<> 144:ef7eb2e8f9f7 162 * @param[in] port
<> 144:ef7eb2e8f9f7 163 * The port to associate with @p pin.
<> 144:ef7eb2e8f9f7 164 *
<> 144:ef7eb2e8f9f7 165 * @param[in] pin
<> 150:02e0a0aed4ec 166 * The pin number on the port.
<> 150:02e0a0aed4ec 167 *
<> 150:02e0a0aed4ec 168 * @param[in] intNo
<> 150:02e0a0aed4ec 169 * The interrupt number to trigger.
<> 144:ef7eb2e8f9f7 170 *
<> 144:ef7eb2e8f9f7 171 * @param[in] risingEdge
<> 144:ef7eb2e8f9f7 172 * Set to true if interrupts shall be enabled on rising edge, otherwise false.
<> 144:ef7eb2e8f9f7 173 *
<> 144:ef7eb2e8f9f7 174 * @param[in] fallingEdge
<> 144:ef7eb2e8f9f7 175 * Set to true if interrupts shall be enabled on falling edge, otherwise false.
<> 144:ef7eb2e8f9f7 176 *
<> 144:ef7eb2e8f9f7 177 * @param[in] enable
<> 144:ef7eb2e8f9f7 178 * Set to true if interrupt shall be enabled after configuration completed,
<> 144:ef7eb2e8f9f7 179 * false to leave disabled. See GPIO_IntDisable() and GPIO_IntEnable().
<> 144:ef7eb2e8f9f7 180 ******************************************************************************/
<> 150:02e0a0aed4ec 181 void GPIO_ExtIntConfig(GPIO_Port_TypeDef port,
<> 150:02e0a0aed4ec 182 unsigned int pin,
<> 150:02e0a0aed4ec 183 unsigned int intNo,
<> 150:02e0a0aed4ec 184 bool risingEdge,
<> 150:02e0a0aed4ec 185 bool fallingEdge,
<> 150:02e0a0aed4ec 186 bool enable)
<> 144:ef7eb2e8f9f7 187 {
<> 161:2cc1468da177 188 uint32_t tmp = 0;
<> 150:02e0a0aed4ec 189 #if !defined(_GPIO_EXTIPINSELL_MASK)
<> 150:02e0a0aed4ec 190 (void)pin;
<> 150:02e0a0aed4ec 191 #endif
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
<> 150:02e0a0aed4ec 194 #if defined(_GPIO_EXTIPINSELL_MASK)
<> 150:02e0a0aed4ec 195 EFM_ASSERT(GPIO_INTNO_PIN_VALID(intNo, pin));
<> 150:02e0a0aed4ec 196 #endif
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /* There are two registers controlling the interrupt configuration:
<> 144:ef7eb2e8f9f7 199 * The EXTIPSELL register controls pins 0-7 and EXTIPSELH controls
<> 144:ef7eb2e8f9f7 200 * pins 8-15. */
<> 150:02e0a0aed4ec 201 if (intNo < 8)
<> 144:ef7eb2e8f9f7 202 {
<> 144:ef7eb2e8f9f7 203 BUS_RegMaskedWrite(&GPIO->EXTIPSELL,
<> 150:02e0a0aed4ec 204 _GPIO_EXTIPSELL_EXTIPSEL0_MASK
<> 150:02e0a0aed4ec 205 << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo),
<> 150:02e0a0aed4ec 206 port << (_GPIO_EXTIPSELL_EXTIPSEL1_SHIFT * intNo));
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208 else
<> 144:ef7eb2e8f9f7 209 {
<> 150:02e0a0aed4ec 210 tmp = intNo - 8;
<> 144:ef7eb2e8f9f7 211 BUS_RegMaskedWrite(&GPIO->EXTIPSELH,
<> 150:02e0a0aed4ec 212 _GPIO_EXTIPSELH_EXTIPSEL8_MASK
<> 150:02e0a0aed4ec 213 << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp),
<> 150:02e0a0aed4ec 214 port << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
<> 144:ef7eb2e8f9f7 215 }
<> 144:ef7eb2e8f9f7 216
<> 150:02e0a0aed4ec 217 #if defined(_GPIO_EXTIPINSELL_MASK)
<> 150:02e0a0aed4ec 218 /* There are two registers controlling the interrupt/pin number mapping:
<> 150:02e0a0aed4ec 219 * The EXTIPINSELL register controls interrupt 0-7 and EXTIPINSELH controls
<> 150:02e0a0aed4ec 220 * interrupt 8-15. */
<> 150:02e0a0aed4ec 221 if (intNo < 8)
<> 150:02e0a0aed4ec 222 {
<> 150:02e0a0aed4ec 223 BUS_RegMaskedWrite(&GPIO->EXTIPINSELL,
<> 150:02e0a0aed4ec 224 _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK
<> 150:02e0a0aed4ec 225 << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo),
<> 150:02e0a0aed4ec 226 ((pin % 4) & _GPIO_EXTIPINSELL_EXTIPINSEL0_MASK)
<> 150:02e0a0aed4ec 227 << (_GPIO_EXTIPINSELL_EXTIPINSEL1_SHIFT * intNo));
<> 150:02e0a0aed4ec 228 }
<> 150:02e0a0aed4ec 229 else
<> 150:02e0a0aed4ec 230 {
<> 150:02e0a0aed4ec 231 BUS_RegMaskedWrite(&GPIO->EXTIPINSELH,
<> 150:02e0a0aed4ec 232 _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK
<> 150:02e0a0aed4ec 233 << (_GPIO_EXTIPINSELH_EXTIPINSEL9_SHIFT * tmp),
<> 150:02e0a0aed4ec 234 ((pin % 4) & _GPIO_EXTIPINSELH_EXTIPINSEL8_MASK)
<> 150:02e0a0aed4ec 235 << (_GPIO_EXTIPSELH_EXTIPSEL9_SHIFT * tmp));
<> 150:02e0a0aed4ec 236 }
<> 150:02e0a0aed4ec 237 #endif
<> 150:02e0a0aed4ec 238
<> 144:ef7eb2e8f9f7 239 /* Enable/disable rising edge */
<> 150:02e0a0aed4ec 240 BUS_RegBitWrite(&(GPIO->EXTIRISE), intNo, risingEdge);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Enable/disable falling edge */
<> 150:02e0a0aed4ec 243 BUS_RegBitWrite(&(GPIO->EXTIFALL), intNo, fallingEdge);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Clear any pending interrupt */
<> 150:02e0a0aed4ec 246 GPIO->IFC = 1 << intNo;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Finally enable/disable interrupt */
<> 150:02e0a0aed4ec 249 BUS_RegBitWrite(&(GPIO->IEN), intNo, enable);
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 253 * @brief
<> 144:ef7eb2e8f9f7 254 * Set the mode for a GPIO pin.
<> 144:ef7eb2e8f9f7 255 *
<> 144:ef7eb2e8f9f7 256 * @param[in] port
<> 144:ef7eb2e8f9f7 257 * The GPIO port to access.
<> 144:ef7eb2e8f9f7 258 *
<> 144:ef7eb2e8f9f7 259 * @param[in] pin
<> 144:ef7eb2e8f9f7 260 * The pin number in the port.
<> 144:ef7eb2e8f9f7 261 *
<> 144:ef7eb2e8f9f7 262 * @param[in] mode
<> 144:ef7eb2e8f9f7 263 * The desired pin mode.
<> 144:ef7eb2e8f9f7 264 *
<> 144:ef7eb2e8f9f7 265 * @param[in] out
<> 144:ef7eb2e8f9f7 266 * Value to set for pin in DOUT register. The DOUT setting is important for
<> 144:ef7eb2e8f9f7 267 * even some input mode configurations, determining pull-up/down direction.
<> 144:ef7eb2e8f9f7 268 ******************************************************************************/
<> 144:ef7eb2e8f9f7 269 void GPIO_PinModeSet(GPIO_Port_TypeDef port,
<> 144:ef7eb2e8f9f7 270 unsigned int pin,
<> 144:ef7eb2e8f9f7 271 GPIO_Mode_TypeDef mode,
<> 144:ef7eb2e8f9f7 272 unsigned int out)
<> 144:ef7eb2e8f9f7 273 {
<> 144:ef7eb2e8f9f7 274 EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* If disabling pin, do not modify DOUT in order to reduce chance for */
<> 144:ef7eb2e8f9f7 277 /* glitch/spike (may not be sufficient precaution in all use cases) */
<> 144:ef7eb2e8f9f7 278 if (mode != gpioModeDisabled)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 if (out)
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 GPIO_PinOutSet(port, pin);
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284 else
<> 144:ef7eb2e8f9f7 285 {
<> 144:ef7eb2e8f9f7 286 GPIO_PinOutClear(port, pin);
<> 144:ef7eb2e8f9f7 287 }
<> 144:ef7eb2e8f9f7 288 }
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* There are two registers controlling the pins for each port. The MODEL
<> 144:ef7eb2e8f9f7 291 * register controls pins 0-7 and MODEH controls pins 8-15. */
<> 144:ef7eb2e8f9f7 292 if (pin < 8)
<> 144:ef7eb2e8f9f7 293 {
<> 161:2cc1468da177 294 GPIO->P[port].MODEL = (GPIO->P[port].MODEL & ~(0xFu << (pin * 4)))
<> 150:02e0a0aed4ec 295 | (mode << (pin * 4));
<> 144:ef7eb2e8f9f7 296 }
<> 144:ef7eb2e8f9f7 297 else
<> 144:ef7eb2e8f9f7 298 {
<> 161:2cc1468da177 299 GPIO->P[port].MODEH = (GPIO->P[port].MODEH & ~(0xFu << ((pin - 8) * 4)))
<> 150:02e0a0aed4ec 300 | (mode << ((pin - 8) * 4));
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 if (mode == gpioModeDisabled)
<> 144:ef7eb2e8f9f7 304 {
<> 144:ef7eb2e8f9f7 305 if (out)
<> 144:ef7eb2e8f9f7 306 {
<> 144:ef7eb2e8f9f7 307 GPIO_PinOutSet(port, pin);
<> 144:ef7eb2e8f9f7 308 }
<> 144:ef7eb2e8f9f7 309 else
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 GPIO_PinOutClear(port, pin);
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313 }
<> 144:ef7eb2e8f9f7 314 }
<> 144:ef7eb2e8f9f7 315
<> 150:02e0a0aed4ec 316 /***************************************************************************//**
<> 150:02e0a0aed4ec 317 * @brief
<> 150:02e0a0aed4ec 318 * Get the mode for a GPIO pin.
<> 150:02e0a0aed4ec 319 *
<> 150:02e0a0aed4ec 320 * @param[in] port
<> 150:02e0a0aed4ec 321 * The GPIO port to access.
<> 150:02e0a0aed4ec 322 *
<> 150:02e0a0aed4ec 323 * @param[in] pin
<> 150:02e0a0aed4ec 324 * The pin number in the port.
<> 150:02e0a0aed4ec 325 *
<> 150:02e0a0aed4ec 326 * @return
<> 150:02e0a0aed4ec 327 * The pin mode.
<> 150:02e0a0aed4ec 328 ******************************************************************************/
<> 150:02e0a0aed4ec 329 GPIO_Mode_TypeDef GPIO_PinModeGet(GPIO_Port_TypeDef port,
<> 150:02e0a0aed4ec 330 unsigned int pin)
<> 150:02e0a0aed4ec 331 {
<> 150:02e0a0aed4ec 332 EFM_ASSERT(GPIO_PORT_PIN_VALID(port, pin));
<> 150:02e0a0aed4ec 333
<> 150:02e0a0aed4ec 334 if (pin < 8)
<> 150:02e0a0aed4ec 335 {
<> 150:02e0a0aed4ec 336 return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEL >> (pin * 4)) & 0xF);
<> 150:02e0a0aed4ec 337 }
<> 150:02e0a0aed4ec 338 else
<> 150:02e0a0aed4ec 339 {
<> 150:02e0a0aed4ec 340 return (GPIO_Mode_TypeDef) ((GPIO->P[port].MODEH >> ((pin - 8) * 4)) & 0xF);
<> 150:02e0a0aed4ec 341 }
<> 150:02e0a0aed4ec 342 }
<> 150:02e0a0aed4ec 343
<> 144:ef7eb2e8f9f7 344 #if defined( _GPIO_EM4WUEN_MASK )
<> 144:ef7eb2e8f9f7 345 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 346 * @brief
<> 144:ef7eb2e8f9f7 347 * Enable GPIO pin wake-up from EM4. When the function exits,
<> 144:ef7eb2e8f9f7 348 * EM4 mode can be safely entered.
<> 144:ef7eb2e8f9f7 349 *
<> 144:ef7eb2e8f9f7 350 * @note
<> 144:ef7eb2e8f9f7 351 * It is assumed that the GPIO pin modes are set correctly.
<> 144:ef7eb2e8f9f7 352 * Valid modes are @ref gpioModeInput and @ref gpioModeInputPull.
<> 144:ef7eb2e8f9f7 353 *
<> 144:ef7eb2e8f9f7 354 * @param[in] pinmask
<> 144:ef7eb2e8f9f7 355 * Bitmask containing the bitwise logic OR of which GPIO pin(s) to enable.
<> 144:ef7eb2e8f9f7 356 * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
<> 144:ef7eb2e8f9f7 357 * @param[in] polaritymask
<> 144:ef7eb2e8f9f7 358 * Bitmask containing the bitwise logic OR of GPIO pin(s) wake-up polarity.
<> 144:ef7eb2e8f9f7 359 * Refer to Reference Manuals for pinmask to GPIO port/pin mapping.
<> 144:ef7eb2e8f9f7 360 *****************************************************************************/
<> 144:ef7eb2e8f9f7 361 void GPIO_EM4EnablePinWakeup(uint32_t pinmask, uint32_t polaritymask)
<> 144:ef7eb2e8f9f7 362 {
<> 144:ef7eb2e8f9f7 363 EFM_ASSERT((pinmask & ~_GPIO_EM4WUEN_MASK) == 0);
<> 144:ef7eb2e8f9f7 364
<> 144:ef7eb2e8f9f7 365 #if defined( _GPIO_EM4WUPOL_MASK )
<> 144:ef7eb2e8f9f7 366 EFM_ASSERT((polaritymask & ~_GPIO_EM4WUPOL_MASK) == 0);
<> 144:ef7eb2e8f9f7 367 GPIO->EM4WUPOL &= ~pinmask; /* Set wakeup polarity */
<> 144:ef7eb2e8f9f7 368 GPIO->EM4WUPOL |= pinmask & polaritymask;
<> 144:ef7eb2e8f9f7 369 #elif defined( _GPIO_EXTILEVEL_MASK )
<> 144:ef7eb2e8f9f7 370 EFM_ASSERT((polaritymask & ~_GPIO_EXTILEVEL_MASK) == 0);
<> 144:ef7eb2e8f9f7 371 GPIO->EXTILEVEL &= ~pinmask;
<> 144:ef7eb2e8f9f7 372 GPIO->EXTILEVEL |= pinmask & polaritymask;
<> 144:ef7eb2e8f9f7 373 #endif
<> 144:ef7eb2e8f9f7 374 GPIO->EM4WUEN |= pinmask; /* Enable wakeup */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 GPIO_EM4SetPinRetention(true); /* Enable pin retention */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 #if defined( _GPIO_CMD_EM4WUCLR_MASK )
<> 144:ef7eb2e8f9f7 379 GPIO->CMD = GPIO_CMD_EM4WUCLR; /* Clear wake-up logic */
<> 144:ef7eb2e8f9f7 380 #elif defined( _GPIO_IFC_EM4WU_MASK )
<> 144:ef7eb2e8f9f7 381 GPIO_IntClear(pinmask);
<> 144:ef7eb2e8f9f7 382 #endif
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384 #endif
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386 /** @} (end addtogroup GPIO) */
<> 150:02e0a0aed4ec 387 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 #endif /* defined(GPIO_COUNT) && (GPIO_COUNT > 0) */