mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_usart.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
153:fa9ff456f731 
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**************************************************************************//**
<> 153:fa9ff456f731 2 * @file efr32mg1p_usart.h
<> 153:fa9ff456f731 3 * @brief EFR32MG1P_USART register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 153:fa9ff456f731 5 ******************************************************************************
<> 153:fa9ff456f731 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 153:fa9ff456f731 8 ******************************************************************************
<> 153:fa9ff456f731 9 *
<> 153:fa9ff456f731 10 * Permission is granted to anyone to use this software for any purpose,
<> 153:fa9ff456f731 11 * including commercial applications, and to alter it and redistribute it
<> 153:fa9ff456f731 12 * freely, subject to the following restrictions:
<> 153:fa9ff456f731 13 *
<> 153:fa9ff456f731 14 * 1. The origin of this software must not be misrepresented; you must not
<> 153:fa9ff456f731 15 * claim that you wrote the original software.@n
<> 153:fa9ff456f731 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 153:fa9ff456f731 17 * misrepresented as being the original software.@n
<> 153:fa9ff456f731 18 * 3. This notice may not be removed or altered from any source distribution.
<> 153:fa9ff456f731 19 *
<> 153:fa9ff456f731 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 153:fa9ff456f731 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 153:fa9ff456f731 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 153:fa9ff456f731 23 * kind, including, but not limited to, any implied warranties of
<> 153:fa9ff456f731 24 * merchantability or fitness for any particular purpose or warranties against
<> 153:fa9ff456f731 25 * infringement of any proprietary rights of a third party.
<> 153:fa9ff456f731 26 *
<> 153:fa9ff456f731 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 153:fa9ff456f731 28 * incidental, or special damages, or any other relief, or for any claim by
<> 153:fa9ff456f731 29 * any third party, arising from your use of this Software.
<> 153:fa9ff456f731 30 *
<> 153:fa9ff456f731 31 *****************************************************************************/
<> 153:fa9ff456f731 32 /**************************************************************************//**
<> 153:fa9ff456f731 33 * @addtogroup Parts
<> 153:fa9ff456f731 34 * @{
<> 153:fa9ff456f731 35 ******************************************************************************/
<> 153:fa9ff456f731 36 /**************************************************************************//**
<> 153:fa9ff456f731 37 * @defgroup EFR32MG1P_USART
<> 153:fa9ff456f731 38 * @{
<> 153:fa9ff456f731 39 * @brief EFR32MG1P_USART Register Declaration
<> 153:fa9ff456f731 40 *****************************************************************************/
<> 153:fa9ff456f731 41 typedef struct
<> 153:fa9ff456f731 42 {
<> 153:fa9ff456f731 43 __IOM uint32_t CTRL; /**< Control Register */
<> 153:fa9ff456f731 44 __IOM uint32_t FRAME; /**< USART Frame Format Register */
<> 153:fa9ff456f731 45 __IOM uint32_t TRIGCTRL; /**< USART Trigger Control register */
<> 153:fa9ff456f731 46 __IOM uint32_t CMD; /**< Command Register */
<> 153:fa9ff456f731 47 __IM uint32_t STATUS; /**< USART Status Register */
<> 153:fa9ff456f731 48 __IOM uint32_t CLKDIV; /**< Clock Control Register */
<> 153:fa9ff456f731 49 __IM uint32_t RXDATAX; /**< RX Buffer Data Extended Register */
<> 153:fa9ff456f731 50 __IM uint32_t RXDATA; /**< RX Buffer Data Register */
<> 153:fa9ff456f731 51 __IM uint32_t RXDOUBLEX; /**< RX Buffer Double Data Extended Register */
<> 153:fa9ff456f731 52 __IM uint32_t RXDOUBLE; /**< RX FIFO Double Data Register */
<> 153:fa9ff456f731 53 __IM uint32_t RXDATAXP; /**< RX Buffer Data Extended Peek Register */
<> 153:fa9ff456f731 54 __IM uint32_t RXDOUBLEXP; /**< RX Buffer Double Data Extended Peek Register */
<> 153:fa9ff456f731 55 __IOM uint32_t TXDATAX; /**< TX Buffer Data Extended Register */
<> 153:fa9ff456f731 56 __IOM uint32_t TXDATA; /**< TX Buffer Data Register */
<> 153:fa9ff456f731 57 __IOM uint32_t TXDOUBLEX; /**< TX Buffer Double Data Extended Register */
<> 153:fa9ff456f731 58 __IOM uint32_t TXDOUBLE; /**< TX Buffer Double Data Register */
<> 153:fa9ff456f731 59 __IM uint32_t IF; /**< Interrupt Flag Register */
<> 153:fa9ff456f731 60 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
<> 153:fa9ff456f731 61 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 153:fa9ff456f731 62 __IOM uint32_t IEN; /**< Interrupt Enable Register */
<> 153:fa9ff456f731 63 __IOM uint32_t IRCTRL; /**< IrDA Control Register */
<> 153:fa9ff456f731 64 uint32_t RESERVED0[1]; /**< Reserved for future use **/
<> 153:fa9ff456f731 65 __IOM uint32_t INPUT; /**< USART Input Register */
<> 153:fa9ff456f731 66 __IOM uint32_t I2SCTRL; /**< I2S Control Register */
<> 153:fa9ff456f731 67 __IOM uint32_t TIMING; /**< Timing Register */
<> 153:fa9ff456f731 68 __IOM uint32_t CTRLX; /**< Control Register Extended */
<> 153:fa9ff456f731 69 __IOM uint32_t TIMECMP0; /**< Used to generate interrupts and various delays */
<> 153:fa9ff456f731 70 __IOM uint32_t TIMECMP1; /**< Used to generate interrupts and various delays */
<> 153:fa9ff456f731 71 __IOM uint32_t TIMECMP2; /**< Used to generate interrupts and various delays */
<> 153:fa9ff456f731 72 __IOM uint32_t ROUTEPEN; /**< I/O Routing Pin Enable Register */
<> 153:fa9ff456f731 73 __IOM uint32_t ROUTELOC0; /**< I/O Routing Location Register */
<> 153:fa9ff456f731 74 __IOM uint32_t ROUTELOC1; /**< I/O Routing Location Register */
<> 153:fa9ff456f731 75 } USART_TypeDef; /** @} */
<> 153:fa9ff456f731 76
<> 153:fa9ff456f731 77 /**************************************************************************//**
<> 153:fa9ff456f731 78 * @defgroup EFR32MG1P_USART_BitFields
<> 153:fa9ff456f731 79 * @{
<> 153:fa9ff456f731 80 *****************************************************************************/
<> 153:fa9ff456f731 81
<> 153:fa9ff456f731 82 /* Bit fields for USART CTRL */
<> 153:fa9ff456f731 83 #define _USART_CTRL_RESETVALUE 0x00000000UL /**< Default value for USART_CTRL */
<> 153:fa9ff456f731 84 #define _USART_CTRL_MASK 0xF3FFFF7FUL /**< Mask for USART_CTRL */
<> 153:fa9ff456f731 85 #define USART_CTRL_SYNC (0x1UL << 0) /**< USART Synchronous Mode */
<> 153:fa9ff456f731 86 #define _USART_CTRL_SYNC_SHIFT 0 /**< Shift value for USART_SYNC */
<> 153:fa9ff456f731 87 #define _USART_CTRL_SYNC_MASK 0x1UL /**< Bit mask for USART_SYNC */
<> 153:fa9ff456f731 88 #define _USART_CTRL_SYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 89 #define USART_CTRL_SYNC_DEFAULT (_USART_CTRL_SYNC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 90 #define USART_CTRL_LOOPBK (0x1UL << 1) /**< Loopback Enable */
<> 153:fa9ff456f731 91 #define _USART_CTRL_LOOPBK_SHIFT 1 /**< Shift value for USART_LOOPBK */
<> 153:fa9ff456f731 92 #define _USART_CTRL_LOOPBK_MASK 0x2UL /**< Bit mask for USART_LOOPBK */
<> 153:fa9ff456f731 93 #define _USART_CTRL_LOOPBK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 94 #define USART_CTRL_LOOPBK_DEFAULT (_USART_CTRL_LOOPBK_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 95 #define USART_CTRL_CCEN (0x1UL << 2) /**< Collision Check Enable */
<> 153:fa9ff456f731 96 #define _USART_CTRL_CCEN_SHIFT 2 /**< Shift value for USART_CCEN */
<> 153:fa9ff456f731 97 #define _USART_CTRL_CCEN_MASK 0x4UL /**< Bit mask for USART_CCEN */
<> 153:fa9ff456f731 98 #define _USART_CTRL_CCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 99 #define USART_CTRL_CCEN_DEFAULT (_USART_CTRL_CCEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 100 #define USART_CTRL_MPM (0x1UL << 3) /**< Multi-Processor Mode */
<> 153:fa9ff456f731 101 #define _USART_CTRL_MPM_SHIFT 3 /**< Shift value for USART_MPM */
<> 153:fa9ff456f731 102 #define _USART_CTRL_MPM_MASK 0x8UL /**< Bit mask for USART_MPM */
<> 153:fa9ff456f731 103 #define _USART_CTRL_MPM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 104 #define USART_CTRL_MPM_DEFAULT (_USART_CTRL_MPM_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 105 #define USART_CTRL_MPAB (0x1UL << 4) /**< Multi-Processor Address-Bit */
<> 153:fa9ff456f731 106 #define _USART_CTRL_MPAB_SHIFT 4 /**< Shift value for USART_MPAB */
<> 153:fa9ff456f731 107 #define _USART_CTRL_MPAB_MASK 0x10UL /**< Bit mask for USART_MPAB */
<> 153:fa9ff456f731 108 #define _USART_CTRL_MPAB_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 109 #define USART_CTRL_MPAB_DEFAULT (_USART_CTRL_MPAB_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 110 #define _USART_CTRL_OVS_SHIFT 5 /**< Shift value for USART_OVS */
<> 153:fa9ff456f731 111 #define _USART_CTRL_OVS_MASK 0x60UL /**< Bit mask for USART_OVS */
<> 153:fa9ff456f731 112 #define _USART_CTRL_OVS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 113 #define _USART_CTRL_OVS_X16 0x00000000UL /**< Mode X16 for USART_CTRL */
<> 153:fa9ff456f731 114 #define _USART_CTRL_OVS_X8 0x00000001UL /**< Mode X8 for USART_CTRL */
<> 153:fa9ff456f731 115 #define _USART_CTRL_OVS_X6 0x00000002UL /**< Mode X6 for USART_CTRL */
<> 153:fa9ff456f731 116 #define _USART_CTRL_OVS_X4 0x00000003UL /**< Mode X4 for USART_CTRL */
<> 153:fa9ff456f731 117 #define USART_CTRL_OVS_DEFAULT (_USART_CTRL_OVS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 118 #define USART_CTRL_OVS_X16 (_USART_CTRL_OVS_X16 << 5) /**< Shifted mode X16 for USART_CTRL */
<> 153:fa9ff456f731 119 #define USART_CTRL_OVS_X8 (_USART_CTRL_OVS_X8 << 5) /**< Shifted mode X8 for USART_CTRL */
<> 153:fa9ff456f731 120 #define USART_CTRL_OVS_X6 (_USART_CTRL_OVS_X6 << 5) /**< Shifted mode X6 for USART_CTRL */
<> 153:fa9ff456f731 121 #define USART_CTRL_OVS_X4 (_USART_CTRL_OVS_X4 << 5) /**< Shifted mode X4 for USART_CTRL */
<> 153:fa9ff456f731 122 #define USART_CTRL_CLKPOL (0x1UL << 8) /**< Clock Polarity */
<> 153:fa9ff456f731 123 #define _USART_CTRL_CLKPOL_SHIFT 8 /**< Shift value for USART_CLKPOL */
<> 153:fa9ff456f731 124 #define _USART_CTRL_CLKPOL_MASK 0x100UL /**< Bit mask for USART_CLKPOL */
<> 153:fa9ff456f731 125 #define _USART_CTRL_CLKPOL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 126 #define _USART_CTRL_CLKPOL_IDLELOW 0x00000000UL /**< Mode IDLELOW for USART_CTRL */
<> 153:fa9ff456f731 127 #define _USART_CTRL_CLKPOL_IDLEHIGH 0x00000001UL /**< Mode IDLEHIGH for USART_CTRL */
<> 153:fa9ff456f731 128 #define USART_CTRL_CLKPOL_DEFAULT (_USART_CTRL_CLKPOL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 129 #define USART_CTRL_CLKPOL_IDLELOW (_USART_CTRL_CLKPOL_IDLELOW << 8) /**< Shifted mode IDLELOW for USART_CTRL */
<> 153:fa9ff456f731 130 #define USART_CTRL_CLKPOL_IDLEHIGH (_USART_CTRL_CLKPOL_IDLEHIGH << 8) /**< Shifted mode IDLEHIGH for USART_CTRL */
<> 153:fa9ff456f731 131 #define USART_CTRL_CLKPHA (0x1UL << 9) /**< Clock Edge For Setup/Sample */
<> 153:fa9ff456f731 132 #define _USART_CTRL_CLKPHA_SHIFT 9 /**< Shift value for USART_CLKPHA */
<> 153:fa9ff456f731 133 #define _USART_CTRL_CLKPHA_MASK 0x200UL /**< Bit mask for USART_CLKPHA */
<> 153:fa9ff456f731 134 #define _USART_CTRL_CLKPHA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 135 #define _USART_CTRL_CLKPHA_SAMPLELEADING 0x00000000UL /**< Mode SAMPLELEADING for USART_CTRL */
<> 153:fa9ff456f731 136 #define _USART_CTRL_CLKPHA_SAMPLETRAILING 0x00000001UL /**< Mode SAMPLETRAILING for USART_CTRL */
<> 153:fa9ff456f731 137 #define USART_CTRL_CLKPHA_DEFAULT (_USART_CTRL_CLKPHA_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 138 #define USART_CTRL_CLKPHA_SAMPLELEADING (_USART_CTRL_CLKPHA_SAMPLELEADING << 9) /**< Shifted mode SAMPLELEADING for USART_CTRL */
<> 153:fa9ff456f731 139 #define USART_CTRL_CLKPHA_SAMPLETRAILING (_USART_CTRL_CLKPHA_SAMPLETRAILING << 9) /**< Shifted mode SAMPLETRAILING for USART_CTRL */
<> 153:fa9ff456f731 140 #define USART_CTRL_MSBF (0x1UL << 10) /**< Most Significant Bit First */
<> 153:fa9ff456f731 141 #define _USART_CTRL_MSBF_SHIFT 10 /**< Shift value for USART_MSBF */
<> 153:fa9ff456f731 142 #define _USART_CTRL_MSBF_MASK 0x400UL /**< Bit mask for USART_MSBF */
<> 153:fa9ff456f731 143 #define _USART_CTRL_MSBF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 144 #define USART_CTRL_MSBF_DEFAULT (_USART_CTRL_MSBF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 145 #define USART_CTRL_CSMA (0x1UL << 11) /**< Action On Slave-Select In Master Mode */
<> 153:fa9ff456f731 146 #define _USART_CTRL_CSMA_SHIFT 11 /**< Shift value for USART_CSMA */
<> 153:fa9ff456f731 147 #define _USART_CTRL_CSMA_MASK 0x800UL /**< Bit mask for USART_CSMA */
<> 153:fa9ff456f731 148 #define _USART_CTRL_CSMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 149 #define _USART_CTRL_CSMA_NOACTION 0x00000000UL /**< Mode NOACTION for USART_CTRL */
<> 153:fa9ff456f731 150 #define _USART_CTRL_CSMA_GOTOSLAVEMODE 0x00000001UL /**< Mode GOTOSLAVEMODE for USART_CTRL */
<> 153:fa9ff456f731 151 #define USART_CTRL_CSMA_DEFAULT (_USART_CTRL_CSMA_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 152 #define USART_CTRL_CSMA_NOACTION (_USART_CTRL_CSMA_NOACTION << 11) /**< Shifted mode NOACTION for USART_CTRL */
<> 153:fa9ff456f731 153 #define USART_CTRL_CSMA_GOTOSLAVEMODE (_USART_CTRL_CSMA_GOTOSLAVEMODE << 11) /**< Shifted mode GOTOSLAVEMODE for USART_CTRL */
<> 153:fa9ff456f731 154 #define USART_CTRL_TXBIL (0x1UL << 12) /**< TX Buffer Interrupt Level */
<> 153:fa9ff456f731 155 #define _USART_CTRL_TXBIL_SHIFT 12 /**< Shift value for USART_TXBIL */
<> 153:fa9ff456f731 156 #define _USART_CTRL_TXBIL_MASK 0x1000UL /**< Bit mask for USART_TXBIL */
<> 153:fa9ff456f731 157 #define _USART_CTRL_TXBIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 158 #define _USART_CTRL_TXBIL_EMPTY 0x00000000UL /**< Mode EMPTY for USART_CTRL */
<> 153:fa9ff456f731 159 #define _USART_CTRL_TXBIL_HALFFULL 0x00000001UL /**< Mode HALFFULL for USART_CTRL */
<> 153:fa9ff456f731 160 #define USART_CTRL_TXBIL_DEFAULT (_USART_CTRL_TXBIL_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 161 #define USART_CTRL_TXBIL_EMPTY (_USART_CTRL_TXBIL_EMPTY << 12) /**< Shifted mode EMPTY for USART_CTRL */
<> 153:fa9ff456f731 162 #define USART_CTRL_TXBIL_HALFFULL (_USART_CTRL_TXBIL_HALFFULL << 12) /**< Shifted mode HALFFULL for USART_CTRL */
<> 153:fa9ff456f731 163 #define USART_CTRL_RXINV (0x1UL << 13) /**< Receiver Input Invert */
<> 153:fa9ff456f731 164 #define _USART_CTRL_RXINV_SHIFT 13 /**< Shift value for USART_RXINV */
<> 153:fa9ff456f731 165 #define _USART_CTRL_RXINV_MASK 0x2000UL /**< Bit mask for USART_RXINV */
<> 153:fa9ff456f731 166 #define _USART_CTRL_RXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 167 #define USART_CTRL_RXINV_DEFAULT (_USART_CTRL_RXINV_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 168 #define USART_CTRL_TXINV (0x1UL << 14) /**< Transmitter output Invert */
<> 153:fa9ff456f731 169 #define _USART_CTRL_TXINV_SHIFT 14 /**< Shift value for USART_TXINV */
<> 153:fa9ff456f731 170 #define _USART_CTRL_TXINV_MASK 0x4000UL /**< Bit mask for USART_TXINV */
<> 153:fa9ff456f731 171 #define _USART_CTRL_TXINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 172 #define USART_CTRL_TXINV_DEFAULT (_USART_CTRL_TXINV_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 173 #define USART_CTRL_CSINV (0x1UL << 15) /**< Chip Select Invert */
<> 153:fa9ff456f731 174 #define _USART_CTRL_CSINV_SHIFT 15 /**< Shift value for USART_CSINV */
<> 153:fa9ff456f731 175 #define _USART_CTRL_CSINV_MASK 0x8000UL /**< Bit mask for USART_CSINV */
<> 153:fa9ff456f731 176 #define _USART_CTRL_CSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 177 #define USART_CTRL_CSINV_DEFAULT (_USART_CTRL_CSINV_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 178 #define USART_CTRL_AUTOCS (0x1UL << 16) /**< Automatic Chip Select */
<> 153:fa9ff456f731 179 #define _USART_CTRL_AUTOCS_SHIFT 16 /**< Shift value for USART_AUTOCS */
<> 153:fa9ff456f731 180 #define _USART_CTRL_AUTOCS_MASK 0x10000UL /**< Bit mask for USART_AUTOCS */
<> 153:fa9ff456f731 181 #define _USART_CTRL_AUTOCS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 182 #define USART_CTRL_AUTOCS_DEFAULT (_USART_CTRL_AUTOCS_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 183 #define USART_CTRL_AUTOTRI (0x1UL << 17) /**< Automatic TX Tristate */
<> 153:fa9ff456f731 184 #define _USART_CTRL_AUTOTRI_SHIFT 17 /**< Shift value for USART_AUTOTRI */
<> 153:fa9ff456f731 185 #define _USART_CTRL_AUTOTRI_MASK 0x20000UL /**< Bit mask for USART_AUTOTRI */
<> 153:fa9ff456f731 186 #define _USART_CTRL_AUTOTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 187 #define USART_CTRL_AUTOTRI_DEFAULT (_USART_CTRL_AUTOTRI_DEFAULT << 17) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 188 #define USART_CTRL_SCMODE (0x1UL << 18) /**< SmartCard Mode */
<> 153:fa9ff456f731 189 #define _USART_CTRL_SCMODE_SHIFT 18 /**< Shift value for USART_SCMODE */
<> 153:fa9ff456f731 190 #define _USART_CTRL_SCMODE_MASK 0x40000UL /**< Bit mask for USART_SCMODE */
<> 153:fa9ff456f731 191 #define _USART_CTRL_SCMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 192 #define USART_CTRL_SCMODE_DEFAULT (_USART_CTRL_SCMODE_DEFAULT << 18) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 193 #define USART_CTRL_SCRETRANS (0x1UL << 19) /**< SmartCard Retransmit */
<> 153:fa9ff456f731 194 #define _USART_CTRL_SCRETRANS_SHIFT 19 /**< Shift value for USART_SCRETRANS */
<> 153:fa9ff456f731 195 #define _USART_CTRL_SCRETRANS_MASK 0x80000UL /**< Bit mask for USART_SCRETRANS */
<> 153:fa9ff456f731 196 #define _USART_CTRL_SCRETRANS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 197 #define USART_CTRL_SCRETRANS_DEFAULT (_USART_CTRL_SCRETRANS_DEFAULT << 19) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 198 #define USART_CTRL_SKIPPERRF (0x1UL << 20) /**< Skip Parity Error Frames */
<> 153:fa9ff456f731 199 #define _USART_CTRL_SKIPPERRF_SHIFT 20 /**< Shift value for USART_SKIPPERRF */
<> 153:fa9ff456f731 200 #define _USART_CTRL_SKIPPERRF_MASK 0x100000UL /**< Bit mask for USART_SKIPPERRF */
<> 153:fa9ff456f731 201 #define _USART_CTRL_SKIPPERRF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 202 #define USART_CTRL_SKIPPERRF_DEFAULT (_USART_CTRL_SKIPPERRF_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 203 #define USART_CTRL_BIT8DV (0x1UL << 21) /**< Bit 8 Default Value */
<> 153:fa9ff456f731 204 #define _USART_CTRL_BIT8DV_SHIFT 21 /**< Shift value for USART_BIT8DV */
<> 153:fa9ff456f731 205 #define _USART_CTRL_BIT8DV_MASK 0x200000UL /**< Bit mask for USART_BIT8DV */
<> 153:fa9ff456f731 206 #define _USART_CTRL_BIT8DV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 207 #define USART_CTRL_BIT8DV_DEFAULT (_USART_CTRL_BIT8DV_DEFAULT << 21) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 208 #define USART_CTRL_ERRSDMA (0x1UL << 22) /**< Halt DMA On Error */
<> 153:fa9ff456f731 209 #define _USART_CTRL_ERRSDMA_SHIFT 22 /**< Shift value for USART_ERRSDMA */
<> 153:fa9ff456f731 210 #define _USART_CTRL_ERRSDMA_MASK 0x400000UL /**< Bit mask for USART_ERRSDMA */
<> 153:fa9ff456f731 211 #define _USART_CTRL_ERRSDMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 212 #define USART_CTRL_ERRSDMA_DEFAULT (_USART_CTRL_ERRSDMA_DEFAULT << 22) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 213 #define USART_CTRL_ERRSRX (0x1UL << 23) /**< Disable RX On Error */
<> 153:fa9ff456f731 214 #define _USART_CTRL_ERRSRX_SHIFT 23 /**< Shift value for USART_ERRSRX */
<> 153:fa9ff456f731 215 #define _USART_CTRL_ERRSRX_MASK 0x800000UL /**< Bit mask for USART_ERRSRX */
<> 153:fa9ff456f731 216 #define _USART_CTRL_ERRSRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 217 #define USART_CTRL_ERRSRX_DEFAULT (_USART_CTRL_ERRSRX_DEFAULT << 23) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 218 #define USART_CTRL_ERRSTX (0x1UL << 24) /**< Disable TX On Error */
<> 153:fa9ff456f731 219 #define _USART_CTRL_ERRSTX_SHIFT 24 /**< Shift value for USART_ERRSTX */
<> 153:fa9ff456f731 220 #define _USART_CTRL_ERRSTX_MASK 0x1000000UL /**< Bit mask for USART_ERRSTX */
<> 153:fa9ff456f731 221 #define _USART_CTRL_ERRSTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 222 #define USART_CTRL_ERRSTX_DEFAULT (_USART_CTRL_ERRSTX_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 223 #define USART_CTRL_SSSEARLY (0x1UL << 25) /**< Synchronous Slave Setup Early */
<> 153:fa9ff456f731 224 #define _USART_CTRL_SSSEARLY_SHIFT 25 /**< Shift value for USART_SSSEARLY */
<> 153:fa9ff456f731 225 #define _USART_CTRL_SSSEARLY_MASK 0x2000000UL /**< Bit mask for USART_SSSEARLY */
<> 153:fa9ff456f731 226 #define _USART_CTRL_SSSEARLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 227 #define USART_CTRL_SSSEARLY_DEFAULT (_USART_CTRL_SSSEARLY_DEFAULT << 25) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 228 #define USART_CTRL_BYTESWAP (0x1UL << 28) /**< Byteswap In Double Accesses */
<> 153:fa9ff456f731 229 #define _USART_CTRL_BYTESWAP_SHIFT 28 /**< Shift value for USART_BYTESWAP */
<> 153:fa9ff456f731 230 #define _USART_CTRL_BYTESWAP_MASK 0x10000000UL /**< Bit mask for USART_BYTESWAP */
<> 153:fa9ff456f731 231 #define _USART_CTRL_BYTESWAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 232 #define USART_CTRL_BYTESWAP_DEFAULT (_USART_CTRL_BYTESWAP_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 233 #define USART_CTRL_AUTOTX (0x1UL << 29) /**< Always Transmit When RX Not Full */
<> 153:fa9ff456f731 234 #define _USART_CTRL_AUTOTX_SHIFT 29 /**< Shift value for USART_AUTOTX */
<> 153:fa9ff456f731 235 #define _USART_CTRL_AUTOTX_MASK 0x20000000UL /**< Bit mask for USART_AUTOTX */
<> 153:fa9ff456f731 236 #define _USART_CTRL_AUTOTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 237 #define USART_CTRL_AUTOTX_DEFAULT (_USART_CTRL_AUTOTX_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 238 #define USART_CTRL_MVDIS (0x1UL << 30) /**< Majority Vote Disable */
<> 153:fa9ff456f731 239 #define _USART_CTRL_MVDIS_SHIFT 30 /**< Shift value for USART_MVDIS */
<> 153:fa9ff456f731 240 #define _USART_CTRL_MVDIS_MASK 0x40000000UL /**< Bit mask for USART_MVDIS */
<> 153:fa9ff456f731 241 #define _USART_CTRL_MVDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 242 #define USART_CTRL_MVDIS_DEFAULT (_USART_CTRL_MVDIS_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 243 #define USART_CTRL_SMSDELAY (0x1UL << 31) /**< Synchronous Master Sample Delay */
<> 153:fa9ff456f731 244 #define _USART_CTRL_SMSDELAY_SHIFT 31 /**< Shift value for USART_SMSDELAY */
<> 153:fa9ff456f731 245 #define _USART_CTRL_SMSDELAY_MASK 0x80000000UL /**< Bit mask for USART_SMSDELAY */
<> 153:fa9ff456f731 246 #define _USART_CTRL_SMSDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 247 #define USART_CTRL_SMSDELAY_DEFAULT (_USART_CTRL_SMSDELAY_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CTRL */
<> 153:fa9ff456f731 248
<> 153:fa9ff456f731 249 /* Bit fields for USART FRAME */
<> 153:fa9ff456f731 250 #define _USART_FRAME_RESETVALUE 0x00001005UL /**< Default value for USART_FRAME */
<> 153:fa9ff456f731 251 #define _USART_FRAME_MASK 0x0000330FUL /**< Mask for USART_FRAME */
<> 153:fa9ff456f731 252 #define _USART_FRAME_DATABITS_SHIFT 0 /**< Shift value for USART_DATABITS */
<> 153:fa9ff456f731 253 #define _USART_FRAME_DATABITS_MASK 0xFUL /**< Bit mask for USART_DATABITS */
<> 153:fa9ff456f731 254 #define _USART_FRAME_DATABITS_FOUR 0x00000001UL /**< Mode FOUR for USART_FRAME */
<> 153:fa9ff456f731 255 #define _USART_FRAME_DATABITS_FIVE 0x00000002UL /**< Mode FIVE for USART_FRAME */
<> 153:fa9ff456f731 256 #define _USART_FRAME_DATABITS_SIX 0x00000003UL /**< Mode SIX for USART_FRAME */
<> 153:fa9ff456f731 257 #define _USART_FRAME_DATABITS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_FRAME */
<> 153:fa9ff456f731 258 #define _USART_FRAME_DATABITS_DEFAULT 0x00000005UL /**< Mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 259 #define _USART_FRAME_DATABITS_EIGHT 0x00000005UL /**< Mode EIGHT for USART_FRAME */
<> 153:fa9ff456f731 260 #define _USART_FRAME_DATABITS_NINE 0x00000006UL /**< Mode NINE for USART_FRAME */
<> 153:fa9ff456f731 261 #define _USART_FRAME_DATABITS_TEN 0x00000007UL /**< Mode TEN for USART_FRAME */
<> 153:fa9ff456f731 262 #define _USART_FRAME_DATABITS_ELEVEN 0x00000008UL /**< Mode ELEVEN for USART_FRAME */
<> 153:fa9ff456f731 263 #define _USART_FRAME_DATABITS_TWELVE 0x00000009UL /**< Mode TWELVE for USART_FRAME */
<> 153:fa9ff456f731 264 #define _USART_FRAME_DATABITS_THIRTEEN 0x0000000AUL /**< Mode THIRTEEN for USART_FRAME */
<> 153:fa9ff456f731 265 #define _USART_FRAME_DATABITS_FOURTEEN 0x0000000BUL /**< Mode FOURTEEN for USART_FRAME */
<> 153:fa9ff456f731 266 #define _USART_FRAME_DATABITS_FIFTEEN 0x0000000CUL /**< Mode FIFTEEN for USART_FRAME */
<> 153:fa9ff456f731 267 #define _USART_FRAME_DATABITS_SIXTEEN 0x0000000DUL /**< Mode SIXTEEN for USART_FRAME */
<> 153:fa9ff456f731 268 #define USART_FRAME_DATABITS_FOUR (_USART_FRAME_DATABITS_FOUR << 0) /**< Shifted mode FOUR for USART_FRAME */
<> 153:fa9ff456f731 269 #define USART_FRAME_DATABITS_FIVE (_USART_FRAME_DATABITS_FIVE << 0) /**< Shifted mode FIVE for USART_FRAME */
<> 153:fa9ff456f731 270 #define USART_FRAME_DATABITS_SIX (_USART_FRAME_DATABITS_SIX << 0) /**< Shifted mode SIX for USART_FRAME */
<> 153:fa9ff456f731 271 #define USART_FRAME_DATABITS_SEVEN (_USART_FRAME_DATABITS_SEVEN << 0) /**< Shifted mode SEVEN for USART_FRAME */
<> 153:fa9ff456f731 272 #define USART_FRAME_DATABITS_DEFAULT (_USART_FRAME_DATABITS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 273 #define USART_FRAME_DATABITS_EIGHT (_USART_FRAME_DATABITS_EIGHT << 0) /**< Shifted mode EIGHT for USART_FRAME */
<> 153:fa9ff456f731 274 #define USART_FRAME_DATABITS_NINE (_USART_FRAME_DATABITS_NINE << 0) /**< Shifted mode NINE for USART_FRAME */
<> 153:fa9ff456f731 275 #define USART_FRAME_DATABITS_TEN (_USART_FRAME_DATABITS_TEN << 0) /**< Shifted mode TEN for USART_FRAME */
<> 153:fa9ff456f731 276 #define USART_FRAME_DATABITS_ELEVEN (_USART_FRAME_DATABITS_ELEVEN << 0) /**< Shifted mode ELEVEN for USART_FRAME */
<> 153:fa9ff456f731 277 #define USART_FRAME_DATABITS_TWELVE (_USART_FRAME_DATABITS_TWELVE << 0) /**< Shifted mode TWELVE for USART_FRAME */
<> 153:fa9ff456f731 278 #define USART_FRAME_DATABITS_THIRTEEN (_USART_FRAME_DATABITS_THIRTEEN << 0) /**< Shifted mode THIRTEEN for USART_FRAME */
<> 153:fa9ff456f731 279 #define USART_FRAME_DATABITS_FOURTEEN (_USART_FRAME_DATABITS_FOURTEEN << 0) /**< Shifted mode FOURTEEN for USART_FRAME */
<> 153:fa9ff456f731 280 #define USART_FRAME_DATABITS_FIFTEEN (_USART_FRAME_DATABITS_FIFTEEN << 0) /**< Shifted mode FIFTEEN for USART_FRAME */
<> 153:fa9ff456f731 281 #define USART_FRAME_DATABITS_SIXTEEN (_USART_FRAME_DATABITS_SIXTEEN << 0) /**< Shifted mode SIXTEEN for USART_FRAME */
<> 153:fa9ff456f731 282 #define _USART_FRAME_PARITY_SHIFT 8 /**< Shift value for USART_PARITY */
<> 153:fa9ff456f731 283 #define _USART_FRAME_PARITY_MASK 0x300UL /**< Bit mask for USART_PARITY */
<> 153:fa9ff456f731 284 #define _USART_FRAME_PARITY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 285 #define _USART_FRAME_PARITY_NONE 0x00000000UL /**< Mode NONE for USART_FRAME */
<> 153:fa9ff456f731 286 #define _USART_FRAME_PARITY_EVEN 0x00000002UL /**< Mode EVEN for USART_FRAME */
<> 153:fa9ff456f731 287 #define _USART_FRAME_PARITY_ODD 0x00000003UL /**< Mode ODD for USART_FRAME */
<> 153:fa9ff456f731 288 #define USART_FRAME_PARITY_DEFAULT (_USART_FRAME_PARITY_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 289 #define USART_FRAME_PARITY_NONE (_USART_FRAME_PARITY_NONE << 8) /**< Shifted mode NONE for USART_FRAME */
<> 153:fa9ff456f731 290 #define USART_FRAME_PARITY_EVEN (_USART_FRAME_PARITY_EVEN << 8) /**< Shifted mode EVEN for USART_FRAME */
<> 153:fa9ff456f731 291 #define USART_FRAME_PARITY_ODD (_USART_FRAME_PARITY_ODD << 8) /**< Shifted mode ODD for USART_FRAME */
<> 153:fa9ff456f731 292 #define _USART_FRAME_STOPBITS_SHIFT 12 /**< Shift value for USART_STOPBITS */
<> 153:fa9ff456f731 293 #define _USART_FRAME_STOPBITS_MASK 0x3000UL /**< Bit mask for USART_STOPBITS */
<> 153:fa9ff456f731 294 #define _USART_FRAME_STOPBITS_HALF 0x00000000UL /**< Mode HALF for USART_FRAME */
<> 153:fa9ff456f731 295 #define _USART_FRAME_STOPBITS_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 296 #define _USART_FRAME_STOPBITS_ONE 0x00000001UL /**< Mode ONE for USART_FRAME */
<> 153:fa9ff456f731 297 #define _USART_FRAME_STOPBITS_ONEANDAHALF 0x00000002UL /**< Mode ONEANDAHALF for USART_FRAME */
<> 153:fa9ff456f731 298 #define _USART_FRAME_STOPBITS_TWO 0x00000003UL /**< Mode TWO for USART_FRAME */
<> 153:fa9ff456f731 299 #define USART_FRAME_STOPBITS_HALF (_USART_FRAME_STOPBITS_HALF << 12) /**< Shifted mode HALF for USART_FRAME */
<> 153:fa9ff456f731 300 #define USART_FRAME_STOPBITS_DEFAULT (_USART_FRAME_STOPBITS_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_FRAME */
<> 153:fa9ff456f731 301 #define USART_FRAME_STOPBITS_ONE (_USART_FRAME_STOPBITS_ONE << 12) /**< Shifted mode ONE for USART_FRAME */
<> 153:fa9ff456f731 302 #define USART_FRAME_STOPBITS_ONEANDAHALF (_USART_FRAME_STOPBITS_ONEANDAHALF << 12) /**< Shifted mode ONEANDAHALF for USART_FRAME */
<> 153:fa9ff456f731 303 #define USART_FRAME_STOPBITS_TWO (_USART_FRAME_STOPBITS_TWO << 12) /**< Shifted mode TWO for USART_FRAME */
<> 153:fa9ff456f731 304
<> 153:fa9ff456f731 305 /* Bit fields for USART TRIGCTRL */
<> 153:fa9ff456f731 306 #define _USART_TRIGCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_TRIGCTRL */
<> 153:fa9ff456f731 307 #define _USART_TRIGCTRL_MASK 0x000F1FF0UL /**< Mask for USART_TRIGCTRL */
<> 153:fa9ff456f731 308 #define USART_TRIGCTRL_RXTEN (0x1UL << 4) /**< Receive Trigger Enable */
<> 153:fa9ff456f731 309 #define _USART_TRIGCTRL_RXTEN_SHIFT 4 /**< Shift value for USART_RXTEN */
<> 153:fa9ff456f731 310 #define _USART_TRIGCTRL_RXTEN_MASK 0x10UL /**< Bit mask for USART_RXTEN */
<> 153:fa9ff456f731 311 #define _USART_TRIGCTRL_RXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 312 #define USART_TRIGCTRL_RXTEN_DEFAULT (_USART_TRIGCTRL_RXTEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 313 #define USART_TRIGCTRL_TXTEN (0x1UL << 5) /**< Transmit Trigger Enable */
<> 153:fa9ff456f731 314 #define _USART_TRIGCTRL_TXTEN_SHIFT 5 /**< Shift value for USART_TXTEN */
<> 153:fa9ff456f731 315 #define _USART_TRIGCTRL_TXTEN_MASK 0x20UL /**< Bit mask for USART_TXTEN */
<> 153:fa9ff456f731 316 #define _USART_TRIGCTRL_TXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 317 #define USART_TRIGCTRL_TXTEN_DEFAULT (_USART_TRIGCTRL_TXTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 318 #define USART_TRIGCTRL_AUTOTXTEN (0x1UL << 6) /**< AUTOTX Trigger Enable */
<> 153:fa9ff456f731 319 #define _USART_TRIGCTRL_AUTOTXTEN_SHIFT 6 /**< Shift value for USART_AUTOTXTEN */
<> 153:fa9ff456f731 320 #define _USART_TRIGCTRL_AUTOTXTEN_MASK 0x40UL /**< Bit mask for USART_AUTOTXTEN */
<> 153:fa9ff456f731 321 #define _USART_TRIGCTRL_AUTOTXTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 322 #define USART_TRIGCTRL_AUTOTXTEN_DEFAULT (_USART_TRIGCTRL_AUTOTXTEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 323 #define USART_TRIGCTRL_TXARX0EN (0x1UL << 7) /**< Enable Transmit Trigger after RX End of Frame plus TCMP0VAL */
<> 153:fa9ff456f731 324 #define _USART_TRIGCTRL_TXARX0EN_SHIFT 7 /**< Shift value for USART_TXARX0EN */
<> 153:fa9ff456f731 325 #define _USART_TRIGCTRL_TXARX0EN_MASK 0x80UL /**< Bit mask for USART_TXARX0EN */
<> 153:fa9ff456f731 326 #define _USART_TRIGCTRL_TXARX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 327 #define USART_TRIGCTRL_TXARX0EN_DEFAULT (_USART_TRIGCTRL_TXARX0EN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 328 #define USART_TRIGCTRL_TXARX1EN (0x1UL << 8) /**< Enable Transmit Trigger after RX End of Frame plus TCMP1VAL */
<> 153:fa9ff456f731 329 #define _USART_TRIGCTRL_TXARX1EN_SHIFT 8 /**< Shift value for USART_TXARX1EN */
<> 153:fa9ff456f731 330 #define _USART_TRIGCTRL_TXARX1EN_MASK 0x100UL /**< Bit mask for USART_TXARX1EN */
<> 153:fa9ff456f731 331 #define _USART_TRIGCTRL_TXARX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 332 #define USART_TRIGCTRL_TXARX1EN_DEFAULT (_USART_TRIGCTRL_TXARX1EN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 333 #define USART_TRIGCTRL_TXARX2EN (0x1UL << 9) /**< Enable Transmit Trigger after RX End of Frame plus TCMP2VAL */
<> 153:fa9ff456f731 334 #define _USART_TRIGCTRL_TXARX2EN_SHIFT 9 /**< Shift value for USART_TXARX2EN */
<> 153:fa9ff456f731 335 #define _USART_TRIGCTRL_TXARX2EN_MASK 0x200UL /**< Bit mask for USART_TXARX2EN */
<> 153:fa9ff456f731 336 #define _USART_TRIGCTRL_TXARX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 337 #define USART_TRIGCTRL_TXARX2EN_DEFAULT (_USART_TRIGCTRL_TXARX2EN_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 338 #define USART_TRIGCTRL_RXATX0EN (0x1UL << 10) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL0 baud-times */
<> 153:fa9ff456f731 339 #define _USART_TRIGCTRL_RXATX0EN_SHIFT 10 /**< Shift value for USART_RXATX0EN */
<> 153:fa9ff456f731 340 #define _USART_TRIGCTRL_RXATX0EN_MASK 0x400UL /**< Bit mask for USART_RXATX0EN */
<> 153:fa9ff456f731 341 #define _USART_TRIGCTRL_RXATX0EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 342 #define USART_TRIGCTRL_RXATX0EN_DEFAULT (_USART_TRIGCTRL_RXATX0EN_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 343 #define USART_TRIGCTRL_RXATX1EN (0x1UL << 11) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL1 baud-times */
<> 153:fa9ff456f731 344 #define _USART_TRIGCTRL_RXATX1EN_SHIFT 11 /**< Shift value for USART_RXATX1EN */
<> 153:fa9ff456f731 345 #define _USART_TRIGCTRL_RXATX1EN_MASK 0x800UL /**< Bit mask for USART_RXATX1EN */
<> 153:fa9ff456f731 346 #define _USART_TRIGCTRL_RXATX1EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 347 #define USART_TRIGCTRL_RXATX1EN_DEFAULT (_USART_TRIGCTRL_RXATX1EN_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 348 #define USART_TRIGCTRL_RXATX2EN (0x1UL << 12) /**< Enable Receive Trigger after TX end of frame plus TCMPVAL2 baud-times */
<> 153:fa9ff456f731 349 #define _USART_TRIGCTRL_RXATX2EN_SHIFT 12 /**< Shift value for USART_RXATX2EN */
<> 153:fa9ff456f731 350 #define _USART_TRIGCTRL_RXATX2EN_MASK 0x1000UL /**< Bit mask for USART_RXATX2EN */
<> 153:fa9ff456f731 351 #define _USART_TRIGCTRL_RXATX2EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 352 #define USART_TRIGCTRL_RXATX2EN_DEFAULT (_USART_TRIGCTRL_RXATX2EN_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 353 #define _USART_TRIGCTRL_TSEL_SHIFT 16 /**< Shift value for USART_TSEL */
<> 153:fa9ff456f731 354 #define _USART_TRIGCTRL_TSEL_MASK 0xF0000UL /**< Bit mask for USART_TSEL */
<> 153:fa9ff456f731 355 #define _USART_TRIGCTRL_TSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 356 #define _USART_TRIGCTRL_TSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_TRIGCTRL */
<> 153:fa9ff456f731 357 #define _USART_TRIGCTRL_TSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_TRIGCTRL */
<> 153:fa9ff456f731 358 #define _USART_TRIGCTRL_TSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_TRIGCTRL */
<> 153:fa9ff456f731 359 #define _USART_TRIGCTRL_TSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_TRIGCTRL */
<> 153:fa9ff456f731 360 #define _USART_TRIGCTRL_TSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_TRIGCTRL */
<> 153:fa9ff456f731 361 #define _USART_TRIGCTRL_TSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_TRIGCTRL */
<> 153:fa9ff456f731 362 #define _USART_TRIGCTRL_TSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_TRIGCTRL */
<> 153:fa9ff456f731 363 #define _USART_TRIGCTRL_TSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_TRIGCTRL */
<> 153:fa9ff456f731 364 #define _USART_TRIGCTRL_TSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_TRIGCTRL */
<> 153:fa9ff456f731 365 #define _USART_TRIGCTRL_TSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_TRIGCTRL */
<> 153:fa9ff456f731 366 #define _USART_TRIGCTRL_TSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_TRIGCTRL */
<> 153:fa9ff456f731 367 #define _USART_TRIGCTRL_TSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_TRIGCTRL */
<> 153:fa9ff456f731 368 #define USART_TRIGCTRL_TSEL_DEFAULT (_USART_TRIGCTRL_TSEL_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TRIGCTRL */
<> 153:fa9ff456f731 369 #define USART_TRIGCTRL_TSEL_PRSCH0 (_USART_TRIGCTRL_TSEL_PRSCH0 << 16) /**< Shifted mode PRSCH0 for USART_TRIGCTRL */
<> 153:fa9ff456f731 370 #define USART_TRIGCTRL_TSEL_PRSCH1 (_USART_TRIGCTRL_TSEL_PRSCH1 << 16) /**< Shifted mode PRSCH1 for USART_TRIGCTRL */
<> 153:fa9ff456f731 371 #define USART_TRIGCTRL_TSEL_PRSCH2 (_USART_TRIGCTRL_TSEL_PRSCH2 << 16) /**< Shifted mode PRSCH2 for USART_TRIGCTRL */
<> 153:fa9ff456f731 372 #define USART_TRIGCTRL_TSEL_PRSCH3 (_USART_TRIGCTRL_TSEL_PRSCH3 << 16) /**< Shifted mode PRSCH3 for USART_TRIGCTRL */
<> 153:fa9ff456f731 373 #define USART_TRIGCTRL_TSEL_PRSCH4 (_USART_TRIGCTRL_TSEL_PRSCH4 << 16) /**< Shifted mode PRSCH4 for USART_TRIGCTRL */
<> 153:fa9ff456f731 374 #define USART_TRIGCTRL_TSEL_PRSCH5 (_USART_TRIGCTRL_TSEL_PRSCH5 << 16) /**< Shifted mode PRSCH5 for USART_TRIGCTRL */
<> 153:fa9ff456f731 375 #define USART_TRIGCTRL_TSEL_PRSCH6 (_USART_TRIGCTRL_TSEL_PRSCH6 << 16) /**< Shifted mode PRSCH6 for USART_TRIGCTRL */
<> 153:fa9ff456f731 376 #define USART_TRIGCTRL_TSEL_PRSCH7 (_USART_TRIGCTRL_TSEL_PRSCH7 << 16) /**< Shifted mode PRSCH7 for USART_TRIGCTRL */
<> 153:fa9ff456f731 377 #define USART_TRIGCTRL_TSEL_PRSCH8 (_USART_TRIGCTRL_TSEL_PRSCH8 << 16) /**< Shifted mode PRSCH8 for USART_TRIGCTRL */
<> 153:fa9ff456f731 378 #define USART_TRIGCTRL_TSEL_PRSCH9 (_USART_TRIGCTRL_TSEL_PRSCH9 << 16) /**< Shifted mode PRSCH9 for USART_TRIGCTRL */
<> 153:fa9ff456f731 379 #define USART_TRIGCTRL_TSEL_PRSCH10 (_USART_TRIGCTRL_TSEL_PRSCH10 << 16) /**< Shifted mode PRSCH10 for USART_TRIGCTRL */
<> 153:fa9ff456f731 380 #define USART_TRIGCTRL_TSEL_PRSCH11 (_USART_TRIGCTRL_TSEL_PRSCH11 << 16) /**< Shifted mode PRSCH11 for USART_TRIGCTRL */
<> 153:fa9ff456f731 381
<> 153:fa9ff456f731 382 /* Bit fields for USART CMD */
<> 153:fa9ff456f731 383 #define _USART_CMD_RESETVALUE 0x00000000UL /**< Default value for USART_CMD */
<> 153:fa9ff456f731 384 #define _USART_CMD_MASK 0x00000FFFUL /**< Mask for USART_CMD */
<> 153:fa9ff456f731 385 #define USART_CMD_RXEN (0x1UL << 0) /**< Receiver Enable */
<> 153:fa9ff456f731 386 #define _USART_CMD_RXEN_SHIFT 0 /**< Shift value for USART_RXEN */
<> 153:fa9ff456f731 387 #define _USART_CMD_RXEN_MASK 0x1UL /**< Bit mask for USART_RXEN */
<> 153:fa9ff456f731 388 #define _USART_CMD_RXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 389 #define USART_CMD_RXEN_DEFAULT (_USART_CMD_RXEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 390 #define USART_CMD_RXDIS (0x1UL << 1) /**< Receiver Disable */
<> 153:fa9ff456f731 391 #define _USART_CMD_RXDIS_SHIFT 1 /**< Shift value for USART_RXDIS */
<> 153:fa9ff456f731 392 #define _USART_CMD_RXDIS_MASK 0x2UL /**< Bit mask for USART_RXDIS */
<> 153:fa9ff456f731 393 #define _USART_CMD_RXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 394 #define USART_CMD_RXDIS_DEFAULT (_USART_CMD_RXDIS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 395 #define USART_CMD_TXEN (0x1UL << 2) /**< Transmitter Enable */
<> 153:fa9ff456f731 396 #define _USART_CMD_TXEN_SHIFT 2 /**< Shift value for USART_TXEN */
<> 153:fa9ff456f731 397 #define _USART_CMD_TXEN_MASK 0x4UL /**< Bit mask for USART_TXEN */
<> 153:fa9ff456f731 398 #define _USART_CMD_TXEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 399 #define USART_CMD_TXEN_DEFAULT (_USART_CMD_TXEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 400 #define USART_CMD_TXDIS (0x1UL << 3) /**< Transmitter Disable */
<> 153:fa9ff456f731 401 #define _USART_CMD_TXDIS_SHIFT 3 /**< Shift value for USART_TXDIS */
<> 153:fa9ff456f731 402 #define _USART_CMD_TXDIS_MASK 0x8UL /**< Bit mask for USART_TXDIS */
<> 153:fa9ff456f731 403 #define _USART_CMD_TXDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 404 #define USART_CMD_TXDIS_DEFAULT (_USART_CMD_TXDIS_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 405 #define USART_CMD_MASTEREN (0x1UL << 4) /**< Master Enable */
<> 153:fa9ff456f731 406 #define _USART_CMD_MASTEREN_SHIFT 4 /**< Shift value for USART_MASTEREN */
<> 153:fa9ff456f731 407 #define _USART_CMD_MASTEREN_MASK 0x10UL /**< Bit mask for USART_MASTEREN */
<> 153:fa9ff456f731 408 #define _USART_CMD_MASTEREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 409 #define USART_CMD_MASTEREN_DEFAULT (_USART_CMD_MASTEREN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 410 #define USART_CMD_MASTERDIS (0x1UL << 5) /**< Master Disable */
<> 153:fa9ff456f731 411 #define _USART_CMD_MASTERDIS_SHIFT 5 /**< Shift value for USART_MASTERDIS */
<> 153:fa9ff456f731 412 #define _USART_CMD_MASTERDIS_MASK 0x20UL /**< Bit mask for USART_MASTERDIS */
<> 153:fa9ff456f731 413 #define _USART_CMD_MASTERDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 414 #define USART_CMD_MASTERDIS_DEFAULT (_USART_CMD_MASTERDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 415 #define USART_CMD_RXBLOCKEN (0x1UL << 6) /**< Receiver Block Enable */
<> 153:fa9ff456f731 416 #define _USART_CMD_RXBLOCKEN_SHIFT 6 /**< Shift value for USART_RXBLOCKEN */
<> 153:fa9ff456f731 417 #define _USART_CMD_RXBLOCKEN_MASK 0x40UL /**< Bit mask for USART_RXBLOCKEN */
<> 153:fa9ff456f731 418 #define _USART_CMD_RXBLOCKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 419 #define USART_CMD_RXBLOCKEN_DEFAULT (_USART_CMD_RXBLOCKEN_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 420 #define USART_CMD_RXBLOCKDIS (0x1UL << 7) /**< Receiver Block Disable */
<> 153:fa9ff456f731 421 #define _USART_CMD_RXBLOCKDIS_SHIFT 7 /**< Shift value for USART_RXBLOCKDIS */
<> 153:fa9ff456f731 422 #define _USART_CMD_RXBLOCKDIS_MASK 0x80UL /**< Bit mask for USART_RXBLOCKDIS */
<> 153:fa9ff456f731 423 #define _USART_CMD_RXBLOCKDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 424 #define USART_CMD_RXBLOCKDIS_DEFAULT (_USART_CMD_RXBLOCKDIS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 425 #define USART_CMD_TXTRIEN (0x1UL << 8) /**< Transmitter Tristate Enable */
<> 153:fa9ff456f731 426 #define _USART_CMD_TXTRIEN_SHIFT 8 /**< Shift value for USART_TXTRIEN */
<> 153:fa9ff456f731 427 #define _USART_CMD_TXTRIEN_MASK 0x100UL /**< Bit mask for USART_TXTRIEN */
<> 153:fa9ff456f731 428 #define _USART_CMD_TXTRIEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 429 #define USART_CMD_TXTRIEN_DEFAULT (_USART_CMD_TXTRIEN_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 430 #define USART_CMD_TXTRIDIS (0x1UL << 9) /**< Transmitter Tristate Disable */
<> 153:fa9ff456f731 431 #define _USART_CMD_TXTRIDIS_SHIFT 9 /**< Shift value for USART_TXTRIDIS */
<> 153:fa9ff456f731 432 #define _USART_CMD_TXTRIDIS_MASK 0x200UL /**< Bit mask for USART_TXTRIDIS */
<> 153:fa9ff456f731 433 #define _USART_CMD_TXTRIDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 434 #define USART_CMD_TXTRIDIS_DEFAULT (_USART_CMD_TXTRIDIS_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 435 #define USART_CMD_CLEARTX (0x1UL << 10) /**< Clear TX */
<> 153:fa9ff456f731 436 #define _USART_CMD_CLEARTX_SHIFT 10 /**< Shift value for USART_CLEARTX */
<> 153:fa9ff456f731 437 #define _USART_CMD_CLEARTX_MASK 0x400UL /**< Bit mask for USART_CLEARTX */
<> 153:fa9ff456f731 438 #define _USART_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 439 #define USART_CMD_CLEARTX_DEFAULT (_USART_CMD_CLEARTX_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 440 #define USART_CMD_CLEARRX (0x1UL << 11) /**< Clear RX */
<> 153:fa9ff456f731 441 #define _USART_CMD_CLEARRX_SHIFT 11 /**< Shift value for USART_CLEARRX */
<> 153:fa9ff456f731 442 #define _USART_CMD_CLEARRX_MASK 0x800UL /**< Bit mask for USART_CLEARRX */
<> 153:fa9ff456f731 443 #define _USART_CMD_CLEARRX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 444 #define USART_CMD_CLEARRX_DEFAULT (_USART_CMD_CLEARRX_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_CMD */
<> 153:fa9ff456f731 445
<> 153:fa9ff456f731 446 /* Bit fields for USART STATUS */
<> 153:fa9ff456f731 447 #define _USART_STATUS_RESETVALUE 0x00002040UL /**< Default value for USART_STATUS */
<> 153:fa9ff456f731 448 #define _USART_STATUS_MASK 0x00037FFFUL /**< Mask for USART_STATUS */
<> 153:fa9ff456f731 449 #define USART_STATUS_RXENS (0x1UL << 0) /**< Receiver Enable Status */
<> 153:fa9ff456f731 450 #define _USART_STATUS_RXENS_SHIFT 0 /**< Shift value for USART_RXENS */
<> 153:fa9ff456f731 451 #define _USART_STATUS_RXENS_MASK 0x1UL /**< Bit mask for USART_RXENS */
<> 153:fa9ff456f731 452 #define _USART_STATUS_RXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 453 #define USART_STATUS_RXENS_DEFAULT (_USART_STATUS_RXENS_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 454 #define USART_STATUS_TXENS (0x1UL << 1) /**< Transmitter Enable Status */
<> 153:fa9ff456f731 455 #define _USART_STATUS_TXENS_SHIFT 1 /**< Shift value for USART_TXENS */
<> 153:fa9ff456f731 456 #define _USART_STATUS_TXENS_MASK 0x2UL /**< Bit mask for USART_TXENS */
<> 153:fa9ff456f731 457 #define _USART_STATUS_TXENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 458 #define USART_STATUS_TXENS_DEFAULT (_USART_STATUS_TXENS_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 459 #define USART_STATUS_MASTER (0x1UL << 2) /**< SPI Master Mode */
<> 153:fa9ff456f731 460 #define _USART_STATUS_MASTER_SHIFT 2 /**< Shift value for USART_MASTER */
<> 153:fa9ff456f731 461 #define _USART_STATUS_MASTER_MASK 0x4UL /**< Bit mask for USART_MASTER */
<> 153:fa9ff456f731 462 #define _USART_STATUS_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 463 #define USART_STATUS_MASTER_DEFAULT (_USART_STATUS_MASTER_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 464 #define USART_STATUS_RXBLOCK (0x1UL << 3) /**< Block Incoming Data */
<> 153:fa9ff456f731 465 #define _USART_STATUS_RXBLOCK_SHIFT 3 /**< Shift value for USART_RXBLOCK */
<> 153:fa9ff456f731 466 #define _USART_STATUS_RXBLOCK_MASK 0x8UL /**< Bit mask for USART_RXBLOCK */
<> 153:fa9ff456f731 467 #define _USART_STATUS_RXBLOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 468 #define USART_STATUS_RXBLOCK_DEFAULT (_USART_STATUS_RXBLOCK_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 469 #define USART_STATUS_TXTRI (0x1UL << 4) /**< Transmitter Tristated */
<> 153:fa9ff456f731 470 #define _USART_STATUS_TXTRI_SHIFT 4 /**< Shift value for USART_TXTRI */
<> 153:fa9ff456f731 471 #define _USART_STATUS_TXTRI_MASK 0x10UL /**< Bit mask for USART_TXTRI */
<> 153:fa9ff456f731 472 #define _USART_STATUS_TXTRI_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 473 #define USART_STATUS_TXTRI_DEFAULT (_USART_STATUS_TXTRI_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 474 #define USART_STATUS_TXC (0x1UL << 5) /**< TX Complete */
<> 153:fa9ff456f731 475 #define _USART_STATUS_TXC_SHIFT 5 /**< Shift value for USART_TXC */
<> 153:fa9ff456f731 476 #define _USART_STATUS_TXC_MASK 0x20UL /**< Bit mask for USART_TXC */
<> 153:fa9ff456f731 477 #define _USART_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 478 #define USART_STATUS_TXC_DEFAULT (_USART_STATUS_TXC_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 479 #define USART_STATUS_TXBL (0x1UL << 6) /**< TX Buffer Level */
<> 153:fa9ff456f731 480 #define _USART_STATUS_TXBL_SHIFT 6 /**< Shift value for USART_TXBL */
<> 153:fa9ff456f731 481 #define _USART_STATUS_TXBL_MASK 0x40UL /**< Bit mask for USART_TXBL */
<> 153:fa9ff456f731 482 #define _USART_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 483 #define USART_STATUS_TXBL_DEFAULT (_USART_STATUS_TXBL_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 484 #define USART_STATUS_RXDATAV (0x1UL << 7) /**< RX Data Valid */
<> 153:fa9ff456f731 485 #define _USART_STATUS_RXDATAV_SHIFT 7 /**< Shift value for USART_RXDATAV */
<> 153:fa9ff456f731 486 #define _USART_STATUS_RXDATAV_MASK 0x80UL /**< Bit mask for USART_RXDATAV */
<> 153:fa9ff456f731 487 #define _USART_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 488 #define USART_STATUS_RXDATAV_DEFAULT (_USART_STATUS_RXDATAV_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 489 #define USART_STATUS_RXFULL (0x1UL << 8) /**< RX FIFO Full */
<> 153:fa9ff456f731 490 #define _USART_STATUS_RXFULL_SHIFT 8 /**< Shift value for USART_RXFULL */
<> 153:fa9ff456f731 491 #define _USART_STATUS_RXFULL_MASK 0x100UL /**< Bit mask for USART_RXFULL */
<> 153:fa9ff456f731 492 #define _USART_STATUS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 493 #define USART_STATUS_RXFULL_DEFAULT (_USART_STATUS_RXFULL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 494 #define USART_STATUS_TXBDRIGHT (0x1UL << 9) /**< TX Buffer Expects Double Right Data */
<> 153:fa9ff456f731 495 #define _USART_STATUS_TXBDRIGHT_SHIFT 9 /**< Shift value for USART_TXBDRIGHT */
<> 153:fa9ff456f731 496 #define _USART_STATUS_TXBDRIGHT_MASK 0x200UL /**< Bit mask for USART_TXBDRIGHT */
<> 153:fa9ff456f731 497 #define _USART_STATUS_TXBDRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 498 #define USART_STATUS_TXBDRIGHT_DEFAULT (_USART_STATUS_TXBDRIGHT_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 499 #define USART_STATUS_TXBSRIGHT (0x1UL << 10) /**< TX Buffer Expects Single Right Data */
<> 153:fa9ff456f731 500 #define _USART_STATUS_TXBSRIGHT_SHIFT 10 /**< Shift value for USART_TXBSRIGHT */
<> 153:fa9ff456f731 501 #define _USART_STATUS_TXBSRIGHT_MASK 0x400UL /**< Bit mask for USART_TXBSRIGHT */
<> 153:fa9ff456f731 502 #define _USART_STATUS_TXBSRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 503 #define USART_STATUS_TXBSRIGHT_DEFAULT (_USART_STATUS_TXBSRIGHT_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 504 #define USART_STATUS_RXDATAVRIGHT (0x1UL << 11) /**< RX Data Right */
<> 153:fa9ff456f731 505 #define _USART_STATUS_RXDATAVRIGHT_SHIFT 11 /**< Shift value for USART_RXDATAVRIGHT */
<> 153:fa9ff456f731 506 #define _USART_STATUS_RXDATAVRIGHT_MASK 0x800UL /**< Bit mask for USART_RXDATAVRIGHT */
<> 153:fa9ff456f731 507 #define _USART_STATUS_RXDATAVRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 508 #define USART_STATUS_RXDATAVRIGHT_DEFAULT (_USART_STATUS_RXDATAVRIGHT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 509 #define USART_STATUS_RXFULLRIGHT (0x1UL << 12) /**< RX Full of Right Data */
<> 153:fa9ff456f731 510 #define _USART_STATUS_RXFULLRIGHT_SHIFT 12 /**< Shift value for USART_RXFULLRIGHT */
<> 153:fa9ff456f731 511 #define _USART_STATUS_RXFULLRIGHT_MASK 0x1000UL /**< Bit mask for USART_RXFULLRIGHT */
<> 153:fa9ff456f731 512 #define _USART_STATUS_RXFULLRIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 513 #define USART_STATUS_RXFULLRIGHT_DEFAULT (_USART_STATUS_RXFULLRIGHT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 514 #define USART_STATUS_TXIDLE (0x1UL << 13) /**< TX Idle */
<> 153:fa9ff456f731 515 #define _USART_STATUS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 153:fa9ff456f731 516 #define _USART_STATUS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 153:fa9ff456f731 517 #define _USART_STATUS_TXIDLE_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 518 #define USART_STATUS_TXIDLE_DEFAULT (_USART_STATUS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 519 #define USART_STATUS_TIMERRESTARTED (0x1UL << 14) /**< The USART Timer restarted itself */
<> 153:fa9ff456f731 520 #define _USART_STATUS_TIMERRESTARTED_SHIFT 14 /**< Shift value for USART_TIMERRESTARTED */
<> 153:fa9ff456f731 521 #define _USART_STATUS_TIMERRESTARTED_MASK 0x4000UL /**< Bit mask for USART_TIMERRESTARTED */
<> 153:fa9ff456f731 522 #define _USART_STATUS_TIMERRESTARTED_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 523 #define USART_STATUS_TIMERRESTARTED_DEFAULT (_USART_STATUS_TIMERRESTARTED_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 524 #define _USART_STATUS_TXBUFCNT_SHIFT 16 /**< Shift value for USART_TXBUFCNT */
<> 153:fa9ff456f731 525 #define _USART_STATUS_TXBUFCNT_MASK 0x30000UL /**< Bit mask for USART_TXBUFCNT */
<> 153:fa9ff456f731 526 #define _USART_STATUS_TXBUFCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 527 #define USART_STATUS_TXBUFCNT_DEFAULT (_USART_STATUS_TXBUFCNT_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_STATUS */
<> 153:fa9ff456f731 528
<> 153:fa9ff456f731 529 /* Bit fields for USART CLKDIV */
<> 153:fa9ff456f731 530 #define _USART_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for USART_CLKDIV */
<> 153:fa9ff456f731 531 #define _USART_CLKDIV_MASK 0x807FFFF8UL /**< Mask for USART_CLKDIV */
<> 153:fa9ff456f731 532 #define _USART_CLKDIV_DIV_SHIFT 3 /**< Shift value for USART_DIV */
<> 153:fa9ff456f731 533 #define _USART_CLKDIV_DIV_MASK 0x7FFFF8UL /**< Bit mask for USART_DIV */
<> 153:fa9ff456f731 534 #define _USART_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
<> 153:fa9ff456f731 535 #define USART_CLKDIV_DIV_DEFAULT (_USART_CLKDIV_DIV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CLKDIV */
<> 153:fa9ff456f731 536 #define USART_CLKDIV_AUTOBAUDEN (0x1UL << 31) /**< AUTOBAUD detection enable */
<> 153:fa9ff456f731 537 #define _USART_CLKDIV_AUTOBAUDEN_SHIFT 31 /**< Shift value for USART_AUTOBAUDEN */
<> 153:fa9ff456f731 538 #define _USART_CLKDIV_AUTOBAUDEN_MASK 0x80000000UL /**< Bit mask for USART_AUTOBAUDEN */
<> 153:fa9ff456f731 539 #define _USART_CLKDIV_AUTOBAUDEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CLKDIV */
<> 153:fa9ff456f731 540 #define USART_CLKDIV_AUTOBAUDEN_DEFAULT (_USART_CLKDIV_AUTOBAUDEN_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_CLKDIV */
<> 153:fa9ff456f731 541
<> 153:fa9ff456f731 542 /* Bit fields for USART RXDATAX */
<> 153:fa9ff456f731 543 #define _USART_RXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAX */
<> 153:fa9ff456f731 544 #define _USART_RXDATAX_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAX */
<> 153:fa9ff456f731 545 #define _USART_RXDATAX_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 153:fa9ff456f731 546 #define _USART_RXDATAX_RXDATA_MASK 0x1FFUL /**< Bit mask for USART_RXDATA */
<> 153:fa9ff456f731 547 #define _USART_RXDATAX_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 548 #define USART_RXDATAX_RXDATA_DEFAULT (_USART_RXDATAX_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 549 #define USART_RXDATAX_PERR (0x1UL << 14) /**< Data Parity Error */
<> 153:fa9ff456f731 550 #define _USART_RXDATAX_PERR_SHIFT 14 /**< Shift value for USART_PERR */
<> 153:fa9ff456f731 551 #define _USART_RXDATAX_PERR_MASK 0x4000UL /**< Bit mask for USART_PERR */
<> 153:fa9ff456f731 552 #define _USART_RXDATAX_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 553 #define USART_RXDATAX_PERR_DEFAULT (_USART_RXDATAX_PERR_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 554 #define USART_RXDATAX_FERR (0x1UL << 15) /**< Data Framing Error */
<> 153:fa9ff456f731 555 #define _USART_RXDATAX_FERR_SHIFT 15 /**< Shift value for USART_FERR */
<> 153:fa9ff456f731 556 #define _USART_RXDATAX_FERR_MASK 0x8000UL /**< Bit mask for USART_FERR */
<> 153:fa9ff456f731 557 #define _USART_RXDATAX_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 558 #define USART_RXDATAX_FERR_DEFAULT (_USART_RXDATAX_FERR_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAX */
<> 153:fa9ff456f731 559
<> 153:fa9ff456f731 560 /* Bit fields for USART RXDATA */
<> 153:fa9ff456f731 561 #define _USART_RXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATA */
<> 153:fa9ff456f731 562 #define _USART_RXDATA_MASK 0x000000FFUL /**< Mask for USART_RXDATA */
<> 153:fa9ff456f731 563 #define _USART_RXDATA_RXDATA_SHIFT 0 /**< Shift value for USART_RXDATA */
<> 153:fa9ff456f731 564 #define _USART_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for USART_RXDATA */
<> 153:fa9ff456f731 565 #define _USART_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATA */
<> 153:fa9ff456f731 566 #define USART_RXDATA_RXDATA_DEFAULT (_USART_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATA */
<> 153:fa9ff456f731 567
<> 153:fa9ff456f731 568 /* Bit fields for USART RXDOUBLEX */
<> 153:fa9ff456f731 569 #define _USART_RXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEX */
<> 153:fa9ff456f731 570 #define _USART_RXDOUBLEX_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEX */
<> 153:fa9ff456f731 571 #define _USART_RXDOUBLEX_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 153:fa9ff456f731 572 #define _USART_RXDOUBLEX_RXDATA0_MASK 0x1FFUL /**< Bit mask for USART_RXDATA0 */
<> 153:fa9ff456f731 573 #define _USART_RXDOUBLEX_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 574 #define USART_RXDOUBLEX_RXDATA0_DEFAULT (_USART_RXDOUBLEX_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 575 #define USART_RXDOUBLEX_PERR0 (0x1UL << 14) /**< Data Parity Error 0 */
<> 153:fa9ff456f731 576 #define _USART_RXDOUBLEX_PERR0_SHIFT 14 /**< Shift value for USART_PERR0 */
<> 153:fa9ff456f731 577 #define _USART_RXDOUBLEX_PERR0_MASK 0x4000UL /**< Bit mask for USART_PERR0 */
<> 153:fa9ff456f731 578 #define _USART_RXDOUBLEX_PERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 579 #define USART_RXDOUBLEX_PERR0_DEFAULT (_USART_RXDOUBLEX_PERR0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 580 #define USART_RXDOUBLEX_FERR0 (0x1UL << 15) /**< Data Framing Error 0 */
<> 153:fa9ff456f731 581 #define _USART_RXDOUBLEX_FERR0_SHIFT 15 /**< Shift value for USART_FERR0 */
<> 153:fa9ff456f731 582 #define _USART_RXDOUBLEX_FERR0_MASK 0x8000UL /**< Bit mask for USART_FERR0 */
<> 153:fa9ff456f731 583 #define _USART_RXDOUBLEX_FERR0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 584 #define USART_RXDOUBLEX_FERR0_DEFAULT (_USART_RXDOUBLEX_FERR0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 585 #define _USART_RXDOUBLEX_RXDATA1_SHIFT 16 /**< Shift value for USART_RXDATA1 */
<> 153:fa9ff456f731 586 #define _USART_RXDOUBLEX_RXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATA1 */
<> 153:fa9ff456f731 587 #define _USART_RXDOUBLEX_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 588 #define USART_RXDOUBLEX_RXDATA1_DEFAULT (_USART_RXDOUBLEX_RXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 589 #define USART_RXDOUBLEX_PERR1 (0x1UL << 30) /**< Data Parity Error 1 */
<> 153:fa9ff456f731 590 #define _USART_RXDOUBLEX_PERR1_SHIFT 30 /**< Shift value for USART_PERR1 */
<> 153:fa9ff456f731 591 #define _USART_RXDOUBLEX_PERR1_MASK 0x40000000UL /**< Bit mask for USART_PERR1 */
<> 153:fa9ff456f731 592 #define _USART_RXDOUBLEX_PERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 593 #define USART_RXDOUBLEX_PERR1_DEFAULT (_USART_RXDOUBLEX_PERR1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 594 #define USART_RXDOUBLEX_FERR1 (0x1UL << 31) /**< Data Framing Error 1 */
<> 153:fa9ff456f731 595 #define _USART_RXDOUBLEX_FERR1_SHIFT 31 /**< Shift value for USART_FERR1 */
<> 153:fa9ff456f731 596 #define _USART_RXDOUBLEX_FERR1_MASK 0x80000000UL /**< Bit mask for USART_FERR1 */
<> 153:fa9ff456f731 597 #define _USART_RXDOUBLEX_FERR1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 598 #define USART_RXDOUBLEX_FERR1_DEFAULT (_USART_RXDOUBLEX_FERR1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEX */
<> 153:fa9ff456f731 599
<> 153:fa9ff456f731 600 /* Bit fields for USART RXDOUBLE */
<> 153:fa9ff456f731 601 #define _USART_RXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLE */
<> 153:fa9ff456f731 602 #define _USART_RXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_RXDOUBLE */
<> 153:fa9ff456f731 603 #define _USART_RXDOUBLE_RXDATA0_SHIFT 0 /**< Shift value for USART_RXDATA0 */
<> 153:fa9ff456f731 604 #define _USART_RXDOUBLE_RXDATA0_MASK 0xFFUL /**< Bit mask for USART_RXDATA0 */
<> 153:fa9ff456f731 605 #define _USART_RXDOUBLE_RXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 153:fa9ff456f731 606 #define USART_RXDOUBLE_RXDATA0_DEFAULT (_USART_RXDOUBLE_RXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 153:fa9ff456f731 607 #define _USART_RXDOUBLE_RXDATA1_SHIFT 8 /**< Shift value for USART_RXDATA1 */
<> 153:fa9ff456f731 608 #define _USART_RXDOUBLE_RXDATA1_MASK 0xFF00UL /**< Bit mask for USART_RXDATA1 */
<> 153:fa9ff456f731 609 #define _USART_RXDOUBLE_RXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLE */
<> 153:fa9ff456f731 610 #define USART_RXDOUBLE_RXDATA1_DEFAULT (_USART_RXDOUBLE_RXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_RXDOUBLE */
<> 153:fa9ff456f731 611
<> 153:fa9ff456f731 612 /* Bit fields for USART RXDATAXP */
<> 153:fa9ff456f731 613 #define _USART_RXDATAXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDATAXP */
<> 153:fa9ff456f731 614 #define _USART_RXDATAXP_MASK 0x0000C1FFUL /**< Mask for USART_RXDATAXP */
<> 153:fa9ff456f731 615 #define _USART_RXDATAXP_RXDATAP_SHIFT 0 /**< Shift value for USART_RXDATAP */
<> 153:fa9ff456f731 616 #define _USART_RXDATAXP_RXDATAP_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP */
<> 153:fa9ff456f731 617 #define _USART_RXDATAXP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 618 #define USART_RXDATAXP_RXDATAP_DEFAULT (_USART_RXDATAXP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 619 #define USART_RXDATAXP_PERRP (0x1UL << 14) /**< Data Parity Error Peek */
<> 153:fa9ff456f731 620 #define _USART_RXDATAXP_PERRP_SHIFT 14 /**< Shift value for USART_PERRP */
<> 153:fa9ff456f731 621 #define _USART_RXDATAXP_PERRP_MASK 0x4000UL /**< Bit mask for USART_PERRP */
<> 153:fa9ff456f731 622 #define _USART_RXDATAXP_PERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 623 #define USART_RXDATAXP_PERRP_DEFAULT (_USART_RXDATAXP_PERRP_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 624 #define USART_RXDATAXP_FERRP (0x1UL << 15) /**< Data Framing Error Peek */
<> 153:fa9ff456f731 625 #define _USART_RXDATAXP_FERRP_SHIFT 15 /**< Shift value for USART_FERRP */
<> 153:fa9ff456f731 626 #define _USART_RXDATAXP_FERRP_MASK 0x8000UL /**< Bit mask for USART_FERRP */
<> 153:fa9ff456f731 627 #define _USART_RXDATAXP_FERRP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 628 #define USART_RXDATAXP_FERRP_DEFAULT (_USART_RXDATAXP_FERRP_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDATAXP */
<> 153:fa9ff456f731 629
<> 153:fa9ff456f731 630 /* Bit fields for USART RXDOUBLEXP */
<> 153:fa9ff456f731 631 #define _USART_RXDOUBLEXP_RESETVALUE 0x00000000UL /**< Default value for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 632 #define _USART_RXDOUBLEXP_MASK 0xC1FFC1FFUL /**< Mask for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 633 #define _USART_RXDOUBLEXP_RXDATAP0_SHIFT 0 /**< Shift value for USART_RXDATAP0 */
<> 153:fa9ff456f731 634 #define _USART_RXDOUBLEXP_RXDATAP0_MASK 0x1FFUL /**< Bit mask for USART_RXDATAP0 */
<> 153:fa9ff456f731 635 #define _USART_RXDOUBLEXP_RXDATAP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 636 #define USART_RXDOUBLEXP_RXDATAP0_DEFAULT (_USART_RXDOUBLEXP_RXDATAP0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 637 #define USART_RXDOUBLEXP_PERRP0 (0x1UL << 14) /**< Data Parity Error 0 Peek */
<> 153:fa9ff456f731 638 #define _USART_RXDOUBLEXP_PERRP0_SHIFT 14 /**< Shift value for USART_PERRP0 */
<> 153:fa9ff456f731 639 #define _USART_RXDOUBLEXP_PERRP0_MASK 0x4000UL /**< Bit mask for USART_PERRP0 */
<> 153:fa9ff456f731 640 #define _USART_RXDOUBLEXP_PERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 641 #define USART_RXDOUBLEXP_PERRP0_DEFAULT (_USART_RXDOUBLEXP_PERRP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 642 #define USART_RXDOUBLEXP_FERRP0 (0x1UL << 15) /**< Data Framing Error 0 Peek */
<> 153:fa9ff456f731 643 #define _USART_RXDOUBLEXP_FERRP0_SHIFT 15 /**< Shift value for USART_FERRP0 */
<> 153:fa9ff456f731 644 #define _USART_RXDOUBLEXP_FERRP0_MASK 0x8000UL /**< Bit mask for USART_FERRP0 */
<> 153:fa9ff456f731 645 #define _USART_RXDOUBLEXP_FERRP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 646 #define USART_RXDOUBLEXP_FERRP0_DEFAULT (_USART_RXDOUBLEXP_FERRP0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 647 #define _USART_RXDOUBLEXP_RXDATAP1_SHIFT 16 /**< Shift value for USART_RXDATAP1 */
<> 153:fa9ff456f731 648 #define _USART_RXDOUBLEXP_RXDATAP1_MASK 0x1FF0000UL /**< Bit mask for USART_RXDATAP1 */
<> 153:fa9ff456f731 649 #define _USART_RXDOUBLEXP_RXDATAP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 650 #define USART_RXDOUBLEXP_RXDATAP1_DEFAULT (_USART_RXDOUBLEXP_RXDATAP1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 651 #define USART_RXDOUBLEXP_PERRP1 (0x1UL << 30) /**< Data Parity Error 1 Peek */
<> 153:fa9ff456f731 652 #define _USART_RXDOUBLEXP_PERRP1_SHIFT 30 /**< Shift value for USART_PERRP1 */
<> 153:fa9ff456f731 653 #define _USART_RXDOUBLEXP_PERRP1_MASK 0x40000000UL /**< Bit mask for USART_PERRP1 */
<> 153:fa9ff456f731 654 #define _USART_RXDOUBLEXP_PERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 655 #define USART_RXDOUBLEXP_PERRP1_DEFAULT (_USART_RXDOUBLEXP_PERRP1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 656 #define USART_RXDOUBLEXP_FERRP1 (0x1UL << 31) /**< Data Framing Error 1 Peek */
<> 153:fa9ff456f731 657 #define _USART_RXDOUBLEXP_FERRP1_SHIFT 31 /**< Shift value for USART_FERRP1 */
<> 153:fa9ff456f731 658 #define _USART_RXDOUBLEXP_FERRP1_MASK 0x80000000UL /**< Bit mask for USART_FERRP1 */
<> 153:fa9ff456f731 659 #define _USART_RXDOUBLEXP_FERRP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 660 #define USART_RXDOUBLEXP_FERRP1_DEFAULT (_USART_RXDOUBLEXP_FERRP1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_RXDOUBLEXP */
<> 153:fa9ff456f731 661
<> 153:fa9ff456f731 662 /* Bit fields for USART TXDATAX */
<> 153:fa9ff456f731 663 #define _USART_TXDATAX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATAX */
<> 153:fa9ff456f731 664 #define _USART_TXDATAX_MASK 0x0000F9FFUL /**< Mask for USART_TXDATAX */
<> 153:fa9ff456f731 665 #define _USART_TXDATAX_TXDATAX_SHIFT 0 /**< Shift value for USART_TXDATAX */
<> 153:fa9ff456f731 666 #define _USART_TXDATAX_TXDATAX_MASK 0x1FFUL /**< Bit mask for USART_TXDATAX */
<> 153:fa9ff456f731 667 #define _USART_TXDATAX_TXDATAX_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 668 #define USART_TXDATAX_TXDATAX_DEFAULT (_USART_TXDATAX_TXDATAX_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 669 #define USART_TXDATAX_UBRXAT (0x1UL << 11) /**< Unblock RX After Transmission */
<> 153:fa9ff456f731 670 #define _USART_TXDATAX_UBRXAT_SHIFT 11 /**< Shift value for USART_UBRXAT */
<> 153:fa9ff456f731 671 #define _USART_TXDATAX_UBRXAT_MASK 0x800UL /**< Bit mask for USART_UBRXAT */
<> 153:fa9ff456f731 672 #define _USART_TXDATAX_UBRXAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 673 #define USART_TXDATAX_UBRXAT_DEFAULT (_USART_TXDATAX_UBRXAT_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 674 #define USART_TXDATAX_TXTRIAT (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 153:fa9ff456f731 675 #define _USART_TXDATAX_TXTRIAT_SHIFT 12 /**< Shift value for USART_TXTRIAT */
<> 153:fa9ff456f731 676 #define _USART_TXDATAX_TXTRIAT_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT */
<> 153:fa9ff456f731 677 #define _USART_TXDATAX_TXTRIAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 678 #define USART_TXDATAX_TXTRIAT_DEFAULT (_USART_TXDATAX_TXTRIAT_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 679 #define USART_TXDATAX_TXBREAK (0x1UL << 13) /**< Transmit Data As Break */
<> 153:fa9ff456f731 680 #define _USART_TXDATAX_TXBREAK_SHIFT 13 /**< Shift value for USART_TXBREAK */
<> 153:fa9ff456f731 681 #define _USART_TXDATAX_TXBREAK_MASK 0x2000UL /**< Bit mask for USART_TXBREAK */
<> 153:fa9ff456f731 682 #define _USART_TXDATAX_TXBREAK_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 683 #define USART_TXDATAX_TXBREAK_DEFAULT (_USART_TXDATAX_TXBREAK_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 684 #define USART_TXDATAX_TXDISAT (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 153:fa9ff456f731 685 #define _USART_TXDATAX_TXDISAT_SHIFT 14 /**< Shift value for USART_TXDISAT */
<> 153:fa9ff456f731 686 #define _USART_TXDATAX_TXDISAT_MASK 0x4000UL /**< Bit mask for USART_TXDISAT */
<> 153:fa9ff456f731 687 #define _USART_TXDATAX_TXDISAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 688 #define USART_TXDATAX_TXDISAT_DEFAULT (_USART_TXDATAX_TXDISAT_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 689 #define USART_TXDATAX_RXENAT (0x1UL << 15) /**< Enable RX After Transmission */
<> 153:fa9ff456f731 690 #define _USART_TXDATAX_RXENAT_SHIFT 15 /**< Shift value for USART_RXENAT */
<> 153:fa9ff456f731 691 #define _USART_TXDATAX_RXENAT_MASK 0x8000UL /**< Bit mask for USART_RXENAT */
<> 153:fa9ff456f731 692 #define _USART_TXDATAX_RXENAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 693 #define USART_TXDATAX_RXENAT_DEFAULT (_USART_TXDATAX_RXENAT_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDATAX */
<> 153:fa9ff456f731 694
<> 153:fa9ff456f731 695 /* Bit fields for USART TXDATA */
<> 153:fa9ff456f731 696 #define _USART_TXDATA_RESETVALUE 0x00000000UL /**< Default value for USART_TXDATA */
<> 153:fa9ff456f731 697 #define _USART_TXDATA_MASK 0x000000FFUL /**< Mask for USART_TXDATA */
<> 153:fa9ff456f731 698 #define _USART_TXDATA_TXDATA_SHIFT 0 /**< Shift value for USART_TXDATA */
<> 153:fa9ff456f731 699 #define _USART_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for USART_TXDATA */
<> 153:fa9ff456f731 700 #define _USART_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDATA */
<> 153:fa9ff456f731 701 #define USART_TXDATA_TXDATA_DEFAULT (_USART_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDATA */
<> 153:fa9ff456f731 702
<> 153:fa9ff456f731 703 /* Bit fields for USART TXDOUBLEX */
<> 153:fa9ff456f731 704 #define _USART_TXDOUBLEX_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLEX */
<> 153:fa9ff456f731 705 #define _USART_TXDOUBLEX_MASK 0xF9FFF9FFUL /**< Mask for USART_TXDOUBLEX */
<> 153:fa9ff456f731 706 #define _USART_TXDOUBLEX_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 153:fa9ff456f731 707 #define _USART_TXDOUBLEX_TXDATA0_MASK 0x1FFUL /**< Bit mask for USART_TXDATA0 */
<> 153:fa9ff456f731 708 #define _USART_TXDOUBLEX_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 709 #define USART_TXDOUBLEX_TXDATA0_DEFAULT (_USART_TXDOUBLEX_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 710 #define USART_TXDOUBLEX_UBRXAT0 (0x1UL << 11) /**< Unblock RX After Transmission */
<> 153:fa9ff456f731 711 #define _USART_TXDOUBLEX_UBRXAT0_SHIFT 11 /**< Shift value for USART_UBRXAT0 */
<> 153:fa9ff456f731 712 #define _USART_TXDOUBLEX_UBRXAT0_MASK 0x800UL /**< Bit mask for USART_UBRXAT0 */
<> 153:fa9ff456f731 713 #define _USART_TXDOUBLEX_UBRXAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 714 #define USART_TXDOUBLEX_UBRXAT0_DEFAULT (_USART_TXDOUBLEX_UBRXAT0_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 715 #define USART_TXDOUBLEX_TXTRIAT0 (0x1UL << 12) /**< Set TXTRI After Transmission */
<> 153:fa9ff456f731 716 #define _USART_TXDOUBLEX_TXTRIAT0_SHIFT 12 /**< Shift value for USART_TXTRIAT0 */
<> 153:fa9ff456f731 717 #define _USART_TXDOUBLEX_TXTRIAT0_MASK 0x1000UL /**< Bit mask for USART_TXTRIAT0 */
<> 153:fa9ff456f731 718 #define _USART_TXDOUBLEX_TXTRIAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 719 #define USART_TXDOUBLEX_TXTRIAT0_DEFAULT (_USART_TXDOUBLEX_TXTRIAT0_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 720 #define USART_TXDOUBLEX_TXBREAK0 (0x1UL << 13) /**< Transmit Data As Break */
<> 153:fa9ff456f731 721 #define _USART_TXDOUBLEX_TXBREAK0_SHIFT 13 /**< Shift value for USART_TXBREAK0 */
<> 153:fa9ff456f731 722 #define _USART_TXDOUBLEX_TXBREAK0_MASK 0x2000UL /**< Bit mask for USART_TXBREAK0 */
<> 153:fa9ff456f731 723 #define _USART_TXDOUBLEX_TXBREAK0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 724 #define USART_TXDOUBLEX_TXBREAK0_DEFAULT (_USART_TXDOUBLEX_TXBREAK0_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 725 #define USART_TXDOUBLEX_TXDISAT0 (0x1UL << 14) /**< Clear TXEN After Transmission */
<> 153:fa9ff456f731 726 #define _USART_TXDOUBLEX_TXDISAT0_SHIFT 14 /**< Shift value for USART_TXDISAT0 */
<> 153:fa9ff456f731 727 #define _USART_TXDOUBLEX_TXDISAT0_MASK 0x4000UL /**< Bit mask for USART_TXDISAT0 */
<> 153:fa9ff456f731 728 #define _USART_TXDOUBLEX_TXDISAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 729 #define USART_TXDOUBLEX_TXDISAT0_DEFAULT (_USART_TXDOUBLEX_TXDISAT0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 730 #define USART_TXDOUBLEX_RXENAT0 (0x1UL << 15) /**< Enable RX After Transmission */
<> 153:fa9ff456f731 731 #define _USART_TXDOUBLEX_RXENAT0_SHIFT 15 /**< Shift value for USART_RXENAT0 */
<> 153:fa9ff456f731 732 #define _USART_TXDOUBLEX_RXENAT0_MASK 0x8000UL /**< Bit mask for USART_RXENAT0 */
<> 153:fa9ff456f731 733 #define _USART_TXDOUBLEX_RXENAT0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 734 #define USART_TXDOUBLEX_RXENAT0_DEFAULT (_USART_TXDOUBLEX_RXENAT0_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 735 #define _USART_TXDOUBLEX_TXDATA1_SHIFT 16 /**< Shift value for USART_TXDATA1 */
<> 153:fa9ff456f731 736 #define _USART_TXDOUBLEX_TXDATA1_MASK 0x1FF0000UL /**< Bit mask for USART_TXDATA1 */
<> 153:fa9ff456f731 737 #define _USART_TXDOUBLEX_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 738 #define USART_TXDOUBLEX_TXDATA1_DEFAULT (_USART_TXDOUBLEX_TXDATA1_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 739 #define USART_TXDOUBLEX_UBRXAT1 (0x1UL << 27) /**< Unblock RX After Transmission */
<> 153:fa9ff456f731 740 #define _USART_TXDOUBLEX_UBRXAT1_SHIFT 27 /**< Shift value for USART_UBRXAT1 */
<> 153:fa9ff456f731 741 #define _USART_TXDOUBLEX_UBRXAT1_MASK 0x8000000UL /**< Bit mask for USART_UBRXAT1 */
<> 153:fa9ff456f731 742 #define _USART_TXDOUBLEX_UBRXAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 743 #define USART_TXDOUBLEX_UBRXAT1_DEFAULT (_USART_TXDOUBLEX_UBRXAT1_DEFAULT << 27) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 744 #define USART_TXDOUBLEX_TXTRIAT1 (0x1UL << 28) /**< Set TXTRI After Transmission */
<> 153:fa9ff456f731 745 #define _USART_TXDOUBLEX_TXTRIAT1_SHIFT 28 /**< Shift value for USART_TXTRIAT1 */
<> 153:fa9ff456f731 746 #define _USART_TXDOUBLEX_TXTRIAT1_MASK 0x10000000UL /**< Bit mask for USART_TXTRIAT1 */
<> 153:fa9ff456f731 747 #define _USART_TXDOUBLEX_TXTRIAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 748 #define USART_TXDOUBLEX_TXTRIAT1_DEFAULT (_USART_TXDOUBLEX_TXTRIAT1_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 749 #define USART_TXDOUBLEX_TXBREAK1 (0x1UL << 29) /**< Transmit Data As Break */
<> 153:fa9ff456f731 750 #define _USART_TXDOUBLEX_TXBREAK1_SHIFT 29 /**< Shift value for USART_TXBREAK1 */
<> 153:fa9ff456f731 751 #define _USART_TXDOUBLEX_TXBREAK1_MASK 0x20000000UL /**< Bit mask for USART_TXBREAK1 */
<> 153:fa9ff456f731 752 #define _USART_TXDOUBLEX_TXBREAK1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 753 #define USART_TXDOUBLEX_TXBREAK1_DEFAULT (_USART_TXDOUBLEX_TXBREAK1_DEFAULT << 29) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 754 #define USART_TXDOUBLEX_TXDISAT1 (0x1UL << 30) /**< Clear TXEN After Transmission */
<> 153:fa9ff456f731 755 #define _USART_TXDOUBLEX_TXDISAT1_SHIFT 30 /**< Shift value for USART_TXDISAT1 */
<> 153:fa9ff456f731 756 #define _USART_TXDOUBLEX_TXDISAT1_MASK 0x40000000UL /**< Bit mask for USART_TXDISAT1 */
<> 153:fa9ff456f731 757 #define _USART_TXDOUBLEX_TXDISAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 758 #define USART_TXDOUBLEX_TXDISAT1_DEFAULT (_USART_TXDOUBLEX_TXDISAT1_DEFAULT << 30) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 759 #define USART_TXDOUBLEX_RXENAT1 (0x1UL << 31) /**< Enable RX After Transmission */
<> 153:fa9ff456f731 760 #define _USART_TXDOUBLEX_RXENAT1_SHIFT 31 /**< Shift value for USART_RXENAT1 */
<> 153:fa9ff456f731 761 #define _USART_TXDOUBLEX_RXENAT1_MASK 0x80000000UL /**< Bit mask for USART_RXENAT1 */
<> 153:fa9ff456f731 762 #define _USART_TXDOUBLEX_RXENAT1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 763 #define USART_TXDOUBLEX_RXENAT1_DEFAULT (_USART_TXDOUBLEX_RXENAT1_DEFAULT << 31) /**< Shifted mode DEFAULT for USART_TXDOUBLEX */
<> 153:fa9ff456f731 764
<> 153:fa9ff456f731 765 /* Bit fields for USART TXDOUBLE */
<> 153:fa9ff456f731 766 #define _USART_TXDOUBLE_RESETVALUE 0x00000000UL /**< Default value for USART_TXDOUBLE */
<> 153:fa9ff456f731 767 #define _USART_TXDOUBLE_MASK 0x0000FFFFUL /**< Mask for USART_TXDOUBLE */
<> 153:fa9ff456f731 768 #define _USART_TXDOUBLE_TXDATA0_SHIFT 0 /**< Shift value for USART_TXDATA0 */
<> 153:fa9ff456f731 769 #define _USART_TXDOUBLE_TXDATA0_MASK 0xFFUL /**< Bit mask for USART_TXDATA0 */
<> 153:fa9ff456f731 770 #define _USART_TXDOUBLE_TXDATA0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 153:fa9ff456f731 771 #define USART_TXDOUBLE_TXDATA0_DEFAULT (_USART_TXDOUBLE_TXDATA0_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 153:fa9ff456f731 772 #define _USART_TXDOUBLE_TXDATA1_SHIFT 8 /**< Shift value for USART_TXDATA1 */
<> 153:fa9ff456f731 773 #define _USART_TXDOUBLE_TXDATA1_MASK 0xFF00UL /**< Bit mask for USART_TXDATA1 */
<> 153:fa9ff456f731 774 #define _USART_TXDOUBLE_TXDATA1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TXDOUBLE */
<> 153:fa9ff456f731 775 #define USART_TXDOUBLE_TXDATA1_DEFAULT (_USART_TXDOUBLE_TXDATA1_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_TXDOUBLE */
<> 153:fa9ff456f731 776
<> 153:fa9ff456f731 777 /* Bit fields for USART IF */
<> 153:fa9ff456f731 778 #define _USART_IF_RESETVALUE 0x00000002UL /**< Default value for USART_IF */
<> 153:fa9ff456f731 779 #define _USART_IF_MASK 0x0001FFFFUL /**< Mask for USART_IF */
<> 153:fa9ff456f731 780 #define USART_IF_TXC (0x1UL << 0) /**< TX Complete Interrupt Flag */
<> 153:fa9ff456f731 781 #define _USART_IF_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 153:fa9ff456f731 782 #define _USART_IF_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 153:fa9ff456f731 783 #define _USART_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 784 #define USART_IF_TXC_DEFAULT (_USART_IF_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 785 #define USART_IF_TXBL (0x1UL << 1) /**< TX Buffer Level Interrupt Flag */
<> 153:fa9ff456f731 786 #define _USART_IF_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 153:fa9ff456f731 787 #define _USART_IF_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 153:fa9ff456f731 788 #define _USART_IF_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 789 #define USART_IF_TXBL_DEFAULT (_USART_IF_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 790 #define USART_IF_RXDATAV (0x1UL << 2) /**< RX Data Valid Interrupt Flag */
<> 153:fa9ff456f731 791 #define _USART_IF_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 153:fa9ff456f731 792 #define _USART_IF_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 153:fa9ff456f731 793 #define _USART_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 794 #define USART_IF_RXDATAV_DEFAULT (_USART_IF_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 795 #define USART_IF_RXFULL (0x1UL << 3) /**< RX Buffer Full Interrupt Flag */
<> 153:fa9ff456f731 796 #define _USART_IF_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 153:fa9ff456f731 797 #define _USART_IF_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 153:fa9ff456f731 798 #define _USART_IF_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 799 #define USART_IF_RXFULL_DEFAULT (_USART_IF_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 800 #define USART_IF_RXOF (0x1UL << 4) /**< RX Overflow Interrupt Flag */
<> 153:fa9ff456f731 801 #define _USART_IF_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 153:fa9ff456f731 802 #define _USART_IF_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 153:fa9ff456f731 803 #define _USART_IF_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 804 #define USART_IF_RXOF_DEFAULT (_USART_IF_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 805 #define USART_IF_RXUF (0x1UL << 5) /**< RX Underflow Interrupt Flag */
<> 153:fa9ff456f731 806 #define _USART_IF_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 153:fa9ff456f731 807 #define _USART_IF_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 153:fa9ff456f731 808 #define _USART_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 809 #define USART_IF_RXUF_DEFAULT (_USART_IF_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 810 #define USART_IF_TXOF (0x1UL << 6) /**< TX Overflow Interrupt Flag */
<> 153:fa9ff456f731 811 #define _USART_IF_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 153:fa9ff456f731 812 #define _USART_IF_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 153:fa9ff456f731 813 #define _USART_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 814 #define USART_IF_TXOF_DEFAULT (_USART_IF_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 815 #define USART_IF_TXUF (0x1UL << 7) /**< TX Underflow Interrupt Flag */
<> 153:fa9ff456f731 816 #define _USART_IF_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 153:fa9ff456f731 817 #define _USART_IF_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 153:fa9ff456f731 818 #define _USART_IF_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 819 #define USART_IF_TXUF_DEFAULT (_USART_IF_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 820 #define USART_IF_PERR (0x1UL << 8) /**< Parity Error Interrupt Flag */
<> 153:fa9ff456f731 821 #define _USART_IF_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 153:fa9ff456f731 822 #define _USART_IF_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 153:fa9ff456f731 823 #define _USART_IF_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 824 #define USART_IF_PERR_DEFAULT (_USART_IF_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 825 #define USART_IF_FERR (0x1UL << 9) /**< Framing Error Interrupt Flag */
<> 153:fa9ff456f731 826 #define _USART_IF_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 153:fa9ff456f731 827 #define _USART_IF_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 153:fa9ff456f731 828 #define _USART_IF_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 829 #define USART_IF_FERR_DEFAULT (_USART_IF_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 830 #define USART_IF_MPAF (0x1UL << 10) /**< Multi-Processor Address Frame Interrupt Flag */
<> 153:fa9ff456f731 831 #define _USART_IF_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 153:fa9ff456f731 832 #define _USART_IF_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 153:fa9ff456f731 833 #define _USART_IF_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 834 #define USART_IF_MPAF_DEFAULT (_USART_IF_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 835 #define USART_IF_SSM (0x1UL << 11) /**< Slave-Select In Master Mode Interrupt Flag */
<> 153:fa9ff456f731 836 #define _USART_IF_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 153:fa9ff456f731 837 #define _USART_IF_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 153:fa9ff456f731 838 #define _USART_IF_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 839 #define USART_IF_SSM_DEFAULT (_USART_IF_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 840 #define USART_IF_CCF (0x1UL << 12) /**< Collision Check Fail Interrupt Flag */
<> 153:fa9ff456f731 841 #define _USART_IF_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 153:fa9ff456f731 842 #define _USART_IF_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 153:fa9ff456f731 843 #define _USART_IF_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 844 #define USART_IF_CCF_DEFAULT (_USART_IF_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 845 #define USART_IF_TXIDLE (0x1UL << 13) /**< TX Idle Interrupt Flag */
<> 153:fa9ff456f731 846 #define _USART_IF_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 153:fa9ff456f731 847 #define _USART_IF_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 153:fa9ff456f731 848 #define _USART_IF_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 849 #define USART_IF_TXIDLE_DEFAULT (_USART_IF_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 850 #define USART_IF_TCMP0 (0x1UL << 14) /**< Timer comparator 0 Interrupt Flag */
<> 153:fa9ff456f731 851 #define _USART_IF_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 153:fa9ff456f731 852 #define _USART_IF_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 153:fa9ff456f731 853 #define _USART_IF_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 854 #define USART_IF_TCMP0_DEFAULT (_USART_IF_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 855 #define USART_IF_TCMP1 (0x1UL << 15) /**< Timer comparator 1 Interrupt Flag */
<> 153:fa9ff456f731 856 #define _USART_IF_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 153:fa9ff456f731 857 #define _USART_IF_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 153:fa9ff456f731 858 #define _USART_IF_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 859 #define USART_IF_TCMP1_DEFAULT (_USART_IF_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 860 #define USART_IF_TCMP2 (0x1UL << 16) /**< Timer comparator 2 Interrupt Flag */
<> 153:fa9ff456f731 861 #define _USART_IF_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 153:fa9ff456f731 862 #define _USART_IF_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 153:fa9ff456f731 863 #define _USART_IF_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 864 #define USART_IF_TCMP2_DEFAULT (_USART_IF_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IF */
<> 153:fa9ff456f731 865
<> 153:fa9ff456f731 866 /* Bit fields for USART IFS */
<> 153:fa9ff456f731 867 #define _USART_IFS_RESETVALUE 0x00000000UL /**< Default value for USART_IFS */
<> 153:fa9ff456f731 868 #define _USART_IFS_MASK 0x0001FFF9UL /**< Mask for USART_IFS */
<> 153:fa9ff456f731 869 #define USART_IFS_TXC (0x1UL << 0) /**< Set TXC Interrupt Flag */
<> 153:fa9ff456f731 870 #define _USART_IFS_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 153:fa9ff456f731 871 #define _USART_IFS_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 153:fa9ff456f731 872 #define _USART_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 873 #define USART_IFS_TXC_DEFAULT (_USART_IFS_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 874 #define USART_IFS_RXFULL (0x1UL << 3) /**< Set RXFULL Interrupt Flag */
<> 153:fa9ff456f731 875 #define _USART_IFS_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 153:fa9ff456f731 876 #define _USART_IFS_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 153:fa9ff456f731 877 #define _USART_IFS_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 878 #define USART_IFS_RXFULL_DEFAULT (_USART_IFS_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 879 #define USART_IFS_RXOF (0x1UL << 4) /**< Set RXOF Interrupt Flag */
<> 153:fa9ff456f731 880 #define _USART_IFS_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 153:fa9ff456f731 881 #define _USART_IFS_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 153:fa9ff456f731 882 #define _USART_IFS_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 883 #define USART_IFS_RXOF_DEFAULT (_USART_IFS_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 884 #define USART_IFS_RXUF (0x1UL << 5) /**< Set RXUF Interrupt Flag */
<> 153:fa9ff456f731 885 #define _USART_IFS_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 153:fa9ff456f731 886 #define _USART_IFS_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 153:fa9ff456f731 887 #define _USART_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 888 #define USART_IFS_RXUF_DEFAULT (_USART_IFS_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 889 #define USART_IFS_TXOF (0x1UL << 6) /**< Set TXOF Interrupt Flag */
<> 153:fa9ff456f731 890 #define _USART_IFS_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 153:fa9ff456f731 891 #define _USART_IFS_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 153:fa9ff456f731 892 #define _USART_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 893 #define USART_IFS_TXOF_DEFAULT (_USART_IFS_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 894 #define USART_IFS_TXUF (0x1UL << 7) /**< Set TXUF Interrupt Flag */
<> 153:fa9ff456f731 895 #define _USART_IFS_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 153:fa9ff456f731 896 #define _USART_IFS_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 153:fa9ff456f731 897 #define _USART_IFS_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 898 #define USART_IFS_TXUF_DEFAULT (_USART_IFS_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 899 #define USART_IFS_PERR (0x1UL << 8) /**< Set PERR Interrupt Flag */
<> 153:fa9ff456f731 900 #define _USART_IFS_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 153:fa9ff456f731 901 #define _USART_IFS_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 153:fa9ff456f731 902 #define _USART_IFS_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 903 #define USART_IFS_PERR_DEFAULT (_USART_IFS_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 904 #define USART_IFS_FERR (0x1UL << 9) /**< Set FERR Interrupt Flag */
<> 153:fa9ff456f731 905 #define _USART_IFS_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 153:fa9ff456f731 906 #define _USART_IFS_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 153:fa9ff456f731 907 #define _USART_IFS_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 908 #define USART_IFS_FERR_DEFAULT (_USART_IFS_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 909 #define USART_IFS_MPAF (0x1UL << 10) /**< Set MPAF Interrupt Flag */
<> 153:fa9ff456f731 910 #define _USART_IFS_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 153:fa9ff456f731 911 #define _USART_IFS_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 153:fa9ff456f731 912 #define _USART_IFS_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 913 #define USART_IFS_MPAF_DEFAULT (_USART_IFS_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 914 #define USART_IFS_SSM (0x1UL << 11) /**< Set SSM Interrupt Flag */
<> 153:fa9ff456f731 915 #define _USART_IFS_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 153:fa9ff456f731 916 #define _USART_IFS_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 153:fa9ff456f731 917 #define _USART_IFS_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 918 #define USART_IFS_SSM_DEFAULT (_USART_IFS_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 919 #define USART_IFS_CCF (0x1UL << 12) /**< Set CCF Interrupt Flag */
<> 153:fa9ff456f731 920 #define _USART_IFS_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 153:fa9ff456f731 921 #define _USART_IFS_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 153:fa9ff456f731 922 #define _USART_IFS_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 923 #define USART_IFS_CCF_DEFAULT (_USART_IFS_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 924 #define USART_IFS_TXIDLE (0x1UL << 13) /**< Set TXIDLE Interrupt Flag */
<> 153:fa9ff456f731 925 #define _USART_IFS_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 153:fa9ff456f731 926 #define _USART_IFS_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 153:fa9ff456f731 927 #define _USART_IFS_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 928 #define USART_IFS_TXIDLE_DEFAULT (_USART_IFS_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 929 #define USART_IFS_TCMP0 (0x1UL << 14) /**< Set TCMP0 Interrupt Flag */
<> 153:fa9ff456f731 930 #define _USART_IFS_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 153:fa9ff456f731 931 #define _USART_IFS_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 153:fa9ff456f731 932 #define _USART_IFS_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 933 #define USART_IFS_TCMP0_DEFAULT (_USART_IFS_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 934 #define USART_IFS_TCMP1 (0x1UL << 15) /**< Set TCMP1 Interrupt Flag */
<> 153:fa9ff456f731 935 #define _USART_IFS_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 153:fa9ff456f731 936 #define _USART_IFS_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 153:fa9ff456f731 937 #define _USART_IFS_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 938 #define USART_IFS_TCMP1_DEFAULT (_USART_IFS_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 939 #define USART_IFS_TCMP2 (0x1UL << 16) /**< Set TCMP2 Interrupt Flag */
<> 153:fa9ff456f731 940 #define _USART_IFS_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 153:fa9ff456f731 941 #define _USART_IFS_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 153:fa9ff456f731 942 #define _USART_IFS_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 943 #define USART_IFS_TCMP2_DEFAULT (_USART_IFS_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFS */
<> 153:fa9ff456f731 944
<> 153:fa9ff456f731 945 /* Bit fields for USART IFC */
<> 153:fa9ff456f731 946 #define _USART_IFC_RESETVALUE 0x00000000UL /**< Default value for USART_IFC */
<> 153:fa9ff456f731 947 #define _USART_IFC_MASK 0x0001FFF9UL /**< Mask for USART_IFC */
<> 153:fa9ff456f731 948 #define USART_IFC_TXC (0x1UL << 0) /**< Clear TXC Interrupt Flag */
<> 153:fa9ff456f731 949 #define _USART_IFC_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 153:fa9ff456f731 950 #define _USART_IFC_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 153:fa9ff456f731 951 #define _USART_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 952 #define USART_IFC_TXC_DEFAULT (_USART_IFC_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 953 #define USART_IFC_RXFULL (0x1UL << 3) /**< Clear RXFULL Interrupt Flag */
<> 153:fa9ff456f731 954 #define _USART_IFC_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 153:fa9ff456f731 955 #define _USART_IFC_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 153:fa9ff456f731 956 #define _USART_IFC_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 957 #define USART_IFC_RXFULL_DEFAULT (_USART_IFC_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 958 #define USART_IFC_RXOF (0x1UL << 4) /**< Clear RXOF Interrupt Flag */
<> 153:fa9ff456f731 959 #define _USART_IFC_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 153:fa9ff456f731 960 #define _USART_IFC_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 153:fa9ff456f731 961 #define _USART_IFC_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 962 #define USART_IFC_RXOF_DEFAULT (_USART_IFC_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 963 #define USART_IFC_RXUF (0x1UL << 5) /**< Clear RXUF Interrupt Flag */
<> 153:fa9ff456f731 964 #define _USART_IFC_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 153:fa9ff456f731 965 #define _USART_IFC_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 153:fa9ff456f731 966 #define _USART_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 967 #define USART_IFC_RXUF_DEFAULT (_USART_IFC_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 968 #define USART_IFC_TXOF (0x1UL << 6) /**< Clear TXOF Interrupt Flag */
<> 153:fa9ff456f731 969 #define _USART_IFC_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 153:fa9ff456f731 970 #define _USART_IFC_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 153:fa9ff456f731 971 #define _USART_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 972 #define USART_IFC_TXOF_DEFAULT (_USART_IFC_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 973 #define USART_IFC_TXUF (0x1UL << 7) /**< Clear TXUF Interrupt Flag */
<> 153:fa9ff456f731 974 #define _USART_IFC_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 153:fa9ff456f731 975 #define _USART_IFC_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 153:fa9ff456f731 976 #define _USART_IFC_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 977 #define USART_IFC_TXUF_DEFAULT (_USART_IFC_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 978 #define USART_IFC_PERR (0x1UL << 8) /**< Clear PERR Interrupt Flag */
<> 153:fa9ff456f731 979 #define _USART_IFC_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 153:fa9ff456f731 980 #define _USART_IFC_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 153:fa9ff456f731 981 #define _USART_IFC_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 982 #define USART_IFC_PERR_DEFAULT (_USART_IFC_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 983 #define USART_IFC_FERR (0x1UL << 9) /**< Clear FERR Interrupt Flag */
<> 153:fa9ff456f731 984 #define _USART_IFC_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 153:fa9ff456f731 985 #define _USART_IFC_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 153:fa9ff456f731 986 #define _USART_IFC_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 987 #define USART_IFC_FERR_DEFAULT (_USART_IFC_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 988 #define USART_IFC_MPAF (0x1UL << 10) /**< Clear MPAF Interrupt Flag */
<> 153:fa9ff456f731 989 #define _USART_IFC_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 153:fa9ff456f731 990 #define _USART_IFC_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 153:fa9ff456f731 991 #define _USART_IFC_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 992 #define USART_IFC_MPAF_DEFAULT (_USART_IFC_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 993 #define USART_IFC_SSM (0x1UL << 11) /**< Clear SSM Interrupt Flag */
<> 153:fa9ff456f731 994 #define _USART_IFC_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 153:fa9ff456f731 995 #define _USART_IFC_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 153:fa9ff456f731 996 #define _USART_IFC_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 997 #define USART_IFC_SSM_DEFAULT (_USART_IFC_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 998 #define USART_IFC_CCF (0x1UL << 12) /**< Clear CCF Interrupt Flag */
<> 153:fa9ff456f731 999 #define _USART_IFC_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 153:fa9ff456f731 1000 #define _USART_IFC_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 153:fa9ff456f731 1001 #define _USART_IFC_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1002 #define USART_IFC_CCF_DEFAULT (_USART_IFC_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1003 #define USART_IFC_TXIDLE (0x1UL << 13) /**< Clear TXIDLE Interrupt Flag */
<> 153:fa9ff456f731 1004 #define _USART_IFC_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 153:fa9ff456f731 1005 #define _USART_IFC_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 153:fa9ff456f731 1006 #define _USART_IFC_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1007 #define USART_IFC_TXIDLE_DEFAULT (_USART_IFC_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1008 #define USART_IFC_TCMP0 (0x1UL << 14) /**< Clear TCMP0 Interrupt Flag */
<> 153:fa9ff456f731 1009 #define _USART_IFC_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 153:fa9ff456f731 1010 #define _USART_IFC_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 153:fa9ff456f731 1011 #define _USART_IFC_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1012 #define USART_IFC_TCMP0_DEFAULT (_USART_IFC_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1013 #define USART_IFC_TCMP1 (0x1UL << 15) /**< Clear TCMP1 Interrupt Flag */
<> 153:fa9ff456f731 1014 #define _USART_IFC_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 153:fa9ff456f731 1015 #define _USART_IFC_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 153:fa9ff456f731 1016 #define _USART_IFC_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1017 #define USART_IFC_TCMP1_DEFAULT (_USART_IFC_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1018 #define USART_IFC_TCMP2 (0x1UL << 16) /**< Clear TCMP2 Interrupt Flag */
<> 153:fa9ff456f731 1019 #define _USART_IFC_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 153:fa9ff456f731 1020 #define _USART_IFC_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 153:fa9ff456f731 1021 #define _USART_IFC_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1022 #define USART_IFC_TCMP2_DEFAULT (_USART_IFC_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IFC */
<> 153:fa9ff456f731 1023
<> 153:fa9ff456f731 1024 /* Bit fields for USART IEN */
<> 153:fa9ff456f731 1025 #define _USART_IEN_RESETVALUE 0x00000000UL /**< Default value for USART_IEN */
<> 153:fa9ff456f731 1026 #define _USART_IEN_MASK 0x0001FFFFUL /**< Mask for USART_IEN */
<> 153:fa9ff456f731 1027 #define USART_IEN_TXC (0x1UL << 0) /**< TXC Interrupt Enable */
<> 153:fa9ff456f731 1028 #define _USART_IEN_TXC_SHIFT 0 /**< Shift value for USART_TXC */
<> 153:fa9ff456f731 1029 #define _USART_IEN_TXC_MASK 0x1UL /**< Bit mask for USART_TXC */
<> 153:fa9ff456f731 1030 #define _USART_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1031 #define USART_IEN_TXC_DEFAULT (_USART_IEN_TXC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1032 #define USART_IEN_TXBL (0x1UL << 1) /**< TXBL Interrupt Enable */
<> 153:fa9ff456f731 1033 #define _USART_IEN_TXBL_SHIFT 1 /**< Shift value for USART_TXBL */
<> 153:fa9ff456f731 1034 #define _USART_IEN_TXBL_MASK 0x2UL /**< Bit mask for USART_TXBL */
<> 153:fa9ff456f731 1035 #define _USART_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1036 #define USART_IEN_TXBL_DEFAULT (_USART_IEN_TXBL_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1037 #define USART_IEN_RXDATAV (0x1UL << 2) /**< RXDATAV Interrupt Enable */
<> 153:fa9ff456f731 1038 #define _USART_IEN_RXDATAV_SHIFT 2 /**< Shift value for USART_RXDATAV */
<> 153:fa9ff456f731 1039 #define _USART_IEN_RXDATAV_MASK 0x4UL /**< Bit mask for USART_RXDATAV */
<> 153:fa9ff456f731 1040 #define _USART_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1041 #define USART_IEN_RXDATAV_DEFAULT (_USART_IEN_RXDATAV_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1042 #define USART_IEN_RXFULL (0x1UL << 3) /**< RXFULL Interrupt Enable */
<> 153:fa9ff456f731 1043 #define _USART_IEN_RXFULL_SHIFT 3 /**< Shift value for USART_RXFULL */
<> 153:fa9ff456f731 1044 #define _USART_IEN_RXFULL_MASK 0x8UL /**< Bit mask for USART_RXFULL */
<> 153:fa9ff456f731 1045 #define _USART_IEN_RXFULL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1046 #define USART_IEN_RXFULL_DEFAULT (_USART_IEN_RXFULL_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1047 #define USART_IEN_RXOF (0x1UL << 4) /**< RXOF Interrupt Enable */
<> 153:fa9ff456f731 1048 #define _USART_IEN_RXOF_SHIFT 4 /**< Shift value for USART_RXOF */
<> 153:fa9ff456f731 1049 #define _USART_IEN_RXOF_MASK 0x10UL /**< Bit mask for USART_RXOF */
<> 153:fa9ff456f731 1050 #define _USART_IEN_RXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1051 #define USART_IEN_RXOF_DEFAULT (_USART_IEN_RXOF_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1052 #define USART_IEN_RXUF (0x1UL << 5) /**< RXUF Interrupt Enable */
<> 153:fa9ff456f731 1053 #define _USART_IEN_RXUF_SHIFT 5 /**< Shift value for USART_RXUF */
<> 153:fa9ff456f731 1054 #define _USART_IEN_RXUF_MASK 0x20UL /**< Bit mask for USART_RXUF */
<> 153:fa9ff456f731 1055 #define _USART_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1056 #define USART_IEN_RXUF_DEFAULT (_USART_IEN_RXUF_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1057 #define USART_IEN_TXOF (0x1UL << 6) /**< TXOF Interrupt Enable */
<> 153:fa9ff456f731 1058 #define _USART_IEN_TXOF_SHIFT 6 /**< Shift value for USART_TXOF */
<> 153:fa9ff456f731 1059 #define _USART_IEN_TXOF_MASK 0x40UL /**< Bit mask for USART_TXOF */
<> 153:fa9ff456f731 1060 #define _USART_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1061 #define USART_IEN_TXOF_DEFAULT (_USART_IEN_TXOF_DEFAULT << 6) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1062 #define USART_IEN_TXUF (0x1UL << 7) /**< TXUF Interrupt Enable */
<> 153:fa9ff456f731 1063 #define _USART_IEN_TXUF_SHIFT 7 /**< Shift value for USART_TXUF */
<> 153:fa9ff456f731 1064 #define _USART_IEN_TXUF_MASK 0x80UL /**< Bit mask for USART_TXUF */
<> 153:fa9ff456f731 1065 #define _USART_IEN_TXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1066 #define USART_IEN_TXUF_DEFAULT (_USART_IEN_TXUF_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1067 #define USART_IEN_PERR (0x1UL << 8) /**< PERR Interrupt Enable */
<> 153:fa9ff456f731 1068 #define _USART_IEN_PERR_SHIFT 8 /**< Shift value for USART_PERR */
<> 153:fa9ff456f731 1069 #define _USART_IEN_PERR_MASK 0x100UL /**< Bit mask for USART_PERR */
<> 153:fa9ff456f731 1070 #define _USART_IEN_PERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1071 #define USART_IEN_PERR_DEFAULT (_USART_IEN_PERR_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1072 #define USART_IEN_FERR (0x1UL << 9) /**< FERR Interrupt Enable */
<> 153:fa9ff456f731 1073 #define _USART_IEN_FERR_SHIFT 9 /**< Shift value for USART_FERR */
<> 153:fa9ff456f731 1074 #define _USART_IEN_FERR_MASK 0x200UL /**< Bit mask for USART_FERR */
<> 153:fa9ff456f731 1075 #define _USART_IEN_FERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1076 #define USART_IEN_FERR_DEFAULT (_USART_IEN_FERR_DEFAULT << 9) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1077 #define USART_IEN_MPAF (0x1UL << 10) /**< MPAF Interrupt Enable */
<> 153:fa9ff456f731 1078 #define _USART_IEN_MPAF_SHIFT 10 /**< Shift value for USART_MPAF */
<> 153:fa9ff456f731 1079 #define _USART_IEN_MPAF_MASK 0x400UL /**< Bit mask for USART_MPAF */
<> 153:fa9ff456f731 1080 #define _USART_IEN_MPAF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1081 #define USART_IEN_MPAF_DEFAULT (_USART_IEN_MPAF_DEFAULT << 10) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1082 #define USART_IEN_SSM (0x1UL << 11) /**< SSM Interrupt Enable */
<> 153:fa9ff456f731 1083 #define _USART_IEN_SSM_SHIFT 11 /**< Shift value for USART_SSM */
<> 153:fa9ff456f731 1084 #define _USART_IEN_SSM_MASK 0x800UL /**< Bit mask for USART_SSM */
<> 153:fa9ff456f731 1085 #define _USART_IEN_SSM_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1086 #define USART_IEN_SSM_DEFAULT (_USART_IEN_SSM_DEFAULT << 11) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1087 #define USART_IEN_CCF (0x1UL << 12) /**< CCF Interrupt Enable */
<> 153:fa9ff456f731 1088 #define _USART_IEN_CCF_SHIFT 12 /**< Shift value for USART_CCF */
<> 153:fa9ff456f731 1089 #define _USART_IEN_CCF_MASK 0x1000UL /**< Bit mask for USART_CCF */
<> 153:fa9ff456f731 1090 #define _USART_IEN_CCF_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1091 #define USART_IEN_CCF_DEFAULT (_USART_IEN_CCF_DEFAULT << 12) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1092 #define USART_IEN_TXIDLE (0x1UL << 13) /**< TXIDLE Interrupt Enable */
<> 153:fa9ff456f731 1093 #define _USART_IEN_TXIDLE_SHIFT 13 /**< Shift value for USART_TXIDLE */
<> 153:fa9ff456f731 1094 #define _USART_IEN_TXIDLE_MASK 0x2000UL /**< Bit mask for USART_TXIDLE */
<> 153:fa9ff456f731 1095 #define _USART_IEN_TXIDLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1096 #define USART_IEN_TXIDLE_DEFAULT (_USART_IEN_TXIDLE_DEFAULT << 13) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1097 #define USART_IEN_TCMP0 (0x1UL << 14) /**< TCMP0 Interrupt Enable */
<> 153:fa9ff456f731 1098 #define _USART_IEN_TCMP0_SHIFT 14 /**< Shift value for USART_TCMP0 */
<> 153:fa9ff456f731 1099 #define _USART_IEN_TCMP0_MASK 0x4000UL /**< Bit mask for USART_TCMP0 */
<> 153:fa9ff456f731 1100 #define _USART_IEN_TCMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1101 #define USART_IEN_TCMP0_DEFAULT (_USART_IEN_TCMP0_DEFAULT << 14) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1102 #define USART_IEN_TCMP1 (0x1UL << 15) /**< TCMP1 Interrupt Enable */
<> 153:fa9ff456f731 1103 #define _USART_IEN_TCMP1_SHIFT 15 /**< Shift value for USART_TCMP1 */
<> 153:fa9ff456f731 1104 #define _USART_IEN_TCMP1_MASK 0x8000UL /**< Bit mask for USART_TCMP1 */
<> 153:fa9ff456f731 1105 #define _USART_IEN_TCMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1106 #define USART_IEN_TCMP1_DEFAULT (_USART_IEN_TCMP1_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1107 #define USART_IEN_TCMP2 (0x1UL << 16) /**< TCMP2 Interrupt Enable */
<> 153:fa9ff456f731 1108 #define _USART_IEN_TCMP2_SHIFT 16 /**< Shift value for USART_TCMP2 */
<> 153:fa9ff456f731 1109 #define _USART_IEN_TCMP2_MASK 0x10000UL /**< Bit mask for USART_TCMP2 */
<> 153:fa9ff456f731 1110 #define _USART_IEN_TCMP2_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1111 #define USART_IEN_TCMP2_DEFAULT (_USART_IEN_TCMP2_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_IEN */
<> 153:fa9ff456f731 1112
<> 153:fa9ff456f731 1113 /* Bit fields for USART IRCTRL */
<> 153:fa9ff456f731 1114 #define _USART_IRCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_IRCTRL */
<> 153:fa9ff456f731 1115 #define _USART_IRCTRL_MASK 0x00000F8FUL /**< Mask for USART_IRCTRL */
<> 153:fa9ff456f731 1116 #define USART_IRCTRL_IREN (0x1UL << 0) /**< Enable IrDA Module */
<> 153:fa9ff456f731 1117 #define _USART_IRCTRL_IREN_SHIFT 0 /**< Shift value for USART_IREN */
<> 153:fa9ff456f731 1118 #define _USART_IRCTRL_IREN_MASK 0x1UL /**< Bit mask for USART_IREN */
<> 153:fa9ff456f731 1119 #define _USART_IRCTRL_IREN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1120 #define USART_IRCTRL_IREN_DEFAULT (_USART_IRCTRL_IREN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1121 #define _USART_IRCTRL_IRPW_SHIFT 1 /**< Shift value for USART_IRPW */
<> 153:fa9ff456f731 1122 #define _USART_IRCTRL_IRPW_MASK 0x6UL /**< Bit mask for USART_IRPW */
<> 153:fa9ff456f731 1123 #define _USART_IRCTRL_IRPW_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1124 #define _USART_IRCTRL_IRPW_ONE 0x00000000UL /**< Mode ONE for USART_IRCTRL */
<> 153:fa9ff456f731 1125 #define _USART_IRCTRL_IRPW_TWO 0x00000001UL /**< Mode TWO for USART_IRCTRL */
<> 153:fa9ff456f731 1126 #define _USART_IRCTRL_IRPW_THREE 0x00000002UL /**< Mode THREE for USART_IRCTRL */
<> 153:fa9ff456f731 1127 #define _USART_IRCTRL_IRPW_FOUR 0x00000003UL /**< Mode FOUR for USART_IRCTRL */
<> 153:fa9ff456f731 1128 #define USART_IRCTRL_IRPW_DEFAULT (_USART_IRCTRL_IRPW_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1129 #define USART_IRCTRL_IRPW_ONE (_USART_IRCTRL_IRPW_ONE << 1) /**< Shifted mode ONE for USART_IRCTRL */
<> 153:fa9ff456f731 1130 #define USART_IRCTRL_IRPW_TWO (_USART_IRCTRL_IRPW_TWO << 1) /**< Shifted mode TWO for USART_IRCTRL */
<> 153:fa9ff456f731 1131 #define USART_IRCTRL_IRPW_THREE (_USART_IRCTRL_IRPW_THREE << 1) /**< Shifted mode THREE for USART_IRCTRL */
<> 153:fa9ff456f731 1132 #define USART_IRCTRL_IRPW_FOUR (_USART_IRCTRL_IRPW_FOUR << 1) /**< Shifted mode FOUR for USART_IRCTRL */
<> 153:fa9ff456f731 1133 #define USART_IRCTRL_IRFILT (0x1UL << 3) /**< IrDA RX Filter */
<> 153:fa9ff456f731 1134 #define _USART_IRCTRL_IRFILT_SHIFT 3 /**< Shift value for USART_IRFILT */
<> 153:fa9ff456f731 1135 #define _USART_IRCTRL_IRFILT_MASK 0x8UL /**< Bit mask for USART_IRFILT */
<> 153:fa9ff456f731 1136 #define _USART_IRCTRL_IRFILT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1137 #define USART_IRCTRL_IRFILT_DEFAULT (_USART_IRCTRL_IRFILT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1138 #define USART_IRCTRL_IRPRSEN (0x1UL << 7) /**< IrDA PRS Channel Enable */
<> 153:fa9ff456f731 1139 #define _USART_IRCTRL_IRPRSEN_SHIFT 7 /**< Shift value for USART_IRPRSEN */
<> 153:fa9ff456f731 1140 #define _USART_IRCTRL_IRPRSEN_MASK 0x80UL /**< Bit mask for USART_IRPRSEN */
<> 153:fa9ff456f731 1141 #define _USART_IRCTRL_IRPRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1142 #define USART_IRCTRL_IRPRSEN_DEFAULT (_USART_IRCTRL_IRPRSEN_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1143 #define _USART_IRCTRL_IRPRSSEL_SHIFT 8 /**< Shift value for USART_IRPRSSEL */
<> 153:fa9ff456f731 1144 #define _USART_IRCTRL_IRPRSSEL_MASK 0xF00UL /**< Bit mask for USART_IRPRSSEL */
<> 153:fa9ff456f731 1145 #define _USART_IRCTRL_IRPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1146 #define _USART_IRCTRL_IRPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_IRCTRL */
<> 153:fa9ff456f731 1147 #define _USART_IRCTRL_IRPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_IRCTRL */
<> 153:fa9ff456f731 1148 #define _USART_IRCTRL_IRPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_IRCTRL */
<> 153:fa9ff456f731 1149 #define _USART_IRCTRL_IRPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_IRCTRL */
<> 153:fa9ff456f731 1150 #define _USART_IRCTRL_IRPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_IRCTRL */
<> 153:fa9ff456f731 1151 #define _USART_IRCTRL_IRPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_IRCTRL */
<> 153:fa9ff456f731 1152 #define _USART_IRCTRL_IRPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_IRCTRL */
<> 153:fa9ff456f731 1153 #define _USART_IRCTRL_IRPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_IRCTRL */
<> 153:fa9ff456f731 1154 #define _USART_IRCTRL_IRPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_IRCTRL */
<> 153:fa9ff456f731 1155 #define _USART_IRCTRL_IRPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_IRCTRL */
<> 153:fa9ff456f731 1156 #define _USART_IRCTRL_IRPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_IRCTRL */
<> 153:fa9ff456f731 1157 #define _USART_IRCTRL_IRPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_IRCTRL */
<> 153:fa9ff456f731 1158 #define USART_IRCTRL_IRPRSSEL_DEFAULT (_USART_IRCTRL_IRPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_IRCTRL */
<> 153:fa9ff456f731 1159 #define USART_IRCTRL_IRPRSSEL_PRSCH0 (_USART_IRCTRL_IRPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_IRCTRL */
<> 153:fa9ff456f731 1160 #define USART_IRCTRL_IRPRSSEL_PRSCH1 (_USART_IRCTRL_IRPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_IRCTRL */
<> 153:fa9ff456f731 1161 #define USART_IRCTRL_IRPRSSEL_PRSCH2 (_USART_IRCTRL_IRPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_IRCTRL */
<> 153:fa9ff456f731 1162 #define USART_IRCTRL_IRPRSSEL_PRSCH3 (_USART_IRCTRL_IRPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_IRCTRL */
<> 153:fa9ff456f731 1163 #define USART_IRCTRL_IRPRSSEL_PRSCH4 (_USART_IRCTRL_IRPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_IRCTRL */
<> 153:fa9ff456f731 1164 #define USART_IRCTRL_IRPRSSEL_PRSCH5 (_USART_IRCTRL_IRPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_IRCTRL */
<> 153:fa9ff456f731 1165 #define USART_IRCTRL_IRPRSSEL_PRSCH6 (_USART_IRCTRL_IRPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_IRCTRL */
<> 153:fa9ff456f731 1166 #define USART_IRCTRL_IRPRSSEL_PRSCH7 (_USART_IRCTRL_IRPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_IRCTRL */
<> 153:fa9ff456f731 1167 #define USART_IRCTRL_IRPRSSEL_PRSCH8 (_USART_IRCTRL_IRPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_IRCTRL */
<> 153:fa9ff456f731 1168 #define USART_IRCTRL_IRPRSSEL_PRSCH9 (_USART_IRCTRL_IRPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_IRCTRL */
<> 153:fa9ff456f731 1169 #define USART_IRCTRL_IRPRSSEL_PRSCH10 (_USART_IRCTRL_IRPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_IRCTRL */
<> 153:fa9ff456f731 1170 #define USART_IRCTRL_IRPRSSEL_PRSCH11 (_USART_IRCTRL_IRPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_IRCTRL */
<> 153:fa9ff456f731 1171
<> 153:fa9ff456f731 1172 /* Bit fields for USART INPUT */
<> 153:fa9ff456f731 1173 #define _USART_INPUT_RESETVALUE 0x00000000UL /**< Default value for USART_INPUT */
<> 153:fa9ff456f731 1174 #define _USART_INPUT_MASK 0x00008F8FUL /**< Mask for USART_INPUT */
<> 153:fa9ff456f731 1175 #define _USART_INPUT_RXPRSSEL_SHIFT 0 /**< Shift value for USART_RXPRSSEL */
<> 153:fa9ff456f731 1176 #define _USART_INPUT_RXPRSSEL_MASK 0xFUL /**< Bit mask for USART_RXPRSSEL */
<> 153:fa9ff456f731 1177 #define _USART_INPUT_RXPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1178 #define _USART_INPUT_RXPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
<> 153:fa9ff456f731 1179 #define _USART_INPUT_RXPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
<> 153:fa9ff456f731 1180 #define _USART_INPUT_RXPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
<> 153:fa9ff456f731 1181 #define _USART_INPUT_RXPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
<> 153:fa9ff456f731 1182 #define _USART_INPUT_RXPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
<> 153:fa9ff456f731 1183 #define _USART_INPUT_RXPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
<> 153:fa9ff456f731 1184 #define _USART_INPUT_RXPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
<> 153:fa9ff456f731 1185 #define _USART_INPUT_RXPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
<> 153:fa9ff456f731 1186 #define _USART_INPUT_RXPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
<> 153:fa9ff456f731 1187 #define _USART_INPUT_RXPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
<> 153:fa9ff456f731 1188 #define _USART_INPUT_RXPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
<> 153:fa9ff456f731 1189 #define _USART_INPUT_RXPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
<> 153:fa9ff456f731 1190 #define USART_INPUT_RXPRSSEL_DEFAULT (_USART_INPUT_RXPRSSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1191 #define USART_INPUT_RXPRSSEL_PRSCH0 (_USART_INPUT_RXPRSSEL_PRSCH0 << 0) /**< Shifted mode PRSCH0 for USART_INPUT */
<> 153:fa9ff456f731 1192 #define USART_INPUT_RXPRSSEL_PRSCH1 (_USART_INPUT_RXPRSSEL_PRSCH1 << 0) /**< Shifted mode PRSCH1 for USART_INPUT */
<> 153:fa9ff456f731 1193 #define USART_INPUT_RXPRSSEL_PRSCH2 (_USART_INPUT_RXPRSSEL_PRSCH2 << 0) /**< Shifted mode PRSCH2 for USART_INPUT */
<> 153:fa9ff456f731 1194 #define USART_INPUT_RXPRSSEL_PRSCH3 (_USART_INPUT_RXPRSSEL_PRSCH3 << 0) /**< Shifted mode PRSCH3 for USART_INPUT */
<> 153:fa9ff456f731 1195 #define USART_INPUT_RXPRSSEL_PRSCH4 (_USART_INPUT_RXPRSSEL_PRSCH4 << 0) /**< Shifted mode PRSCH4 for USART_INPUT */
<> 153:fa9ff456f731 1196 #define USART_INPUT_RXPRSSEL_PRSCH5 (_USART_INPUT_RXPRSSEL_PRSCH5 << 0) /**< Shifted mode PRSCH5 for USART_INPUT */
<> 153:fa9ff456f731 1197 #define USART_INPUT_RXPRSSEL_PRSCH6 (_USART_INPUT_RXPRSSEL_PRSCH6 << 0) /**< Shifted mode PRSCH6 for USART_INPUT */
<> 153:fa9ff456f731 1198 #define USART_INPUT_RXPRSSEL_PRSCH7 (_USART_INPUT_RXPRSSEL_PRSCH7 << 0) /**< Shifted mode PRSCH7 for USART_INPUT */
<> 153:fa9ff456f731 1199 #define USART_INPUT_RXPRSSEL_PRSCH8 (_USART_INPUT_RXPRSSEL_PRSCH8 << 0) /**< Shifted mode PRSCH8 for USART_INPUT */
<> 153:fa9ff456f731 1200 #define USART_INPUT_RXPRSSEL_PRSCH9 (_USART_INPUT_RXPRSSEL_PRSCH9 << 0) /**< Shifted mode PRSCH9 for USART_INPUT */
<> 153:fa9ff456f731 1201 #define USART_INPUT_RXPRSSEL_PRSCH10 (_USART_INPUT_RXPRSSEL_PRSCH10 << 0) /**< Shifted mode PRSCH10 for USART_INPUT */
<> 153:fa9ff456f731 1202 #define USART_INPUT_RXPRSSEL_PRSCH11 (_USART_INPUT_RXPRSSEL_PRSCH11 << 0) /**< Shifted mode PRSCH11 for USART_INPUT */
<> 153:fa9ff456f731 1203 #define USART_INPUT_RXPRS (0x1UL << 7) /**< PRS RX Enable */
<> 153:fa9ff456f731 1204 #define _USART_INPUT_RXPRS_SHIFT 7 /**< Shift value for USART_RXPRS */
<> 153:fa9ff456f731 1205 #define _USART_INPUT_RXPRS_MASK 0x80UL /**< Bit mask for USART_RXPRS */
<> 153:fa9ff456f731 1206 #define _USART_INPUT_RXPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1207 #define USART_INPUT_RXPRS_DEFAULT (_USART_INPUT_RXPRS_DEFAULT << 7) /**< Shifted mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1208 #define _USART_INPUT_CLKPRSSEL_SHIFT 8 /**< Shift value for USART_CLKPRSSEL */
<> 153:fa9ff456f731 1209 #define _USART_INPUT_CLKPRSSEL_MASK 0xF00UL /**< Bit mask for USART_CLKPRSSEL */
<> 153:fa9ff456f731 1210 #define _USART_INPUT_CLKPRSSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1211 #define _USART_INPUT_CLKPRSSEL_PRSCH0 0x00000000UL /**< Mode PRSCH0 for USART_INPUT */
<> 153:fa9ff456f731 1212 #define _USART_INPUT_CLKPRSSEL_PRSCH1 0x00000001UL /**< Mode PRSCH1 for USART_INPUT */
<> 153:fa9ff456f731 1213 #define _USART_INPUT_CLKPRSSEL_PRSCH2 0x00000002UL /**< Mode PRSCH2 for USART_INPUT */
<> 153:fa9ff456f731 1214 #define _USART_INPUT_CLKPRSSEL_PRSCH3 0x00000003UL /**< Mode PRSCH3 for USART_INPUT */
<> 153:fa9ff456f731 1215 #define _USART_INPUT_CLKPRSSEL_PRSCH4 0x00000004UL /**< Mode PRSCH4 for USART_INPUT */
<> 153:fa9ff456f731 1216 #define _USART_INPUT_CLKPRSSEL_PRSCH5 0x00000005UL /**< Mode PRSCH5 for USART_INPUT */
<> 153:fa9ff456f731 1217 #define _USART_INPUT_CLKPRSSEL_PRSCH6 0x00000006UL /**< Mode PRSCH6 for USART_INPUT */
<> 153:fa9ff456f731 1218 #define _USART_INPUT_CLKPRSSEL_PRSCH7 0x00000007UL /**< Mode PRSCH7 for USART_INPUT */
<> 153:fa9ff456f731 1219 #define _USART_INPUT_CLKPRSSEL_PRSCH8 0x00000008UL /**< Mode PRSCH8 for USART_INPUT */
<> 153:fa9ff456f731 1220 #define _USART_INPUT_CLKPRSSEL_PRSCH9 0x00000009UL /**< Mode PRSCH9 for USART_INPUT */
<> 153:fa9ff456f731 1221 #define _USART_INPUT_CLKPRSSEL_PRSCH10 0x0000000AUL /**< Mode PRSCH10 for USART_INPUT */
<> 153:fa9ff456f731 1222 #define _USART_INPUT_CLKPRSSEL_PRSCH11 0x0000000BUL /**< Mode PRSCH11 for USART_INPUT */
<> 153:fa9ff456f731 1223 #define USART_INPUT_CLKPRSSEL_DEFAULT (_USART_INPUT_CLKPRSSEL_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1224 #define USART_INPUT_CLKPRSSEL_PRSCH0 (_USART_INPUT_CLKPRSSEL_PRSCH0 << 8) /**< Shifted mode PRSCH0 for USART_INPUT */
<> 153:fa9ff456f731 1225 #define USART_INPUT_CLKPRSSEL_PRSCH1 (_USART_INPUT_CLKPRSSEL_PRSCH1 << 8) /**< Shifted mode PRSCH1 for USART_INPUT */
<> 153:fa9ff456f731 1226 #define USART_INPUT_CLKPRSSEL_PRSCH2 (_USART_INPUT_CLKPRSSEL_PRSCH2 << 8) /**< Shifted mode PRSCH2 for USART_INPUT */
<> 153:fa9ff456f731 1227 #define USART_INPUT_CLKPRSSEL_PRSCH3 (_USART_INPUT_CLKPRSSEL_PRSCH3 << 8) /**< Shifted mode PRSCH3 for USART_INPUT */
<> 153:fa9ff456f731 1228 #define USART_INPUT_CLKPRSSEL_PRSCH4 (_USART_INPUT_CLKPRSSEL_PRSCH4 << 8) /**< Shifted mode PRSCH4 for USART_INPUT */
<> 153:fa9ff456f731 1229 #define USART_INPUT_CLKPRSSEL_PRSCH5 (_USART_INPUT_CLKPRSSEL_PRSCH5 << 8) /**< Shifted mode PRSCH5 for USART_INPUT */
<> 153:fa9ff456f731 1230 #define USART_INPUT_CLKPRSSEL_PRSCH6 (_USART_INPUT_CLKPRSSEL_PRSCH6 << 8) /**< Shifted mode PRSCH6 for USART_INPUT */
<> 153:fa9ff456f731 1231 #define USART_INPUT_CLKPRSSEL_PRSCH7 (_USART_INPUT_CLKPRSSEL_PRSCH7 << 8) /**< Shifted mode PRSCH7 for USART_INPUT */
<> 153:fa9ff456f731 1232 #define USART_INPUT_CLKPRSSEL_PRSCH8 (_USART_INPUT_CLKPRSSEL_PRSCH8 << 8) /**< Shifted mode PRSCH8 for USART_INPUT */
<> 153:fa9ff456f731 1233 #define USART_INPUT_CLKPRSSEL_PRSCH9 (_USART_INPUT_CLKPRSSEL_PRSCH9 << 8) /**< Shifted mode PRSCH9 for USART_INPUT */
<> 153:fa9ff456f731 1234 #define USART_INPUT_CLKPRSSEL_PRSCH10 (_USART_INPUT_CLKPRSSEL_PRSCH10 << 8) /**< Shifted mode PRSCH10 for USART_INPUT */
<> 153:fa9ff456f731 1235 #define USART_INPUT_CLKPRSSEL_PRSCH11 (_USART_INPUT_CLKPRSSEL_PRSCH11 << 8) /**< Shifted mode PRSCH11 for USART_INPUT */
<> 153:fa9ff456f731 1236 #define USART_INPUT_CLKPRS (0x1UL << 15) /**< PRS CLK Enable */
<> 153:fa9ff456f731 1237 #define _USART_INPUT_CLKPRS_SHIFT 15 /**< Shift value for USART_CLKPRS */
<> 153:fa9ff456f731 1238 #define _USART_INPUT_CLKPRS_MASK 0x8000UL /**< Bit mask for USART_CLKPRS */
<> 153:fa9ff456f731 1239 #define _USART_INPUT_CLKPRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1240 #define USART_INPUT_CLKPRS_DEFAULT (_USART_INPUT_CLKPRS_DEFAULT << 15) /**< Shifted mode DEFAULT for USART_INPUT */
<> 153:fa9ff456f731 1241
<> 153:fa9ff456f731 1242 /* Bit fields for USART I2SCTRL */
<> 153:fa9ff456f731 1243 #define _USART_I2SCTRL_RESETVALUE 0x00000000UL /**< Default value for USART_I2SCTRL */
<> 153:fa9ff456f731 1244 #define _USART_I2SCTRL_MASK 0x0000071FUL /**< Mask for USART_I2SCTRL */
<> 153:fa9ff456f731 1245 #define USART_I2SCTRL_EN (0x1UL << 0) /**< Enable I2S Mode */
<> 153:fa9ff456f731 1246 #define _USART_I2SCTRL_EN_SHIFT 0 /**< Shift value for USART_EN */
<> 153:fa9ff456f731 1247 #define _USART_I2SCTRL_EN_MASK 0x1UL /**< Bit mask for USART_EN */
<> 153:fa9ff456f731 1248 #define _USART_I2SCTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1249 #define USART_I2SCTRL_EN_DEFAULT (_USART_I2SCTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1250 #define USART_I2SCTRL_MONO (0x1UL << 1) /**< Stero or Mono */
<> 153:fa9ff456f731 1251 #define _USART_I2SCTRL_MONO_SHIFT 1 /**< Shift value for USART_MONO */
<> 153:fa9ff456f731 1252 #define _USART_I2SCTRL_MONO_MASK 0x2UL /**< Bit mask for USART_MONO */
<> 153:fa9ff456f731 1253 #define _USART_I2SCTRL_MONO_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1254 #define USART_I2SCTRL_MONO_DEFAULT (_USART_I2SCTRL_MONO_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1255 #define USART_I2SCTRL_JUSTIFY (0x1UL << 2) /**< Justification of I2S Data */
<> 153:fa9ff456f731 1256 #define _USART_I2SCTRL_JUSTIFY_SHIFT 2 /**< Shift value for USART_JUSTIFY */
<> 153:fa9ff456f731 1257 #define _USART_I2SCTRL_JUSTIFY_MASK 0x4UL /**< Bit mask for USART_JUSTIFY */
<> 153:fa9ff456f731 1258 #define _USART_I2SCTRL_JUSTIFY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1259 #define _USART_I2SCTRL_JUSTIFY_LEFT 0x00000000UL /**< Mode LEFT for USART_I2SCTRL */
<> 153:fa9ff456f731 1260 #define _USART_I2SCTRL_JUSTIFY_RIGHT 0x00000001UL /**< Mode RIGHT for USART_I2SCTRL */
<> 153:fa9ff456f731 1261 #define USART_I2SCTRL_JUSTIFY_DEFAULT (_USART_I2SCTRL_JUSTIFY_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1262 #define USART_I2SCTRL_JUSTIFY_LEFT (_USART_I2SCTRL_JUSTIFY_LEFT << 2) /**< Shifted mode LEFT for USART_I2SCTRL */
<> 153:fa9ff456f731 1263 #define USART_I2SCTRL_JUSTIFY_RIGHT (_USART_I2SCTRL_JUSTIFY_RIGHT << 2) /**< Shifted mode RIGHT for USART_I2SCTRL */
<> 153:fa9ff456f731 1264 #define USART_I2SCTRL_DMASPLIT (0x1UL << 3) /**< Separate DMA Request For Left/Right Data */
<> 153:fa9ff456f731 1265 #define _USART_I2SCTRL_DMASPLIT_SHIFT 3 /**< Shift value for USART_DMASPLIT */
<> 153:fa9ff456f731 1266 #define _USART_I2SCTRL_DMASPLIT_MASK 0x8UL /**< Bit mask for USART_DMASPLIT */
<> 153:fa9ff456f731 1267 #define _USART_I2SCTRL_DMASPLIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1268 #define USART_I2SCTRL_DMASPLIT_DEFAULT (_USART_I2SCTRL_DMASPLIT_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1269 #define USART_I2SCTRL_DELAY (0x1UL << 4) /**< Delay on I2S data */
<> 153:fa9ff456f731 1270 #define _USART_I2SCTRL_DELAY_SHIFT 4 /**< Shift value for USART_DELAY */
<> 153:fa9ff456f731 1271 #define _USART_I2SCTRL_DELAY_MASK 0x10UL /**< Bit mask for USART_DELAY */
<> 153:fa9ff456f731 1272 #define _USART_I2SCTRL_DELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1273 #define USART_I2SCTRL_DELAY_DEFAULT (_USART_I2SCTRL_DELAY_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1274 #define _USART_I2SCTRL_FORMAT_SHIFT 8 /**< Shift value for USART_FORMAT */
<> 153:fa9ff456f731 1275 #define _USART_I2SCTRL_FORMAT_MASK 0x700UL /**< Bit mask for USART_FORMAT */
<> 153:fa9ff456f731 1276 #define _USART_I2SCTRL_FORMAT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1277 #define _USART_I2SCTRL_FORMAT_W32D32 0x00000000UL /**< Mode W32D32 for USART_I2SCTRL */
<> 153:fa9ff456f731 1278 #define _USART_I2SCTRL_FORMAT_W32D24M 0x00000001UL /**< Mode W32D24M for USART_I2SCTRL */
<> 153:fa9ff456f731 1279 #define _USART_I2SCTRL_FORMAT_W32D24 0x00000002UL /**< Mode W32D24 for USART_I2SCTRL */
<> 153:fa9ff456f731 1280 #define _USART_I2SCTRL_FORMAT_W32D16 0x00000003UL /**< Mode W32D16 for USART_I2SCTRL */
<> 153:fa9ff456f731 1281 #define _USART_I2SCTRL_FORMAT_W32D8 0x00000004UL /**< Mode W32D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1282 #define _USART_I2SCTRL_FORMAT_W16D16 0x00000005UL /**< Mode W16D16 for USART_I2SCTRL */
<> 153:fa9ff456f731 1283 #define _USART_I2SCTRL_FORMAT_W16D8 0x00000006UL /**< Mode W16D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1284 #define _USART_I2SCTRL_FORMAT_W8D8 0x00000007UL /**< Mode W8D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1285 #define USART_I2SCTRL_FORMAT_DEFAULT (_USART_I2SCTRL_FORMAT_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_I2SCTRL */
<> 153:fa9ff456f731 1286 #define USART_I2SCTRL_FORMAT_W32D32 (_USART_I2SCTRL_FORMAT_W32D32 << 8) /**< Shifted mode W32D32 for USART_I2SCTRL */
<> 153:fa9ff456f731 1287 #define USART_I2SCTRL_FORMAT_W32D24M (_USART_I2SCTRL_FORMAT_W32D24M << 8) /**< Shifted mode W32D24M for USART_I2SCTRL */
<> 153:fa9ff456f731 1288 #define USART_I2SCTRL_FORMAT_W32D24 (_USART_I2SCTRL_FORMAT_W32D24 << 8) /**< Shifted mode W32D24 for USART_I2SCTRL */
<> 153:fa9ff456f731 1289 #define USART_I2SCTRL_FORMAT_W32D16 (_USART_I2SCTRL_FORMAT_W32D16 << 8) /**< Shifted mode W32D16 for USART_I2SCTRL */
<> 153:fa9ff456f731 1290 #define USART_I2SCTRL_FORMAT_W32D8 (_USART_I2SCTRL_FORMAT_W32D8 << 8) /**< Shifted mode W32D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1291 #define USART_I2SCTRL_FORMAT_W16D16 (_USART_I2SCTRL_FORMAT_W16D16 << 8) /**< Shifted mode W16D16 for USART_I2SCTRL */
<> 153:fa9ff456f731 1292 #define USART_I2SCTRL_FORMAT_W16D8 (_USART_I2SCTRL_FORMAT_W16D8 << 8) /**< Shifted mode W16D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1293 #define USART_I2SCTRL_FORMAT_W8D8 (_USART_I2SCTRL_FORMAT_W8D8 << 8) /**< Shifted mode W8D8 for USART_I2SCTRL */
<> 153:fa9ff456f731 1294
<> 153:fa9ff456f731 1295 /* Bit fields for USART TIMING */
<> 153:fa9ff456f731 1296 #define _USART_TIMING_RESETVALUE 0x00000000UL /**< Default value for USART_TIMING */
<> 153:fa9ff456f731 1297 #define _USART_TIMING_MASK 0x77770000UL /**< Mask for USART_TIMING */
<> 153:fa9ff456f731 1298 #define _USART_TIMING_TXDELAY_SHIFT 16 /**< Shift value for USART_TXDELAY */
<> 153:fa9ff456f731 1299 #define _USART_TIMING_TXDELAY_MASK 0x70000UL /**< Bit mask for USART_TXDELAY */
<> 153:fa9ff456f731 1300 #define _USART_TIMING_TXDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1301 #define _USART_TIMING_TXDELAY_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMING */
<> 153:fa9ff456f731 1302 #define _USART_TIMING_TXDELAY_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1303 #define _USART_TIMING_TXDELAY_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1304 #define _USART_TIMING_TXDELAY_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1305 #define _USART_TIMING_TXDELAY_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1306 #define _USART_TIMING_TXDELAY_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1307 #define _USART_TIMING_TXDELAY_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1308 #define _USART_TIMING_TXDELAY_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1309 #define USART_TIMING_TXDELAY_DEFAULT (_USART_TIMING_TXDELAY_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1310 #define USART_TIMING_TXDELAY_DISABLE (_USART_TIMING_TXDELAY_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMING */
<> 153:fa9ff456f731 1311 #define USART_TIMING_TXDELAY_ONE (_USART_TIMING_TXDELAY_ONE << 16) /**< Shifted mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1312 #define USART_TIMING_TXDELAY_TWO (_USART_TIMING_TXDELAY_TWO << 16) /**< Shifted mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1313 #define USART_TIMING_TXDELAY_THREE (_USART_TIMING_TXDELAY_THREE << 16) /**< Shifted mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1314 #define USART_TIMING_TXDELAY_SEVEN (_USART_TIMING_TXDELAY_SEVEN << 16) /**< Shifted mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1315 #define USART_TIMING_TXDELAY_TCMP0 (_USART_TIMING_TXDELAY_TCMP0 << 16) /**< Shifted mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1316 #define USART_TIMING_TXDELAY_TCMP1 (_USART_TIMING_TXDELAY_TCMP1 << 16) /**< Shifted mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1317 #define USART_TIMING_TXDELAY_TCMP2 (_USART_TIMING_TXDELAY_TCMP2 << 16) /**< Shifted mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1318 #define _USART_TIMING_CSSETUP_SHIFT 20 /**< Shift value for USART_CSSETUP */
<> 153:fa9ff456f731 1319 #define _USART_TIMING_CSSETUP_MASK 0x700000UL /**< Bit mask for USART_CSSETUP */
<> 153:fa9ff456f731 1320 #define _USART_TIMING_CSSETUP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1321 #define _USART_TIMING_CSSETUP_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1322 #define _USART_TIMING_CSSETUP_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1323 #define _USART_TIMING_CSSETUP_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1324 #define _USART_TIMING_CSSETUP_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1325 #define _USART_TIMING_CSSETUP_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1326 #define _USART_TIMING_CSSETUP_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1327 #define _USART_TIMING_CSSETUP_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1328 #define _USART_TIMING_CSSETUP_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1329 #define USART_TIMING_CSSETUP_DEFAULT (_USART_TIMING_CSSETUP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1330 #define USART_TIMING_CSSETUP_ZERO (_USART_TIMING_CSSETUP_ZERO << 20) /**< Shifted mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1331 #define USART_TIMING_CSSETUP_ONE (_USART_TIMING_CSSETUP_ONE << 20) /**< Shifted mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1332 #define USART_TIMING_CSSETUP_TWO (_USART_TIMING_CSSETUP_TWO << 20) /**< Shifted mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1333 #define USART_TIMING_CSSETUP_THREE (_USART_TIMING_CSSETUP_THREE << 20) /**< Shifted mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1334 #define USART_TIMING_CSSETUP_SEVEN (_USART_TIMING_CSSETUP_SEVEN << 20) /**< Shifted mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1335 #define USART_TIMING_CSSETUP_TCMP0 (_USART_TIMING_CSSETUP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1336 #define USART_TIMING_CSSETUP_TCMP1 (_USART_TIMING_CSSETUP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1337 #define USART_TIMING_CSSETUP_TCMP2 (_USART_TIMING_CSSETUP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1338 #define _USART_TIMING_ICS_SHIFT 24 /**< Shift value for USART_ICS */
<> 153:fa9ff456f731 1339 #define _USART_TIMING_ICS_MASK 0x7000000UL /**< Bit mask for USART_ICS */
<> 153:fa9ff456f731 1340 #define _USART_TIMING_ICS_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1341 #define _USART_TIMING_ICS_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1342 #define _USART_TIMING_ICS_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1343 #define _USART_TIMING_ICS_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1344 #define _USART_TIMING_ICS_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1345 #define _USART_TIMING_ICS_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1346 #define _USART_TIMING_ICS_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1347 #define _USART_TIMING_ICS_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1348 #define _USART_TIMING_ICS_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1349 #define USART_TIMING_ICS_DEFAULT (_USART_TIMING_ICS_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1350 #define USART_TIMING_ICS_ZERO (_USART_TIMING_ICS_ZERO << 24) /**< Shifted mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1351 #define USART_TIMING_ICS_ONE (_USART_TIMING_ICS_ONE << 24) /**< Shifted mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1352 #define USART_TIMING_ICS_TWO (_USART_TIMING_ICS_TWO << 24) /**< Shifted mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1353 #define USART_TIMING_ICS_THREE (_USART_TIMING_ICS_THREE << 24) /**< Shifted mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1354 #define USART_TIMING_ICS_SEVEN (_USART_TIMING_ICS_SEVEN << 24) /**< Shifted mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1355 #define USART_TIMING_ICS_TCMP0 (_USART_TIMING_ICS_TCMP0 << 24) /**< Shifted mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1356 #define USART_TIMING_ICS_TCMP1 (_USART_TIMING_ICS_TCMP1 << 24) /**< Shifted mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1357 #define USART_TIMING_ICS_TCMP2 (_USART_TIMING_ICS_TCMP2 << 24) /**< Shifted mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1358 #define _USART_TIMING_CSHOLD_SHIFT 28 /**< Shift value for USART_CSHOLD */
<> 153:fa9ff456f731 1359 #define _USART_TIMING_CSHOLD_MASK 0x70000000UL /**< Bit mask for USART_CSHOLD */
<> 153:fa9ff456f731 1360 #define _USART_TIMING_CSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1361 #define _USART_TIMING_CSHOLD_ZERO 0x00000000UL /**< Mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1362 #define _USART_TIMING_CSHOLD_ONE 0x00000001UL /**< Mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1363 #define _USART_TIMING_CSHOLD_TWO 0x00000002UL /**< Mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1364 #define _USART_TIMING_CSHOLD_THREE 0x00000003UL /**< Mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1365 #define _USART_TIMING_CSHOLD_SEVEN 0x00000004UL /**< Mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1366 #define _USART_TIMING_CSHOLD_TCMP0 0x00000005UL /**< Mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1367 #define _USART_TIMING_CSHOLD_TCMP1 0x00000006UL /**< Mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1368 #define _USART_TIMING_CSHOLD_TCMP2 0x00000007UL /**< Mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1369 #define USART_TIMING_CSHOLD_DEFAULT (_USART_TIMING_CSHOLD_DEFAULT << 28) /**< Shifted mode DEFAULT for USART_TIMING */
<> 153:fa9ff456f731 1370 #define USART_TIMING_CSHOLD_ZERO (_USART_TIMING_CSHOLD_ZERO << 28) /**< Shifted mode ZERO for USART_TIMING */
<> 153:fa9ff456f731 1371 #define USART_TIMING_CSHOLD_ONE (_USART_TIMING_CSHOLD_ONE << 28) /**< Shifted mode ONE for USART_TIMING */
<> 153:fa9ff456f731 1372 #define USART_TIMING_CSHOLD_TWO (_USART_TIMING_CSHOLD_TWO << 28) /**< Shifted mode TWO for USART_TIMING */
<> 153:fa9ff456f731 1373 #define USART_TIMING_CSHOLD_THREE (_USART_TIMING_CSHOLD_THREE << 28) /**< Shifted mode THREE for USART_TIMING */
<> 153:fa9ff456f731 1374 #define USART_TIMING_CSHOLD_SEVEN (_USART_TIMING_CSHOLD_SEVEN << 28) /**< Shifted mode SEVEN for USART_TIMING */
<> 153:fa9ff456f731 1375 #define USART_TIMING_CSHOLD_TCMP0 (_USART_TIMING_CSHOLD_TCMP0 << 28) /**< Shifted mode TCMP0 for USART_TIMING */
<> 153:fa9ff456f731 1376 #define USART_TIMING_CSHOLD_TCMP1 (_USART_TIMING_CSHOLD_TCMP1 << 28) /**< Shifted mode TCMP1 for USART_TIMING */
<> 153:fa9ff456f731 1377 #define USART_TIMING_CSHOLD_TCMP2 (_USART_TIMING_CSHOLD_TCMP2 << 28) /**< Shifted mode TCMP2 for USART_TIMING */
<> 153:fa9ff456f731 1378
<> 153:fa9ff456f731 1379 /* Bit fields for USART CTRLX */
<> 153:fa9ff456f731 1380 #define _USART_CTRLX_RESETVALUE 0x00000000UL /**< Default value for USART_CTRLX */
<> 153:fa9ff456f731 1381 #define _USART_CTRLX_MASK 0x0000000FUL /**< Mask for USART_CTRLX */
<> 153:fa9ff456f731 1382 #define USART_CTRLX_DBGHALT (0x1UL << 0) /**< Debug halt */
<> 153:fa9ff456f731 1383 #define _USART_CTRLX_DBGHALT_SHIFT 0 /**< Shift value for USART_DBGHALT */
<> 153:fa9ff456f731 1384 #define _USART_CTRLX_DBGHALT_MASK 0x1UL /**< Bit mask for USART_DBGHALT */
<> 153:fa9ff456f731 1385 #define _USART_CTRLX_DBGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1386 #define USART_CTRLX_DBGHALT_DEFAULT (_USART_CTRLX_DBGHALT_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1387 #define USART_CTRLX_CTSINV (0x1UL << 1) /**< CTS Pin Inversion */
<> 153:fa9ff456f731 1388 #define _USART_CTRLX_CTSINV_SHIFT 1 /**< Shift value for USART_CTSINV */
<> 153:fa9ff456f731 1389 #define _USART_CTRLX_CTSINV_MASK 0x2UL /**< Bit mask for USART_CTSINV */
<> 153:fa9ff456f731 1390 #define _USART_CTRLX_CTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1391 #define USART_CTRLX_CTSINV_DEFAULT (_USART_CTRLX_CTSINV_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1392 #define USART_CTRLX_CTSEN (0x1UL << 2) /**< CTS Function enabled */
<> 153:fa9ff456f731 1393 #define _USART_CTRLX_CTSEN_SHIFT 2 /**< Shift value for USART_CTSEN */
<> 153:fa9ff456f731 1394 #define _USART_CTRLX_CTSEN_MASK 0x4UL /**< Bit mask for USART_CTSEN */
<> 153:fa9ff456f731 1395 #define _USART_CTRLX_CTSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1396 #define USART_CTRLX_CTSEN_DEFAULT (_USART_CTRLX_CTSEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1397 #define USART_CTRLX_RTSINV (0x1UL << 3) /**< RTS Pin Inversion */
<> 153:fa9ff456f731 1398 #define _USART_CTRLX_RTSINV_SHIFT 3 /**< Shift value for USART_RTSINV */
<> 153:fa9ff456f731 1399 #define _USART_CTRLX_RTSINV_MASK 0x8UL /**< Bit mask for USART_RTSINV */
<> 153:fa9ff456f731 1400 #define _USART_CTRLX_RTSINV_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1401 #define USART_CTRLX_RTSINV_DEFAULT (_USART_CTRLX_RTSINV_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_CTRLX */
<> 153:fa9ff456f731 1402
<> 153:fa9ff456f731 1403 /* Bit fields for USART TIMECMP0 */
<> 153:fa9ff456f731 1404 #define _USART_TIMECMP0_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP0 */
<> 153:fa9ff456f731 1405 #define _USART_TIMECMP0_MASK 0x017700FFUL /**< Mask for USART_TIMECMP0 */
<> 153:fa9ff456f731 1406 #define _USART_TIMECMP0_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 153:fa9ff456f731 1407 #define _USART_TIMECMP0_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 153:fa9ff456f731 1408 #define _USART_TIMECMP0_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1409 #define USART_TIMECMP0_TCMPVAL_DEFAULT (_USART_TIMECMP0_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1410 #define _USART_TIMECMP0_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 153:fa9ff456f731 1411 #define _USART_TIMECMP0_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 153:fa9ff456f731 1412 #define _USART_TIMECMP0_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1413 #define _USART_TIMECMP0_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP0 */
<> 153:fa9ff456f731 1414 #define _USART_TIMECMP0_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP0 */
<> 153:fa9ff456f731 1415 #define _USART_TIMECMP0_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP0 */
<> 153:fa9ff456f731 1416 #define _USART_TIMECMP0_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1417 #define _USART_TIMECMP0_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP0 */
<> 153:fa9ff456f731 1418 #define USART_TIMECMP0_TSTART_DEFAULT (_USART_TIMECMP0_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1419 #define USART_TIMECMP0_TSTART_DISABLE (_USART_TIMECMP0_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP0 */
<> 153:fa9ff456f731 1420 #define USART_TIMECMP0_TSTART_TXEOF (_USART_TIMECMP0_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP0 */
<> 153:fa9ff456f731 1421 #define USART_TIMECMP0_TSTART_TXC (_USART_TIMECMP0_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP0 */
<> 153:fa9ff456f731 1422 #define USART_TIMECMP0_TSTART_RXACT (_USART_TIMECMP0_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1423 #define USART_TIMECMP0_TSTART_RXEOF (_USART_TIMECMP0_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP0 */
<> 153:fa9ff456f731 1424 #define _USART_TIMECMP0_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 153:fa9ff456f731 1425 #define _USART_TIMECMP0_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 153:fa9ff456f731 1426 #define _USART_TIMECMP0_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1427 #define _USART_TIMECMP0_TSTOP_TCMP0 0x00000000UL /**< Mode TCMP0 for USART_TIMECMP0 */
<> 153:fa9ff456f731 1428 #define _USART_TIMECMP0_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP0 */
<> 153:fa9ff456f731 1429 #define _USART_TIMECMP0_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1430 #define _USART_TIMECMP0_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP0 */
<> 153:fa9ff456f731 1431 #define USART_TIMECMP0_TSTOP_DEFAULT (_USART_TIMECMP0_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1432 #define USART_TIMECMP0_TSTOP_TCMP0 (_USART_TIMECMP0_TSTOP_TCMP0 << 20) /**< Shifted mode TCMP0 for USART_TIMECMP0 */
<> 153:fa9ff456f731 1433 #define USART_TIMECMP0_TSTOP_TXST (_USART_TIMECMP0_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP0 */
<> 153:fa9ff456f731 1434 #define USART_TIMECMP0_TSTOP_RXACT (_USART_TIMECMP0_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1435 #define USART_TIMECMP0_TSTOP_RXACTN (_USART_TIMECMP0_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP0 */
<> 153:fa9ff456f731 1436 #define USART_TIMECMP0_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP0 */
<> 153:fa9ff456f731 1437 #define _USART_TIMECMP0_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 153:fa9ff456f731 1438 #define _USART_TIMECMP0_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 153:fa9ff456f731 1439 #define _USART_TIMECMP0_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1440 #define USART_TIMECMP0_RESTARTEN_DEFAULT (_USART_TIMECMP0_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP0 */
<> 153:fa9ff456f731 1441
<> 153:fa9ff456f731 1442 /* Bit fields for USART TIMECMP1 */
<> 153:fa9ff456f731 1443 #define _USART_TIMECMP1_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP1 */
<> 153:fa9ff456f731 1444 #define _USART_TIMECMP1_MASK 0x017700FFUL /**< Mask for USART_TIMECMP1 */
<> 153:fa9ff456f731 1445 #define _USART_TIMECMP1_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 153:fa9ff456f731 1446 #define _USART_TIMECMP1_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 153:fa9ff456f731 1447 #define _USART_TIMECMP1_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1448 #define USART_TIMECMP1_TCMPVAL_DEFAULT (_USART_TIMECMP1_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1449 #define _USART_TIMECMP1_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 153:fa9ff456f731 1450 #define _USART_TIMECMP1_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 153:fa9ff456f731 1451 #define _USART_TIMECMP1_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1452 #define _USART_TIMECMP1_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP1 */
<> 153:fa9ff456f731 1453 #define _USART_TIMECMP1_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP1 */
<> 153:fa9ff456f731 1454 #define _USART_TIMECMP1_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP1 */
<> 153:fa9ff456f731 1455 #define _USART_TIMECMP1_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1456 #define _USART_TIMECMP1_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP1 */
<> 153:fa9ff456f731 1457 #define USART_TIMECMP1_TSTART_DEFAULT (_USART_TIMECMP1_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1458 #define USART_TIMECMP1_TSTART_DISABLE (_USART_TIMECMP1_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP1 */
<> 153:fa9ff456f731 1459 #define USART_TIMECMP1_TSTART_TXEOF (_USART_TIMECMP1_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP1 */
<> 153:fa9ff456f731 1460 #define USART_TIMECMP1_TSTART_TXC (_USART_TIMECMP1_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP1 */
<> 153:fa9ff456f731 1461 #define USART_TIMECMP1_TSTART_RXACT (_USART_TIMECMP1_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1462 #define USART_TIMECMP1_TSTART_RXEOF (_USART_TIMECMP1_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP1 */
<> 153:fa9ff456f731 1463 #define _USART_TIMECMP1_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 153:fa9ff456f731 1464 #define _USART_TIMECMP1_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 153:fa9ff456f731 1465 #define _USART_TIMECMP1_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1466 #define _USART_TIMECMP1_TSTOP_TCMP1 0x00000000UL /**< Mode TCMP1 for USART_TIMECMP1 */
<> 153:fa9ff456f731 1467 #define _USART_TIMECMP1_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP1 */
<> 153:fa9ff456f731 1468 #define _USART_TIMECMP1_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1469 #define _USART_TIMECMP1_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP1 */
<> 153:fa9ff456f731 1470 #define USART_TIMECMP1_TSTOP_DEFAULT (_USART_TIMECMP1_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1471 #define USART_TIMECMP1_TSTOP_TCMP1 (_USART_TIMECMP1_TSTOP_TCMP1 << 20) /**< Shifted mode TCMP1 for USART_TIMECMP1 */
<> 153:fa9ff456f731 1472 #define USART_TIMECMP1_TSTOP_TXST (_USART_TIMECMP1_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP1 */
<> 153:fa9ff456f731 1473 #define USART_TIMECMP1_TSTOP_RXACT (_USART_TIMECMP1_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1474 #define USART_TIMECMP1_TSTOP_RXACTN (_USART_TIMECMP1_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP1 */
<> 153:fa9ff456f731 1475 #define USART_TIMECMP1_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP1 */
<> 153:fa9ff456f731 1476 #define _USART_TIMECMP1_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 153:fa9ff456f731 1477 #define _USART_TIMECMP1_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 153:fa9ff456f731 1478 #define _USART_TIMECMP1_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1479 #define USART_TIMECMP1_RESTARTEN_DEFAULT (_USART_TIMECMP1_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP1 */
<> 153:fa9ff456f731 1480
<> 153:fa9ff456f731 1481 /* Bit fields for USART TIMECMP2 */
<> 153:fa9ff456f731 1482 #define _USART_TIMECMP2_RESETVALUE 0x00000000UL /**< Default value for USART_TIMECMP2 */
<> 153:fa9ff456f731 1483 #define _USART_TIMECMP2_MASK 0x017700FFUL /**< Mask for USART_TIMECMP2 */
<> 153:fa9ff456f731 1484 #define _USART_TIMECMP2_TCMPVAL_SHIFT 0 /**< Shift value for USART_TCMPVAL */
<> 153:fa9ff456f731 1485 #define _USART_TIMECMP2_TCMPVAL_MASK 0xFFUL /**< Bit mask for USART_TCMPVAL */
<> 153:fa9ff456f731 1486 #define _USART_TIMECMP2_TCMPVAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1487 #define USART_TIMECMP2_TCMPVAL_DEFAULT (_USART_TIMECMP2_TCMPVAL_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1488 #define _USART_TIMECMP2_TSTART_SHIFT 16 /**< Shift value for USART_TSTART */
<> 153:fa9ff456f731 1489 #define _USART_TIMECMP2_TSTART_MASK 0x70000UL /**< Bit mask for USART_TSTART */
<> 153:fa9ff456f731 1490 #define _USART_TIMECMP2_TSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1491 #define _USART_TIMECMP2_TSTART_DISABLE 0x00000000UL /**< Mode DISABLE for USART_TIMECMP2 */
<> 153:fa9ff456f731 1492 #define _USART_TIMECMP2_TSTART_TXEOF 0x00000001UL /**< Mode TXEOF for USART_TIMECMP2 */
<> 153:fa9ff456f731 1493 #define _USART_TIMECMP2_TSTART_TXC 0x00000002UL /**< Mode TXC for USART_TIMECMP2 */
<> 153:fa9ff456f731 1494 #define _USART_TIMECMP2_TSTART_RXACT 0x00000003UL /**< Mode RXACT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1495 #define _USART_TIMECMP2_TSTART_RXEOF 0x00000004UL /**< Mode RXEOF for USART_TIMECMP2 */
<> 153:fa9ff456f731 1496 #define USART_TIMECMP2_TSTART_DEFAULT (_USART_TIMECMP2_TSTART_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1497 #define USART_TIMECMP2_TSTART_DISABLE (_USART_TIMECMP2_TSTART_DISABLE << 16) /**< Shifted mode DISABLE for USART_TIMECMP2 */
<> 153:fa9ff456f731 1498 #define USART_TIMECMP2_TSTART_TXEOF (_USART_TIMECMP2_TSTART_TXEOF << 16) /**< Shifted mode TXEOF for USART_TIMECMP2 */
<> 153:fa9ff456f731 1499 #define USART_TIMECMP2_TSTART_TXC (_USART_TIMECMP2_TSTART_TXC << 16) /**< Shifted mode TXC for USART_TIMECMP2 */
<> 153:fa9ff456f731 1500 #define USART_TIMECMP2_TSTART_RXACT (_USART_TIMECMP2_TSTART_RXACT << 16) /**< Shifted mode RXACT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1501 #define USART_TIMECMP2_TSTART_RXEOF (_USART_TIMECMP2_TSTART_RXEOF << 16) /**< Shifted mode RXEOF for USART_TIMECMP2 */
<> 153:fa9ff456f731 1502 #define _USART_TIMECMP2_TSTOP_SHIFT 20 /**< Shift value for USART_TSTOP */
<> 153:fa9ff456f731 1503 #define _USART_TIMECMP2_TSTOP_MASK 0x700000UL /**< Bit mask for USART_TSTOP */
<> 153:fa9ff456f731 1504 #define _USART_TIMECMP2_TSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1505 #define _USART_TIMECMP2_TSTOP_TCMP2 0x00000000UL /**< Mode TCMP2 for USART_TIMECMP2 */
<> 153:fa9ff456f731 1506 #define _USART_TIMECMP2_TSTOP_TXST 0x00000001UL /**< Mode TXST for USART_TIMECMP2 */
<> 153:fa9ff456f731 1507 #define _USART_TIMECMP2_TSTOP_RXACT 0x00000002UL /**< Mode RXACT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1508 #define _USART_TIMECMP2_TSTOP_RXACTN 0x00000003UL /**< Mode RXACTN for USART_TIMECMP2 */
<> 153:fa9ff456f731 1509 #define USART_TIMECMP2_TSTOP_DEFAULT (_USART_TIMECMP2_TSTOP_DEFAULT << 20) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1510 #define USART_TIMECMP2_TSTOP_TCMP2 (_USART_TIMECMP2_TSTOP_TCMP2 << 20) /**< Shifted mode TCMP2 for USART_TIMECMP2 */
<> 153:fa9ff456f731 1511 #define USART_TIMECMP2_TSTOP_TXST (_USART_TIMECMP2_TSTOP_TXST << 20) /**< Shifted mode TXST for USART_TIMECMP2 */
<> 153:fa9ff456f731 1512 #define USART_TIMECMP2_TSTOP_RXACT (_USART_TIMECMP2_TSTOP_RXACT << 20) /**< Shifted mode RXACT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1513 #define USART_TIMECMP2_TSTOP_RXACTN (_USART_TIMECMP2_TSTOP_RXACTN << 20) /**< Shifted mode RXACTN for USART_TIMECMP2 */
<> 153:fa9ff456f731 1514 #define USART_TIMECMP2_RESTARTEN (0x1UL << 24) /**< Restart Timer on TCMP2 */
<> 153:fa9ff456f731 1515 #define _USART_TIMECMP2_RESTARTEN_SHIFT 24 /**< Shift value for USART_RESTARTEN */
<> 153:fa9ff456f731 1516 #define _USART_TIMECMP2_RESTARTEN_MASK 0x1000000UL /**< Bit mask for USART_RESTARTEN */
<> 153:fa9ff456f731 1517 #define _USART_TIMECMP2_RESTARTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1518 #define USART_TIMECMP2_RESTARTEN_DEFAULT (_USART_TIMECMP2_RESTARTEN_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_TIMECMP2 */
<> 153:fa9ff456f731 1519
<> 153:fa9ff456f731 1520 /* Bit fields for USART ROUTEPEN */
<> 153:fa9ff456f731 1521 #define _USART_ROUTEPEN_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTEPEN */
<> 153:fa9ff456f731 1522 #define _USART_ROUTEPEN_MASK 0x0000003FUL /**< Mask for USART_ROUTEPEN */
<> 153:fa9ff456f731 1523 #define USART_ROUTEPEN_RXPEN (0x1UL << 0) /**< RX Pin Enable */
<> 153:fa9ff456f731 1524 #define _USART_ROUTEPEN_RXPEN_SHIFT 0 /**< Shift value for USART_RXPEN */
<> 153:fa9ff456f731 1525 #define _USART_ROUTEPEN_RXPEN_MASK 0x1UL /**< Bit mask for USART_RXPEN */
<> 153:fa9ff456f731 1526 #define _USART_ROUTEPEN_RXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1527 #define USART_ROUTEPEN_RXPEN_DEFAULT (_USART_ROUTEPEN_RXPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1528 #define USART_ROUTEPEN_TXPEN (0x1UL << 1) /**< TX Pin Enable */
<> 153:fa9ff456f731 1529 #define _USART_ROUTEPEN_TXPEN_SHIFT 1 /**< Shift value for USART_TXPEN */
<> 153:fa9ff456f731 1530 #define _USART_ROUTEPEN_TXPEN_MASK 0x2UL /**< Bit mask for USART_TXPEN */
<> 153:fa9ff456f731 1531 #define _USART_ROUTEPEN_TXPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1532 #define USART_ROUTEPEN_TXPEN_DEFAULT (_USART_ROUTEPEN_TXPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1533 #define USART_ROUTEPEN_CSPEN (0x1UL << 2) /**< CS Pin Enable */
<> 153:fa9ff456f731 1534 #define _USART_ROUTEPEN_CSPEN_SHIFT 2 /**< Shift value for USART_CSPEN */
<> 153:fa9ff456f731 1535 #define _USART_ROUTEPEN_CSPEN_MASK 0x4UL /**< Bit mask for USART_CSPEN */
<> 153:fa9ff456f731 1536 #define _USART_ROUTEPEN_CSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1537 #define USART_ROUTEPEN_CSPEN_DEFAULT (_USART_ROUTEPEN_CSPEN_DEFAULT << 2) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1538 #define USART_ROUTEPEN_CLKPEN (0x1UL << 3) /**< CLK Pin Enable */
<> 153:fa9ff456f731 1539 #define _USART_ROUTEPEN_CLKPEN_SHIFT 3 /**< Shift value for USART_CLKPEN */
<> 153:fa9ff456f731 1540 #define _USART_ROUTEPEN_CLKPEN_MASK 0x8UL /**< Bit mask for USART_CLKPEN */
<> 153:fa9ff456f731 1541 #define _USART_ROUTEPEN_CLKPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1542 #define USART_ROUTEPEN_CLKPEN_DEFAULT (_USART_ROUTEPEN_CLKPEN_DEFAULT << 3) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1543 #define USART_ROUTEPEN_CTSPEN (0x1UL << 4) /**< CTS Pin Enable */
<> 153:fa9ff456f731 1544 #define _USART_ROUTEPEN_CTSPEN_SHIFT 4 /**< Shift value for USART_CTSPEN */
<> 153:fa9ff456f731 1545 #define _USART_ROUTEPEN_CTSPEN_MASK 0x10UL /**< Bit mask for USART_CTSPEN */
<> 153:fa9ff456f731 1546 #define _USART_ROUTEPEN_CTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1547 #define USART_ROUTEPEN_CTSPEN_DEFAULT (_USART_ROUTEPEN_CTSPEN_DEFAULT << 4) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1548 #define USART_ROUTEPEN_RTSPEN (0x1UL << 5) /**< RTS Pin Enable */
<> 153:fa9ff456f731 1549 #define _USART_ROUTEPEN_RTSPEN_SHIFT 5 /**< Shift value for USART_RTSPEN */
<> 153:fa9ff456f731 1550 #define _USART_ROUTEPEN_RTSPEN_MASK 0x20UL /**< Bit mask for USART_RTSPEN */
<> 153:fa9ff456f731 1551 #define _USART_ROUTEPEN_RTSPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1552 #define USART_ROUTEPEN_RTSPEN_DEFAULT (_USART_ROUTEPEN_RTSPEN_DEFAULT << 5) /**< Shifted mode DEFAULT for USART_ROUTEPEN */
<> 153:fa9ff456f731 1553
<> 153:fa9ff456f731 1554 /* Bit fields for USART ROUTELOC0 */
<> 153:fa9ff456f731 1555 #define _USART_ROUTELOC0_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1556 #define _USART_ROUTELOC0_MASK 0x1F1F1F1FUL /**< Mask for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1557 #define _USART_ROUTELOC0_RXLOC_SHIFT 0 /**< Shift value for USART_RXLOC */
<> 153:fa9ff456f731 1558 #define _USART_ROUTELOC0_RXLOC_MASK 0x1FUL /**< Bit mask for USART_RXLOC */
<> 153:fa9ff456f731 1559 #define _USART_ROUTELOC0_RXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1560 #define _USART_ROUTELOC0_RXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1561 #define _USART_ROUTELOC0_RXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1562 #define _USART_ROUTELOC0_RXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1563 #define _USART_ROUTELOC0_RXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1564 #define _USART_ROUTELOC0_RXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1565 #define _USART_ROUTELOC0_RXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1566 #define _USART_ROUTELOC0_RXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1567 #define _USART_ROUTELOC0_RXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1568 #define _USART_ROUTELOC0_RXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1569 #define _USART_ROUTELOC0_RXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1570 #define _USART_ROUTELOC0_RXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1571 #define _USART_ROUTELOC0_RXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1572 #define _USART_ROUTELOC0_RXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1573 #define _USART_ROUTELOC0_RXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1574 #define _USART_ROUTELOC0_RXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1575 #define _USART_ROUTELOC0_RXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1576 #define _USART_ROUTELOC0_RXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1577 #define _USART_ROUTELOC0_RXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1578 #define _USART_ROUTELOC0_RXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1579 #define _USART_ROUTELOC0_RXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1580 #define _USART_ROUTELOC0_RXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1581 #define _USART_ROUTELOC0_RXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1582 #define _USART_ROUTELOC0_RXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1583 #define _USART_ROUTELOC0_RXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1584 #define _USART_ROUTELOC0_RXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1585 #define _USART_ROUTELOC0_RXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1586 #define _USART_ROUTELOC0_RXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1587 #define _USART_ROUTELOC0_RXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1588 #define _USART_ROUTELOC0_RXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1589 #define _USART_ROUTELOC0_RXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1590 #define _USART_ROUTELOC0_RXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1591 #define _USART_ROUTELOC0_RXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1592 #define USART_ROUTELOC0_RXLOC_LOC0 (_USART_ROUTELOC0_RXLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1593 #define USART_ROUTELOC0_RXLOC_DEFAULT (_USART_ROUTELOC0_RXLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1594 #define USART_ROUTELOC0_RXLOC_LOC1 (_USART_ROUTELOC0_RXLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1595 #define USART_ROUTELOC0_RXLOC_LOC2 (_USART_ROUTELOC0_RXLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1596 #define USART_ROUTELOC0_RXLOC_LOC3 (_USART_ROUTELOC0_RXLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1597 #define USART_ROUTELOC0_RXLOC_LOC4 (_USART_ROUTELOC0_RXLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1598 #define USART_ROUTELOC0_RXLOC_LOC5 (_USART_ROUTELOC0_RXLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1599 #define USART_ROUTELOC0_RXLOC_LOC6 (_USART_ROUTELOC0_RXLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1600 #define USART_ROUTELOC0_RXLOC_LOC7 (_USART_ROUTELOC0_RXLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1601 #define USART_ROUTELOC0_RXLOC_LOC8 (_USART_ROUTELOC0_RXLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1602 #define USART_ROUTELOC0_RXLOC_LOC9 (_USART_ROUTELOC0_RXLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1603 #define USART_ROUTELOC0_RXLOC_LOC10 (_USART_ROUTELOC0_RXLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1604 #define USART_ROUTELOC0_RXLOC_LOC11 (_USART_ROUTELOC0_RXLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1605 #define USART_ROUTELOC0_RXLOC_LOC12 (_USART_ROUTELOC0_RXLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1606 #define USART_ROUTELOC0_RXLOC_LOC13 (_USART_ROUTELOC0_RXLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1607 #define USART_ROUTELOC0_RXLOC_LOC14 (_USART_ROUTELOC0_RXLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1608 #define USART_ROUTELOC0_RXLOC_LOC15 (_USART_ROUTELOC0_RXLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1609 #define USART_ROUTELOC0_RXLOC_LOC16 (_USART_ROUTELOC0_RXLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1610 #define USART_ROUTELOC0_RXLOC_LOC17 (_USART_ROUTELOC0_RXLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1611 #define USART_ROUTELOC0_RXLOC_LOC18 (_USART_ROUTELOC0_RXLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1612 #define USART_ROUTELOC0_RXLOC_LOC19 (_USART_ROUTELOC0_RXLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1613 #define USART_ROUTELOC0_RXLOC_LOC20 (_USART_ROUTELOC0_RXLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1614 #define USART_ROUTELOC0_RXLOC_LOC21 (_USART_ROUTELOC0_RXLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1615 #define USART_ROUTELOC0_RXLOC_LOC22 (_USART_ROUTELOC0_RXLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1616 #define USART_ROUTELOC0_RXLOC_LOC23 (_USART_ROUTELOC0_RXLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1617 #define USART_ROUTELOC0_RXLOC_LOC24 (_USART_ROUTELOC0_RXLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1618 #define USART_ROUTELOC0_RXLOC_LOC25 (_USART_ROUTELOC0_RXLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1619 #define USART_ROUTELOC0_RXLOC_LOC26 (_USART_ROUTELOC0_RXLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1620 #define USART_ROUTELOC0_RXLOC_LOC27 (_USART_ROUTELOC0_RXLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1621 #define USART_ROUTELOC0_RXLOC_LOC28 (_USART_ROUTELOC0_RXLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1622 #define USART_ROUTELOC0_RXLOC_LOC29 (_USART_ROUTELOC0_RXLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1623 #define USART_ROUTELOC0_RXLOC_LOC30 (_USART_ROUTELOC0_RXLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1624 #define USART_ROUTELOC0_RXLOC_LOC31 (_USART_ROUTELOC0_RXLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1625 #define _USART_ROUTELOC0_TXLOC_SHIFT 8 /**< Shift value for USART_TXLOC */
<> 153:fa9ff456f731 1626 #define _USART_ROUTELOC0_TXLOC_MASK 0x1F00UL /**< Bit mask for USART_TXLOC */
<> 153:fa9ff456f731 1627 #define _USART_ROUTELOC0_TXLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1628 #define _USART_ROUTELOC0_TXLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1629 #define _USART_ROUTELOC0_TXLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1630 #define _USART_ROUTELOC0_TXLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1631 #define _USART_ROUTELOC0_TXLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1632 #define _USART_ROUTELOC0_TXLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1633 #define _USART_ROUTELOC0_TXLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1634 #define _USART_ROUTELOC0_TXLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1635 #define _USART_ROUTELOC0_TXLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1636 #define _USART_ROUTELOC0_TXLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1637 #define _USART_ROUTELOC0_TXLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1638 #define _USART_ROUTELOC0_TXLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1639 #define _USART_ROUTELOC0_TXLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1640 #define _USART_ROUTELOC0_TXLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1641 #define _USART_ROUTELOC0_TXLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1642 #define _USART_ROUTELOC0_TXLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1643 #define _USART_ROUTELOC0_TXLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1644 #define _USART_ROUTELOC0_TXLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1645 #define _USART_ROUTELOC0_TXLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1646 #define _USART_ROUTELOC0_TXLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1647 #define _USART_ROUTELOC0_TXLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1648 #define _USART_ROUTELOC0_TXLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1649 #define _USART_ROUTELOC0_TXLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1650 #define _USART_ROUTELOC0_TXLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1651 #define _USART_ROUTELOC0_TXLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1652 #define _USART_ROUTELOC0_TXLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1653 #define _USART_ROUTELOC0_TXLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1654 #define _USART_ROUTELOC0_TXLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1655 #define _USART_ROUTELOC0_TXLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1656 #define _USART_ROUTELOC0_TXLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1657 #define _USART_ROUTELOC0_TXLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1658 #define _USART_ROUTELOC0_TXLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1659 #define _USART_ROUTELOC0_TXLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1660 #define USART_ROUTELOC0_TXLOC_LOC0 (_USART_ROUTELOC0_TXLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1661 #define USART_ROUTELOC0_TXLOC_DEFAULT (_USART_ROUTELOC0_TXLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1662 #define USART_ROUTELOC0_TXLOC_LOC1 (_USART_ROUTELOC0_TXLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1663 #define USART_ROUTELOC0_TXLOC_LOC2 (_USART_ROUTELOC0_TXLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1664 #define USART_ROUTELOC0_TXLOC_LOC3 (_USART_ROUTELOC0_TXLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1665 #define USART_ROUTELOC0_TXLOC_LOC4 (_USART_ROUTELOC0_TXLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1666 #define USART_ROUTELOC0_TXLOC_LOC5 (_USART_ROUTELOC0_TXLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1667 #define USART_ROUTELOC0_TXLOC_LOC6 (_USART_ROUTELOC0_TXLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1668 #define USART_ROUTELOC0_TXLOC_LOC7 (_USART_ROUTELOC0_TXLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1669 #define USART_ROUTELOC0_TXLOC_LOC8 (_USART_ROUTELOC0_TXLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1670 #define USART_ROUTELOC0_TXLOC_LOC9 (_USART_ROUTELOC0_TXLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1671 #define USART_ROUTELOC0_TXLOC_LOC10 (_USART_ROUTELOC0_TXLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1672 #define USART_ROUTELOC0_TXLOC_LOC11 (_USART_ROUTELOC0_TXLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1673 #define USART_ROUTELOC0_TXLOC_LOC12 (_USART_ROUTELOC0_TXLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1674 #define USART_ROUTELOC0_TXLOC_LOC13 (_USART_ROUTELOC0_TXLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1675 #define USART_ROUTELOC0_TXLOC_LOC14 (_USART_ROUTELOC0_TXLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1676 #define USART_ROUTELOC0_TXLOC_LOC15 (_USART_ROUTELOC0_TXLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1677 #define USART_ROUTELOC0_TXLOC_LOC16 (_USART_ROUTELOC0_TXLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1678 #define USART_ROUTELOC0_TXLOC_LOC17 (_USART_ROUTELOC0_TXLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1679 #define USART_ROUTELOC0_TXLOC_LOC18 (_USART_ROUTELOC0_TXLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1680 #define USART_ROUTELOC0_TXLOC_LOC19 (_USART_ROUTELOC0_TXLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1681 #define USART_ROUTELOC0_TXLOC_LOC20 (_USART_ROUTELOC0_TXLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1682 #define USART_ROUTELOC0_TXLOC_LOC21 (_USART_ROUTELOC0_TXLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1683 #define USART_ROUTELOC0_TXLOC_LOC22 (_USART_ROUTELOC0_TXLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1684 #define USART_ROUTELOC0_TXLOC_LOC23 (_USART_ROUTELOC0_TXLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1685 #define USART_ROUTELOC0_TXLOC_LOC24 (_USART_ROUTELOC0_TXLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1686 #define USART_ROUTELOC0_TXLOC_LOC25 (_USART_ROUTELOC0_TXLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1687 #define USART_ROUTELOC0_TXLOC_LOC26 (_USART_ROUTELOC0_TXLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1688 #define USART_ROUTELOC0_TXLOC_LOC27 (_USART_ROUTELOC0_TXLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1689 #define USART_ROUTELOC0_TXLOC_LOC28 (_USART_ROUTELOC0_TXLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1690 #define USART_ROUTELOC0_TXLOC_LOC29 (_USART_ROUTELOC0_TXLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1691 #define USART_ROUTELOC0_TXLOC_LOC30 (_USART_ROUTELOC0_TXLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1692 #define USART_ROUTELOC0_TXLOC_LOC31 (_USART_ROUTELOC0_TXLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1693 #define _USART_ROUTELOC0_CSLOC_SHIFT 16 /**< Shift value for USART_CSLOC */
<> 153:fa9ff456f731 1694 #define _USART_ROUTELOC0_CSLOC_MASK 0x1F0000UL /**< Bit mask for USART_CSLOC */
<> 153:fa9ff456f731 1695 #define _USART_ROUTELOC0_CSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1696 #define _USART_ROUTELOC0_CSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1697 #define _USART_ROUTELOC0_CSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1698 #define _USART_ROUTELOC0_CSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1699 #define _USART_ROUTELOC0_CSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1700 #define _USART_ROUTELOC0_CSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1701 #define _USART_ROUTELOC0_CSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1702 #define _USART_ROUTELOC0_CSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1703 #define _USART_ROUTELOC0_CSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1704 #define _USART_ROUTELOC0_CSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1705 #define _USART_ROUTELOC0_CSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1706 #define _USART_ROUTELOC0_CSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1707 #define _USART_ROUTELOC0_CSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1708 #define _USART_ROUTELOC0_CSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1709 #define _USART_ROUTELOC0_CSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1710 #define _USART_ROUTELOC0_CSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1711 #define _USART_ROUTELOC0_CSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1712 #define _USART_ROUTELOC0_CSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1713 #define _USART_ROUTELOC0_CSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1714 #define _USART_ROUTELOC0_CSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1715 #define _USART_ROUTELOC0_CSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1716 #define _USART_ROUTELOC0_CSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1717 #define _USART_ROUTELOC0_CSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1718 #define _USART_ROUTELOC0_CSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1719 #define _USART_ROUTELOC0_CSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1720 #define _USART_ROUTELOC0_CSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1721 #define _USART_ROUTELOC0_CSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1722 #define _USART_ROUTELOC0_CSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1723 #define _USART_ROUTELOC0_CSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1724 #define _USART_ROUTELOC0_CSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1725 #define _USART_ROUTELOC0_CSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1726 #define _USART_ROUTELOC0_CSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1727 #define _USART_ROUTELOC0_CSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1728 #define USART_ROUTELOC0_CSLOC_LOC0 (_USART_ROUTELOC0_CSLOC_LOC0 << 16) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1729 #define USART_ROUTELOC0_CSLOC_DEFAULT (_USART_ROUTELOC0_CSLOC_DEFAULT << 16) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1730 #define USART_ROUTELOC0_CSLOC_LOC1 (_USART_ROUTELOC0_CSLOC_LOC1 << 16) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1731 #define USART_ROUTELOC0_CSLOC_LOC2 (_USART_ROUTELOC0_CSLOC_LOC2 << 16) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1732 #define USART_ROUTELOC0_CSLOC_LOC3 (_USART_ROUTELOC0_CSLOC_LOC3 << 16) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1733 #define USART_ROUTELOC0_CSLOC_LOC4 (_USART_ROUTELOC0_CSLOC_LOC4 << 16) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1734 #define USART_ROUTELOC0_CSLOC_LOC5 (_USART_ROUTELOC0_CSLOC_LOC5 << 16) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1735 #define USART_ROUTELOC0_CSLOC_LOC6 (_USART_ROUTELOC0_CSLOC_LOC6 << 16) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1736 #define USART_ROUTELOC0_CSLOC_LOC7 (_USART_ROUTELOC0_CSLOC_LOC7 << 16) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1737 #define USART_ROUTELOC0_CSLOC_LOC8 (_USART_ROUTELOC0_CSLOC_LOC8 << 16) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1738 #define USART_ROUTELOC0_CSLOC_LOC9 (_USART_ROUTELOC0_CSLOC_LOC9 << 16) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1739 #define USART_ROUTELOC0_CSLOC_LOC10 (_USART_ROUTELOC0_CSLOC_LOC10 << 16) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1740 #define USART_ROUTELOC0_CSLOC_LOC11 (_USART_ROUTELOC0_CSLOC_LOC11 << 16) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1741 #define USART_ROUTELOC0_CSLOC_LOC12 (_USART_ROUTELOC0_CSLOC_LOC12 << 16) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1742 #define USART_ROUTELOC0_CSLOC_LOC13 (_USART_ROUTELOC0_CSLOC_LOC13 << 16) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1743 #define USART_ROUTELOC0_CSLOC_LOC14 (_USART_ROUTELOC0_CSLOC_LOC14 << 16) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1744 #define USART_ROUTELOC0_CSLOC_LOC15 (_USART_ROUTELOC0_CSLOC_LOC15 << 16) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1745 #define USART_ROUTELOC0_CSLOC_LOC16 (_USART_ROUTELOC0_CSLOC_LOC16 << 16) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1746 #define USART_ROUTELOC0_CSLOC_LOC17 (_USART_ROUTELOC0_CSLOC_LOC17 << 16) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1747 #define USART_ROUTELOC0_CSLOC_LOC18 (_USART_ROUTELOC0_CSLOC_LOC18 << 16) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1748 #define USART_ROUTELOC0_CSLOC_LOC19 (_USART_ROUTELOC0_CSLOC_LOC19 << 16) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1749 #define USART_ROUTELOC0_CSLOC_LOC20 (_USART_ROUTELOC0_CSLOC_LOC20 << 16) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1750 #define USART_ROUTELOC0_CSLOC_LOC21 (_USART_ROUTELOC0_CSLOC_LOC21 << 16) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1751 #define USART_ROUTELOC0_CSLOC_LOC22 (_USART_ROUTELOC0_CSLOC_LOC22 << 16) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1752 #define USART_ROUTELOC0_CSLOC_LOC23 (_USART_ROUTELOC0_CSLOC_LOC23 << 16) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1753 #define USART_ROUTELOC0_CSLOC_LOC24 (_USART_ROUTELOC0_CSLOC_LOC24 << 16) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1754 #define USART_ROUTELOC0_CSLOC_LOC25 (_USART_ROUTELOC0_CSLOC_LOC25 << 16) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1755 #define USART_ROUTELOC0_CSLOC_LOC26 (_USART_ROUTELOC0_CSLOC_LOC26 << 16) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1756 #define USART_ROUTELOC0_CSLOC_LOC27 (_USART_ROUTELOC0_CSLOC_LOC27 << 16) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1757 #define USART_ROUTELOC0_CSLOC_LOC28 (_USART_ROUTELOC0_CSLOC_LOC28 << 16) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1758 #define USART_ROUTELOC0_CSLOC_LOC29 (_USART_ROUTELOC0_CSLOC_LOC29 << 16) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1759 #define USART_ROUTELOC0_CSLOC_LOC30 (_USART_ROUTELOC0_CSLOC_LOC30 << 16) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1760 #define USART_ROUTELOC0_CSLOC_LOC31 (_USART_ROUTELOC0_CSLOC_LOC31 << 16) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1761 #define _USART_ROUTELOC0_CLKLOC_SHIFT 24 /**< Shift value for USART_CLKLOC */
<> 153:fa9ff456f731 1762 #define _USART_ROUTELOC0_CLKLOC_MASK 0x1F000000UL /**< Bit mask for USART_CLKLOC */
<> 153:fa9ff456f731 1763 #define _USART_ROUTELOC0_CLKLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1764 #define _USART_ROUTELOC0_CLKLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1765 #define _USART_ROUTELOC0_CLKLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1766 #define _USART_ROUTELOC0_CLKLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1767 #define _USART_ROUTELOC0_CLKLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1768 #define _USART_ROUTELOC0_CLKLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1769 #define _USART_ROUTELOC0_CLKLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1770 #define _USART_ROUTELOC0_CLKLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1771 #define _USART_ROUTELOC0_CLKLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1772 #define _USART_ROUTELOC0_CLKLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1773 #define _USART_ROUTELOC0_CLKLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1774 #define _USART_ROUTELOC0_CLKLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1775 #define _USART_ROUTELOC0_CLKLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1776 #define _USART_ROUTELOC0_CLKLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1777 #define _USART_ROUTELOC0_CLKLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1778 #define _USART_ROUTELOC0_CLKLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1779 #define _USART_ROUTELOC0_CLKLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1780 #define _USART_ROUTELOC0_CLKLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1781 #define _USART_ROUTELOC0_CLKLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1782 #define _USART_ROUTELOC0_CLKLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1783 #define _USART_ROUTELOC0_CLKLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1784 #define _USART_ROUTELOC0_CLKLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1785 #define _USART_ROUTELOC0_CLKLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1786 #define _USART_ROUTELOC0_CLKLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1787 #define _USART_ROUTELOC0_CLKLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1788 #define _USART_ROUTELOC0_CLKLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1789 #define _USART_ROUTELOC0_CLKLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1790 #define _USART_ROUTELOC0_CLKLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1791 #define _USART_ROUTELOC0_CLKLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1792 #define _USART_ROUTELOC0_CLKLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1793 #define _USART_ROUTELOC0_CLKLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1794 #define _USART_ROUTELOC0_CLKLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1795 #define _USART_ROUTELOC0_CLKLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1796 #define USART_ROUTELOC0_CLKLOC_LOC0 (_USART_ROUTELOC0_CLKLOC_LOC0 << 24) /**< Shifted mode LOC0 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1797 #define USART_ROUTELOC0_CLKLOC_DEFAULT (_USART_ROUTELOC0_CLKLOC_DEFAULT << 24) /**< Shifted mode DEFAULT for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1798 #define USART_ROUTELOC0_CLKLOC_LOC1 (_USART_ROUTELOC0_CLKLOC_LOC1 << 24) /**< Shifted mode LOC1 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1799 #define USART_ROUTELOC0_CLKLOC_LOC2 (_USART_ROUTELOC0_CLKLOC_LOC2 << 24) /**< Shifted mode LOC2 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1800 #define USART_ROUTELOC0_CLKLOC_LOC3 (_USART_ROUTELOC0_CLKLOC_LOC3 << 24) /**< Shifted mode LOC3 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1801 #define USART_ROUTELOC0_CLKLOC_LOC4 (_USART_ROUTELOC0_CLKLOC_LOC4 << 24) /**< Shifted mode LOC4 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1802 #define USART_ROUTELOC0_CLKLOC_LOC5 (_USART_ROUTELOC0_CLKLOC_LOC5 << 24) /**< Shifted mode LOC5 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1803 #define USART_ROUTELOC0_CLKLOC_LOC6 (_USART_ROUTELOC0_CLKLOC_LOC6 << 24) /**< Shifted mode LOC6 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1804 #define USART_ROUTELOC0_CLKLOC_LOC7 (_USART_ROUTELOC0_CLKLOC_LOC7 << 24) /**< Shifted mode LOC7 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1805 #define USART_ROUTELOC0_CLKLOC_LOC8 (_USART_ROUTELOC0_CLKLOC_LOC8 << 24) /**< Shifted mode LOC8 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1806 #define USART_ROUTELOC0_CLKLOC_LOC9 (_USART_ROUTELOC0_CLKLOC_LOC9 << 24) /**< Shifted mode LOC9 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1807 #define USART_ROUTELOC0_CLKLOC_LOC10 (_USART_ROUTELOC0_CLKLOC_LOC10 << 24) /**< Shifted mode LOC10 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1808 #define USART_ROUTELOC0_CLKLOC_LOC11 (_USART_ROUTELOC0_CLKLOC_LOC11 << 24) /**< Shifted mode LOC11 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1809 #define USART_ROUTELOC0_CLKLOC_LOC12 (_USART_ROUTELOC0_CLKLOC_LOC12 << 24) /**< Shifted mode LOC12 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1810 #define USART_ROUTELOC0_CLKLOC_LOC13 (_USART_ROUTELOC0_CLKLOC_LOC13 << 24) /**< Shifted mode LOC13 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1811 #define USART_ROUTELOC0_CLKLOC_LOC14 (_USART_ROUTELOC0_CLKLOC_LOC14 << 24) /**< Shifted mode LOC14 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1812 #define USART_ROUTELOC0_CLKLOC_LOC15 (_USART_ROUTELOC0_CLKLOC_LOC15 << 24) /**< Shifted mode LOC15 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1813 #define USART_ROUTELOC0_CLKLOC_LOC16 (_USART_ROUTELOC0_CLKLOC_LOC16 << 24) /**< Shifted mode LOC16 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1814 #define USART_ROUTELOC0_CLKLOC_LOC17 (_USART_ROUTELOC0_CLKLOC_LOC17 << 24) /**< Shifted mode LOC17 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1815 #define USART_ROUTELOC0_CLKLOC_LOC18 (_USART_ROUTELOC0_CLKLOC_LOC18 << 24) /**< Shifted mode LOC18 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1816 #define USART_ROUTELOC0_CLKLOC_LOC19 (_USART_ROUTELOC0_CLKLOC_LOC19 << 24) /**< Shifted mode LOC19 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1817 #define USART_ROUTELOC0_CLKLOC_LOC20 (_USART_ROUTELOC0_CLKLOC_LOC20 << 24) /**< Shifted mode LOC20 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1818 #define USART_ROUTELOC0_CLKLOC_LOC21 (_USART_ROUTELOC0_CLKLOC_LOC21 << 24) /**< Shifted mode LOC21 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1819 #define USART_ROUTELOC0_CLKLOC_LOC22 (_USART_ROUTELOC0_CLKLOC_LOC22 << 24) /**< Shifted mode LOC22 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1820 #define USART_ROUTELOC0_CLKLOC_LOC23 (_USART_ROUTELOC0_CLKLOC_LOC23 << 24) /**< Shifted mode LOC23 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1821 #define USART_ROUTELOC0_CLKLOC_LOC24 (_USART_ROUTELOC0_CLKLOC_LOC24 << 24) /**< Shifted mode LOC24 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1822 #define USART_ROUTELOC0_CLKLOC_LOC25 (_USART_ROUTELOC0_CLKLOC_LOC25 << 24) /**< Shifted mode LOC25 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1823 #define USART_ROUTELOC0_CLKLOC_LOC26 (_USART_ROUTELOC0_CLKLOC_LOC26 << 24) /**< Shifted mode LOC26 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1824 #define USART_ROUTELOC0_CLKLOC_LOC27 (_USART_ROUTELOC0_CLKLOC_LOC27 << 24) /**< Shifted mode LOC27 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1825 #define USART_ROUTELOC0_CLKLOC_LOC28 (_USART_ROUTELOC0_CLKLOC_LOC28 << 24) /**< Shifted mode LOC28 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1826 #define USART_ROUTELOC0_CLKLOC_LOC29 (_USART_ROUTELOC0_CLKLOC_LOC29 << 24) /**< Shifted mode LOC29 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1827 #define USART_ROUTELOC0_CLKLOC_LOC30 (_USART_ROUTELOC0_CLKLOC_LOC30 << 24) /**< Shifted mode LOC30 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1828 #define USART_ROUTELOC0_CLKLOC_LOC31 (_USART_ROUTELOC0_CLKLOC_LOC31 << 24) /**< Shifted mode LOC31 for USART_ROUTELOC0 */
<> 153:fa9ff456f731 1829
<> 153:fa9ff456f731 1830 /* Bit fields for USART ROUTELOC1 */
<> 153:fa9ff456f731 1831 #define _USART_ROUTELOC1_RESETVALUE 0x00000000UL /**< Default value for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1832 #define _USART_ROUTELOC1_MASK 0x00001F1FUL /**< Mask for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1833 #define _USART_ROUTELOC1_CTSLOC_SHIFT 0 /**< Shift value for USART_CTSLOC */
<> 153:fa9ff456f731 1834 #define _USART_ROUTELOC1_CTSLOC_MASK 0x1FUL /**< Bit mask for USART_CTSLOC */
<> 153:fa9ff456f731 1835 #define _USART_ROUTELOC1_CTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1836 #define _USART_ROUTELOC1_CTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1837 #define _USART_ROUTELOC1_CTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1838 #define _USART_ROUTELOC1_CTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1839 #define _USART_ROUTELOC1_CTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1840 #define _USART_ROUTELOC1_CTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1841 #define _USART_ROUTELOC1_CTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1842 #define _USART_ROUTELOC1_CTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1843 #define _USART_ROUTELOC1_CTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1844 #define _USART_ROUTELOC1_CTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1845 #define _USART_ROUTELOC1_CTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1846 #define _USART_ROUTELOC1_CTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1847 #define _USART_ROUTELOC1_CTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1848 #define _USART_ROUTELOC1_CTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1849 #define _USART_ROUTELOC1_CTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1850 #define _USART_ROUTELOC1_CTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1851 #define _USART_ROUTELOC1_CTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1852 #define _USART_ROUTELOC1_CTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1853 #define _USART_ROUTELOC1_CTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1854 #define _USART_ROUTELOC1_CTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1855 #define _USART_ROUTELOC1_CTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1856 #define _USART_ROUTELOC1_CTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1857 #define _USART_ROUTELOC1_CTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1858 #define _USART_ROUTELOC1_CTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1859 #define _USART_ROUTELOC1_CTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1860 #define _USART_ROUTELOC1_CTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1861 #define _USART_ROUTELOC1_CTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1862 #define _USART_ROUTELOC1_CTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1863 #define _USART_ROUTELOC1_CTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1864 #define _USART_ROUTELOC1_CTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1865 #define _USART_ROUTELOC1_CTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1866 #define _USART_ROUTELOC1_CTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1867 #define _USART_ROUTELOC1_CTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1868 #define USART_ROUTELOC1_CTSLOC_LOC0 (_USART_ROUTELOC1_CTSLOC_LOC0 << 0) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1869 #define USART_ROUTELOC1_CTSLOC_DEFAULT (_USART_ROUTELOC1_CTSLOC_DEFAULT << 0) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1870 #define USART_ROUTELOC1_CTSLOC_LOC1 (_USART_ROUTELOC1_CTSLOC_LOC1 << 0) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1871 #define USART_ROUTELOC1_CTSLOC_LOC2 (_USART_ROUTELOC1_CTSLOC_LOC2 << 0) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1872 #define USART_ROUTELOC1_CTSLOC_LOC3 (_USART_ROUTELOC1_CTSLOC_LOC3 << 0) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1873 #define USART_ROUTELOC1_CTSLOC_LOC4 (_USART_ROUTELOC1_CTSLOC_LOC4 << 0) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1874 #define USART_ROUTELOC1_CTSLOC_LOC5 (_USART_ROUTELOC1_CTSLOC_LOC5 << 0) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1875 #define USART_ROUTELOC1_CTSLOC_LOC6 (_USART_ROUTELOC1_CTSLOC_LOC6 << 0) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1876 #define USART_ROUTELOC1_CTSLOC_LOC7 (_USART_ROUTELOC1_CTSLOC_LOC7 << 0) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1877 #define USART_ROUTELOC1_CTSLOC_LOC8 (_USART_ROUTELOC1_CTSLOC_LOC8 << 0) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1878 #define USART_ROUTELOC1_CTSLOC_LOC9 (_USART_ROUTELOC1_CTSLOC_LOC9 << 0) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1879 #define USART_ROUTELOC1_CTSLOC_LOC10 (_USART_ROUTELOC1_CTSLOC_LOC10 << 0) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1880 #define USART_ROUTELOC1_CTSLOC_LOC11 (_USART_ROUTELOC1_CTSLOC_LOC11 << 0) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1881 #define USART_ROUTELOC1_CTSLOC_LOC12 (_USART_ROUTELOC1_CTSLOC_LOC12 << 0) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1882 #define USART_ROUTELOC1_CTSLOC_LOC13 (_USART_ROUTELOC1_CTSLOC_LOC13 << 0) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1883 #define USART_ROUTELOC1_CTSLOC_LOC14 (_USART_ROUTELOC1_CTSLOC_LOC14 << 0) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1884 #define USART_ROUTELOC1_CTSLOC_LOC15 (_USART_ROUTELOC1_CTSLOC_LOC15 << 0) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1885 #define USART_ROUTELOC1_CTSLOC_LOC16 (_USART_ROUTELOC1_CTSLOC_LOC16 << 0) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1886 #define USART_ROUTELOC1_CTSLOC_LOC17 (_USART_ROUTELOC1_CTSLOC_LOC17 << 0) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1887 #define USART_ROUTELOC1_CTSLOC_LOC18 (_USART_ROUTELOC1_CTSLOC_LOC18 << 0) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1888 #define USART_ROUTELOC1_CTSLOC_LOC19 (_USART_ROUTELOC1_CTSLOC_LOC19 << 0) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1889 #define USART_ROUTELOC1_CTSLOC_LOC20 (_USART_ROUTELOC1_CTSLOC_LOC20 << 0) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1890 #define USART_ROUTELOC1_CTSLOC_LOC21 (_USART_ROUTELOC1_CTSLOC_LOC21 << 0) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1891 #define USART_ROUTELOC1_CTSLOC_LOC22 (_USART_ROUTELOC1_CTSLOC_LOC22 << 0) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1892 #define USART_ROUTELOC1_CTSLOC_LOC23 (_USART_ROUTELOC1_CTSLOC_LOC23 << 0) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1893 #define USART_ROUTELOC1_CTSLOC_LOC24 (_USART_ROUTELOC1_CTSLOC_LOC24 << 0) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1894 #define USART_ROUTELOC1_CTSLOC_LOC25 (_USART_ROUTELOC1_CTSLOC_LOC25 << 0) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1895 #define USART_ROUTELOC1_CTSLOC_LOC26 (_USART_ROUTELOC1_CTSLOC_LOC26 << 0) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1896 #define USART_ROUTELOC1_CTSLOC_LOC27 (_USART_ROUTELOC1_CTSLOC_LOC27 << 0) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1897 #define USART_ROUTELOC1_CTSLOC_LOC28 (_USART_ROUTELOC1_CTSLOC_LOC28 << 0) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1898 #define USART_ROUTELOC1_CTSLOC_LOC29 (_USART_ROUTELOC1_CTSLOC_LOC29 << 0) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1899 #define USART_ROUTELOC1_CTSLOC_LOC30 (_USART_ROUTELOC1_CTSLOC_LOC30 << 0) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1900 #define USART_ROUTELOC1_CTSLOC_LOC31 (_USART_ROUTELOC1_CTSLOC_LOC31 << 0) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1901 #define _USART_ROUTELOC1_RTSLOC_SHIFT 8 /**< Shift value for USART_RTSLOC */
<> 153:fa9ff456f731 1902 #define _USART_ROUTELOC1_RTSLOC_MASK 0x1F00UL /**< Bit mask for USART_RTSLOC */
<> 153:fa9ff456f731 1903 #define _USART_ROUTELOC1_RTSLOC_LOC0 0x00000000UL /**< Mode LOC0 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1904 #define _USART_ROUTELOC1_RTSLOC_DEFAULT 0x00000000UL /**< Mode DEFAULT for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1905 #define _USART_ROUTELOC1_RTSLOC_LOC1 0x00000001UL /**< Mode LOC1 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1906 #define _USART_ROUTELOC1_RTSLOC_LOC2 0x00000002UL /**< Mode LOC2 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1907 #define _USART_ROUTELOC1_RTSLOC_LOC3 0x00000003UL /**< Mode LOC3 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1908 #define _USART_ROUTELOC1_RTSLOC_LOC4 0x00000004UL /**< Mode LOC4 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1909 #define _USART_ROUTELOC1_RTSLOC_LOC5 0x00000005UL /**< Mode LOC5 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1910 #define _USART_ROUTELOC1_RTSLOC_LOC6 0x00000006UL /**< Mode LOC6 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1911 #define _USART_ROUTELOC1_RTSLOC_LOC7 0x00000007UL /**< Mode LOC7 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1912 #define _USART_ROUTELOC1_RTSLOC_LOC8 0x00000008UL /**< Mode LOC8 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1913 #define _USART_ROUTELOC1_RTSLOC_LOC9 0x00000009UL /**< Mode LOC9 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1914 #define _USART_ROUTELOC1_RTSLOC_LOC10 0x0000000AUL /**< Mode LOC10 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1915 #define _USART_ROUTELOC1_RTSLOC_LOC11 0x0000000BUL /**< Mode LOC11 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1916 #define _USART_ROUTELOC1_RTSLOC_LOC12 0x0000000CUL /**< Mode LOC12 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1917 #define _USART_ROUTELOC1_RTSLOC_LOC13 0x0000000DUL /**< Mode LOC13 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1918 #define _USART_ROUTELOC1_RTSLOC_LOC14 0x0000000EUL /**< Mode LOC14 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1919 #define _USART_ROUTELOC1_RTSLOC_LOC15 0x0000000FUL /**< Mode LOC15 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1920 #define _USART_ROUTELOC1_RTSLOC_LOC16 0x00000010UL /**< Mode LOC16 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1921 #define _USART_ROUTELOC1_RTSLOC_LOC17 0x00000011UL /**< Mode LOC17 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1922 #define _USART_ROUTELOC1_RTSLOC_LOC18 0x00000012UL /**< Mode LOC18 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1923 #define _USART_ROUTELOC1_RTSLOC_LOC19 0x00000013UL /**< Mode LOC19 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1924 #define _USART_ROUTELOC1_RTSLOC_LOC20 0x00000014UL /**< Mode LOC20 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1925 #define _USART_ROUTELOC1_RTSLOC_LOC21 0x00000015UL /**< Mode LOC21 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1926 #define _USART_ROUTELOC1_RTSLOC_LOC22 0x00000016UL /**< Mode LOC22 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1927 #define _USART_ROUTELOC1_RTSLOC_LOC23 0x00000017UL /**< Mode LOC23 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1928 #define _USART_ROUTELOC1_RTSLOC_LOC24 0x00000018UL /**< Mode LOC24 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1929 #define _USART_ROUTELOC1_RTSLOC_LOC25 0x00000019UL /**< Mode LOC25 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1930 #define _USART_ROUTELOC1_RTSLOC_LOC26 0x0000001AUL /**< Mode LOC26 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1931 #define _USART_ROUTELOC1_RTSLOC_LOC27 0x0000001BUL /**< Mode LOC27 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1932 #define _USART_ROUTELOC1_RTSLOC_LOC28 0x0000001CUL /**< Mode LOC28 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1933 #define _USART_ROUTELOC1_RTSLOC_LOC29 0x0000001DUL /**< Mode LOC29 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1934 #define _USART_ROUTELOC1_RTSLOC_LOC30 0x0000001EUL /**< Mode LOC30 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1935 #define _USART_ROUTELOC1_RTSLOC_LOC31 0x0000001FUL /**< Mode LOC31 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1936 #define USART_ROUTELOC1_RTSLOC_LOC0 (_USART_ROUTELOC1_RTSLOC_LOC0 << 8) /**< Shifted mode LOC0 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1937 #define USART_ROUTELOC1_RTSLOC_DEFAULT (_USART_ROUTELOC1_RTSLOC_DEFAULT << 8) /**< Shifted mode DEFAULT for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1938 #define USART_ROUTELOC1_RTSLOC_LOC1 (_USART_ROUTELOC1_RTSLOC_LOC1 << 8) /**< Shifted mode LOC1 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1939 #define USART_ROUTELOC1_RTSLOC_LOC2 (_USART_ROUTELOC1_RTSLOC_LOC2 << 8) /**< Shifted mode LOC2 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1940 #define USART_ROUTELOC1_RTSLOC_LOC3 (_USART_ROUTELOC1_RTSLOC_LOC3 << 8) /**< Shifted mode LOC3 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1941 #define USART_ROUTELOC1_RTSLOC_LOC4 (_USART_ROUTELOC1_RTSLOC_LOC4 << 8) /**< Shifted mode LOC4 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1942 #define USART_ROUTELOC1_RTSLOC_LOC5 (_USART_ROUTELOC1_RTSLOC_LOC5 << 8) /**< Shifted mode LOC5 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1943 #define USART_ROUTELOC1_RTSLOC_LOC6 (_USART_ROUTELOC1_RTSLOC_LOC6 << 8) /**< Shifted mode LOC6 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1944 #define USART_ROUTELOC1_RTSLOC_LOC7 (_USART_ROUTELOC1_RTSLOC_LOC7 << 8) /**< Shifted mode LOC7 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1945 #define USART_ROUTELOC1_RTSLOC_LOC8 (_USART_ROUTELOC1_RTSLOC_LOC8 << 8) /**< Shifted mode LOC8 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1946 #define USART_ROUTELOC1_RTSLOC_LOC9 (_USART_ROUTELOC1_RTSLOC_LOC9 << 8) /**< Shifted mode LOC9 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1947 #define USART_ROUTELOC1_RTSLOC_LOC10 (_USART_ROUTELOC1_RTSLOC_LOC10 << 8) /**< Shifted mode LOC10 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1948 #define USART_ROUTELOC1_RTSLOC_LOC11 (_USART_ROUTELOC1_RTSLOC_LOC11 << 8) /**< Shifted mode LOC11 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1949 #define USART_ROUTELOC1_RTSLOC_LOC12 (_USART_ROUTELOC1_RTSLOC_LOC12 << 8) /**< Shifted mode LOC12 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1950 #define USART_ROUTELOC1_RTSLOC_LOC13 (_USART_ROUTELOC1_RTSLOC_LOC13 << 8) /**< Shifted mode LOC13 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1951 #define USART_ROUTELOC1_RTSLOC_LOC14 (_USART_ROUTELOC1_RTSLOC_LOC14 << 8) /**< Shifted mode LOC14 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1952 #define USART_ROUTELOC1_RTSLOC_LOC15 (_USART_ROUTELOC1_RTSLOC_LOC15 << 8) /**< Shifted mode LOC15 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1953 #define USART_ROUTELOC1_RTSLOC_LOC16 (_USART_ROUTELOC1_RTSLOC_LOC16 << 8) /**< Shifted mode LOC16 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1954 #define USART_ROUTELOC1_RTSLOC_LOC17 (_USART_ROUTELOC1_RTSLOC_LOC17 << 8) /**< Shifted mode LOC17 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1955 #define USART_ROUTELOC1_RTSLOC_LOC18 (_USART_ROUTELOC1_RTSLOC_LOC18 << 8) /**< Shifted mode LOC18 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1956 #define USART_ROUTELOC1_RTSLOC_LOC19 (_USART_ROUTELOC1_RTSLOC_LOC19 << 8) /**< Shifted mode LOC19 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1957 #define USART_ROUTELOC1_RTSLOC_LOC20 (_USART_ROUTELOC1_RTSLOC_LOC20 << 8) /**< Shifted mode LOC20 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1958 #define USART_ROUTELOC1_RTSLOC_LOC21 (_USART_ROUTELOC1_RTSLOC_LOC21 << 8) /**< Shifted mode LOC21 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1959 #define USART_ROUTELOC1_RTSLOC_LOC22 (_USART_ROUTELOC1_RTSLOC_LOC22 << 8) /**< Shifted mode LOC22 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1960 #define USART_ROUTELOC1_RTSLOC_LOC23 (_USART_ROUTELOC1_RTSLOC_LOC23 << 8) /**< Shifted mode LOC23 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1961 #define USART_ROUTELOC1_RTSLOC_LOC24 (_USART_ROUTELOC1_RTSLOC_LOC24 << 8) /**< Shifted mode LOC24 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1962 #define USART_ROUTELOC1_RTSLOC_LOC25 (_USART_ROUTELOC1_RTSLOC_LOC25 << 8) /**< Shifted mode LOC25 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1963 #define USART_ROUTELOC1_RTSLOC_LOC26 (_USART_ROUTELOC1_RTSLOC_LOC26 << 8) /**< Shifted mode LOC26 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1964 #define USART_ROUTELOC1_RTSLOC_LOC27 (_USART_ROUTELOC1_RTSLOC_LOC27 << 8) /**< Shifted mode LOC27 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1965 #define USART_ROUTELOC1_RTSLOC_LOC28 (_USART_ROUTELOC1_RTSLOC_LOC28 << 8) /**< Shifted mode LOC28 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1966 #define USART_ROUTELOC1_RTSLOC_LOC29 (_USART_ROUTELOC1_RTSLOC_LOC29 << 8) /**< Shifted mode LOC29 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1967 #define USART_ROUTELOC1_RTSLOC_LOC30 (_USART_ROUTELOC1_RTSLOC_LOC30 << 8) /**< Shifted mode LOC30 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1968 #define USART_ROUTELOC1_RTSLOC_LOC31 (_USART_ROUTELOC1_RTSLOC_LOC31 << 8) /**< Shifted mode LOC31 for USART_ROUTELOC1 */
<> 153:fa9ff456f731 1969
<> 153:fa9ff456f731 1970 /** @} End of group EFR32MG1P_USART */
<> 153:fa9ff456f731 1971 /** @} End of group Parts */
<> 153:fa9ff456f731 1972