mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/efr32mg1p_dmareq.h@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
153:fa9ff456f731 
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 153:fa9ff456f731 1 /**************************************************************************//**
<> 153:fa9ff456f731 2 * @file efr32mg1p_dmareq.h
<> 153:fa9ff456f731 3 * @brief EFR32MG1P_DMAREQ register and bit field definitions
<> 161:2cc1468da177 4 * @version 5.1.2
<> 153:fa9ff456f731 5 ******************************************************************************
<> 153:fa9ff456f731 6 * @section License
<> 161:2cc1468da177 7 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 153:fa9ff456f731 8 ******************************************************************************
<> 153:fa9ff456f731 9 *
<> 153:fa9ff456f731 10 * Permission is granted to anyone to use this software for any purpose,
<> 153:fa9ff456f731 11 * including commercial applications, and to alter it and redistribute it
<> 153:fa9ff456f731 12 * freely, subject to the following restrictions:
<> 153:fa9ff456f731 13 *
<> 153:fa9ff456f731 14 * 1. The origin of this software must not be misrepresented; you must not
<> 153:fa9ff456f731 15 * claim that you wrote the original software.@n
<> 153:fa9ff456f731 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 153:fa9ff456f731 17 * misrepresented as being the original software.@n
<> 153:fa9ff456f731 18 * 3. This notice may not be removed or altered from any source distribution.
<> 153:fa9ff456f731 19 *
<> 153:fa9ff456f731 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 153:fa9ff456f731 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 153:fa9ff456f731 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 153:fa9ff456f731 23 * kind, including, but not limited to, any implied warranties of
<> 153:fa9ff456f731 24 * merchantability or fitness for any particular purpose or warranties against
<> 153:fa9ff456f731 25 * infringement of any proprietary rights of a third party.
<> 153:fa9ff456f731 26 *
<> 153:fa9ff456f731 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 153:fa9ff456f731 28 * incidental, or special damages, or any other relief, or for any claim by
<> 153:fa9ff456f731 29 * any third party, arising from your use of this Software.
<> 153:fa9ff456f731 30 *
<> 153:fa9ff456f731 31 *****************************************************************************/
<> 153:fa9ff456f731 32 /**************************************************************************//**
<> 153:fa9ff456f731 33 * @addtogroup Parts
<> 153:fa9ff456f731 34 * @{
<> 153:fa9ff456f731 35 ******************************************************************************/
<> 153:fa9ff456f731 36
<> 153:fa9ff456f731 37 /**************************************************************************//**
<> 153:fa9ff456f731 38 * @defgroup EFR32MG1P_DMAREQ_BitFields
<> 153:fa9ff456f731 39 * @{
<> 153:fa9ff456f731 40 *****************************************************************************/
<> 153:fa9ff456f731 41 #define DMAREQ_PRS_REQ0 ((1 << 16) + 0) /**< DMA channel select for PRS_REQ0 */
<> 153:fa9ff456f731 42 #define DMAREQ_PRS_REQ1 ((1 << 16) + 1) /**< DMA channel select for PRS_REQ1 */
<> 153:fa9ff456f731 43 #define DMAREQ_ADC0_SINGLE ((8 << 16) + 0) /**< DMA channel select for ADC0_SINGLE */
<> 153:fa9ff456f731 44 #define DMAREQ_ADC0_SCAN ((8 << 16) + 1) /**< DMA channel select for ADC0_SCAN */
<> 153:fa9ff456f731 45 #define DMAREQ_USART0_RXDATAV ((12 << 16) + 0) /**< DMA channel select for USART0_RXDATAV */
<> 153:fa9ff456f731 46 #define DMAREQ_USART0_TXBL ((12 << 16) + 1) /**< DMA channel select for USART0_TXBL */
<> 153:fa9ff456f731 47 #define DMAREQ_USART0_TXEMPTY ((12 << 16) + 2) /**< DMA channel select for USART0_TXEMPTY */
<> 153:fa9ff456f731 48 #define DMAREQ_USART1_RXDATAV ((13 << 16) + 0) /**< DMA channel select for USART1_RXDATAV */
<> 153:fa9ff456f731 49 #define DMAREQ_USART1_TXBL ((13 << 16) + 1) /**< DMA channel select for USART1_TXBL */
<> 153:fa9ff456f731 50 #define DMAREQ_USART1_TXEMPTY ((13 << 16) + 2) /**< DMA channel select for USART1_TXEMPTY */
<> 153:fa9ff456f731 51 #define DMAREQ_USART1_RXDATAVRIGHT ((13 << 16) + 3) /**< DMA channel select for USART1_RXDATAVRIGHT */
<> 153:fa9ff456f731 52 #define DMAREQ_USART1_TXBLRIGHT ((13 << 16) + 4) /**< DMA channel select for USART1_TXBLRIGHT */
<> 153:fa9ff456f731 53 #define DMAREQ_LEUART0_RXDATAV ((16 << 16) + 0) /**< DMA channel select for LEUART0_RXDATAV */
<> 153:fa9ff456f731 54 #define DMAREQ_LEUART0_TXBL ((16 << 16) + 1) /**< DMA channel select for LEUART0_TXBL */
<> 153:fa9ff456f731 55 #define DMAREQ_LEUART0_TXEMPTY ((16 << 16) + 2) /**< DMA channel select for LEUART0_TXEMPTY */
<> 153:fa9ff456f731 56 #define DMAREQ_I2C0_RXDATAV ((20 << 16) + 0) /**< DMA channel select for I2C0_RXDATAV */
<> 153:fa9ff456f731 57 #define DMAREQ_I2C0_TXBL ((20 << 16) + 1) /**< DMA channel select for I2C0_TXBL */
<> 153:fa9ff456f731 58 #define DMAREQ_TIMER0_UFOF ((24 << 16) + 0) /**< DMA channel select for TIMER0_UFOF */
<> 153:fa9ff456f731 59 #define DMAREQ_TIMER0_CC0 ((24 << 16) + 1) /**< DMA channel select for TIMER0_CC0 */
<> 153:fa9ff456f731 60 #define DMAREQ_TIMER0_CC1 ((24 << 16) + 2) /**< DMA channel select for TIMER0_CC1 */
<> 153:fa9ff456f731 61 #define DMAREQ_TIMER0_CC2 ((24 << 16) + 3) /**< DMA channel select for TIMER0_CC2 */
<> 153:fa9ff456f731 62 #define DMAREQ_TIMER1_UFOF ((25 << 16) + 0) /**< DMA channel select for TIMER1_UFOF */
<> 153:fa9ff456f731 63 #define DMAREQ_TIMER1_CC0 ((25 << 16) + 1) /**< DMA channel select for TIMER1_CC0 */
<> 153:fa9ff456f731 64 #define DMAREQ_TIMER1_CC1 ((25 << 16) + 2) /**< DMA channel select for TIMER1_CC1 */
<> 153:fa9ff456f731 65 #define DMAREQ_TIMER1_CC2 ((25 << 16) + 3) /**< DMA channel select for TIMER1_CC2 */
<> 153:fa9ff456f731 66 #define DMAREQ_TIMER1_CC3 ((25 << 16) + 4) /**< DMA channel select for TIMER1_CC3 */
<> 153:fa9ff456f731 67 #define DMAREQ_MSC_WDATA ((48 << 16) + 0) /**< DMA channel select for MSC_WDATA */
<> 153:fa9ff456f731 68 #define DMAREQ_CRYPTO_DATA0WR ((49 << 16) + 0) /**< DMA channel select for CRYPTO_DATA0WR */
<> 153:fa9ff456f731 69 #define DMAREQ_CRYPTO_DATA0XWR ((49 << 16) + 1) /**< DMA channel select for CRYPTO_DATA0XWR */
<> 153:fa9ff456f731 70 #define DMAREQ_CRYPTO_DATA0RD ((49 << 16) + 2) /**< DMA channel select for CRYPTO_DATA0RD */
<> 153:fa9ff456f731 71 #define DMAREQ_CRYPTO_DATA1WR ((49 << 16) + 3) /**< DMA channel select for CRYPTO_DATA1WR */
<> 153:fa9ff456f731 72 #define DMAREQ_CRYPTO_DATA1RD ((49 << 16) + 4) /**< DMA channel select for CRYPTO_DATA1RD */
<> 153:fa9ff456f731 73
<> 153:fa9ff456f731 74 /** @} End of group EFR32MG1P_DMAREQ */
<> 153:fa9ff456f731 75 /** @} End of group Parts */
<> 153:fa9ff456f731 76