mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_iwdg.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_ll_iwdg.h@144:ef7eb2e8f9f7
Child:
167:e84263d55307
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l4xx_ll_iwdg.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.1
<> 144:ef7eb2e8f9f7 6 * @date 31-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of IWDG LL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L4xx_LL_IWDG_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L4xx_LL_IWDG_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l4xx.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L4xx_LL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 #if defined(IWDG)
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /** @defgroup IWDG_LL IWDG
<> 144:ef7eb2e8f9f7 56 * @{
<> 144:ef7eb2e8f9f7 57 */
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /* Private types -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 60 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /* Private constants ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 63 /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 #define LL_IWDG_KEY_RELOAD ((uint32_t)0x0000AAAAU) /*!< IWDG Reload Counter Enable */
<> 144:ef7eb2e8f9f7 68 #define LL_IWDG_KEY_ENABLE ((uint32_t)0x0000CCCCU) /*!< IWDG Peripheral Enable */
<> 144:ef7eb2e8f9f7 69 #define LL_IWDG_KEY_WR_ACCESS_ENABLE ((uint32_t)0x00005555U) /*!< IWDG KR Write Access Enable */
<> 144:ef7eb2e8f9f7 70 #define LL_IWDG_KEY_WR_ACCESS_DISABLE ((uint32_t)0x00000000U) /*!< IWDG KR Write Access Disable */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 /**
<> 144:ef7eb2e8f9f7 73 * @}
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 79 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 80 /** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
<> 144:ef7eb2e8f9f7 85 * @brief Flags defines which can be used with LL_IWDG_ReadReg function
<> 144:ef7eb2e8f9f7 86 * @{
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88 #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
<> 144:ef7eb2e8f9f7 89 #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
<> 144:ef7eb2e8f9f7 90 #define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /**
<> 144:ef7eb2e8f9f7 93 * @}
<> 144:ef7eb2e8f9f7 94 */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 #define LL_IWDG_PRESCALER_4 ((uint32_t)0x00000000U) /*!< Divider by 4 */
<> 144:ef7eb2e8f9f7 100 #define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
<> 144:ef7eb2e8f9f7 101 #define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
<> 144:ef7eb2e8f9f7 102 #define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
<> 144:ef7eb2e8f9f7 103 #define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
<> 144:ef7eb2e8f9f7 104 #define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
<> 144:ef7eb2e8f9f7 105 #define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
<> 144:ef7eb2e8f9f7 106 /**
<> 144:ef7eb2e8f9f7 107 * @}
<> 144:ef7eb2e8f9f7 108 */
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 /**
<> 144:ef7eb2e8f9f7 111 * @}
<> 144:ef7eb2e8f9f7 112 */
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
<> 144:ef7eb2e8f9f7 116 * @{
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
<> 144:ef7eb2e8f9f7 120 * @{
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /**
<> 144:ef7eb2e8f9f7 124 * @brief Write a value in IWDG register
<> 144:ef7eb2e8f9f7 125 * @param __INSTANCE__ IWDG Instance
<> 144:ef7eb2e8f9f7 126 * @param __REG__ Register to be written
<> 144:ef7eb2e8f9f7 127 * @param __VALUE__ Value to be written in the register
<> 144:ef7eb2e8f9f7 128 * @retval None
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130 #define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /**
<> 144:ef7eb2e8f9f7 133 * @brief Read a value in IWDG register
<> 144:ef7eb2e8f9f7 134 * @param __INSTANCE__ IWDG Instance
<> 144:ef7eb2e8f9f7 135 * @param __REG__ Register to be read
<> 144:ef7eb2e8f9f7 136 * @retval Register value
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138 #define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 144:ef7eb2e8f9f7 139 /**
<> 144:ef7eb2e8f9f7 140 * @}
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 144:ef7eb2e8f9f7 145 */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 149 /** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /** @defgroup IWDG_LL_EF_Configuration Configuration
<> 144:ef7eb2e8f9f7 153 * @{
<> 144:ef7eb2e8f9f7 154 */
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @brief Start the Independent Watchdog
<> 144:ef7eb2e8f9f7 158 * @note Except if the hardware watchdog option is selected
<> 144:ef7eb2e8f9f7 159 * @rmtoll KR KEY LL_IWDG_Enable
<> 144:ef7eb2e8f9f7 160 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 161 * @retval None
<> 144:ef7eb2e8f9f7 162 */
<> 144:ef7eb2e8f9f7 163 __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 164 {
<> 144:ef7eb2e8f9f7 165 WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE);
<> 144:ef7eb2e8f9f7 166 }
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Reloads IWDG counter with value defined in the reload register
<> 144:ef7eb2e8f9f7 170 * @rmtoll KR KEY LL_IWDG_ReloadCounter
<> 144:ef7eb2e8f9f7 171 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 172 * @retval None
<> 144:ef7eb2e8f9f7 173 */
<> 144:ef7eb2e8f9f7 174 __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 175 {
<> 144:ef7eb2e8f9f7 176 WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD);
<> 144:ef7eb2e8f9f7 177 }
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /**
<> 144:ef7eb2e8f9f7 180 * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
<> 144:ef7eb2e8f9f7 181 * @rmtoll KR KEY LL_IWDG_EnableWriteAccess
<> 144:ef7eb2e8f9f7 182 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 183 * @retval None
<> 144:ef7eb2e8f9f7 184 */
<> 144:ef7eb2e8f9f7 185 __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 186 {
<> 144:ef7eb2e8f9f7 187 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
<> 144:ef7eb2e8f9f7 188 }
<> 144:ef7eb2e8f9f7 189
<> 144:ef7eb2e8f9f7 190 /**
<> 144:ef7eb2e8f9f7 191 * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
<> 144:ef7eb2e8f9f7 192 * @rmtoll KR KEY LL_IWDG_DisableWriteAccess
<> 144:ef7eb2e8f9f7 193 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 194 * @retval None
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196 __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 197 {
<> 144:ef7eb2e8f9f7 198 WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
<> 144:ef7eb2e8f9f7 199 }
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @brief Select the prescaler of the IWDG
<> 144:ef7eb2e8f9f7 203 * @rmtoll PR PR LL_IWDG_SetPrescaler
<> 144:ef7eb2e8f9f7 204 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 205 * @param Prescaler This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 206 * @arg @ref LL_IWDG_PRESCALER_4
<> 144:ef7eb2e8f9f7 207 * @arg @ref LL_IWDG_PRESCALER_8
<> 144:ef7eb2e8f9f7 208 * @arg @ref LL_IWDG_PRESCALER_16
<> 144:ef7eb2e8f9f7 209 * @arg @ref LL_IWDG_PRESCALER_32
<> 144:ef7eb2e8f9f7 210 * @arg @ref LL_IWDG_PRESCALER_64
<> 144:ef7eb2e8f9f7 211 * @arg @ref LL_IWDG_PRESCALER_128
<> 144:ef7eb2e8f9f7 212 * @arg @ref LL_IWDG_PRESCALER_256
<> 144:ef7eb2e8f9f7 213 * @retval None
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
<> 144:ef7eb2e8f9f7 216 {
<> 144:ef7eb2e8f9f7 217 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
<> 144:ef7eb2e8f9f7 218 }
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /**
<> 144:ef7eb2e8f9f7 221 * @brief Get the selected prescaler of the IWDG
<> 144:ef7eb2e8f9f7 222 * @rmtoll PR PR LL_IWDG_GetPrescaler
<> 144:ef7eb2e8f9f7 223 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 224 * @retval Returned value can be one of the following values:
<> 144:ef7eb2e8f9f7 225 * @arg @ref LL_IWDG_PRESCALER_4
<> 144:ef7eb2e8f9f7 226 * @arg @ref LL_IWDG_PRESCALER_8
<> 144:ef7eb2e8f9f7 227 * @arg @ref LL_IWDG_PRESCALER_16
<> 144:ef7eb2e8f9f7 228 * @arg @ref LL_IWDG_PRESCALER_32
<> 144:ef7eb2e8f9f7 229 * @arg @ref LL_IWDG_PRESCALER_64
<> 144:ef7eb2e8f9f7 230 * @arg @ref LL_IWDG_PRESCALER_128
<> 144:ef7eb2e8f9f7 231 * @arg @ref LL_IWDG_PRESCALER_256
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 return (uint32_t)(READ_REG(IWDGx->PR));
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 /**
<> 144:ef7eb2e8f9f7 239 * @brief Specify the IWDG down-counter reload value
<> 144:ef7eb2e8f9f7 240 * @rmtoll RLR RL LL_IWDG_SetReloadCounter
<> 144:ef7eb2e8f9f7 241 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 242 * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
<> 144:ef7eb2e8f9f7 243 * @retval None
<> 144:ef7eb2e8f9f7 244 */
<> 144:ef7eb2e8f9f7 245 __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
<> 144:ef7eb2e8f9f7 246 {
<> 144:ef7eb2e8f9f7 247 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
<> 144:ef7eb2e8f9f7 248 }
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /**
<> 144:ef7eb2e8f9f7 251 * @brief Get the specified IWDG down-counter reload value
<> 144:ef7eb2e8f9f7 252 * @rmtoll RLR RL LL_IWDG_GetReloadCounter
<> 144:ef7eb2e8f9f7 253 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 254 * @retval Value between Min_Data=0 and Max_Data=0x0FFF
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 return (uint32_t)(READ_REG(IWDGx->RLR));
<> 144:ef7eb2e8f9f7 259 }
<> 144:ef7eb2e8f9f7 260
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @brief Specify high limit of the window value to be compared to the down-counter.
<> 144:ef7eb2e8f9f7 263 * @rmtoll WINR WIN LL_IWDG_SetWindow
<> 144:ef7eb2e8f9f7 264 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 265 * @param Window Value between Min_Data=0 and Max_Data=0x0FFF
<> 144:ef7eb2e8f9f7 266 * @retval None
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268 __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @brief Get the high limit of the window value specified.
<> 144:ef7eb2e8f9f7 275 * @rmtoll WINR WIN LL_IWDG_GetWindow
<> 144:ef7eb2e8f9f7 276 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 277 * @retval Value between Min_Data=0 and Max_Data=0x0FFF
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279 __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 280 {
<> 144:ef7eb2e8f9f7 281 return (uint32_t)(READ_REG(IWDGx->WINR));
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @}
<> 144:ef7eb2e8f9f7 286 */
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 /** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
<> 144:ef7eb2e8f9f7 289 * @{
<> 144:ef7eb2e8f9f7 290 */
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * @brief Check if flag Prescaler Value Update is set or not
<> 144:ef7eb2e8f9f7 294 * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
<> 144:ef7eb2e8f9f7 295 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 296 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 297 */
<> 144:ef7eb2e8f9f7 298 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 299 {
<> 144:ef7eb2e8f9f7 300 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU));
<> 144:ef7eb2e8f9f7 301 }
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /**
<> 144:ef7eb2e8f9f7 304 * @brief Check if flag Reload Value Update is set or not
<> 144:ef7eb2e8f9f7 305 * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
<> 144:ef7eb2e8f9f7 306 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 307 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 308 */
<> 144:ef7eb2e8f9f7 309 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 310 {
<> 144:ef7eb2e8f9f7 311 return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU));
<> 144:ef7eb2e8f9f7 312 }
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /**
<> 144:ef7eb2e8f9f7 315 * @brief Check if flag Window Value Update is set or not
<> 144:ef7eb2e8f9f7 316 * @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
<> 144:ef7eb2e8f9f7 317 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 318 * @retval State of bit (1 or 0).
<> 144:ef7eb2e8f9f7 319 */
<> 144:ef7eb2e8f9f7 320 __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 return (READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU));
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
<> 144:ef7eb2e8f9f7 327 * @rmtoll SR PVU LL_IWDG_IsReady\n
<> 144:ef7eb2e8f9f7 328 * SR WVU LL_IWDG_IsReady\n
<> 144:ef7eb2e8f9f7 329 * SR RVU LL_IWDG_IsReady
<> 144:ef7eb2e8f9f7 330 * @param IWDGx IWDG Instance
<> 144:ef7eb2e8f9f7 331 * @retval State of bits (1 or 0).
<> 144:ef7eb2e8f9f7 332 */
<> 144:ef7eb2e8f9f7 333 __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
<> 144:ef7eb2e8f9f7 334 {
<> 144:ef7eb2e8f9f7 335 return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U);
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 /**
<> 144:ef7eb2e8f9f7 339 * @}
<> 144:ef7eb2e8f9f7 340 */
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 /**
<> 144:ef7eb2e8f9f7 344 * @}
<> 144:ef7eb2e8f9f7 345 */
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /**
<> 144:ef7eb2e8f9f7 348 * @}
<> 144:ef7eb2e8f9f7 349 */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351 #endif /* IWDG) */
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @}
<> 144:ef7eb2e8f9f7 355 */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 358 }
<> 144:ef7eb2e8f9f7 359 #endif
<> 144:ef7eb2e8f9f7 360
<> 144:ef7eb2e8f9f7 361 #endif /* __STM32L4xx_LL_IWDG_H */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/