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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_ll_bus.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
184:08ed48f1de7f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_ll_bus.h
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief Header file of BUS LL module.
<> 149:156823d33999 8
<> 149:156823d33999 9 @verbatim
<> 149:156823d33999 10 ##### RCC Limitations #####
<> 149:156823d33999 11 ==============================================================================
<> 149:156823d33999 12 [..]
<> 149:156823d33999 13 A delay between an RCC peripheral clock enable and the effective peripheral
<> 149:156823d33999 14 enabling should be taken into account in order to manage the peripheral read/write
<> 149:156823d33999 15 from/to registers.
<> 149:156823d33999 16 (+) This delay depends on the peripheral mapping.
<> 149:156823d33999 17 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 149:156823d33999 18
<> 149:156823d33999 19 [..]
<> 149:156823d33999 20 Workarounds:
<> 149:156823d33999 21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 149:156823d33999 22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
<> 149:156823d33999 23
<> 149:156823d33999 24 @endverbatim
<> 149:156823d33999 25 ******************************************************************************
<> 149:156823d33999 26 * @attention
<> 149:156823d33999 27 *
<> 149:156823d33999 28 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 29 *
<> 149:156823d33999 30 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 31 * are permitted provided that the following conditions are met:
<> 149:156823d33999 32 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 33 * this list of conditions and the following disclaimer.
<> 149:156823d33999 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 35 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 36 * and/or other materials provided with the distribution.
<> 149:156823d33999 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 38 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 39 * without specific prior written permission.
<> 149:156823d33999 40 *
<> 149:156823d33999 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 51 *
<> 149:156823d33999 52 ******************************************************************************
<> 149:156823d33999 53 */
<> 149:156823d33999 54
<> 149:156823d33999 55 /* Define to prevent recursive inclusion -------------------------------------*/
<> 149:156823d33999 56 #ifndef __STM32L1xx_LL_BUS_H
<> 149:156823d33999 57 #define __STM32L1xx_LL_BUS_H
<> 149:156823d33999 58
<> 149:156823d33999 59 #ifdef __cplusplus
<> 149:156823d33999 60 extern "C" {
<> 149:156823d33999 61 #endif
<> 149:156823d33999 62
<> 149:156823d33999 63 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 64 #include "stm32l1xx.h"
<> 149:156823d33999 65
<> 149:156823d33999 66 /** @addtogroup STM32L1xx_LL_Driver
<> 149:156823d33999 67 * @{
<> 149:156823d33999 68 */
<> 149:156823d33999 69
<> 149:156823d33999 70 #if defined(RCC)
<> 149:156823d33999 71
<> 149:156823d33999 72 /** @defgroup BUS_LL BUS
<> 149:156823d33999 73 * @{
<> 149:156823d33999 74 */
<> 149:156823d33999 75
<> 149:156823d33999 76 /* Private types -------------------------------------------------------------*/
<> 149:156823d33999 77 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 78
<> 149:156823d33999 79 /* Private constants ---------------------------------------------------------*/
<> 149:156823d33999 80
<> 149:156823d33999 81 /* Private macros ------------------------------------------------------------*/
<> 149:156823d33999 82
<> 149:156823d33999 83 /* Exported types ------------------------------------------------------------*/
<> 149:156823d33999 84 /* Exported constants --------------------------------------------------------*/
<> 149:156823d33999 85 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
<> 149:156823d33999 86 * @{
<> 149:156823d33999 87 */
<> 149:156823d33999 88
<> 149:156823d33999 89 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
<> 149:156823d33999 90 * @{
<> 149:156823d33999 91 */
<> 149:156823d33999 92 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 149:156823d33999 93 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHBENR_GPIOAEN
<> 149:156823d33999 94 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHBENR_GPIOBEN
<> 149:156823d33999 95 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHBENR_GPIOCEN
<> 149:156823d33999 96 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHBENR_GPIODEN
<> 149:156823d33999 97 #if defined(GPIOE)
<> 149:156823d33999 98 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHBENR_GPIOEEN
<> 149:156823d33999 99 #endif/*GPIOE*/
<> 149:156823d33999 100 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHBENR_GPIOHEN
<> 149:156823d33999 101 #if defined(GPIOF)
<> 149:156823d33999 102 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHBENR_GPIOFEN
<> 149:156823d33999 103 #endif/*GPIOF*/
<> 149:156823d33999 104 #if defined(GPIOG)
<> 149:156823d33999 105 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHBENR_GPIOGEN
<> 149:156823d33999 106 #endif/*GPIOG*/
<> 149:156823d33999 107 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBLPENR_SRAMLPEN
<> 149:156823d33999 108 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
<> 149:156823d33999 109 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN
<> 149:156823d33999 110 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN
<> 149:156823d33999 111 #if defined(DMA2)
<> 149:156823d33999 112 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN
<> 149:156823d33999 113 #endif/*DMA2*/
<> 149:156823d33999 114 #if defined(AES)
<> 149:156823d33999 115 #define LL_AHB1_GRP1_PERIPH_CRYP RCC_AHBENR_AESEN
<> 149:156823d33999 116 #endif/*AES*/
<> 149:156823d33999 117 #if defined(FSMC_Bank1)
<> 149:156823d33999 118 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN
<> 149:156823d33999 119 #endif/*FSMC_Bank1*/
<> 149:156823d33999 120 /**
<> 149:156823d33999 121 * @}
<> 149:156823d33999 122 */
<> 149:156823d33999 123
<> 149:156823d33999 124 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
<> 149:156823d33999 125 * @{
<> 149:156823d33999 126 */
<> 149:156823d33999 127 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 149:156823d33999 128 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
<> 149:156823d33999 129 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
<> 149:156823d33999 130 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
<> 149:156823d33999 131 #if defined(TIM5)
<> 149:156823d33999 132 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
<> 149:156823d33999 133 #endif /*TIM5*/
<> 149:156823d33999 134 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
<> 149:156823d33999 135 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
<> 149:156823d33999 136 #if defined(LCD)
<> 149:156823d33999 137 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR_LCDEN
<> 149:156823d33999 138 #endif /*LCD*/
<> 149:156823d33999 139 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
<> 149:156823d33999 140 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
<> 149:156823d33999 141 #if defined(SPI3)
<> 149:156823d33999 142 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
<> 149:156823d33999 143 #endif /*SPI3*/
<> 149:156823d33999 144 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
<> 149:156823d33999 145 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
<> 149:156823d33999 146 #if defined(UART4)
<> 149:156823d33999 147 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
<> 149:156823d33999 148 #endif /*UART4*/
<> 149:156823d33999 149 #if defined(UART5)
<> 149:156823d33999 150 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
<> 149:156823d33999 151 #endif /*UART5*/
<> 149:156823d33999 152 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
<> 149:156823d33999 153 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
<> 149:156823d33999 154 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN
<> 149:156823d33999 155 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
<> 149:156823d33999 156 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
<> 149:156823d33999 157 #define LL_APB1_GRP1_PERIPH_COMP RCC_APB1ENR_COMPEN
<> 149:156823d33999 158 #if defined(OPAMP)
<> 149:156823d33999 159 /* Note: Peripherals COMP and OPAMP share the same clock domain */
<> 149:156823d33999 160 #define LL_APB1_GRP1_PERIPH_OPAMP LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 161 #endif
<> 149:156823d33999 162 /**
<> 149:156823d33999 163 * @}
<> 149:156823d33999 164 */
<> 149:156823d33999 165
<> 149:156823d33999 166 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
<> 149:156823d33999 167 * @{
<> 149:156823d33999 168 */
<> 149:156823d33999 169 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU
<> 149:156823d33999 170 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
<> 149:156823d33999 171 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
<> 149:156823d33999 172 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
<> 149:156823d33999 173 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
<> 149:156823d33999 174 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
<> 149:156823d33999 175 #if defined(SDIO)
<> 149:156823d33999 176 #define LL_APB2_GRP1_PERIPH_SDIO RCC_APB2ENR_SDIOEN
<> 149:156823d33999 177 #endif /*SDIO*/
<> 149:156823d33999 178 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
<> 149:156823d33999 179 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
<> 149:156823d33999 180 /**
<> 149:156823d33999 181 * @}
<> 149:156823d33999 182 */
<> 149:156823d33999 183
<> 149:156823d33999 184 /**
<> 149:156823d33999 185 * @}
<> 149:156823d33999 186 */
<> 149:156823d33999 187
<> 149:156823d33999 188 /* Exported macro ------------------------------------------------------------*/
<> 149:156823d33999 189
<> 149:156823d33999 190 /* Exported functions --------------------------------------------------------*/
<> 149:156823d33999 191 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
<> 149:156823d33999 192 * @{
<> 149:156823d33999 193 */
<> 149:156823d33999 194
<> 149:156823d33999 195 /** @defgroup BUS_LL_EF_AHB1 AHB1
<> 149:156823d33999 196 * @{
<> 149:156823d33999 197 */
<> 149:156823d33999 198
<> 149:156823d33999 199 /**
<> 149:156823d33999 200 * @brief Enable AHB1 peripherals clock.
<> 149:156823d33999 201 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 202 * AHBENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 203 * AHBENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 204 * AHBENR GPIODEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 205 * AHBENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 206 * AHBENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 207 * AHBENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 208 * AHBENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 209 * AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 210 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 211 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 212 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 213 * AHBENR AESEN LL_AHB1_GRP1_EnableClock\n
<> 149:156823d33999 214 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock
<> 149:156823d33999 215 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 216 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 217 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 218 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 219 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 220 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 221 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 222 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 223 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 224 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 225 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 226 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 227 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 228 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 229 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 230 *
<> 149:156823d33999 231 * (*) value not defined in all devices.
<> 149:156823d33999 232 * @retval None
<> 149:156823d33999 233 */
<> 149:156823d33999 234 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
<> 149:156823d33999 235 {
<> 149:156823d33999 236 __IO uint32_t tmpreg;
<> 149:156823d33999 237 SET_BIT(RCC->AHBENR, Periphs);
<> 149:156823d33999 238 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 239 tmpreg = READ_BIT(RCC->AHBENR, Periphs);
<> 149:156823d33999 240 (void)tmpreg;
<> 149:156823d33999 241 }
<> 149:156823d33999 242
<> 149:156823d33999 243 /**
<> 149:156823d33999 244 * @brief Check if AHB1 peripheral clock is enabled or not
<> 149:156823d33999 245 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 246 * AHBENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 247 * AHBENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 248 * AHBENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 249 * AHBENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 250 * AHBENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 251 * AHBENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 252 * AHBENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 253 * AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 254 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 255 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 256 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 257 * AHBENR AESEN LL_AHB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 258 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock
<> 149:156823d33999 259 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 260 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 261 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 262 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 263 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 264 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 265 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 266 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 267 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 268 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 269 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 270 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 271 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 272 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 273 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 274 *
<> 149:156823d33999 275 * (*) value not defined in all devices.
<> 149:156823d33999 276 * @retval State of Periphs (1 or 0).
<> 149:156823d33999 277 */
<> 149:156823d33999 278 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 149:156823d33999 279 {
<> 149:156823d33999 280 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs);
<> 149:156823d33999 281 }
<> 149:156823d33999 282
<> 149:156823d33999 283 /**
<> 149:156823d33999 284 * @brief Disable AHB1 peripherals clock.
<> 149:156823d33999 285 * @rmtoll AHBENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 286 * AHBENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 287 * AHBENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 288 * AHBENR GPIODEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 289 * AHBENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 290 * AHBENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 291 * AHBENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 292 * AHBENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 293 * AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 294 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 295 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 296 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 297 * AHBENR AESEN LL_AHB1_GRP1_DisableClock\n
<> 149:156823d33999 298 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock
<> 149:156823d33999 299 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 300 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 301 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 302 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 303 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 304 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 306 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 307 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 308 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 309 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 310 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 311 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 312 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 313 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 314 *
<> 149:156823d33999 315 * (*) value not defined in all devices.
<> 149:156823d33999 316 * @retval None
<> 149:156823d33999 317 */
<> 149:156823d33999 318 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
<> 149:156823d33999 319 {
<> 149:156823d33999 320 CLEAR_BIT(RCC->AHBENR, Periphs);
<> 149:156823d33999 321 }
<> 149:156823d33999 322
<> 149:156823d33999 323 /**
<> 149:156823d33999 324 * @brief Force AHB1 peripherals reset.
<> 149:156823d33999 325 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 326 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 327 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 328 * AHBRSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 329 * AHBRSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 330 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 331 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 332 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 333 * AHBRSTR CRCRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 334 * AHBRSTR FLITFRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 335 * AHBRSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 336 * AHBRSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 337 * AHBRSTR AESRST LL_AHB1_GRP1_ForceReset\n
<> 149:156823d33999 338 * AHBRSTR FSMCRST LL_AHB1_GRP1_ForceReset
<> 149:156823d33999 339 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 340 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 149:156823d33999 341 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 342 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 343 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 344 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 345 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 346 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 347 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 348 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 349 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 350 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 351 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 352 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 353 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 354 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 355 *
<> 149:156823d33999 356 * (*) value not defined in all devices.
<> 149:156823d33999 357 * @retval None
<> 149:156823d33999 358 */
<> 149:156823d33999 359 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
<> 149:156823d33999 360 {
<> 149:156823d33999 361 SET_BIT(RCC->AHBRSTR, Periphs);
<> 149:156823d33999 362 }
<> 149:156823d33999 363
<> 149:156823d33999 364 /**
<> 149:156823d33999 365 * @brief Release AHB1 peripherals reset.
<> 149:156823d33999 366 * @rmtoll AHBRSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 367 * AHBRSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 368 * AHBRSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 369 * AHBRSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 370 * AHBRSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 371 * AHBRSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 372 * AHBRSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 373 * AHBRSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 374 * AHBRSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 375 * AHBRSTR FLITFRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 376 * AHBRSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 377 * AHBRSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 378 * AHBRSTR AESRST LL_AHB1_GRP1_ReleaseReset\n
<> 149:156823d33999 379 * AHBRSTR FSMCRST LL_AHB1_GRP1_ReleaseReset
<> 149:156823d33999 380 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 381 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
<> 149:156823d33999 382 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 383 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 384 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 385 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 386 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 387 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 388 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 389 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 390 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 391 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 393 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 395 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 396 *
<> 149:156823d33999 397 * (*) value not defined in all devices.
<> 149:156823d33999 398 * @retval None
<> 149:156823d33999 399 */
<> 149:156823d33999 400 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 149:156823d33999 401 {
<> 149:156823d33999 402 CLEAR_BIT(RCC->AHBRSTR, Periphs);
<> 149:156823d33999 403 }
<> 149:156823d33999 404
<> 149:156823d33999 405 /**
<> 149:156823d33999 406 * @brief Enable AHB1 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 407 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 408 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 409 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 410 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 411 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 412 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 413 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 414 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 415 * AHBLPENR CRCLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 416 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 417 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 418 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 419 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 420 * AHBLPENR AESLPEN LL_AHB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 421 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_EnableClockSleep
<> 149:156823d33999 422 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 423 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 424 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 425 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 429 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 430 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 431 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 432 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 433 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 149:156823d33999 434 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 435 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 436 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 437 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 438 *
<> 149:156823d33999 439 * (*) value not defined in all devices.
<> 149:156823d33999 440 * @retval None
<> 149:156823d33999 441 */
<> 149:156823d33999 442 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)
<> 149:156823d33999 443 {
<> 149:156823d33999 444 __IO uint32_t tmpreg;
<> 149:156823d33999 445 SET_BIT(RCC->AHBLPENR, Periphs);
<> 149:156823d33999 446 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 447 tmpreg = READ_BIT(RCC->AHBLPENR, Periphs);
<> 149:156823d33999 448 (void)tmpreg;
<> 149:156823d33999 449 }
<> 149:156823d33999 450
<> 149:156823d33999 451 /**
<> 149:156823d33999 452 * @brief Disable AHB1 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 453 * @rmtoll AHBLPENR GPIOALPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 454 * AHBLPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 455 * AHBLPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 456 * AHBLPENR GPIODLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 457 * AHBLPENR GPIOELPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 458 * AHBLPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 459 * AHBLPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 460 * AHBLPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 461 * AHBLPENR CRCLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 462 * AHBLPENR FLITFLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 463 * AHBLPENR SRAMLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 464 * AHBLPENR DMA1LPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 465 * AHBLPENR DMA2LPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 466 * AHBLPENR AESLPEN LL_AHB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 467 * AHBLPENR FSMCLPEN LL_AHB1_GRP1_DisableClockSleep
<> 149:156823d33999 468 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 469 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
<> 149:156823d33999 470 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
<> 149:156823d33999 471 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
<> 149:156823d33999 472 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
<> 149:156823d33999 473 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE (*)
<> 149:156823d33999 474 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
<> 149:156823d33999 475 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF (*)
<> 149:156823d33999 476 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG (*)
<> 149:156823d33999 477 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
<> 149:156823d33999 478 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
<> 149:156823d33999 479 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
<> 149:156823d33999 480 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
<> 149:156823d33999 481 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*)
<> 149:156823d33999 482 * @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)
<> 149:156823d33999 483 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*)
<> 149:156823d33999 484 *
<> 149:156823d33999 485 * (*) value not defined in all devices.
<> 149:156823d33999 486 * @retval None
<> 149:156823d33999 487 */
<> 149:156823d33999 488 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)
<> 149:156823d33999 489 {
<> 149:156823d33999 490 CLEAR_BIT(RCC->AHBLPENR, Periphs);
<> 149:156823d33999 491 }
<> 149:156823d33999 492
<> 149:156823d33999 493 /**
<> 149:156823d33999 494 * @}
<> 149:156823d33999 495 */
<> 149:156823d33999 496
<> 149:156823d33999 497 /** @defgroup BUS_LL_EF_APB1 APB1
<> 149:156823d33999 498 * @{
<> 149:156823d33999 499 */
<> 149:156823d33999 500
<> 149:156823d33999 501 /**
<> 149:156823d33999 502 * @brief Enable APB1 peripherals clock.
<> 149:156823d33999 503 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 504 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 505 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 506 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 507 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 508 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 509 * APB1ENR LCDEN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 510 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 511 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 512 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 513 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 514 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 515 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 516 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 517 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 518 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 519 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 520 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 521 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
<> 149:156823d33999 522 * APB1ENR COMPEN LL_APB1_GRP1_EnableClock
<> 149:156823d33999 523 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 524 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 525 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 526 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 527 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 528 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 529 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 530 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 531 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 532 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 533 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 534 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 535 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 536 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 537 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 538 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 539 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 540 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 541 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 542 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 543 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 544 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 545 *
<> 149:156823d33999 546 * (*) value not defined in all devices.
<> 149:156823d33999 547 * @retval None
<> 149:156823d33999 548 */
<> 149:156823d33999 549 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
<> 149:156823d33999 550 {
<> 149:156823d33999 551 __IO uint32_t tmpreg;
<> 149:156823d33999 552 SET_BIT(RCC->APB1ENR, Periphs);
<> 149:156823d33999 553 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 554 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
<> 149:156823d33999 555 (void)tmpreg;
<> 149:156823d33999 556 }
<> 149:156823d33999 557
<> 149:156823d33999 558 /**
<> 149:156823d33999 559 * @brief Check if APB1 peripheral clock is enabled or not
<> 149:156823d33999 560 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 561 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 562 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 563 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 564 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 565 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 566 * APB1ENR LCDEN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 567 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 568 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 569 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 570 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 571 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 572 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 573 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 574 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 575 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 576 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 577 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 578 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
<> 149:156823d33999 579 * APB1ENR COMPEN LL_APB1_GRP1_IsEnabledClock
<> 149:156823d33999 580 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 581 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 582 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 583 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 584 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 585 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 586 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 587 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 588 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 589 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 590 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 591 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 592 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 593 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 594 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 595 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 596 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 597 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 598 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 599 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 600 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 601 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 602 *
<> 149:156823d33999 603 * (*) value not defined in all devices.
<> 149:156823d33999 604 * @retval State of Periphs (1 or 0).
<> 149:156823d33999 605 */
<> 149:156823d33999 606 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
<> 149:156823d33999 607 {
<> 149:156823d33999 608 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
<> 149:156823d33999 609 }
<> 149:156823d33999 610
<> 149:156823d33999 611 /**
<> 149:156823d33999 612 * @brief Disable APB1 peripherals clock.
<> 149:156823d33999 613 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 614 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 615 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 616 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 617 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 618 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 619 * APB1ENR LCDEN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 620 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 621 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 622 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 623 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 624 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 625 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 626 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 627 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 628 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 629 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 630 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 631 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
<> 149:156823d33999 632 * APB1ENR COMPEN LL_APB1_GRP1_DisableClock
<> 149:156823d33999 633 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 634 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 635 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 636 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 637 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 638 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 639 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 640 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 641 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 642 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 643 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 644 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 645 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 646 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 647 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 648 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 649 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 650 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 651 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 652 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 653 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 654 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 655 *
<> 149:156823d33999 656 * (*) value not defined in all devices.
<> 149:156823d33999 657 * @retval None
<> 149:156823d33999 658 */
<> 149:156823d33999 659 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
<> 149:156823d33999 660 {
<> 149:156823d33999 661 CLEAR_BIT(RCC->APB1ENR, Periphs);
<> 149:156823d33999 662 }
<> 149:156823d33999 663
<> 149:156823d33999 664 /**
<> 149:156823d33999 665 * @brief Force APB1 peripherals reset.
<> 149:156823d33999 666 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 667 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 668 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 669 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 670 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 671 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 672 * APB1RSTR LCDRST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 673 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 674 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 675 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 676 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 677 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 678 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 679 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 680 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 681 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 682 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 683 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 684 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
<> 149:156823d33999 685 * APB1RSTR COMPRST LL_APB1_GRP1_ForceReset
<> 149:156823d33999 686 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 687 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 149:156823d33999 688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 691 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 692 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 693 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 694 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 695 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 696 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 697 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 698 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 699 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 700 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 701 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 702 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 703 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 704 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 705 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 706 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 707 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 708 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 709 *
<> 149:156823d33999 710 * (*) value not defined in all devices.
<> 149:156823d33999 711 * @retval None
<> 149:156823d33999 712 */
<> 149:156823d33999 713 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
<> 149:156823d33999 714 {
<> 149:156823d33999 715 SET_BIT(RCC->APB1RSTR, Periphs);
<> 149:156823d33999 716 }
<> 149:156823d33999 717
<> 149:156823d33999 718 /**
<> 149:156823d33999 719 * @brief Release APB1 peripherals reset.
<> 149:156823d33999 720 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 721 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 722 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 723 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 724 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 725 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 726 * APB1RSTR LCDRST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 727 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 728 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 729 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 730 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 731 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 732 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 733 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 734 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 735 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 736 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 737 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 738 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
<> 149:156823d33999 739 * APB1RSTR COMPRST LL_APB1_GRP1_ReleaseReset
<> 149:156823d33999 740 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 741 * @arg @ref LL_APB1_GRP1_PERIPH_ALL
<> 149:156823d33999 742 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 743 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 744 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 745 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 746 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 747 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 748 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 749 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 750 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 751 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 752 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 753 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 754 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 755 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 756 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 757 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 758 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 759 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 760 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 761 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 762 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 763 *
<> 149:156823d33999 764 * (*) value not defined in all devices.
<> 149:156823d33999 765 * @retval None
<> 149:156823d33999 766 */
<> 149:156823d33999 767 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
<> 149:156823d33999 768 {
<> 149:156823d33999 769 CLEAR_BIT(RCC->APB1RSTR, Periphs);
<> 149:156823d33999 770 }
<> 149:156823d33999 771
<> 149:156823d33999 772 /**
<> 149:156823d33999 773 * @brief Enable APB1 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 774 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 775 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 776 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 777 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 778 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 779 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 780 * APB1LPENR LCDLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 781 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 782 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 783 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 784 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 785 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 786 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 787 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 788 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 789 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 790 * APB1LPENR USBLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 791 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 792 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockSleep\n
<> 149:156823d33999 793 * APB1LPENR COMPLPEN LL_APB1_GRP1_EnableClockSleep
<> 149:156823d33999 794 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 795 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 796 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 797 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 798 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 799 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 800 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 801 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 802 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 803 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 804 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 805 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 806 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 807 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 808 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 809 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 810 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 811 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 812 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 813 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 814 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 815 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 816 *
<> 149:156823d33999 817 * (*) value not defined in all devices.
<> 149:156823d33999 818 * @retval None
<> 149:156823d33999 819 */
<> 149:156823d33999 820 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)
<> 149:156823d33999 821 {
<> 149:156823d33999 822 __IO uint32_t tmpreg;
<> 149:156823d33999 823 SET_BIT(RCC->APB1LPENR, Periphs);
<> 149:156823d33999 824 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 825 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
<> 149:156823d33999 826 (void)tmpreg;
<> 149:156823d33999 827 }
<> 149:156823d33999 828
<> 149:156823d33999 829 /**
<> 149:156823d33999 830 * @brief Disable APB1 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 831 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 832 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 833 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 834 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 835 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 836 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 837 * APB1LPENR LCDLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 838 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 839 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 840 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 841 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 842 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 843 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 844 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 845 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 846 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 847 * APB1LPENR USBLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 848 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 849 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockSleep\n
<> 149:156823d33999 850 * APB1LPENR COMPLPEN LL_APB1_GRP1_DisableClockSleep
<> 149:156823d33999 851 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 852 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
<> 149:156823d33999 853 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
<> 149:156823d33999 854 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
<> 149:156823d33999 855 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
<> 149:156823d33999 856 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
<> 149:156823d33999 857 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
<> 149:156823d33999 858 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
<> 149:156823d33999 859 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
<> 149:156823d33999 860 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
<> 149:156823d33999 861 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*)
<> 149:156823d33999 862 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
<> 149:156823d33999 863 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
<> 149:156823d33999 864 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
<> 149:156823d33999 865 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
<> 149:156823d33999 866 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
<> 149:156823d33999 867 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
<> 149:156823d33999 868 * @arg @ref LL_APB1_GRP1_PERIPH_USB
<> 149:156823d33999 869 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
<> 149:156823d33999 870 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
<> 149:156823d33999 871 * @arg @ref LL_APB1_GRP1_PERIPH_COMP
<> 149:156823d33999 872 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP (*)
<> 149:156823d33999 873 *
<> 149:156823d33999 874 * (*) value not defined in all devices.
<> 149:156823d33999 875 * @retval None
<> 149:156823d33999 876 */
<> 149:156823d33999 877 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)
<> 149:156823d33999 878 {
<> 149:156823d33999 879 CLEAR_BIT(RCC->APB1LPENR, Periphs);
<> 149:156823d33999 880 }
<> 149:156823d33999 881
<> 149:156823d33999 882 /**
<> 149:156823d33999 883 * @}
<> 149:156823d33999 884 */
<> 149:156823d33999 885
<> 149:156823d33999 886 /** @defgroup BUS_LL_EF_APB2 APB2
<> 149:156823d33999 887 * @{
<> 149:156823d33999 888 */
<> 149:156823d33999 889
<> 149:156823d33999 890 /**
<> 149:156823d33999 891 * @brief Enable APB2 peripherals clock.
<> 149:156823d33999 892 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 893 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 894 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 895 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 896 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 897 * APB2ENR SDIOEN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 898 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
<> 149:156823d33999 899 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock
<> 149:156823d33999 900 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 901 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 902 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 903 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 904 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 905 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 906 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 907 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 908 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 909 *
<> 149:156823d33999 910 * (*) value not defined in all devices.
<> 149:156823d33999 911 * @retval None
<> 149:156823d33999 912 */
<> 149:156823d33999 913 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
<> 149:156823d33999 914 {
<> 149:156823d33999 915 __IO uint32_t tmpreg;
<> 149:156823d33999 916 SET_BIT(RCC->APB2ENR, Periphs);
<> 149:156823d33999 917 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 918 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
<> 149:156823d33999 919 (void)tmpreg;
<> 149:156823d33999 920 }
<> 149:156823d33999 921
<> 149:156823d33999 922 /**
<> 149:156823d33999 923 * @brief Check if APB2 peripheral clock is enabled or not
<> 149:156823d33999 924 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 925 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 926 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 927 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 928 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 929 * APB2ENR SDIOEN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 930 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
<> 149:156823d33999 931 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock
<> 149:156823d33999 932 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 933 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 934 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 935 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 936 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 937 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 938 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 939 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 940 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 941 *
<> 149:156823d33999 942 * (*) value not defined in all devices.
<> 149:156823d33999 943 * @retval State of Periphs (1 or 0).
<> 149:156823d33999 944 */
<> 149:156823d33999 945 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
<> 149:156823d33999 946 {
<> 149:156823d33999 947 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
<> 149:156823d33999 948 }
<> 149:156823d33999 949
<> 149:156823d33999 950 /**
<> 149:156823d33999 951 * @brief Disable APB2 peripherals clock.
<> 149:156823d33999 952 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 953 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 954 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 955 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 956 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 957 * APB2ENR SDIOEN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 958 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
<> 149:156823d33999 959 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock
<> 149:156823d33999 960 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 961 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 962 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 963 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 964 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 965 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 966 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 967 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 968 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 969 *
<> 149:156823d33999 970 * (*) value not defined in all devices.
<> 149:156823d33999 971 * @retval None
<> 149:156823d33999 972 */
<> 149:156823d33999 973 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
<> 149:156823d33999 974 {
<> 149:156823d33999 975 CLEAR_BIT(RCC->APB2ENR, Periphs);
<> 149:156823d33999 976 }
<> 149:156823d33999 977
<> 149:156823d33999 978 /**
<> 149:156823d33999 979 * @brief Force APB2 peripherals reset.
<> 149:156823d33999 980 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 981 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 982 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 983 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 984 * APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 985 * APB2RSTR SDIORST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 986 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
<> 149:156823d33999 987 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset
<> 149:156823d33999 988 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 989 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
<> 149:156823d33999 990 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 991 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 992 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 993 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 994 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 995 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 996 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 997 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 998 *
<> 149:156823d33999 999 * (*) value not defined in all devices.
<> 149:156823d33999 1000 * @retval None
<> 149:156823d33999 1001 */
<> 149:156823d33999 1002 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
<> 149:156823d33999 1003 {
<> 149:156823d33999 1004 SET_BIT(RCC->APB2RSTR, Periphs);
<> 149:156823d33999 1005 }
<> 149:156823d33999 1006
<> 149:156823d33999 1007 /**
<> 149:156823d33999 1008 * @brief Release APB2 peripherals reset.
<> 149:156823d33999 1009 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1010 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1011 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1012 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1013 * APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1014 * APB2RSTR SDIORST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1015 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
<> 149:156823d33999 1016 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset
<> 149:156823d33999 1017 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 1018 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
<> 149:156823d33999 1019 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 1020 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 1021 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 1022 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 1023 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 1024 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 1025 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 1026 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 1027 *
<> 149:156823d33999 1028 * (*) value not defined in all devices.
<> 149:156823d33999 1029 * @retval None
<> 149:156823d33999 1030 */
<> 149:156823d33999 1031 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
<> 149:156823d33999 1032 {
<> 149:156823d33999 1033 CLEAR_BIT(RCC->APB2RSTR, Periphs);
<> 149:156823d33999 1034 }
<> 149:156823d33999 1035
<> 149:156823d33999 1036 /**
<> 149:156823d33999 1037 * @brief Enable APB2 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 1038 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1039 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1040 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1041 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1042 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1043 * APB2LPENR SDIOLPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1044 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockSleep\n
<> 149:156823d33999 1045 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockSleep
<> 149:156823d33999 1046 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 1047 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 1048 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 1049 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 1050 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 1051 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 1052 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 1053 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 1054 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 1055 *
<> 149:156823d33999 1056 * (*) value not defined in all devices.
<> 149:156823d33999 1057 * @retval None
<> 149:156823d33999 1058 */
<> 149:156823d33999 1059 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)
<> 149:156823d33999 1060 {
<> 149:156823d33999 1061 __IO uint32_t tmpreg;
<> 149:156823d33999 1062 SET_BIT(RCC->APB2LPENR, Periphs);
<> 149:156823d33999 1063 /* Delay after an RCC peripheral clock enabling */
<> 149:156823d33999 1064 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
<> 149:156823d33999 1065 (void)tmpreg;
<> 149:156823d33999 1066 }
<> 149:156823d33999 1067
<> 149:156823d33999 1068 /**
<> 149:156823d33999 1069 * @brief Disable APB2 peripherals clock during Low Power (Sleep) mode.
<> 149:156823d33999 1070 * @rmtoll APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1071 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1072 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1073 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1074 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1075 * APB2LPENR SDIOLPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1076 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockSleep\n
<> 149:156823d33999 1077 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockSleep
<> 149:156823d33999 1078 * @param Periphs This parameter can be a combination of the following values:
<> 149:156823d33999 1079 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
<> 149:156823d33999 1080 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
<> 149:156823d33999 1081 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
<> 149:156823d33999 1082 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
<> 149:156823d33999 1083 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
<> 149:156823d33999 1084 * @arg @ref LL_APB2_GRP1_PERIPH_SDIO (*)
<> 149:156823d33999 1085 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
<> 149:156823d33999 1086 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
<> 149:156823d33999 1087 *
<> 149:156823d33999 1088 * (*) value not defined in all devices.
<> 149:156823d33999 1089 * @retval None
<> 149:156823d33999 1090 */
<> 149:156823d33999 1091 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)
<> 149:156823d33999 1092 {
<> 149:156823d33999 1093 CLEAR_BIT(RCC->APB2LPENR, Periphs);
<> 149:156823d33999 1094 }
<> 149:156823d33999 1095
<> 149:156823d33999 1096 /**
<> 149:156823d33999 1097 * @}
<> 149:156823d33999 1098 */
<> 149:156823d33999 1099
<> 149:156823d33999 1100
<> 149:156823d33999 1101 /**
<> 149:156823d33999 1102 * @}
<> 149:156823d33999 1103 */
<> 149:156823d33999 1104
<> 149:156823d33999 1105 /**
<> 149:156823d33999 1106 * @}
<> 149:156823d33999 1107 */
<> 149:156823d33999 1108
<> 149:156823d33999 1109 #endif /* defined(RCC) */
<> 149:156823d33999 1110
<> 149:156823d33999 1111 /**
<> 149:156823d33999 1112 * @}
<> 149:156823d33999 1113 */
<> 149:156823d33999 1114
<> 149:156823d33999 1115 #ifdef __cplusplus
<> 149:156823d33999 1116 }
<> 149:156823d33999 1117 #endif
<> 149:156823d33999 1118
<> 149:156823d33999 1119 #endif /* __STM32L1xx_LL_BUS_H */
<> 149:156823d33999 1120
<> 149:156823d33999 1121 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/