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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_cortex.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
184:08ed48f1de7f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_cortex.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief CORTEX HAL module driver.
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * This file provides firmware functions to manage the following
<> 149:156823d33999 10 * functionalities of the CORTEX:
<> 149:156823d33999 11 * + Initialization and de-initialization functions
<> 149:156823d33999 12 * + Peripheral Control functions
<> 149:156823d33999 13 *
<> 149:156823d33999 14 * @verbatim
<> 149:156823d33999 15 ==============================================================================
<> 149:156823d33999 16 ##### How to use this driver #####
<> 149:156823d33999 17 ==============================================================================
<> 149:156823d33999 18
<> 149:156823d33999 19 [..]
<> 149:156823d33999 20 *** How to configure Interrupts using Cortex HAL driver ***
<> 149:156823d33999 21 ===========================================================
<> 149:156823d33999 22 [..]
<> 149:156823d33999 23 This section provide functions allowing to configure the NVIC interrupts (IRQ).
<> 149:156823d33999 24 The Cortex-M3 exceptions are managed by CMSIS functions.
<> 149:156823d33999 25
<> 149:156823d33999 26 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
<> 149:156823d33999 27 function according to the following table.
<> 149:156823d33999 28
<> 149:156823d33999 29 The table below gives the allowed values of the pre-emption priority and subpriority according
<> 149:156823d33999 30 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
<> 149:156823d33999 31 ==========================================================================================================================
<> 149:156823d33999 32 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
<> 149:156823d33999 33 ==========================================================================================================================
<> 149:156823d33999 34 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
<> 149:156823d33999 35 | | | 4 bits for subpriority
<> 149:156823d33999 36 --------------------------------------------------------------------------------------------------------------------------
<> 149:156823d33999 37 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
<> 149:156823d33999 38 | | | 3 bits for subpriority
<> 149:156823d33999 39 --------------------------------------------------------------------------------------------------------------------------
<> 149:156823d33999 40 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
<> 149:156823d33999 41 | | | 2 bits for subpriority
<> 149:156823d33999 42 --------------------------------------------------------------------------------------------------------------------------
<> 149:156823d33999 43 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
<> 149:156823d33999 44 | | | 1 bits for subpriority
<> 149:156823d33999 45 --------------------------------------------------------------------------------------------------------------------------
<> 149:156823d33999 46 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
<> 149:156823d33999 47 | | | 0 bits for subpriority
<> 149:156823d33999 48 ==========================================================================================================================
<> 149:156823d33999 49 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
<> 149:156823d33999 50
<> 149:156823d33999 51 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
<> 149:156823d33999 52
<> 149:156823d33999 53
<> 149:156823d33999 54 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
<> 149:156823d33999 55 The pending IRQ priority will be managed only by the sub priority.
<> 149:156823d33999 56
<> 149:156823d33999 57 -@- IRQ priority order (sorted by highest to lowest priority):
<> 149:156823d33999 58 (+@) Lowest pre-emption priority
<> 149:156823d33999 59 (+@) Lowest sub priority
<> 149:156823d33999 60 (+@) Lowest hardware priority (IRQ number)
<> 149:156823d33999 61
<> 149:156823d33999 62 [..]
<> 149:156823d33999 63 *** How to configure Systick using Cortex HAL driver ***
<> 149:156823d33999 64 ========================================================
<> 149:156823d33999 65 [..]
<> 149:156823d33999 66 Setup SysTick Timer for 1 msec interrupts.
<> 149:156823d33999 67
<> 149:156823d33999 68 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 149:156823d33999 69 is a CMSIS function that:
<> 149:156823d33999 70 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 149:156823d33999 71 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 149:156823d33999 72 (++) Resets the SysTick Counter register.
<> 149:156823d33999 73 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 149:156823d33999 74 (++) Enables the SysTick Interrupt.
<> 149:156823d33999 75 (++) Starts the SysTick Counter.
<> 149:156823d33999 76
<> 149:156823d33999 77 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 149:156823d33999 78 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 149:156823d33999 79 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
<> 149:156823d33999 80 inside the stm32l1xx_hal_cortex.h file.
<> 149:156823d33999 81
<> 149:156823d33999 82 (+) You can change the SysTick IRQ priority by calling the
<> 149:156823d33999 83 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 149:156823d33999 84 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 149:156823d33999 85
<> 149:156823d33999 86 (+) To adjust the SysTick time base, use the following formula:
<> 149:156823d33999 87
<> 149:156823d33999 88 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 149:156823d33999 89 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 149:156823d33999 90 (++) Reload Value should not exceed 0xFFFFFF
<> 149:156823d33999 91
<> 149:156823d33999 92 @endverbatim
<> 149:156823d33999 93 ******************************************************************************
<> 149:156823d33999 94 * @attention
<> 149:156823d33999 95 *
<> 149:156823d33999 96 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 97 *
<> 149:156823d33999 98 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 99 * are permitted provided that the following conditions are met:
<> 149:156823d33999 100 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 101 * this list of conditions and the following disclaimer.
<> 149:156823d33999 102 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 103 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 104 * and/or other materials provided with the distribution.
<> 149:156823d33999 105 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 106 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 107 * without specific prior written permission.
<> 149:156823d33999 108 *
<> 149:156823d33999 109 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 110 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 111 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 112 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 113 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 114 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 115 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 116 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 117 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 118 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 119 *
<> 149:156823d33999 120 ******************************************************************************
<> 149:156823d33999 121 */
<> 149:156823d33999 122
<> 149:156823d33999 123 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 124 #include "stm32l1xx_hal.h"
<> 149:156823d33999 125
<> 149:156823d33999 126 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 127 * @{
<> 149:156823d33999 128 */
<> 149:156823d33999 129
<> 149:156823d33999 130 /** @defgroup CORTEX CORTEX
<> 149:156823d33999 131 * @brief CORTEX HAL module driver
<> 149:156823d33999 132 * @{
<> 149:156823d33999 133 */
<> 149:156823d33999 134
<> 149:156823d33999 135 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 149:156823d33999 136
<> 149:156823d33999 137 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 138 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 139 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 140 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 141 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 142 /* Private functions ---------------------------------------------------------*/
<> 149:156823d33999 143
<> 149:156823d33999 144 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 149:156823d33999 145 * @{
<> 149:156823d33999 146 */
<> 149:156823d33999 147
<> 149:156823d33999 148
<> 149:156823d33999 149 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 149:156823d33999 150 * @brief Initialization and Configuration functions
<> 149:156823d33999 151 *
<> 149:156823d33999 152 @verbatim
<> 149:156823d33999 153 ==============================================================================
<> 149:156823d33999 154 ##### Initialization and de-initialization functions #####
<> 149:156823d33999 155 ==============================================================================
<> 149:156823d33999 156 [..]
<> 149:156823d33999 157 This section provide the Cortex HAL driver functions allowing to configure Interrupts
<> 149:156823d33999 158 Systick functionalities
<> 149:156823d33999 159
<> 149:156823d33999 160 @endverbatim
<> 149:156823d33999 161 * @{
<> 149:156823d33999 162 */
<> 149:156823d33999 163
<> 149:156823d33999 164
<> 149:156823d33999 165 /**
<> 149:156823d33999 166 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
<> 149:156823d33999 167 * using the required unlock sequence.
<> 149:156823d33999 168 * @param PriorityGroup: The priority grouping bits length.
<> 149:156823d33999 169 * This parameter can be one of the following values:
<> 149:156823d33999 170 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 149:156823d33999 171 * 4 bits for subpriority
<> 149:156823d33999 172 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 149:156823d33999 173 * 3 bits for subpriority
<> 149:156823d33999 174 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 149:156823d33999 175 * 2 bits for subpriority
<> 149:156823d33999 176 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 149:156823d33999 177 * 1 bits for subpriority
<> 149:156823d33999 178 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 149:156823d33999 179 * 0 bits for subpriority
<> 149:156823d33999 180 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
<> 149:156823d33999 181 * The pending IRQ priority will be managed only by the subpriority.
<> 149:156823d33999 182 * @retval None
<> 149:156823d33999 183 */
<> 149:156823d33999 184 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 149:156823d33999 185 {
<> 149:156823d33999 186 /* Check the parameters */
<> 149:156823d33999 187 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 149:156823d33999 188
<> 149:156823d33999 189 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 149:156823d33999 190 NVIC_SetPriorityGrouping(PriorityGroup);
<> 149:156823d33999 191 }
<> 149:156823d33999 192
<> 149:156823d33999 193 /**
<> 149:156823d33999 194 * @brief Sets the priority of an interrupt.
<> 149:156823d33999 195 * @param IRQn: External interrupt number
<> 149:156823d33999 196 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 197 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
<> 149:156823d33999 198 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
<> 149:156823d33999 199 * This parameter can be a value between 0 and 15
<> 149:156823d33999 200 * A lower priority value indicates a higher priority
<> 149:156823d33999 201 * @param SubPriority: the subpriority level for the IRQ channel.
<> 149:156823d33999 202 * This parameter can be a value between 0 and 15
<> 149:156823d33999 203 * A lower priority value indicates a higher priority.
<> 149:156823d33999 204 * @retval None
<> 149:156823d33999 205 */
<> 149:156823d33999 206 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 149:156823d33999 207 {
<> 149:156823d33999 208 uint32_t prioritygroup = 0x00;
<> 149:156823d33999 209
<> 149:156823d33999 210 /* Check the parameters */
<> 149:156823d33999 211 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 149:156823d33999 212 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 149:156823d33999 213
<> 149:156823d33999 214 prioritygroup = NVIC_GetPriorityGrouping();
<> 149:156823d33999 215
<> 149:156823d33999 216 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 149:156823d33999 217 }
<> 149:156823d33999 218
<> 149:156823d33999 219 /**
<> 149:156823d33999 220 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 149:156823d33999 221 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 149:156823d33999 222 * function should be called before.
<> 149:156823d33999 223 * @param IRQn External interrupt number
<> 149:156823d33999 224 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 225 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
<> 149:156823d33999 226 * @retval None
<> 149:156823d33999 227 */
<> 149:156823d33999 228 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 229 {
<> 149:156823d33999 230 /* Check the parameters */
<> 149:156823d33999 231 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 149:156823d33999 232
<> 149:156823d33999 233 /* Enable interrupt */
<> 149:156823d33999 234 NVIC_EnableIRQ(IRQn);
<> 149:156823d33999 235 }
<> 149:156823d33999 236
<> 149:156823d33999 237 /**
<> 149:156823d33999 238 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 149:156823d33999 239 * @param IRQn External interrupt number
<> 149:156823d33999 240 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 241 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 242 * @retval None
<> 149:156823d33999 243 */
<> 149:156823d33999 244 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 149:156823d33999 245 {
<> 149:156823d33999 246 /* Check the parameters */
<> 149:156823d33999 247 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 149:156823d33999 248
<> 149:156823d33999 249 /* Disable interrupt */
<> 149:156823d33999 250 NVIC_DisableIRQ(IRQn);
<> 149:156823d33999 251 }
<> 149:156823d33999 252
<> 149:156823d33999 253 /**
<> 149:156823d33999 254 * @brief Initiates a system reset request to reset the MCU.
<> 149:156823d33999 255 * @retval None
<> 149:156823d33999 256 */
<> 149:156823d33999 257 void HAL_NVIC_SystemReset(void)
<> 149:156823d33999 258 {
<> 149:156823d33999 259 /* System Reset */
<> 149:156823d33999 260 NVIC_SystemReset();
<> 149:156823d33999 261 }
<> 149:156823d33999 262
<> 149:156823d33999 263 /**
<> 149:156823d33999 264 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 149:156823d33999 265 * Counter is in free running mode to generate periodic interrupts.
<> 149:156823d33999 266 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 149:156823d33999 267 * @retval status: - 0 Function succeeded.
<> 149:156823d33999 268 * - 1 Function failed.
<> 149:156823d33999 269 */
<> 149:156823d33999 270 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 149:156823d33999 271 {
<> 149:156823d33999 272 return SysTick_Config(TicksNumb);
<> 149:156823d33999 273 }
<> 149:156823d33999 274 /**
<> 149:156823d33999 275 * @}
<> 149:156823d33999 276 */
<> 149:156823d33999 277
<> 149:156823d33999 278 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 149:156823d33999 279 * @brief Cortex control functions
<> 149:156823d33999 280 *
<> 149:156823d33999 281 @verbatim
<> 149:156823d33999 282 ==============================================================================
<> 149:156823d33999 283 ##### Peripheral Control functions #####
<> 149:156823d33999 284 ==============================================================================
<> 149:156823d33999 285 [..]
<> 149:156823d33999 286 This subsection provides a set of functions allowing to control the CORTEX
<> 149:156823d33999 287 (NVIC, SYSTICK, MPU) functionalities.
<> 149:156823d33999 288
<> 149:156823d33999 289
<> 149:156823d33999 290 @endverbatim
<> 149:156823d33999 291 * @{
<> 149:156823d33999 292 */
<> 149:156823d33999 293
<> 149:156823d33999 294 #if (__MPU_PRESENT == 1)
<> 149:156823d33999 295 /**
<> 149:156823d33999 296 * @brief Initializes and configures the Region and the memory to be protected.
<> 149:156823d33999 297 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 149:156823d33999 298 * the initialization and configuration information.
<> 149:156823d33999 299 * @retval None
<> 149:156823d33999 300 */
<> 149:156823d33999 301 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 149:156823d33999 302 {
<> 149:156823d33999 303 /* Check the parameters */
<> 149:156823d33999 304 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 149:156823d33999 305 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 149:156823d33999 306
<> 149:156823d33999 307 /* Set the Region number */
<> 149:156823d33999 308 MPU->RNR = MPU_Init->Number;
<> 149:156823d33999 309
<> 149:156823d33999 310 if ((MPU_Init->Enable) != RESET)
<> 149:156823d33999 311 {
<> 149:156823d33999 312 /* Check the parameters */
<> 149:156823d33999 313 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 149:156823d33999 314 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 149:156823d33999 315 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 149:156823d33999 316 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 149:156823d33999 317 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 149:156823d33999 318 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 149:156823d33999 319 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 149:156823d33999 320 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 149:156823d33999 321
<> 149:156823d33999 322 MPU->RBAR = MPU_Init->BaseAddress;
<> 149:156823d33999 323 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 149:156823d33999 324 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 149:156823d33999 325 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 149:156823d33999 326 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 149:156823d33999 327 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 149:156823d33999 328 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 149:156823d33999 329 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 149:156823d33999 330 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 149:156823d33999 331 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 149:156823d33999 332 }
<> 149:156823d33999 333 else
<> 149:156823d33999 334 {
<> 149:156823d33999 335 MPU->RBAR = 0x00;
<> 149:156823d33999 336 MPU->RASR = 0x00;
<> 149:156823d33999 337 }
<> 149:156823d33999 338 }
<> 149:156823d33999 339 #endif /* __MPU_PRESENT */
<> 149:156823d33999 340
<> 149:156823d33999 341 /**
<> 149:156823d33999 342 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
<> 149:156823d33999 343 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 149:156823d33999 344 */
<> 149:156823d33999 345 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 149:156823d33999 346 {
<> 149:156823d33999 347 /* Get the PRIGROUP[10:8] field value */
<> 149:156823d33999 348 return NVIC_GetPriorityGrouping();
<> 149:156823d33999 349 }
<> 149:156823d33999 350
<> 149:156823d33999 351 /**
<> 149:156823d33999 352 * @brief Gets the priority of an interrupt.
<> 149:156823d33999 353 * @param IRQn: External interrupt number
<> 149:156823d33999 354 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 355 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 356 * @param PriorityGroup: the priority grouping bits length.
<> 149:156823d33999 357 * This parameter can be one of the following values:
<> 149:156823d33999 358 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 149:156823d33999 359 * 4 bits for subpriority
<> 149:156823d33999 360 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 149:156823d33999 361 * 3 bits for subpriority
<> 149:156823d33999 362 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 149:156823d33999 363 * 2 bits for subpriority
<> 149:156823d33999 364 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 149:156823d33999 365 * 1 bits for subpriority
<> 149:156823d33999 366 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 149:156823d33999 367 * 0 bits for subpriority
<> 149:156823d33999 368 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 149:156823d33999 369 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 149:156823d33999 370 * @retval None
<> 149:156823d33999 371 */
<> 149:156823d33999 372 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 149:156823d33999 373 {
<> 149:156823d33999 374 /* Check the parameters */
<> 149:156823d33999 375 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 149:156823d33999 376 /* Get priority for Cortex-M system or device specific interrupts */
<> 149:156823d33999 377 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 149:156823d33999 378 }
<> 149:156823d33999 379
<> 149:156823d33999 380 /**
<> 149:156823d33999 381 * @brief Sets Pending bit of an external interrupt.
<> 149:156823d33999 382 * @param IRQn External interrupt number
<> 149:156823d33999 383 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 384 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 385 * @retval None
<> 149:156823d33999 386 */
<> 149:156823d33999 387 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 388 {
<> 149:156823d33999 389 /* Set interrupt pending */
<> 149:156823d33999 390 NVIC_SetPendingIRQ(IRQn);
<> 149:156823d33999 391 }
<> 149:156823d33999 392
<> 149:156823d33999 393 /**
<> 149:156823d33999 394 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 149:156823d33999 395 * and returns the pending bit for the specified interrupt).
<> 149:156823d33999 396 * @param IRQn External interrupt number
<> 149:156823d33999 397 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 398 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 399 * @retval status: - 0 Interrupt status is not pending.
<> 149:156823d33999 400 * - 1 Interrupt status is pending.
<> 149:156823d33999 401 */
<> 149:156823d33999 402 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 403 {
<> 149:156823d33999 404 /* Return 1 if pending else 0 */
<> 149:156823d33999 405 return NVIC_GetPendingIRQ(IRQn);
<> 149:156823d33999 406 }
<> 149:156823d33999 407
<> 149:156823d33999 408 /**
<> 149:156823d33999 409 * @brief Clears the pending bit of an external interrupt.
<> 149:156823d33999 410 * @param IRQn External interrupt number
<> 149:156823d33999 411 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 412 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 413 * @retval None
<> 149:156823d33999 414 */
<> 149:156823d33999 415 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 149:156823d33999 416 {
<> 149:156823d33999 417 /* Clear pending interrupt */
<> 149:156823d33999 418 NVIC_ClearPendingIRQ(IRQn);
<> 149:156823d33999 419 }
<> 149:156823d33999 420
<> 149:156823d33999 421 /**
<> 149:156823d33999 422 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
<> 149:156823d33999 423 * @param IRQn External interrupt number
<> 149:156823d33999 424 * This parameter can be an enumerator of IRQn_Type enumeration
<> 149:156823d33999 425 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
<> 149:156823d33999 426 * @retval status: - 0 Interrupt status is not pending.
<> 149:156823d33999 427 * - 1 Interrupt status is pending.
<> 149:156823d33999 428 */
<> 149:156823d33999 429 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 149:156823d33999 430 {
<> 149:156823d33999 431 /* Return 1 if active else 0 */
<> 149:156823d33999 432 return NVIC_GetActive(IRQn);
<> 149:156823d33999 433 }
<> 149:156823d33999 434
<> 149:156823d33999 435 /**
<> 149:156823d33999 436 * @brief Configures the SysTick clock source.
<> 149:156823d33999 437 * @param CLKSource: specifies the SysTick clock source.
<> 149:156823d33999 438 * This parameter can be one of the following values:
<> 149:156823d33999 439 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 149:156823d33999 440 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 149:156823d33999 441 * @retval None
<> 149:156823d33999 442 */
<> 149:156823d33999 443 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 149:156823d33999 444 {
<> 149:156823d33999 445 /* Check the parameters */
<> 149:156823d33999 446 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 149:156823d33999 447 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 149:156823d33999 448 {
<> 149:156823d33999 449 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 149:156823d33999 450 }
<> 149:156823d33999 451 else
<> 149:156823d33999 452 {
<> 149:156823d33999 453 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 149:156823d33999 454 }
<> 149:156823d33999 455 }
<> 149:156823d33999 456
<> 149:156823d33999 457 /**
<> 149:156823d33999 458 * @brief This function handles SYSTICK interrupt request.
<> 149:156823d33999 459 * @retval None
<> 149:156823d33999 460 */
<> 149:156823d33999 461 void HAL_SYSTICK_IRQHandler(void)
<> 149:156823d33999 462 {
<> 149:156823d33999 463 HAL_SYSTICK_Callback();
<> 149:156823d33999 464 }
<> 149:156823d33999 465
<> 149:156823d33999 466 /**
<> 149:156823d33999 467 * @brief SYSTICK callback.
<> 149:156823d33999 468 * @retval None
<> 149:156823d33999 469 */
<> 149:156823d33999 470 __weak void HAL_SYSTICK_Callback(void)
<> 149:156823d33999 471 {
<> 149:156823d33999 472 /* NOTE : This function Should not be modified, when the callback is needed,
<> 149:156823d33999 473 the HAL_SYSTICK_Callback could be implemented in the user file
<> 149:156823d33999 474 */
<> 149:156823d33999 475 }
<> 149:156823d33999 476
<> 149:156823d33999 477 /**
<> 149:156823d33999 478 * @}
<> 149:156823d33999 479 */
<> 149:156823d33999 480
<> 149:156823d33999 481 /**
<> 149:156823d33999 482 * @}
<> 149:156823d33999 483 */
<> 149:156823d33999 484
<> 149:156823d33999 485 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 149:156823d33999 486 /**
<> 149:156823d33999 487 * @}
<> 149:156823d33999 488 */
<> 149:156823d33999 489
<> 149:156823d33999 490 /**
<> 149:156823d33999 491 * @}
<> 149:156823d33999 492 */
<> 149:156823d33999 493
<> 149:156823d33999 494 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/