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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_adc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Child:: 184:08ed48f1de7f

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	149:156823d33999	1	/**
<>	149:156823d33999	2	******************************************************************************
<>	149:156823d33999	3	* @file stm32l1xx_hal_adc.h
<>	149:156823d33999	4	* @author MCD Application Team
<>	149:156823d33999	5	* @version V1.2.0
<>	149:156823d33999	6	* @date 01-July-2016
<>	149:156823d33999	7	* @brief Header file containing functions prototypes of ADC HAL library.
<>	149:156823d33999	8	******************************************************************************
<>	149:156823d33999	9	* @attention
<>	149:156823d33999	10	*
<>	149:156823d33999	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	149:156823d33999	12	*
<>	149:156823d33999	13	* Redistribution and use in source and binary forms, with or without modification,
<>	149:156823d33999	14	* are permitted provided that the following conditions are met:
<>	149:156823d33999	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	149:156823d33999	16	* this list of conditions and the following disclaimer.
<>	149:156823d33999	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	149:156823d33999	18	* this list of conditions and the following disclaimer in the documentation
<>	149:156823d33999	19	* and/or other materials provided with the distribution.
<>	149:156823d33999	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	149:156823d33999	21	* may be used to endorse or promote products derived from this software
<>	149:156823d33999	22	* without specific prior written permission.
<>	149:156823d33999	23	*
<>	149:156823d33999	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	149:156823d33999	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	149:156823d33999	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	149:156823d33999	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	149:156823d33999	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	149:156823d33999	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	149:156823d33999	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	149:156823d33999	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	149:156823d33999	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	149:156823d33999	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	149:156823d33999	34	*
<>	149:156823d33999	35	******************************************************************************
<>	149:156823d33999	36	*/
<>	149:156823d33999	37
<>	149:156823d33999	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	149:156823d33999	39	#ifndef __STM32L1xx_HAL_ADC_H
<>	149:156823d33999	40	#define __STM32L1xx_HAL_ADC_H
<>	149:156823d33999	41
<>	149:156823d33999	42	#ifdef __cplusplus
<>	149:156823d33999	43	extern "C" {
<>	149:156823d33999	44	#endif
<>	149:156823d33999	45
<>	149:156823d33999	46	/* Includes ------------------------------------------------------------------*/
<>	149:156823d33999	47	#include "stm32l1xx_hal_def.h"
<>	149:156823d33999	48
<>	149:156823d33999	49	/** @addtogroup STM32L1xx_HAL_Driver
<>	149:156823d33999	50	* @{
<>	149:156823d33999	51	*/
<>	149:156823d33999	52
<>	149:156823d33999	53	/** @addtogroup ADC
<>	149:156823d33999	54	* @{
<>	149:156823d33999	55	*/
<>	149:156823d33999	56
<>	149:156823d33999	57	/* Exported types ------------------------------------------------------------*/
<>	149:156823d33999	58	/** @defgroup ADC_Exported_Types ADC Exported Types
<>	149:156823d33999	59	* @{
<>	149:156823d33999	60	*/
<>	149:156823d33999	61
<>	149:156823d33999	62	/**
<>	149:156823d33999	63	* @brief Structure definition of ADC and regular group initialization
<>	149:156823d33999	64	* @note Parameters of this structure are shared within 2 scopes:
<>	149:156823d33999	65	* - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
<>	149:156823d33999	66	* - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
<>	149:156823d33999	67	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
<>	149:156823d33999	68	* ADC state can be either:
<>	149:156823d33999	69	* - For all parameters: ADC disabled
<>	149:156823d33999	70	* - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
<>	149:156823d33999	71	* - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
<>	149:156823d33999	72	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	149:156823d33999	73	* without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
<>	149:156823d33999	74	*/
<>	149:156823d33999	75	typedef struct
<>	149:156823d33999	76	{
<>	149:156823d33999	77	uint32_t ClockPrescaler; /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
<>	149:156823d33999	78	This parameter can be a value of @ref ADC_ClockPrescaler
<>	149:156823d33999	79	Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
<>	149:156823d33999	80	AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
<>	149:156823d33999	81	Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
<>	149:156823d33999	82	uint32_t Resolution; /*!< Configures the ADC resolution.
<>	149:156823d33999	83	This parameter can be a value of @ref ADC_Resolution */
<>	149:156823d33999	84	uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
<>	149:156823d33999	85	or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
<>	149:156823d33999	86	This parameter can be a value of @ref ADC_Data_align */
<>	149:156823d33999	87	uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
<>	149:156823d33999	88	This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
<>	149:156823d33999	89	If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
<>	149:156823d33999	90	Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
<>	149:156823d33999	91	If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
<>	149:156823d33999	92	Scan direction is upward: from rank1 to rank 'n'.
<>	149:156823d33999	93	This parameter can be a value of @ref ADC_Scan_mode */
<>	149:156823d33999	94	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
<>	149:156823d33999	95	This parameter can be a value of @ref ADC_EOCSelection.
<>	149:156823d33999	96	Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
<>	149:156823d33999	97	Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
<>	149:156823d33999	98	or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
<>	149:156823d33999	99	Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
<>	149:156823d33999	100	If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
<>	149:156823d33999	101	uint32_t LowPowerAutoWait; /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
<>	149:156823d33999	102	conversion (for regular group) or previous sequence (for injected group) has been treated by user software, using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
<>	149:156823d33999	103	This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications.
<>	149:156823d33999	104	This parameter can be a value of @ref ADC_LowPowerAutoWait.
<>	149:156823d33999	105	Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
<>	149:156823d33999	106	Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
<>	149:156823d33999	107	and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion (in case of usage of injected group, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...).
<>	149:156823d33999	108	Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
<>	149:156823d33999	109	uint32_t LowPowerAutoPowerOff; /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
<>	149:156823d33999	110	This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
<>	149:156823d33999	111	This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
<>	149:156823d33999	112	uint32_t ChannelsBank; /*!< Selects the ADC channels bank.
<>	149:156823d33999	113	This parameter can be a value of @ref ADC_ChannelsBank.
<>	149:156823d33999	114	Note: Banks availability depends on devices categories.
<>	149:156823d33999	115	Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
<>	149:156823d33999	116	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
<>	149:156823d33999	117	after the selected trigger occurred (software start or external trigger).
<>	149:156823d33999	118	This parameter can be set to ENABLE or DISABLE. */
<>	149:156823d33999	119	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	120	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	149:156823d33999	121	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	149:156823d33999	122	This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
<>	149:156823d33999	123	#else
<>	149:156823d33999	124	uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
<>	149:156823d33999	125	To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
<>	149:156823d33999	126	This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
<>	149:156823d33999	127	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	128	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
<>	149:156823d33999	129	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
<>	149:156823d33999	130	Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
<>	149:156823d33999	131	This parameter can be set to ENABLE or DISABLE. */
<>	149:156823d33999	132	uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
<>	149:156823d33999	133	If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
<>	149:156823d33999	134	This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
<>	149:156823d33999	135	uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
<>	149:156823d33999	136	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	149:156823d33999	137	If set to external trigger source, triggering is on event rising edge by default.
<>	149:156823d33999	138	This parameter can be a value of @ref ADC_External_trigger_source_Regular */
<>	149:156823d33999	139	uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
<>	149:156823d33999	140	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<>	149:156823d33999	141	This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
<>	149:156823d33999	142	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<>	149:156823d33999	143	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	149:156823d33999	144	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
<>	149:156823d33999	145	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
<>	149:156823d33999	146	This parameter can be set to ENABLE or DISABLE. */
<>	149:156823d33999	147	}ADC_InitTypeDef;
<>	149:156823d33999	148
<>	149:156823d33999	149	/**
<>	149:156823d33999	150	* @brief Structure definition of ADC channel for regular group
<>	149:156823d33999	151	* @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
<>	149:156823d33999	152	* ADC can be either disabled or enabled without conversion on going on regular group.
<>	149:156823d33999	153	*/
<>	149:156823d33999	154	typedef struct
<>	149:156823d33999	155	{
<>	149:156823d33999	156	uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
<>	149:156823d33999	157	This parameter can be a value of @ref ADC_channels
<>	149:156823d33999	158	Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
<>	149:156823d33999	159	Maximum number of channels by device category (without taking in account each device package constraints):
<>	149:156823d33999	160	STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
<>	149:156823d33999	161	STM32L1 category 3: 25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<>	149:156823d33999	162	STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
<>	149:156823d33999	163	Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
<>	149:156823d33999	164	Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
<>	149:156823d33999	165	uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
<>	149:156823d33999	166	This parameter can be a value of @ref ADC_regular_rank
<>	149:156823d33999	167	Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
<>	149:156823d33999	168	uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
<>	149:156823d33999	169	Unit: ADC clock cycles
<>	149:156823d33999	170	Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
<>	149:156823d33999	171	This parameter can be a value of @ref ADC_sampling_times
<>	149:156823d33999	172	Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
<>	149:156823d33999	173	If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
<>	149:156823d33999	174	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
<>	149:156823d33999	175	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
<>	149:156823d33999	176	Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
<>	149:156823d33999	177	}ADC_ChannelConfTypeDef;
<>	149:156823d33999	178
<>	149:156823d33999	179	/**
<>	149:156823d33999	180	* @brief ADC Configuration analog watchdog definition
<>	149:156823d33999	181	* @note The setting of these parameters with function is conditioned to ADC state.
<>	149:156823d33999	182	* ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
<>	149:156823d33999	183	*/
<>	149:156823d33999	184	typedef struct
<>	149:156823d33999	185	{
<>	149:156823d33999	186	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
<>	149:156823d33999	187	This parameter can be a value of @ref ADC_analog_watchdog_mode. */
<>	149:156823d33999	188	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<>	149:156823d33999	189	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<>	149:156823d33999	190	This parameter can be a value of @ref ADC_channels. */
<>	149:156823d33999	191	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<>	149:156823d33999	192	This parameter can be set to ENABLE or DISABLE */
<>	149:156823d33999	193	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	149:156823d33999	194	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	149:156823d33999	195	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	149:156823d33999	196	This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
<>	149:156823d33999	197	uint32_t WatchdogNumber; /!< Reserved for future use, can be set to 0 /
<>	149:156823d33999	198	}ADC_AnalogWDGConfTypeDef;
<>	149:156823d33999	199
<>	149:156823d33999	200	/**
<>	149:156823d33999	201	* @brief HAL ADC state machine: ADC states definition (bitfields)
<>	149:156823d33999	202	*/
<>	149:156823d33999	203	/* States of ADC global scope */
<>	149:156823d33999	204	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
<>	149:156823d33999	205	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
<>	149:156823d33999	206	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy to internal process (initialization, calibration) /
<>	149:156823d33999	207	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
<>	149:156823d33999	208
<>	149:156823d33999	209	/* States of ADC errors */
<>	149:156823d33999	210	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
<>	149:156823d33999	211	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
<>	149:156823d33999	212	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
<>	149:156823d33999	213
<>	149:156823d33999	214	/* States of ADC group regular */
<>	149:156823d33999	215	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<>	149:156823d33999	216	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	149:156823d33999	217	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
<>	149:156823d33999	218	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
<>	149:156823d33999	219	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on STM32L1 device: End Of Sampling flag raised /
<>	149:156823d33999	220
<>	149:156823d33999	221	/* States of ADC group injected */
<>	149:156823d33999	222	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<>	149:156823d33999	223	external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
<>	149:156823d33999	224	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Conversion data available on group injected /
<>	149:156823d33999	225	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on STM32L1 device: Injected queue overflow occurrence /
<>	149:156823d33999	226
<>	149:156823d33999	227	/* States of ADC analog watchdogs */
<>	149:156823d33999	228	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of analog watchdog 1 /
<>	149:156823d33999	229	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 2 /
<>	149:156823d33999	230	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on STM32L1 device: Out-of-window occurrence of analog watchdog 3 /
<>	149:156823d33999	231
<>	149:156823d33999	232	/* States of ADC multi-mode */
<>	149:156823d33999	233	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on STM32L1 device: ADC in multimode slave state, controlled by another ADC master ( /
<>	149:156823d33999	234
<>	149:156823d33999	235
<>	149:156823d33999	236	/**
<>	149:156823d33999	237	* @brief ADC handle Structure definition
<>	149:156823d33999	238	*/
<>	149:156823d33999	239	typedef struct
<>	149:156823d33999	240	{
<>	149:156823d33999	241	ADC_TypeDef Instance; /!< Register base address */
<>	149:156823d33999	242
<>	149:156823d33999	243	ADC_InitTypeDef Init; /!< ADC required parameters /
<>	149:156823d33999	244
<>	149:156823d33999	245	__IO uint32_t NbrOfConversionRank ; /!< ADC conversion rank counter /
<>	149:156823d33999	246
<>	149:156823d33999	247	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	149:156823d33999	248
<>	149:156823d33999	249	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	149:156823d33999	250
<>	149:156823d33999	251	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
<>	149:156823d33999	252
<>	149:156823d33999	253	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	149:156823d33999	254	}ADC_HandleTypeDef;
<>	149:156823d33999	255	/**
<>	149:156823d33999	256	* @}
<>	149:156823d33999	257	*/
<>	149:156823d33999	258
<>	149:156823d33999	259
<>	149:156823d33999	260
<>	149:156823d33999	261	/* Exported constants --------------------------------------------------------*/
<>	149:156823d33999	262
<>	149:156823d33999	263	/** @defgroup ADC_Exported_Constants ADC Exported Constants
<>	149:156823d33999	264	* @{
<>	149:156823d33999	265	*/
<>	149:156823d33999	266
<>	149:156823d33999	267	/** @defgroup ADC_Error_Code ADC Error Code
<>	149:156823d33999	268	* @{
<>	149:156823d33999	269	*/
<>	149:156823d33999	270	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
<>	149:156823d33999	271	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<>	149:156823d33999	272	enable/disable, erroneous state */
<>	149:156823d33999	273	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< Overrun error /
<>	149:156823d33999	274	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
<>	149:156823d33999	275	/**
<>	149:156823d33999	276	* @}
<>	149:156823d33999	277	*/
<>	149:156823d33999	278
<>	149:156823d33999	279	/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
<>	149:156823d33999	280	* @{
<>	149:156823d33999	281	*/
<>	149:156823d33999	282	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler /
<>	149:156823d33999	283	#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_ADCPRE_0) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 /
<>	149:156823d33999	284	#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_ADCPRE_1) /!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 /
<>	149:156823d33999	285	/**
<>	149:156823d33999	286	* @}
<>	149:156823d33999	287	*/
<>	149:156823d33999	288
<>	149:156823d33999	289	/** @defgroup ADC_Resolution ADC Resolution
<>	149:156823d33999	290	* @{
<>	149:156823d33999	291	*/
<>	149:156823d33999	292	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
<>	149:156823d33999	293	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) /!< ADC 10-bit resolution /
<>	149:156823d33999	294	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) /!< ADC 8-bit resolution /
<>	149:156823d33999	295	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /!< ADC 6-bit resolution /
<>	149:156823d33999	296	/**
<>	149:156823d33999	297	* @}
<>	149:156823d33999	298	*/
<>	149:156823d33999	299
<>	149:156823d33999	300	/** @defgroup ADC_Data_align ADC Data_align
<>	149:156823d33999	301	* @{
<>	149:156823d33999	302	*/
<>	149:156823d33999	303	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<>	149:156823d33999	304	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
<>	149:156823d33999	305	/**
<>	149:156823d33999	306	* @}
<>	149:156823d33999	307	*/
<>	149:156823d33999	308
<>	149:156823d33999	309	/** @defgroup ADC_Scan_mode ADC Scan mode
<>	149:156823d33999	310	* @{
<>	149:156823d33999	311	*/
<>	149:156823d33999	312	#define ADC_SCAN_DISABLE ((uint32_t)0x00000000)
<>	149:156823d33999	313	#define ADC_SCAN_ENABLE ((uint32_t)ADC_CR1_SCAN)
<>	149:156823d33999	314	/**
<>	149:156823d33999	315	* @}
<>	149:156823d33999	316	*/
<>	149:156823d33999	317
<>	149:156823d33999	318	/** @defgroup ADC_External_trigger_edge_Regular ADC external trigger enable for regular group
<>	149:156823d33999	319	* @{
<>	149:156823d33999	320	*/
<>	149:156823d33999	321	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<>	149:156823d33999	322	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
<>	149:156823d33999	323	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
<>	149:156823d33999	324	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
<>	149:156823d33999	325	/**
<>	149:156823d33999	326	* @}
<>	149:156823d33999	327	*/
<>	149:156823d33999	328
<>	149:156823d33999	329	/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
<>	149:156823d33999	330	* @{
<>	149:156823d33999	331	*/
<>	149:156823d33999	332	/* List of external triggers with generic trigger name, sorted by trigger */
<>	149:156823d33999	333	/* name: */
<>	149:156823d33999	334
<>	149:156823d33999	335	/* External triggers of regular group for ADC1 */
<>	149:156823d33999	336	#define ADC_EXTERNALTRIGCONV_T2_CC3 ADC_EXTERNALTRIG_T2_CC3
<>	149:156823d33999	337	#define ADC_EXTERNALTRIGCONV_T2_CC2 ADC_EXTERNALTRIG_T2_CC2
<>	149:156823d33999	338	#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_EXTERNALTRIG_T2_TRGO
<>	149:156823d33999	339	#define ADC_EXTERNALTRIGCONV_T3_CC1 ADC_EXTERNALTRIG_T3_CC1
<>	149:156823d33999	340	#define ADC_EXTERNALTRIGCONV_T3_CC3 ADC_EXTERNALTRIG_T3_CC3
<>	149:156823d33999	341	#define ADC_EXTERNALTRIGCONV_T3_TRGO ADC_EXTERNALTRIG_T3_TRGO
<>	149:156823d33999	342	#define ADC_EXTERNALTRIGCONV_T4_CC4 ADC_EXTERNALTRIG_T4_CC4
<>	149:156823d33999	343	#define ADC_EXTERNALTRIGCONV_T4_TRGO ADC_EXTERNALTRIG_T4_TRGO
<>	149:156823d33999	344	#define ADC_EXTERNALTRIGCONV_T6_TRGO ADC_EXTERNALTRIG_T6_TRGO
<>	149:156823d33999	345	#define ADC_EXTERNALTRIGCONV_T9_CC2 ADC_EXTERNALTRIG_T9_CC2
<>	149:156823d33999	346	#define ADC_EXTERNALTRIGCONV_T9_TRGO ADC_EXTERNALTRIG_T9_TRGO
<>	149:156823d33999	347	#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_EXTERNALTRIG_EXT_IT11
<>	149:156823d33999	348	#define ADC_SOFTWARE_START ((uint32_t)0x00000010)
<>	149:156823d33999	349	/**
<>	149:156823d33999	350	* @}
<>	149:156823d33999	351	*/
<>	149:156823d33999	352
<>	149:156823d33999	353	/** @defgroup ADC_EOCSelection ADC EOCSelection
<>	149:156823d33999	354	* @{
<>	149:156823d33999	355	*/
<>	149:156823d33999	356	#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
<>	149:156823d33999	357	#define ADC_EOC_SINGLE_CONV ((uint32_t)ADC_CR2_EOCS)
<>	149:156823d33999	358	/**
<>	149:156823d33999	359	* @}
<>	149:156823d33999	360	*/
<>	149:156823d33999	361
<>	149:156823d33999	362	/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
<>	149:156823d33999	363	* @{
<>	149:156823d33999	364	*/
<>	149:156823d33999	365	/!< Note : For compatibility with other STM32 devices with ADC autowait /
<>	149:156823d33999	366	/* feature limited to enable or disable settings: */
<>	149:156823d33999	367	/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE". */
<>	149:156823d33999	368
<>	149:156823d33999	369	#define ADC_AUTOWAIT_DISABLE ((uint32_t)0x00000000)
<>	149:156823d33999	370	#define ADC_AUTOWAIT_UNTIL_DATA_READ ((uint32_t)( ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read /
<>	149:156823d33999	371	#define ADC_AUTOWAIT_7_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 7 APB clock cycles /
<>	149:156823d33999	372	#define ADC_AUTOWAIT_15_APBCLOCKCYCLES ((uint32_t)( ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 15 APB clock cycles /
<>	149:156823d33999	373	#define ADC_AUTOWAIT_31_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 )) /!< Insert a delay between ADC conversions: 31 APB clock cycles /
<>	149:156823d33999	374	#define ADC_AUTOWAIT_63_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 63 APB clock cycles /
<>	149:156823d33999	375	#define ADC_AUTOWAIT_127_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 )) /!< Insert a delay between ADC conversions: 127 APB clock cycles /
<>	149:156823d33999	376	#define ADC_AUTOWAIT_255_APBCLOCKCYCLES ((uint32_t)(ADC_CR2_DELS_2 \| ADC_CR2_DELS_1 \| ADC_CR2_DELS_0)) /!< Insert a delay between ADC conversions: 255 APB clock cycles /
<>	149:156823d33999	377
<>	149:156823d33999	378	/**
<>	149:156823d33999	379	* @}
<>	149:156823d33999	380	*/
<>	149:156823d33999	381
<>	149:156823d33999	382	/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
<>	149:156823d33999	383	* @{
<>	149:156823d33999	384	*/
<>	149:156823d33999	385	#define ADC_AUTOPOWEROFF_DISABLE ((uint32_t)0x00000000)
<>	149:156823d33999	386	#define ADC_AUTOPOWEROFF_IDLE_PHASE ((uint32_t)ADC_CR1_PDI) /!< ADC power off when ADC is not converting (idle phase) /
<>	149:156823d33999	387	#define ADC_AUTOPOWEROFF_DELAY_PHASE ((uint32_t)ADC_CR1_PDD) /!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) /
<>	149:156823d33999	388	#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES ((uint32_t)(ADC_CR1_PDI \| ADC_CR1_PDD)) /!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions /
<>	149:156823d33999	389	/**
<>	149:156823d33999	390	* @}
<>	149:156823d33999	391	*/
<>	149:156823d33999	392
<>	149:156823d33999	393
<>	149:156823d33999	394	/** @defgroup ADC_ChannelsBank ADC ChannelsBank
<>	149:156823d33999	395	* @{
<>	149:156823d33999	396	*/
<>	149:156823d33999	397	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	398	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<>	149:156823d33999	399	#define ADC_CHANNELS_BANK_B ((uint32_t)ADC_CR2_CFG)
<>	149:156823d33999	400
<>	149:156823d33999	401	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
<>	149:156823d33999	402	((BANK) == ADC_CHANNELS_BANK_B) )
<>	149:156823d33999	403	#else
<>	149:156823d33999	404	#define ADC_CHANNELS_BANK_A ((uint32_t)0x00000000)
<>	149:156823d33999	405
<>	149:156823d33999	406	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<>	149:156823d33999	407	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	408	/**
<>	149:156823d33999	409	* @}
<>	149:156823d33999	410	*/
<>	149:156823d33999	411
<>	149:156823d33999	412	/** @defgroup ADC_channels ADC channels
<>	149:156823d33999	413	* @{
<>	149:156823d33999	414	*/
<>	149:156823d33999	415	/* Note: Depending on devices, some channels may not be available on package */
<>	149:156823d33999	416	/* pins. Refer to device datasheet for channels availability. */
<>	149:156823d33999	417	#define ADC_CHANNEL_0 ((uint32_t)0x00000000) /* Channel different in bank A and bank B */
<>	149:156823d33999	418	#define ADC_CHANNEL_1 ((uint32_t)( ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	149:156823d33999	419	#define ADC_CHANNEL_2 ((uint32_t)( ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	149:156823d33999	420	#define ADC_CHANNEL_3 ((uint32_t)( ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	149:156823d33999	421	#define ADC_CHANNEL_4 ((uint32_t)( ADC_SQR5_SQ1_2 )) /* Direct (fast) channel */
<>	149:156823d33999	422	#define ADC_CHANNEL_5 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	149:156823d33999	423	#define ADC_CHANNEL_6 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	149:156823d33999	424	#define ADC_CHANNEL_7 ((uint32_t)( ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	149:156823d33999	425	#define ADC_CHANNEL_8 ((uint32_t)( ADC_SQR5_SQ1_3 )) /* Channel different in bank A and bank B */
<>	149:156823d33999	426	#define ADC_CHANNEL_9 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	149:156823d33999	427	#define ADC_CHANNEL_10 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel different in bank A and bank B */
<>	149:156823d33999	428	#define ADC_CHANNEL_11 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel different in bank A and bank B */
<>	149:156823d33999	429	#define ADC_CHANNEL_12 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel different in bank A and bank B */
<>	149:156823d33999	430	#define ADC_CHANNEL_13 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	431	#define ADC_CHANNEL_14 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	432	#define ADC_CHANNEL_15 ((uint32_t)( ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	433	#define ADC_CHANNEL_16 ((uint32_t)(ADC_SQR5_SQ1_4 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	434	#define ADC_CHANNEL_17 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	435	#define ADC_CHANNEL_18 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	436	#define ADC_CHANNEL_19 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	437	#define ADC_CHANNEL_20 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	438	#define ADC_CHANNEL_21 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	439	#define ADC_CHANNEL_22 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Direct (fast) channel */
<>	149:156823d33999	440	#define ADC_CHANNEL_23 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	149:156823d33999	441	#define ADC_CHANNEL_24 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 )) /* Direct (fast) channel */
<>	149:156823d33999	442	#define ADC_CHANNEL_25 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_0)) /* Direct (fast) channel */
<>	149:156823d33999	443	#define ADC_CHANNEL_26 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	444	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	445	#define ADC_CHANNEL_27 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	446	#define ADC_CHANNEL_28 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	447	#define ADC_CHANNEL_29 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	448	#define ADC_CHANNEL_30 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 )) /* Channel common to both bank A and bank B */
<>	149:156823d33999	449	#define ADC_CHANNEL_31 ((uint32_t)(ADC_SQR5_SQ1_4 \| ADC_SQR5_SQ1_3 \| ADC_SQR5_SQ1_2 \| ADC_SQR5_SQ1_1 \| ADC_SQR5_SQ1_0)) /* Channel common to both bank A and bank B */
<>	149:156823d33999	450	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	451
<>	149:156823d33999	452	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_16 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	149:156823d33999	453	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	149:156823d33999	454	#define ADC_CHANNEL_VCOMP ADC_CHANNEL_26 /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
<>	149:156823d33999	455
<>	149:156823d33999	456	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	457	#define ADC_CHANNEL_VOPAMP1 ADC_CHANNEL_3 /* Internal connection from OPAMP1 output to ADC switch matrix */
<>	149:156823d33999	458	#define ADC_CHANNEL_VOPAMP2 ADC_CHANNEL_8 /* Internal connection from OPAMP2 output to ADC switch matrix */
<>	149:156823d33999	459	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD)
<>	149:156823d33999	460	#define ADC_CHANNEL_VOPAMP3 ADC_CHANNEL_13 /* Internal connection from OPAMP3 output to ADC switch matrix */
<>	149:156823d33999	461	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD */
<>	149:156823d33999	462	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	463	/**
<>	149:156823d33999	464	* @}
<>	149:156823d33999	465	*/
<>	149:156823d33999	466
<>	149:156823d33999	467	/** @defgroup ADC_sampling_times ADC sampling times
<>	149:156823d33999	468	* @{
<>	149:156823d33999	469	*/
<>	149:156823d33999	470	#define ADC_SAMPLETIME_4CYCLES ((uint32_t)0x00000000) /!< Sampling time 4 ADC clock cycles /
<>	149:156823d33999	471	#define ADC_SAMPLETIME_9CYCLES ((uint32_t) ADC_SMPR3_SMP0_0) /!< Sampling time 9 ADC clock cycles /
<>	149:156823d33999	472	#define ADC_SAMPLETIME_16CYCLES ((uint32_t) ADC_SMPR3_SMP0_1) /!< Sampling time 16 ADC clock cycles /
<>	149:156823d33999	473	#define ADC_SAMPLETIME_24CYCLES ((uint32_t)(ADC_SMPR3_SMP0_1 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 24 ADC clock cycles /
<>	149:156823d33999	474	#define ADC_SAMPLETIME_48CYCLES ((uint32_t) ADC_SMPR3_SMP0_2) /!< Sampling time 48 ADC clock cycles /
<>	149:156823d33999	475	#define ADC_SAMPLETIME_96CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_0)) /!< Sampling time 96 ADC clock cycles /
<>	149:156823d33999	476	#define ADC_SAMPLETIME_192CYCLES ((uint32_t)(ADC_SMPR3_SMP0_2 \| ADC_SMPR3_SMP0_1)) /!< Sampling time 192 ADC clock cycles /
<>	149:156823d33999	477	#define ADC_SAMPLETIME_384CYCLES ((uint32_t) ADC_SMPR3_SMP0) /!< Sampling time 384 ADC clock cycles /
<>	149:156823d33999	478	/**
<>	149:156823d33999	479	* @}
<>	149:156823d33999	480	*/
<>	149:156823d33999	481
<>	149:156823d33999	482	/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
<>	149:156823d33999	483	* @{
<>	149:156823d33999	484	*/
<>	149:156823d33999	485	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2 \
<>	149:156823d33999	486	(ADC_SMPR3_SMP9_2 \| ADC_SMPR3_SMP8_2 \| ADC_SMPR3_SMP7_2 \| ADC_SMPR3_SMP6_2 \| \
<>	149:156823d33999	487	ADC_SMPR3_SMP5_2 \| ADC_SMPR3_SMP4_2 \| ADC_SMPR3_SMP3_2 \| ADC_SMPR3_SMP2_2 \| \
<>	149:156823d33999	488	ADC_SMPR3_SMP1_2 \| ADC_SMPR3_SMP0_2)
<>	149:156823d33999	489	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2 \
<>	149:156823d33999	490	(ADC_SMPR2_SMP19_2 \| ADC_SMPR2_SMP18_2 \| ADC_SMPR2_SMP17_2 \| ADC_SMPR2_SMP16_2 \| \
<>	149:156823d33999	491	ADC_SMPR2_SMP15_2 \| ADC_SMPR2_SMP14_2 \| ADC_SMPR2_SMP13_2 \| ADC_SMPR2_SMP12_2 \| \
<>	149:156823d33999	492	ADC_SMPR2_SMP11_2 \| ADC_SMPR2_SMP10_2)
<>	149:156823d33999	493	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	149:156823d33999	494	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<>	149:156823d33999	495	(ADC_SMPR1_SMP26_2 \| ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| \
<>	149:156823d33999	496	ADC_SMPR1_SMP22_2 \| ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
<>	149:156823d33999	497	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	149:156823d33999	498	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	499	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2 \
<>	149:156823d33999	500	(ADC_SMPR1_SMP29_2 \| ADC_SMPR1_SMP28_2 \| ADC_SMPR1_SMP27_2 \| ADC_SMPR1_SMP26_2 \| \
<>	149:156823d33999	501	ADC_SMPR1_SMP25_2 \| ADC_SMPR1_SMP24_2 \| ADC_SMPR1_SMP23_2 \| ADC_SMPR1_SMP22_2 \| \
<>	149:156823d33999	502	ADC_SMPR1_SMP21_2 \| ADC_SMPR1_SMP20_2)
<>	149:156823d33999	503	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2 \
<>	149:156823d33999	504	(ADC_SMPR0_SMP31_2 \| ADC_SMPR0_SMP30_2 )
<>	149:156823d33999	505	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	506
<>	149:156823d33999	507	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1 \
<>	149:156823d33999	508	(ADC_SMPR3_SMP9_1 \| ADC_SMPR3_SMP8_1 \| ADC_SMPR3_SMP7_1 \| ADC_SMPR3_SMP6_1 \| \
<>	149:156823d33999	509	ADC_SMPR3_SMP5_1 \| ADC_SMPR3_SMP4_1 \| ADC_SMPR3_SMP3_1 \| ADC_SMPR3_SMP2_1 \| \
<>	149:156823d33999	510	ADC_SMPR3_SMP1_1 \| ADC_SMPR3_SMP0_1)
<>	149:156823d33999	511	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1 \
<>	149:156823d33999	512	(ADC_SMPR2_SMP19_1 \| ADC_SMPR2_SMP18_1 \| ADC_SMPR2_SMP17_1 \| ADC_SMPR2_SMP16_1 \| \
<>	149:156823d33999	513	ADC_SMPR2_SMP15_1 \| ADC_SMPR2_SMP14_1 \| ADC_SMPR2_SMP13_1 \| ADC_SMPR2_SMP12_1 \| \
<>	149:156823d33999	514	ADC_SMPR2_SMP11_1 \| ADC_SMPR2_SMP10_1)
<>	149:156823d33999	515	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	149:156823d33999	516	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<>	149:156823d33999	517	(ADC_SMPR1_SMP26_1 \| ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| \
<>	149:156823d33999	518	ADC_SMPR1_SMP22_1 \| ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
<>	149:156823d33999	519	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	149:156823d33999	520	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	521	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1 \
<>	149:156823d33999	522	(ADC_SMPR1_SMP29_1 \| ADC_SMPR1_SMP28_1 \| ADC_SMPR1_SMP27_1 \| ADC_SMPR1_SMP26_1 \| \
<>	149:156823d33999	523	ADC_SMPR1_SMP25_1 \| ADC_SMPR1_SMP24_1 \| ADC_SMPR1_SMP23_1 \| ADC_SMPR1_SMP22_1 \| \
<>	149:156823d33999	524	ADC_SMPR1_SMP21_1 \| ADC_SMPR1_SMP20_1)
<>	149:156823d33999	525	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1 \
<>	149:156823d33999	526	(ADC_SMPR0_SMP31_1 \| ADC_SMPR0_SMP30_1 )
<>	149:156823d33999	527	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	528
<>	149:156823d33999	529	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0 \
<>	149:156823d33999	530	(ADC_SMPR3_SMP9_0 \| ADC_SMPR3_SMP8_0 \| ADC_SMPR3_SMP7_0 \| ADC_SMPR3_SMP6_0 \| \
<>	149:156823d33999	531	ADC_SMPR3_SMP5_0 \| ADC_SMPR3_SMP4_0 \| ADC_SMPR3_SMP3_0 \| ADC_SMPR3_SMP2_0 \| \
<>	149:156823d33999	532	ADC_SMPR3_SMP1_0 \| ADC_SMPR3_SMP0_0)
<>	149:156823d33999	533	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0 \
<>	149:156823d33999	534	(ADC_SMPR2_SMP19_0 \| ADC_SMPR2_SMP18_0 \| ADC_SMPR2_SMP17_0 \| ADC_SMPR2_SMP16_0 \| \
<>	149:156823d33999	535	ADC_SMPR2_SMP15_0 \| ADC_SMPR2_SMP14_0 \| ADC_SMPR2_SMP13_0 \| ADC_SMPR2_SMP12_0 \| \
<>	149:156823d33999	536	ADC_SMPR2_SMP11_0 \| ADC_SMPR2_SMP10_0)
<>	149:156823d33999	537	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	149:156823d33999	538	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<>	149:156823d33999	539	(ADC_SMPR1_SMP26_0 \| ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| \
<>	149:156823d33999	540	ADC_SMPR1_SMP22_0 \| ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
<>	149:156823d33999	541	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	149:156823d33999	542	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	543	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0 \
<>	149:156823d33999	544	(ADC_SMPR1_SMP29_0 \| ADC_SMPR1_SMP28_0 \| ADC_SMPR1_SMP27_0 \| ADC_SMPR1_SMP26_0 \| \
<>	149:156823d33999	545	ADC_SMPR1_SMP25_0 \| ADC_SMPR1_SMP24_0 \| ADC_SMPR1_SMP23_0 \| ADC_SMPR1_SMP22_0 \| \
<>	149:156823d33999	546	ADC_SMPR1_SMP21_0 \| ADC_SMPR1_SMP20_0)
<>	149:156823d33999	547	#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0 \
<>	149:156823d33999	548	(ADC_SMPR0_SMP31_0 \| ADC_SMPR0_SMP30_0 )
<>	149:156823d33999	549	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	550	/**
<>	149:156823d33999	551	* @}
<>	149:156823d33999	552	*/
<>	149:156823d33999	553
<>	149:156823d33999	554	/** @defgroup ADC_regular_rank ADC rank into regular group
<>	149:156823d33999	555	* @{
<>	149:156823d33999	556	*/
<>	149:156823d33999	557	#define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001)
<>	149:156823d33999	558	#define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002)
<>	149:156823d33999	559	#define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003)
<>	149:156823d33999	560	#define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004)
<>	149:156823d33999	561	#define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005)
<>	149:156823d33999	562	#define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006)
<>	149:156823d33999	563	#define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007)
<>	149:156823d33999	564	#define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008)
<>	149:156823d33999	565	#define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009)
<>	149:156823d33999	566	#define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A)
<>	149:156823d33999	567	#define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B)
<>	149:156823d33999	568	#define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C)
<>	149:156823d33999	569	#define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D)
<>	149:156823d33999	570	#define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E)
<>	149:156823d33999	571	#define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F)
<>	149:156823d33999	572	#define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010)
<>	149:156823d33999	573	#define ADC_REGULAR_RANK_17 ((uint32_t)0x00000011)
<>	149:156823d33999	574	#define ADC_REGULAR_RANK_18 ((uint32_t)0x00000012)
<>	149:156823d33999	575	#define ADC_REGULAR_RANK_19 ((uint32_t)0x00000013)
<>	149:156823d33999	576	#define ADC_REGULAR_RANK_20 ((uint32_t)0x00000014)
<>	149:156823d33999	577	#define ADC_REGULAR_RANK_21 ((uint32_t)0x00000015)
<>	149:156823d33999	578	#define ADC_REGULAR_RANK_22 ((uint32_t)0x00000016)
<>	149:156823d33999	579	#define ADC_REGULAR_RANK_23 ((uint32_t)0x00000017)
<>	149:156823d33999	580	#define ADC_REGULAR_RANK_24 ((uint32_t)0x00000018)
<>	149:156823d33999	581	#define ADC_REGULAR_RANK_25 ((uint32_t)0x00000019)
<>	149:156823d33999	582	#define ADC_REGULAR_RANK_26 ((uint32_t)0x0000001A)
<>	149:156823d33999	583	#define ADC_REGULAR_RANK_27 ((uint32_t)0x0000001B)
<>	149:156823d33999	584	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	585	#define ADC_REGULAR_RANK_28 ((uint32_t)0x0000001C)
<>	149:156823d33999	586	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	587	/**
<>	149:156823d33999	588	* @}
<>	149:156823d33999	589	*/
<>	149:156823d33999	590
<>	149:156823d33999	591	/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
<>	149:156823d33999	592	* @{
<>	149:156823d33999	593	*/
<>	149:156823d33999	594	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
<>	149:156823d33999	595	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN))
<>	149:156823d33999	596	#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_JAWDEN))
<>	149:156823d33999	597	#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL \| ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	149:156823d33999	598	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CR1_AWDEN)
<>	149:156823d33999	599	#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t) ADC_CR1_JAWDEN)
<>	149:156823d33999	600	#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN \| ADC_CR1_JAWDEN))
<>	149:156823d33999	601	/**
<>	149:156823d33999	602	* @}
<>	149:156823d33999	603	*/
<>	149:156823d33999	604
<>	149:156823d33999	605	/** @defgroup ADC_conversion_group ADC conversion group
<>	149:156823d33999	606	* @{
<>	149:156823d33999	607	*/
<>	149:156823d33999	608	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC))
<>	149:156823d33999	609	#define ADC_INJECTED_GROUP ((uint32_t)(ADC_FLAG_JEOC))
<>	149:156823d33999	610	#define ADC_REGULAR_INJECTED_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_JEOC))
<>	149:156823d33999	611	/**
<>	149:156823d33999	612	* @}
<>	149:156823d33999	613	*/
<>	149:156823d33999	614
<>	149:156823d33999	615	/** @defgroup ADC_Event_type ADC Event type
<>	149:156823d33999	616	* @{
<>	149:156823d33999	617	*/
<>	149:156823d33999	618	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) /!< ADC Analog watchdog event /
<>	149:156823d33999	619	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /!< ADC overrun event /
<>	149:156823d33999	620	/**
<>	149:156823d33999	621	* @}
<>	149:156823d33999	622	*/
<>	149:156823d33999	623
<>	149:156823d33999	624	/** @defgroup ADC_interrupts_definition ADC interrupts definition
<>	149:156823d33999	625	* @{
<>	149:156823d33999	626	*/
<>	149:156823d33999	627	#define ADC_IT_EOC ADC_CR1_EOCIE /!< ADC End of Regular Conversion interrupt source /
<>	149:156823d33999	628	#define ADC_IT_JEOC ADC_CR1_JEOCIE /!< ADC End of Injected Conversion interrupt source /
<>	149:156823d33999	629	#define ADC_IT_AWD ADC_CR1_AWDIE /!< ADC Analog watchdog interrupt source /
<>	149:156823d33999	630	#define ADC_IT_OVR ADC_CR1_OVRIE /!< ADC overrun interrupt source /
<>	149:156823d33999	631	/**
<>	149:156823d33999	632	* @}
<>	149:156823d33999	633	*/
<>	149:156823d33999	634
<>	149:156823d33999	635	/** @defgroup ADC_flags_definition ADC flags definition
<>	149:156823d33999	636	* @{
<>	149:156823d33999	637	*/
<>	149:156823d33999	638	#define ADC_FLAG_AWD ADC_SR_AWD /!< ADC Analog watchdog flag /
<>	149:156823d33999	639	#define ADC_FLAG_EOC ADC_SR_EOC /!< ADC End of Regular conversion flag /
<>	149:156823d33999	640	#define ADC_FLAG_JEOC ADC_SR_JEOC /!< ADC End of Injected conversion flag /
<>	149:156823d33999	641	#define ADC_FLAG_JSTRT ADC_SR_JSTRT /!< ADC Injected group start flag /
<>	149:156823d33999	642	#define ADC_FLAG_STRT ADC_SR_STRT /!< ADC Regular group start flag /
<>	149:156823d33999	643	#define ADC_FLAG_OVR ADC_SR_OVR /!< ADC overrun flag /
<>	149:156823d33999	644	#define ADC_FLAG_ADONS ADC_SR_ADONS /!< ADC ready status flag /
<>	149:156823d33999	645	#define ADC_FLAG_RCNR ADC_SR_RCNR /!< ADC Regular group ready status flag /
<>	149:156823d33999	646	#define ADC_FLAG_JCNR ADC_SR_JCNR /!< ADC Injected group ready status flag /
<>	149:156823d33999	647	/**
<>	149:156823d33999	648	* @}
<>	149:156823d33999	649	*/
<>	149:156823d33999	650
<>	149:156823d33999	651	/**
<>	149:156823d33999	652	* @}
<>	149:156823d33999	653	*/
<>	149:156823d33999	654
<>	149:156823d33999	655
<>	149:156823d33999	656	/* Private constants ---------------------------------------------------------*/
<>	149:156823d33999	657
<>	149:156823d33999	658	/** @addtogroup ADC_Private_Constants ADC Private Constants
<>	149:156823d33999	659	* @{
<>	149:156823d33999	660	*/
<>	149:156823d33999	661
<>	149:156823d33999	662	/* List of external triggers of regular group for ADC1: */
<>	149:156823d33999	663	/* (used internally by HAL driver. To not use into HAL structure parameters) */
<>	149:156823d33999	664
<>	149:156823d33999	665	/* External triggers of regular group for ADC1 */
<>	149:156823d33999	666	#define ADC_EXTERNALTRIG_T9_CC2 ((uint32_t) 0x00000000)
<>	149:156823d33999	667	#define ADC_EXTERNALTRIG_T9_TRGO ((uint32_t)( ADC_CR2_EXTSEL_0))
<>	149:156823d33999	668	#define ADC_EXTERNALTRIG_T2_CC3 ((uint32_t)( ADC_CR2_EXTSEL_1 ))
<>	149:156823d33999	669	#define ADC_EXTERNALTRIG_T2_CC2 ((uint32_t)( ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	149:156823d33999	670	#define ADC_EXTERNALTRIG_T3_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 ))
<>	149:156823d33999	671	#define ADC_EXTERNALTRIG_T4_CC4 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_0))
<>	149:156823d33999	672	#define ADC_EXTERNALTRIG_T2_TRGO ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 ))
<>	149:156823d33999	673	#define ADC_EXTERNALTRIG_T3_CC1 ((uint32_t)( ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	149:156823d33999	674	#define ADC_EXTERNALTRIG_T3_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 ))
<>	149:156823d33999	675	#define ADC_EXTERNALTRIG_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_0))
<>	149:156823d33999	676	#define ADC_EXTERNALTRIG_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_1 ))
<>	149:156823d33999	677	#define ADC_EXTERNALTRIG_EXT_IT11 ((uint32_t)(ADC_CR2_EXTSEL_3 \| ADC_CR2_EXTSEL_2 \| ADC_CR2_EXTSEL_1 \| ADC_CR2_EXTSEL_0))
<>	149:156823d33999	678
<>	149:156823d33999	679	/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
<>	149:156823d33999	680	#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC \| ADC_FLAG_JEOC \| ADC_FLAG_AWD \| \
<>	149:156823d33999	681	ADC_FLAG_OVR)
<>	149:156823d33999	682
<>	149:156823d33999	683	/**
<>	149:156823d33999	684	* @}
<>	149:156823d33999	685	*/
<>	149:156823d33999	686
<>	149:156823d33999	687
<>	149:156823d33999	688	/* Exported macro ------------------------------------------------------------*/
<>	149:156823d33999	689
<>	149:156823d33999	690	/** @defgroup ADC_Exported_Macros ADC Exported Macros
<>	149:156823d33999	691	* @{
<>	149:156823d33999	692	*/
<>	149:156823d33999	693	/* Macro for internal HAL driver usage, and possibly can be used into code of */
<>	149:156823d33999	694	/* final user. */
<>	149:156823d33999	695
<>	149:156823d33999	696	/**
<>	149:156823d33999	697	* @brief Enable the ADC peripheral
<>	149:156823d33999	698	* @param __HANDLE__: ADC handle
<>	149:156823d33999	699	* @retval None
<>	149:156823d33999	700	*/
<>	149:156823d33999	701	#define __HAL_ADC_ENABLE(__HANDLE__) \
<>	149:156823d33999	702	(__HANDLE__)->Instance->CR2 \|= ADC_CR2_ADON
<>	149:156823d33999	703
<>	149:156823d33999	704	/**
<>	149:156823d33999	705	* @brief Disable the ADC peripheral
<>	149:156823d33999	706	* @param __HANDLE__: ADC handle
<>	149:156823d33999	707	* @retval None
<>	149:156823d33999	708	*/
<>	149:156823d33999	709	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	149:156823d33999	710	(__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
<>	149:156823d33999	711
<>	149:156823d33999	712	/**
<>	149:156823d33999	713	* @brief Enable the ADC end of conversion interrupt.
<>	149:156823d33999	714	* @param __HANDLE__: ADC handle
<>	149:156823d33999	715	* @param __INTERRUPT__: ADC Interrupt
<>	149:156823d33999	716	* This parameter can be any combination of the following values:
<>	149:156823d33999	717	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	149:156823d33999	718	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	149:156823d33999	719	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	149:156823d33999	720	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	149:156823d33999	721	* @retval None
<>	149:156823d33999	722	*/
<>	149:156823d33999	723	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	149:156823d33999	724	(SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	149:156823d33999	725
<>	149:156823d33999	726	/**
<>	149:156823d33999	727	* @brief Disable the ADC end of conversion interrupt.
<>	149:156823d33999	728	* @param __HANDLE__: ADC handle
<>	149:156823d33999	729	* @param __INTERRUPT__: ADC Interrupt
<>	149:156823d33999	730	* This parameter can be any combination of the following values:
<>	149:156823d33999	731	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	149:156823d33999	732	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	149:156823d33999	733	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	149:156823d33999	734	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	149:156823d33999	735	* @retval None
<>	149:156823d33999	736	*/
<>	149:156823d33999	737	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	149:156823d33999	738	(CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
<>	149:156823d33999	739
<>	149:156823d33999	740	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	149:156823d33999	741	* @param __HANDLE__: ADC handle
<>	149:156823d33999	742	* @param __INTERRUPT__: ADC interrupt source to check
<>	149:156823d33999	743	* This parameter can be any combination of the following values:
<>	149:156823d33999	744	* @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
<>	149:156823d33999	745	* @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
<>	149:156823d33999	746	* @arg ADC_IT_AWD: ADC Analog watchdog interrupt source
<>	149:156823d33999	747	* @arg ADC_IT_OVR: ADC overrun interrupt source
<>	149:156823d33999	748	* @retval State of interruption (SET or RESET)
<>	149:156823d33999	749	*/
<>	149:156823d33999	750	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	149:156823d33999	751	(((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
<>	149:156823d33999	752
<>	149:156823d33999	753	/**
<>	149:156823d33999	754	* @brief Get the selected ADC's flag status.
<>	149:156823d33999	755	* @param __HANDLE__: ADC handle
<>	149:156823d33999	756	* @param __FLAG__: ADC flag
<>	149:156823d33999	757	* This parameter can be any combination of the following values:
<>	149:156823d33999	758	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	149:156823d33999	759	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	149:156823d33999	760	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	149:156823d33999	761	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	149:156823d33999	762	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	149:156823d33999	763	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	149:156823d33999	764	* @arg ADC_FLAG_ADONS: ADC ready status flag
<>	149:156823d33999	765	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<>	149:156823d33999	766	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<>	149:156823d33999	767	* @retval None
<>	149:156823d33999	768	*/
<>	149:156823d33999	769	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	149:156823d33999	770	((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
<>	149:156823d33999	771
<>	149:156823d33999	772	/**
<>	149:156823d33999	773	* @brief Clear the ADC's pending flags
<>	149:156823d33999	774	* @param __HANDLE__: ADC handle
<>	149:156823d33999	775	* @param __FLAG__: ADC flag
<>	149:156823d33999	776	* @arg ADC_FLAG_STRT: ADC Regular group start flag
<>	149:156823d33999	777	* @arg ADC_FLAG_JSTRT: ADC Injected group start flag
<>	149:156823d33999	778	* @arg ADC_FLAG_EOC: ADC End of Regular conversion flag
<>	149:156823d33999	779	* @arg ADC_FLAG_JEOC: ADC End of Injected conversion flag
<>	149:156823d33999	780	* @arg ADC_FLAG_AWD: ADC Analog watchdog flag
<>	149:156823d33999	781	* @arg ADC_FLAG_OVR: ADC overrun flag
<>	149:156823d33999	782	* @arg ADC_FLAG_ADONS: ADC ready status flag
<>	149:156823d33999	783	* @arg ADC_FLAG_RCNR: ADC Regular group ready status flag
<>	149:156823d33999	784	* @arg ADC_FLAG_JCNR: ADC Injected group ready status flag
<>	149:156823d33999	785	* @retval None
<>	149:156823d33999	786	*/
<>	149:156823d33999	787	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	149:156823d33999	788	(((__HANDLE__)->Instance->SR) = ~(__FLAG__))
<>	149:156823d33999	789
<>	149:156823d33999	790	/** @brief Reset ADC handle state
<>	149:156823d33999	791	* @param __HANDLE__: ADC handle
<>	149:156823d33999	792	* @retval None
<>	149:156823d33999	793	*/
<>	149:156823d33999	794	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
<>	149:156823d33999	795	((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	149:156823d33999	796
<>	149:156823d33999	797	/**
<>	149:156823d33999	798	* @}
<>	149:156823d33999	799	*/
<>	149:156823d33999	800
<>	149:156823d33999	801	/* Private macro ------------------------------------------------------------*/
<>	149:156823d33999	802
<>	149:156823d33999	803	/** @defgroup ADC_Private_Macros ADC Private Macros
<>	149:156823d33999	804	* @{
<>	149:156823d33999	805	*/
<>	149:156823d33999	806	/* Macro reserved for internal HAL driver usage, not intended to be used in */
<>	149:156823d33999	807	/* code of final user. */
<>	149:156823d33999	808
<>	149:156823d33999	809	/**
<>	149:156823d33999	810	* @brief Verification of ADC state: enabled or disabled
<>	149:156823d33999	811	* @param __HANDLE__: ADC handle
<>	149:156823d33999	812	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	149:156823d33999	813	*/
<>	149:156823d33999	814	#define ADC_IS_ENABLE(__HANDLE__) \
<>	149:156823d33999	815	((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
<>	149:156823d33999	816	) ? SET : RESET)
<>	149:156823d33999	817
<>	149:156823d33999	818	/**
<>	149:156823d33999	819	* @brief Test if conversion trigger of regular group is software start
<>	149:156823d33999	820	* or external trigger.
<>	149:156823d33999	821	* @param __HANDLE__: ADC handle
<>	149:156823d33999	822	* @retval SET (software start) or RESET (external trigger)
<>	149:156823d33999	823	*/
<>	149:156823d33999	824	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	149:156823d33999	825	(((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
<>	149:156823d33999	826
<>	149:156823d33999	827	/**
<>	149:156823d33999	828	* @brief Test if conversion trigger of injected group is software start
<>	149:156823d33999	829	* or external trigger.
<>	149:156823d33999	830	* @param __HANDLE__: ADC handle
<>	149:156823d33999	831	* @retval SET (software start) or RESET (external trigger)
<>	149:156823d33999	832	*/
<>	149:156823d33999	833	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
<>	149:156823d33999	834	(((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
<>	149:156823d33999	835
<>	149:156823d33999	836	/**
<>	149:156823d33999	837	* @brief Simultaneously clears and sets specific bits of the handle State
<>	149:156823d33999	838	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	149:156823d33999	839	* the first parameter is the ADC handle State, the second parameter is the
<>	149:156823d33999	840	* bit field to clear, the third and last parameter is the bit field to set.
<>	149:156823d33999	841	* @retval None
<>	149:156823d33999	842	*/
<>	149:156823d33999	843	#define ADC_STATE_CLR_SET MODIFY_REG
<>	149:156823d33999	844
<>	149:156823d33999	845	/**
<>	149:156823d33999	846	* @brief Clear ADC error code (set it to error code: "no error")
<>	149:156823d33999	847	* @param __HANDLE__: ADC handle
<>	149:156823d33999	848	* @retval None
<>	149:156823d33999	849	*/
<>	149:156823d33999	850	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	149:156823d33999	851	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	149:156823d33999	852
<>	149:156823d33999	853	/**
<>	149:156823d33999	854	* @brief Set ADC number of ranks into regular channel sequence length.
<>	149:156823d33999	855	* @param _NbrOfConversion_: Regular channel sequence length
<>	149:156823d33999	856	* @retval None
<>	149:156823d33999	857	*/
<>	149:156823d33999	858	#define ADC_SQR1_L_SHIFT(_NbrOfConversion_) \
<>	149:156823d33999	859	(((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
<>	149:156823d33999	860
<>	149:156823d33999	861	/**
<>	149:156823d33999	862	* @brief Set the ADC's sample time for channel numbers between 10 and 18.
<>	149:156823d33999	863	* @param _SAMPLETIME_: Sample time parameter.
<>	149:156823d33999	864	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	865	* @retval None
<>	149:156823d33999	866	*/
<>	149:156823d33999	867	#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) \
<>	149:156823d33999	868	((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
<>	149:156823d33999	869
<>	149:156823d33999	870	/**
<>	149:156823d33999	871	* @brief Set the ADC's sample time for channel numbers between 0 and 9.
<>	149:156823d33999	872	* @param _SAMPLETIME_: Sample time parameter.
<>	149:156823d33999	873	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	874	* @retval None
<>	149:156823d33999	875	*/
<>	149:156823d33999	876	#define ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) \
<>	149:156823d33999	877	((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
<>	149:156823d33999	878
<>	149:156823d33999	879	/**
<>	149:156823d33999	880	* @brief Set the selected regular channel rank for rank between 1 and 6.
<>	149:156823d33999	881	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	882	* @param _RANKNB_: Rank number.
<>	149:156823d33999	883	* @retval None
<>	149:156823d33999	884	*/
<>	149:156823d33999	885	#define ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) \
<>	149:156823d33999	886	((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
<>	149:156823d33999	887
<>	149:156823d33999	888	/**
<>	149:156823d33999	889	* @brief Set the selected regular channel rank for rank between 7 and 12.
<>	149:156823d33999	890	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	891	* @param _RANKNB_: Rank number.
<>	149:156823d33999	892	* @retval None
<>	149:156823d33999	893	*/
<>	149:156823d33999	894	#define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) \
<>	149:156823d33999	895	((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
<>	149:156823d33999	896
<>	149:156823d33999	897	/**
<>	149:156823d33999	898	* @brief Set the selected regular channel rank for rank between 13 and 18.
<>	149:156823d33999	899	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	900	* @param _RANKNB_: Rank number.
<>	149:156823d33999	901	* @retval None
<>	149:156823d33999	902	*/
<>	149:156823d33999	903	#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) \
<>	149:156823d33999	904	((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
<>	149:156823d33999	905
<>	149:156823d33999	906	/**
<>	149:156823d33999	907	* @brief Set the selected regular channel rank for rank between 19 and 24.
<>	149:156823d33999	908	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	909	* @param _RANKNB_: Rank number.
<>	149:156823d33999	910	* @retval None
<>	149:156823d33999	911	*/
<>	149:156823d33999	912	#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) \
<>	149:156823d33999	913	((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
<>	149:156823d33999	914
<>	149:156823d33999	915	/**
<>	149:156823d33999	916	* @brief Set the selected regular channel rank for rank between 25 and 28.
<>	149:156823d33999	917	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	918	* @param _RANKNB_: Rank number.
<>	149:156823d33999	919	* @retval None
<>	149:156823d33999	920	*/
<>	149:156823d33999	921	#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) \
<>	149:156823d33999	922	((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
<>	149:156823d33999	923
<>	149:156823d33999	924	/**
<>	149:156823d33999	925	* @brief Set the injected sequence length.
<>	149:156823d33999	926	* @param _JSQR_JL_: Sequence length.
<>	149:156823d33999	927	* @retval None
<>	149:156823d33999	928	*/
<>	149:156823d33999	929	#define ADC_JSQR_JL_SHIFT(_JSQR_JL_) (((_JSQR_JL_) -1) << 20)
<>	149:156823d33999	930
<>	149:156823d33999	931	/**
<>	149:156823d33999	932	* @brief Set the selected injected channel rank
<>	149:156823d33999	933	* Note: on STM32L1 devices, channel rank position in JSQR register
<>	149:156823d33999	934	* is depending on total number of ranks selected into
<>	149:156823d33999	935	* injected sequencer (ranks sequence starting from 4-JL)
<>	149:156823d33999	936	* @param _CHANNELNB_: Channel number.
<>	149:156823d33999	937	* @param _RANKNB_: Rank number.
<>	149:156823d33999	938	* @param _JSQR_JL_: Sequence length.
<>	149:156823d33999	939	* @retval None
<>	149:156823d33999	940	*/
<>	149:156823d33999	941	#define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_) \
<>	149:156823d33999	942	((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
<>	149:156823d33999	943
<>	149:156823d33999	944	/**
<>	149:156823d33999	945	* @brief Enable the ADC DMA continuous request.
<>	149:156823d33999	946	* @param _DMACONTREQ_MODE_: DMA continuous request mode.
<>	149:156823d33999	947	* @retval None
<>	149:156823d33999	948	*/
<>	149:156823d33999	949	#define ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) \
<>	149:156823d33999	950	((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
<>	149:156823d33999	951
<>	149:156823d33999	952	/**
<>	149:156823d33999	953	* @brief Enable ADC continuous conversion mode.
<>	149:156823d33999	954	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	149:156823d33999	955	* @retval None
<>	149:156823d33999	956	*/
<>	149:156823d33999	957	#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) \
<>	149:156823d33999	958	((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
<>	149:156823d33999	959
<>	149:156823d33999	960	/**
<>	149:156823d33999	961	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	149:156823d33999	962	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	149:156823d33999	963	* @retval None
<>	149:156823d33999	964	*/
<>	149:156823d33999	965	#define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) \
<>	149:156823d33999	966	(((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
<>	149:156823d33999	967
<>	149:156823d33999	968	/**
<>	149:156823d33999	969	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<>	149:156823d33999	970	* @param _SCAN_MODE_: Scan conversion mode.
<>	149:156823d33999	971	* @retval None
<>	149:156823d33999	972	*/
<>	149:156823d33999	973	/* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter */
<>	149:156823d33999	974	/* is equivalent to ADC_SCAN_ENABLE. */
<>	149:156823d33999	975	#define ADC_CR1_SCAN_SET(_SCAN_MODE_) \
<>	149:156823d33999	976	(( ((_SCAN_MODE_) == ADC_SCAN_ENABLE) \|\| ((_SCAN_MODE_) == ENABLE) \
<>	149:156823d33999	977	)? (ADC_SCAN_ENABLE) : (ADC_SCAN_DISABLE) \
<>	149:156823d33999	978	)
<>	149:156823d33999	979
<>	149:156823d33999	980
<>	149:156823d33999	981	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\| \
<>	149:156823d33999	982	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) \|\| \
<>	149:156823d33999	983	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4) )
<>	149:156823d33999	984
<>	149:156823d33999	985	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
<>	149:156823d33999	986	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
<>	149:156823d33999	987	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	149:156823d33999	988	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	149:156823d33999	989
<>	149:156823d33999	990	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	149:156823d33999	991	((RESOLUTION) == ADC_RESOLUTION_6B) )
<>	149:156823d33999	992
<>	149:156823d33999	993	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	149:156823d33999	994	((ALIGN) == ADC_DATAALIGN_LEFT) )
<>	149:156823d33999	995
<>	149:156823d33999	996	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) \|\| \
<>	149:156823d33999	997	((SCAN_MODE) == ADC_SCAN_ENABLE) )
<>	149:156823d33999	998
<>	149:156823d33999	999	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	149:156823d33999	1000	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	149:156823d33999	1001	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	149:156823d33999	1002	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
<>	149:156823d33999	1003
<>	149:156823d33999	1004	#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) \|\| \
<>	149:156823d33999	1005	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) \|\| \
<>	149:156823d33999	1006	((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) \|\| \
<>	149:156823d33999	1007	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) \|\| \
<>	149:156823d33999	1008	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3) \|\| \
<>	149:156823d33999	1009	((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) \|\| \
<>	149:156823d33999	1010	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) \|\| \
<>	149:156823d33999	1011	((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO) \|\| \
<>	149:156823d33999	1012	((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO) \|\| \
<>	149:156823d33999	1013	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2) \|\| \
<>	149:156823d33999	1014	((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO) \|\| \
<>	149:156823d33999	1015	((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) \|\| \
<>	149:156823d33999	1016	((REGTRIG) == ADC_SOFTWARE_START) )
<>	149:156823d33999	1017
<>	149:156823d33999	1018	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
<>	149:156823d33999	1019	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) )
<>	149:156823d33999	1020
<>	149:156823d33999	1021	#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE) \|\| \
<>	149:156823d33999	1022	((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ) \|\| \
<>	149:156823d33999	1023	((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES) \|\| \
<>	149:156823d33999	1024	((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES) \|\| \
<>	149:156823d33999	1025	((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES) \|\| \
<>	149:156823d33999	1026	((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES) \|\| \
<>	149:156823d33999	1027	((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) \|\| \
<>	149:156823d33999	1028	((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES) )
<>	149:156823d33999	1029
<>	149:156823d33999	1030	#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE) \|\| \
<>	149:156823d33999	1031	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE) \|\| \
<>	149:156823d33999	1032	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE) \|\| \
<>	149:156823d33999	1033	((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES) )
<>	149:156823d33999	1034
<>	149:156823d33999	1035	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	1036
<>	149:156823d33999	1037	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) \|\| \
<>	149:156823d33999	1038	((BANK) == ADC_CHANNELS_BANK_B) )
<>	149:156823d33999	1039	#else
<>	149:156823d33999	1040
<>	149:156823d33999	1041	#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
<>	149:156823d33999	1042	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	1043
<>	149:156823d33999	1044	#if defined(STM32L100xB) \|\| defined (STM32L151xB) \|\| defined (STM32L152xB) \|\| defined(STM32L100xBA) \|\| defined (STM32L151xBA) \|\| defined (STM32L152xBA) \|\| defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC)
<>	149:156823d33999	1045	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	149:156823d33999	1046	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	149:156823d33999	1047	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	149:156823d33999	1048	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	149:156823d33999	1049	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	149:156823d33999	1050	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	149:156823d33999	1051	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	149:156823d33999	1052	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	149:156823d33999	1053	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	149:156823d33999	1054	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	149:156823d33999	1055	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	149:156823d33999	1056	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	149:156823d33999	1057	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	149:156823d33999	1058	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	149:156823d33999	1059	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	149:156823d33999	1060	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	149:156823d33999	1061	((CHANNEL) == ADC_CHANNEL_16) \|\| \
<>	149:156823d33999	1062	((CHANNEL) == ADC_CHANNEL_17) \|\| \
<>	149:156823d33999	1063	((CHANNEL) == ADC_CHANNEL_18) \|\| \
<>	149:156823d33999	1064	((CHANNEL) == ADC_CHANNEL_19) \|\| \
<>	149:156823d33999	1065	((CHANNEL) == ADC_CHANNEL_20) \|\| \
<>	149:156823d33999	1066	((CHANNEL) == ADC_CHANNEL_21) \|\| \
<>	149:156823d33999	1067	((CHANNEL) == ADC_CHANNEL_22) \|\| \
<>	149:156823d33999	1068	((CHANNEL) == ADC_CHANNEL_23) \|\| \
<>	149:156823d33999	1069	((CHANNEL) == ADC_CHANNEL_24) \|\| \
<>	149:156823d33999	1070	((CHANNEL) == ADC_CHANNEL_25) \|\| \
<>	149:156823d33999	1071	((CHANNEL) == ADC_CHANNEL_26) )
<>	149:156823d33999	1072	#endif /* STM32L100xB \|\| STM32L151xB \|\| STM32L152xB \|\| STM32L100xBA \|\| STM32L151xBA \|\| STM32L152xBA \|\| STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC */
<>	149:156823d33999	1073	#if defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	1074	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	149:156823d33999	1075	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	149:156823d33999	1076	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	149:156823d33999	1077	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	149:156823d33999	1078	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	149:156823d33999	1079	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	149:156823d33999	1080	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	149:156823d33999	1081	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	149:156823d33999	1082	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	149:156823d33999	1083	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	149:156823d33999	1084	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	149:156823d33999	1085	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	149:156823d33999	1086	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	149:156823d33999	1087	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	149:156823d33999	1088	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	149:156823d33999	1089	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	149:156823d33999	1090	((CHANNEL) == ADC_CHANNEL_16) \|\| \
<>	149:156823d33999	1091	((CHANNEL) == ADC_CHANNEL_17) \|\| \
<>	149:156823d33999	1092	((CHANNEL) == ADC_CHANNEL_18) \|\| \
<>	149:156823d33999	1093	((CHANNEL) == ADC_CHANNEL_19) \|\| \
<>	149:156823d33999	1094	((CHANNEL) == ADC_CHANNEL_20) \|\| \
<>	149:156823d33999	1095	((CHANNEL) == ADC_CHANNEL_21) \|\| \
<>	149:156823d33999	1096	((CHANNEL) == ADC_CHANNEL_22) \|\| \
<>	149:156823d33999	1097	((CHANNEL) == ADC_CHANNEL_23) \|\| \
<>	149:156823d33999	1098	((CHANNEL) == ADC_CHANNEL_24) \|\| \
<>	149:156823d33999	1099	((CHANNEL) == ADC_CHANNEL_25) \|\| \
<>	149:156823d33999	1100	((CHANNEL) == ADC_CHANNEL_26) \|\| \
<>	149:156823d33999	1101	((CHANNEL) == ADC_CHANNEL_27) \|\| \
<>	149:156823d33999	1102	((CHANNEL) == ADC_CHANNEL_28) \|\| \
<>	149:156823d33999	1103	((CHANNEL) == ADC_CHANNEL_29) \|\| \
<>	149:156823d33999	1104	((CHANNEL) == ADC_CHANNEL_30) \|\| \
<>	149:156823d33999	1105	((CHANNEL) == ADC_CHANNEL_31) )
<>	149:156823d33999	1106	#endif /* STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	1107
<>	149:156823d33999	1108	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES) \|\| \
<>	149:156823d33999	1109	((TIME) == ADC_SAMPLETIME_9CYCLES) \|\| \
<>	149:156823d33999	1110	((TIME) == ADC_SAMPLETIME_16CYCLES) \|\| \
<>	149:156823d33999	1111	((TIME) == ADC_SAMPLETIME_24CYCLES) \|\| \
<>	149:156823d33999	1112	((TIME) == ADC_SAMPLETIME_48CYCLES) \|\| \
<>	149:156823d33999	1113	((TIME) == ADC_SAMPLETIME_96CYCLES) \|\| \
<>	149:156823d33999	1114	((TIME) == ADC_SAMPLETIME_192CYCLES) \|\| \
<>	149:156823d33999	1115	((TIME) == ADC_SAMPLETIME_384CYCLES) )
<>	149:156823d33999	1116
<>	149:156823d33999	1117	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	1118
<>	149:156823d33999	1119	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	149:156823d33999	1120	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	149:156823d33999	1121	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	149:156823d33999	1122	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	149:156823d33999	1123	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	149:156823d33999	1124	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	149:156823d33999	1125	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	149:156823d33999	1126	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	149:156823d33999	1127	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	149:156823d33999	1128	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	149:156823d33999	1129	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	149:156823d33999	1130	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	149:156823d33999	1131	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	149:156823d33999	1132	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	149:156823d33999	1133	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	149:156823d33999	1134	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
<>	149:156823d33999	1135	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
<>	149:156823d33999	1136	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
<>	149:156823d33999	1137	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
<>	149:156823d33999	1138	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
<>	149:156823d33999	1139	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
<>	149:156823d33999	1140	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
<>	149:156823d33999	1141	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
<>	149:156823d33999	1142	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
<>	149:156823d33999	1143	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
<>	149:156823d33999	1144	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
<>	149:156823d33999	1145	((CHANNEL) == ADC_REGULAR_RANK_27) \|\| \
<>	149:156823d33999	1146	((CHANNEL) == ADC_REGULAR_RANK_28) )
<>	149:156823d33999	1147	#else
<>	149:156823d33999	1148
<>	149:156823d33999	1149	#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) \|\| \
<>	149:156823d33999	1150	((CHANNEL) == ADC_REGULAR_RANK_2 ) \|\| \
<>	149:156823d33999	1151	((CHANNEL) == ADC_REGULAR_RANK_3 ) \|\| \
<>	149:156823d33999	1152	((CHANNEL) == ADC_REGULAR_RANK_4 ) \|\| \
<>	149:156823d33999	1153	((CHANNEL) == ADC_REGULAR_RANK_5 ) \|\| \
<>	149:156823d33999	1154	((CHANNEL) == ADC_REGULAR_RANK_6 ) \|\| \
<>	149:156823d33999	1155	((CHANNEL) == ADC_REGULAR_RANK_7 ) \|\| \
<>	149:156823d33999	1156	((CHANNEL) == ADC_REGULAR_RANK_8 ) \|\| \
<>	149:156823d33999	1157	((CHANNEL) == ADC_REGULAR_RANK_9 ) \|\| \
<>	149:156823d33999	1158	((CHANNEL) == ADC_REGULAR_RANK_10) \|\| \
<>	149:156823d33999	1159	((CHANNEL) == ADC_REGULAR_RANK_11) \|\| \
<>	149:156823d33999	1160	((CHANNEL) == ADC_REGULAR_RANK_12) \|\| \
<>	149:156823d33999	1161	((CHANNEL) == ADC_REGULAR_RANK_13) \|\| \
<>	149:156823d33999	1162	((CHANNEL) == ADC_REGULAR_RANK_14) \|\| \
<>	149:156823d33999	1163	((CHANNEL) == ADC_REGULAR_RANK_15) \|\| \
<>	149:156823d33999	1164	((CHANNEL) == ADC_REGULAR_RANK_16) \|\| \
<>	149:156823d33999	1165	((CHANNEL) == ADC_REGULAR_RANK_17) \|\| \
<>	149:156823d33999	1166	((CHANNEL) == ADC_REGULAR_RANK_18) \|\| \
<>	149:156823d33999	1167	((CHANNEL) == ADC_REGULAR_RANK_19) \|\| \
<>	149:156823d33999	1168	((CHANNEL) == ADC_REGULAR_RANK_20) \|\| \
<>	149:156823d33999	1169	((CHANNEL) == ADC_REGULAR_RANK_21) \|\| \
<>	149:156823d33999	1170	((CHANNEL) == ADC_REGULAR_RANK_22) \|\| \
<>	149:156823d33999	1171	((CHANNEL) == ADC_REGULAR_RANK_23) \|\| \
<>	149:156823d33999	1172	((CHANNEL) == ADC_REGULAR_RANK_24) \|\| \
<>	149:156823d33999	1173	((CHANNEL) == ADC_REGULAR_RANK_25) \|\| \
<>	149:156823d33999	1174	((CHANNEL) == ADC_REGULAR_RANK_26) \|\| \
<>	149:156823d33999	1175	((CHANNEL) == ADC_REGULAR_RANK_27) )
<>	149:156823d33999	1176	#endif /* STM32L100xC \|\| STM32L151xC \|\| STM32L152xC \|\| STM32L162xC \|\| STM32L151xCA \|\| STM32L151xD \|\| STM32L152xCA \|\| STM32L152xD \|\| STM32L162xCA \|\| STM32L162xD \|\| STM32L151xE \|\| STM32L151xDX \|\| STM32L152xE \|\| STM32L152xDX \|\| STM32L162xE \|\| STM32L162xDX */
<>	149:156823d33999	1177
<>	149:156823d33999	1178	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) \|\| \
<>	149:156823d33999	1179	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	149:156823d33999	1180	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
<>	149:156823d33999	1181	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
<>	149:156823d33999	1182	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
<>	149:156823d33999	1183	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
<>	149:156823d33999	1184	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
<>	149:156823d33999	1185
<>	149:156823d33999	1186	#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == ADC_REGULAR_GROUP) \|\| \
<>	149:156823d33999	1187	((CONVERSION) == ADC_INJECTED_GROUP) \|\| \
<>	149:156823d33999	1188	((CONVERSION) == ADC_REGULAR_INJECTED_GROUP) )
<>	149:156823d33999	1189
<>	149:156823d33999	1190	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
<>	149:156823d33999	1191	((EVENT) == ADC_FLAG_OVR) )
<>	149:156823d33999	1192
<>	149:156823d33999	1193	/**
<>	149:156823d33999	1194	* @brief Verify that a ADC data is within range corresponding to
<>	149:156823d33999	1195	* ADC resolution.
<>	149:156823d33999	1196	* @param __RESOLUTION__: ADC resolution (12, 10, 8 or 6 bits).
<>	149:156823d33999	1197	* @param __ADC_DATA__: value checked against the resolution.
<>	149:156823d33999	1198	* @retval SET: ADC data is within range corresponding to ADC resolution
<>	149:156823d33999	1199	* RESET: ADC data is not within range corresponding to ADC resolution
<>	149:156823d33999	1200	*
<>	149:156823d33999	1201	*/
<>	149:156823d33999	1202	#define IS_ADC_RANGE(__RESOLUTION__, __ADC_DATA__) \
<>	149:156823d33999	1203	((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_DATA__) <= ((uint32_t)0x0FFF))) \|\| \
<>	149:156823d33999	1204	(((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_DATA__) <= ((uint32_t)0x03FF))) \|\| \
<>	149:156823d33999	1205	(((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_DATA__) <= ((uint32_t)0x00FF))) \|\| \
<>	149:156823d33999	1206	(((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_DATA__) <= ((uint32_t)0x003F))) )
<>	149:156823d33999	1207
<>	149:156823d33999	1208
<>	149:156823d33999	1209	#if defined(STM32L100xC) \|\| defined (STM32L151xC) \|\| defined (STM32L152xC) \|\| defined (STM32L162xC) \|\| defined(STM32L151xCA) \|\| defined (STM32L151xD) \|\| defined (STM32L152xCA) \|\| defined (STM32L152xD) \|\| defined (STM32L162xCA) \|\| defined (STM32L162xD) \|\| defined(STM32L151xE) \|\| defined(STM32L151xDX) \|\| defined (STM32L152xE) \|\| defined (STM32L152xDX) \|\| defined (STM32L162xE) \|\| defined (STM32L162xDX)
<>	149:156823d33999	1210	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
<>	149:156823d33999	1211	#else
<>	149:156823d33999	1212	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
<>	149:156823d33999	1213	#endif
<>	149:156823d33999	1214
<>	149:156823d33999	1215	#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
<>	149:156823d33999	1216
<>	149:156823d33999	1217	/**
<>	149:156823d33999	1218	* @}
<>	149:156823d33999	1219	*/
<>	149:156823d33999	1220
<>	149:156823d33999	1221
<>	149:156823d33999	1222	/* Include ADC HAL Extension module */
<>	149:156823d33999	1223	#include "stm32l1xx_hal_adc_ex.h"
<>	149:156823d33999	1224
<>	149:156823d33999	1225	/* Exported functions --------------------------------------------------------*/
<>	149:156823d33999	1226	/** @addtogroup ADC_Exported_Functions
<>	149:156823d33999	1227	* @{
<>	149:156823d33999	1228	*/
<>	149:156823d33999	1229
<>	149:156823d33999	1230	/** @addtogroup ADC_Exported_Functions_Group1
<>	149:156823d33999	1231	* @{
<>	149:156823d33999	1232	*/
<>	149:156823d33999	1233
<>	149:156823d33999	1234
<>	149:156823d33999	1235	/* Initialization and de-initialization functions **********************************/
<>	149:156823d33999	1236	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1237	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<>	149:156823d33999	1238	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1239	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1240	/**
<>	149:156823d33999	1241	* @}
<>	149:156823d33999	1242	*/
<>	149:156823d33999	1243
<>	149:156823d33999	1244	/* IO operation functions *****************************************************/
<>	149:156823d33999	1245
<>	149:156823d33999	1246	/** @addtogroup ADC_Exported_Functions_Group2
<>	149:156823d33999	1247	* @{
<>	149:156823d33999	1248	*/
<>	149:156823d33999	1249
<>	149:156823d33999	1250
<>	149:156823d33999	1251	/* Blocking mode: Polling */
<>	149:156823d33999	1252	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1253	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1254	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	149:156823d33999	1255	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<>	149:156823d33999	1256
<>	149:156823d33999	1257	/* Non-blocking mode: Interruption */
<>	149:156823d33999	1258	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1259	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1260
<>	149:156823d33999	1261	/* Non-blocking mode: DMA */
<>	149:156823d33999	1262	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<>	149:156823d33999	1263	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1264
<>	149:156823d33999	1265	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	149:156823d33999	1266	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1267
<>	149:156823d33999	1268	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<>	149:156823d33999	1269	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1270	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1271	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1272	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1273	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<>	149:156823d33999	1274	/**
<>	149:156823d33999	1275	* @}
<>	149:156823d33999	1276	*/
<>	149:156823d33999	1277
<>	149:156823d33999	1278
<>	149:156823d33999	1279	/* Peripheral Control functions ***********************************************/
<>	149:156823d33999	1280	/** @addtogroup ADC_Exported_Functions_Group3
<>	149:156823d33999	1281	* @{
<>	149:156823d33999	1282	*/
<>	149:156823d33999	1283	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<>	149:156823d33999	1284	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<>	149:156823d33999	1285	/**
<>	149:156823d33999	1286	* @}
<>	149:156823d33999	1287	*/
<>	149:156823d33999	1288
<>	149:156823d33999	1289
<>	149:156823d33999	1290	/* Peripheral State functions *************************************************/
<>	149:156823d33999	1291	/** @addtogroup ADC_Exported_Functions_Group4
<>	149:156823d33999	1292	* @{
<>	149:156823d33999	1293	*/
<>	149:156823d33999	1294	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1295	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<>	149:156823d33999	1296	/**
<>	149:156823d33999	1297	* @}
<>	149:156823d33999	1298	*/
<>	149:156823d33999	1299
<>	149:156823d33999	1300
<>	149:156823d33999	1301	/**
<>	149:156823d33999	1302	* @}
<>	149:156823d33999	1303	*/
<>	149:156823d33999	1304
<>	149:156823d33999	1305
<>	149:156823d33999	1306	/* Internal HAL driver functions **********************************************/
<>	149:156823d33999	1307	/** @addtogroup ADC_Private_Functions
<>	149:156823d33999	1308	* @{
<>	149:156823d33999	1309	*/
<>	149:156823d33999	1310
<>	149:156823d33999	1311	HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1312	HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
<>	149:156823d33999	1313	/**
<>	149:156823d33999	1314	* @}
<>	149:156823d33999	1315	*/
<>	149:156823d33999	1316
<>	149:156823d33999	1317
<>	149:156823d33999	1318	/**
<>	149:156823d33999	1319	* @}
<>	149:156823d33999	1320	*/
<>	149:156823d33999	1321
<>	149:156823d33999	1322	/**
<>	149:156823d33999	1323	* @}
<>	149:156823d33999	1324	*/
<>	149:156823d33999	1325
<>	149:156823d33999	1326	#ifdef __cplusplus
<>	149:156823d33999	1327	}
<>	149:156823d33999	1328	#endif
<>	149:156823d33999	1329
<>	149:156823d33999	1330
<>	149:156823d33999	1331	#endif /* __STM32L1xx_HAL_ADC_H */
<>	149:156823d33999	1332
<>	149:156823d33999	1333	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/