mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim_ex.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h@144:ef7eb2e8f9f7
Child:
151:5eaa88a5bcc7
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_tim_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of TIM HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L0xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L0xx_HAL_TIM_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup TIM_Exported_Types TIM Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 /**
<> 144:ef7eb2e8f9f7 62 * @brief TIM Master configuration Structure definition
<> 144:ef7eb2e8f9f7 63 */
<> 144:ef7eb2e8f9f7 64 typedef struct {
<> 144:ef7eb2e8f9f7 65 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
<> 144:ef7eb2e8f9f7 66 This parameter can be a value of @ref TIM_Master_Mode_Selection */
<> 144:ef7eb2e8f9f7 67 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
<> 144:ef7eb2e8f9f7 68 This parameter can be a value of @ref TIM_Master_Slave_Mode */
<> 144:ef7eb2e8f9f7 69 }TIM_MasterConfigTypeDef;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /**
<> 144:ef7eb2e8f9f7 72 * @}
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 /** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants
<> 144:ef7eb2e8f9f7 77 * @{
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /** @defgroup TIMEx_Trigger_Selection Trigger selection
<> 144:ef7eb2e8f9f7 81 * @{
<> 144:ef7eb2e8f9f7 82 */
<> 144:ef7eb2e8f9f7 83 #define TIM_TRGO_RESET ((uint32_t)0x0000)
<> 144:ef7eb2e8f9f7 84 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
<> 144:ef7eb2e8f9f7 85 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
<> 144:ef7eb2e8f9f7 86 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 87 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
<> 144:ef7eb2e8f9f7 88 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 89 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
<> 144:ef7eb2e8f9f7 90 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
<> 144:ef7eb2e8f9f7 93 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
<> 144:ef7eb2e8f9f7 94 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
<> 144:ef7eb2e8f9f7 95 ((__SOURCE__) == TIM_TRGO_OC1) || \
<> 144:ef7eb2e8f9f7 96 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
<> 144:ef7eb2e8f9f7 97 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
<> 144:ef7eb2e8f9f7 98 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
<> 144:ef7eb2e8f9f7 99 ((__SOURCE__) == TIM_TRGO_OC4REF))
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /**
<> 144:ef7eb2e8f9f7 102 * @}
<> 144:ef7eb2e8f9f7 103 */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @defgroup TIMEx_Remap Remaping
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
<> 144:ef7eb2e8f9f7 109 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define TIM2_ETR_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 112 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
<> 144:ef7eb2e8f9f7 113 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
<> 144:ef7eb2e8f9f7 114 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
<> 144:ef7eb2e8f9f7 115 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
<> 144:ef7eb2e8f9f7 116 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 #elif defined (STM32L011xx) || defined (STM32L021xx) || defined (STM32L031xx) || defined (STM32L041xx)
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 #define TIM2_ETR_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 121 #define TIM2_ETR_HSI16 (TIM2_OR_ETR_RMP_1 | TIM2_OR_ETR_RMP_0)
<> 144:ef7eb2e8f9f7 122 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
<> 144:ef7eb2e8f9f7 123 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
<> 144:ef7eb2e8f9f7 124 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 #else
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #define TIM2_ETR_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 129 #define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2
<> 144:ef7eb2e8f9f7 130 #define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0)
<> 144:ef7eb2e8f9f7 131 #define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1)
<> 144:ef7eb2e8f9f7 132 #define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #define TIM2_TI4_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 139 #define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0
<> 144:ef7eb2e8f9f7 140 #define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1
<> 144:ef7eb2e8f9f7 141
<> 144:ef7eb2e8f9f7 142 #define TIM21_ETR_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 143 #define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0
<> 144:ef7eb2e8f9f7 144 #define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1
<> 144:ef7eb2e8f9f7 145 #define TIM21_ETR_LSE TIM21_OR_ETR_RMP
<> 144:ef7eb2e8f9f7 146 #define TIM21_TI1_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 147 #define TIM21_TI1_MCO TIM21_OR_TI1_RMP
<> 144:ef7eb2e8f9f7 148 #define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0
<> 144:ef7eb2e8f9f7 149 #define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1
<> 144:ef7eb2e8f9f7 150 #define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1)
<> 144:ef7eb2e8f9f7 151 #define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2
<> 144:ef7eb2e8f9f7 152 #define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0)
<> 144:ef7eb2e8f9f7 153 #define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1)
<> 144:ef7eb2e8f9f7 154 #define TIM21_TI2_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 155 #define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 #if !defined(STM32L011xx) && !defined(STM32L021xx)
<> 144:ef7eb2e8f9f7 158 #define TIM22_ETR_LSE ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 159 #define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0
<> 144:ef7eb2e8f9f7 160 #define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1
<> 144:ef7eb2e8f9f7 161 #define TIM22_ETR_GPIO TIM22_OR_ETR_RMP
<> 144:ef7eb2e8f9f7 162 #define TIM22_TI1_GPIO1 ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 163 #define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0
<> 144:ef7eb2e8f9f7 164 #define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1
<> 144:ef7eb2e8f9f7 165 #define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP
<> 144:ef7eb2e8f9f7 166 #endif
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
<> 144:ef7eb2e8f9f7 169 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 #define TIM3_TI4_GPIO_DEF ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 172 #define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP
<> 144:ef7eb2e8f9f7 173 #define TIM3_TI2_GPIO_DEF ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 174 #define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP
<> 144:ef7eb2e8f9f7 175 #define TIM3_TI1_USB_SOF ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 176 #define TIM3_TI1_GPIO TIM3_OR_TI1_RMP
<> 144:ef7eb2e8f9f7 177 #define TIM3_ETR_GPIO ((uint32_t)0x0)
<> 144:ef7eb2e8f9f7 178 #define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182
<> 144:ef7eb2e8f9f7 183 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
<> 144:ef7eb2e8f9f7 184 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
<> 144:ef7eb2e8f9f7 185
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
<> 144:ef7eb2e8f9f7 188 (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
<> 144:ef7eb2e8f9f7 189 ((__INSTANCE__ == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
<> 144:ef7eb2e8f9f7 190 ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \
<> 144:ef7eb2e8f9f7 191 ((__INSTANCE__ == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP))))
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 194 (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 195 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 196 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 197 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
<> 144:ef7eb2e8f9f7 198 ((__INSTANCE__ == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 199 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 200 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 201 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
<> 144:ef7eb2e8f9f7 202 ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 203 ((__CHANNEL__) == TIM_CHANNEL_2))) || \
<> 144:ef7eb2e8f9f7 204 ((__INSTANCE__ == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 205 ((__CHANNEL__) == TIM_CHANNEL_2))))
<> 144:ef7eb2e8f9f7 206
<> 144:ef7eb2e8f9f7 207 #elif defined (STM32L011xx) || defined (STM32L021xx)
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
<> 144:ef7eb2e8f9f7 210 (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
<> 144:ef7eb2e8f9f7 211 ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 214 (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 215 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 216 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 217 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
<> 144:ef7eb2e8f9f7 218 ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 219 ((__CHANNEL__) == TIM_CHANNEL_2))))
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 #else
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 #define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \
<> 144:ef7eb2e8f9f7 224 (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \
<> 144:ef7eb2e8f9f7 225 ((__INSTANCE__ == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \
<> 144:ef7eb2e8f9f7 226 ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))))
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \
<> 144:ef7eb2e8f9f7 229 (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 230 ((__CHANNEL__) == TIM_CHANNEL_2) || \
<> 144:ef7eb2e8f9f7 231 ((__CHANNEL__) == TIM_CHANNEL_3) || \
<> 144:ef7eb2e8f9f7 232 ((__CHANNEL__) == TIM_CHANNEL_4))) || \
<> 144:ef7eb2e8f9f7 233 ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 234 ((__CHANNEL__) == TIM_CHANNEL_2))) || \
<> 144:ef7eb2e8f9f7 235 ((__INSTANCE__ == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \
<> 144:ef7eb2e8f9f7 236 ((__CHANNEL__) == TIM_CHANNEL_2))))
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 #endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /**
<> 144:ef7eb2e8f9f7 242 * @}
<> 144:ef7eb2e8f9f7 243 */
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 251 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 252 /* Control functions ***********************************************************/
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<> 144:ef7eb2e8f9f7 255 * @{
<> 144:ef7eb2e8f9f7 256 */
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions
<> 144:ef7eb2e8f9f7 259 * @{
<> 144:ef7eb2e8f9f7 260 */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
<> 144:ef7eb2e8f9f7 263 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /**
<> 144:ef7eb2e8f9f7 266 * @}
<> 144:ef7eb2e8f9f7 267 */
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @}
<> 144:ef7eb2e8f9f7 271 */
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /**
<> 144:ef7eb2e8f9f7 274 * @}
<> 144:ef7eb2e8f9f7 275 */
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @}
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282 #endif
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 #endif /* __STM32L0xx_HAL_TIM_EX_H */
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 287