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mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_rcc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@144:ef7eb2e8f9f7
Child:: 151:5eaa88a5bcc7

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_rcc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 8-January-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of RCC HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L0xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L0xx_HAL_RCC_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @defgroup RCC RCC
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/** @defgroup RCC_Exported_Types RCC Exported Types
<>	144:ef7eb2e8f9f7	58	* @{
<>	144:ef7eb2e8f9f7	59	*/
<>	144:ef7eb2e8f9f7	60
<>	144:ef7eb2e8f9f7	61	/**
<>	144:ef7eb2e8f9f7	62	* @brief RCC PLL configuration structure definition
<>	144:ef7eb2e8f9f7	63	*/
<>	144:ef7eb2e8f9f7	64	typedef struct
<>	144:ef7eb2e8f9f7	65	{
<>	144:ef7eb2e8f9f7	66	uint32_t PLLState; /*!< The new state of the PLL.
<>	144:ef7eb2e8f9f7	67	This parameter can be a value of @ref RCC_PLL_Config */
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
<>	144:ef7eb2e8f9f7	70	This parameter must be a value of @ref RCC_PLL_Clock_Source */
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
<>	144:ef7eb2e8f9f7	73	This parameter must of @ref RCC_PLLMultiplication_Factor */
<>	144:ef7eb2e8f9f7	74
<>	144:ef7eb2e8f9f7	75	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
<>	144:ef7eb2e8f9f7	76	This parameter must be a value of @ref RCC_PLLDivider_Factor */
<>	144:ef7eb2e8f9f7	77
<>	144:ef7eb2e8f9f7	78	}RCC_PLLInitTypeDef;
<>	144:ef7eb2e8f9f7	79
<>	144:ef7eb2e8f9f7	80	/**
<>	144:ef7eb2e8f9f7	81	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
<>	144:ef7eb2e8f9f7	82	*/
<>	144:ef7eb2e8f9f7	83	typedef struct
<>	144:ef7eb2e8f9f7	84	{
<>	144:ef7eb2e8f9f7	85	uint32_t OscillatorType; /*!< The oscillators to be configured.
<>	144:ef7eb2e8f9f7	86	This parameter can be a value of @ref RCC_Oscillator_Type */
<>	144:ef7eb2e8f9f7	87
<>	144:ef7eb2e8f9f7	88	uint32_t HSEState; /*!< The new state of the HSE.
<>	144:ef7eb2e8f9f7	89	This parameter can be a value of @ref RCC_HSE_Config */
<>	144:ef7eb2e8f9f7	90
<>	144:ef7eb2e8f9f7	91	uint32_t LSEState; /*!< The new state of the LSE.
<>	144:ef7eb2e8f9f7	92	This parameter can be a value of @ref RCC_LSE_Config */
<>	144:ef7eb2e8f9f7	93
<>	144:ef7eb2e8f9f7	94	uint32_t HSIState; /*!< The new state of the HSI.
<>	144:ef7eb2e8f9f7	95	This parameter can be a value of @ref RCC_HSI_Config */
<>	144:ef7eb2e8f9f7	96
<>	144:ef7eb2e8f9f7	97	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
<>	144:ef7eb2e8f9f7	98	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
<>	144:ef7eb2e8f9f7	99
<>	144:ef7eb2e8f9f7	100	uint32_t LSIState; /*!< The new state of the LSI.
<>	144:ef7eb2e8f9f7	101	This parameter can be a value of @ref RCC_LSI_Config */
<>	144:ef7eb2e8f9f7	102
<>	144:ef7eb2e8f9f7	103	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
<>	144:ef7eb2e8f9f7	104	!defined (STM32L011xx) && !defined (STM32L021xx)
<>	144:ef7eb2e8f9f7	105	uint32_t HSI48State; /*!< The new state of the HSI48.
<>	144:ef7eb2e8f9f7	106	This parameter can be a value of @ref RCC_HSI48_Config */
<>	144:ef7eb2e8f9f7	107	#endif
<>	144:ef7eb2e8f9f7	108
<>	144:ef7eb2e8f9f7	109	uint32_t MSIState; /*!< The new state of the MSI.
<>	144:ef7eb2e8f9f7	110	This parameter can be a value of @ref RCC_MSI_Config */
<>	144:ef7eb2e8f9f7	111
<>	144:ef7eb2e8f9f7	112	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
<>	144:ef7eb2e8f9f7	113	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	uint32_t MSIClockRange; /*!< The MSI frequency range.
<>	144:ef7eb2e8f9f7	116	This parameter can be a value of @ref RCC_MSI_Clock_Range */
<>	144:ef7eb2e8f9f7	117
<>	144:ef7eb2e8f9f7	118	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
<>	144:ef7eb2e8f9f7	119
<>	144:ef7eb2e8f9f7	120	}RCC_OscInitTypeDef;
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122	/**
<>	144:ef7eb2e8f9f7	123	* @brief RCC System, AHB and APB busses clock configuration structure definition
<>	144:ef7eb2e8f9f7	124	*/
<>	144:ef7eb2e8f9f7	125	typedef struct
<>	144:ef7eb2e8f9f7	126	{
<>	144:ef7eb2e8f9f7	127	uint32_t ClockType; /*!< The clock to be configured.
<>	144:ef7eb2e8f9f7	128	This parameter can be a value of @ref RCC_System_Clock_Type */
<>	144:ef7eb2e8f9f7	129
<>	144:ef7eb2e8f9f7	130	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
<>	144:ef7eb2e8f9f7	131	This parameter can be a value of @ref RCC_System_Clock_Source */
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
<>	144:ef7eb2e8f9f7	134	This parameter can be a value of @ref RCC_AHB_Clock_Source */
<>	144:ef7eb2e8f9f7	135
<>	144:ef7eb2e8f9f7	136	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
<>	144:ef7eb2e8f9f7	141
<>	144:ef7eb2e8f9f7	142	}RCC_ClkInitTypeDef;
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144	/**
<>	144:ef7eb2e8f9f7	145	* @}
<>	144:ef7eb2e8f9f7	146	*/
<>	144:ef7eb2e8f9f7	147
<>	144:ef7eb2e8f9f7	148	/* Private constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	149	/** @addtogroup RCC_Private
<>	144:ef7eb2e8f9f7	150	* @brief RCC registers bit address in the alias region
<>	144:ef7eb2e8f9f7	151	* @{
<>	144:ef7eb2e8f9f7	152	*/
<>	144:ef7eb2e8f9f7	153	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
<>	144:ef7eb2e8f9f7	154	/* --- CR Register ---*/
<>	144:ef7eb2e8f9f7	155	/* Alias word address of HSION bit */
<>	144:ef7eb2e8f9f7	156	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
<>	144:ef7eb2e8f9f7	157	/* --- CFGR Register ---*/
<>	144:ef7eb2e8f9f7	158	/* Alias word address of I2SSRC bit */
<>	144:ef7eb2e8f9f7	159	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
<>	144:ef7eb2e8f9f7	160	/* --- CSR Register ---*/
<>	144:ef7eb2e8f9f7	161	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
<>	144:ef7eb2e8f9f7	162
<>	144:ef7eb2e8f9f7	163	/* CR register byte 3 (Bits[23:16]) base address */
<>	144:ef7eb2e8f9f7	164	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
<>	144:ef7eb2e8f9f7	165
<>	144:ef7eb2e8f9f7	166	/* CIER register byte 0 (Bits[0:8]) base address */
<>	144:ef7eb2e8f9f7	167	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
<>	144:ef7eb2e8f9f7	168
<>	144:ef7eb2e8f9f7	169	/**
<>	144:ef7eb2e8f9f7	170	* @}
<>	144:ef7eb2e8f9f7	171	*/
<>	144:ef7eb2e8f9f7	172
<>	144:ef7eb2e8f9f7	173	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	174	/** @defgroup RCC_Exported_Constants RCC Exported Constants
<>	144:ef7eb2e8f9f7	175	* @{
<>	144:ef7eb2e8f9f7	176	*/
<>	144:ef7eb2e8f9f7	177
<>	144:ef7eb2e8f9f7	178	/** @defgroup RCC_Timeout_Value Timeout Values
<>	144:ef7eb2e8f9f7	179	* @{
<>	144:ef7eb2e8f9f7	180	*/
<>	144:ef7eb2e8f9f7	181	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
<>	144:ef7eb2e8f9f7	182	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	183	#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
<>	144:ef7eb2e8f9f7	184	/**
<>	144:ef7eb2e8f9f7	185	* @}
<>	144:ef7eb2e8f9f7	186	*/
<>	144:ef7eb2e8f9f7	187
<>	144:ef7eb2e8f9f7	188	/** @defgroup RCC_Oscillator_Type Oscillator Type
<>	144:ef7eb2e8f9f7	189	* @{
<>	144:ef7eb2e8f9f7	190	*/
<>	144:ef7eb2e8f9f7	191	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) /!< Oscillator configuration unchanged /
<>	144:ef7eb2e8f9f7	192	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001) /!< HSE to configure /
<>	144:ef7eb2e8f9f7	193	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002) /!< HSI to configure /
<>	144:ef7eb2e8f9f7	194	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) /!< LSE to configure /
<>	144:ef7eb2e8f9f7	195	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) /!< LSI to configure /
<>	144:ef7eb2e8f9f7	196	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) /!< MSI to configure /
<>	144:ef7eb2e8f9f7	197	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	198	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
<>	144:ef7eb2e8f9f7	199	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	/**
<>	144:ef7eb2e8f9f7	202	* @}
<>	144:ef7eb2e8f9f7	203	*/
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/** @defgroup RCC_HSE_Config RCC HSE Config
<>	144:ef7eb2e8f9f7	206	* @{
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	#define RCC_HSE_OFF ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	209	#define RCC_HSE_ON RCC_CR_HSEON
<>	144:ef7eb2e8f9f7	210	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
<>	144:ef7eb2e8f9f7	211
<>	144:ef7eb2e8f9f7	212	/**
<>	144:ef7eb2e8f9f7	213	* @}
<>	144:ef7eb2e8f9f7	214	*/
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	/** @defgroup RCC_LSE_Config RCC LSE Config
<>	144:ef7eb2e8f9f7	217	* @{
<>	144:ef7eb2e8f9f7	218	*/
<>	144:ef7eb2e8f9f7	219	#define RCC_LSE_OFF ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	220	#define RCC_LSE_ON RCC_CSR_LSEON
<>	144:ef7eb2e8f9f7	221	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223	/**
<>	144:ef7eb2e8f9f7	224	* @}
<>	144:ef7eb2e8f9f7	225	*/
<>	144:ef7eb2e8f9f7	226
<>	144:ef7eb2e8f9f7	227
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/** @defgroup RCC_LSI_Config RCC LSI Config
<>	144:ef7eb2e8f9f7	230	* @{
<>	144:ef7eb2e8f9f7	231	*/
<>	144:ef7eb2e8f9f7	232	#define RCC_LSI_OFF ((uint8_t)0x00)
<>	144:ef7eb2e8f9f7	233	#define RCC_LSI_ON ((uint8_t)0x01)
<>	144:ef7eb2e8f9f7	234
<>	144:ef7eb2e8f9f7	235	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
<>	144:ef7eb2e8f9f7	236
<>	144:ef7eb2e8f9f7	237	/**
<>	144:ef7eb2e8f9f7	238	* @}
<>	144:ef7eb2e8f9f7	239	*/
<>	144:ef7eb2e8f9f7	240
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	/** @defgroup RCC_MSI_Config RCC MSI Config
<>	144:ef7eb2e8f9f7	243	* @{
<>	144:ef7eb2e8f9f7	244	*/
<>	144:ef7eb2e8f9f7	245	#define RCC_MSI_OFF ((uint8_t)0x00)
<>	144:ef7eb2e8f9f7	246	#define RCC_MSI_ON ((uint8_t)0x01)
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
<>	144:ef7eb2e8f9f7	249
<>	144:ef7eb2e8f9f7	250	/**
<>	144:ef7eb2e8f9f7	251	* @}
<>	144:ef7eb2e8f9f7	252	*/
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	255	/** @defgroup RCC_HSI48_Config RCC HSI48 Configuration
<>	144:ef7eb2e8f9f7	256	* @{
<>	144:ef7eb2e8f9f7	257	*/
<>	144:ef7eb2e8f9f7	258	#define RCC_HSI48_OFF ((uint8_t)0x00)
<>	144:ef7eb2e8f9f7	259	#define RCC_HSI48_ON ((uint8_t)0x01)
<>	144:ef7eb2e8f9f7	260
<>	144:ef7eb2e8f9f7	261	/**
<>	144:ef7eb2e8f9f7	262	* @}
<>	144:ef7eb2e8f9f7	263	*/
<>	144:ef7eb2e8f9f7	264	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	/** @defgroup RCC_PLL_Config RCC PLL Config
<>	144:ef7eb2e8f9f7	267	* @{
<>	144:ef7eb2e8f9f7	268	*/
<>	144:ef7eb2e8f9f7	269	#define RCC_PLL_NONE ((uint8_t)0x00)
<>	144:ef7eb2e8f9f7	270	#define RCC_PLL_OFF ((uint8_t)0x01)
<>	144:ef7eb2e8f9f7	271	#define RCC_PLL_ON ((uint8_t)0x02)
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	/**
<>	144:ef7eb2e8f9f7	274	* @}
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
<>	144:ef7eb2e8f9f7	278	* @{
<>	144:ef7eb2e8f9f7	279	*/
<>	144:ef7eb2e8f9f7	280	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
<>	144:ef7eb2e8f9f7	281	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283
<>	144:ef7eb2e8f9f7	284	/**
<>	144:ef7eb2e8f9f7	285	* @}
<>	144:ef7eb2e8f9f7	286	*/
<>	144:ef7eb2e8f9f7	287
<>	144:ef7eb2e8f9f7	288	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
<>	144:ef7eb2e8f9f7	289	* @{
<>	144:ef7eb2e8f9f7	290	*/
<>	144:ef7eb2e8f9f7	291
<>	144:ef7eb2e8f9f7	292	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
<>	144:ef7eb2e8f9f7	293	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
<>	144:ef7eb2e8f9f7	294	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
<>	144:ef7eb2e8f9f7	295	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
<>	144:ef7eb2e8f9f7	296	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
<>	144:ef7eb2e8f9f7	297	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
<>	144:ef7eb2e8f9f7	298	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
<>	144:ef7eb2e8f9f7	299	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
<>	144:ef7eb2e8f9f7	300	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
<>	144:ef7eb2e8f9f7	301
<>	144:ef7eb2e8f9f7	302	/**
<>	144:ef7eb2e8f9f7	303	* @}
<>	144:ef7eb2e8f9f7	304	*/
<>	144:ef7eb2e8f9f7	305
<>	144:ef7eb2e8f9f7	306	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
<>	144:ef7eb2e8f9f7	307	* @{
<>	144:ef7eb2e8f9f7	308	*/
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
<>	144:ef7eb2e8f9f7	311	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
<>	144:ef7eb2e8f9f7	312	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/**
<>	144:ef7eb2e8f9f7	315	* @}
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317
<>	144:ef7eb2e8f9f7	318	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
<>	144:ef7eb2e8f9f7	319	* @{
<>	144:ef7eb2e8f9f7	320	*/
<>	144:ef7eb2e8f9f7	321
<>	144:ef7eb2e8f9f7	322	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
<>	144:ef7eb2e8f9f7	323	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
<>	144:ef7eb2e8f9f7	324	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
<>	144:ef7eb2e8f9f7	325	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
<>	144:ef7eb2e8f9f7	326	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
<>	144:ef7eb2e8f9f7	327	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
<>	144:ef7eb2e8f9f7	328	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
<>	144:ef7eb2e8f9f7	329
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/**
<>	144:ef7eb2e8f9f7	332	* @}
<>	144:ef7eb2e8f9f7	333	*/
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
<>	144:ef7eb2e8f9f7	336	* @{
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) /!< SYSCLK to configure /
<>	144:ef7eb2e8f9f7	339	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002) /!< HCLK to configure /
<>	144:ef7eb2e8f9f7	340	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) /!< PCLK1 to configure /
<>	144:ef7eb2e8f9f7	341	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) /!< PCLK2 to configure /
<>	144:ef7eb2e8f9f7	342	/**
<>	144:ef7eb2e8f9f7	343	* @}
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
<>	144:ef7eb2e8f9f7	347	* @{
<>	144:ef7eb2e8f9f7	348	*/
<>	144:ef7eb2e8f9f7	349	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
<>	144:ef7eb2e8f9f7	350	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	144:ef7eb2e8f9f7	351	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	144:ef7eb2e8f9f7	352	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	144:ef7eb2e8f9f7	353	/**
<>	144:ef7eb2e8f9f7	354	* @}
<>	144:ef7eb2e8f9f7	355	*/
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/** @defgroup RCC_System_Clock_SOURCE_Status RCC System Clock Source Status
<>	144:ef7eb2e8f9f7	358	* @{
<>	144:ef7eb2e8f9f7	359	*/
<>	144:ef7eb2e8f9f7	360	#define RCC_SYSCLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
<>	144:ef7eb2e8f9f7	361	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	144:ef7eb2e8f9f7	362	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	144:ef7eb2e8f9f7	363	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	144:ef7eb2e8f9f7	364	/**
<>	144:ef7eb2e8f9f7	365	* @}
<>	144:ef7eb2e8f9f7	366	*/
<>	144:ef7eb2e8f9f7	367
<>	144:ef7eb2e8f9f7	368	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
<>	144:ef7eb2e8f9f7	369	* @{
<>	144:ef7eb2e8f9f7	370	*/
<>	144:ef7eb2e8f9f7	371	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	144:ef7eb2e8f9f7	372	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	144:ef7eb2e8f9f7	373	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	144:ef7eb2e8f9f7	374	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	144:ef7eb2e8f9f7	375	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	144:ef7eb2e8f9f7	376	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	144:ef7eb2e8f9f7	377	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	144:ef7eb2e8f9f7	378	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	144:ef7eb2e8f9f7	379	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	144:ef7eb2e8f9f7	380	/**
<>	144:ef7eb2e8f9f7	381	* @}
<>	144:ef7eb2e8f9f7	382	*/
<>	144:ef7eb2e8f9f7	383
<>	144:ef7eb2e8f9f7	384	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
<>	144:ef7eb2e8f9f7	385	* @{
<>	144:ef7eb2e8f9f7	386	*/
<>	144:ef7eb2e8f9f7	387	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	144:ef7eb2e8f9f7	388	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	144:ef7eb2e8f9f7	389	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	144:ef7eb2e8f9f7	390	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	144:ef7eb2e8f9f7	391	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	144:ef7eb2e8f9f7	392	/**
<>	144:ef7eb2e8f9f7	393	* @}
<>	144:ef7eb2e8f9f7	394	*/
<>	144:ef7eb2e8f9f7	395
<>	144:ef7eb2e8f9f7	396	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
<>	144:ef7eb2e8f9f7	397	* @{
<>	144:ef7eb2e8f9f7	398	*/
<>	144:ef7eb2e8f9f7	399	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	400	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
<>	144:ef7eb2e8f9f7	401	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
<>	144:ef7eb2e8f9f7	402	#define RCC_RTCCLKSOURCE_HSE_DIVX RCC_CSR_RTCSEL_HSE
<>	144:ef7eb2e8f9f7	403
<>	144:ef7eb2e8f9f7	404	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
<>	144:ef7eb2e8f9f7	405	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
<>	144:ef7eb2e8f9f7	406	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
<>	144:ef7eb2e8f9f7	407	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	#define RCC_RTC_HSE_DIV_2 (uint32_t)0x00000000U /!< HSE is divided by 2 for RTC clock /
<>	144:ef7eb2e8f9f7	410	#define RCC_RTC_HSE_DIV_4 RCC_CR_RTCPRE_0 /!< HSE is divided by 4 for RTC clock /
<>	144:ef7eb2e8f9f7	411	#define RCC_RTC_HSE_DIV_8 RCC_CR_RTCPRE_1 /!< HSE is divided by 8 for RTC clock /
<>	144:ef7eb2e8f9f7	412	#define RCC_RTC_HSE_DIV_16 RCC_CR_RTCPRE /!< HSE is divided by 16 for RTC clock /
<>	144:ef7eb2e8f9f7	413
<>	144:ef7eb2e8f9f7	414	/**
<>	144:ef7eb2e8f9f7	415	* @}
<>	144:ef7eb2e8f9f7	416	*/
<>	144:ef7eb2e8f9f7	417
<>	144:ef7eb2e8f9f7	418	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
<>	144:ef7eb2e8f9f7	419	* @{
<>	144:ef7eb2e8f9f7	420	*/
<>	144:ef7eb2e8f9f7	421
<>	144:ef7eb2e8f9f7	422	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
<>	144:ef7eb2e8f9f7	423	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
<>	144:ef7eb2e8f9f7	424	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
<>	144:ef7eb2e8f9f7	425	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
<>	144:ef7eb2e8f9f7	426	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
<>	144:ef7eb2e8f9f7	427	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
<>	144:ef7eb2e8f9f7	428	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
<>	144:ef7eb2e8f9f7	429	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
<>	144:ef7eb2e8f9f7	430	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
<>	144:ef7eb2e8f9f7	431	&& !defined (STM32L011xx) && !defined (STM32L021xx)
<>	144:ef7eb2e8f9f7	432	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
<>	144:ef7eb2e8f9f7	433	#endif
<>	144:ef7eb2e8f9f7	434
<>	144:ef7eb2e8f9f7	435
<>	144:ef7eb2e8f9f7	436	/**
<>	144:ef7eb2e8f9f7	437	* @}
<>	144:ef7eb2e8f9f7	438	*/
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
<>	144:ef7eb2e8f9f7	441	* @{
<>	144:ef7eb2e8f9f7	442	*/
<>	144:ef7eb2e8f9f7	443
<>	144:ef7eb2e8f9f7	444	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
<>	144:ef7eb2e8f9f7	445	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
<>	144:ef7eb2e8f9f7	446	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
<>	144:ef7eb2e8f9f7	447	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
<>	144:ef7eb2e8f9f7	448	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
<>	144:ef7eb2e8f9f7	449
<>	144:ef7eb2e8f9f7	450	/**
<>	144:ef7eb2e8f9f7	451	* @}
<>	144:ef7eb2e8f9f7	452	*/
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/** @defgroup RCC_MCO_Index RCC MCO Index
<>	144:ef7eb2e8f9f7	455	* @{
<>	144:ef7eb2e8f9f7	456	*/
<>	144:ef7eb2e8f9f7	457	#define RCC_MCO1 ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	458	#define RCC_MCO2 ((uint32_t)0x00000001)
<>	144:ef7eb2e8f9f7	459	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
<>	144:ef7eb2e8f9f7	460	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	461	#define RCC_MCO3 ((uint32_t)0x00000002)
<>	144:ef7eb2e8f9f7	462	#endif
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	/**
<>	144:ef7eb2e8f9f7	465	* @}
<>	144:ef7eb2e8f9f7	466	*/
<>	144:ef7eb2e8f9f7	467
<>	144:ef7eb2e8f9f7	468	/** @defgroup RCC_Interrupt RCC Interruptions
<>	144:ef7eb2e8f9f7	469	* @{
<>	144:ef7eb2e8f9f7	470	*/
<>	144:ef7eb2e8f9f7	471	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
<>	144:ef7eb2e8f9f7	472	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
<>	144:ef7eb2e8f9f7	473	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
<>	144:ef7eb2e8f9f7	474	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
<>	144:ef7eb2e8f9f7	475	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
<>	144:ef7eb2e8f9f7	476	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
<>	144:ef7eb2e8f9f7	477
<>	144:ef7eb2e8f9f7	478	#define RCC_IT_CSSLSE RCC_CIFR_CSSLSEF
<>	144:ef7eb2e8f9f7	479	#define RCC_IT_CSSHSE RCC_CIFR_CSSHSEF
<>	144:ef7eb2e8f9f7	480
<>	144:ef7eb2e8f9f7	481	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	482	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
<>	144:ef7eb2e8f9f7	483	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
<>	144:ef7eb2e8f9f7	484	/**
<>	144:ef7eb2e8f9f7	485	* @}
<>	144:ef7eb2e8f9f7	486	*/
<>	144:ef7eb2e8f9f7	487
<>	144:ef7eb2e8f9f7	488	/** @defgroup RCC_Flag RCC Flag
<>	144:ef7eb2e8f9f7	489	* Elements values convention: 0XXYYYYYb
<>	144:ef7eb2e8f9f7	490	* - YYYYY : Flag position in the register
<>	144:ef7eb2e8f9f7	491	* - 0XX : Register index
<>	144:ef7eb2e8f9f7	492	* - 01: CR register
<>	144:ef7eb2e8f9f7	493	* - 10: CSR register
<>	144:ef7eb2e8f9f7	494	* - 11: CRRCR register
<>	144:ef7eb2e8f9f7	495	* @{
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497	/* Flags in the CR register */
<>	144:ef7eb2e8f9f7	498	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
<>	144:ef7eb2e8f9f7	499	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
<>	144:ef7eb2e8f9f7	500	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
<>	144:ef7eb2e8f9f7	501	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
<>	144:ef7eb2e8f9f7	502	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
<>	144:ef7eb2e8f9f7	503
<>	144:ef7eb2e8f9f7	504	/* Flags in the CSR register */
<>	144:ef7eb2e8f9f7	505	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
<>	144:ef7eb2e8f9f7	506	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
<>	144:ef7eb2e8f9f7	507	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
<>	144:ef7eb2e8f9f7	508	#define RCC_FLAG_FWRST ((uint8_t)0x58)
<>	144:ef7eb2e8f9f7	509	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
<>	144:ef7eb2e8f9f7	510	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
<>	144:ef7eb2e8f9f7	511	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
<>	144:ef7eb2e8f9f7	512	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
<>	144:ef7eb2e8f9f7	513	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
<>	144:ef7eb2e8f9f7	514	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
<>	144:ef7eb2e8f9f7	515	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
<>	144:ef7eb2e8f9f7	516
<>	144:ef7eb2e8f9f7	517	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	518	/* Flags in the CRRCR register */
<>	144:ef7eb2e8f9f7	519	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
<>	144:ef7eb2e8f9f7	520	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
<>	144:ef7eb2e8f9f7	521
<>	144:ef7eb2e8f9f7	522
<>	144:ef7eb2e8f9f7	523	/**
<>	144:ef7eb2e8f9f7	524	* @}
<>	144:ef7eb2e8f9f7	525	*/
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/**
<>	144:ef7eb2e8f9f7	528	* @}
<>	144:ef7eb2e8f9f7	529	*/
<>	144:ef7eb2e8f9f7	530	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	531	/** @defgroup RCC_Exported_Macros RCC Exported Macros
<>	144:ef7eb2e8f9f7	532	* @{
<>	144:ef7eb2e8f9f7	533	*/
<>	144:ef7eb2e8f9f7	534
<>	144:ef7eb2e8f9f7	535	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable AHB Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	536	* @brief Enable or disable the AHB peripheral clock.
<>	144:ef7eb2e8f9f7	537	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	538	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	539	* using it.
<>	144:ef7eb2e8f9f7	540	* @{
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	543	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	544	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	545	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	546	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
<>	144:ef7eb2e8f9f7	547	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	548	} while(0)
<>	144:ef7eb2e8f9f7	549
<>	144:ef7eb2e8f9f7	550	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	551	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	552	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
<>	144:ef7eb2e8f9f7	553	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	554	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
<>	144:ef7eb2e8f9f7	555	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	556	} while(0)
<>	144:ef7eb2e8f9f7	557
<>	144:ef7eb2e8f9f7	558	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	559	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	560	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	561	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	562	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
<>	144:ef7eb2e8f9f7	563	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	564	} while(0)
<>	144:ef7eb2e8f9f7	565
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN)
<>	144:ef7eb2e8f9f7	568	#define __HAL_RCC_MIF_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN)
<>	144:ef7eb2e8f9f7	569	#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN)
<>	144:ef7eb2e8f9f7	570
<>	144:ef7eb2e8f9f7	571	/**
<>	144:ef7eb2e8f9f7	572	* @}
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574
<>	144:ef7eb2e8f9f7	575	/** @defgroup RCC_IOPORT_Clock_Enable_Disable IOPORT Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	576	* @brief Enable or disable the IOPORT peripheral clock.
<>	144:ef7eb2e8f9f7	577	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	578	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	579	* using it.
<>	144:ef7eb2e8f9f7	580	* @{
<>	144:ef7eb2e8f9f7	581	*/
<>	144:ef7eb2e8f9f7	582	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	583	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	584	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	585	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	586	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
<>	144:ef7eb2e8f9f7	587	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	588	} while(0)
<>	144:ef7eb2e8f9f7	589
<>	144:ef7eb2e8f9f7	590	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	591	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	592	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	593	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	594	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
<>	144:ef7eb2e8f9f7	595	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	596	} while(0)
<>	144:ef7eb2e8f9f7	597
<>	144:ef7eb2e8f9f7	598	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	599	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	600	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	601	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	602	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
<>	144:ef7eb2e8f9f7	603	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	604	} while(0)
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
<>	144:ef7eb2e8f9f7	607	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	608	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	609	/* Delay after an RCC peripheral clock enabling */ \
<>	144:ef7eb2e8f9f7	610	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
<>	144:ef7eb2e8f9f7	611	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	612	} while(0)
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614
<>	144:ef7eb2e8f9f7	615	#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN)
<>	144:ef7eb2e8f9f7	616	#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN)
<>	144:ef7eb2e8f9f7	617	#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN)
<>	144:ef7eb2e8f9f7	618	#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN)
<>	144:ef7eb2e8f9f7	619
<>	144:ef7eb2e8f9f7	620	/**
<>	144:ef7eb2e8f9f7	621	* @}
<>	144:ef7eb2e8f9f7	622	*/
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	625	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
<>	144:ef7eb2e8f9f7	626	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	627	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	628	* using it.
<>	144:ef7eb2e8f9f7	629	* @{
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631	#define __HAL_RCC_WWDG_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	632	#define __HAL_RCC_PWR_CLK_ENABLE() SET_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_WWDGEN))
<>	144:ef7eb2e8f9f7	635	#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR, (RCC_APB1ENR_PWREN))
<>	144:ef7eb2e8f9f7	636	/**
<>	144:ef7eb2e8f9f7	637	* @}
<>	144:ef7eb2e8f9f7	638	*/
<>	144:ef7eb2e8f9f7	639
<>	144:ef7eb2e8f9f7	640	/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
<>	144:ef7eb2e8f9f7	641	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
<>	144:ef7eb2e8f9f7	642	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	643	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	644	* using it.
<>	144:ef7eb2e8f9f7	645	* @{
<>	144:ef7eb2e8f9f7	646	*/
<>	144:ef7eb2e8f9f7	647	#define __HAL_RCC_SYSCFG_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	648	#define __HAL_RCC_DBGMCU_CLK_ENABLE() SET_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_SYSCFGEN))
<>	144:ef7eb2e8f9f7	651	#define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, (RCC_APB2ENR_DBGMCUEN))
<>	144:ef7eb2e8f9f7	652	/**
<>	144:ef7eb2e8f9f7	653	* @}
<>	144:ef7eb2e8f9f7	654	*/
<>	144:ef7eb2e8f9f7	655
<>	144:ef7eb2e8f9f7	656	/** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	657	* @brief Check whether the AHB peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	658	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	659	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	660	* using it.
<>	144:ef7eb2e8f9f7	661	* @{
<>	144:ef7eb2e8f9f7	662	*/
<>	144:ef7eb2e8f9f7	663
<>	144:ef7eb2e8f9f7	664	#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN) != RESET)
<>	144:ef7eb2e8f9f7	665	#define __HAL_RCC_MIF_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN) != RESET)
<>	144:ef7eb2e8f9f7	666	#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN) != RESET)
<>	144:ef7eb2e8f9f7	667
<>	144:ef7eb2e8f9f7	668	/**
<>	144:ef7eb2e8f9f7	669	* @}
<>	144:ef7eb2e8f9f7	670	*/
<>	144:ef7eb2e8f9f7	671
<>	144:ef7eb2e8f9f7	672	/** @defgroup RCC_IOPORT_Peripheral_Clock_Enable_Disable_Status IOPORT Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	673	* @brief Check whether the IOPORT peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	674	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	675	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	676	* using it.
<>	144:ef7eb2e8f9f7	677	* @{
<>	144:ef7eb2e8f9f7	678	*/
<>	144:ef7eb2e8f9f7	679
<>	144:ef7eb2e8f9f7	680	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN) != RESET)
<>	144:ef7eb2e8f9f7	681	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN) != RESET)
<>	144:ef7eb2e8f9f7	682	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN) != RESET)
<>	144:ef7eb2e8f9f7	683	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN) != RESET)
<>	144:ef7eb2e8f9f7	684
<>	144:ef7eb2e8f9f7	685	/**
<>	144:ef7eb2e8f9f7	686	* @}
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689	/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	690	* @brief Check whether the APB1 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	691	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	692	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	693	* using it.
<>	144:ef7eb2e8f9f7	694	* @{
<>	144:ef7eb2e8f9f7	695	*/
<>	144:ef7eb2e8f9f7	696	#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN) != RESET)
<>	144:ef7eb2e8f9f7	697	#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN) != RESET)
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/**
<>	144:ef7eb2e8f9f7	700	* @}
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	704	* @brief Check whether the APB2 peripheral clock is enabled or not.
<>	144:ef7eb2e8f9f7	705	* @note After reset, the peripheral clock (used for registers read/write access)
<>	144:ef7eb2e8f9f7	706	* is disabled and the application software has to enable this clock before
<>	144:ef7eb2e8f9f7	707	* using it.
<>	144:ef7eb2e8f9f7	708	* @{
<>	144:ef7eb2e8f9f7	709	*/
<>	144:ef7eb2e8f9f7	710	#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != RESET)
<>	144:ef7eb2e8f9f7	711	#define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DBGMCUEN) != RESET)
<>	144:ef7eb2e8f9f7	712
<>	144:ef7eb2e8f9f7	713	/**
<>	144:ef7eb2e8f9f7	714	* @}
<>	144:ef7eb2e8f9f7	715	*/
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/** @defgroup RCC_AHB_Force_Release_Reset AHB Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	718	* @brief Force or release AHB peripheral reset.
<>	144:ef7eb2e8f9f7	719	* @{
<>	144:ef7eb2e8f9f7	720	*/
<>	144:ef7eb2e8f9f7	721	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	722	#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	723	#define __HAL_RCC_MIF_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
<>	144:ef7eb2e8f9f7	724	#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
<>	144:ef7eb2e8f9f7	727	#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_CRCRST))
<>	144:ef7eb2e8f9f7	728	#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_DMA1RST))
<>	144:ef7eb2e8f9f7	729	#define __HAL_RCC_MIF_RELEASE_RESET() CLEAR_BIT(RCC->AHBRSTR, (RCC_AHBRSTR_MIFRST))
<>	144:ef7eb2e8f9f7	730	/**
<>	144:ef7eb2e8f9f7	731	* @}
<>	144:ef7eb2e8f9f7	732	*/
<>	144:ef7eb2e8f9f7	733
<>	144:ef7eb2e8f9f7	734	/** @defgroup RCC_IOPORT_Force_Release_Reset IOPORT Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	735	* @brief Force or release IOPORT peripheral reset.
<>	144:ef7eb2e8f9f7	736	* @{
<>	144:ef7eb2e8f9f7	737	*/
<>	144:ef7eb2e8f9f7	738	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	739	#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	740	#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	741	#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	742	#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	743
<>	144:ef7eb2e8f9f7	744	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
<>	144:ef7eb2e8f9f7	745	#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOARST))
<>	144:ef7eb2e8f9f7	746	#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOBRST))
<>	144:ef7eb2e8f9f7	747	#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOCRST))
<>	144:ef7eb2e8f9f7	748	#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->IOPRSTR, (RCC_IOPRSTR_GPIOHRST))
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/**
<>	144:ef7eb2e8f9f7	751	* @}
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	755	* @brief Force or release APB1 peripheral reset.
<>	144:ef7eb2e8f9f7	756	* @{
<>	144:ef7eb2e8f9f7	757	*/
<>	144:ef7eb2e8f9f7	758	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	759	#define __HAL_RCC_WWDG_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	760	#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	761
<>	144:ef7eb2e8f9f7	762	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
<>	144:ef7eb2e8f9f7	763	#define __HAL_RCC_WWDG_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_WWDGRST))
<>	144:ef7eb2e8f9f7	764	#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR, (RCC_APB1RSTR_PWRRST))
<>	144:ef7eb2e8f9f7	765
<>	144:ef7eb2e8f9f7	766	/**
<>	144:ef7eb2e8f9f7	767	* @}
<>	144:ef7eb2e8f9f7	768	*/
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
<>	144:ef7eb2e8f9f7	771	* @brief Force or release APB2 peripheral reset.
<>	144:ef7eb2e8f9f7	772	* @{
<>	144:ef7eb2e8f9f7	773	*/
<>	144:ef7eb2e8f9f7	774	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
<>	144:ef7eb2e8f9f7	775	#define __HAL_RCC_DBGMCU_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
<>	144:ef7eb2e8f9f7	776	#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
<>	144:ef7eb2e8f9f7	779	#define __HAL_RCC_DBGMCU_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_DBGMCURST))
<>	144:ef7eb2e8f9f7	780	#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, (RCC_APB2RSTR_SYSCFGRST))
<>	144:ef7eb2e8f9f7	781	/**
<>	144:ef7eb2e8f9f7	782	* @}
<>	144:ef7eb2e8f9f7	783	*/
<>	144:ef7eb2e8f9f7	784
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable AHB Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	787	* @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	788	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	789	* power consumption.
<>	144:ef7eb2e8f9f7	790	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	791	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	792	* @{
<>	144:ef7eb2e8f9f7	793	*/
<>	144:ef7eb2e8f9f7	794	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
<>	144:ef7eb2e8f9f7	795	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
<>	144:ef7eb2e8f9f7	796	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
<>	144:ef7eb2e8f9f7	797	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_CRCSMEN))
<>	144:ef7eb2e8f9f7	800	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_MIFSMEN))
<>	144:ef7eb2e8f9f7	801	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_SRAMSMEN))
<>	144:ef7eb2e8f9f7	802	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHBSMENR, (RCC_AHBSMENR_DMA1SMEN))
<>	144:ef7eb2e8f9f7	803	/**
<>	144:ef7eb2e8f9f7	804	* @}
<>	144:ef7eb2e8f9f7	805	*/
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable IOPORT Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	808	* @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	809	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	810	* power consumption.
<>	144:ef7eb2e8f9f7	811	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	812	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	813	* @{
<>	144:ef7eb2e8f9f7	814	*/
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
<>	144:ef7eb2e8f9f7	817	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
<>	144:ef7eb2e8f9f7	818	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
<>	144:ef7eb2e8f9f7	819	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
<>	144:ef7eb2e8f9f7	820
<>	144:ef7eb2e8f9f7	821	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOASMEN))
<>	144:ef7eb2e8f9f7	822	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOBSMEN))
<>	144:ef7eb2e8f9f7	823	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOCSMEN))
<>	144:ef7eb2e8f9f7	824	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->IOPSMENR, (RCC_IOPSMENR_GPIOHSMEN))
<>	144:ef7eb2e8f9f7	825	/**
<>	144:ef7eb2e8f9f7	826	* @}
<>	144:ef7eb2e8f9f7	827	*/
<>	144:ef7eb2e8f9f7	828
<>	144:ef7eb2e8f9f7	829	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	830	* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	831	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	832	* power consumption.
<>	144:ef7eb2e8f9f7	833	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	834	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	835	* @{
<>	144:ef7eb2e8f9f7	836	*/
<>	144:ef7eb2e8f9f7	837	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
<>	144:ef7eb2e8f9f7	838	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
<>	144:ef7eb2e8f9f7	839
<>	144:ef7eb2e8f9f7	840	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_WWDGSMEN))
<>	144:ef7eb2e8f9f7	841	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR, (RCC_APB1SMENR_PWRSMEN))
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	/**
<>	144:ef7eb2e8f9f7	844	* @}
<>	144:ef7eb2e8f9f7	845	*/
<>	144:ef7eb2e8f9f7	846
<>	144:ef7eb2e8f9f7	847	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
<>	144:ef7eb2e8f9f7	848	* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
<>	144:ef7eb2e8f9f7	849	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	850	* power consumption.
<>	144:ef7eb2e8f9f7	851	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	852	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	853	* @{
<>	144:ef7eb2e8f9f7	854	*/
<>	144:ef7eb2e8f9f7	855	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
<>	144:ef7eb2e8f9f7	856	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
<>	144:ef7eb2e8f9f7	857
<>	144:ef7eb2e8f9f7	858	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_SYSCFGSMEN))
<>	144:ef7eb2e8f9f7	859	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, (RCC_APB2SMENR_DBGMCUSMEN))
<>	144:ef7eb2e8f9f7	860
<>	144:ef7eb2e8f9f7	861	/**
<>	144:ef7eb2e8f9f7	862	* @}
<>	144:ef7eb2e8f9f7	863	*/
<>	144:ef7eb2e8f9f7	864
<>	144:ef7eb2e8f9f7	865	/** @defgroup RCC_AHB_Clock_Sleep_Enable_Disable_Status AHB Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	866	* @brief Check whether the AHB peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	867	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	868	* power consumption.
<>	144:ef7eb2e8f9f7	869	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	870	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	871	* @{
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873	#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_CRCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	874	#define __HAL_RCC_MIF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_MIFSMEN) != RESET)
<>	144:ef7eb2e8f9f7	875	#define __HAL_RCC_SRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_SRAMSMEN) != RESET)
<>	144:ef7eb2e8f9f7	876	#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHBSMENR, RCC_AHBSMENR_DMA1SMEN) != RESET)
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/**
<>	144:ef7eb2e8f9f7	879	* @}
<>	144:ef7eb2e8f9f7	880	*/
<>	144:ef7eb2e8f9f7	881
<>	144:ef7eb2e8f9f7	882	/** @defgroup RCC_IOPORT_Clock_Sleep_Enable_Disable_Status IOPORT Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	883	* @brief Check whether the IOPORT peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	884	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	885	* power consumption.
<>	144:ef7eb2e8f9f7	886	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	887	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	888	* @{
<>	144:ef7eb2e8f9f7	889	*/
<>	144:ef7eb2e8f9f7	890	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOASMEN) != RESET)
<>	144:ef7eb2e8f9f7	891	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOBSMEN) != RESET)
<>	144:ef7eb2e8f9f7	892	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOCSMEN) != RESET)
<>	144:ef7eb2e8f9f7	893	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->IOPSMENR, RCC_IOPSMENR_GPIOHSMEN) != RESET)
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/**
<>	144:ef7eb2e8f9f7	896	* @}
<>	144:ef7eb2e8f9f7	897	*/
<>	144:ef7eb2e8f9f7	898
<>	144:ef7eb2e8f9f7	899	/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	900	* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	901	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	902	* power consumption.
<>	144:ef7eb2e8f9f7	903	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	904	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	905	* @{
<>	144:ef7eb2e8f9f7	906	*/
<>	144:ef7eb2e8f9f7	907	#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_WWDGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	908	#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR, RCC_APB1SMENR_PWRSMEN) != RESET)
<>	144:ef7eb2e8f9f7	909
<>	144:ef7eb2e8f9f7	910	/**
<>	144:ef7eb2e8f9f7	911	* @}
<>	144:ef7eb2e8f9f7	912	*/
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
<>	144:ef7eb2e8f9f7	915	* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
<>	144:ef7eb2e8f9f7	916	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
<>	144:ef7eb2e8f9f7	917	* power consumption.
<>	144:ef7eb2e8f9f7	918	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
<>	144:ef7eb2e8f9f7	919	* @note By default, all peripheral clocks are enabled during SLEEP mode.
<>	144:ef7eb2e8f9f7	920	* @{
<>	144:ef7eb2e8f9f7	921	*/
<>	144:ef7eb2e8f9f7	922	#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != RESET)
<>	144:ef7eb2e8f9f7	923	#define __HAL_RCC_DBGMCU_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DBGMCUSMEN) != RESET)
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/**
<>	144:ef7eb2e8f9f7	926	* @}
<>	144:ef7eb2e8f9f7	927	*/
<>	144:ef7eb2e8f9f7	928
<>	144:ef7eb2e8f9f7	929	/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
<>	144:ef7eb2e8f9f7	930	* @{
<>	144:ef7eb2e8f9f7	931	*/
<>	144:ef7eb2e8f9f7	932
<>	144:ef7eb2e8f9f7	933	/** @brief Macros to force or release the Backup domain reset.
<>	144:ef7eb2e8f9f7	934	* @note This function resets the RTC peripheral (including the backup registers)
<>	144:ef7eb2e8f9f7	935	* and the RTC clock source selection in RCC_CSR register.
<>	144:ef7eb2e8f9f7	936	* @note The BKPSRAM is not affected by this reset.
<>	144:ef7eb2e8f9f7	937	*/
<>	144:ef7eb2e8f9f7	938	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
<>	144:ef7eb2e8f9f7	939	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	/**
<>	144:ef7eb2e8f9f7	942	* @}
<>	144:ef7eb2e8f9f7	943	*/
<>	144:ef7eb2e8f9f7	944
<>	144:ef7eb2e8f9f7	945	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
<>	144:ef7eb2e8f9f7	946	* @{
<>	144:ef7eb2e8f9f7	947	*/
<>	144:ef7eb2e8f9f7	948
<>	144:ef7eb2e8f9f7	949	/** @brief Macros to enable or disable the the RTC clock.
<>	144:ef7eb2e8f9f7	950	* @note These macros must be used only after the RTC clock source was selected.
<>	144:ef7eb2e8f9f7	951	*/
<>	144:ef7eb2e8f9f7	952	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
<>	144:ef7eb2e8f9f7	953	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
<>	144:ef7eb2e8f9f7	954
<>	144:ef7eb2e8f9f7	955	/**
<>	144:ef7eb2e8f9f7	956	* @}
<>	144:ef7eb2e8f9f7	957	*/
<>	144:ef7eb2e8f9f7	958
<>	144:ef7eb2e8f9f7	959	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	960	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	961	* It is used (enabled by hardware) as system clock source after startup
<>	144:ef7eb2e8f9f7	962	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
<>	144:ef7eb2e8f9f7	963	* of the HSE used directly or indirectly as system clock (if the Clock
<>	144:ef7eb2e8f9f7	964	* Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	965	* @note HSI can not be stopped if it is used as system clock source. In this case,
<>	144:ef7eb2e8f9f7	966	* you have to select another source of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	967	* @note After enabling the HSI, the application software should wait on HSIRDY
<>	144:ef7eb2e8f9f7	968	* flag to be set indicating that HSI clock is stable and can be used as
<>	144:ef7eb2e8f9f7	969	* system clock source.
<>	144:ef7eb2e8f9f7	970	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	971	* clock cycles.
<>	144:ef7eb2e8f9f7	972	*/
<>	144:ef7eb2e8f9f7	973	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	974	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
<>	144:ef7eb2e8f9f7	977	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	978	* and temperature that influence the frequency of the internal HSI RC.
<>	144:ef7eb2e8f9f7	979	* @param __HSICalibrationValue__: specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	980	* This parameter must be a number between 0 and 0x1F.
<>	144:ef7eb2e8f9f7	981	*/
<>	144:ef7eb2e8f9f7	982	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
<>	144:ef7eb2e8f9f7	983	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
<>	144:ef7eb2e8f9f7	984
<>	144:ef7eb2e8f9f7	985	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
<>	144:ef7eb2e8f9f7	986	* @note After enabling the HSI, the application software should wait on
<>	144:ef7eb2e8f9f7	987	* HSIRDY flag to be set indicating that HSI clock is stable and can
<>	144:ef7eb2e8f9f7	988	* be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	989	* @note HSI can not be stopped if it is used directly or through the PLL
<>	144:ef7eb2e8f9f7	990	* as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	991	* of the system clock then stop the HSI.
<>	144:ef7eb2e8f9f7	992	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	993	* @param __STATE__: specifies the new state of the HSI.
<>	144:ef7eb2e8f9f7	994	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	995	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
<>	144:ef7eb2e8f9f7	996	* @arg RCC_HSI_ON: turn ON the HSI oscillator
<>	144:ef7eb2e8f9f7	997	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
<>	144:ef7eb2e8f9f7	998	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
<>	144:ef7eb2e8f9f7	999	* clock cycles.
<>	144:ef7eb2e8f9f7	1000	*/
<>	144:ef7eb2e8f9f7	1001	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	1002	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/**
<>	144:ef7eb2e8f9f7	1005	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
<>	144:ef7eb2e8f9f7	1006	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1007	* It is used (enabled by hardware) as system clock source after
<>	144:ef7eb2e8f9f7	1008	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
<>	144:ef7eb2e8f9f7	1009	* of failure of the HSE used directly or indirectly as system clock
<>	144:ef7eb2e8f9f7	1010	* (if the Clock Security System CSS is enabled).
<>	144:ef7eb2e8f9f7	1011	* @note MSI can not be stopped if it is used as system clock source.
<>	144:ef7eb2e8f9f7	1012	* In this case, you have to select another source of the system
<>	144:ef7eb2e8f9f7	1013	* clock then stop the MSI.
<>	144:ef7eb2e8f9f7	1014	* @note After enabling the MSI, the application software should wait on
<>	144:ef7eb2e8f9f7	1015	* MSIRDY flag to be set indicating that MSI clock is stable and can
<>	144:ef7eb2e8f9f7	1016	* be used as system clock source.
<>	144:ef7eb2e8f9f7	1017	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
<>	144:ef7eb2e8f9f7	1018	* clock cycles.
<>	144:ef7eb2e8f9f7	1019	*/
<>	144:ef7eb2e8f9f7	1020	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
<>	144:ef7eb2e8f9f7	1021	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023
<>	144:ef7eb2e8f9f7	1024	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
<>	144:ef7eb2e8f9f7	1025	* @note The calibration is used to compensate for the variations in voltage
<>	144:ef7eb2e8f9f7	1026	* and temperature that influence the frequency of the internal MSI RC.
<>	144:ef7eb2e8f9f7	1027	* Refer to the Application Note AN3300 for more details on how to
<>	144:ef7eb2e8f9f7	1028	* calibrate the MSI.
<>	144:ef7eb2e8f9f7	1029	* @param __MSICalibrationValue__: specifies the calibration trimming value.
<>	144:ef7eb2e8f9f7	1030	* This parameter must be a number between 0 and 0xFF.
<>	144:ef7eb2e8f9f7	1031	*/
<>	144:ef7eb2e8f9f7	1032	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
<>	144:ef7eb2e8f9f7	1033	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
<>	144:ef7eb2e8f9f7	1034
<>	144:ef7eb2e8f9f7	1035	/**
<>	144:ef7eb2e8f9f7	1036	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
<>	144:ef7eb2e8f9f7	1037	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
<>	144:ef7eb2e8f9f7	1038	* around 2.097 MHz. The MSI clock does not change after wake-up from
<>	144:ef7eb2e8f9f7	1039	* STOP mode.
<>	144:ef7eb2e8f9f7	1040	* @note The MSI clock range can be modified on the fly.
<>	144:ef7eb2e8f9f7	1041	* @param __RCC_MSIRange__: specifies the MSI Clock range.
<>	144:ef7eb2e8f9f7	1042	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	1043	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
<>	144:ef7eb2e8f9f7	1044	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
<>	144:ef7eb2e8f9f7	1045	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
<>	144:ef7eb2e8f9f7	1046	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
<>	144:ef7eb2e8f9f7	1047	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
<>	144:ef7eb2e8f9f7	1048	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
<>	144:ef7eb2e8f9f7	1049	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
<>	144:ef7eb2e8f9f7	1050	*/
<>	144:ef7eb2e8f9f7	1051	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
<>	144:ef7eb2e8f9f7	1052	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
<>	144:ef7eb2e8f9f7	1053
<>	144:ef7eb2e8f9f7	1054	/** @brief Macro to get the Internal Multi Speed oscillator (__MSI__) clock range in run mode
<>	144:ef7eb2e8f9f7	1055	* @retval MSI clock range.
<>	144:ef7eb2e8f9f7	1056	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	1057	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
<>	144:ef7eb2e8f9f7	1058	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
<>	144:ef7eb2e8f9f7	1059	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
<>	144:ef7eb2e8f9f7	1060	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
<>	144:ef7eb2e8f9f7	1061	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
<>	144:ef7eb2e8f9f7	1062	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
<>	144:ef7eb2e8f9f7	1063	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
<>	144:ef7eb2e8f9f7	1064
<>	144:ef7eb2e8f9f7	1065	*/
<>	144:ef7eb2e8f9f7	1066	#define __HAL_RCC_GET_MSI_RANGE() \
<>	144:ef7eb2e8f9f7	1067	((uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSIRANGE) >> 12))
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
<>	144:ef7eb2e8f9f7	1070	* @note After enabling the LSI, the application software should wait on
<>	144:ef7eb2e8f9f7	1071	* LSIRDY flag to be set indicating that LSI clock is stable and can
<>	144:ef7eb2e8f9f7	1072	* be used to clock the IWDG and/or the RTC.
<>	144:ef7eb2e8f9f7	1073	* @note LSI can not be disabled if the IWDG is running.
<>	144:ef7eb2e8f9f7	1074	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
<>	144:ef7eb2e8f9f7	1075	* clock cycles.
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	1078	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
<>	144:ef7eb2e8f9f7	1079
<>	144:ef7eb2e8f9f7	1080	/**
<>	144:ef7eb2e8f9f7	1081	* @brief Macro to configure the External High Speed oscillator (HSE).
<>	144:ef7eb2e8f9f7	1082	* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<>	144:ef7eb2e8f9f7	1083	* supported by this macro. User should request a transition to HSE Off
<>	144:ef7eb2e8f9f7	1084	* first and then HSE On or HSE Bypass.
<>	144:ef7eb2e8f9f7	1085	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
<>	144:ef7eb2e8f9f7	1086	* software should wait on HSERDY flag to be set indicating that HSE clock
<>	144:ef7eb2e8f9f7	1087	* is stable and can be used to clock the PLL and/or system clock.
<>	144:ef7eb2e8f9f7	1088	* @note HSE state can not be changed if it is used directly or through the
<>	144:ef7eb2e8f9f7	1089	* PLL as system clock. In this case, you have to select another source
<>	144:ef7eb2e8f9f7	1090	* of the system clock then change the HSE state (ex. disable it).
<>	144:ef7eb2e8f9f7	1091	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1092	* @note This function reset the CSSON bit, so if the clock security system(CSS)
<>	144:ef7eb2e8f9f7	1093	* was previously enabled you have to enable it again after calling this
<>	144:ef7eb2e8f9f7	1094	* function.
<>	144:ef7eb2e8f9f7	1095	* @param __STATE__: specifies the new state of the HSE.
<>	144:ef7eb2e8f9f7	1096	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1097	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1098	* 6 HSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	1099	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
<>	144:ef7eb2e8f9f7	1100	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	1101	*/
<>	144:ef7eb2e8f9f7	1102	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	1103	do { \
<>	144:ef7eb2e8f9f7	1104	__IO uint32_t tmpreg; \
<>	144:ef7eb2e8f9f7	1105	if((__STATE__) == RCC_HSE_ON) \
<>	144:ef7eb2e8f9f7	1106	{ \
<>	144:ef7eb2e8f9f7	1107	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	1108	} \
<>	144:ef7eb2e8f9f7	1109	else if((__STATE__) == RCC_HSE_BYPASS) \
<>	144:ef7eb2e8f9f7	1110	{ \
<>	144:ef7eb2e8f9f7	1111	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	1112	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	1113	SET_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	1114	} \
<>	144:ef7eb2e8f9f7	1115	else \
<>	144:ef7eb2e8f9f7	1116	{ \
<>	144:ef7eb2e8f9f7	1117	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	1118	/* Delay after an RCC peripheral clock */ \
<>	144:ef7eb2e8f9f7	1119	tmpreg = READ_BIT(RCC->CR, RCC_CR_HSEON); \
<>	144:ef7eb2e8f9f7	1120	UNUSED(tmpreg); \
<>	144:ef7eb2e8f9f7	1121	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
<>	144:ef7eb2e8f9f7	1122	} \
<>	144:ef7eb2e8f9f7	1123	} while(0)
<>	144:ef7eb2e8f9f7	1124
<>	144:ef7eb2e8f9f7	1125	/**
<>	144:ef7eb2e8f9f7	1126	* @brief Macro to configure the External Low Speed oscillator (LSE).
<>	144:ef7eb2e8f9f7	1127	* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<>	144:ef7eb2e8f9f7	1128	* supported by this macro. User should request a transition to LSE Off
<>	144:ef7eb2e8f9f7	1129	* first and then LSE On or LSE Bypass.
<>	144:ef7eb2e8f9f7	1130	* @note As the LSE is in the Backup domain and write access is denied to
<>	144:ef7eb2e8f9f7	1131	* this domain after reset, you have to enable write access using
<>	144:ef7eb2e8f9f7	1132	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
<>	144:ef7eb2e8f9f7	1133	* (to be done once after reset).
<>	144:ef7eb2e8f9f7	1134	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
<>	144:ef7eb2e8f9f7	1135	* software should wait on LSERDY flag to be set indicating that LSE clock
<>	144:ef7eb2e8f9f7	1136	* is stable and can be used to clock the RTC.
<>	144:ef7eb2e8f9f7	1137	* @param __STATE__: specifies the new state of the LSE.
<>	144:ef7eb2e8f9f7	1138	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1139	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
<>	144:ef7eb2e8f9f7	1140	* 6 LSE oscillator clock cycles.
<>	144:ef7eb2e8f9f7	1141	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
<>	144:ef7eb2e8f9f7	1142	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
<>	144:ef7eb2e8f9f7	1143	*/
<>	144:ef7eb2e8f9f7	1144	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
<>	144:ef7eb2e8f9f7	1145	do { \
<>	144:ef7eb2e8f9f7	1146	if((__STATE__) == RCC_LSE_ON) \
<>	144:ef7eb2e8f9f7	1147	{ \
<>	144:ef7eb2e8f9f7	1148	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
<>	144:ef7eb2e8f9f7	1149	} \
<>	144:ef7eb2e8f9f7	1150	else if((__STATE__) == RCC_LSE_OFF) \
<>	144:ef7eb2e8f9f7	1151	{ \
<>	144:ef7eb2e8f9f7	1152	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
<>	144:ef7eb2e8f9f7	1153	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<>	144:ef7eb2e8f9f7	1154	} \
<>	144:ef7eb2e8f9f7	1155	else if((__STATE__) == RCC_LSE_BYPASS) \
<>	144:ef7eb2e8f9f7	1156	{ \
<>	144:ef7eb2e8f9f7	1157	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
<>	144:ef7eb2e8f9f7	1158	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<>	144:ef7eb2e8f9f7	1159	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
<>	144:ef7eb2e8f9f7	1160	} \
<>	144:ef7eb2e8f9f7	1161	else \
<>	144:ef7eb2e8f9f7	1162	{ \
<>	144:ef7eb2e8f9f7	1163	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
<>	144:ef7eb2e8f9f7	1164	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
<>	144:ef7eb2e8f9f7	1165	} \
<>	144:ef7eb2e8f9f7	1166	} while(0)
<>	144:ef7eb2e8f9f7	1167
<>	144:ef7eb2e8f9f7	1168
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/**
<>	144:ef7eb2e8f9f7	1171	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
<>	144:ef7eb2e8f9f7	1172	* @note As the RTC clock configuration bits are in the RTC domain and write
<>	144:ef7eb2e8f9f7	1173	* access is denied to this domain after reset, you have to enable write
<>	144:ef7eb2e8f9f7	1174	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
<>	144:ef7eb2e8f9f7	1175	* the RTC clock source (to be done once after reset).
<>	144:ef7eb2e8f9f7	1176	* @note Once the RTC clock is configured it cannot be changed unless the RTC
<>	144:ef7eb2e8f9f7	1177	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
<>	144:ef7eb2e8f9f7	1178	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
<>	144:ef7eb2e8f9f7	1179	*
<>	144:ef7eb2e8f9f7	1180	* @param __RTCCLKSOURCE__: specifies the RTC clock source.
<>	144:ef7eb2e8f9f7	1181	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1182	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
<>	144:ef7eb2e8f9f7	1183	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
<>	144:ef7eb2e8f9f7	1184	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
<>	144:ef7eb2e8f9f7	1185	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
<>	144:ef7eb2e8f9f7	1186	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
<>	144:ef7eb2e8f9f7	1187	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
<>	144:ef7eb2e8f9f7	1188	*
<>	144:ef7eb2e8f9f7	1189	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
<>	144:ef7eb2e8f9f7	1190	* work in STOP and STANDBY modes, and can be used as wakeup source.
<>	144:ef7eb2e8f9f7	1191	* However, when the HSE clock is used as RTC clock source, the RTC
<>	144:ef7eb2e8f9f7	1192	* cannot be used in STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1193	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
<>	144:ef7eb2e8f9f7	1194	* RTC clock source).
<>	144:ef7eb2e8f9f7	1195	*/
<>	144:ef7eb2e8f9f7	1196
<>	144:ef7eb2e8f9f7	1197	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__) (((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
<>	144:ef7eb2e8f9f7	1198	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, (uint32_t)((__RTCCLKSOURCE__) & RCC_CR_RTCPRE)) : \
<>	144:ef7eb2e8f9f7	1199	CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
<>	144:ef7eb2e8f9f7	1200
<>	144:ef7eb2e8f9f7	1201	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSOURCE__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSOURCE__); \
<>	144:ef7eb2e8f9f7	1202	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)((__RTCCLKSOURCE__) & RCC_CSR_RTCSEL)); \
<>	144:ef7eb2e8f9f7	1203	} while (0)
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205
<>	144:ef7eb2e8f9f7	1206	/**
<>	144:ef7eb2e8f9f7	1207	* @brief Get the RTC and LCD clock (RTCCLK / LCDCLK).
<>	144:ef7eb2e8f9f7	1208	*
<>	144:ef7eb2e8f9f7	1209	* @retval The clock source can be one of the following values:
<>	144:ef7eb2e8f9f7	1210	* @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
<>	144:ef7eb2e8f9f7	1211	* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
<>	144:ef7eb2e8f9f7	1212	* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
<>	144:ef7eb2e8f9f7	1213	* @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
<>	144:ef7eb2e8f9f7	1214	*
<>	144:ef7eb2e8f9f7	1215	*/
<>	144:ef7eb2e8f9f7	1216	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/**
<>	144:ef7eb2e8f9f7	1219	* @brief Get the RTC and LCD HSE clock divider (RTCCLK / LCDCLK).
<>	144:ef7eb2e8f9f7	1220	*
<>	144:ef7eb2e8f9f7	1221	* @retval Returned value can be one of the following values:
<>	144:ef7eb2e8f9f7	1222	* @arg @ref RCC_RTC_HSE_DIV_2: HSE divided by 2 selected as RTC clock
<>	144:ef7eb2e8f9f7	1223	* @arg @ref RCC_RTC_HSE_DIV_4: HSE divided by 4 selected as RTC clock
<>	144:ef7eb2e8f9f7	1224	* @arg @ref RCC_RTC_HSE_DIV_8: HSE divided by 8 selected as RTC clock
<>	144:ef7eb2e8f9f7	1225	* @arg @ref RCC_RTC_HSE_DIV_16: HSE divided by 16 selected as RTC clock
<>	144:ef7eb2e8f9f7	1226	*
<>	144:ef7eb2e8f9f7	1227	*/
<>	144:ef7eb2e8f9f7	1228	#define __HAL_RCC_GET_RTC_HSE_PRESCALER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_RTCPRE)))
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/** @brief Macros to enable or disable the main PLL.
<>	144:ef7eb2e8f9f7	1231	* @note After enabling the main PLL, the application software should wait on
<>	144:ef7eb2e8f9f7	1232	* PLLRDY flag to be set indicating that PLL clock is stable and can
<>	144:ef7eb2e8f9f7	1233	* be used as system clock source.
<>	144:ef7eb2e8f9f7	1234	* @note The main PLL can not be disabled if it is used as system clock source
<>	144:ef7eb2e8f9f7	1235	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
<>	144:ef7eb2e8f9f7	1236	*/
<>	144:ef7eb2e8f9f7	1237	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	1238	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
<>	144:ef7eb2e8f9f7	1241	* @note This function must be used only when the main PLL is disabled.
<>	144:ef7eb2e8f9f7	1242	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
<>	144:ef7eb2e8f9f7	1243	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1244	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1245	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
<>	144:ef7eb2e8f9f7	1246	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
<>	144:ef7eb2e8f9f7	1247	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	1248	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
<>	144:ef7eb2e8f9f7	1249	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
<>	144:ef7eb2e8f9f7	1250	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
<>	144:ef7eb2e8f9f7	1251	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
<>	144:ef7eb2e8f9f7	1252	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
<>	144:ef7eb2e8f9f7	1253	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
<>	144:ef7eb2e8f9f7	1254	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
<>	144:ef7eb2e8f9f7	1255	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
<>	144:ef7eb2e8f9f7	1256	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
<>	144:ef7eb2e8f9f7	1257	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
<>	144:ef7eb2e8f9f7	1258	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
<>	144:ef7eb2e8f9f7	1259	* in Range 3.
<>	144:ef7eb2e8f9f7	1260	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
<>	144:ef7eb2e8f9f7	1261	* This parameter must be one of the following values:
<>	144:ef7eb2e8f9f7	1262	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
<>	144:ef7eb2e8f9f7	1263	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
<>	144:ef7eb2e8f9f7	1264	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
<>	144:ef7eb2e8f9f7	1265	*/
<>	144:ef7eb2e8f9f7	1266
<>	144:ef7eb2e8f9f7	1267	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__ , __PLLMUL__ ,__PLLDIV__ ) \
<>	144:ef7eb2e8f9f7	1268	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSOURCE__)))
<>	144:ef7eb2e8f9f7	1269
<>	144:ef7eb2e8f9f7	1270	/** @brief Macro to get the oscillator used as PLL clock source.
<>	144:ef7eb2e8f9f7	1271	* @retval The oscillator used as PLL clock source. The returned value can be one
<>	144:ef7eb2e8f9f7	1272	* of the following:
<>	144:ef7eb2e8f9f7	1273	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1274	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
<>	144:ef7eb2e8f9f7	1275	*/
<>	144:ef7eb2e8f9f7	1276	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
<>	144:ef7eb2e8f9f7	1277
<>	144:ef7eb2e8f9f7	1278	/**
<>	144:ef7eb2e8f9f7	1279	* @brief Macro to configure the system clock source.
<>	144:ef7eb2e8f9f7	1280	* @param __SYSCLKSOURCE__: specifies the system clock source.
<>	144:ef7eb2e8f9f7	1281	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1282	* - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1283	* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1284	* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
<>	144:ef7eb2e8f9f7	1285	* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
<>	144:ef7eb2e8f9f7	1286	* @retval None
<>	144:ef7eb2e8f9f7	1287	*/
<>	144:ef7eb2e8f9f7	1288	#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
<>	144:ef7eb2e8f9f7	1289	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/** @brief Macro to get the clock source used as system clock.
<>	144:ef7eb2e8f9f7	1292	* @retval The clock source used as system clock. The returned value can be one
<>	144:ef7eb2e8f9f7	1293	* of the following:
<>	144:ef7eb2e8f9f7	1294	* - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock.
<>	144:ef7eb2e8f9f7	1295	* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
<>	144:ef7eb2e8f9f7	1296	* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
<>	144:ef7eb2e8f9f7	1297	* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
<>	144:ef7eb2e8f9f7	1298	*/
<>	144:ef7eb2e8f9f7	1299	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
<>	144:ef7eb2e8f9f7	1300
<>	144:ef7eb2e8f9f7	1301
<>	144:ef7eb2e8f9f7	1302	/** @brief Macro to configure the MCO clock.
<>	144:ef7eb2e8f9f7	1303	* @param __MCOCLKSOURCE__ specifies the MCO clock source.
<>	144:ef7eb2e8f9f7	1304	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1305	* @arg RCC_CFGR_MCO_HSI: HSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	1306	* @arg RCC_CFGR_MCO_MSI: MSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	1307	* @arg RCC_CFGR_MCO_HSE: HSE clock selected as MCO source
<>	144:ef7eb2e8f9f7	1308	* @arg RCC_CFGR_MCO_PLL: PLL clock selected as MCO source
<>	144:ef7eb2e8f9f7	1309	* @arg RCC_CFGR_MCO_LSI: LSI clock selected as MCO source
<>	144:ef7eb2e8f9f7	1310	* @arg RCC_CFGR_MCO_LSE: LSE clock selected as MCO source
<>	144:ef7eb2e8f9f7	1311	* @param __MCODIV__ specifies the MCO clock prescaler.
<>	144:ef7eb2e8f9f7	1312	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1313	* @arg RCC_CFGR_MCO_PRE_1: no division applied to MCO clock
<>	144:ef7eb2e8f9f7	1314	* @arg RCC_CFGR_MCO_PRE_2: division by 2 applied to MCO clock
<>	144:ef7eb2e8f9f7	1315	* @arg RCC_CFGR_MCO_PRE_4: division by 4 applied to MCO clock
<>	144:ef7eb2e8f9f7	1316	* @arg RCC_CFGR_MCO_PRE_8: division by 8 applied to MCO clock
<>	144:ef7eb2e8f9f7	1317	* @arg RCC_CFGR_MCO_PRE_16: division by 16 applied to MCO clock
<>	144:ef7eb2e8f9f7	1318	*/
<>	144:ef7eb2e8f9f7	1319
<>	144:ef7eb2e8f9f7	1320	#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
<>	144:ef7eb2e8f9f7	1321	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL \| RCC_CFGR_MCO_PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
<>	144:ef7eb2e8f9f7	1322
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
<>	144:ef7eb2e8f9f7	1325	* @brief macros to manage the specified RCC Flags and interrupts.
<>	144:ef7eb2e8f9f7	1326	* @{
<>	144:ef7eb2e8f9f7	1327	*/
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
<>	144:ef7eb2e8f9f7	1330	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1331	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
<>	144:ef7eb2e8f9f7	1332	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
<>	144:ef7eb2e8f9f7	1333	* automatically generated. The NMI will be executed indefinitely, and
<>	144:ef7eb2e8f9f7	1334	* since NMI has higher priority than any other IRQ (and main program)
<>	144:ef7eb2e8f9f7	1335	* the application will be stacked in the NMI ISR unless the CSS interrupt
<>	144:ef7eb2e8f9f7	1336	* pending bit is cleared.
<>	144:ef7eb2e8f9f7	1337	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
<>	144:ef7eb2e8f9f7	1338	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1339	* @arg RCC_IT_LSIRDY: LSI ready interrupt
<>	144:ef7eb2e8f9f7	1340	* @arg RCC_IT_LSERDY: LSE ready interrupt
<>	144:ef7eb2e8f9f7	1341	* @arg RCC_IT_HSIRDY: HSI ready interrupt
<>	144:ef7eb2e8f9f7	1342	* @arg RCC_IT_HSERDY: HSE ready interrupt
<>	144:ef7eb2e8f9f7	1343	* @arg RCC_IT_PLLRDY: PLL ready interrupt
<>	144:ef7eb2e8f9f7	1344	* @arg RCC_IT_MSIRDY: MSI ready interrupt
<>	144:ef7eb2e8f9f7	1345	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
<>	144:ef7eb2e8f9f7	1346	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
<>	144:ef7eb2e8f9f7	1347	*/
<>	144:ef7eb2e8f9f7	1348	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
<>	144:ef7eb2e8f9f7	1351	* the selected interrupts).
<>	144:ef7eb2e8f9f7	1352	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
<>	144:ef7eb2e8f9f7	1353	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
<>	144:ef7eb2e8f9f7	1354	* automatically generated. The NMI will be executed indefinitely, and
<>	144:ef7eb2e8f9f7	1355	* since NMI has higher priority than any other IRQ (and main program)
<>	144:ef7eb2e8f9f7	1356	* the application will be stacked in the NMI ISR unless the CSS interrupt
<>	144:ef7eb2e8f9f7	1357	* pending bit is cleared.
<>	144:ef7eb2e8f9f7	1358	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
<>	144:ef7eb2e8f9f7	1359	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1360	* @arg RCC_IT_LSIRDY: LSI ready interrupt
<>	144:ef7eb2e8f9f7	1361	* @arg RCC_IT_LSERDY: LSE ready interrupt
<>	144:ef7eb2e8f9f7	1362	* @arg RCC_IT_HSIRDY: HSI ready interrupt
<>	144:ef7eb2e8f9f7	1363	* @arg RCC_IT_HSERDY: HSE ready interrupt
<>	144:ef7eb2e8f9f7	1364	* @arg RCC_IT_PLLRDY: PLL ready interrupt
<>	144:ef7eb2e8f9f7	1365	* @arg RCC_IT_MSIRDY: MSI ready interrupt
<>	144:ef7eb2e8f9f7	1366	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
<>	144:ef7eb2e8f9f7	1367	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
<>	144:ef7eb2e8f9f7	1368
<>	144:ef7eb2e8f9f7	1369	*/
<>	144:ef7eb2e8f9f7	1370	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1371
<>	144:ef7eb2e8f9f7	1372	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
<>	144:ef7eb2e8f9f7	1373	* bits to clear the selected interrupt pending bits.
<>	144:ef7eb2e8f9f7	1374	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
<>	144:ef7eb2e8f9f7	1375	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	1376	* @arg RCC_IT_LSIRDY: LSI ready interrupt
<>	144:ef7eb2e8f9f7	1377	* @arg RCC_IT_LSERDY: LSE ready interrupt
<>	144:ef7eb2e8f9f7	1378	* @arg RCC_IT_HSIRDY: HSI ready interrupt
<>	144:ef7eb2e8f9f7	1379	* @arg RCC_IT_HSERDY: HSE ready interrupt
<>	144:ef7eb2e8f9f7	1380	* @arg RCC_IT_PLLRDY: PLL ready interrupt
<>	144:ef7eb2e8f9f7	1381	* @arg RCC_IT_MSIRDY: MSI ready interrupt
<>	144:ef7eb2e8f9f7	1382	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
<>	144:ef7eb2e8f9f7	1383	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
<>	144:ef7eb2e8f9f7	1384	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1385	*/
<>	144:ef7eb2e8f9f7	1386	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1387
<>	144:ef7eb2e8f9f7	1388	/** @brief Check the RCC's interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	1389	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
<>	144:ef7eb2e8f9f7	1390	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1391	* @arg RCC_IT_LSIRDY: LSI ready interrupt
<>	144:ef7eb2e8f9f7	1392	* @arg RCC_IT_LSERDY: LSE ready interrupt
<>	144:ef7eb2e8f9f7	1393	* @arg RCC_IT_HSIRDY: HSI ready interrupt
<>	144:ef7eb2e8f9f7	1394	* @arg RCC_IT_HSERDY: HSE ready interrupt
<>	144:ef7eb2e8f9f7	1395	* @arg RCC_IT_PLLRDY: PLL ready interrupt
<>	144:ef7eb2e8f9f7	1396	* @arg RCC_IT_MSIRDY: MSI ready interrupt
<>	144:ef7eb2e8f9f7	1397	* @arg RCC_IT_CSSLSE: LSE CSS interrupt
<>	144:ef7eb2e8f9f7	1398	* @arg RCC_IT_CSSHSE: Clock Security System interrupt
<>	144:ef7eb2e8f9f7	1399	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1400	*/
<>	144:ef7eb2e8f9f7	1401	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/** @brief Set RMVF bit to clear the reset flags.
<>	144:ef7eb2e8f9f7	1405	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
<>	144:ef7eb2e8f9f7	1406	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
<>	144:ef7eb2e8f9f7	1407	*/
<>	144:ef7eb2e8f9f7	1408	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	/** @brief Check RCC flag is set or not.
<>	144:ef7eb2e8f9f7	1411	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	1412	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1413	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
<>	144:ef7eb2e8f9f7	1414	* @arg RCC_FLAG_HSIDIV: HSI clock divider flag
<>	144:ef7eb2e8f9f7	1415	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
<>	144:ef7eb2e8f9f7	1416	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
<>	144:ef7eb2e8f9f7	1417	* @arg RCC_FLAG_PLLRDY: PLL clock ready
<>	144:ef7eb2e8f9f7	1418	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
<>	144:ef7eb2e8f9f7	1419	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
<>	144:ef7eb2e8f9f7	1420	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
<>	144:ef7eb2e8f9f7	1421	* @arg RCC_FLAG_FWRST: Firewall reset
<>	144:ef7eb2e8f9f7	1422	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
<>	144:ef7eb2e8f9f7	1423	* @arg RCC_FLAG_PINRST: Pin reset
<>	144:ef7eb2e8f9f7	1424	* @arg RCC_FLAG_PORRST: POR/PDR reset
<>	144:ef7eb2e8f9f7	1425	* @arg RCC_FLAG_SFTRST: Software reset
<>	144:ef7eb2e8f9f7	1426	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
<>	144:ef7eb2e8f9f7	1427	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
<>	144:ef7eb2e8f9f7	1428	* @arg RCC_FLAG_LPWRRST: Low Power reset
<>	144:ef7eb2e8f9f7	1429	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1430	*/
<>	144:ef7eb2e8f9f7	1431	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
<>	144:ef7eb2e8f9f7	1432	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
<>	144:ef7eb2e8f9f7	1433
<>	144:ef7eb2e8f9f7	1434	/**
<>	144:ef7eb2e8f9f7	1435	* @}
<>	144:ef7eb2e8f9f7	1436	*/
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/**
<>	144:ef7eb2e8f9f7	1439	* @}
<>	144:ef7eb2e8f9f7	1440	*/
<>	144:ef7eb2e8f9f7	1441
<>	144:ef7eb2e8f9f7	1442
<>	144:ef7eb2e8f9f7	1443	/* Private constants ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1444	/** @defgroup RCC_Private_Constants RCC Private Constants
<>	144:ef7eb2e8f9f7	1445	* @{
<>	144:ef7eb2e8f9f7	1446	*/
<>	144:ef7eb2e8f9f7	1447	/* Defines used for Flags */
<>	144:ef7eb2e8f9f7	1448	#define RCC_FLAG_MASK ((uint8_t)0x1F)
<>	144:ef7eb2e8f9f7	1449
<>	144:ef7eb2e8f9f7	1450	/**
<>	144:ef7eb2e8f9f7	1451	* @}
<>	144:ef7eb2e8f9f7	1452	*/
<>	144:ef7eb2e8f9f7	1453
<>	144:ef7eb2e8f9f7	1454	/* Private macros ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1455	/** @addtogroup RCC_Private_Macros
<>	144:ef7eb2e8f9f7	1456	* @{
<>	144:ef7eb2e8f9f7	1457	*/
<>	144:ef7eb2e8f9f7	1458
<>	144:ef7eb2e8f9f7	1459	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	1460	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
<>	144:ef7eb2e8f9f7	1461	#else
<>	144:ef7eb2e8f9f7	1462	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
<>	144:ef7eb2e8f9f7	1463	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
<>	144:ef7eb2e8f9f7	1464
<>	144:ef7eb2e8f9f7	1465	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1466	((__HSE__) == RCC_HSE_BYPASS))
<>	144:ef7eb2e8f9f7	1467	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
<>	144:ef7eb2e8f9f7	1468	((__LSE__) == RCC_LSE_BYPASS))
<>	144:ef7eb2e8f9f7	1469
<>	144:ef7eb2e8f9f7	1470	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
<>	144:ef7eb2e8f9f7	1471	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
<>	144:ef7eb2e8f9f7	1472	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
<>	144:ef7eb2e8f9f7	1473	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
<>	144:ef7eb2e8f9f7	1474	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
<>	144:ef7eb2e8f9f7	1475	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
<>	144:ef7eb2e8f9f7	1476	((__RANGE__) == RCC_MSIRANGE_6))
<>	144:ef7eb2e8f9f7	1477
<>	144:ef7eb2e8f9f7	1478	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
<>	144:ef7eb2e8f9f7	1479	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
<>	144:ef7eb2e8f9f7	1480	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
<>	144:ef7eb2e8f9f7	1481
<>	144:ef7eb2e8f9f7	1482	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
<>	144:ef7eb2e8f9f7	1483
<>	144:ef7eb2e8f9f7	1484	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1485	((__SOURCE__) == RCC_PLLSOURCE_HSE))
<>	144:ef7eb2e8f9f7	1486
<>	144:ef7eb2e8f9f7	1487	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
<>	144:ef7eb2e8f9f7	1488	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
<>	144:ef7eb2e8f9f7	1489	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
<>	144:ef7eb2e8f9f7	1490	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
<>	144:ef7eb2e8f9f7	1491	((__MUL__) == RCC_PLLMUL_48))
<>	144:ef7eb2e8f9f7	1492
<>	144:ef7eb2e8f9f7	1493	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
<>	144:ef7eb2e8f9f7	1494	((__DIV__) == RCC_PLLDIV_4))
<>	144:ef7eb2e8f9f7	1495
<>	144:ef7eb2e8f9f7	1496	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
<>	144:ef7eb2e8f9f7	1497
<>	144:ef7eb2e8f9f7	1498	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
<>	144:ef7eb2e8f9f7	1499	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
<>	144:ef7eb2e8f9f7	1500	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	1501	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
<>	144:ef7eb2e8f9f7	1502
<>	144:ef7eb2e8f9f7	1503	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1504	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1505	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
<>	144:ef7eb2e8f9f7	1506	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
<>	144:ef7eb2e8f9f7	1507	((__HCLK__) == RCC_SYSCLK_DIV512))
<>	144:ef7eb2e8f9f7	1508
<>	144:ef7eb2e8f9f7	1509	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1510	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1511	((__PCLK__) == RCC_HCLK_DIV16))
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1514	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
<>	144:ef7eb2e8f9f7	1515	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	1516	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
<>	144:ef7eb2e8f9f7	1517	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
<>	144:ef7eb2e8f9f7	1518	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
<>	144:ef7eb2e8f9f7	1519
<>	144:ef7eb2e8f9f7	1520	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) \
<>	144:ef7eb2e8f9f7	1521	&& !defined (STM32L011xx) && !defined (STM32L021xx)
<>	144:ef7eb2e8f9f7	1522	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	1523	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	1524	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
<>	144:ef7eb2e8f9f7	1525	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
<>	144:ef7eb2e8f9f7	1526	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
<>	144:ef7eb2e8f9f7	1527	#else
<>	144:ef7eb2e8f9f7	1528	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
<>	144:ef7eb2e8f9f7	1529	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
<>	144:ef7eb2e8f9f7	1530	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
<>	144:ef7eb2e8f9f7	1531	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
<>	144:ef7eb2e8f9f7	1532	#endif
<>	144:ef7eb2e8f9f7	1533
<>	144:ef7eb2e8f9f7	1534	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
<>	144:ef7eb2e8f9f7	1535	((__DIV__) == RCC_MCODIV_2) \|\| \
<>	144:ef7eb2e8f9f7	1536	((__DIV__) == RCC_MCODIV_4) \|\| \
<>	144:ef7eb2e8f9f7	1537	((__DIV__) == RCC_MCODIV_8) \|\| \
<>	144:ef7eb2e8f9f7	1538	((__DIV__) == RCC_MCODIV_16))
<>	144:ef7eb2e8f9f7	1539
<>	144:ef7eb2e8f9f7	1540	#if defined(STM32L031xx) \|\| defined(STM32L041xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
<>	144:ef7eb2e8f9f7	1541	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
<>	144:ef7eb2e8f9f7	1542	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2) \|\| ((__MCOx__) == RCC_MCO3))
<>	144:ef7eb2e8f9f7	1543	#else
<>	144:ef7eb2e8f9f7	1544	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
<>	144:ef7eb2e8f9f7	1545
<>	144:ef7eb2e8f9f7	1546	#endif
<>	144:ef7eb2e8f9f7	1547
<>	144:ef7eb2e8f9f7	1548	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
<>	144:ef7eb2e8f9f7	1549	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
<>	144:ef7eb2e8f9f7	1550
<>	144:ef7eb2e8f9f7	1551	/**
<>	144:ef7eb2e8f9f7	1552	* @}
<>	144:ef7eb2e8f9f7	1553	*/
<>	144:ef7eb2e8f9f7	1554
<>	144:ef7eb2e8f9f7	1555	/* Include RCC HAL Extension module */
<>	144:ef7eb2e8f9f7	1556	#include "stm32l0xx_hal_rcc_ex.h"
<>	144:ef7eb2e8f9f7	1557
<>	144:ef7eb2e8f9f7	1558	/** @defgroup RCC_Exported_Functions RCC Exported Functions
<>	144:ef7eb2e8f9f7	1559	* @{
<>	144:ef7eb2e8f9f7	1560	*/
<>	144:ef7eb2e8f9f7	1561
<>	144:ef7eb2e8f9f7	1562	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1563	* @{
<>	144:ef7eb2e8f9f7	1564	*/
<>	144:ef7eb2e8f9f7	1565	void HAL_RCC_DeInit(void);
<>	144:ef7eb2e8f9f7	1566	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1567	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
<>	144:ef7eb2e8f9f7	1568	/**
<>	144:ef7eb2e8f9f7	1569	* @}
<>	144:ef7eb2e8f9f7	1570	*/
<>	144:ef7eb2e8f9f7	1571
<>	144:ef7eb2e8f9f7	1572	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1573	* @{
<>	144:ef7eb2e8f9f7	1574	*/
<>	144:ef7eb2e8f9f7	1575	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
<>	144:ef7eb2e8f9f7	1576	#if !defined (STM32L011xx) && !defined (STM32L021xx)
<>	144:ef7eb2e8f9f7	1577	void HAL_RCC_EnableCSS(void);
<>	144:ef7eb2e8f9f7	1578	#endif
<>	144:ef7eb2e8f9f7	1579	uint32_t HAL_RCC_GetSysClockFreq(void);
<>	144:ef7eb2e8f9f7	1580	uint32_t HAL_RCC_GetHCLKFreq(void);
<>	144:ef7eb2e8f9f7	1581	uint32_t HAL_RCC_GetPCLK1Freq(void);
<>	144:ef7eb2e8f9f7	1582	uint32_t HAL_RCC_GetPCLK2Freq(void);
<>	144:ef7eb2e8f9f7	1583	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
<>	144:ef7eb2e8f9f7	1584	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
<>	144:ef7eb2e8f9f7	1585	/* CSS NMI IRQ handler */
<>	144:ef7eb2e8f9f7	1586	void HAL_RCC_NMI_IRQHandler(void);
<>	144:ef7eb2e8f9f7	1587
<>	144:ef7eb2e8f9f7	1588	/* User Callbacks in non blocking mode (IT mode) */
<>	144:ef7eb2e8f9f7	1589	void HAL_RCC_CSSCallback(void);
<>	144:ef7eb2e8f9f7	1590	/**
<>	144:ef7eb2e8f9f7	1591	* @}
<>	144:ef7eb2e8f9f7	1592	*/
<>	144:ef7eb2e8f9f7	1593
<>	144:ef7eb2e8f9f7	1594	/**
<>	144:ef7eb2e8f9f7	1595	* @}
<>	144:ef7eb2e8f9f7	1596	*/
<>	144:ef7eb2e8f9f7	1597
<>	144:ef7eb2e8f9f7	1598
<>	144:ef7eb2e8f9f7	1599	/**
<>	144:ef7eb2e8f9f7	1600	* @}
<>	144:ef7eb2e8f9f7	1601	*/
<>	144:ef7eb2e8f9f7	1602
<>	144:ef7eb2e8f9f7	1603	/**
<>	144:ef7eb2e8f9f7	1604	* @}
<>	144:ef7eb2e8f9f7	1605	*/
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1608	}
<>	144:ef7eb2e8f9f7	1609	#endif
<>	144:ef7eb2e8f9f7	1610
<>	144:ef7eb2e8f9f7	1611	#endif /* __STM32l0xx_HAL_RCC_H */
<>	144:ef7eb2e8f9f7	1612
<>	144:ef7eb2e8f9f7	1613	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
<>	144:ef7eb2e8f9f7	1614