mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h@144:ef7eb2e8f9f7
Child:
151:5eaa88a5bcc7
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32l0xx_hal_i2c.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 8-January-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of I2C HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32L0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 40 #define __STM32L0xx_HAL_I2C_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32l0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32L0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @defgroup I2C I2C
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 /** @defgroup I2C_Exported_Types I2C Exported Types
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 /** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 63 * @brief I2C Configuration Structure definition
<> 144:ef7eb2e8f9f7 64 * @{
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
<> 144:ef7eb2e8f9f7 69 This parameter calculated by referring to I2C initialization
<> 144:ef7eb2e8f9f7 70 section in Reference manual */
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 uint32_t OwnAddress1; /*!< Specifies the first device own address.
<> 144:ef7eb2e8f9f7 73 This parameter can be a 7-bit or 10-bit address. */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
<> 144:ef7eb2e8f9f7 76 This parameter can be a value of @ref I2C_addressing_mode */
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
<> 144:ef7eb2e8f9f7 79 This parameter can be a value of @ref I2C_dual_addressing_mode */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 82 This parameter can be a 7-bit address. */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
<> 144:ef7eb2e8f9f7 85 This parameter can be a value of @ref I2C_own_address2_masks */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
<> 144:ef7eb2e8f9f7 88 This parameter can be a value of @ref I2C_general_call_addressing_mode */
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
<> 144:ef7eb2e8f9f7 91 This parameter can be a value of @ref I2C_nostretch_mode */
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 }I2C_InitTypeDef;
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /**
<> 144:ef7eb2e8f9f7 96 * @}
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /** @defgroup HAL_state_structure_definition HAL state structure definition
<> 144:ef7eb2e8f9f7 100 * @brief HAL State structure definition
<> 144:ef7eb2e8f9f7 101 * @{
<> 144:ef7eb2e8f9f7 102 */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 typedef enum
<> 144:ef7eb2e8f9f7 105 {
<> 144:ef7eb2e8f9f7 106 HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
<> 144:ef7eb2e8f9f7 107 HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
<> 144:ef7eb2e8f9f7 108 HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
<> 144:ef7eb2e8f9f7 109 HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 110 HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 111 HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 112 HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 113 HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 114 HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 115 HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 116 HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 117 }HAL_I2C_StateTypeDef;
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /**
<> 144:ef7eb2e8f9f7 120 * @}
<> 144:ef7eb2e8f9f7 121 */
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** @defgroup I2C_Error_Code I2C Error Code
<> 144:ef7eb2e8f9f7 124 * @brief I2C Error Code
<> 144:ef7eb2e8f9f7 125 * @{
<> 144:ef7eb2e8f9f7 126 */
<> 144:ef7eb2e8f9f7 127 #define HAL_I2C_ERROR_NONE 0x00 /*!< No error */
<> 144:ef7eb2e8f9f7 128 #define HAL_I2C_ERROR_BERR 0x01 /*!< BERR error */
<> 144:ef7eb2e8f9f7 129 #define HAL_I2C_ERROR_ARLO 0x02 /*!< ARLO error */
<> 144:ef7eb2e8f9f7 130 #define HAL_I2C_ERROR_AF 0x04 /*!< ACKF error */
<> 144:ef7eb2e8f9f7 131 #define HAL_I2C_ERROR_OVR 0x08 /*!< OVR error */
<> 144:ef7eb2e8f9f7 132 #define HAL_I2C_ERROR_DMA 0x10 /*!< DMA transfer error */
<> 144:ef7eb2e8f9f7 133 #define HAL_I2C_ERROR_TIMEOUT 0x20 /*!< Timeout error */
<> 144:ef7eb2e8f9f7 134 #define HAL_I2C_ERROR_SIZE 0x40 /*!< Size Management error */
<> 144:ef7eb2e8f9f7 135 /**
<> 144:ef7eb2e8f9f7 136 * @}
<> 144:ef7eb2e8f9f7 137 */
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 /** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
<> 144:ef7eb2e8f9f7 140 * @brief I2C handle Structure definition
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143 typedef struct
<> 144:ef7eb2e8f9f7 144 {
<> 144:ef7eb2e8f9f7 145 I2C_TypeDef *Instance; /*!< I2C registers base address */
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 I2C_InitTypeDef Init; /*!< I2C communication parameters */
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 uint16_t XferSize; /*!< I2C transfer size */
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 __IO uint16_t XferCount; /*!< I2C transfer counter */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 HAL_LockTypeDef Lock; /*!< I2C locking object */
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 __IO uint32_t ErrorCode; /*!< I2C Error code, see I2C_Error_Code */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 }I2C_HandleTypeDef;
<> 144:ef7eb2e8f9f7 166 /**
<> 144:ef7eb2e8f9f7 167 * @}
<> 144:ef7eb2e8f9f7 168 */
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 /**
<> 144:ef7eb2e8f9f7 171 * @}
<> 144:ef7eb2e8f9f7 172 */
<> 144:ef7eb2e8f9f7 173 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /** @defgroup I2C_Exported_Constants I2C Exported Constants
<> 144:ef7eb2e8f9f7 176 * @{
<> 144:ef7eb2e8f9f7 177 */
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /** @defgroup I2C_addressing_mode I2C addressing mode
<> 144:ef7eb2e8f9f7 180 * @{
<> 144:ef7eb2e8f9f7 181 */
<> 144:ef7eb2e8f9f7 182 #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 183 #define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 184 /**
<> 144:ef7eb2e8f9f7 185 * @}
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
<> 144:ef7eb2e8f9f7 189 * @{
<> 144:ef7eb2e8f9f7 190 */
<> 144:ef7eb2e8f9f7 191 #define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 192 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
<> 144:ef7eb2e8f9f7 193 /**
<> 144:ef7eb2e8f9f7 194 * @}
<> 144:ef7eb2e8f9f7 195 */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /** @defgroup I2C_own_address2_masks I2C own address2 masks
<> 144:ef7eb2e8f9f7 198 * @{
<> 144:ef7eb2e8f9f7 199 */
<> 144:ef7eb2e8f9f7 200 #define I2C_OA2_NOMASK ((uint8_t)0x00)
<> 144:ef7eb2e8f9f7 201 #define I2C_OA2_MASK01 ((uint8_t)0x01)
<> 144:ef7eb2e8f9f7 202 #define I2C_OA2_MASK02 ((uint8_t)0x02)
<> 144:ef7eb2e8f9f7 203 #define I2C_OA2_MASK03 ((uint8_t)0x03)
<> 144:ef7eb2e8f9f7 204 #define I2C_OA2_MASK04 ((uint8_t)0x04)
<> 144:ef7eb2e8f9f7 205 #define I2C_OA2_MASK05 ((uint8_t)0x05)
<> 144:ef7eb2e8f9f7 206 #define I2C_OA2_MASK06 ((uint8_t)0x06)
<> 144:ef7eb2e8f9f7 207 #define I2C_OA2_MASK07 ((uint8_t)0x07)
<> 144:ef7eb2e8f9f7 208 /**
<> 144:ef7eb2e8f9f7 209 * @}
<> 144:ef7eb2e8f9f7 210 */
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
<> 144:ef7eb2e8f9f7 213 * @{
<> 144:ef7eb2e8f9f7 214 */
<> 144:ef7eb2e8f9f7 215 #define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 216 #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @}
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /** @defgroup I2C_nostretch_mode I2C nostretch mode
<> 144:ef7eb2e8f9f7 222 * @{
<> 144:ef7eb2e8f9f7 223 */
<> 144:ef7eb2e8f9f7 224 #define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 225 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @}
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
<> 144:ef7eb2e8f9f7 231 * @{
<> 144:ef7eb2e8f9f7 232 */
<> 144:ef7eb2e8f9f7 233 #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 234 #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 235 /**
<> 144:ef7eb2e8f9f7 236 * @}
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
<> 144:ef7eb2e8f9f7 240 * @{
<> 144:ef7eb2e8f9f7 241 */
<> 144:ef7eb2e8f9f7 242 #define I2C_RELOAD_MODE I2C_CR2_RELOAD
<> 144:ef7eb2e8f9f7 243 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
<> 144:ef7eb2e8f9f7 244 #define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 245 /**
<> 144:ef7eb2e8f9f7 246 * @}
<> 144:ef7eb2e8f9f7 247 */
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249 /** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
<> 144:ef7eb2e8f9f7 250 * @{
<> 144:ef7eb2e8f9f7 251 */
<> 144:ef7eb2e8f9f7 252 #define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 253 #define I2C_GENERATE_STOP I2C_CR2_STOP
<> 144:ef7eb2e8f9f7 254 #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
<> 144:ef7eb2e8f9f7 255 #define I2C_GENERATE_START_WRITE I2C_CR2_START
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @}
<> 144:ef7eb2e8f9f7 258 */
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
<> 144:ef7eb2e8f9f7 261 * @brief I2C Interrupt definition
<> 144:ef7eb2e8f9f7 262 * Elements values convention: 0xXXXXXXXX
<> 144:ef7eb2e8f9f7 263 * - XXXXXXXX : Interrupt control mask
<> 144:ef7eb2e8f9f7 264 * @{
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266 #define I2C_IT_ERRI I2C_CR1_ERRIE
<> 144:ef7eb2e8f9f7 267 #define I2C_IT_TCI I2C_CR1_TCIE
<> 144:ef7eb2e8f9f7 268 #define I2C_IT_STOPI I2C_CR1_STOPIE
<> 144:ef7eb2e8f9f7 269 #define I2C_IT_NACKI I2C_CR1_NACKIE
<> 144:ef7eb2e8f9f7 270 #define I2C_IT_ADDRI I2C_CR1_ADDRIE
<> 144:ef7eb2e8f9f7 271 #define I2C_IT_RXI I2C_CR1_RXIE
<> 144:ef7eb2e8f9f7 272 #define I2C_IT_TXI I2C_CR1_TXIE
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 /**
<> 144:ef7eb2e8f9f7 275 * @}
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /** @defgroup I2C_Flag_definition I2C Flag definition
<> 144:ef7eb2e8f9f7 280 * @{
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 #define I2C_FLAG_TXE I2C_ISR_TXE
<> 144:ef7eb2e8f9f7 283 #define I2C_FLAG_TXIS I2C_ISR_TXIS
<> 144:ef7eb2e8f9f7 284 #define I2C_FLAG_RXNE I2C_ISR_RXNE
<> 144:ef7eb2e8f9f7 285 #define I2C_FLAG_ADDR I2C_ISR_ADDR
<> 144:ef7eb2e8f9f7 286 #define I2C_FLAG_AF I2C_ISR_NACKF
<> 144:ef7eb2e8f9f7 287 #define I2C_FLAG_STOPF I2C_ISR_STOPF
<> 144:ef7eb2e8f9f7 288 #define I2C_FLAG_TC I2C_ISR_TC
<> 144:ef7eb2e8f9f7 289 #define I2C_FLAG_TCR I2C_ISR_TCR
<> 144:ef7eb2e8f9f7 290 #define I2C_FLAG_BERR I2C_ISR_BERR
<> 144:ef7eb2e8f9f7 291 #define I2C_FLAG_ARLO I2C_ISR_ARLO
<> 144:ef7eb2e8f9f7 292 #define I2C_FLAG_OVR I2C_ISR_OVR
<> 144:ef7eb2e8f9f7 293 #define I2C_FLAG_PECERR I2C_ISR_PECERR
<> 144:ef7eb2e8f9f7 294 #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
<> 144:ef7eb2e8f9f7 295 #define I2C_FLAG_ALERT I2C_ISR_ALERT
<> 144:ef7eb2e8f9f7 296 #define I2C_FLAG_BUSY I2C_ISR_BUSY
<> 144:ef7eb2e8f9f7 297 #define I2C_FLAG_DIR I2C_ISR_DIR
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @}
<> 144:ef7eb2e8f9f7 300 */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Exported macros -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 303
<> 144:ef7eb2e8f9f7 304 /** @defgroup I2C_Exported_Macros I2C Exported Macros
<> 144:ef7eb2e8f9f7 305 * @{
<> 144:ef7eb2e8f9f7 306 */
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /** @brief Reset I2C handle state
<> 144:ef7eb2e8f9f7 309 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 310 * @retval None
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /** @brief Enable the specified I2C interrupts.
<> 144:ef7eb2e8f9f7 315 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 316 * @param __INTERRUPT__: specifies the interrupt source to enable.
<> 144:ef7eb2e8f9f7 317 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 318 * @arg I2C_IT_ERRI: Errors interrupt enable
<> 144:ef7eb2e8f9f7 319 * @arg I2C_IT_TCI: Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 320 * @arg I2C_IT_STOPI: STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 321 * @arg I2C_IT_NACKI: NACK received interrupt enable
<> 144:ef7eb2e8f9f7 322 * @arg I2C_IT_ADDRI: Address match interrupt enable
<> 144:ef7eb2e8f9f7 323 * @arg I2C_IT_RXI: RX interrupt enable
<> 144:ef7eb2e8f9f7 324 * @arg I2C_IT_TXI: TX interrupt enable
<> 144:ef7eb2e8f9f7 325 *
<> 144:ef7eb2e8f9f7 326 * @retval None
<> 144:ef7eb2e8f9f7 327 */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /** @brief Disable the specified I2C interrupts.
<> 144:ef7eb2e8f9f7 332 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 333 * @param __INTERRUPT__: specifies the interrupt source to disable.
<> 144:ef7eb2e8f9f7 334 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 335 * @arg I2C_IT_ERRI: Errors interrupt enable
<> 144:ef7eb2e8f9f7 336 * @arg I2C_IT_TCI: Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 337 * @arg I2C_IT_STOPI: STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 338 * @arg I2C_IT_NACKI: NACK received interrupt enable
<> 144:ef7eb2e8f9f7 339 * @arg I2C_IT_ADDRI: Address match interrupt enable
<> 144:ef7eb2e8f9f7 340 * @arg I2C_IT_RXI: RX interrupt enable
<> 144:ef7eb2e8f9f7 341 * @arg I2C_IT_TXI: TX interrupt enable
<> 144:ef7eb2e8f9f7 342 *
<> 144:ef7eb2e8f9f7 343 * @retval None
<> 144:ef7eb2e8f9f7 344 */
<> 144:ef7eb2e8f9f7 345 #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /** @brief Checks if the specified I2C interrupt source is enabled or disabled.
<> 144:ef7eb2e8f9f7 348 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 349 * @param __INTERRUPT__: specifies the I2C interrupt source to check.
<> 144:ef7eb2e8f9f7 350 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 351 * @arg I2C_IT_ERRI: Errors interrupt enable
<> 144:ef7eb2e8f9f7 352 * @arg I2C_IT_TCI: Transfer complete interrupt enable
<> 144:ef7eb2e8f9f7 353 * @arg I2C_IT_STOPI: STOP detection interrupt enable
<> 144:ef7eb2e8f9f7 354 * @arg I2C_IT_NACKI: NACK received interrupt enable
<> 144:ef7eb2e8f9f7 355 * @arg I2C_IT_ADDRI: Address match interrupt enable
<> 144:ef7eb2e8f9f7 356 * @arg I2C_IT_RXI: RX interrupt enable
<> 144:ef7eb2e8f9f7 357 * @arg I2C_IT_TXI: TX interrupt enable
<> 144:ef7eb2e8f9f7 358 *
<> 144:ef7eb2e8f9f7 359 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 360 */
<> 144:ef7eb2e8f9f7 361 #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /** @brief Checks whether the specified I2C flag is set or not.
<> 144:ef7eb2e8f9f7 364 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 365 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 366 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 367 * @arg I2C_FLAG_TXE: Transmit data register empty
<> 144:ef7eb2e8f9f7 368 * @arg I2C_FLAG_TXIS: Transmit interrupt status
<> 144:ef7eb2e8f9f7 369 * @arg I2C_FLAG_RXNE: Receive data register not empty
<> 144:ef7eb2e8f9f7 370 * @arg I2C_FLAG_ADDR: Address matched (slave mode)
<> 144:ef7eb2e8f9f7 371 * @arg I2C_FLAG_AF: Acknowledge failure received flag
<> 144:ef7eb2e8f9f7 372 * @arg I2C_FLAG_STOPF: STOP detection flag
<> 144:ef7eb2e8f9f7 373 * @arg I2C_FLAG_TC: Transfer complete (master mode)
<> 144:ef7eb2e8f9f7 374 * @arg I2C_FLAG_TCR: Transfer complete reload
<> 144:ef7eb2e8f9f7 375 * @arg I2C_FLAG_BERR: Bus error
<> 144:ef7eb2e8f9f7 376 * @arg I2C_FLAG_ARLO: Arbitration lost
<> 144:ef7eb2e8f9f7 377 * @arg I2C_FLAG_OVR: Overrun/Underrun
<> 144:ef7eb2e8f9f7 378 * @arg I2C_FLAG_PECERR: PEC error in reception
<> 144:ef7eb2e8f9f7 379 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 380 * @arg I2C_FLAG_ALERT: SMBus alert
<> 144:ef7eb2e8f9f7 381 * @arg I2C_FLAG_BUSY: Bus busy
<> 144:ef7eb2e8f9f7 382 * @arg I2C_FLAG_DIR: Transfer direction (slave mode)
<> 144:ef7eb2e8f9f7 383 *
<> 144:ef7eb2e8f9f7 384 * @retval The new state of __FLAG__ (TRUE or FALSE).
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 #define I2C_FLAG_MASK ((uint32_t)0x0001FFFF)
<> 144:ef7eb2e8f9f7 387 #define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
<> 144:ef7eb2e8f9f7 388
<> 144:ef7eb2e8f9f7 389 /** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
<> 144:ef7eb2e8f9f7 390 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 391 * @param __FLAG__: specifies the flag to clear.
<> 144:ef7eb2e8f9f7 392 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 393 * @arg I2C_FLAG_ADDR: Address matched (slave mode)
<> 144:ef7eb2e8f9f7 394 * @arg I2C_FLAG_AF: Acknowledge failure received flag
<> 144:ef7eb2e8f9f7 395 * @arg I2C_FLAG_STOPF: STOP detection flag
<> 144:ef7eb2e8f9f7 396 * @arg I2C_FLAG_BERR: Bus error
<> 144:ef7eb2e8f9f7 397 * @arg I2C_FLAG_ARLO: Arbitration lost
<> 144:ef7eb2e8f9f7 398 * @arg I2C_FLAG_OVR: Overrun/Underrun
<> 144:ef7eb2e8f9f7 399 * @arg I2C_FLAG_PECERR: PEC error in reception
<> 144:ef7eb2e8f9f7 400 * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
<> 144:ef7eb2e8f9f7 401 * @arg I2C_FLAG_ALERT: SMBus alert
<> 144:ef7eb2e8f9f7 402 *
<> 144:ef7eb2e8f9f7 403 * @retval None
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 #define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407 /** @brief Enable the specified I2C peripheral.
<> 144:ef7eb2e8f9f7 408 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 409 * @retval None
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 #define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /** @brief Disable the specified I2C peripheral.
<> 144:ef7eb2e8f9f7 414 * @param __HANDLE__: specifies the I2C Handle.
<> 144:ef7eb2e8f9f7 415 * @retval None
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 #define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /**
<> 144:ef7eb2e8f9f7 420 * @}
<> 144:ef7eb2e8f9f7 421 */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /**
<> 144:ef7eb2e8f9f7 424 * @}
<> 144:ef7eb2e8f9f7 425 */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 /* Include I2C HAL Extension module */
<> 144:ef7eb2e8f9f7 428 #include "stm32l0xx_hal_i2c_ex.h"
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 431 /** @addtogroup I2C_Private
<> 144:ef7eb2e8f9f7 432 * @{
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 #define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
<> 144:ef7eb2e8f9f7 436 ((MODE) == I2C_ADDRESSINGMODE_10BIT))
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 #define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
<> 144:ef7eb2e8f9f7 439 ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 #define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
<> 144:ef7eb2e8f9f7 442 ((MASK) == I2C_OA2_MASK01) || \
<> 144:ef7eb2e8f9f7 443 ((MASK) == I2C_OA2_MASK02) || \
<> 144:ef7eb2e8f9f7 444 ((MASK) == I2C_OA2_MASK03) || \
<> 144:ef7eb2e8f9f7 445 ((MASK) == I2C_OA2_MASK04) || \
<> 144:ef7eb2e8f9f7 446 ((MASK) == I2C_OA2_MASK05) || \
<> 144:ef7eb2e8f9f7 447 ((MASK) == I2C_OA2_MASK06) || \
<> 144:ef7eb2e8f9f7 448 ((MASK) == I2C_OA2_MASK07))
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 #define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
<> 144:ef7eb2e8f9f7 451 ((CALL) == I2C_GENERALCALL_ENABLE))
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453 #define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
<> 144:ef7eb2e8f9f7 454 ((STRETCH) == I2C_NOSTRETCH_ENABLE))
<> 144:ef7eb2e8f9f7 455
<> 144:ef7eb2e8f9f7 456 #define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
<> 144:ef7eb2e8f9f7 457 ((SIZE) == I2C_MEMADD_SIZE_16BIT))
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 #define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
<> 144:ef7eb2e8f9f7 461 ((MODE) == I2C_AUTOEND_MODE) || \
<> 144:ef7eb2e8f9f7 462 ((MODE) == I2C_SOFTEND_MODE))
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 #define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
<> 144:ef7eb2e8f9f7 465 ((REQUEST) == I2C_GENERATE_START_READ) || \
<> 144:ef7eb2e8f9f7 466 ((REQUEST) == I2C_GENERATE_START_WRITE) || \
<> 144:ef7eb2e8f9f7 467 ((REQUEST) == I2C_NO_STARTSTOP))
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 #define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 #define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
<> 144:ef7eb2e8f9f7 473 #define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475 #define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
<> 144:ef7eb2e8f9f7 476 #define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 #define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
<> 144:ef7eb2e8f9f7 479 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 487 /** @defgroup I2C_Exported_Functions I2C Exported Functions
<> 144:ef7eb2e8f9f7 488 * @{
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 492 * @{
<> 144:ef7eb2e8f9f7 493 */
<> 144:ef7eb2e8f9f7 494 /* Initialization and de-initialization functions******************************/
<> 144:ef7eb2e8f9f7 495 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 496 HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 497 void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 498 void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 499 /**
<> 144:ef7eb2e8f9f7 500 * @}
<> 144:ef7eb2e8f9f7 501 */
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
<> 144:ef7eb2e8f9f7 504 * @{
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506 /* IO operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 507 /******* Blocking mode: Polling */
<> 144:ef7eb2e8f9f7 508 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 509 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 510 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 511 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 512 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 513 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 514 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 /******* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 517 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 518 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 519 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 520 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 522 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /******* Non-Blocking mode: DMA */
<> 144:ef7eb2e8f9f7 525 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 526 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 527 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 528 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 529 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 530 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
<> 144:ef7eb2e8f9f7 531 /**
<> 144:ef7eb2e8f9f7 532 * @}
<> 144:ef7eb2e8f9f7 533 */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /** @defgroup IRQ_Handler_and_Callbacks RQ Handler and Callbacks
<> 144:ef7eb2e8f9f7 536 * @{
<> 144:ef7eb2e8f9f7 537 */
<> 144:ef7eb2e8f9f7 538 /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
<> 144:ef7eb2e8f9f7 539 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 540 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 541 void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 542 void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 543 void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 544 void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 545 void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 546 void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 547 void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 548 /**
<> 144:ef7eb2e8f9f7 549 * @}
<> 144:ef7eb2e8f9f7 550 */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
<> 144:ef7eb2e8f9f7 553 * @{
<> 144:ef7eb2e8f9f7 554 */
<> 144:ef7eb2e8f9f7 555 /* Peripheral State and Errors functions *************************************/
<> 144:ef7eb2e8f9f7 556 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 557 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 /**
<> 144:ef7eb2e8f9f7 560 * @}
<> 144:ef7eb2e8f9f7 561 */
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 /**
<> 144:ef7eb2e8f9f7 564 * @}
<> 144:ef7eb2e8f9f7 565 */
<> 144:ef7eb2e8f9f7 566
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 /* Define the private group ***********************************/
<> 144:ef7eb2e8f9f7 569 /**************************************************************/
<> 144:ef7eb2e8f9f7 570 /** @defgroup I2C_Private I2C Private
<> 144:ef7eb2e8f9f7 571 * @{
<> 144:ef7eb2e8f9f7 572 */
<> 144:ef7eb2e8f9f7 573 /**
<> 144:ef7eb2e8f9f7 574 * @}
<> 144:ef7eb2e8f9f7 575 */
<> 144:ef7eb2e8f9f7 576 /**************************************************************/
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578 /**
<> 144:ef7eb2e8f9f7 579 * @}
<> 144:ef7eb2e8f9f7 580 */
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 /**
<> 144:ef7eb2e8f9f7 583 * @}
<> 144:ef7eb2e8f9f7 584 */
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 587 }
<> 144:ef7eb2e8f9f7 588 #endif
<> 144:ef7eb2e8f9f7 589
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 #endif /* __STM32L0xx_HAL_I2C_H */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 594