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mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h@144:ef7eb2e8f9f7
Child:: 151:5eaa88a5bcc7

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l0xx_hal_adc.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.0
<>	144:ef7eb2e8f9f7	6	* @date 8-January-2016
<>	144:ef7eb2e8f9f7	7	* @brief This file contains all the functions prototypes for the ADC firmware
<>	144:ef7eb2e8f9f7	8	* library.
<>	144:ef7eb2e8f9f7	9	******************************************************************************
<>	144:ef7eb2e8f9f7	10	* @attention
<>	144:ef7eb2e8f9f7	11	*
<>	144:ef7eb2e8f9f7	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	13	*
<>	144:ef7eb2e8f9f7	14	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	15	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	16	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	17	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	19	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	20	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	22	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	23	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	24	*
<>	144:ef7eb2e8f9f7	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	35	*
<>	144:ef7eb2e8f9f7	36	******************************************************************************
<>	144:ef7eb2e8f9f7	37	*/
<>	144:ef7eb2e8f9f7	38
<>	144:ef7eb2e8f9f7	39	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	40	#ifndef __STM32L0xx_ADC_H
<>	144:ef7eb2e8f9f7	41	#define __STM32L0xx_ADC_H
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	44	extern "C" {
<>	144:ef7eb2e8f9f7	45	#endif
<>	144:ef7eb2e8f9f7	46
<>	144:ef7eb2e8f9f7	47	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	48	#include "stm32l0xx_hal_def.h"
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	/** @addtogroup STM32L0xx_HAL_Driver
<>	144:ef7eb2e8f9f7	51	* @{
<>	144:ef7eb2e8f9f7	52	*/
<>	144:ef7eb2e8f9f7	53
<>	144:ef7eb2e8f9f7	54	/** @defgroup ADC ADC
<>	144:ef7eb2e8f9f7	55	* @{
<>	144:ef7eb2e8f9f7	56	*/
<>	144:ef7eb2e8f9f7	57
<>	144:ef7eb2e8f9f7	58	/** @defgroup ADC_Exported_Types ADC Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	63	/**
<>	144:ef7eb2e8f9f7	64	* @brief HAL ADC state machine: ADC states definition (bitfields)
<>	144:ef7eb2e8f9f7	65	*/
<>	144:ef7eb2e8f9f7	66	/* States of ADC global scope */
<>	144:ef7eb2e8f9f7	67	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /!< ADC not yet initialized or disabled /
<>	144:ef7eb2e8f9f7	68	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /!< ADC peripheral ready for use /
<>	144:ef7eb2e8f9f7	69	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /!< ADC is busy to internal process (initialization, calibration) /
<>	144:ef7eb2e8f9f7	70	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /!< TimeOut occurrence /
<>	144:ef7eb2e8f9f7	71
<>	144:ef7eb2e8f9f7	72	/* States of ADC errors */
<>	144:ef7eb2e8f9f7	73	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /!< Internal error occurrence /
<>	144:ef7eb2e8f9f7	74	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /!< Configuration error occurrence /
<>	144:ef7eb2e8f9f7	75	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /!< DMA error occurrence /
<>	144:ef7eb2e8f9f7	76
<>	144:ef7eb2e8f9f7	77	/* States of ADC group regular */
<>	144:ef7eb2e8f9f7	78	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
<>	144:ef7eb2e8f9f7	79	external trigger, low power auto power-on, multimode ADC master control) */
<>	144:ef7eb2e8f9f7	80	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /!< Conversion data available on group regular /
<>	144:ef7eb2e8f9f7	81	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /!< Overrun occurrence /
<>	144:ef7eb2e8f9f7	82	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /!< Not available on STM32F0 device: End Of Sampling flag raised /
<>	144:ef7eb2e8f9f7	83
<>	144:ef7eb2e8f9f7	84	/* States of ADC group injected */
<>	144:ef7eb2e8f9f7	85	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
<>	144:ef7eb2e8f9f7	86	external trigger, low power auto power-on, multimode ADC master control) */
<>	144:ef7eb2e8f9f7	87	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /!< Not available on STM32F0 device: Conversion data available on group injected /
<>	144:ef7eb2e8f9f7	88	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence /
<>	144:ef7eb2e8f9f7	89
<>	144:ef7eb2e8f9f7	90	/* States of ADC analog watchdogs */
<>	144:ef7eb2e8f9f7	91	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /!< Out-of-window occurrence of analog watchdog 1 /
<>	144:ef7eb2e8f9f7	92	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 /
<>	144:ef7eb2e8f9f7	93	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 /
<>	144:ef7eb2e8f9f7	94
<>	144:ef7eb2e8f9f7	95	/* States of ADC multi-mode */
<>	144:ef7eb2e8f9f7	96	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( /
<>	144:ef7eb2e8f9f7	97
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	/**
<>	144:ef7eb2e8f9f7	100	* @brief ADC Oversampler structure definition
<>	144:ef7eb2e8f9f7	101	*/
<>	144:ef7eb2e8f9f7	102	typedef struct
<>	144:ef7eb2e8f9f7	103	{
<>	144:ef7eb2e8f9f7	104	uint32_t Ratio; /*!< Configures the oversampling ratio.
<>	144:ef7eb2e8f9f7	105	This parameter can be a value of @ref ADC_Oversampling_Ratio */
<>	144:ef7eb2e8f9f7	106	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
<>	144:ef7eb2e8f9f7	107	This parameter can be a value of @ref ADC_Right_Bit_Shift */
<>	144:ef7eb2e8f9f7	108	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
<>	144:ef7eb2e8f9f7	109	This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
<>	144:ef7eb2e8f9f7	110
<>	144:ef7eb2e8f9f7	111	}ADC_OversamplingTypeDef;
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	/**
<>	144:ef7eb2e8f9f7	114	* @brief ADC Init structure definition
<>	144:ef7eb2e8f9f7	115	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
<>	144:ef7eb2e8f9f7	116	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
<>	144:ef7eb2e8f9f7	117	* without error reporting (as it can be the expected behaviour in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
<>	144:ef7eb2e8f9f7	118	*/
<>	144:ef7eb2e8f9f7	119	typedef struct
<>	144:ef7eb2e8f9f7	120	{
<>	144:ef7eb2e8f9f7	121	uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
<>	144:ef7eb2e8f9f7	122	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	123	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	124	ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
<>	144:ef7eb2e8f9f7	125	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	126	uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
<>	144:ef7eb2e8f9f7	127	This parameter can be a value of @ref ADC_ClockPrescaler
<>	144:ef7eb2e8f9f7	128	Note: This parameter can be modified only if ADC is disabled.
<>	144:ef7eb2e8f9f7	129	Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
<>	144:ef7eb2e8f9f7	130	if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
<>	144:ef7eb2e8f9f7	131	must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
<>	144:ef7eb2e8f9f7	132	uint32_t Resolution; /*!< Configures the ADC resolution mode.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref ADC_Resolution
<>	144:ef7eb2e8f9f7	134	Note: This parameter can be modified only if ADC is disabled. */
<>	144:ef7eb2e8f9f7	135	uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
<>	144:ef7eb2e8f9f7	136	This parameter can be a value of @ref ADC_sampling_times
<>	144:ef7eb2e8f9f7	137	Note: This parameter can be modified only if there is no conversion ongoing. */
<>	144:ef7eb2e8f9f7	138	uint32_t ScanConvMode; /*!< The scan sequence direction.
<>	144:ef7eb2e8f9f7	139	If several channels are set: Conversions are performed in sequence mode
<>	144:ef7eb2e8f9f7	140	(ranks defined by each channel number: channel 0 fixed on rank 0,
<>	144:ef7eb2e8f9f7	141	channel 1 fixed on rank1, ...).
<>	144:ef7eb2e8f9f7	142	This parameter can be a value of @ref ADC_Scan_mode
<>	144:ef7eb2e8f9f7	143	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	144	uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
<>	144:ef7eb2e8f9f7	145	This parameter can be a value of @ref ADC_data_align
<>	144:ef7eb2e8f9f7	146	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	147	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
<>	144:ef7eb2e8f9f7	148	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	149	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	150	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
<>	144:ef7eb2e8f9f7	151	in Complete-sequence/Discontinuous-sequence.
<>	144:ef7eb2e8f9f7	152	Discontinuous mode can be enabled only if continuous mode is disabled.
<>	144:ef7eb2e8f9f7	153	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	154	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	155	uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
<>	144:ef7eb2e8f9f7	156	If set to ADC_SOFTWARE_START, external triggers are disabled.
<>	144:ef7eb2e8f9f7	157	This parameter can be a value of @ref ADC_External_trigger_Source
<>	144:ef7eb2e8f9f7	158	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	159	uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
<>	144:ef7eb2e8f9f7	160	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
<>	144:ef7eb2e8f9f7	161	This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
<>	144:ef7eb2e8f9f7	162	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	163	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
<>	144:ef7eb2e8f9f7	164	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
<>	144:ef7eb2e8f9f7	165	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
<>	144:ef7eb2e8f9f7	166	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	167	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	168	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
<>	144:ef7eb2e8f9f7	169	end of single channel conversion or end of channels conversions sequence.
<>	144:ef7eb2e8f9f7	170	This parameter can be a value of @ref ADC_EOCSelection */
<>	144:ef7eb2e8f9f7	171	uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
<>	144:ef7eb2e8f9f7	172	This parameter has an effect on regular channels only, including in DMA mode.
<>	144:ef7eb2e8f9f7	173	This parameter can be a value of @ref ADC_Overrun
<>	144:ef7eb2e8f9f7	174	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	175	uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
<>	144:ef7eb2e8f9f7	176	when the previous conversion (for regular channel) is completed.
<>	144:ef7eb2e8f9f7	177	This avoids risk of overrun for low frequency application.
<>	144:ef7eb2e8f9f7	178	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	179	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	180	uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
<>	144:ef7eb2e8f9f7	181	it is mandatory to first enable the Low Frequency Mode.
<>	144:ef7eb2e8f9f7	182	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	183	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	184	uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
<>	144:ef7eb2e8f9f7	185	wakes-up when a conversion is started (by software or hardware trigger).
<>	144:ef7eb2e8f9f7	186	This parameter can be set to ENABLE or DISABLE.
<>	144:ef7eb2e8f9f7	187	Note: This parameter can be modified only if there is no conversion is ongoing. */
<>	144:ef7eb2e8f9f7	188	}ADC_InitTypeDef;
<>	144:ef7eb2e8f9f7	189
<>	144:ef7eb2e8f9f7	190	/**
<>	144:ef7eb2e8f9f7	191	* @brief ADC handle Structure definition
<>	144:ef7eb2e8f9f7	192	*/
<>	144:ef7eb2e8f9f7	193	typedef struct
<>	144:ef7eb2e8f9f7	194	{
<>	144:ef7eb2e8f9f7	195	ADC_TypeDef Instance; /!< Register base address */
<>	144:ef7eb2e8f9f7	196
<>	144:ef7eb2e8f9f7	197	ADC_InitTypeDef Init; /!< ADC required parameters /
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
<>	144:ef7eb2e8f9f7	200
<>	144:ef7eb2e8f9f7	201	HAL_LockTypeDef Lock; /!< ADC locking object /
<>	144:ef7eb2e8f9f7	202
<>	144:ef7eb2e8f9f7	203	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	__IO uint32_t ErrorCode; /!< ADC Error code /
<>	144:ef7eb2e8f9f7	206	}ADC_HandleTypeDef;
<>	144:ef7eb2e8f9f7	207
<>	144:ef7eb2e8f9f7	208	/**
<>	144:ef7eb2e8f9f7	209	* @brief ADC Configuration regular Channel structure definition
<>	144:ef7eb2e8f9f7	210	*/
<>	144:ef7eb2e8f9f7	211	typedef struct
<>	144:ef7eb2e8f9f7	212	{
<>	144:ef7eb2e8f9f7	213	uint32_t Channel; /*!< the ADC channel to configure
<>	144:ef7eb2e8f9f7	214	This parameter can be a value of @ref ADC_channels */
<>	144:ef7eb2e8f9f7	215
<>	144:ef7eb2e8f9f7	216	uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
<>	144:ef7eb2e8f9f7	217	On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
<>	144:ef7eb2e8f9f7	218	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
<>	144:ef7eb2e8f9f7	219	Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
<>	144:ef7eb2e8f9f7	220	This parameter can be a value of @ref ADC_rank */
<>	144:ef7eb2e8f9f7	221	}ADC_ChannelConfTypeDef;
<>	144:ef7eb2e8f9f7	222
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/**
<>	144:ef7eb2e8f9f7	225	* @brief ADC Configuration analog watchdog definition
<>	144:ef7eb2e8f9f7	226	*/
<>	144:ef7eb2e8f9f7	227	typedef struct
<>	144:ef7eb2e8f9f7	228	{
<>	144:ef7eb2e8f9f7	229	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
<>	144:ef7eb2e8f9f7	230	This parameter can be a value of @ref ADC_analog_watchdog_mode */
<>	144:ef7eb2e8f9f7	231	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
<>	144:ef7eb2e8f9f7	232	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
<>	144:ef7eb2e8f9f7	233	This parameter can be a value of @ref ADC_channels */
<>	144:ef7eb2e8f9f7	234	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
<>	144:ef7eb2e8f9f7	235	This parameter can be set to ENABLE or DISABLE */
<>	144:ef7eb2e8f9f7	236	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	237	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<>	144:ef7eb2e8f9f7	238	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<>	144:ef7eb2e8f9f7	239	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
<>	144:ef7eb2e8f9f7	240	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
<>	144:ef7eb2e8f9f7	241	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
<>	144:ef7eb2e8f9f7	242	}ADC_AnalogWDGConfTypeDef;
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	/**
<>	144:ef7eb2e8f9f7	245	* @}
<>	144:ef7eb2e8f9f7	246	*/
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/** @defgroup ADC_Exported_Constants ADC Exported Constants
<>	144:ef7eb2e8f9f7	252	* @{
<>	144:ef7eb2e8f9f7	253	*/
<>	144:ef7eb2e8f9f7	254
<>	144:ef7eb2e8f9f7	255	/** @defgroup ADC_Error_Code ADC Error Code
<>	144:ef7eb2e8f9f7	256	* @{
<>	144:ef7eb2e8f9f7	257	*/
<>	144:ef7eb2e8f9f7	258	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /!< No error /
<>	144:ef7eb2e8f9f7	259	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
<>	144:ef7eb2e8f9f7	260	enable/disable, erroneous state */
<>	144:ef7eb2e8f9f7	261	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /!< OVR error /
<>	144:ef7eb2e8f9f7	262	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	263	/**
<>	144:ef7eb2e8f9f7	264	* @}
<>	144:ef7eb2e8f9f7	265	*/
<>	144:ef7eb2e8f9f7	266
<>	144:ef7eb2e8f9f7	267	/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
<>	144:ef7eb2e8f9f7	268	* @{
<>	144:ef7eb2e8f9f7	269	*/
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	/* Fixed timeout values for ADC calibration, enable settling time, disable */
<>	144:ef7eb2e8f9f7	272	/* settling time. */
<>	144:ef7eb2e8f9f7	273	/* Values defined to be higher than worst cases: low clocks freq, */
<>	144:ef7eb2e8f9f7	274	/* maximum prescalers. */
<>	144:ef7eb2e8f9f7	275	/* Unit: ms */
<>	144:ef7eb2e8f9f7	276	#define ADC_ENABLE_TIMEOUT 10
<>	144:ef7eb2e8f9f7	277	#define ADC_DISABLE_TIMEOUT 10
<>	144:ef7eb2e8f9f7	278	#define ADC_STOP_CONVERSION_TIMEOUT 10
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
<>	144:ef7eb2e8f9f7	281	/* the minimum number of CPU cycles to fulfill this delay */
<>	144:ef7eb2e8f9f7	282	#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800
<>	144:ef7eb2e8f9f7	283	/**
<>	144:ef7eb2e8f9f7	284	* @}
<>	144:ef7eb2e8f9f7	285	*/
<>	144:ef7eb2e8f9f7	286
<>	144:ef7eb2e8f9f7	287	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
<>	144:ef7eb2e8f9f7	288	* @{
<>	144:ef7eb2e8f9f7	289	*/
<>	144:ef7eb2e8f9f7	290	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000) /!< ADC Asynchronous clock mode divided by 1 /
<>	144:ef7eb2e8f9f7	291	#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	292	#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	293	#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	294	#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	295	#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	296	#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	297	#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	298	#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	299	#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	300	#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	301	#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
<>	144:ef7eb2e8f9f7	304	This configuration must be enabled only if PCLK has a 50%
<>	144:ef7eb2e8f9f7	305	duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
<>	144:ef7eb2e8f9f7	306	must by 50% duty cycle)*/
<>	144:ef7eb2e8f9f7	307	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /!< Synchronous clock mode divided by 2 /
<>	144:ef7eb2e8f9f7	308	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /!< Synchronous clock mode divided by 4 /
<>	144:ef7eb2e8f9f7	309
<>	144:ef7eb2e8f9f7	310	/**
<>	144:ef7eb2e8f9f7	311	* @}
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/** @defgroup ADC_Resolution ADC Resolution
<>	144:ef7eb2e8f9f7	315	* @{
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /!< ADC 12-bit resolution /
<>	144:ef7eb2e8f9f7	318	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /!< ADC 10-bit resolution /
<>	144:ef7eb2e8f9f7	319	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /!< ADC 8-bit resolution /
<>	144:ef7eb2e8f9f7	320	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /!< ADC 6-bit resolution /
<>	144:ef7eb2e8f9f7	321	/**
<>	144:ef7eb2e8f9f7	322	* @}
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324
<>	144:ef7eb2e8f9f7	325	/** @defgroup ADC_data_align ADC Data Align
<>	144:ef7eb2e8f9f7	326	* @{
<>	144:ef7eb2e8f9f7	327	*/
<>	144:ef7eb2e8f9f7	328	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	329	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
<>	144:ef7eb2e8f9f7	330
<>	144:ef7eb2e8f9f7	331	/**
<>	144:ef7eb2e8f9f7	332	* @}
<>	144:ef7eb2e8f9f7	333	*/
<>	144:ef7eb2e8f9f7	334
<>	144:ef7eb2e8f9f7	335	/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
<>	144:ef7eb2e8f9f7	336	* @{
<>	144:ef7eb2e8f9f7	337	*/
<>	144:ef7eb2e8f9f7	338	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	339	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
<>	144:ef7eb2e8f9f7	340	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
<>	144:ef7eb2e8f9f7	341	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
<>	144:ef7eb2e8f9f7	342	/**
<>	144:ef7eb2e8f9f7	343	* @}
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345
<>	144:ef7eb2e8f9f7	346	/** @defgroup ADC_EOCSelection ADC EOC Selection
<>	144:ef7eb2e8f9f7	347	* @{
<>	144:ef7eb2e8f9f7	348	*/
<>	144:ef7eb2e8f9f7	349	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
<>	144:ef7eb2e8f9f7	350	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
<>	144:ef7eb2e8f9f7	351	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
<>	144:ef7eb2e8f9f7	352	/**
<>	144:ef7eb2e8f9f7	353	* @}
<>	144:ef7eb2e8f9f7	354	*/
<>	144:ef7eb2e8f9f7	355
<>	144:ef7eb2e8f9f7	356	/** @defgroup ADC_Overrun ADC Overrun
<>	144:ef7eb2e8f9f7	357	* @{
<>	144:ef7eb2e8f9f7	358	*/
<>	144:ef7eb2e8f9f7	359	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000)
<>	144:ef7eb2e8f9f7	360	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
<>	144:ef7eb2e8f9f7	361	/**
<>	144:ef7eb2e8f9f7	362	* @}
<>	144:ef7eb2e8f9f7	363	*/
<>	144:ef7eb2e8f9f7	364
<>	144:ef7eb2e8f9f7	365
<>	144:ef7eb2e8f9f7	366	/** @defgroup ADC_rank ADC rank
<>	144:ef7eb2e8f9f7	367	* @{
<>	144:ef7eb2e8f9f7	368	*/
<>	144:ef7eb2e8f9f7	369	#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000) /!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) /
<>	144:ef7eb2e8f9f7	370	#define ADC_RANK_NONE ((uint32_t)0x00001001) /!< Disable the selected rank (selected channel) from sequencer /
<>	144:ef7eb2e8f9f7	371	/**
<>	144:ef7eb2e8f9f7	372	* @}
<>	144:ef7eb2e8f9f7	373	*/
<>	144:ef7eb2e8f9f7	374
<>	144:ef7eb2e8f9f7	375
<>	144:ef7eb2e8f9f7	376	/** @defgroup ADC_channels ADC_Channels
<>	144:ef7eb2e8f9f7	377	* @{
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379	#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
<>	144:ef7eb2e8f9f7	380	#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	381	#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) \| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	382	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	383	#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)\| ADC_CFGR1_AWDCH_2)
<>	144:ef7eb2e8f9f7	384	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	385	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	386	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	387	#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)\| ADC_CFGR1_AWDCH_3)
<>	144:ef7eb2e8f9f7	388	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	389	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	390	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	391	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2)
<>	144:ef7eb2e8f9f7	392	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	393	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	394	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	395	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	396	#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)\| ADC_CFGR1_AWDCH_4)
<>	144:ef7eb2e8f9f7	397	#endif
<>	144:ef7eb2e8f9f7	398	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_0)
<>	144:ef7eb2e8f9f7	399	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_1)
<>	144:ef7eb2e8f9f7	400
<>	144:ef7eb2e8f9f7	401	/* Internal channels */
<>	144:ef7eb2e8f9f7	402	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	403	#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
<>	144:ef7eb2e8f9f7	404	#endif
<>	144:ef7eb2e8f9f7	405	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
<>	144:ef7eb2e8f9f7	406	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
<>	144:ef7eb2e8f9f7	407	/**
<>	144:ef7eb2e8f9f7	408	* @}
<>	144:ef7eb2e8f9f7	409	*/
<>	144:ef7eb2e8f9f7	410
<>	144:ef7eb2e8f9f7	411	/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
<>	144:ef7eb2e8f9f7	412	* @{
<>	144:ef7eb2e8f9f7	413	*/
<>	144:ef7eb2e8f9f7	414	#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFF)
<>	144:ef7eb2e8f9f7	415	#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000)
<>	144:ef7eb2e8f9f7	416	/**
<>	144:ef7eb2e8f9f7	417	* @}
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	/** @defgroup ADC_sampling_times ADC Sampling Cycles
<>	144:ef7eb2e8f9f7	422	* @{
<>	144:ef7eb2e8f9f7	423	*/
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000) /!< ADC sampling time 1.5 cycle /
<>	144:ef7eb2e8f9f7	426	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /!< ADC sampling time 7.5 CYCLES /
<>	144:ef7eb2e8f9f7	427	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /!< ADC sampling time 13.5 CYCLES /
<>	144:ef7eb2e8f9f7	428	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 28.5 CYCLES /
<>	144:ef7eb2e8f9f7	429	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /!< ADC sampling time 41.5 CYCLES /
<>	144:ef7eb2e8f9f7	430	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 55.5 CYCLES /
<>	144:ef7eb2e8f9f7	431	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_1)) /!< ADC sampling time 71.5 CYCLES /
<>	144:ef7eb2e8f9f7	432	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /!< ADC sampling time 239.5 CYCLES /
<>	144:ef7eb2e8f9f7	433	/**
<>	144:ef7eb2e8f9f7	434	* @}
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437
<>	144:ef7eb2e8f9f7	438	/** @defgroup ADC_Scan_mode ADC Scan mode
<>	144:ef7eb2e8f9f7	439	* @{
<>	144:ef7eb2e8f9f7	440	*/
<>	144:ef7eb2e8f9f7	441	/* Note: Scan mode values must be compatible with other STM32 devices having */
<>	144:ef7eb2e8f9f7	442	/* a configurable sequencer. */
<>	144:ef7eb2e8f9f7	443	/* Scan direction setting values are defined by taking in account */
<>	144:ef7eb2e8f9f7	444	/* already defined values for other STM32 devices: */
<>	144:ef7eb2e8f9f7	445	/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
<>	144:ef7eb2e8f9f7	446	/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
<>	144:ef7eb2e8f9f7	447	/* Scan direction forward is considered as default setting equivalent */
<>	144:ef7eb2e8f9f7	448	/* to scan enable. */
<>	144:ef7eb2e8f9f7	449	/* Scan direction backward is considered as additional setting. */
<>	144:ef7eb2e8f9f7	450	/* In case of migration from another STM32 device, the user will be */
<>	144:ef7eb2e8f9f7	451	/* warned of change of setting choices with assert check. */
<>	144:ef7eb2e8f9f7	452	#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /!< Scan direction forward: from channel 0 to channel 18 /
<>	144:ef7eb2e8f9f7	453	#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /!< Scan direction backward: from channel 18 to channel 0 /
<>	144:ef7eb2e8f9f7	454
<>	144:ef7eb2e8f9f7	455	#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
<>	144:ef7eb2e8f9f7	456	/**
<>	144:ef7eb2e8f9f7	457	* @}
<>	144:ef7eb2e8f9f7	458	*/
<>	144:ef7eb2e8f9f7	459
<>	144:ef7eb2e8f9f7	460	/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
<>	144:ef7eb2e8f9f7	461	* @{
<>	144:ef7eb2e8f9f7	462	*/
<>	144:ef7eb2e8f9f7	463
<>	144:ef7eb2e8f9f7	464	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /!< ADC Oversampling ratio 2x /
<>	144:ef7eb2e8f9f7	465	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004) /!< ADC Oversampling ratio 4x /
<>	144:ef7eb2e8f9f7	466	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008) /!< ADC Oversampling ratio 8x /
<>	144:ef7eb2e8f9f7	467	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000C) /!< ADC Oversampling ratio 16x /
<>	144:ef7eb2e8f9f7	468	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010) /!< ADC Oversampling ratio 32x /
<>	144:ef7eb2e8f9f7	469	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014) /!< ADC Oversampling ratio 64x /
<>	144:ef7eb2e8f9f7	470	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018) /!< ADC Oversampling ratio 128x /
<>	144:ef7eb2e8f9f7	471	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001C) /!< ADC Oversampling ratio 256x /
<>	144:ef7eb2e8f9f7	472	/**
<>	144:ef7eb2e8f9f7	473	* @}
<>	144:ef7eb2e8f9f7	474	*/
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
<>	144:ef7eb2e8f9f7	477	* @{
<>	144:ef7eb2e8f9f7	478	*/
<>	144:ef7eb2e8f9f7	479	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
<>	144:ef7eb2e8f9f7	480	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020) /!< ADC 1 bit shift for oversampling /
<>	144:ef7eb2e8f9f7	481	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040) /!< ADC 2 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	482	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060) /!< ADC 3 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	483	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080) /!< ADC 4 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	484	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0) /!< ADC 5 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	485	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0) /!< ADC 6 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	486	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0) /!< ADC 7 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	487	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100) /!< ADC 8 bits shift for oversampling /
<>	144:ef7eb2e8f9f7	488	/**
<>	144:ef7eb2e8f9f7	489	* @}
<>	144:ef7eb2e8f9f7	490	*/
<>	144:ef7eb2e8f9f7	491
<>	144:ef7eb2e8f9f7	492	/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
<>	144:ef7eb2e8f9f7	493	* @{
<>	144:ef7eb2e8f9f7	494	*/
<>	144:ef7eb2e8f9f7	495	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000) /!< ADC No bit shift for oversampling /
<>	144:ef7eb2e8f9f7	496	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200) /!< ADC No bit shift for oversampling /
<>	144:ef7eb2e8f9f7	497	/**
<>	144:ef7eb2e8f9f7	498	* @}
<>	144:ef7eb2e8f9f7	499	*/
<>	144:ef7eb2e8f9f7	500
<>	144:ef7eb2e8f9f7	501	/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
<>	144:ef7eb2e8f9f7	502	* @{
<>	144:ef7eb2e8f9f7	503	*/
<>	144:ef7eb2e8f9f7	504	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000)
<>	144:ef7eb2e8f9f7	505	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN))
<>	144:ef7eb2e8f9f7	506	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @}
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510
<>	144:ef7eb2e8f9f7	511	/** @defgroup ADC_conversion_type ADC Conversion Group
<>	144:ef7eb2e8f9f7	512	* @{
<>	144:ef7eb2e8f9f7	513	*/
<>	144:ef7eb2e8f9f7	514	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
<>	144:ef7eb2e8f9f7	515	/**
<>	144:ef7eb2e8f9f7	516	* @}
<>	144:ef7eb2e8f9f7	517	*/
<>	144:ef7eb2e8f9f7	518
<>	144:ef7eb2e8f9f7	519	/** @defgroup ADC_Event_type ADC Event
<>	144:ef7eb2e8f9f7	520	* @{
<>	144:ef7eb2e8f9f7	521	*/
<>	144:ef7eb2e8f9f7	522	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
<>	144:ef7eb2e8f9f7	523	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
<>	144:ef7eb2e8f9f7	524	/**
<>	144:ef7eb2e8f9f7	525	* @}
<>	144:ef7eb2e8f9f7	526	*/
<>	144:ef7eb2e8f9f7	527
<>	144:ef7eb2e8f9f7	528	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
<>	144:ef7eb2e8f9f7	529	* @{
<>	144:ef7eb2e8f9f7	530	*/
<>	144:ef7eb2e8f9f7	531	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready (ADRDY) interrupt source /
<>	144:ef7eb2e8f9f7	532	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of Sampling interrupt source /
<>	144:ef7eb2e8f9f7	533	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of Regular Conversion interrupt source /
<>	144:ef7eb2e8f9f7	534	#define ADC_IT_EOS ADC_IER_EOSEQIE /!< ADC End of Regular sequence of Conversions interrupt source /
<>	144:ef7eb2e8f9f7	535	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
<>	144:ef7eb2e8f9f7	536	#define ADC_IT_AWD ADC_IER_AWDIE /!< ADC Analog watchdog 1 interrupt source /
<>	144:ef7eb2e8f9f7	537	#define ADC_IT_EOCAL ADC_IER_EOCALIE /!< ADC End of Calibration interrupt source /
<>	144:ef7eb2e8f9f7	538	/**
<>	144:ef7eb2e8f9f7	539	* @}
<>	144:ef7eb2e8f9f7	540	*/
<>	144:ef7eb2e8f9f7	541
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543
<>	144:ef7eb2e8f9f7	544	/** @defgroup ADC_flags_definition ADC Flags Definition
<>	144:ef7eb2e8f9f7	545	* @{
<>	144:ef7eb2e8f9f7	546	*/
<>	144:ef7eb2e8f9f7	547	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready (ADRDY) flag /
<>	144:ef7eb2e8f9f7	548	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
<>	144:ef7eb2e8f9f7	549	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
<>	144:ef7eb2e8f9f7	550	#define ADC_FLAG_EOS ADC_ISR_EOSEQ /!< ADC End of Regular sequence of Conversions flag /
<>	144:ef7eb2e8f9f7	551	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
<>	144:ef7eb2e8f9f7	552	#define ADC_FLAG_AWD ADC_ISR_AWD /!< ADC Analog watchdog flag /
<>	144:ef7eb2e8f9f7	553	#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /!< ADC Enf Of Calibration flag /
<>	144:ef7eb2e8f9f7	554
<>	144:ef7eb2e8f9f7	555
<>	144:ef7eb2e8f9f7	556	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
<>	144:ef7eb2e8f9f7	557	ADC_FLAG_OVR \| ADC_FLAG_AWD \| ADC_FLAG_EOCAL)
<>	144:ef7eb2e8f9f7	558	/**
<>	144:ef7eb2e8f9f7	559	* @}
<>	144:ef7eb2e8f9f7	560	*/
<>	144:ef7eb2e8f9f7	561
<>	144:ef7eb2e8f9f7	562	/**
<>	144:ef7eb2e8f9f7	563	* @}
<>	144:ef7eb2e8f9f7	564	*/
<>	144:ef7eb2e8f9f7	565	/* Exported macro ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/** @defgroup ADC_Exported_Macro ADC Exported Macro
<>	144:ef7eb2e8f9f7	568	* @{
<>	144:ef7eb2e8f9f7	569	*/
<>	144:ef7eb2e8f9f7	570	/** @brief Reset ADC handle state
<>	144:ef7eb2e8f9f7	571	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	572	* @retval None
<>	144:ef7eb2e8f9f7	573	*/
<>	144:ef7eb2e8f9f7	574	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
<>	144:ef7eb2e8f9f7	575
<>	144:ef7eb2e8f9f7	576	/**
<>	144:ef7eb2e8f9f7	577	* @brief Enable the ADC peripheral
<>	144:ef7eb2e8f9f7	578	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	579	* @retval None
<>	144:ef7eb2e8f9f7	580	*/
<>	144:ef7eb2e8f9f7	581	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
<>	144:ef7eb2e8f9f7	582
<>	144:ef7eb2e8f9f7	583	/**
<>	144:ef7eb2e8f9f7	584	* @brief Verification of hardware constraints before ADC can be enabled
<>	144:ef7eb2e8f9f7	585	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	586	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
<>	144:ef7eb2e8f9f7	587	*/
<>	144:ef7eb2e8f9f7	588	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	589	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	590	(ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| \
<>	144:ef7eb2e8f9f7	591	ADC_CR_ADDIS \| ADC_CR_ADEN ) \
<>	144:ef7eb2e8f9f7	592	) == RESET \
<>	144:ef7eb2e8f9f7	593	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	594
<>	144:ef7eb2e8f9f7	595	/**
<>	144:ef7eb2e8f9f7	596	* @brief Disable the ADC peripheral
<>	144:ef7eb2e8f9f7	597	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	598	* @retval None
<>	144:ef7eb2e8f9f7	599	*/
<>	144:ef7eb2e8f9f7	600	#define __HAL_ADC_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	601	do{ \
<>	144:ef7eb2e8f9f7	602	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
<>	144:ef7eb2e8f9f7	603	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
<>	144:ef7eb2e8f9f7	604	} while(0)
<>	144:ef7eb2e8f9f7	605
<>	144:ef7eb2e8f9f7	606	/**
<>	144:ef7eb2e8f9f7	607	* @brief Verification of hardware constraints before ADC can be disabled
<>	144:ef7eb2e8f9f7	608	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	609	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
<>	144:ef7eb2e8f9f7	610	*/
<>	144:ef7eb2e8f9f7	611	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
<>	144:ef7eb2e8f9f7	612	(( ( ((__HANDLE__)->Instance->CR) & \
<>	144:ef7eb2e8f9f7	613	(ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
<>	144:ef7eb2e8f9f7	614	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	615
<>	144:ef7eb2e8f9f7	616	/**
<>	144:ef7eb2e8f9f7	617	* @brief Verification of ADC state: enabled or disabled
<>	144:ef7eb2e8f9f7	618	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	619	* @retval SET (ADC enabled) or RESET (ADC disabled)
<>	144:ef7eb2e8f9f7	620	*/
<>	144:ef7eb2e8f9f7	621	#define ADC_IS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	622	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
<>	144:ef7eb2e8f9f7	623	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
<>	144:ef7eb2e8f9f7	624	) ? SET : RESET)
<>	144:ef7eb2e8f9f7	625
<>	144:ef7eb2e8f9f7	626	/**
<>	144:ef7eb2e8f9f7	627	* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
<>	144:ef7eb2e8f9f7	628	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	629	* @retval None
<>	144:ef7eb2e8f9f7	630	*/
<>	144:ef7eb2e8f9f7	631	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
<>	144:ef7eb2e8f9f7	632	/**
<>	144:ef7eb2e8f9f7	633	* @brief Test if conversion trigger of regular group is software start
<>	144:ef7eb2e8f9f7	634	* or external trigger.
<>	144:ef7eb2e8f9f7	635	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	636	* @retval SET (software start) or RESET (external trigger)
<>	144:ef7eb2e8f9f7	637	*/
<>	144:ef7eb2e8f9f7	638	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	639	(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
<>	144:ef7eb2e8f9f7	640
<>	144:ef7eb2e8f9f7	641
<>	144:ef7eb2e8f9f7	642
<>	144:ef7eb2e8f9f7	643	/**
<>	144:ef7eb2e8f9f7	644	* @brief Check if no conversion on going on regular group
<>	144:ef7eb2e8f9f7	645	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	646	* @retval SET (conversion is on going) or RESET (no conversion is on going)
<>	144:ef7eb2e8f9f7	647	*/
<>	144:ef7eb2e8f9f7	648	#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
<>	144:ef7eb2e8f9f7	649	(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
<>	144:ef7eb2e8f9f7	650	) ? RESET : SET)
<>	144:ef7eb2e8f9f7	651
<>	144:ef7eb2e8f9f7	652	/**
<>	144:ef7eb2e8f9f7	653	* @brief Enable ADC continuous conversion mode.
<>	144:ef7eb2e8f9f7	654	* @param _CONTINUOUS_MODE_: Continuous mode.
<>	144:ef7eb2e8f9f7	655	* @retval None
<>	144:ef7eb2e8f9f7	656	*/
<>	144:ef7eb2e8f9f7	657	#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13)
<>	144:ef7eb2e8f9f7	658
<>	144:ef7eb2e8f9f7	659	/**
<>	144:ef7eb2e8f9f7	660	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
<>	144:ef7eb2e8f9f7	661	* @param _SCAN_MODE_: Scan conversion mode.
<>	144:ef7eb2e8f9f7	662	* @retval None
<>	144:ef7eb2e8f9f7	663	*/
<>	144:ef7eb2e8f9f7	664	#define ADC_SCANDIR(_SCAN_MODE_) \
<>	144:ef7eb2e8f9f7	665	( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
<>	144:ef7eb2e8f9f7	666	)? (ADC_CFGR1_SCANDIR) : (0x00000000) \
<>	144:ef7eb2e8f9f7	667	)
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	/**
<>	144:ef7eb2e8f9f7	670	* @brief Configures the number of discontinuous conversions for the regular group channels.
<>	144:ef7eb2e8f9f7	671	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
<>	144:ef7eb2e8f9f7	672	* @retval None
<>	144:ef7eb2e8f9f7	673	*/
<>	144:ef7eb2e8f9f7	674	#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << 17)
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	/**
<>	144:ef7eb2e8f9f7	677	* @brief Enable the ADC DMA continuous request.
<>	144:ef7eb2e8f9f7	678	* @param _DMAContReq_MODE_: DMA continuous request mode.
<>	144:ef7eb2e8f9f7	679	* @retval None
<>	144:ef7eb2e8f9f7	680	*/
<>	144:ef7eb2e8f9f7	681	#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1)
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	/**
<>	144:ef7eb2e8f9f7	684	* @brief Enable the ADC Auto Delay.
<>	144:ef7eb2e8f9f7	685	* @param _AutoDelay_: Auto delay bit enable or disable.
<>	144:ef7eb2e8f9f7	686	* @retval None
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688	#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14)
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/**
<>	144:ef7eb2e8f9f7	691	* @brief Enable the ADC LowPowerAutoPowerOff.
<>	144:ef7eb2e8f9f7	692	* @param _AUTOFF_: AutoOff bit enable or disable.
<>	144:ef7eb2e8f9f7	693	* @retval None
<>	144:ef7eb2e8f9f7	694	*/
<>	144:ef7eb2e8f9f7	695	#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15)
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	/**
<>	144:ef7eb2e8f9f7	698	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
<>	144:ef7eb2e8f9f7	699	* @param _Threshold_: Threshold value
<>	144:ef7eb2e8f9f7	700	* @retval None
<>	144:ef7eb2e8f9f7	701	*/
<>	144:ef7eb2e8f9f7	702	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16)
<>	144:ef7eb2e8f9f7	703
<>	144:ef7eb2e8f9f7	704	/**
<>	144:ef7eb2e8f9f7	705	* @brief Enable the ADC Low Frequency mode.
<>	144:ef7eb2e8f9f7	706	* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
<>	144:ef7eb2e8f9f7	707	* @retval None
<>	144:ef7eb2e8f9f7	708	*/
<>	144:ef7eb2e8f9f7	709	#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25)
<>	144:ef7eb2e8f9f7	710
<>	144:ef7eb2e8f9f7	711	/**
<>	144:ef7eb2e8f9f7	712	* @brief Shift the offset in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	713	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
<>	144:ef7eb2e8f9f7	714	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	715	* If resolution 10 bits, shift of 2 ranks on the right.
<>	144:ef7eb2e8f9f7	716	* If resolution 8 bits, shift of 4 ranks on the right.
<>	144:ef7eb2e8f9f7	717	* If resolution 6 bits, shift of 6 ranks on the right.
<>	144:ef7eb2e8f9f7	718	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	719	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	720	* @param _Offset_: Value to be shifted
<>	144:ef7eb2e8f9f7	721	* @retval None
<>	144:ef7eb2e8f9f7	722	*/
<>	144:ef7eb2e8f9f7	723	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
<>	144:ef7eb2e8f9f7	724	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	/**
<>	144:ef7eb2e8f9f7	727	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
<>	144:ef7eb2e8f9f7	728	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
<>	144:ef7eb2e8f9f7	729	* If resolution 12 bits, no shift.
<>	144:ef7eb2e8f9f7	730	* If resolution 10 bits, shift of 2 ranks on the right.
<>	144:ef7eb2e8f9f7	731	* If resolution 8 bits, shift of 4 ranks on the right.
<>	144:ef7eb2e8f9f7	732	* If resolution 6 bits, shift of 6 ranks on the right.
<>	144:ef7eb2e8f9f7	733	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
<>	144:ef7eb2e8f9f7	734	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	735	* @param _Threshold_: Value to be shifted
<>	144:ef7eb2e8f9f7	736	* @retval None
<>	144:ef7eb2e8f9f7	737	*/
<>	144:ef7eb2e8f9f7	738	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
<>	144:ef7eb2e8f9f7	739	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2))
<>	144:ef7eb2e8f9f7	740
<>	144:ef7eb2e8f9f7	741	/**
<>	144:ef7eb2e8f9f7	742	* @brief Shift the value on the left, less significant are set to 0.
<>	144:ef7eb2e8f9f7	743	* @param _Value_: Value to be shifted
<>	144:ef7eb2e8f9f7	744	* @param _Shift_: Number of shift to be done
<>	144:ef7eb2e8f9f7	745	* @retval None
<>	144:ef7eb2e8f9f7	746	*/
<>	144:ef7eb2e8f9f7	747	#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749
<>	144:ef7eb2e8f9f7	750	/**
<>	144:ef7eb2e8f9f7	751	* @brief Enable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	752	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	753	* @param __INTERRUPT__: ADC Interrupt.
<>	144:ef7eb2e8f9f7	754	* @retval None
<>	144:ef7eb2e8f9f7	755	*/
<>	144:ef7eb2e8f9f7	756	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	757	(((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	/**
<>	144:ef7eb2e8f9f7	760	* @brief Disable the ADC end of conversion interrupt.
<>	144:ef7eb2e8f9f7	761	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	762	* @param __INTERRUPT__: ADC interrupt.
<>	144:ef7eb2e8f9f7	763	* @retval None
<>	144:ef7eb2e8f9f7	764	*/
<>	144:ef7eb2e8f9f7	765	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	766	(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
<>	144:ef7eb2e8f9f7	767
<>	144:ef7eb2e8f9f7	768	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
<>	144:ef7eb2e8f9f7	769	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	770	* @param __INTERRUPT__: ADC interrupt source to check
<>	144:ef7eb2e8f9f7	771	* @arg ...
<>	144:ef7eb2e8f9f7	772	* @arg ...
<>	144:ef7eb2e8f9f7	773	* @retval State of interruption (TRUE or FALSE)
<>	144:ef7eb2e8f9f7	774	*/
<>	144:ef7eb2e8f9f7	775	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
<>	144:ef7eb2e8f9f7	776	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
<>	144:ef7eb2e8f9f7	777
<>	144:ef7eb2e8f9f7	778	/**
<>	144:ef7eb2e8f9f7	779	* @brief Clear the ADC's pending flags
<>	144:ef7eb2e8f9f7	780	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	781	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	782	* @retval None
<>	144:ef7eb2e8f9f7	783	*/
<>	144:ef7eb2e8f9f7	784	/* Note: bit cleared bit by writing 1 */
<>	144:ef7eb2e8f9f7	785	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	786	(((__HANDLE__)->Instance->ISR) = (__FLAG__))
<>	144:ef7eb2e8f9f7	787
<>	144:ef7eb2e8f9f7	788	/**
<>	144:ef7eb2e8f9f7	789	* @brief Get the selected ADC's flag status.
<>	144:ef7eb2e8f9f7	790	* @param __HANDLE__: ADC handle.
<>	144:ef7eb2e8f9f7	791	* @param __FLAG__: ADC flag.
<>	144:ef7eb2e8f9f7	792	* @retval None
<>	144:ef7eb2e8f9f7	793	*/
<>	144:ef7eb2e8f9f7	794	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
<>	144:ef7eb2e8f9f7	795	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	796
<>	144:ef7eb2e8f9f7	797
<>	144:ef7eb2e8f9f7	798	/**
<>	144:ef7eb2e8f9f7	799	* @brief Simultaneously clears and sets specific bits of the handle State
<>	144:ef7eb2e8f9f7	800	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
<>	144:ef7eb2e8f9f7	801	* the first parameter is the ADC handle State, the second parameter is the
<>	144:ef7eb2e8f9f7	802	* bit field to clear, the third and last parameter is the bit field to set.
<>	144:ef7eb2e8f9f7	803	* @retval None
<>	144:ef7eb2e8f9f7	804	*/
<>	144:ef7eb2e8f9f7	805	#define ADC_STATE_CLR_SET MODIFY_REG
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	/**
<>	144:ef7eb2e8f9f7	808	* @brief Clear ADC error code (set it to error code: "no error")
<>	144:ef7eb2e8f9f7	809	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	810	* @retval None
<>	144:ef7eb2e8f9f7	811	*/
<>	144:ef7eb2e8f9f7	812	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	813	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
<>	144:ef7eb2e8f9f7	814
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817
<>	144:ef7eb2e8f9f7	818	/**
<>	144:ef7eb2e8f9f7	819	* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
<>	144:ef7eb2e8f9f7	820	* @param __HANDLE__: ADC handle
<>	144:ef7eb2e8f9f7	821	* @retval None
<>	144:ef7eb2e8f9f7	822	*/
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	825	do{ \
<>	144:ef7eb2e8f9f7	826	if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
<>	144:ef7eb2e8f9f7	827	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
<>	144:ef7eb2e8f9f7	828	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
<>	144:ef7eb2e8f9f7	829	{ \
<>	144:ef7eb2e8f9f7	830	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
<>	144:ef7eb2e8f9f7	831	(__HANDLE__)->Instance->CFGR2 \|= (__HANDLE__)->Init.ClockPrescaler; \
<>	144:ef7eb2e8f9f7	832	} \
<>	144:ef7eb2e8f9f7	833	else \
<>	144:ef7eb2e8f9f7	834	{ \
<>	144:ef7eb2e8f9f7	835	/* CKMOD bits must be reset */ \
<>	144:ef7eb2e8f9f7	836	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
<>	144:ef7eb2e8f9f7	837	ADC->CCR &= ~(ADC_CCR_PRESC); \
<>	144:ef7eb2e8f9f7	838	ADC->CCR \|= (__HANDLE__)->Init.ClockPrescaler; \
<>	144:ef7eb2e8f9f7	839	} \
<>	144:ef7eb2e8f9f7	840	} while(0)
<>	144:ef7eb2e8f9f7	841
<>	144:ef7eb2e8f9f7	842
<>	144:ef7eb2e8f9f7	843	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\|\
<>	144:ef7eb2e8f9f7	844	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
<>	144:ef7eb2e8f9f7	845	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
<>	144:ef7eb2e8f9f7	846	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
<>	144:ef7eb2e8f9f7	847	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
<>	144:ef7eb2e8f9f7	848	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
<>	144:ef7eb2e8f9f7	849	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
<>	144:ef7eb2e8f9f7	850	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
<>	144:ef7eb2e8f9f7	851	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
<>	144:ef7eb2e8f9f7	852	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
<>	144:ef7eb2e8f9f7	853	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
<>	144:ef7eb2e8f9f7	854	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
<>	144:ef7eb2e8f9f7	855	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
<>	144:ef7eb2e8f9f7	856	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
<>	144:ef7eb2e8f9f7	857	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
<>	144:ef7eb2e8f9f7	858	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
<>	144:ef7eb2e8f9f7	859
<>	144:ef7eb2e8f9f7	860	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
<>	144:ef7eb2e8f9f7	861	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
<>	144:ef7eb2e8f9f7	862	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	863	((RESOLUTION) == ADC_RESOLUTION_6B))
<>	144:ef7eb2e8f9f7	864
<>	144:ef7eb2e8f9f7	865	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
<>	144:ef7eb2e8f9f7	866	((RESOLUTION) == ADC_RESOLUTION_6B))
<>	144:ef7eb2e8f9f7	867
<>	144:ef7eb2e8f9f7	868	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
<>	144:ef7eb2e8f9f7	869	((ALIGN) == ADC_DATAALIGN_LEFT))
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
<>	144:ef7eb2e8f9f7	872	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
<>	144:ef7eb2e8f9f7	873	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
<>	144:ef7eb2e8f9f7	874	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
<>	144:ef7eb2e8f9f7	877	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
<>	144:ef7eb2e8f9f7	878	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
<>	144:ef7eb2e8f9f7	879
<>	144:ef7eb2e8f9f7	880	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
<>	144:ef7eb2e8f9f7	881	((OVR) == ADC_OVR_DATA_OVERWRITTEN))
<>	144:ef7eb2e8f9f7	882
<>	144:ef7eb2e8f9f7	883	#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) \|\| \
<>	144:ef7eb2e8f9f7	884	((WATCHDOG) == ADC_RANK_NONE))
<>	144:ef7eb2e8f9f7	885
<>	144:ef7eb2e8f9f7	886	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
<>	144:ef7eb2e8f9f7	887	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	888	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	889	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	890	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	891	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	892	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	893	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	894	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	895	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	896	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	897	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	898	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	899	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	900	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	901	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	902	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	903	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	904	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
<>	144:ef7eb2e8f9f7	905	((CHANNEL) == ADC_CHANNEL_VLCD))
<>	144:ef7eb2e8f9f7	906	#else
<>	144:ef7eb2e8f9f7	907	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
<>	144:ef7eb2e8f9f7	908	((CHANNEL) == ADC_CHANNEL_1) \|\| \
<>	144:ef7eb2e8f9f7	909	((CHANNEL) == ADC_CHANNEL_2) \|\| \
<>	144:ef7eb2e8f9f7	910	((CHANNEL) == ADC_CHANNEL_3) \|\| \
<>	144:ef7eb2e8f9f7	911	((CHANNEL) == ADC_CHANNEL_4) \|\| \
<>	144:ef7eb2e8f9f7	912	((CHANNEL) == ADC_CHANNEL_5) \|\| \
<>	144:ef7eb2e8f9f7	913	((CHANNEL) == ADC_CHANNEL_6) \|\| \
<>	144:ef7eb2e8f9f7	914	((CHANNEL) == ADC_CHANNEL_7) \|\| \
<>	144:ef7eb2e8f9f7	915	((CHANNEL) == ADC_CHANNEL_8) \|\| \
<>	144:ef7eb2e8f9f7	916	((CHANNEL) == ADC_CHANNEL_9) \|\| \
<>	144:ef7eb2e8f9f7	917	((CHANNEL) == ADC_CHANNEL_10) \|\| \
<>	144:ef7eb2e8f9f7	918	((CHANNEL) == ADC_CHANNEL_11) \|\| \
<>	144:ef7eb2e8f9f7	919	((CHANNEL) == ADC_CHANNEL_12) \|\| \
<>	144:ef7eb2e8f9f7	920	((CHANNEL) == ADC_CHANNEL_13) \|\| \
<>	144:ef7eb2e8f9f7	921	((CHANNEL) == ADC_CHANNEL_14) \|\| \
<>	144:ef7eb2e8f9f7	922	((CHANNEL) == ADC_CHANNEL_15) \|\| \
<>	144:ef7eb2e8f9f7	923	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
<>	144:ef7eb2e8f9f7	924	((CHANNEL) == ADC_CHANNEL_VREFINT))
<>	144:ef7eb2e8f9f7	925	#endif
<>	144:ef7eb2e8f9f7	926
<>	144:ef7eb2e8f9f7	927	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) \|\| \
<>	144:ef7eb2e8f9f7	928	((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	929	((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	930	((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	931	((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	932	((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	933	((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) \|\| \
<>	144:ef7eb2e8f9f7	934	((TIME) == ADC_SAMPLETIME_239CYCLES_5))
<>	144:ef7eb2e8f9f7	935
<>	144:ef7eb2e8f9f7	936	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) \|\| \
<>	144:ef7eb2e8f9f7	937	((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
<>	144:ef7eb2e8f9f7	938
<>	144:ef7eb2e8f9f7	939	#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
<>	144:ef7eb2e8f9f7	940	((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
<>	144:ef7eb2e8f9f7	941	((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
<>	144:ef7eb2e8f9f7	942	((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
<>	144:ef7eb2e8f9f7	943	((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
<>	144:ef7eb2e8f9f7	944	((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
<>	144:ef7eb2e8f9f7	945	((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
<>	144:ef7eb2e8f9f7	946	((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
<>	144:ef7eb2e8f9f7	947
<>	144:ef7eb2e8f9f7	948	#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) \|\| \
<>	144:ef7eb2e8f9f7	949	((SHIFT) == ADC_RIGHTBITSHIFT_1 ) \|\| \
<>	144:ef7eb2e8f9f7	950	((SHIFT) == ADC_RIGHTBITSHIFT_2 ) \|\| \
<>	144:ef7eb2e8f9f7	951	((SHIFT) == ADC_RIGHTBITSHIFT_3 ) \|\| \
<>	144:ef7eb2e8f9f7	952	((SHIFT) == ADC_RIGHTBITSHIFT_4 ) \|\| \
<>	144:ef7eb2e8f9f7	953	((SHIFT) == ADC_RIGHTBITSHIFT_5 ) \|\| \
<>	144:ef7eb2e8f9f7	954	((SHIFT) == ADC_RIGHTBITSHIFT_6 ) \|\| \
<>	144:ef7eb2e8f9f7	955	((SHIFT) == ADC_RIGHTBITSHIFT_7 ) \|\| \
<>	144:ef7eb2e8f9f7	956	((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
<>	144:ef7eb2e8f9f7	957
<>	144:ef7eb2e8f9f7	958	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
<>	144:ef7eb2e8f9f7	959	((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
<>	144:ef7eb2e8f9f7	960
<>	144:ef7eb2e8f9f7	961	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) \|\| \
<>	144:ef7eb2e8f9f7	962	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
<>	144:ef7eb2e8f9f7	963	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
<>	144:ef7eb2e8f9f7	964
<>	144:ef7eb2e8f9f7	965	#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
<>	144:ef7eb2e8f9f7	966
<>	144:ef7eb2e8f9f7	967	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
<>	144:ef7eb2e8f9f7	968	((EVENT) == ADC_OVR_EVENT))
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970
<>	144:ef7eb2e8f9f7	971	/** @defgroup ADC_range_verification ADC Range Verification
<>	144:ef7eb2e8f9f7	972	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
<>	144:ef7eb2e8f9f7	973	* @{
<>	144:ef7eb2e8f9f7	974	*/
<>	144:ef7eb2e8f9f7	975	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
<>	144:ef7eb2e8f9f7	976	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) \|\| \
<>	144:ef7eb2e8f9f7	977	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) \|\| \
<>	144:ef7eb2e8f9f7	978	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) \|\| \
<>	144:ef7eb2e8f9f7	979	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F))))
<>	144:ef7eb2e8f9f7	980	/**
<>	144:ef7eb2e8f9f7	981	* @}
<>	144:ef7eb2e8f9f7	982	*/
<>	144:ef7eb2e8f9f7	983
<>	144:ef7eb2e8f9f7	984	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
<>	144:ef7eb2e8f9f7	985	* @{
<>	144:ef7eb2e8f9f7	986	*/
<>	144:ef7eb2e8f9f7	987	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)16)))
<>	144:ef7eb2e8f9f7	988	/**
<>	144:ef7eb2e8f9f7	989	* @}
<>	144:ef7eb2e8f9f7	990	*/
<>	144:ef7eb2e8f9f7	991
<>	144:ef7eb2e8f9f7	992	/**
<>	144:ef7eb2e8f9f7	993	* @}
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995
<>	144:ef7eb2e8f9f7	996	/* Include ADC HAL Extension module */
<>	144:ef7eb2e8f9f7	997	#include "stm32l0xx_hal_adc_ex.h"
<>	144:ef7eb2e8f9f7	998
<>	144:ef7eb2e8f9f7	999	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1000	/** @defgroup ADC_Exported_Functions ADC Exported Functions
<>	144:ef7eb2e8f9f7	1001	* @{
<>	144:ef7eb2e8f9f7	1002	*/
<>	144:ef7eb2e8f9f7	1003	/* Initialization and de-initialization functions **********************************/
<>	144:ef7eb2e8f9f7	1004	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1005	* @brief Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1006	* @{
<>	144:ef7eb2e8f9f7	1007	*/
<>	144:ef7eb2e8f9f7	1008	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1009	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1010	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1011	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1012	/**
<>	144:ef7eb2e8f9f7	1013	* @}
<>	144:ef7eb2e8f9f7	1014	*/
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	/* IO operation functions *****************************************************/
<>	144:ef7eb2e8f9f7	1017	/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
<>	144:ef7eb2e8f9f7	1018	* @{
<>	144:ef7eb2e8f9f7	1019	*/
<>	144:ef7eb2e8f9f7	1020	/* Blocking mode: Polling */
<>	144:ef7eb2e8f9f7	1021	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1022	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1023	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1024	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/* Non-blocking mode: Interruption */
<>	144:ef7eb2e8f9f7	1027	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1028	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	/* Non-blocking mode: DMA */
<>	144:ef7eb2e8f9f7	1031	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
<>	144:ef7eb2e8f9f7	1032	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/* ADC retrieve conversion value intended to be used with polling or interruption */
<>	144:ef7eb2e8f9f7	1035	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
<>	144:ef7eb2e8f9f7	1038	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1039	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1040	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1041	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1042	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1043	/**
<>	144:ef7eb2e8f9f7	1044	* @}
<>	144:ef7eb2e8f9f7	1045	*/
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/* Peripheral Control functions ***********************************************/
<>	144:ef7eb2e8f9f7	1048	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1049	* @{
<>	144:ef7eb2e8f9f7	1050	*/
<>	144:ef7eb2e8f9f7	1051	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
<>	144:ef7eb2e8f9f7	1052	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
<>	144:ef7eb2e8f9f7	1053	/**
<>	144:ef7eb2e8f9f7	1054	* @}
<>	144:ef7eb2e8f9f7	1055	*/
<>	144:ef7eb2e8f9f7	1056
<>	144:ef7eb2e8f9f7	1057	/* Peripheral State functions *************************************************/
<>	144:ef7eb2e8f9f7	1058	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
<>	144:ef7eb2e8f9f7	1059	* @{
<>	144:ef7eb2e8f9f7	1060	*/
<>	144:ef7eb2e8f9f7	1061	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
<>	144:ef7eb2e8f9f7	1062	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
<>	144:ef7eb2e8f9f7	1063	/**
<>	144:ef7eb2e8f9f7	1064	* @}
<>	144:ef7eb2e8f9f7	1065	*/
<>	144:ef7eb2e8f9f7	1066
<>	144:ef7eb2e8f9f7	1067
<>	144:ef7eb2e8f9f7	1068	/**
<>	144:ef7eb2e8f9f7	1069	* @}
<>	144:ef7eb2e8f9f7	1070	*/
<>	144:ef7eb2e8f9f7	1071
<>	144:ef7eb2e8f9f7	1072	/* Define the private group ***********************************/
<>	144:ef7eb2e8f9f7	1073	/**************************************************************/
<>	144:ef7eb2e8f9f7	1074	/** @defgroup ADC_Private ADC Private
<>	144:ef7eb2e8f9f7	1075	* @{
<>	144:ef7eb2e8f9f7	1076	*/
<>	144:ef7eb2e8f9f7	1077	/**
<>	144:ef7eb2e8f9f7	1078	* @}
<>	144:ef7eb2e8f9f7	1079	*/
<>	144:ef7eb2e8f9f7	1080	/**************************************************************/
<>	144:ef7eb2e8f9f7	1081
<>	144:ef7eb2e8f9f7	1082	/**
<>	144:ef7eb2e8f9f7	1083	* @}
<>	144:ef7eb2e8f9f7	1084	*/
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/**
<>	144:ef7eb2e8f9f7	1087	* @}
<>	144:ef7eb2e8f9f7	1088	*/
<>	144:ef7eb2e8f9f7	1089
<>	144:ef7eb2e8f9f7	1090	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1091	}
<>	144:ef7eb2e8f9f7	1092	#endif
<>	144:ef7eb2e8f9f7	1093
<>	144:ef7eb2e8f9f7	1094	#endif /__STM32L0xx_ADC_H /
<>	144:ef7eb2e8f9f7	1095
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/