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mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/stm32l031xx.h@114:fe4fe5cfc3a3
Child:: 151:5eaa88a5bcc7

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	114:fe4fe5cfc3a3	1	/**
mbed_official	114:fe4fe5cfc3a3	2	******************************************************************************
mbed_official	114:fe4fe5cfc3a3	3	* @file stm32l031xx.h
mbed_official	114:fe4fe5cfc3a3	4	* @author MCD Application Team
mbed_official	114:fe4fe5cfc3a3	5	* @version V1.5.0
mbed_official	114:fe4fe5cfc3a3	6	* @date 8-January-2016
mbed_official	114:fe4fe5cfc3a3	7	* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
mbed_official	114:fe4fe5cfc3a3	8	* This file contains all the peripheral register's definitions, bits
mbed_official	114:fe4fe5cfc3a3	9	* definitions and memory mapping for stm32l031xx devices.
mbed_official	114:fe4fe5cfc3a3	10	*
mbed_official	114:fe4fe5cfc3a3	11	* This file contains:
mbed_official	114:fe4fe5cfc3a3	12	* - Data structures and the address mapping for all peripherals
mbed_official	114:fe4fe5cfc3a3	13	* - Peripheral's registers declarations and bits definition
mbed_official	114:fe4fe5cfc3a3	14	* - Macros to access peripheral's registers hardware
mbed_official	114:fe4fe5cfc3a3	15	*
mbed_official	114:fe4fe5cfc3a3	16	******************************************************************************
mbed_official	114:fe4fe5cfc3a3	17	* @attention
mbed_official	114:fe4fe5cfc3a3	18	*
mbed_official	114:fe4fe5cfc3a3	19	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
mbed_official	114:fe4fe5cfc3a3	20	*
mbed_official	114:fe4fe5cfc3a3	21	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	114:fe4fe5cfc3a3	22	* are permitted provided that the following conditions are met:
mbed_official	114:fe4fe5cfc3a3	23	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	114:fe4fe5cfc3a3	24	* this list of conditions and the following disclaimer.
mbed_official	114:fe4fe5cfc3a3	25	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	114:fe4fe5cfc3a3	26	* this list of conditions and the following disclaimer in the documentation
mbed_official	114:fe4fe5cfc3a3	27	* and/or other materials provided with the distribution.
mbed_official	114:fe4fe5cfc3a3	28	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	114:fe4fe5cfc3a3	29	* may be used to endorse or promote products derived from this software
mbed_official	114:fe4fe5cfc3a3	30	* without specific prior written permission.
mbed_official	114:fe4fe5cfc3a3	31	*
mbed_official	114:fe4fe5cfc3a3	32	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	114:fe4fe5cfc3a3	33	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	114:fe4fe5cfc3a3	34	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	114:fe4fe5cfc3a3	35	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	114:fe4fe5cfc3a3	36	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	114:fe4fe5cfc3a3	37	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	114:fe4fe5cfc3a3	38	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	114:fe4fe5cfc3a3	39	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	114:fe4fe5cfc3a3	40	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	114:fe4fe5cfc3a3	41	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	114:fe4fe5cfc3a3	42	*
mbed_official	114:fe4fe5cfc3a3	43	******************************************************************************
mbed_official	114:fe4fe5cfc3a3	44	*/
mbed_official	114:fe4fe5cfc3a3	45
mbed_official	114:fe4fe5cfc3a3	46	/** @addtogroup CMSIS
mbed_official	114:fe4fe5cfc3a3	47	* @{
mbed_official	114:fe4fe5cfc3a3	48	*/
mbed_official	114:fe4fe5cfc3a3	49
mbed_official	114:fe4fe5cfc3a3	50	/** @addtogroup stm32l031xx
mbed_official	114:fe4fe5cfc3a3	51	* @{
mbed_official	114:fe4fe5cfc3a3	52	*/
mbed_official	114:fe4fe5cfc3a3	53
mbed_official	114:fe4fe5cfc3a3	54	#ifndef __STM32L031xx_H
mbed_official	114:fe4fe5cfc3a3	55	#define __STM32L031xx_H
mbed_official	114:fe4fe5cfc3a3	56
mbed_official	114:fe4fe5cfc3a3	57	#ifdef __cplusplus
mbed_official	114:fe4fe5cfc3a3	58	extern "C" {
mbed_official	114:fe4fe5cfc3a3	59	#endif
mbed_official	114:fe4fe5cfc3a3	60
mbed_official	114:fe4fe5cfc3a3	61
mbed_official	114:fe4fe5cfc3a3	62	/** @addtogroup Configuration_section_for_CMSIS
mbed_official	114:fe4fe5cfc3a3	63	* @{
mbed_official	114:fe4fe5cfc3a3	64	*/
mbed_official	114:fe4fe5cfc3a3	65	/**
mbed_official	114:fe4fe5cfc3a3	66	* @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
mbed_official	114:fe4fe5cfc3a3	67	*/
mbed_official	114:fe4fe5cfc3a3	68	#define __CM0PLUS_REV 0 /!< Core Revision r0p0 /
mbed_official	114:fe4fe5cfc3a3	69	#define __MPU_PRESENT 0 /!< STM32L0xx provides no MPU /
mbed_official	114:fe4fe5cfc3a3	70	#define __VTOR_PRESENT 1 /!< Vector Table Register supported /
mbed_official	114:fe4fe5cfc3a3	71	#define __NVIC_PRIO_BITS 2 /!< STM32L0xx uses 2 Bits for the Priority Levels /
mbed_official	114:fe4fe5cfc3a3	72	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
mbed_official	114:fe4fe5cfc3a3	73
mbed_official	114:fe4fe5cfc3a3	74	/**
mbed_official	114:fe4fe5cfc3a3	75	* @}
mbed_official	114:fe4fe5cfc3a3	76	*/
mbed_official	114:fe4fe5cfc3a3	77
mbed_official	114:fe4fe5cfc3a3	78	/** @addtogroup Peripheral_interrupt_number_definition
mbed_official	114:fe4fe5cfc3a3	79	* @{
mbed_official	114:fe4fe5cfc3a3	80	*/
mbed_official	114:fe4fe5cfc3a3	81
mbed_official	114:fe4fe5cfc3a3	82	/**
mbed_official	114:fe4fe5cfc3a3	83	* @brief stm32l031xx Interrupt Number Definition, according to the selected device
mbed_official	114:fe4fe5cfc3a3	84	* in @ref Library_configuration_section
mbed_official	114:fe4fe5cfc3a3	85	*/
mbed_official	114:fe4fe5cfc3a3	86
mbed_official	114:fe4fe5cfc3a3	87	/!< Interrupt Number Definition /
mbed_official	114:fe4fe5cfc3a3	88	typedef enum
mbed_official	114:fe4fe5cfc3a3	89	{
mbed_official	114:fe4fe5cfc3a3	90	/**** Cortex-M0 Processor Exceptions Numbers ****************************************************/
mbed_official	114:fe4fe5cfc3a3	91	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
mbed_official	114:fe4fe5cfc3a3	92	HardFault_IRQn = -13, /!< 3 Cortex-M0+ Hard Fault Interrupt /
mbed_official	114:fe4fe5cfc3a3	93	SVC_IRQn = -5, /!< 11 Cortex-M0+ SV Call Interrupt /
mbed_official	114:fe4fe5cfc3a3	94	PendSV_IRQn = -2, /!< 14 Cortex-M0+ Pend SV Interrupt /
mbed_official	114:fe4fe5cfc3a3	95	SysTick_IRQn = -1, /!< 15 Cortex-M0+ System Tick Interrupt /
mbed_official	114:fe4fe5cfc3a3	96
mbed_official	114:fe4fe5cfc3a3	97	/**** STM32L-0 specific Interrupt Numbers *******************************************************/
mbed_official	114:fe4fe5cfc3a3	98	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
mbed_official	114:fe4fe5cfc3a3	99	PVD_IRQn = 1, /!< PVD through EXTI Line detect Interrupt /
mbed_official	114:fe4fe5cfc3a3	100	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
mbed_official	114:fe4fe5cfc3a3	101	FLASH_IRQn = 3, /!< FLASH Interrupt /
mbed_official	114:fe4fe5cfc3a3	102	RCC_IRQn = 4, /!< RCC Interrupt /
mbed_official	114:fe4fe5cfc3a3	103	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
mbed_official	114:fe4fe5cfc3a3	104	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
mbed_official	114:fe4fe5cfc3a3	105	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
mbed_official	114:fe4fe5cfc3a3	106	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
mbed_official	114:fe4fe5cfc3a3	107	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
mbed_official	114:fe4fe5cfc3a3	108	DMA1_Channel4_5_6_7_IRQn = 11, /!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts /
mbed_official	114:fe4fe5cfc3a3	109	ADC1_COMP_IRQn = 12, /!< ADC1, COMP1 and COMP2 Interrupts /
mbed_official	114:fe4fe5cfc3a3	110	LPTIM1_IRQn = 13, /!< LPTIM1 Interrupt /
mbed_official	114:fe4fe5cfc3a3	111	TIM2_IRQn = 15, /!< TIM2 Interrupt /
mbed_official	114:fe4fe5cfc3a3	112	TIM21_IRQn = 20, /!< TIM21 Interrupt /
mbed_official	114:fe4fe5cfc3a3	113	TIM22_IRQn = 22, /!< TIM22 Interrupt /
mbed_official	114:fe4fe5cfc3a3	114	I2C1_IRQn = 23, /!< I2C1 Interrupt /
mbed_official	114:fe4fe5cfc3a3	115	SPI1_IRQn = 25, /!< SPI1 Interrupt /
mbed_official	114:fe4fe5cfc3a3	116	USART2_IRQn = 28, /!< USART2 Interrupt /
mbed_official	114:fe4fe5cfc3a3	117	LPUART1_IRQn = 29, /!< LPUART1 Interrupt /
mbed_official	114:fe4fe5cfc3a3	118	} IRQn_Type;
mbed_official	114:fe4fe5cfc3a3	119
mbed_official	114:fe4fe5cfc3a3	120	/**
mbed_official	114:fe4fe5cfc3a3	121	* @}
mbed_official	114:fe4fe5cfc3a3	122	*/
mbed_official	114:fe4fe5cfc3a3	123
mbed_official	114:fe4fe5cfc3a3	124	#include "core_cm0plus.h"
mbed_official	114:fe4fe5cfc3a3	125	#include "system_stm32l0xx.h"
mbed_official	114:fe4fe5cfc3a3	126	#include <stdint.h>
mbed_official	114:fe4fe5cfc3a3	127
mbed_official	114:fe4fe5cfc3a3	128	/** @addtogroup Peripheral_registers_structures
mbed_official	114:fe4fe5cfc3a3	129	* @{
mbed_official	114:fe4fe5cfc3a3	130	*/
mbed_official	114:fe4fe5cfc3a3	131
mbed_official	114:fe4fe5cfc3a3	132	/**
mbed_official	114:fe4fe5cfc3a3	133	* @brief Analog to Digital Converter
mbed_official	114:fe4fe5cfc3a3	134	*/
mbed_official	114:fe4fe5cfc3a3	135
mbed_official	114:fe4fe5cfc3a3	136	typedef struct
mbed_official	114:fe4fe5cfc3a3	137	{
mbed_official	114:fe4fe5cfc3a3	138	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
mbed_official	114:fe4fe5cfc3a3	139	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
mbed_official	114:fe4fe5cfc3a3	140	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
mbed_official	114:fe4fe5cfc3a3	141	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
mbed_official	114:fe4fe5cfc3a3	142	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
mbed_official	114:fe4fe5cfc3a3	143	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
mbed_official	114:fe4fe5cfc3a3	144	uint32_t RESERVED1; /!< Reserved, 0x18 /
mbed_official	114:fe4fe5cfc3a3	145	uint32_t RESERVED2; /!< Reserved, 0x1C /
mbed_official	114:fe4fe5cfc3a3	146	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
mbed_official	114:fe4fe5cfc3a3	147	uint32_t RESERVED3; /!< Reserved, 0x24 /
mbed_official	114:fe4fe5cfc3a3	148	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
mbed_official	114:fe4fe5cfc3a3	149	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
mbed_official	114:fe4fe5cfc3a3	150	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
mbed_official	114:fe4fe5cfc3a3	151	uint32_t RESERVED5[28]; /!< Reserved, 0x44 - 0xB0 /
mbed_official	114:fe4fe5cfc3a3	152	__IO uint32_t CALFACT; /!< ADC data register, Address offset:0xB4 /
mbed_official	114:fe4fe5cfc3a3	153	} ADC_TypeDef;
mbed_official	114:fe4fe5cfc3a3	154
mbed_official	114:fe4fe5cfc3a3	155	typedef struct
mbed_official	114:fe4fe5cfc3a3	156	{
mbed_official	114:fe4fe5cfc3a3	157	__IO uint32_t CCR;
mbed_official	114:fe4fe5cfc3a3	158	} ADC_Common_TypeDef;
mbed_official	114:fe4fe5cfc3a3	159
mbed_official	114:fe4fe5cfc3a3	160
mbed_official	114:fe4fe5cfc3a3	161	/**
mbed_official	114:fe4fe5cfc3a3	162	* @brief Comparator
mbed_official	114:fe4fe5cfc3a3	163	*/
mbed_official	114:fe4fe5cfc3a3	164
mbed_official	114:fe4fe5cfc3a3	165	typedef struct
mbed_official	114:fe4fe5cfc3a3	166	{
mbed_official	114:fe4fe5cfc3a3	167	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	168	} COMP_TypeDef;
mbed_official	114:fe4fe5cfc3a3	169
mbed_official	114:fe4fe5cfc3a3	170	typedef struct
mbed_official	114:fe4fe5cfc3a3	171	{
mbed_official	114:fe4fe5cfc3a3	172	__IO uint32_t CSR; /!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	173	} COMP_Common_TypeDef;
mbed_official	114:fe4fe5cfc3a3	174
mbed_official	114:fe4fe5cfc3a3	175
mbed_official	114:fe4fe5cfc3a3	176	/**
mbed_official	114:fe4fe5cfc3a3	177	* @brief CRC calculation unit
mbed_official	114:fe4fe5cfc3a3	178	*/
mbed_official	114:fe4fe5cfc3a3	179
mbed_official	114:fe4fe5cfc3a3	180	typedef struct
mbed_official	114:fe4fe5cfc3a3	181	{
mbed_official	114:fe4fe5cfc3a3	182	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	183	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	184	uint8_t RESERVED0; /!< Reserved, 0x05 /
mbed_official	114:fe4fe5cfc3a3	185	uint16_t RESERVED1; /!< Reserved, 0x06 /
mbed_official	114:fe4fe5cfc3a3	186	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	187	uint32_t RESERVED2; /!< Reserved, 0x0C /
mbed_official	114:fe4fe5cfc3a3	188	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	189	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	190	} CRC_TypeDef;
mbed_official	114:fe4fe5cfc3a3	191
mbed_official	114:fe4fe5cfc3a3	192	/**
mbed_official	114:fe4fe5cfc3a3	193	* @brief Debug MCU
mbed_official	114:fe4fe5cfc3a3	194	*/
mbed_official	114:fe4fe5cfc3a3	195
mbed_official	114:fe4fe5cfc3a3	196	typedef struct
mbed_official	114:fe4fe5cfc3a3	197	{
mbed_official	114:fe4fe5cfc3a3	198	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	199	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	200	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	201	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	202	}DBGMCU_TypeDef;
mbed_official	114:fe4fe5cfc3a3	203
mbed_official	114:fe4fe5cfc3a3	204	/**
mbed_official	114:fe4fe5cfc3a3	205	* @brief DMA Controller
mbed_official	114:fe4fe5cfc3a3	206	*/
mbed_official	114:fe4fe5cfc3a3	207
mbed_official	114:fe4fe5cfc3a3	208	typedef struct
mbed_official	114:fe4fe5cfc3a3	209	{
mbed_official	114:fe4fe5cfc3a3	210	__IO uint32_t CCR; /!< DMA channel x configuration register /
mbed_official	114:fe4fe5cfc3a3	211	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
mbed_official	114:fe4fe5cfc3a3	212	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
mbed_official	114:fe4fe5cfc3a3	213	__IO uint32_t CMAR; /!< DMA channel x memory address register /
mbed_official	114:fe4fe5cfc3a3	214	} DMA_Channel_TypeDef;
mbed_official	114:fe4fe5cfc3a3	215
mbed_official	114:fe4fe5cfc3a3	216	typedef struct
mbed_official	114:fe4fe5cfc3a3	217	{
mbed_official	114:fe4fe5cfc3a3	218	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	219	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	220	} DMA_TypeDef;
mbed_official	114:fe4fe5cfc3a3	221
mbed_official	114:fe4fe5cfc3a3	222	typedef struct
mbed_official	114:fe4fe5cfc3a3	223	{
mbed_official	114:fe4fe5cfc3a3	224	__IO uint32_t CSELR; /!< DMA channel selection register, Address offset: 0xA8 /
mbed_official	114:fe4fe5cfc3a3	225	} DMA_Request_TypeDef;
mbed_official	114:fe4fe5cfc3a3	226
mbed_official	114:fe4fe5cfc3a3	227	/**
mbed_official	114:fe4fe5cfc3a3	228	* @brief External Interrupt/Event Controller
mbed_official	114:fe4fe5cfc3a3	229	*/
mbed_official	114:fe4fe5cfc3a3	230
mbed_official	114:fe4fe5cfc3a3	231	typedef struct
mbed_official	114:fe4fe5cfc3a3	232	{
mbed_official	114:fe4fe5cfc3a3	233	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	234	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	235	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	236	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	237	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	238	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	239	}EXTI_TypeDef;
mbed_official	114:fe4fe5cfc3a3	240
mbed_official	114:fe4fe5cfc3a3	241	/**
mbed_official	114:fe4fe5cfc3a3	242	* @brief FLASH Registers
mbed_official	114:fe4fe5cfc3a3	243	*/
mbed_official	114:fe4fe5cfc3a3	244	typedef struct
mbed_official	114:fe4fe5cfc3a3	245	{
mbed_official	114:fe4fe5cfc3a3	246	__IO uint32_t ACR; /!< Access control register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	247	__IO uint32_t PECR; /!< Program/erase control register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	248	__IO uint32_t PDKEYR; /!< Power down key register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	249	__IO uint32_t PEKEYR; /!< Program/erase key register, Address offset: 0x0c /
mbed_official	114:fe4fe5cfc3a3	250	__IO uint32_t PRGKEYR; /!< Program memory key register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	251	__IO uint32_t OPTKEYR; /!< Option byte key register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	252	__IO uint32_t SR; /!< Status register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	253	__IO uint32_t OPTR; /!< Option byte register, Address offset: 0x1c /
mbed_official	114:fe4fe5cfc3a3	254	__IO uint32_t WRPR; /!< Write protection register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	255	} FLASH_TypeDef;
mbed_official	114:fe4fe5cfc3a3	256
mbed_official	114:fe4fe5cfc3a3	257
mbed_official	114:fe4fe5cfc3a3	258	/**
mbed_official	114:fe4fe5cfc3a3	259	* @brief Option Bytes Registers
mbed_official	114:fe4fe5cfc3a3	260	*/
mbed_official	114:fe4fe5cfc3a3	261	typedef struct
mbed_official	114:fe4fe5cfc3a3	262	{
mbed_official	114:fe4fe5cfc3a3	263	__IO uint32_t RDP; /!< Read protection register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	264	__IO uint32_t USER; /!< user register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	265	__IO uint32_t WRP01; /!< write protection Bytes 0 and 1 Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	266	} OB_TypeDef;
mbed_official	114:fe4fe5cfc3a3	267
mbed_official	114:fe4fe5cfc3a3	268
mbed_official	114:fe4fe5cfc3a3	269	/**
mbed_official	114:fe4fe5cfc3a3	270	* @brief General Purpose IO
mbed_official	114:fe4fe5cfc3a3	271	*/
mbed_official	114:fe4fe5cfc3a3	272
mbed_official	114:fe4fe5cfc3a3	273	typedef struct
mbed_official	114:fe4fe5cfc3a3	274	{
mbed_official	114:fe4fe5cfc3a3	275	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	276	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	277	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	278	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	279	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	280	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	281	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	282	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	283	__IO uint32_t AFR[2]; /!< GPIO alternate function register, Address offset: 0x20-0x24 /
mbed_official	114:fe4fe5cfc3a3	284	__IO uint32_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	285	}GPIO_TypeDef;
mbed_official	114:fe4fe5cfc3a3	286
mbed_official	114:fe4fe5cfc3a3	287	/**
mbed_official	114:fe4fe5cfc3a3	288	* @brief LPTIMIMER
mbed_official	114:fe4fe5cfc3a3	289	*/
mbed_official	114:fe4fe5cfc3a3	290	typedef struct
mbed_official	114:fe4fe5cfc3a3	291	{
mbed_official	114:fe4fe5cfc3a3	292	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	293	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	294	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	295	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	296	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	297	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	298	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	299	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	300	} LPTIM_TypeDef;
mbed_official	114:fe4fe5cfc3a3	301
mbed_official	114:fe4fe5cfc3a3	302	/**
mbed_official	114:fe4fe5cfc3a3	303	* @brief SysTem Configuration
mbed_official	114:fe4fe5cfc3a3	304	*/
mbed_official	114:fe4fe5cfc3a3	305
mbed_official	114:fe4fe5cfc3a3	306	typedef struct
mbed_official	114:fe4fe5cfc3a3	307	{
mbed_official	114:fe4fe5cfc3a3	308	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	309	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	310	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
mbed_official	114:fe4fe5cfc3a3	311	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
mbed_official	114:fe4fe5cfc3a3	312	__IO uint32_t CFGR3; /!< SYSCFG configuration register 3, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	313	} SYSCFG_TypeDef;
mbed_official	114:fe4fe5cfc3a3	314
mbed_official	114:fe4fe5cfc3a3	315
mbed_official	114:fe4fe5cfc3a3	316
mbed_official	114:fe4fe5cfc3a3	317	/**
mbed_official	114:fe4fe5cfc3a3	318	* @brief Inter-integrated Circuit Interface
mbed_official	114:fe4fe5cfc3a3	319	*/
mbed_official	114:fe4fe5cfc3a3	320
mbed_official	114:fe4fe5cfc3a3	321	typedef struct
mbed_official	114:fe4fe5cfc3a3	322	{
mbed_official	114:fe4fe5cfc3a3	323	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	324	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	325	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	326	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	327	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	328	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	329	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	330	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	331	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	332	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
mbed_official	114:fe4fe5cfc3a3	333	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	334	}I2C_TypeDef;
mbed_official	114:fe4fe5cfc3a3	335
mbed_official	114:fe4fe5cfc3a3	336
mbed_official	114:fe4fe5cfc3a3	337	/**
mbed_official	114:fe4fe5cfc3a3	338	* @brief Independent WATCHDOG
mbed_official	114:fe4fe5cfc3a3	339	*/
mbed_official	114:fe4fe5cfc3a3	340	typedef struct
mbed_official	114:fe4fe5cfc3a3	341	{
mbed_official	114:fe4fe5cfc3a3	342	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	343	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	344	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	345	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	346	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	347	} IWDG_TypeDef;
mbed_official	114:fe4fe5cfc3a3	348
mbed_official	114:fe4fe5cfc3a3	349	/**
mbed_official	114:fe4fe5cfc3a3	350	* @brief Power Control
mbed_official	114:fe4fe5cfc3a3	351	*/
mbed_official	114:fe4fe5cfc3a3	352	typedef struct
mbed_official	114:fe4fe5cfc3a3	353	{
mbed_official	114:fe4fe5cfc3a3	354	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	355	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	356	} PWR_TypeDef;
mbed_official	114:fe4fe5cfc3a3	357
mbed_official	114:fe4fe5cfc3a3	358	/**
mbed_official	114:fe4fe5cfc3a3	359	* @brief Reset and Clock Control
mbed_official	114:fe4fe5cfc3a3	360	*/
mbed_official	114:fe4fe5cfc3a3	361	typedef struct
mbed_official	114:fe4fe5cfc3a3	362	{
mbed_official	114:fe4fe5cfc3a3	363	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	364	__IO uint32_t ICSCR; /!< RCC Internal clock sources calibration register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	365	__IO uint32_t CRRCR; /!< RCC Clock recovery RC register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	366	__IO uint32_t CFGR; /!< RCC Clock configuration register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	367	__IO uint32_t CIER; /!< RCC Clock interrupt enable register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	368	__IO uint32_t CIFR; /!< RCC Clock interrupt flag register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	369	__IO uint32_t CICR; /!< RCC Clock interrupt clear register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	370	__IO uint32_t IOPRSTR; /!< RCC IO port reset register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	371	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	372	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
mbed_official	114:fe4fe5cfc3a3	373	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	374	__IO uint32_t IOPENR; /!< RCC Clock IO port enable register, Address offset: 0x2C /
mbed_official	114:fe4fe5cfc3a3	375	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock enable register, Address offset: 0x30 /
mbed_official	114:fe4fe5cfc3a3	376	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral enable register, Address offset: 0x34 /
mbed_official	114:fe4fe5cfc3a3	377	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral enable register, Address offset: 0x38 /
mbed_official	114:fe4fe5cfc3a3	378	__IO uint32_t IOPSMENR; /!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C /
mbed_official	114:fe4fe5cfc3a3	379	__IO uint32_t AHBSMENR; /!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 /
mbed_official	114:fe4fe5cfc3a3	380	__IO uint32_t APB2SMENR; /!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 /
mbed_official	114:fe4fe5cfc3a3	381	__IO uint32_t APB1SMENR; /!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 /
mbed_official	114:fe4fe5cfc3a3	382	__IO uint32_t CCIPR; /!< RCC clock configuration register, Address offset: 0x4C /
mbed_official	114:fe4fe5cfc3a3	383	__IO uint32_t CSR; /!< RCC Control/status register, Address offset: 0x50 /
mbed_official	114:fe4fe5cfc3a3	384	} RCC_TypeDef;
mbed_official	114:fe4fe5cfc3a3	385
mbed_official	114:fe4fe5cfc3a3	386	/**
mbed_official	114:fe4fe5cfc3a3	387	* @brief Real-Time Clock
mbed_official	114:fe4fe5cfc3a3	388	*/
mbed_official	114:fe4fe5cfc3a3	389	typedef struct
mbed_official	114:fe4fe5cfc3a3	390	{
mbed_official	114:fe4fe5cfc3a3	391	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	392	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	393	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	394	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	395	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	396	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	397	uint32_t RESERVED; /!< Reserved, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	398	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	399	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	400	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
mbed_official	114:fe4fe5cfc3a3	401	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	402	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
mbed_official	114:fe4fe5cfc3a3	403	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
mbed_official	114:fe4fe5cfc3a3	404	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
mbed_official	114:fe4fe5cfc3a3	405	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
mbed_official	114:fe4fe5cfc3a3	406	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
mbed_official	114:fe4fe5cfc3a3	407	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
mbed_official	114:fe4fe5cfc3a3	408	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
mbed_official	114:fe4fe5cfc3a3	409	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
mbed_official	114:fe4fe5cfc3a3	410	__IO uint32_t OR; /!< RTC option register, Address offset 0x4C /
mbed_official	114:fe4fe5cfc3a3	411	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
mbed_official	114:fe4fe5cfc3a3	412	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
mbed_official	114:fe4fe5cfc3a3	413	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
mbed_official	114:fe4fe5cfc3a3	414	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
mbed_official	114:fe4fe5cfc3a3	415	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
mbed_official	114:fe4fe5cfc3a3	416	} RTC_TypeDef;
mbed_official	114:fe4fe5cfc3a3	417
mbed_official	114:fe4fe5cfc3a3	418
mbed_official	114:fe4fe5cfc3a3	419	/**
mbed_official	114:fe4fe5cfc3a3	420	* @brief Serial Peripheral Interface
mbed_official	114:fe4fe5cfc3a3	421	*/
mbed_official	114:fe4fe5cfc3a3	422	typedef struct
mbed_official	114:fe4fe5cfc3a3	423	{
mbed_official	114:fe4fe5cfc3a3	424	__IO uint32_t CR1; /!< SPI Control register 1, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	425	__IO uint32_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	426	__IO uint32_t SR; /!< SPI Status register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	427	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	428	__IO uint32_t CRCPR; /!< SPI CRC polynomial register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	429	__IO uint32_t RXCRCR; /!< SPI Rx CRC register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	430	__IO uint32_t TXCRCR; /!< SPI Tx CRC register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	431	} SPI_TypeDef;
mbed_official	114:fe4fe5cfc3a3	432
mbed_official	114:fe4fe5cfc3a3	433	/**
mbed_official	114:fe4fe5cfc3a3	434	* @brief TIM
mbed_official	114:fe4fe5cfc3a3	435	*/
mbed_official	114:fe4fe5cfc3a3	436	typedef struct
mbed_official	114:fe4fe5cfc3a3	437	{
mbed_official	114:fe4fe5cfc3a3	438	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	439	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	440	__IO uint32_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	441	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	442	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	443	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	444	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	445	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	446	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	447	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
mbed_official	114:fe4fe5cfc3a3	448	__IO uint32_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	449	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
mbed_official	114:fe4fe5cfc3a3	450	uint32_t RESERVED12;/!< Reserved Address offset: 0x30 /
mbed_official	114:fe4fe5cfc3a3	451	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
mbed_official	114:fe4fe5cfc3a3	452	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
mbed_official	114:fe4fe5cfc3a3	453	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
mbed_official	114:fe4fe5cfc3a3	454	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
mbed_official	114:fe4fe5cfc3a3	455	uint32_t RESERVED17;/!< Reserved, Address offset: 0x44 /
mbed_official	114:fe4fe5cfc3a3	456	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
mbed_official	114:fe4fe5cfc3a3	457	__IO uint32_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
mbed_official	114:fe4fe5cfc3a3	458	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
mbed_official	114:fe4fe5cfc3a3	459	} TIM_TypeDef;
mbed_official	114:fe4fe5cfc3a3	460
mbed_official	114:fe4fe5cfc3a3	461	/**
mbed_official	114:fe4fe5cfc3a3	462	* @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official	114:fe4fe5cfc3a3	463	*/
mbed_official	114:fe4fe5cfc3a3	464	typedef struct
mbed_official	114:fe4fe5cfc3a3	465	{
mbed_official	114:fe4fe5cfc3a3	466	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	467	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	468	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	469	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
mbed_official	114:fe4fe5cfc3a3	470	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
mbed_official	114:fe4fe5cfc3a3	471	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
mbed_official	114:fe4fe5cfc3a3	472	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
mbed_official	114:fe4fe5cfc3a3	473	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
mbed_official	114:fe4fe5cfc3a3	474	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
mbed_official	114:fe4fe5cfc3a3	475	__IO uint32_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
mbed_official	114:fe4fe5cfc3a3	476	__IO uint32_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
mbed_official	114:fe4fe5cfc3a3	477	} USART_TypeDef;
mbed_official	114:fe4fe5cfc3a3	478
mbed_official	114:fe4fe5cfc3a3	479	/**
mbed_official	114:fe4fe5cfc3a3	480	* @brief Window WATCHDOG
mbed_official	114:fe4fe5cfc3a3	481	*/
mbed_official	114:fe4fe5cfc3a3	482	typedef struct
mbed_official	114:fe4fe5cfc3a3	483	{
mbed_official	114:fe4fe5cfc3a3	484	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
mbed_official	114:fe4fe5cfc3a3	485	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
mbed_official	114:fe4fe5cfc3a3	486	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
mbed_official	114:fe4fe5cfc3a3	487	} WWDG_TypeDef;
mbed_official	114:fe4fe5cfc3a3	488
mbed_official	114:fe4fe5cfc3a3	489
mbed_official	114:fe4fe5cfc3a3	490	/**
mbed_official	114:fe4fe5cfc3a3	491	* @}
mbed_official	114:fe4fe5cfc3a3	492	*/
mbed_official	114:fe4fe5cfc3a3	493
mbed_official	114:fe4fe5cfc3a3	494	/** @addtogroup Peripheral_memory_map
mbed_official	114:fe4fe5cfc3a3	495	* @{
mbed_official	114:fe4fe5cfc3a3	496	*/
mbed_official	114:fe4fe5cfc3a3	497	#define FLASH_BASE ((uint32_t)0x08000000U) /!< FLASH base address in the alias region /
mbed_official	114:fe4fe5cfc3a3	498	#define FLASH_END ((uint32_t)0x08007FFFU) /!< FLASH end address in the alias region /
mbed_official	114:fe4fe5cfc3a3	499	#define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /!< DATA_EEPROM base address in the alias region /
mbed_official	114:fe4fe5cfc3a3	500	#define DATA_EEPROM_END ((uint32_t)0x080803FFU) /!< DATA EEPROM end address in the alias region /
mbed_official	114:fe4fe5cfc3a3	501	#define SRAM_BASE ((uint32_t)0x20000000U) /!< SRAM base address in the alias region /
mbed_official	114:fe4fe5cfc3a3	502	#define PERIPH_BASE ((uint32_t)0x40000000U) /!< Peripheral base address in the alias region /
mbed_official	114:fe4fe5cfc3a3	503
mbed_official	114:fe4fe5cfc3a3	504	/!< Peripheral memory map /
mbed_official	114:fe4fe5cfc3a3	505	#define APBPERIPH_BASE PERIPH_BASE
mbed_official	114:fe4fe5cfc3a3	506	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official	114:fe4fe5cfc3a3	507	#define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official	114:fe4fe5cfc3a3	508
mbed_official	114:fe4fe5cfc3a3	509	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official	114:fe4fe5cfc3a3	510	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official	114:fe4fe5cfc3a3	511	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official	114:fe4fe5cfc3a3	512	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official	114:fe4fe5cfc3a3	513	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official	114:fe4fe5cfc3a3	514	#define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official	114:fe4fe5cfc3a3	515	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official	114:fe4fe5cfc3a3	516	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official	114:fe4fe5cfc3a3	517	#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
mbed_official	114:fe4fe5cfc3a3	518
mbed_official	114:fe4fe5cfc3a3	519	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official	114:fe4fe5cfc3a3	520	#define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
mbed_official	114:fe4fe5cfc3a3	521	#define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official	114:fe4fe5cfc3a3	522	#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
mbed_official	114:fe4fe5cfc3a3	523	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official	114:fe4fe5cfc3a3	524	#define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
mbed_official	114:fe4fe5cfc3a3	525	#define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
mbed_official	114:fe4fe5cfc3a3	526	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official	114:fe4fe5cfc3a3	527	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official	114:fe4fe5cfc3a3	528	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official	114:fe4fe5cfc3a3	529	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official	114:fe4fe5cfc3a3	530
mbed_official	114:fe4fe5cfc3a3	531	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official	114:fe4fe5cfc3a3	532	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official	114:fe4fe5cfc3a3	533	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official	114:fe4fe5cfc3a3	534	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official	114:fe4fe5cfc3a3	535	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official	114:fe4fe5cfc3a3	536	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official	114:fe4fe5cfc3a3	537	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official	114:fe4fe5cfc3a3	538	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official	114:fe4fe5cfc3a3	539	#define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
mbed_official	114:fe4fe5cfc3a3	540
mbed_official	114:fe4fe5cfc3a3	541
mbed_official	114:fe4fe5cfc3a3	542	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official	114:fe4fe5cfc3a3	543	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
mbed_official	114:fe4fe5cfc3a3	544	#define OB_BASE ((uint32_t)0x1FF80000U) /!< FLASH Option Bytes base address /
mbed_official	114:fe4fe5cfc3a3	545	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official	114:fe4fe5cfc3a3	546
mbed_official	114:fe4fe5cfc3a3	547	#define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
mbed_official	114:fe4fe5cfc3a3	548	#define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
mbed_official	114:fe4fe5cfc3a3	549	#define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
mbed_official	114:fe4fe5cfc3a3	550	#define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
mbed_official	114:fe4fe5cfc3a3	551
mbed_official	114:fe4fe5cfc3a3	552	/**
mbed_official	114:fe4fe5cfc3a3	553	* @}
mbed_official	114:fe4fe5cfc3a3	554	*/
mbed_official	114:fe4fe5cfc3a3	555
mbed_official	114:fe4fe5cfc3a3	556	/** @addtogroup Peripheral_declaration
mbed_official	114:fe4fe5cfc3a3	557	* @{
mbed_official	114:fe4fe5cfc3a3	558	*/
mbed_official	114:fe4fe5cfc3a3	559
mbed_official	114:fe4fe5cfc3a3	560	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official	114:fe4fe5cfc3a3	561	#define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official	114:fe4fe5cfc3a3	562	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official	114:fe4fe5cfc3a3	563	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official	114:fe4fe5cfc3a3	564	#define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official	114:fe4fe5cfc3a3	565	#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
mbed_official	114:fe4fe5cfc3a3	566	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official	114:fe4fe5cfc3a3	567	#define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official	114:fe4fe5cfc3a3	568	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
mbed_official	114:fe4fe5cfc3a3	569
mbed_official	114:fe4fe5cfc3a3	570	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official	114:fe4fe5cfc3a3	571	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
mbed_official	114:fe4fe5cfc3a3	572	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official	114:fe4fe5cfc3a3	573	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official	114:fe4fe5cfc3a3	574	#define TIM21 ((TIM_TypeDef *) TIM21_BASE)
mbed_official	114:fe4fe5cfc3a3	575	#define TIM22 ((TIM_TypeDef *) TIM22_BASE)
mbed_official	114:fe4fe5cfc3a3	576	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official	114:fe4fe5cfc3a3	577	#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official	114:fe4fe5cfc3a3	578	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	579	#define ADC ADC1_COMMON
mbed_official	114:fe4fe5cfc3a3	580	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official	114:fe4fe5cfc3a3	581	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official	114:fe4fe5cfc3a3	582
mbed_official	114:fe4fe5cfc3a3	583	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official	114:fe4fe5cfc3a3	584	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official	114:fe4fe5cfc3a3	585	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official	114:fe4fe5cfc3a3	586	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official	114:fe4fe5cfc3a3	587	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official	114:fe4fe5cfc3a3	588	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official	114:fe4fe5cfc3a3	589	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official	114:fe4fe5cfc3a3	590	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official	114:fe4fe5cfc3a3	591	#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
mbed_official	114:fe4fe5cfc3a3	592
mbed_official	114:fe4fe5cfc3a3	593
mbed_official	114:fe4fe5cfc3a3	594	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official	114:fe4fe5cfc3a3	595	#define OB ((OB_TypeDef *) OB_BASE)
mbed_official	114:fe4fe5cfc3a3	596	#define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official	114:fe4fe5cfc3a3	597	#define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official	114:fe4fe5cfc3a3	598
mbed_official	114:fe4fe5cfc3a3	599	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official	114:fe4fe5cfc3a3	600	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official	114:fe4fe5cfc3a3	601	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official	114:fe4fe5cfc3a3	602	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official	114:fe4fe5cfc3a3	603
mbed_official	114:fe4fe5cfc3a3	604	/**
mbed_official	114:fe4fe5cfc3a3	605	* @}
mbed_official	114:fe4fe5cfc3a3	606	*/
mbed_official	114:fe4fe5cfc3a3	607
mbed_official	114:fe4fe5cfc3a3	608	/** @addtogroup Exported_constants
mbed_official	114:fe4fe5cfc3a3	609	* @{
mbed_official	114:fe4fe5cfc3a3	610	*/
mbed_official	114:fe4fe5cfc3a3	611
mbed_official	114:fe4fe5cfc3a3	612	/** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official	114:fe4fe5cfc3a3	613	* @{
mbed_official	114:fe4fe5cfc3a3	614	*/
mbed_official	114:fe4fe5cfc3a3	615
mbed_official	114:fe4fe5cfc3a3	616	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	617	/* Peripheral Registers Bits Definition */
mbed_official	114:fe4fe5cfc3a3	618	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	619	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	620	/* */
mbed_official	114:fe4fe5cfc3a3	621	/* Analog to Digital Converter (ADC) */
mbed_official	114:fe4fe5cfc3a3	622	/* */
mbed_official	114:fe4fe5cfc3a3	623	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	624	/****************** Bits definition for ADC_ISR register ****************/
mbed_official	114:fe4fe5cfc3a3	625	#define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /!< End of calibration flag /
mbed_official	114:fe4fe5cfc3a3	626	#define ADC_ISR_AWD ((uint32_t)0x00000080U) /!< Analog watchdog flag /
mbed_official	114:fe4fe5cfc3a3	627	#define ADC_ISR_OVR ((uint32_t)0x00000010U) /!< Overrun flag /
mbed_official	114:fe4fe5cfc3a3	628	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /!< End of Sequence flag /
mbed_official	114:fe4fe5cfc3a3	629	#define ADC_ISR_EOC ((uint32_t)0x00000004U) /!< End of Conversion /
mbed_official	114:fe4fe5cfc3a3	630	#define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /!< End of sampling flag /
mbed_official	114:fe4fe5cfc3a3	631	#define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /!< ADC Ready /
mbed_official	114:fe4fe5cfc3a3	632
mbed_official	114:fe4fe5cfc3a3	633	/* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official	114:fe4fe5cfc3a3	634	#define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official	114:fe4fe5cfc3a3	635
mbed_official	114:fe4fe5cfc3a3	636	/****************** Bits definition for ADC_IER register ****************/
mbed_official	114:fe4fe5cfc3a3	637	#define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /!< Enf Of Calibration interrupt enable /
mbed_official	114:fe4fe5cfc3a3	638	#define ADC_IER_AWDIE ((uint32_t)0x00000080U) /!< Analog Watchdog interrupt enable /
mbed_official	114:fe4fe5cfc3a3	639	#define ADC_IER_OVRIE ((uint32_t)0x00000010U) /!< Overrun interrupt enable /
mbed_official	114:fe4fe5cfc3a3	640	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /!< End of Sequence of conversion interrupt enable /
mbed_official	114:fe4fe5cfc3a3	641	#define ADC_IER_EOCIE ((uint32_t)0x00000004U) /!< End of Conversion interrupt enable /
mbed_official	114:fe4fe5cfc3a3	642	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /!< End of sampling interrupt enable /
mbed_official	114:fe4fe5cfc3a3	643	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /!< ADC Ready interrupt enable /
mbed_official	114:fe4fe5cfc3a3	644
mbed_official	114:fe4fe5cfc3a3	645	/* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official	114:fe4fe5cfc3a3	646	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official	114:fe4fe5cfc3a3	647
mbed_official	114:fe4fe5cfc3a3	648	/****************** Bits definition for ADC_CR register *****************/
mbed_official	114:fe4fe5cfc3a3	649	#define ADC_CR_ADCAL ((uint32_t)0x80000000U) /!< ADC calibration /
mbed_official	114:fe4fe5cfc3a3	650	#define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /!< ADC Voltage Regulator Enable /
mbed_official	114:fe4fe5cfc3a3	651	#define ADC_CR_ADSTP ((uint32_t)0x00000010U) /!< ADC stop of conversion command /
mbed_official	114:fe4fe5cfc3a3	652	#define ADC_CR_ADSTART ((uint32_t)0x00000004U) /!< ADC start of conversion /
mbed_official	114:fe4fe5cfc3a3	653	#define ADC_CR_ADDIS ((uint32_t)0x00000002U) /!< ADC disable command /
mbed_official	114:fe4fe5cfc3a3	654	#define ADC_CR_ADEN ((uint32_t)0x00000001U) /!< ADC enable control / /#### TBV /
mbed_official	114:fe4fe5cfc3a3	655
mbed_official	114:fe4fe5cfc3a3	656	/***************** Bits definition for ADC_CFGR1 register ***************/
mbed_official	114:fe4fe5cfc3a3	657	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
mbed_official	114:fe4fe5cfc3a3	658	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	659	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	660	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	661	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	662	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	663	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /!< Analog watchdog enable on regular channels /
mbed_official	114:fe4fe5cfc3a3	664	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /!< Enable the watchdog on a single channel or on all channels /
mbed_official	114:fe4fe5cfc3a3	665	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /!< Discontinuous mode on regular channels /
mbed_official	114:fe4fe5cfc3a3	666	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /!< ADC auto power off /
mbed_official	114:fe4fe5cfc3a3	667	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /!< ADC wait conversion mode /
mbed_official	114:fe4fe5cfc3a3	668	#define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /!< Continuous Conversion /
mbed_official	114:fe4fe5cfc3a3	669	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /!< Overrun mode /
mbed_official	114:fe4fe5cfc3a3	670	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
mbed_official	114:fe4fe5cfc3a3	671	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	672	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	673	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
mbed_official	114:fe4fe5cfc3a3	674	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	675	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	676	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	677	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /!< Data Alignment /
mbed_official	114:fe4fe5cfc3a3	678	#define ADC_CFGR1_RES ((uint32_t)0x00000018U) /!< RES[1:0] bits (Resolution) /
mbed_official	114:fe4fe5cfc3a3	679	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	680	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	681	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /!< Sequence scan direction /
mbed_official	114:fe4fe5cfc3a3	682	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /!< Direct memory access configuration /
mbed_official	114:fe4fe5cfc3a3	683	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /!< Direct memory access enable /
mbed_official	114:fe4fe5cfc3a3	684
mbed_official	114:fe4fe5cfc3a3	685	/* Old WAIT bit definition, maintained for legacy purpose */
mbed_official	114:fe4fe5cfc3a3	686	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official	114:fe4fe5cfc3a3	687
mbed_official	114:fe4fe5cfc3a3	688	/***************** Bits definition for ADC_CFGR2 register ***************/
mbed_official	114:fe4fe5cfc3a3	689	#define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /!< Triggered Oversampling /
mbed_official	114:fe4fe5cfc3a3	690	#define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /!< OVSS [3:0] bits (Oversampling shift) /
mbed_official	114:fe4fe5cfc3a3	691	#define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	692	#define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	693	#define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	694	#define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	695	#define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /!< OVSR [2:0] bits (Oversampling ratio) /
mbed_official	114:fe4fe5cfc3a3	696	#define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	697	#define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	698	#define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	699	#define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /!< Oversampler Enable /
mbed_official	114:fe4fe5cfc3a3	700	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /!< CKMODE [1:0] bits (ADC clock mode) /
mbed_official	114:fe4fe5cfc3a3	701	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	702	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	703
mbed_official	114:fe4fe5cfc3a3	704
mbed_official	114:fe4fe5cfc3a3	705	/**************** Bit definition for ADC_SMPR register ******************/
mbed_official	114:fe4fe5cfc3a3	706	#define ADC_SMPR_SMP ((uint32_t)0x00000007U) /!< SMPR[2:0] bits (Sampling time selection) /
mbed_official	114:fe4fe5cfc3a3	707	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	708	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	709	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	710
mbed_official	114:fe4fe5cfc3a3	711	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	712	#define ADC_SMPR_SMPR ADC_SMPR_SMP
mbed_official	114:fe4fe5cfc3a3	713	#define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
mbed_official	114:fe4fe5cfc3a3	714	#define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
mbed_official	114:fe4fe5cfc3a3	715	#define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
mbed_official	114:fe4fe5cfc3a3	716
mbed_official	114:fe4fe5cfc3a3	717	/***************** Bit definition for ADC_TR register ******************/
mbed_official	114:fe4fe5cfc3a3	718	#define ADC_TR_HT ((uint32_t)0x0FFF0000U) /!< Analog watchdog high threshold /
mbed_official	114:fe4fe5cfc3a3	719	#define ADC_TR_LT ((uint32_t)0x00000FFFU) /!< Analog watchdog low threshold /
mbed_official	114:fe4fe5cfc3a3	720
mbed_official	114:fe4fe5cfc3a3	721	/**************** Bit definition for ADC_CHSELR register ****************/
mbed_official	114:fe4fe5cfc3a3	722	#define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /!< ADC group regular sequencer channels /
mbed_official	114:fe4fe5cfc3a3	723	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /!< Channel 18 selection /
mbed_official	114:fe4fe5cfc3a3	724	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /!< Channel 17 selection /
mbed_official	114:fe4fe5cfc3a3	725	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /!< Channel 15 selection /
mbed_official	114:fe4fe5cfc3a3	726	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /!< Channel 14 selection /
mbed_official	114:fe4fe5cfc3a3	727	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /!< Channel 13 selection /
mbed_official	114:fe4fe5cfc3a3	728	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /!< Channel 12 selection /
mbed_official	114:fe4fe5cfc3a3	729	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /!< Channel 11 selection /
mbed_official	114:fe4fe5cfc3a3	730	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /!< Channel 10 selection /
mbed_official	114:fe4fe5cfc3a3	731	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /!< Channel 9 selection /
mbed_official	114:fe4fe5cfc3a3	732	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /!< Channel 8 selection /
mbed_official	114:fe4fe5cfc3a3	733	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /!< Channel 7 selection /
mbed_official	114:fe4fe5cfc3a3	734	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /!< Channel 6 selection /
mbed_official	114:fe4fe5cfc3a3	735	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /!< Channel 5 selection /
mbed_official	114:fe4fe5cfc3a3	736	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /!< Channel 4 selection /
mbed_official	114:fe4fe5cfc3a3	737	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /!< Channel 3 selection /
mbed_official	114:fe4fe5cfc3a3	738	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /!< Channel 2 selection /
mbed_official	114:fe4fe5cfc3a3	739	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /!< Channel 1 selection /
mbed_official	114:fe4fe5cfc3a3	740	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /!< Channel 0 selection /
mbed_official	114:fe4fe5cfc3a3	741
mbed_official	114:fe4fe5cfc3a3	742	/****************** Bit definition for ADC_DR register ******************/
mbed_official	114:fe4fe5cfc3a3	743	#define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /!< Regular data /
mbed_official	114:fe4fe5cfc3a3	744
mbed_official	114:fe4fe5cfc3a3	745	/****************** Bit definition for ADC_CALFACT register ******************/
mbed_official	114:fe4fe5cfc3a3	746	#define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /!< Calibration factor /
mbed_official	114:fe4fe5cfc3a3	747
mbed_official	114:fe4fe5cfc3a3	748	/***************** Bit definition for ADC_CCR register ******************/
mbed_official	114:fe4fe5cfc3a3	749	#define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /!< Low Frequency Mode enable /
mbed_official	114:fe4fe5cfc3a3	750	#define ADC_CCR_TSEN ((uint32_t)0x00800000U) /!< Temperature sensore enable /
mbed_official	114:fe4fe5cfc3a3	751	#define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /!< Vrefint enable /
mbed_official	114:fe4fe5cfc3a3	752	#define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /!< PRESC [3:0] bits (ADC prescaler) /
mbed_official	114:fe4fe5cfc3a3	753	#define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	754	#define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	755	#define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	756	#define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	757
mbed_official	114:fe4fe5cfc3a3	758	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	759	/* */
mbed_official	114:fe4fe5cfc3a3	760	/* Analog Comparators (COMP) */
mbed_official	114:fe4fe5cfc3a3	761	/* */
mbed_official	114:fe4fe5cfc3a3	762	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	763	/*********** Bit definition for COMP_CSR register (COMP1 and COMP2) ************/
mbed_official	114:fe4fe5cfc3a3	764	/* COMP1 bits definition */
mbed_official	114:fe4fe5cfc3a3	765	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /!< COMP1 enable /
mbed_official	114:fe4fe5cfc3a3	766	#define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /!< COMP1 inverting input select /
mbed_official	114:fe4fe5cfc3a3	767	#define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /!< COMP1 inverting input select bit 0 /
mbed_official	114:fe4fe5cfc3a3	768	#define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /!< COMP1 inverting input select bit 1 /
mbed_official	114:fe4fe5cfc3a3	769	#define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /!< Comparators window mode enable /
mbed_official	114:fe4fe5cfc3a3	770	#define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /!< COMP1 LPTIM1 IN1 connection /
mbed_official	114:fe4fe5cfc3a3	771	#define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /!< COMP1 output polarity /
mbed_official	114:fe4fe5cfc3a3	772	#define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /!< COMP1 output level /
mbed_official	114:fe4fe5cfc3a3	773	#define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /!< COMP1 lock /
mbed_official	114:fe4fe5cfc3a3	774	/* COMP2 bits definition */
mbed_official	114:fe4fe5cfc3a3	775	#define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /!< COMP2 enable /
mbed_official	114:fe4fe5cfc3a3	776	#define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /!< COMP2 power mode /
mbed_official	114:fe4fe5cfc3a3	777	#define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /!< COMP2 inverting input select /
mbed_official	114:fe4fe5cfc3a3	778	#define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /!< COMP2 inverting input select bit 0 /
mbed_official	114:fe4fe5cfc3a3	779	#define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /!< COMP2 inverting input select bit 1 /
mbed_official	114:fe4fe5cfc3a3	780	#define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /!< COMP2 inverting input select bit 2 /
mbed_official	114:fe4fe5cfc3a3	781	#define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /!< COMPx non inverting input select /
mbed_official	114:fe4fe5cfc3a3	782	#define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /!< COMPx non inverting input select /
mbed_official	114:fe4fe5cfc3a3	783	#define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /!< COMPx non inverting input select /
mbed_official	114:fe4fe5cfc3a3	784	#define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /!< COMPx non inverting input select /
mbed_official	114:fe4fe5cfc3a3	785	#define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /!< COMP2 LPTIM1 IN2 connection /
mbed_official	114:fe4fe5cfc3a3	786	#define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /!< COMP2 LPTIM1 IN1 connection /
mbed_official	114:fe4fe5cfc3a3	787	#define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /!< COMP2 output polarity /
mbed_official	114:fe4fe5cfc3a3	788	#define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /!< COMP2 output level /
mbed_official	114:fe4fe5cfc3a3	789	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /!< COMP2 lock /
mbed_official	114:fe4fe5cfc3a3	790
mbed_official	114:fe4fe5cfc3a3	791	/******************** Bit definition for COMP_CSR register common **************/
mbed_official	114:fe4fe5cfc3a3	792	#define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /!< COMPx enable /
mbed_official	114:fe4fe5cfc3a3	793	#define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /!< COMPx output polarity /
mbed_official	114:fe4fe5cfc3a3	794	#define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /!< COMPx output level /
mbed_official	114:fe4fe5cfc3a3	795	#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /!< COMPx lock /
mbed_official	114:fe4fe5cfc3a3	796
mbed_official	114:fe4fe5cfc3a3	797	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	798	#define COMP_CSR_WINMODE COMP_CSR_COMP1WM /!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) /
mbed_official	114:fe4fe5cfc3a3	799
mbed_official	114:fe4fe5cfc3a3	800	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	801	/* */
mbed_official	114:fe4fe5cfc3a3	802	/* CRC calculation unit (CRC) */
mbed_official	114:fe4fe5cfc3a3	803	/* */
mbed_official	114:fe4fe5cfc3a3	804	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	805	/***************** Bit definition for CRC_DR register *******************/
mbed_official	114:fe4fe5cfc3a3	806	#define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /!< Data register bits /
mbed_official	114:fe4fe5cfc3a3	807
mbed_official	114:fe4fe5cfc3a3	808	/***************** Bit definition for CRC_IDR register ******************/
mbed_official	114:fe4fe5cfc3a3	809	#define CRC_IDR_IDR ((uint8_t)0xFFU) /!< General-purpose 8-bit data register bits /
mbed_official	114:fe4fe5cfc3a3	810
mbed_official	114:fe4fe5cfc3a3	811	/****************** Bit definition for CRC_CR register ******************/
mbed_official	114:fe4fe5cfc3a3	812	#define CRC_CR_RESET ((uint32_t)0x00000001U) /!< RESET the CRC computation unit bit /
mbed_official	114:fe4fe5cfc3a3	813	#define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /!< Polynomial size bits /
mbed_official	114:fe4fe5cfc3a3	814	#define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /!< Polynomial size bit 0 /
mbed_official	114:fe4fe5cfc3a3	815	#define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /!< Polynomial size bit 1 /
mbed_official	114:fe4fe5cfc3a3	816	#define CRC_CR_REV_IN ((uint32_t)0x00000060U) /!< REV_IN Reverse Input Data bits /
mbed_official	114:fe4fe5cfc3a3	817	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	818	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	819	#define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /!< REV_OUT Reverse Output Data bits /
mbed_official	114:fe4fe5cfc3a3	820
mbed_official	114:fe4fe5cfc3a3	821	/***************** Bit definition for CRC_INIT register *****************/
mbed_official	114:fe4fe5cfc3a3	822	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /!< Initial CRC value bits /
mbed_official	114:fe4fe5cfc3a3	823
mbed_official	114:fe4fe5cfc3a3	824	/***************** Bit definition for CRC_POL register ******************/
mbed_official	114:fe4fe5cfc3a3	825	#define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /!< Coefficients of the polynomial /
mbed_official	114:fe4fe5cfc3a3	826
mbed_official	114:fe4fe5cfc3a3	827	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	828	/* */
mbed_official	114:fe4fe5cfc3a3	829	/* Debug MCU (DBGMCU) */
mbed_official	114:fe4fe5cfc3a3	830	/* */
mbed_official	114:fe4fe5cfc3a3	831	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	832
mbed_official	114:fe4fe5cfc3a3	833	/************** Bit definition for DBGMCU_IDCODE register ***************/
mbed_official	114:fe4fe5cfc3a3	834	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /!< Device Identifier /
mbed_official	114:fe4fe5cfc3a3	835
mbed_official	114:fe4fe5cfc3a3	836	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /!< REV_ID[15:0] bits (Revision Identifier) /
mbed_official	114:fe4fe5cfc3a3	837	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	838	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	839	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	840	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	841	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	842	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /!< Bit 5 /
mbed_official	114:fe4fe5cfc3a3	843	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /!< Bit 6 /
mbed_official	114:fe4fe5cfc3a3	844	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /!< Bit 7 /
mbed_official	114:fe4fe5cfc3a3	845	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /!< Bit 8 /
mbed_official	114:fe4fe5cfc3a3	846	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /!< Bit 9 /
mbed_official	114:fe4fe5cfc3a3	847	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /!< Bit 10 /
mbed_official	114:fe4fe5cfc3a3	848	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /!< Bit 11 /
mbed_official	114:fe4fe5cfc3a3	849	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /!< Bit 12 /
mbed_official	114:fe4fe5cfc3a3	850	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /!< Bit 13 /
mbed_official	114:fe4fe5cfc3a3	851	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /!< Bit 14 /
mbed_official	114:fe4fe5cfc3a3	852	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /!< Bit 15 /
mbed_official	114:fe4fe5cfc3a3	853
mbed_official	114:fe4fe5cfc3a3	854	/**************** Bit definition for DBGMCU_CR register *****************/
mbed_official	114:fe4fe5cfc3a3	855	#define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /!< Debug mode mask /
mbed_official	114:fe4fe5cfc3a3	856	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /!< Debug Sleep Mode /
mbed_official	114:fe4fe5cfc3a3	857	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /!< Debug Stop Mode /
mbed_official	114:fe4fe5cfc3a3	858	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /!< Debug Standby mode /
mbed_official	114:fe4fe5cfc3a3	859
mbed_official	114:fe4fe5cfc3a3	860	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official	114:fe4fe5cfc3a3	861	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /!< TIM2 counter stopped when core is halted /
mbed_official	114:fe4fe5cfc3a3	862	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /!< RTC Calendar frozen when core is halted /
mbed_official	114:fe4fe5cfc3a3	863	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /!< Debug Window Watchdog stopped when Core is halted /
mbed_official	114:fe4fe5cfc3a3	864	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /!< Debug Independent Watchdog stopped when Core is halted /
mbed_official	114:fe4fe5cfc3a3	865	#define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
mbed_official	114:fe4fe5cfc3a3	866	#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /!< LPTIM1 counter stopped when core is halted /
mbed_official	114:fe4fe5cfc3a3	867	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official	114:fe4fe5cfc3a3	868	#define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /!< TIM22 counter stopped when core is halted /
mbed_official	114:fe4fe5cfc3a3	869	#define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /!< TIM21 counter stopped when core is halted /
mbed_official	114:fe4fe5cfc3a3	870
mbed_official	114:fe4fe5cfc3a3	871	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	872	/* */
mbed_official	114:fe4fe5cfc3a3	873	/* DMA Controller (DMA) */
mbed_official	114:fe4fe5cfc3a3	874	/* */
mbed_official	114:fe4fe5cfc3a3	875	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	876
mbed_official	114:fe4fe5cfc3a3	877	/***************** Bit definition for DMA_ISR register ******************/
mbed_official	114:fe4fe5cfc3a3	878	#define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /!< Channel 1 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	879	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /!< Channel 1 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	880	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /!< Channel 1 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	881	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /!< Channel 1 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	882	#define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /!< Channel 2 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	883	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /!< Channel 2 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	884	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /!< Channel 2 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	885	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /!< Channel 2 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	886	#define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /!< Channel 3 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	887	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /!< Channel 3 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	888	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /!< Channel 3 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	889	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /!< Channel 3 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	890	#define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /!< Channel 4 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	891	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /!< Channel 4 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	892	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /!< Channel 4 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	893	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /!< Channel 4 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	894	#define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /!< Channel 5 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	895	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /!< Channel 5 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	896	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /!< Channel 5 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	897	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /!< Channel 5 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	898	#define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /!< Channel 6 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	899	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /!< Channel 6 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	900	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /!< Channel 6 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	901	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /!< Channel 6 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	902	#define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /!< Channel 7 Global interrupt flag /
mbed_official	114:fe4fe5cfc3a3	903	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /!< Channel 7 Transfer Complete flag /
mbed_official	114:fe4fe5cfc3a3	904	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /!< Channel 7 Half Transfer flag /
mbed_official	114:fe4fe5cfc3a3	905	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /!< Channel 7 Transfer Error flag /
mbed_official	114:fe4fe5cfc3a3	906
mbed_official	114:fe4fe5cfc3a3	907	/***************** Bit definition for DMA_IFCR register *****************/
mbed_official	114:fe4fe5cfc3a3	908	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /!< Channel 1 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	909	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /!< Channel 1 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	910	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /!< Channel 1 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	911	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /!< Channel 1 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	912	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /!< Channel 2 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	913	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /!< Channel 2 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	914	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /!< Channel 2 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	915	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /!< Channel 2 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	916	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /!< Channel 3 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	917	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /!< Channel 3 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	918	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /!< Channel 3 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	919	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /!< Channel 3 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	920	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /!< Channel 4 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	921	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /!< Channel 4 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	922	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /!< Channel 4 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	923	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /!< Channel 4 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	924	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /!< Channel 5 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	925	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /!< Channel 5 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	926	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /!< Channel 5 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	927	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /!< Channel 5 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	928	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /!< Channel 6 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	929	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /!< Channel 6 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	930	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /!< Channel 6 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	931	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /!< Channel 6 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	932	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /!< Channel 7 Global interrupt clear /
mbed_official	114:fe4fe5cfc3a3	933	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /!< Channel 7 Transfer Complete clear /
mbed_official	114:fe4fe5cfc3a3	934	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /!< Channel 7 Half Transfer clear /
mbed_official	114:fe4fe5cfc3a3	935	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /!< Channel 7 Transfer Error clear /
mbed_official	114:fe4fe5cfc3a3	936
mbed_official	114:fe4fe5cfc3a3	937	/***************** Bit definition for DMA_CCR register ******************/
mbed_official	114:fe4fe5cfc3a3	938	#define DMA_CCR_EN ((uint32_t)0x00000001U) /!< Channel enable /
mbed_official	114:fe4fe5cfc3a3	939	#define DMA_CCR_TCIE ((uint32_t)0x00000002U) /!< Transfer complete interrupt enable /
mbed_official	114:fe4fe5cfc3a3	940	#define DMA_CCR_HTIE ((uint32_t)0x00000004U) /!< Half Transfer interrupt enable /
mbed_official	114:fe4fe5cfc3a3	941	#define DMA_CCR_TEIE ((uint32_t)0x00000008U) /!< Transfer error interrupt enable /
mbed_official	114:fe4fe5cfc3a3	942	#define DMA_CCR_DIR ((uint32_t)0x00000010U) /!< Data transfer direction /
mbed_official	114:fe4fe5cfc3a3	943	#define DMA_CCR_CIRC ((uint32_t)0x00000020U) /!< Circular mode /
mbed_official	114:fe4fe5cfc3a3	944	#define DMA_CCR_PINC ((uint32_t)0x00000040U) /!< Peripheral increment mode /
mbed_official	114:fe4fe5cfc3a3	945	#define DMA_CCR_MINC ((uint32_t)0x00000080U) /!< Memory increment mode /
mbed_official	114:fe4fe5cfc3a3	946
mbed_official	114:fe4fe5cfc3a3	947	#define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /!< PSIZE[1:0] bits (Peripheral size) /
mbed_official	114:fe4fe5cfc3a3	948	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	949	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	950
mbed_official	114:fe4fe5cfc3a3	951	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /!< MSIZE[1:0] bits (Memory size) /
mbed_official	114:fe4fe5cfc3a3	952	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	953	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	954
mbed_official	114:fe4fe5cfc3a3	955	#define DMA_CCR_PL ((uint32_t)0x00003000U) /!< PL[1:0] bits(Channel Priority level)/
mbed_official	114:fe4fe5cfc3a3	956	#define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	957	#define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	958
mbed_official	114:fe4fe5cfc3a3	959	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /!< Memory to memory mode /
mbed_official	114:fe4fe5cfc3a3	960
mbed_official	114:fe4fe5cfc3a3	961	/**************** Bit definition for DMA_CNDTR register *****************/
mbed_official	114:fe4fe5cfc3a3	962	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /!< Number of data to Transfer /
mbed_official	114:fe4fe5cfc3a3	963
mbed_official	114:fe4fe5cfc3a3	964	/**************** Bit definition for DMA_CPAR register ******************/
mbed_official	114:fe4fe5cfc3a3	965	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /!< Peripheral Address /
mbed_official	114:fe4fe5cfc3a3	966
mbed_official	114:fe4fe5cfc3a3	967	/**************** Bit definition for DMA_CMAR register ******************/
mbed_official	114:fe4fe5cfc3a3	968	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /!< Memory Address /
mbed_official	114:fe4fe5cfc3a3	969
mbed_official	114:fe4fe5cfc3a3	970
mbed_official	114:fe4fe5cfc3a3	971	/***************** Bit definition for DMA_CSELR register *****************/
mbed_official	114:fe4fe5cfc3a3	972	#define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /!< Channel 1 Selection /
mbed_official	114:fe4fe5cfc3a3	973	#define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /!< Channel 2 Selection /
mbed_official	114:fe4fe5cfc3a3	974	#define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /!< Channel 3 Selection /
mbed_official	114:fe4fe5cfc3a3	975	#define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /!< Channel 4 Selection /
mbed_official	114:fe4fe5cfc3a3	976	#define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /!< Channel 5 Selection /
mbed_official	114:fe4fe5cfc3a3	977	#define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /!< Channel 6 Selection /
mbed_official	114:fe4fe5cfc3a3	978	#define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /!< Channel 7 Selection /
mbed_official	114:fe4fe5cfc3a3	979
mbed_official	114:fe4fe5cfc3a3	980
mbed_official	114:fe4fe5cfc3a3	981	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	982	/* */
mbed_official	114:fe4fe5cfc3a3	983	/* External Interrupt/Event Controller (EXTI) */
mbed_official	114:fe4fe5cfc3a3	984	/* */
mbed_official	114:fe4fe5cfc3a3	985	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	986
mbed_official	114:fe4fe5cfc3a3	987	/***************** Bit definition for EXTI_IMR register *****************/
mbed_official	114:fe4fe5cfc3a3	988	#define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /!< Interrupt Mask on line 0 /
mbed_official	114:fe4fe5cfc3a3	989	#define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /!< Interrupt Mask on line 1 /
mbed_official	114:fe4fe5cfc3a3	990	#define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /!< Interrupt Mask on line 2 /
mbed_official	114:fe4fe5cfc3a3	991	#define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /!< Interrupt Mask on line 3 /
mbed_official	114:fe4fe5cfc3a3	992	#define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /!< Interrupt Mask on line 4 /
mbed_official	114:fe4fe5cfc3a3	993	#define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /!< Interrupt Mask on line 5 /
mbed_official	114:fe4fe5cfc3a3	994	#define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /!< Interrupt Mask on line 6 /
mbed_official	114:fe4fe5cfc3a3	995	#define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /!< Interrupt Mask on line 7 /
mbed_official	114:fe4fe5cfc3a3	996	#define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /!< Interrupt Mask on line 8 /
mbed_official	114:fe4fe5cfc3a3	997	#define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /!< Interrupt Mask on line 9 /
mbed_official	114:fe4fe5cfc3a3	998	#define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /!< Interrupt Mask on line 10 /
mbed_official	114:fe4fe5cfc3a3	999	#define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /!< Interrupt Mask on line 11 /
mbed_official	114:fe4fe5cfc3a3	1000	#define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /!< Interrupt Mask on line 12 /
mbed_official	114:fe4fe5cfc3a3	1001	#define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /!< Interrupt Mask on line 13 /
mbed_official	114:fe4fe5cfc3a3	1002	#define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /!< Interrupt Mask on line 14 /
mbed_official	114:fe4fe5cfc3a3	1003	#define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /!< Interrupt Mask on line 15 /
mbed_official	114:fe4fe5cfc3a3	1004	#define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /!< Interrupt Mask on line 16 /
mbed_official	114:fe4fe5cfc3a3	1005	#define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /!< Interrupt Mask on line 17 /
mbed_official	114:fe4fe5cfc3a3	1006	#define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /!< Interrupt Mask on line 18 /
mbed_official	114:fe4fe5cfc3a3	1007	#define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /!< Interrupt Mask on line 19 /
mbed_official	114:fe4fe5cfc3a3	1008	#define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /!< Interrupt Mask on line 20 /
mbed_official	114:fe4fe5cfc3a3	1009	#define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /!< Interrupt Mask on line 21 /
mbed_official	114:fe4fe5cfc3a3	1010	#define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /!< Interrupt Mask on line 22 /
mbed_official	114:fe4fe5cfc3a3	1011	#define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /!< Interrupt Mask on line 23 /
mbed_official	114:fe4fe5cfc3a3	1012	#define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /!< Interrupt Mask on line 25 /
mbed_official	114:fe4fe5cfc3a3	1013	#define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /!< Interrupt Mask on line 26 /
mbed_official	114:fe4fe5cfc3a3	1014	#define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /!< Interrupt Mask on line 28 /
mbed_official	114:fe4fe5cfc3a3	1015	#define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /!< Interrupt Mask on line 29 /
mbed_official	114:fe4fe5cfc3a3	1016
mbed_official	114:fe4fe5cfc3a3	1017	/**************** Bit definition for EXTI_EMR register ******************/
mbed_official	114:fe4fe5cfc3a3	1018	#define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /!< Event Mask on line 0 /
mbed_official	114:fe4fe5cfc3a3	1019	#define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /!< Event Mask on line 1 /
mbed_official	114:fe4fe5cfc3a3	1020	#define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /!< Event Mask on line 2 /
mbed_official	114:fe4fe5cfc3a3	1021	#define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /!< Event Mask on line 3 /
mbed_official	114:fe4fe5cfc3a3	1022	#define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /!< Event Mask on line 4 /
mbed_official	114:fe4fe5cfc3a3	1023	#define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /!< Event Mask on line 5 /
mbed_official	114:fe4fe5cfc3a3	1024	#define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /!< Event Mask on line 6 /
mbed_official	114:fe4fe5cfc3a3	1025	#define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /!< Event Mask on line 7 /
mbed_official	114:fe4fe5cfc3a3	1026	#define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /!< Event Mask on line 8 /
mbed_official	114:fe4fe5cfc3a3	1027	#define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /!< Event Mask on line 9 /
mbed_official	114:fe4fe5cfc3a3	1028	#define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /!< Event Mask on line 10 /
mbed_official	114:fe4fe5cfc3a3	1029	#define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /!< Event Mask on line 11 /
mbed_official	114:fe4fe5cfc3a3	1030	#define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /!< Event Mask on line 12 /
mbed_official	114:fe4fe5cfc3a3	1031	#define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /!< Event Mask on line 13 /
mbed_official	114:fe4fe5cfc3a3	1032	#define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /!< Event Mask on line 14 /
mbed_official	114:fe4fe5cfc3a3	1033	#define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /!< Event Mask on line 15 /
mbed_official	114:fe4fe5cfc3a3	1034	#define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /!< Event Mask on line 16 /
mbed_official	114:fe4fe5cfc3a3	1035	#define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /!< Event Mask on line 17 /
mbed_official	114:fe4fe5cfc3a3	1036	#define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /!< Event Mask on line 18 /
mbed_official	114:fe4fe5cfc3a3	1037	#define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /!< Event Mask on line 19 /
mbed_official	114:fe4fe5cfc3a3	1038	#define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /!< Event Mask on line 20 /
mbed_official	114:fe4fe5cfc3a3	1039	#define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /!< Event Mask on line 21 /
mbed_official	114:fe4fe5cfc3a3	1040	#define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /!< Event Mask on line 22 /
mbed_official	114:fe4fe5cfc3a3	1041	#define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /!< Event Mask on line 23 /
mbed_official	114:fe4fe5cfc3a3	1042	#define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /!< Event Mask on line 25 /
mbed_official	114:fe4fe5cfc3a3	1043	#define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /!< Event Mask on line 26 /
mbed_official	114:fe4fe5cfc3a3	1044	#define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /!< Event Mask on line 28 /
mbed_official	114:fe4fe5cfc3a3	1045	#define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /!< Event Mask on line 29 /
mbed_official	114:fe4fe5cfc3a3	1046
mbed_official	114:fe4fe5cfc3a3	1047	/***************** Bit definition for EXTI_RTSR register ****************/
mbed_official	114:fe4fe5cfc3a3	1048	#define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /!< Rising trigger event configuration bit of line 0 /
mbed_official	114:fe4fe5cfc3a3	1049	#define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /!< Rising trigger event configuration bit of line 1 /
mbed_official	114:fe4fe5cfc3a3	1050	#define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /!< Rising trigger event configuration bit of line 2 /
mbed_official	114:fe4fe5cfc3a3	1051	#define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /!< Rising trigger event configuration bit of line 3 /
mbed_official	114:fe4fe5cfc3a3	1052	#define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /!< Rising trigger event configuration bit of line 4 /
mbed_official	114:fe4fe5cfc3a3	1053	#define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /!< Rising trigger event configuration bit of line 5 /
mbed_official	114:fe4fe5cfc3a3	1054	#define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /!< Rising trigger event configuration bit of line 6 /
mbed_official	114:fe4fe5cfc3a3	1055	#define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /!< Rising trigger event configuration bit of line 7 /
mbed_official	114:fe4fe5cfc3a3	1056	#define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /!< Rising trigger event configuration bit of line 8 /
mbed_official	114:fe4fe5cfc3a3	1057	#define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /!< Rising trigger event configuration bit of line 9 /
mbed_official	114:fe4fe5cfc3a3	1058	#define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /!< Rising trigger event configuration bit of line 10 /
mbed_official	114:fe4fe5cfc3a3	1059	#define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /!< Rising trigger event configuration bit of line 11 /
mbed_official	114:fe4fe5cfc3a3	1060	#define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /!< Rising trigger event configuration bit of line 12 /
mbed_official	114:fe4fe5cfc3a3	1061	#define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /!< Rising trigger event configuration bit of line 13 /
mbed_official	114:fe4fe5cfc3a3	1062	#define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /!< Rising trigger event configuration bit of line 14 /
mbed_official	114:fe4fe5cfc3a3	1063	#define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /!< Rising trigger event configuration bit of line 15 /
mbed_official	114:fe4fe5cfc3a3	1064	#define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /!< Rising trigger event configuration bit of line 16 /
mbed_official	114:fe4fe5cfc3a3	1065	#define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /!< Rising trigger event configuration bit of line 17 /
mbed_official	114:fe4fe5cfc3a3	1066	#define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /!< Rising trigger event configuration bit of line 19 /
mbed_official	114:fe4fe5cfc3a3	1067	#define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /!< Rising trigger event configuration bit of line 20 /
mbed_official	114:fe4fe5cfc3a3	1068	#define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /!< Rising trigger event configuration bit of line 21 /
mbed_official	114:fe4fe5cfc3a3	1069	#define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /!< Rising trigger event configuration bit of line 22 /
mbed_official	114:fe4fe5cfc3a3	1070
mbed_official	114:fe4fe5cfc3a3	1071	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	1072	#define EXTI_RTSR_TR0 EXTI_RTSR_RT0
mbed_official	114:fe4fe5cfc3a3	1073	#define EXTI_RTSR_TR1 EXTI_RTSR_RT1
mbed_official	114:fe4fe5cfc3a3	1074	#define EXTI_RTSR_TR2 EXTI_RTSR_RT2
mbed_official	114:fe4fe5cfc3a3	1075	#define EXTI_RTSR_TR3 EXTI_RTSR_RT3
mbed_official	114:fe4fe5cfc3a3	1076	#define EXTI_RTSR_TR4 EXTI_RTSR_RT4
mbed_official	114:fe4fe5cfc3a3	1077	#define EXTI_RTSR_TR5 EXTI_RTSR_RT5
mbed_official	114:fe4fe5cfc3a3	1078	#define EXTI_RTSR_TR6 EXTI_RTSR_RT6
mbed_official	114:fe4fe5cfc3a3	1079	#define EXTI_RTSR_TR7 EXTI_RTSR_RT7
mbed_official	114:fe4fe5cfc3a3	1080	#define EXTI_RTSR_TR8 EXTI_RTSR_RT8
mbed_official	114:fe4fe5cfc3a3	1081	#define EXTI_RTSR_TR9 EXTI_RTSR_RT9
mbed_official	114:fe4fe5cfc3a3	1082	#define EXTI_RTSR_TR10 EXTI_RTSR_RT10
mbed_official	114:fe4fe5cfc3a3	1083	#define EXTI_RTSR_TR11 EXTI_RTSR_RT11
mbed_official	114:fe4fe5cfc3a3	1084	#define EXTI_RTSR_TR12 EXTI_RTSR_RT12
mbed_official	114:fe4fe5cfc3a3	1085	#define EXTI_RTSR_TR13 EXTI_RTSR_RT13
mbed_official	114:fe4fe5cfc3a3	1086	#define EXTI_RTSR_TR14 EXTI_RTSR_RT14
mbed_official	114:fe4fe5cfc3a3	1087	#define EXTI_RTSR_TR15 EXTI_RTSR_RT15
mbed_official	114:fe4fe5cfc3a3	1088	#define EXTI_RTSR_TR16 EXTI_RTSR_RT16
mbed_official	114:fe4fe5cfc3a3	1089	#define EXTI_RTSR_TR17 EXTI_RTSR_RT17
mbed_official	114:fe4fe5cfc3a3	1090	#define EXTI_RTSR_TR19 EXTI_RTSR_RT19
mbed_official	114:fe4fe5cfc3a3	1091	#define EXTI_RTSR_TR20 EXTI_RTSR_RT20
mbed_official	114:fe4fe5cfc3a3	1092	#define EXTI_RTSR_TR21 EXTI_RTSR_RT21
mbed_official	114:fe4fe5cfc3a3	1093	#define EXTI_RTSR_TR22 EXTI_RTSR_RT22
mbed_official	114:fe4fe5cfc3a3	1094
mbed_official	114:fe4fe5cfc3a3	1095	/***************** Bit definition for EXTI_FTSR register *****************/
mbed_official	114:fe4fe5cfc3a3	1096	#define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /!< Falling trigger event configuration bit of line 0 /
mbed_official	114:fe4fe5cfc3a3	1097	#define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /!< Falling trigger event configuration bit of line 1 /
mbed_official	114:fe4fe5cfc3a3	1098	#define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /!< Falling trigger event configuration bit of line 2 /
mbed_official	114:fe4fe5cfc3a3	1099	#define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /!< Falling trigger event configuration bit of line 3 /
mbed_official	114:fe4fe5cfc3a3	1100	#define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /!< Falling trigger event configuration bit of line 4 /
mbed_official	114:fe4fe5cfc3a3	1101	#define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /!< Falling trigger event configuration bit of line 5 /
mbed_official	114:fe4fe5cfc3a3	1102	#define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /!< Falling trigger event configuration bit of line 6 /
mbed_official	114:fe4fe5cfc3a3	1103	#define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /!< Falling trigger event configuration bit of line 7 /
mbed_official	114:fe4fe5cfc3a3	1104	#define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /!< Falling trigger event configuration bit of line 8 /
mbed_official	114:fe4fe5cfc3a3	1105	#define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /!< Falling trigger event configuration bit of line 9 /
mbed_official	114:fe4fe5cfc3a3	1106	#define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /!< Falling trigger event configuration bit of line 10 /
mbed_official	114:fe4fe5cfc3a3	1107	#define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /!< Falling trigger event configuration bit of line 11 /
mbed_official	114:fe4fe5cfc3a3	1108	#define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /!< Falling trigger event configuration bit of line 12 /
mbed_official	114:fe4fe5cfc3a3	1109	#define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /!< Falling trigger event configuration bit of line 13 /
mbed_official	114:fe4fe5cfc3a3	1110	#define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /!< Falling trigger event configuration bit of line 14 /
mbed_official	114:fe4fe5cfc3a3	1111	#define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /!< Falling trigger event configuration bit of line 15 /
mbed_official	114:fe4fe5cfc3a3	1112	#define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /!< Falling trigger event configuration bit of line 16 /
mbed_official	114:fe4fe5cfc3a3	1113	#define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /!< Falling trigger event configuration bit of line 17 /
mbed_official	114:fe4fe5cfc3a3	1114	#define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /!< Falling trigger event configuration bit of line 19 /
mbed_official	114:fe4fe5cfc3a3	1115	#define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /!< Falling trigger event configuration bit of line 20 /
mbed_official	114:fe4fe5cfc3a3	1116	#define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /!< Falling trigger event configuration bit of line 21 /
mbed_official	114:fe4fe5cfc3a3	1117	#define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /!< Falling trigger event configuration bit of line 22 /
mbed_official	114:fe4fe5cfc3a3	1118
mbed_official	114:fe4fe5cfc3a3	1119	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	1120	#define EXTI_FTSR_TR0 EXTI_FTSR_FT0
mbed_official	114:fe4fe5cfc3a3	1121	#define EXTI_FTSR_TR1 EXTI_FTSR_FT1
mbed_official	114:fe4fe5cfc3a3	1122	#define EXTI_FTSR_TR2 EXTI_FTSR_FT2
mbed_official	114:fe4fe5cfc3a3	1123	#define EXTI_FTSR_TR3 EXTI_FTSR_FT3
mbed_official	114:fe4fe5cfc3a3	1124	#define EXTI_FTSR_TR4 EXTI_FTSR_FT4
mbed_official	114:fe4fe5cfc3a3	1125	#define EXTI_FTSR_TR5 EXTI_FTSR_FT5
mbed_official	114:fe4fe5cfc3a3	1126	#define EXTI_FTSR_TR6 EXTI_FTSR_FT6
mbed_official	114:fe4fe5cfc3a3	1127	#define EXTI_FTSR_TR7 EXTI_FTSR_FT7
mbed_official	114:fe4fe5cfc3a3	1128	#define EXTI_FTSR_TR8 EXTI_FTSR_FT8
mbed_official	114:fe4fe5cfc3a3	1129	#define EXTI_FTSR_TR9 EXTI_FTSR_FT9
mbed_official	114:fe4fe5cfc3a3	1130	#define EXTI_FTSR_TR10 EXTI_FTSR_FT10
mbed_official	114:fe4fe5cfc3a3	1131	#define EXTI_FTSR_TR11 EXTI_FTSR_FT11
mbed_official	114:fe4fe5cfc3a3	1132	#define EXTI_FTSR_TR12 EXTI_FTSR_FT12
mbed_official	114:fe4fe5cfc3a3	1133	#define EXTI_FTSR_TR13 EXTI_FTSR_FT13
mbed_official	114:fe4fe5cfc3a3	1134	#define EXTI_FTSR_TR14 EXTI_FTSR_FT14
mbed_official	114:fe4fe5cfc3a3	1135	#define EXTI_FTSR_TR15 EXTI_FTSR_FT15
mbed_official	114:fe4fe5cfc3a3	1136	#define EXTI_FTSR_TR16 EXTI_FTSR_FT16
mbed_official	114:fe4fe5cfc3a3	1137	#define EXTI_FTSR_TR17 EXTI_FTSR_FT17
mbed_official	114:fe4fe5cfc3a3	1138	#define EXTI_FTSR_TR19 EXTI_FTSR_FT19
mbed_official	114:fe4fe5cfc3a3	1139	#define EXTI_FTSR_TR20 EXTI_FTSR_FT20
mbed_official	114:fe4fe5cfc3a3	1140	#define EXTI_FTSR_TR21 EXTI_FTSR_FT21
mbed_official	114:fe4fe5cfc3a3	1141	#define EXTI_FTSR_TR22 EXTI_FTSR_FT22
mbed_official	114:fe4fe5cfc3a3	1142
mbed_official	114:fe4fe5cfc3a3	1143	/***************** Bit definition for EXTI_SWIER register *****************/
mbed_official	114:fe4fe5cfc3a3	1144	#define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /!< Software Interrupt on line 0 /
mbed_official	114:fe4fe5cfc3a3	1145	#define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /!< Software Interrupt on line 1 /
mbed_official	114:fe4fe5cfc3a3	1146	#define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /!< Software Interrupt on line 2 /
mbed_official	114:fe4fe5cfc3a3	1147	#define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /!< Software Interrupt on line 3 /
mbed_official	114:fe4fe5cfc3a3	1148	#define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /!< Software Interrupt on line 4 /
mbed_official	114:fe4fe5cfc3a3	1149	#define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /!< Software Interrupt on line 5 /
mbed_official	114:fe4fe5cfc3a3	1150	#define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /!< Software Interrupt on line 6 /
mbed_official	114:fe4fe5cfc3a3	1151	#define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /!< Software Interrupt on line 7 /
mbed_official	114:fe4fe5cfc3a3	1152	#define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /!< Software Interrupt on line 8 /
mbed_official	114:fe4fe5cfc3a3	1153	#define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /!< Software Interrupt on line 9 /
mbed_official	114:fe4fe5cfc3a3	1154	#define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /!< Software Interrupt on line 10 /
mbed_official	114:fe4fe5cfc3a3	1155	#define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /!< Software Interrupt on line 11 /
mbed_official	114:fe4fe5cfc3a3	1156	#define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /!< Software Interrupt on line 12 /
mbed_official	114:fe4fe5cfc3a3	1157	#define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /!< Software Interrupt on line 13 /
mbed_official	114:fe4fe5cfc3a3	1158	#define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /!< Software Interrupt on line 14 /
mbed_official	114:fe4fe5cfc3a3	1159	#define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /!< Software Interrupt on line 15 /
mbed_official	114:fe4fe5cfc3a3	1160	#define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /!< Software Interrupt on line 16 /
mbed_official	114:fe4fe5cfc3a3	1161	#define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /!< Software Interrupt on line 17 /
mbed_official	114:fe4fe5cfc3a3	1162	#define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /!< Software Interrupt on line 19 /
mbed_official	114:fe4fe5cfc3a3	1163	#define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /!< Software Interrupt on line 20 /
mbed_official	114:fe4fe5cfc3a3	1164	#define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /!< Software Interrupt on line 21 /
mbed_official	114:fe4fe5cfc3a3	1165	#define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /!< Software Interrupt on line 22 /
mbed_official	114:fe4fe5cfc3a3	1166
mbed_official	114:fe4fe5cfc3a3	1167	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	1168	#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
mbed_official	114:fe4fe5cfc3a3	1169	#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
mbed_official	114:fe4fe5cfc3a3	1170	#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
mbed_official	114:fe4fe5cfc3a3	1171	#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
mbed_official	114:fe4fe5cfc3a3	1172	#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
mbed_official	114:fe4fe5cfc3a3	1173	#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
mbed_official	114:fe4fe5cfc3a3	1174	#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
mbed_official	114:fe4fe5cfc3a3	1175	#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
mbed_official	114:fe4fe5cfc3a3	1176	#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
mbed_official	114:fe4fe5cfc3a3	1177	#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
mbed_official	114:fe4fe5cfc3a3	1178	#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
mbed_official	114:fe4fe5cfc3a3	1179	#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
mbed_official	114:fe4fe5cfc3a3	1180	#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
mbed_official	114:fe4fe5cfc3a3	1181	#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
mbed_official	114:fe4fe5cfc3a3	1182	#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
mbed_official	114:fe4fe5cfc3a3	1183	#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
mbed_official	114:fe4fe5cfc3a3	1184	#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
mbed_official	114:fe4fe5cfc3a3	1185	#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
mbed_official	114:fe4fe5cfc3a3	1186	#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
mbed_official	114:fe4fe5cfc3a3	1187	#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
mbed_official	114:fe4fe5cfc3a3	1188	#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
mbed_official	114:fe4fe5cfc3a3	1189	#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
mbed_official	114:fe4fe5cfc3a3	1190
mbed_official	114:fe4fe5cfc3a3	1191	/**************** Bit definition for EXTI_PR register *******************/
mbed_official	114:fe4fe5cfc3a3	1192	#define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /!< Pending bit 0 /
mbed_official	114:fe4fe5cfc3a3	1193	#define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /!< Pending bit 1 /
mbed_official	114:fe4fe5cfc3a3	1194	#define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /!< Pending bit 2 /
mbed_official	114:fe4fe5cfc3a3	1195	#define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /!< Pending bit 3 /
mbed_official	114:fe4fe5cfc3a3	1196	#define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /!< Pending bit 4 /
mbed_official	114:fe4fe5cfc3a3	1197	#define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /!< Pending bit 5 /
mbed_official	114:fe4fe5cfc3a3	1198	#define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /!< Pending bit 6 /
mbed_official	114:fe4fe5cfc3a3	1199	#define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /!< Pending bit 7 /
mbed_official	114:fe4fe5cfc3a3	1200	#define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /!< Pending bit 8 /
mbed_official	114:fe4fe5cfc3a3	1201	#define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /!< Pending bit 9 /
mbed_official	114:fe4fe5cfc3a3	1202	#define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /!< Pending bit 10 /
mbed_official	114:fe4fe5cfc3a3	1203	#define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /!< Pending bit 11 /
mbed_official	114:fe4fe5cfc3a3	1204	#define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /!< Pending bit 12 /
mbed_official	114:fe4fe5cfc3a3	1205	#define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /!< Pending bit 13 /
mbed_official	114:fe4fe5cfc3a3	1206	#define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /!< Pending bit 14 /
mbed_official	114:fe4fe5cfc3a3	1207	#define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /!< Pending bit 15 /
mbed_official	114:fe4fe5cfc3a3	1208	#define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /!< Pending bit 16 /
mbed_official	114:fe4fe5cfc3a3	1209	#define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /!< Pending bit 17 /
mbed_official	114:fe4fe5cfc3a3	1210	#define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /!< Pending bit 19 /
mbed_official	114:fe4fe5cfc3a3	1211	#define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /!< Pending bit 20 /
mbed_official	114:fe4fe5cfc3a3	1212	#define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /!< Pending bit 21 /
mbed_official	114:fe4fe5cfc3a3	1213	#define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /!< Pending bit 22 /
mbed_official	114:fe4fe5cfc3a3	1214
mbed_official	114:fe4fe5cfc3a3	1215	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	1216	#define EXTI_PR_PR0 EXTI_PR_PIF0
mbed_official	114:fe4fe5cfc3a3	1217	#define EXTI_PR_PR1 EXTI_PR_PIF1
mbed_official	114:fe4fe5cfc3a3	1218	#define EXTI_PR_PR2 EXTI_PR_PIF2
mbed_official	114:fe4fe5cfc3a3	1219	#define EXTI_PR_PR3 EXTI_PR_PIF3
mbed_official	114:fe4fe5cfc3a3	1220	#define EXTI_PR_PR4 EXTI_PR_PIF4
mbed_official	114:fe4fe5cfc3a3	1221	#define EXTI_PR_PR5 EXTI_PR_PIF5
mbed_official	114:fe4fe5cfc3a3	1222	#define EXTI_PR_PR6 EXTI_PR_PIF6
mbed_official	114:fe4fe5cfc3a3	1223	#define EXTI_PR_PR7 EXTI_PR_PIF7
mbed_official	114:fe4fe5cfc3a3	1224	#define EXTI_PR_PR8 EXTI_PR_PIF8
mbed_official	114:fe4fe5cfc3a3	1225	#define EXTI_PR_PR9 EXTI_PR_PIF9
mbed_official	114:fe4fe5cfc3a3	1226	#define EXTI_PR_PR10 EXTI_PR_PIF10
mbed_official	114:fe4fe5cfc3a3	1227	#define EXTI_PR_PR11 EXTI_PR_PIF11
mbed_official	114:fe4fe5cfc3a3	1228	#define EXTI_PR_PR12 EXTI_PR_PIF12
mbed_official	114:fe4fe5cfc3a3	1229	#define EXTI_PR_PR13 EXTI_PR_PIF13
mbed_official	114:fe4fe5cfc3a3	1230	#define EXTI_PR_PR14 EXTI_PR_PIF14
mbed_official	114:fe4fe5cfc3a3	1231	#define EXTI_PR_PR15 EXTI_PR_PIF15
mbed_official	114:fe4fe5cfc3a3	1232	#define EXTI_PR_PR16 EXTI_PR_PIF16
mbed_official	114:fe4fe5cfc3a3	1233	#define EXTI_PR_PR17 EXTI_PR_PIF17
mbed_official	114:fe4fe5cfc3a3	1234	#define EXTI_PR_PR19 EXTI_PR_PIF19
mbed_official	114:fe4fe5cfc3a3	1235	#define EXTI_PR_PR20 EXTI_PR_PIF20
mbed_official	114:fe4fe5cfc3a3	1236	#define EXTI_PR_PR21 EXTI_PR_PIF21
mbed_official	114:fe4fe5cfc3a3	1237	#define EXTI_PR_PR22 EXTI_PR_PIF22
mbed_official	114:fe4fe5cfc3a3	1238
mbed_official	114:fe4fe5cfc3a3	1239	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1240	/* */
mbed_official	114:fe4fe5cfc3a3	1241	/* FLASH and Option Bytes Registers */
mbed_official	114:fe4fe5cfc3a3	1242	/* */
mbed_official	114:fe4fe5cfc3a3	1243	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1244
mbed_official	114:fe4fe5cfc3a3	1245	/***************** Bit definition for FLASH_ACR register ****************/
mbed_official	114:fe4fe5cfc3a3	1246	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /!< LATENCY bit (Latency) /
mbed_official	114:fe4fe5cfc3a3	1247	#define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /!< Prefetch Buffer Enable /
mbed_official	114:fe4fe5cfc3a3	1248	#define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /!< Flash mode during sleep mode /
mbed_official	114:fe4fe5cfc3a3	1249	#define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /!< Flash mode during RUN mode /
mbed_official	114:fe4fe5cfc3a3	1250	#define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /!< Disable Buffer /
mbed_official	114:fe4fe5cfc3a3	1251	#define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /!< Pre-read data address /
mbed_official	114:fe4fe5cfc3a3	1252
mbed_official	114:fe4fe5cfc3a3	1253	/***************** Bit definition for FLASH_PECR register ****************/
mbed_official	114:fe4fe5cfc3a3	1254	#define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /!< FLASH_PECR and Flash data Lock /
mbed_official	114:fe4fe5cfc3a3	1255	#define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /!< Program matrix Lock /
mbed_official	114:fe4fe5cfc3a3	1256	#define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /!< Option byte matrix Lock /
mbed_official	114:fe4fe5cfc3a3	1257	#define FLASH_PECR_PROG ((uint32_t)0x00000008U) /!< Program matrix selection /
mbed_official	114:fe4fe5cfc3a3	1258	#define FLASH_PECR_DATA ((uint32_t)0x00000010U) /!< Data matrix selection /
mbed_official	114:fe4fe5cfc3a3	1259	#define FLASH_PECR_FIX ((uint32_t)0x00000100U) /!< Fixed Time Data write for Word/Half Word/Byte programming /
mbed_official	114:fe4fe5cfc3a3	1260	#define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /!< Page erasing mode /
mbed_official	114:fe4fe5cfc3a3	1261	#define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /!< Fast Page/Half Page programming mode /
mbed_official	114:fe4fe5cfc3a3	1262	#define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /!< End of programming interrupt /
mbed_official	114:fe4fe5cfc3a3	1263	#define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /!< Error interrupt /
mbed_official	114:fe4fe5cfc3a3	1264	#define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /!< Launch the option byte loading /
mbed_official	114:fe4fe5cfc3a3	1265	#define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /!< Half array mode /
mbed_official	114:fe4fe5cfc3a3	1266
mbed_official	114:fe4fe5cfc3a3	1267	/**************** Bit definition for FLASH_PDKEYR register ****************/
mbed_official	114:fe4fe5cfc3a3	1268	#define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /!< FLASH_PEC and data matrix Key /
mbed_official	114:fe4fe5cfc3a3	1269
mbed_official	114:fe4fe5cfc3a3	1270	/**************** Bit definition for FLASH_PEKEYR register ****************/
mbed_official	114:fe4fe5cfc3a3	1271	#define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /!< FLASH_PEC and data matrix Key /
mbed_official	114:fe4fe5cfc3a3	1272
mbed_official	114:fe4fe5cfc3a3	1273	/**************** Bit definition for FLASH_PRGKEYR register ****************/
mbed_official	114:fe4fe5cfc3a3	1274	#define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /!< Program matrix Key /
mbed_official	114:fe4fe5cfc3a3	1275
mbed_official	114:fe4fe5cfc3a3	1276	/**************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official	114:fe4fe5cfc3a3	1277	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /!< Option bytes matrix Key /
mbed_official	114:fe4fe5cfc3a3	1278
mbed_official	114:fe4fe5cfc3a3	1279	/**************** Bit definition for FLASH_SR register *****************/
mbed_official	114:fe4fe5cfc3a3	1280	#define FLASH_SR_BSY ((uint32_t)0x00000001U) /!< Busy /
mbed_official	114:fe4fe5cfc3a3	1281	#define FLASH_SR_EOP ((uint32_t)0x00000002U) /!< End Of Programming/
mbed_official	114:fe4fe5cfc3a3	1282	#define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /!< End of high voltage /
mbed_official	114:fe4fe5cfc3a3	1283	#define FLASH_SR_READY ((uint32_t)0x00000008U) /!< Flash ready after low power mode /
mbed_official	114:fe4fe5cfc3a3	1284
mbed_official	114:fe4fe5cfc3a3	1285	#define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /!< Write protection error /
mbed_official	114:fe4fe5cfc3a3	1286	#define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /!< Programming Alignment Error /
mbed_official	114:fe4fe5cfc3a3	1287	#define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /!< Size error /
mbed_official	114:fe4fe5cfc3a3	1288	#define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /!< Option Valid error /
mbed_official	114:fe4fe5cfc3a3	1289	#define FLASH_SR_RDERR ((uint32_t)0x00002000U) /!< Read protected error /
mbed_official	114:fe4fe5cfc3a3	1290	#define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /!< Not Zero error /
mbed_official	114:fe4fe5cfc3a3	1291	#define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /!< Write/Errase operation aborted /
mbed_official	114:fe4fe5cfc3a3	1292
mbed_official	114:fe4fe5cfc3a3	1293	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	1294	#define FLASH_SR_FWWER FLASH_SR_FWWERR
mbed_official	114:fe4fe5cfc3a3	1295	#define FLASH_SR_ENHV FLASH_SR_HVOFF
mbed_official	114:fe4fe5cfc3a3	1296	#define FLASH_SR_ENDHV FLASH_SR_HVOFF
mbed_official	114:fe4fe5cfc3a3	1297
mbed_official	114:fe4fe5cfc3a3	1298	/**************** Bit definition for FLASH_OPTR register *****************/
mbed_official	114:fe4fe5cfc3a3	1299	#define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /!< Read Protection /
mbed_official	114:fe4fe5cfc3a3	1300	#define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /!< Selection of protection mode of WPR bits /
mbed_official	114:fe4fe5cfc3a3	1301	#define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /!< BOR_LEV[3:0] Brown Out Reset Threshold Level/
mbed_official	114:fe4fe5cfc3a3	1302	#define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /!< IWDG_SW /
mbed_official	114:fe4fe5cfc3a3	1303	#define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /!< nRST_STOP /
mbed_official	114:fe4fe5cfc3a3	1304	#define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /!< nRST_STDBY /
mbed_official	114:fe4fe5cfc3a3	1305	#define FLASH_OPTR_USER ((uint32_t)0x00700000U) /!< User Option Bytes /
mbed_official	114:fe4fe5cfc3a3	1306	#define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /!< BOOT1 /
mbed_official	114:fe4fe5cfc3a3	1307
mbed_official	114:fe4fe5cfc3a3	1308	/**************** Bit definition for FLASH_WRPR register ****************/
mbed_official	114:fe4fe5cfc3a3	1309	#define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /!< Write Protection bits /
mbed_official	114:fe4fe5cfc3a3	1310
mbed_official	114:fe4fe5cfc3a3	1311	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1312	/* */
mbed_official	114:fe4fe5cfc3a3	1313	/* General Purpose IOs (GPIO) */
mbed_official	114:fe4fe5cfc3a3	1314	/* */
mbed_official	114:fe4fe5cfc3a3	1315	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1316	/***************** Bit definition for GPIO_MODER register ***************/
mbed_official	114:fe4fe5cfc3a3	1317	#define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
mbed_official	114:fe4fe5cfc3a3	1318	#define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1319	#define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1320	#define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
mbed_official	114:fe4fe5cfc3a3	1321	#define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1322	#define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1323	#define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
mbed_official	114:fe4fe5cfc3a3	1324	#define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1325	#define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1326	#define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
mbed_official	114:fe4fe5cfc3a3	1327	#define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1328	#define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1329	#define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
mbed_official	114:fe4fe5cfc3a3	1330	#define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1331	#define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1332	#define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
mbed_official	114:fe4fe5cfc3a3	1333	#define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1334	#define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1335	#define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
mbed_official	114:fe4fe5cfc3a3	1336	#define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1337	#define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1338	#define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
mbed_official	114:fe4fe5cfc3a3	1339	#define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1340	#define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1341	#define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
mbed_official	114:fe4fe5cfc3a3	1342	#define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
mbed_official	114:fe4fe5cfc3a3	1343	#define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
mbed_official	114:fe4fe5cfc3a3	1344	#define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
mbed_official	114:fe4fe5cfc3a3	1345	#define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
mbed_official	114:fe4fe5cfc3a3	1346	#define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
mbed_official	114:fe4fe5cfc3a3	1347	#define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
mbed_official	114:fe4fe5cfc3a3	1348	#define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
mbed_official	114:fe4fe5cfc3a3	1349	#define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
mbed_official	114:fe4fe5cfc3a3	1350	#define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
mbed_official	114:fe4fe5cfc3a3	1351	#define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
mbed_official	114:fe4fe5cfc3a3	1352	#define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
mbed_official	114:fe4fe5cfc3a3	1353	#define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
mbed_official	114:fe4fe5cfc3a3	1354	#define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	1355	#define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	1356	#define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
mbed_official	114:fe4fe5cfc3a3	1357	#define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	1358	#define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	1359	#define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
mbed_official	114:fe4fe5cfc3a3	1360	#define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
mbed_official	114:fe4fe5cfc3a3	1361	#define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
mbed_official	114:fe4fe5cfc3a3	1362	#define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
mbed_official	114:fe4fe5cfc3a3	1363	#define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
mbed_official	114:fe4fe5cfc3a3	1364	#define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
mbed_official	114:fe4fe5cfc3a3	1365
mbed_official	114:fe4fe5cfc3a3	1366	/**************** Bit definition for GPIO_OTYPER register ***************/
mbed_official	114:fe4fe5cfc3a3	1367	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1368	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1369	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1370	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1371	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1372	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1373	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1374	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1375	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1376	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1377	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1378	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1379	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1380	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1381	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1382	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1383
mbed_official	114:fe4fe5cfc3a3	1384	/************** Bit definition for GPIO_OSPEEDR register ****************/
mbed_official	114:fe4fe5cfc3a3	1385	#define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
mbed_official	114:fe4fe5cfc3a3	1386	#define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1387	#define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1388	#define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
mbed_official	114:fe4fe5cfc3a3	1389	#define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1390	#define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1391	#define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
mbed_official	114:fe4fe5cfc3a3	1392	#define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1393	#define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1394	#define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
mbed_official	114:fe4fe5cfc3a3	1395	#define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1396	#define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1397	#define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
mbed_official	114:fe4fe5cfc3a3	1398	#define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1399	#define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1400	#define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
mbed_official	114:fe4fe5cfc3a3	1401	#define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1402	#define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1403	#define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
mbed_official	114:fe4fe5cfc3a3	1404	#define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1405	#define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1406	#define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
mbed_official	114:fe4fe5cfc3a3	1407	#define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1408	#define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1409	#define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
mbed_official	114:fe4fe5cfc3a3	1410	#define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
mbed_official	114:fe4fe5cfc3a3	1411	#define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
mbed_official	114:fe4fe5cfc3a3	1412	#define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
mbed_official	114:fe4fe5cfc3a3	1413	#define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
mbed_official	114:fe4fe5cfc3a3	1414	#define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
mbed_official	114:fe4fe5cfc3a3	1415	#define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
mbed_official	114:fe4fe5cfc3a3	1416	#define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
mbed_official	114:fe4fe5cfc3a3	1417	#define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
mbed_official	114:fe4fe5cfc3a3	1418	#define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
mbed_official	114:fe4fe5cfc3a3	1419	#define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
mbed_official	114:fe4fe5cfc3a3	1420	#define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
mbed_official	114:fe4fe5cfc3a3	1421	#define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
mbed_official	114:fe4fe5cfc3a3	1422	#define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	1423	#define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	1424	#define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
mbed_official	114:fe4fe5cfc3a3	1425	#define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	1426	#define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	1427	#define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
mbed_official	114:fe4fe5cfc3a3	1428	#define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
mbed_official	114:fe4fe5cfc3a3	1429	#define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
mbed_official	114:fe4fe5cfc3a3	1430	#define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
mbed_official	114:fe4fe5cfc3a3	1431	#define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
mbed_official	114:fe4fe5cfc3a3	1432	#define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
mbed_official	114:fe4fe5cfc3a3	1433
mbed_official	114:fe4fe5cfc3a3	1434	/***************** Bit definition for GPIO_PUPDR register ****************/
mbed_official	114:fe4fe5cfc3a3	1435	#define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
mbed_official	114:fe4fe5cfc3a3	1436	#define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1437	#define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1438	#define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
mbed_official	114:fe4fe5cfc3a3	1439	#define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1440	#define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1441	#define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
mbed_official	114:fe4fe5cfc3a3	1442	#define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1443	#define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1444	#define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
mbed_official	114:fe4fe5cfc3a3	1445	#define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1446	#define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1447	#define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
mbed_official	114:fe4fe5cfc3a3	1448	#define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1449	#define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1450	#define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
mbed_official	114:fe4fe5cfc3a3	1451	#define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1452	#define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1453	#define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
mbed_official	114:fe4fe5cfc3a3	1454	#define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1455	#define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1456	#define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
mbed_official	114:fe4fe5cfc3a3	1457	#define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1458	#define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1459	#define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
mbed_official	114:fe4fe5cfc3a3	1460	#define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
mbed_official	114:fe4fe5cfc3a3	1461	#define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
mbed_official	114:fe4fe5cfc3a3	1462	#define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
mbed_official	114:fe4fe5cfc3a3	1463	#define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
mbed_official	114:fe4fe5cfc3a3	1464	#define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
mbed_official	114:fe4fe5cfc3a3	1465	#define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
mbed_official	114:fe4fe5cfc3a3	1466	#define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
mbed_official	114:fe4fe5cfc3a3	1467	#define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
mbed_official	114:fe4fe5cfc3a3	1468	#define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
mbed_official	114:fe4fe5cfc3a3	1469	#define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
mbed_official	114:fe4fe5cfc3a3	1470	#define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
mbed_official	114:fe4fe5cfc3a3	1471	#define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
mbed_official	114:fe4fe5cfc3a3	1472	#define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	1473	#define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	1474	#define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
mbed_official	114:fe4fe5cfc3a3	1475	#define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	1476	#define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	1477	#define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
mbed_official	114:fe4fe5cfc3a3	1478	#define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
mbed_official	114:fe4fe5cfc3a3	1479	#define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
mbed_official	114:fe4fe5cfc3a3	1480	#define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
mbed_official	114:fe4fe5cfc3a3	1481	#define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
mbed_official	114:fe4fe5cfc3a3	1482	#define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
mbed_official	114:fe4fe5cfc3a3	1483
mbed_official	114:fe4fe5cfc3a3	1484	/***************** Bit definition for GPIO_IDR register *****************/
mbed_official	114:fe4fe5cfc3a3	1485	#define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1486	#define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1487	#define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1488	#define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1489	#define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1490	#define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1491	#define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1492	#define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1493	#define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1494	#define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1495	#define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1496	#define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1497	#define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1498	#define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1499	#define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1500	#define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1501
mbed_official	114:fe4fe5cfc3a3	1502	/**************** Bit definition for GPIO_ODR register ******************/
mbed_official	114:fe4fe5cfc3a3	1503	#define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1504	#define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1505	#define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1506	#define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1507	#define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1508	#define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1509	#define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1510	#define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1511	#define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1512	#define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1513	#define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1514	#define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1515	#define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1516	#define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1517	#define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1518	#define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1519
mbed_official	114:fe4fe5cfc3a3	1520	/**************** Bit definition for GPIO_BSRR register ******************/
mbed_official	114:fe4fe5cfc3a3	1521	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1522	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1523	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1524	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1525	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1526	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1527	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1528	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1529	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1530	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1531	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1532	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1533	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1534	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1535	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1536	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1537	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
mbed_official	114:fe4fe5cfc3a3	1538	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
mbed_official	114:fe4fe5cfc3a3	1539	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
mbed_official	114:fe4fe5cfc3a3	1540	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
mbed_official	114:fe4fe5cfc3a3	1541	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
mbed_official	114:fe4fe5cfc3a3	1542	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
mbed_official	114:fe4fe5cfc3a3	1543	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
mbed_official	114:fe4fe5cfc3a3	1544	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
mbed_official	114:fe4fe5cfc3a3	1545	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	1546	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	1547	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	1548	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	1549	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
mbed_official	114:fe4fe5cfc3a3	1550	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
mbed_official	114:fe4fe5cfc3a3	1551	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
mbed_official	114:fe4fe5cfc3a3	1552	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
mbed_official	114:fe4fe5cfc3a3	1553
mbed_official	114:fe4fe5cfc3a3	1554	/**************** Bit definition for GPIO_LCKR register ******************/
mbed_official	114:fe4fe5cfc3a3	1555	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1556	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1557	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1558	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1559	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1560	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1561	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1562	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1563	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1564	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1565	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1566	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1567	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1568	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1569	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1570	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1571	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
mbed_official	114:fe4fe5cfc3a3	1572
mbed_official	114:fe4fe5cfc3a3	1573	/**************** Bit definition for GPIO_AFRL register ******************/
mbed_official	114:fe4fe5cfc3a3	1574	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
mbed_official	114:fe4fe5cfc3a3	1575	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
mbed_official	114:fe4fe5cfc3a3	1576	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
mbed_official	114:fe4fe5cfc3a3	1577	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
mbed_official	114:fe4fe5cfc3a3	1578	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
mbed_official	114:fe4fe5cfc3a3	1579	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
mbed_official	114:fe4fe5cfc3a3	1580	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
mbed_official	114:fe4fe5cfc3a3	1581	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
mbed_official	114:fe4fe5cfc3a3	1582
mbed_official	114:fe4fe5cfc3a3	1583	/**************** Bit definition for GPIO_AFRH register ******************/
mbed_official	114:fe4fe5cfc3a3	1584	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
mbed_official	114:fe4fe5cfc3a3	1585	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
mbed_official	114:fe4fe5cfc3a3	1586	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
mbed_official	114:fe4fe5cfc3a3	1587	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
mbed_official	114:fe4fe5cfc3a3	1588	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
mbed_official	114:fe4fe5cfc3a3	1589	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
mbed_official	114:fe4fe5cfc3a3	1590	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
mbed_official	114:fe4fe5cfc3a3	1591	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
mbed_official	114:fe4fe5cfc3a3	1592
mbed_official	114:fe4fe5cfc3a3	1593	/**************** Bit definition for GPIO_BRR register *******************/
mbed_official	114:fe4fe5cfc3a3	1594	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
mbed_official	114:fe4fe5cfc3a3	1595	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
mbed_official	114:fe4fe5cfc3a3	1596	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
mbed_official	114:fe4fe5cfc3a3	1597	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
mbed_official	114:fe4fe5cfc3a3	1598	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
mbed_official	114:fe4fe5cfc3a3	1599	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
mbed_official	114:fe4fe5cfc3a3	1600	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
mbed_official	114:fe4fe5cfc3a3	1601	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
mbed_official	114:fe4fe5cfc3a3	1602	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
mbed_official	114:fe4fe5cfc3a3	1603	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
mbed_official	114:fe4fe5cfc3a3	1604	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
mbed_official	114:fe4fe5cfc3a3	1605	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
mbed_official	114:fe4fe5cfc3a3	1606	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
mbed_official	114:fe4fe5cfc3a3	1607	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
mbed_official	114:fe4fe5cfc3a3	1608	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
mbed_official	114:fe4fe5cfc3a3	1609	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
mbed_official	114:fe4fe5cfc3a3	1610
mbed_official	114:fe4fe5cfc3a3	1611	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1612	/* */
mbed_official	114:fe4fe5cfc3a3	1613	/* Inter-integrated Circuit Interface (I2C) */
mbed_official	114:fe4fe5cfc3a3	1614	/* */
mbed_official	114:fe4fe5cfc3a3	1615	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1616
mbed_official	114:fe4fe5cfc3a3	1617	/***************** Bit definition for I2C_CR1 register *****************/
mbed_official	114:fe4fe5cfc3a3	1618	#define I2C_CR1_PE ((uint32_t)0x00000001U) /!< Peripheral enable /
mbed_official	114:fe4fe5cfc3a3	1619	#define I2C_CR1_TXIE ((uint32_t)0x00000002U) /!< TX interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1620	#define I2C_CR1_RXIE ((uint32_t)0x00000004U) /!< RX interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1621	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /!< Address match interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1622	#define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /!< NACK received interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1623	#define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /!< STOP detection interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1624	#define I2C_CR1_TCIE ((uint32_t)0x00000040U) /!< Transfer complete interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1625	#define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /!< Errors interrupt enable /
mbed_official	114:fe4fe5cfc3a3	1626	#define I2C_CR1_DNF ((uint32_t)0x00000F00U) /!< Digital noise filter /
mbed_official	114:fe4fe5cfc3a3	1627	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /!< Analog noise filter OFF /
mbed_official	114:fe4fe5cfc3a3	1628	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /!< DMA transmission requests enable /
mbed_official	114:fe4fe5cfc3a3	1629	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /!< DMA reception requests enable /
mbed_official	114:fe4fe5cfc3a3	1630	#define I2C_CR1_SBC ((uint32_t)0x00010000U) /!< Slave byte control /
mbed_official	114:fe4fe5cfc3a3	1631	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /!< Clock stretching disable /
mbed_official	114:fe4fe5cfc3a3	1632	#define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /!< Wakeup from STOP enable /
mbed_official	114:fe4fe5cfc3a3	1633	#define I2C_CR1_GCEN ((uint32_t)0x00080000U) /!< General call enable /
mbed_official	114:fe4fe5cfc3a3	1634	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /!< SMBus host address enable /
mbed_official	114:fe4fe5cfc3a3	1635	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /!< SMBus device default address enable /
mbed_official	114:fe4fe5cfc3a3	1636	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /!< SMBus alert enable /
mbed_official	114:fe4fe5cfc3a3	1637	#define I2C_CR1_PECEN ((uint32_t)0x00800000U) /!< PEC enable /
mbed_official	114:fe4fe5cfc3a3	1638
mbed_official	114:fe4fe5cfc3a3	1639	/**************** Bit definition for I2C_CR2 register ******************/
mbed_official	114:fe4fe5cfc3a3	1640	#define I2C_CR2_SADD ((uint32_t)0x000003FFU) /!< Slave address (master mode) /
mbed_official	114:fe4fe5cfc3a3	1641	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /!< Transfer direction (master mode) /
mbed_official	114:fe4fe5cfc3a3	1642	#define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /!< 10-bit addressing mode (master mode) /
mbed_official	114:fe4fe5cfc3a3	1643	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /!< 10-bit address header only read direction (master mode) /
mbed_official	114:fe4fe5cfc3a3	1644	#define I2C_CR2_START ((uint32_t)0x00002000U) /!< START generation /
mbed_official	114:fe4fe5cfc3a3	1645	#define I2C_CR2_STOP ((uint32_t)0x00004000U) /!< STOP generation (master mode) /
mbed_official	114:fe4fe5cfc3a3	1646	#define I2C_CR2_NACK ((uint32_t)0x00008000U) /!< NACK generation (slave mode) /
mbed_official	114:fe4fe5cfc3a3	1647	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /!< Number of bytes /
mbed_official	114:fe4fe5cfc3a3	1648	#define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /!< NBYTES reload mode /
mbed_official	114:fe4fe5cfc3a3	1649	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /!< Automatic end mode (master mode) /
mbed_official	114:fe4fe5cfc3a3	1650	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /!< Packet error checking byte /
mbed_official	114:fe4fe5cfc3a3	1651
mbed_official	114:fe4fe5cfc3a3	1652	/***************** Bit definition for I2C_OAR1 register ****************/
mbed_official	114:fe4fe5cfc3a3	1653	#define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /!< Interface own address 1 /
mbed_official	114:fe4fe5cfc3a3	1654	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /!< Own address 1 10-bit mode /
mbed_official	114:fe4fe5cfc3a3	1655	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /!< Own address 1 enable /
mbed_official	114:fe4fe5cfc3a3	1656
mbed_official	114:fe4fe5cfc3a3	1657	/***************** Bit definition for I2C_OAR2 register ****************/
mbed_official	114:fe4fe5cfc3a3	1658	#define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /!< Interface own address 2 /
mbed_official	114:fe4fe5cfc3a3	1659	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /!< Own address 2 masks /
mbed_official	114:fe4fe5cfc3a3	1660	#define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /!< No mask /
mbed_official	114:fe4fe5cfc3a3	1661	#define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /!< OA2[1] is masked, Only OA2[7:2] are compared /
mbed_official	114:fe4fe5cfc3a3	1662	#define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
mbed_official	114:fe4fe5cfc3a3	1663	#define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
mbed_official	114:fe4fe5cfc3a3	1664	#define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
mbed_official	114:fe4fe5cfc3a3	1665	#define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
mbed_official	114:fe4fe5cfc3a3	1666	#define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /!< OA2[6:1] is masked, Only OA2[7] are compared /
mbed_official	114:fe4fe5cfc3a3	1667	#define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /!< OA2[7:1] is masked, No comparison is done /
mbed_official	114:fe4fe5cfc3a3	1668	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /!< Own address 2 enable /
mbed_official	114:fe4fe5cfc3a3	1669
mbed_official	114:fe4fe5cfc3a3	1670	/***************** Bit definition for I2C_TIMINGR register *****************/
mbed_official	114:fe4fe5cfc3a3	1671	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /!< SCL low period (master mode) /
mbed_official	114:fe4fe5cfc3a3	1672	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /!< SCL high period (master mode) /
mbed_official	114:fe4fe5cfc3a3	1673	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /!< Data hold time /
mbed_official	114:fe4fe5cfc3a3	1674	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /!< Data setup time /
mbed_official	114:fe4fe5cfc3a3	1675	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /!< Timings prescaler /
mbed_official	114:fe4fe5cfc3a3	1676
mbed_official	114:fe4fe5cfc3a3	1677	/***************** Bit definition for I2C_TIMEOUTR register *****************/
mbed_official	114:fe4fe5cfc3a3	1678	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /!< Bus timeout A /
mbed_official	114:fe4fe5cfc3a3	1679	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /!< Idle clock timeout detection /
mbed_official	114:fe4fe5cfc3a3	1680	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /!< Clock timeout enable /
mbed_official	114:fe4fe5cfc3a3	1681	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /!< Bus timeout B/
mbed_official	114:fe4fe5cfc3a3	1682	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /!< Extended clock timeout enable /
mbed_official	114:fe4fe5cfc3a3	1683
mbed_official	114:fe4fe5cfc3a3	1684	/**************** Bit definition for I2C_ISR register *******************/
mbed_official	114:fe4fe5cfc3a3	1685	#define I2C_ISR_TXE ((uint32_t)0x00000001U) /!< Transmit data register empty /
mbed_official	114:fe4fe5cfc3a3	1686	#define I2C_ISR_TXIS ((uint32_t)0x00000002U) /!< Transmit interrupt status /
mbed_official	114:fe4fe5cfc3a3	1687	#define I2C_ISR_RXNE ((uint32_t)0x00000004U) /!< Receive data register not empty /
mbed_official	114:fe4fe5cfc3a3	1688	#define I2C_ISR_ADDR ((uint32_t)0x00000008U) /!< Address matched (slave mode)/
mbed_official	114:fe4fe5cfc3a3	1689	#define I2C_ISR_NACKF ((uint32_t)0x00000010U) /!< NACK received flag /
mbed_official	114:fe4fe5cfc3a3	1690	#define I2C_ISR_STOPF ((uint32_t)0x00000020U) /!< STOP detection flag /
mbed_official	114:fe4fe5cfc3a3	1691	#define I2C_ISR_TC ((uint32_t)0x00000040U) /!< Transfer complete (master mode) /
mbed_official	114:fe4fe5cfc3a3	1692	#define I2C_ISR_TCR ((uint32_t)0x00000080U) /!< Transfer complete reload /
mbed_official	114:fe4fe5cfc3a3	1693	#define I2C_ISR_BERR ((uint32_t)0x00000100U) /!< Bus error /
mbed_official	114:fe4fe5cfc3a3	1694	#define I2C_ISR_ARLO ((uint32_t)0x00000200U) /!< Arbitration lost /
mbed_official	114:fe4fe5cfc3a3	1695	#define I2C_ISR_OVR ((uint32_t)0x00000400U) /!< Overrun/Underrun /
mbed_official	114:fe4fe5cfc3a3	1696	#define I2C_ISR_PECERR ((uint32_t)0x00000800U) /!< PEC error in reception /
mbed_official	114:fe4fe5cfc3a3	1697	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /!< Timeout or Tlow detection flag /
mbed_official	114:fe4fe5cfc3a3	1698	#define I2C_ISR_ALERT ((uint32_t)0x00002000U) /!< SMBus alert /
mbed_official	114:fe4fe5cfc3a3	1699	#define I2C_ISR_BUSY ((uint32_t)0x00008000U) /!< Bus busy /
mbed_official	114:fe4fe5cfc3a3	1700	#define I2C_ISR_DIR ((uint32_t)0x00010000U) /!< Transfer direction (slave mode) /
mbed_official	114:fe4fe5cfc3a3	1701	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /!< Address match code (slave mode) /
mbed_official	114:fe4fe5cfc3a3	1702
mbed_official	114:fe4fe5cfc3a3	1703	/**************** Bit definition for I2C_ICR register *******************/
mbed_official	114:fe4fe5cfc3a3	1704	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /!< Address matched clear flag /
mbed_official	114:fe4fe5cfc3a3	1705	#define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /!< NACK clear flag /
mbed_official	114:fe4fe5cfc3a3	1706	#define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /!< STOP detection clear flag /
mbed_official	114:fe4fe5cfc3a3	1707	#define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /!< Bus error clear flag /
mbed_official	114:fe4fe5cfc3a3	1708	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /!< Arbitration lost clear flag /
mbed_official	114:fe4fe5cfc3a3	1709	#define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /!< Overrun/Underrun clear flag /
mbed_official	114:fe4fe5cfc3a3	1710	#define I2C_ICR_PECCF ((uint32_t)0x00000800U) /!< PAC error clear flag /
mbed_official	114:fe4fe5cfc3a3	1711	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /!< Timeout clear flag /
mbed_official	114:fe4fe5cfc3a3	1712	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /!< Alert clear flag /
mbed_official	114:fe4fe5cfc3a3	1713
mbed_official	114:fe4fe5cfc3a3	1714	/**************** Bit definition for I2C_PECR register *******************/
mbed_official	114:fe4fe5cfc3a3	1715	#define I2C_PECR_PEC ((uint32_t)0x000000FFU) /!< PEC register /
mbed_official	114:fe4fe5cfc3a3	1716
mbed_official	114:fe4fe5cfc3a3	1717	/**************** Bit definition for I2C_RXDR register *******************/
mbed_official	114:fe4fe5cfc3a3	1718	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /!< 8-bit receive data /
mbed_official	114:fe4fe5cfc3a3	1719
mbed_official	114:fe4fe5cfc3a3	1720	/**************** Bit definition for I2C_TXDR register *******************/
mbed_official	114:fe4fe5cfc3a3	1721	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /!< 8-bit transmit data /
mbed_official	114:fe4fe5cfc3a3	1722
mbed_official	114:fe4fe5cfc3a3	1723	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1724	/* */
mbed_official	114:fe4fe5cfc3a3	1725	/* Independent WATCHDOG (IWDG) */
mbed_official	114:fe4fe5cfc3a3	1726	/* */
mbed_official	114:fe4fe5cfc3a3	1727	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1728	/***************** Bit definition for IWDG_KR register ******************/
mbed_official	114:fe4fe5cfc3a3	1729	#define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /!< Key value (write only, read 0000h) /
mbed_official	114:fe4fe5cfc3a3	1730
mbed_official	114:fe4fe5cfc3a3	1731	/***************** Bit definition for IWDG_PR register ******************/
mbed_official	114:fe4fe5cfc3a3	1732	#define IWDG_PR_PR ((uint32_t)0x00000007U) /!< PR[2:0] (Prescaler divider) /
mbed_official	114:fe4fe5cfc3a3	1733	#define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1734	#define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1735	#define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1736
mbed_official	114:fe4fe5cfc3a3	1737	/***************** Bit definition for IWDG_RLR register *****************/
mbed_official	114:fe4fe5cfc3a3	1738	#define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /!< Watchdog counter reload value /
mbed_official	114:fe4fe5cfc3a3	1739
mbed_official	114:fe4fe5cfc3a3	1740	/***************** Bit definition for IWDG_SR register ******************/
mbed_official	114:fe4fe5cfc3a3	1741	#define IWDG_SR_PVU ((uint32_t)0x00000001U) /!< Watchdog prescaler value update /
mbed_official	114:fe4fe5cfc3a3	1742	#define IWDG_SR_RVU ((uint32_t)0x00000002U) /!< Watchdog counter reload value update /
mbed_official	114:fe4fe5cfc3a3	1743	#define IWDG_SR_WVU ((uint32_t)0x00000004U) /!< Watchdog counter window value update /
mbed_official	114:fe4fe5cfc3a3	1744
mbed_official	114:fe4fe5cfc3a3	1745	/***************** Bit definition for IWDG_KR register ******************/
mbed_official	114:fe4fe5cfc3a3	1746	#define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /!< Watchdog counter window value /
mbed_official	114:fe4fe5cfc3a3	1747
mbed_official	114:fe4fe5cfc3a3	1748	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1749	/* */
mbed_official	114:fe4fe5cfc3a3	1750	/* Low Power Timer (LPTTIM) */
mbed_official	114:fe4fe5cfc3a3	1751	/* */
mbed_official	114:fe4fe5cfc3a3	1752	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1753	/**************** Bit definition for LPTIM_ISR register *****************/
mbed_official	114:fe4fe5cfc3a3	1754	#define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /!< Compare match /
mbed_official	114:fe4fe5cfc3a3	1755	#define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /!< Autoreload match /
mbed_official	114:fe4fe5cfc3a3	1756	#define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /!< External trigger edge event /
mbed_official	114:fe4fe5cfc3a3	1757	#define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /!< Compare register update OK /
mbed_official	114:fe4fe5cfc3a3	1758	#define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /!< Autoreload register update OK /
mbed_official	114:fe4fe5cfc3a3	1759	#define LPTIM_ISR_UP ((uint32_t)0x00000020U) /!< Counter direction change down to up /
mbed_official	114:fe4fe5cfc3a3	1760	#define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /!< Counter direction change up to down /
mbed_official	114:fe4fe5cfc3a3	1761
mbed_official	114:fe4fe5cfc3a3	1762	/**************** Bit definition for LPTIM_ICR register *****************/
mbed_official	114:fe4fe5cfc3a3	1763	#define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /!< Compare match Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1764	#define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /!< Autoreload match Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1765	#define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /!< External trigger edge event Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1766	#define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /!< Compare register update OK Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1767	#define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /!< Autoreload register update OK Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1768	#define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /!< Counter direction change down to up Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1769	#define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /!< Counter direction change up to down Clear Flag /
mbed_official	114:fe4fe5cfc3a3	1770
mbed_official	114:fe4fe5cfc3a3	1771	/**************** Bit definition for LPTIM_IER register ******************/
mbed_official	114:fe4fe5cfc3a3	1772	#define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /!< Compare match Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1773	#define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /!< Autoreload match Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1774	#define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /!< External trigger edge event Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1775	#define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /!< Compare register update OK Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1776	#define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /!< Autoreload register update OK Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1777	#define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /!< Counter direction change down to up Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1778	#define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /!< Counter direction change up to down Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	1779
mbed_official	114:fe4fe5cfc3a3	1780	/**************** Bit definition for LPTIM_CFGR register *****************/
mbed_official	114:fe4fe5cfc3a3	1781	#define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /!< Clock selector /
mbed_official	114:fe4fe5cfc3a3	1782
mbed_official	114:fe4fe5cfc3a3	1783	#define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /!< CKPOL[1:0] bits (Clock polarity) /
mbed_official	114:fe4fe5cfc3a3	1784	#define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1785	#define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1786
mbed_official	114:fe4fe5cfc3a3	1787	#define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
mbed_official	114:fe4fe5cfc3a3	1788	#define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1789	#define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1790
mbed_official	114:fe4fe5cfc3a3	1791	#define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
mbed_official	114:fe4fe5cfc3a3	1792	#define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1793	#define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1794
mbed_official	114:fe4fe5cfc3a3	1795	#define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /!< PRESC[2:0] bits (Clock prescaler) /
mbed_official	114:fe4fe5cfc3a3	1796	#define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1797	#define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1798	#define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1799
mbed_official	114:fe4fe5cfc3a3	1800	#define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /!< TRIGSEL[2:0]] bits (Trigger selector) /
mbed_official	114:fe4fe5cfc3a3	1801	#define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1802	#define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1803	#define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1804
mbed_official	114:fe4fe5cfc3a3	1805	#define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
mbed_official	114:fe4fe5cfc3a3	1806	#define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1807	#define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1808
mbed_official	114:fe4fe5cfc3a3	1809	#define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /!< Timout enable /
mbed_official	114:fe4fe5cfc3a3	1810	#define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /!< Waveform shape /
mbed_official	114:fe4fe5cfc3a3	1811	#define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /!< Waveform shape polarity /
mbed_official	114:fe4fe5cfc3a3	1812	#define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /!< Reg update mode /
mbed_official	114:fe4fe5cfc3a3	1813	#define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /!< Counter mode enable /
mbed_official	114:fe4fe5cfc3a3	1814	#define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /!< Encoder mode enable /
mbed_official	114:fe4fe5cfc3a3	1815
mbed_official	114:fe4fe5cfc3a3	1816	/**************** Bit definition for LPTIM_CR register ******************/
mbed_official	114:fe4fe5cfc3a3	1817	#define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /!< LPTIMer enable /
mbed_official	114:fe4fe5cfc3a3	1818	#define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /!< Timer start in single mode /
mbed_official	114:fe4fe5cfc3a3	1819	#define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /!< Timer start in continuous mode /
mbed_official	114:fe4fe5cfc3a3	1820
mbed_official	114:fe4fe5cfc3a3	1821	/**************** Bit definition for LPTIM_CMP register *****************/
mbed_official	114:fe4fe5cfc3a3	1822	#define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /!< Compare register /
mbed_official	114:fe4fe5cfc3a3	1823
mbed_official	114:fe4fe5cfc3a3	1824	/**************** Bit definition for LPTIM_ARR register *****************/
mbed_official	114:fe4fe5cfc3a3	1825	#define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /!< Auto reload register /
mbed_official	114:fe4fe5cfc3a3	1826
mbed_official	114:fe4fe5cfc3a3	1827	/**************** Bit definition for LPTIM_CNT register *****************/
mbed_official	114:fe4fe5cfc3a3	1828	#define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /!< Counter register /
mbed_official	114:fe4fe5cfc3a3	1829
mbed_official	114:fe4fe5cfc3a3	1830	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1831	/* */
mbed_official	114:fe4fe5cfc3a3	1832	/* Power Control (PWR) */
mbed_official	114:fe4fe5cfc3a3	1833	/* */
mbed_official	114:fe4fe5cfc3a3	1834	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1835
mbed_official	114:fe4fe5cfc3a3	1836	/****************** Bit definition for PWR_CR register ******************/
mbed_official	114:fe4fe5cfc3a3	1837	#define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /!< Low-power deepsleep/sleep/low power run /
mbed_official	114:fe4fe5cfc3a3	1838	#define PWR_CR_PDDS ((uint32_t)0x00000002U) /!< Power Down Deepsleep /
mbed_official	114:fe4fe5cfc3a3	1839	#define PWR_CR_CWUF ((uint32_t)0x00000004U) /!< Clear Wakeup Flag /
mbed_official	114:fe4fe5cfc3a3	1840	#define PWR_CR_CSBF ((uint32_t)0x00000008U) /!< Clear Standby Flag /
mbed_official	114:fe4fe5cfc3a3	1841	#define PWR_CR_PVDE ((uint32_t)0x00000010U) /!< Power Voltage Detector Enable /
mbed_official	114:fe4fe5cfc3a3	1842
mbed_official	114:fe4fe5cfc3a3	1843	#define PWR_CR_PLS ((uint32_t)0x000000E0U) /!< PLS[2:0] bits (PVD Level Selection) /
mbed_official	114:fe4fe5cfc3a3	1844	#define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1845	#define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1846	#define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1847
mbed_official	114:fe4fe5cfc3a3	1848	/!< PVD level configuration /
mbed_official	114:fe4fe5cfc3a3	1849	#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /!< PVD level 0 /
mbed_official	114:fe4fe5cfc3a3	1850	#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /!< PVD level 1 /
mbed_official	114:fe4fe5cfc3a3	1851	#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /!< PVD level 2 /
mbed_official	114:fe4fe5cfc3a3	1852	#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /!< PVD level 3 /
mbed_official	114:fe4fe5cfc3a3	1853	#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /!< PVD level 4 /
mbed_official	114:fe4fe5cfc3a3	1854	#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /!< PVD level 5 /
mbed_official	114:fe4fe5cfc3a3	1855	#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /!< PVD level 6 /
mbed_official	114:fe4fe5cfc3a3	1856	#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /!< PVD level 7 /
mbed_official	114:fe4fe5cfc3a3	1857
mbed_official	114:fe4fe5cfc3a3	1858	#define PWR_CR_DBP ((uint32_t)0x00000100U) /!< Disable Backup Domain write protection /
mbed_official	114:fe4fe5cfc3a3	1859	#define PWR_CR_ULP ((uint32_t)0x00000200U) /!< Ultra Low Power mode /
mbed_official	114:fe4fe5cfc3a3	1860	#define PWR_CR_FWU ((uint32_t)0x00000400U) /!< Fast wakeup /
mbed_official	114:fe4fe5cfc3a3	1861
mbed_official	114:fe4fe5cfc3a3	1862	#define PWR_CR_VOS ((uint32_t)0x00001800U) /!< VOS[1:0] bits (Voltage scaling range selection) /
mbed_official	114:fe4fe5cfc3a3	1863	#define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1864	#define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1865	#define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /!< Deep Sleep mode with EEPROM kept Off /
mbed_official	114:fe4fe5cfc3a3	1866	#define PWR_CR_LPRUN ((uint32_t)0x00004000U) /!< Low power run mode /
mbed_official	114:fe4fe5cfc3a3	1867
mbed_official	114:fe4fe5cfc3a3	1868	/***************** Bit definition for PWR_CSR register ******************/
mbed_official	114:fe4fe5cfc3a3	1869	#define PWR_CSR_WUF ((uint32_t)0x00000001U) /!< Wakeup Flag /
mbed_official	114:fe4fe5cfc3a3	1870	#define PWR_CSR_SBF ((uint32_t)0x00000002U) /!< Standby Flag /
mbed_official	114:fe4fe5cfc3a3	1871	#define PWR_CSR_PVDO ((uint32_t)0x00000004U) /!< PVD Output /
mbed_official	114:fe4fe5cfc3a3	1872	#define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /!< Internal voltage reference (VREFINT) ready flag /
mbed_official	114:fe4fe5cfc3a3	1873	#define PWR_CSR_VOSF ((uint32_t)0x00000010U) /!< Voltage Scaling select flag /
mbed_official	114:fe4fe5cfc3a3	1874	#define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /!< Regulator LP flag /
mbed_official	114:fe4fe5cfc3a3	1875
mbed_official	114:fe4fe5cfc3a3	1876	#define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /!< Enable WKUP pin 1 /
mbed_official	114:fe4fe5cfc3a3	1877	#define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /!< Enable WKUP pin 2 /
mbed_official	114:fe4fe5cfc3a3	1878	#define PWR_CSR_EWUP3 ((uint32_t)0x00000400U) /!< Enable WKUP pin 3 /
mbed_official	114:fe4fe5cfc3a3	1879
mbed_official	114:fe4fe5cfc3a3	1880	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1881	/* */
mbed_official	114:fe4fe5cfc3a3	1882	/* Reset and Clock Control */
mbed_official	114:fe4fe5cfc3a3	1883	/* */
mbed_official	114:fe4fe5cfc3a3	1884	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	1885
mbed_official	114:fe4fe5cfc3a3	1886	/****************** Bit definition for RCC_CR register ******************/
mbed_official	114:fe4fe5cfc3a3	1887	#define RCC_CR_HSION ((uint32_t)0x00000001U) /!< Internal High Speed clock enable /
mbed_official	114:fe4fe5cfc3a3	1888	#define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /!< Internal High Speed clock enable for some IPs Kernel /
mbed_official	114:fe4fe5cfc3a3	1889	#define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /!< Internal High Speed clock ready flag /
mbed_official	114:fe4fe5cfc3a3	1890	#define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /!< Internal High Speed clock divider enable /
mbed_official	114:fe4fe5cfc3a3	1891	#define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /!< Internal High Speed clock divider flag /
mbed_official	114:fe4fe5cfc3a3	1892	#define RCC_CR_HSIOUTEN ((uint32_t)0x00000020U) /!< Internal High Speed clock out enable /
mbed_official	114:fe4fe5cfc3a3	1893	#define RCC_CR_MSION ((uint32_t)0x00000100U) /!< Internal Multi Speed clock enable /
mbed_official	114:fe4fe5cfc3a3	1894	#define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /!< Internal Multi Speed clock ready flag /
mbed_official	114:fe4fe5cfc3a3	1895	#define RCC_CR_HSEON ((uint32_t)0x00010000U) /!< External High Speed clock enable /
mbed_official	114:fe4fe5cfc3a3	1896	#define RCC_CR_HSERDY ((uint32_t)0x00020000U) /!< External High Speed clock ready flag /
mbed_official	114:fe4fe5cfc3a3	1897	#define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /!< External High Speed clock Bypass /
mbed_official	114:fe4fe5cfc3a3	1898	#define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /!< HSE Clock Security System enable /
mbed_official	114:fe4fe5cfc3a3	1899	#define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /!< RTC prescaler [1:0] bits /
mbed_official	114:fe4fe5cfc3a3	1900	#define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /!< RTC prescaler Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1901	#define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /!< RTC prescaler Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1902	#define RCC_CR_PLLON ((uint32_t)0x01000000U) /!< PLL enable /
mbed_official	114:fe4fe5cfc3a3	1903	#define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /!< PLL clock ready flag /
mbed_official	114:fe4fe5cfc3a3	1904
mbed_official	114:fe4fe5cfc3a3	1905	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	1906	#define RCC_CR_CSSON RCC_CR_CSSHSEON
mbed_official	114:fe4fe5cfc3a3	1907
mbed_official	114:fe4fe5cfc3a3	1908	/****************** Bit definition for RCC_ICSCR register ***************/
mbed_official	114:fe4fe5cfc3a3	1909	#define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /!< Internal High Speed clock Calibration /
mbed_official	114:fe4fe5cfc3a3	1910	#define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /!< Internal High Speed clock trimming /
mbed_official	114:fe4fe5cfc3a3	1911
mbed_official	114:fe4fe5cfc3a3	1912	#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /!< Internal Multi Speed clock Range /
mbed_official	114:fe4fe5cfc3a3	1913	#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /!< Internal Multi Speed clock Range 65.536 KHz /
mbed_official	114:fe4fe5cfc3a3	1914	#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /!< Internal Multi Speed clock Range 131.072 KHz /
mbed_official	114:fe4fe5cfc3a3	1915	#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /!< Internal Multi Speed clock Range 262.144 KHz /
mbed_official	114:fe4fe5cfc3a3	1916	#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /!< Internal Multi Speed clock Range 524.288 KHz /
mbed_official	114:fe4fe5cfc3a3	1917	#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /!< Internal Multi Speed clock Range 1.048 MHz /
mbed_official	114:fe4fe5cfc3a3	1918	#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /!< Internal Multi Speed clock Range 2.097 MHz /
mbed_official	114:fe4fe5cfc3a3	1919	#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /!< Internal Multi Speed clock Range 4.194 MHz /
mbed_official	114:fe4fe5cfc3a3	1920	#define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /!< Internal Multi Speed clock Calibration /
mbed_official	114:fe4fe5cfc3a3	1921	#define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /!< Internal Multi Speed clock trimming /
mbed_official	114:fe4fe5cfc3a3	1922
mbed_official	114:fe4fe5cfc3a3	1923
mbed_official	114:fe4fe5cfc3a3	1924	/***************** Bit definition for RCC_CFGR register *****************/
mbed_official	114:fe4fe5cfc3a3	1925	/!< SW configuration /
mbed_official	114:fe4fe5cfc3a3	1926	#define RCC_CFGR_SW ((uint32_t)0x00000003U) /!< SW[1:0] bits (System clock Switch) /
mbed_official	114:fe4fe5cfc3a3	1927	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1928	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1929
mbed_official	114:fe4fe5cfc3a3	1930	#define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /!< MSI selected as system clock /
mbed_official	114:fe4fe5cfc3a3	1931	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /!< HSI selected as system clock /
mbed_official	114:fe4fe5cfc3a3	1932	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /!< HSE selected as system clock /
mbed_official	114:fe4fe5cfc3a3	1933	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /!< PLL selected as system clock /
mbed_official	114:fe4fe5cfc3a3	1934
mbed_official	114:fe4fe5cfc3a3	1935	/!< SWS configuration /
mbed_official	114:fe4fe5cfc3a3	1936	#define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /!< SWS[1:0] bits (System Clock Switch Status) /
mbed_official	114:fe4fe5cfc3a3	1937	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1938	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1939
mbed_official	114:fe4fe5cfc3a3	1940	#define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /!< MSI oscillator used as system clock /
mbed_official	114:fe4fe5cfc3a3	1941	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /!< HSI oscillator used as system clock /
mbed_official	114:fe4fe5cfc3a3	1942	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /!< HSE oscillator used as system clock /
mbed_official	114:fe4fe5cfc3a3	1943	#define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /!< PLL used as system clock /
mbed_official	114:fe4fe5cfc3a3	1944
mbed_official	114:fe4fe5cfc3a3	1945	/!< HPRE configuration /
mbed_official	114:fe4fe5cfc3a3	1946	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /!< HPRE[3:0] bits (AHB prescaler) /
mbed_official	114:fe4fe5cfc3a3	1947	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1948	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1949	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1950	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	1951
mbed_official	114:fe4fe5cfc3a3	1952	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /!< SYSCLK not divided /
mbed_official	114:fe4fe5cfc3a3	1953	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /!< SYSCLK divided by 2 /
mbed_official	114:fe4fe5cfc3a3	1954	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /!< SYSCLK divided by 4 /
mbed_official	114:fe4fe5cfc3a3	1955	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /!< SYSCLK divided by 8 /
mbed_official	114:fe4fe5cfc3a3	1956	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /!< SYSCLK divided by 16 /
mbed_official	114:fe4fe5cfc3a3	1957	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /!< SYSCLK divided by 64 /
mbed_official	114:fe4fe5cfc3a3	1958	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /!< SYSCLK divided by 128 /
mbed_official	114:fe4fe5cfc3a3	1959	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /!< SYSCLK divided by 256 /
mbed_official	114:fe4fe5cfc3a3	1960	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /!< SYSCLK divided by 512 /
mbed_official	114:fe4fe5cfc3a3	1961
mbed_official	114:fe4fe5cfc3a3	1962	/!< PPRE1 configuration /
mbed_official	114:fe4fe5cfc3a3	1963	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /!< PRE1[2:0] bits (APB1 prescaler) /
mbed_official	114:fe4fe5cfc3a3	1964	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1965	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1966	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1967
mbed_official	114:fe4fe5cfc3a3	1968	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /!< HCLK not divided /
mbed_official	114:fe4fe5cfc3a3	1969	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /!< HCLK divided by 2 /
mbed_official	114:fe4fe5cfc3a3	1970	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /!< HCLK divided by 4 /
mbed_official	114:fe4fe5cfc3a3	1971	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /!< HCLK divided by 8 /
mbed_official	114:fe4fe5cfc3a3	1972	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /!< HCLK divided by 16 /
mbed_official	114:fe4fe5cfc3a3	1973
mbed_official	114:fe4fe5cfc3a3	1974	/!< PPRE2 configuration /
mbed_official	114:fe4fe5cfc3a3	1975	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /!< PRE2[2:0] bits (APB2 prescaler) /
mbed_official	114:fe4fe5cfc3a3	1976	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1977	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1978	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	1979
mbed_official	114:fe4fe5cfc3a3	1980	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /!< HCLK not divided /
mbed_official	114:fe4fe5cfc3a3	1981	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /!< HCLK divided by 2 /
mbed_official	114:fe4fe5cfc3a3	1982	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /!< HCLK divided by 4 /
mbed_official	114:fe4fe5cfc3a3	1983	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /!< HCLK divided by 8 /
mbed_official	114:fe4fe5cfc3a3	1984	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /!< HCLK divided by 16 /
mbed_official	114:fe4fe5cfc3a3	1985
mbed_official	114:fe4fe5cfc3a3	1986	#define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /!< Wake Up from Stop Clock selection /
mbed_official	114:fe4fe5cfc3a3	1987
mbed_official	114:fe4fe5cfc3a3	1988	/!< PLL entry clock source/
mbed_official	114:fe4fe5cfc3a3	1989	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /!< PLL entry clock source /
mbed_official	114:fe4fe5cfc3a3	1990
mbed_official	114:fe4fe5cfc3a3	1991	#define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /!< HSI as PLL entry clock source /
mbed_official	114:fe4fe5cfc3a3	1992	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /!< HSE as PLL entry clock source /
mbed_official	114:fe4fe5cfc3a3	1993
mbed_official	114:fe4fe5cfc3a3	1994
mbed_official	114:fe4fe5cfc3a3	1995	/!< PLLMUL configuration /
mbed_official	114:fe4fe5cfc3a3	1996	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
mbed_official	114:fe4fe5cfc3a3	1997	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	1998	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	1999	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2000	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	2001
mbed_official	114:fe4fe5cfc3a3	2002	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /!< PLL input clock 3 */
mbed_official	114:fe4fe5cfc3a3	2003	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /!< PLL input clock 4 */
mbed_official	114:fe4fe5cfc3a3	2004	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /!< PLL input clock 6 */
mbed_official	114:fe4fe5cfc3a3	2005	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /!< PLL input clock 8 */
mbed_official	114:fe4fe5cfc3a3	2006	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /!< PLL input clock 12 */
mbed_official	114:fe4fe5cfc3a3	2007	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /!< PLL input clock 16 */
mbed_official	114:fe4fe5cfc3a3	2008	#define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /!< PLL input clock 24 */
mbed_official	114:fe4fe5cfc3a3	2009	#define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /!< PLL input clock 32 */
mbed_official	114:fe4fe5cfc3a3	2010	#define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /!< PLL input clock 48 */
mbed_official	114:fe4fe5cfc3a3	2011
mbed_official	114:fe4fe5cfc3a3	2012	/!< PLLDIV configuration /
mbed_official	114:fe4fe5cfc3a3	2013	#define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /!< PLLDIV[1:0] bits (PLL Output Division) /
mbed_official	114:fe4fe5cfc3a3	2014	#define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /!< Bit0 /
mbed_official	114:fe4fe5cfc3a3	2015	#define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /!< Bit1 /
mbed_official	114:fe4fe5cfc3a3	2016
mbed_official	114:fe4fe5cfc3a3	2017	#define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /!< PLL clock output = CKVCO / 2 /
mbed_official	114:fe4fe5cfc3a3	2018	#define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /!< PLL clock output = CKVCO / 3 /
mbed_official	114:fe4fe5cfc3a3	2019	#define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /!< PLL clock output = CKVCO / 4 /
mbed_official	114:fe4fe5cfc3a3	2020
mbed_official	114:fe4fe5cfc3a3	2021	/!< MCO configuration /
mbed_official	114:fe4fe5cfc3a3	2022	#define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /!< MCO[3:0] bits (Microcontroller Clock Output) /
mbed_official	114:fe4fe5cfc3a3	2023	#define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2024	#define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2025	#define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2026	#define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	2027
mbed_official	114:fe4fe5cfc3a3	2028	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /!< No clock /
mbed_official	114:fe4fe5cfc3a3	2029	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /!< System clock selected as MCO source /
mbed_official	114:fe4fe5cfc3a3	2030	#define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /!< Internal 16 MHz RC oscillator clock selected /
mbed_official	114:fe4fe5cfc3a3	2031	#define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /!< Internal Medium Speed RC oscillator clock selected /
mbed_official	114:fe4fe5cfc3a3	2032	#define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /!< External 1-25 MHz oscillator clock selected /
mbed_official	114:fe4fe5cfc3a3	2033	#define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /!< PLL clock divided /
mbed_official	114:fe4fe5cfc3a3	2034	#define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /!< LSI selected /
mbed_official	114:fe4fe5cfc3a3	2035	#define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /!< LSE selected /
mbed_official	114:fe4fe5cfc3a3	2036
mbed_official	114:fe4fe5cfc3a3	2037	#define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /!< MCO prescaler /
mbed_official	114:fe4fe5cfc3a3	2038	#define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /!< MCO is divided by 2 /
mbed_official	114:fe4fe5cfc3a3	2039	#define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /!< MCO is divided by 4 /
mbed_official	114:fe4fe5cfc3a3	2040	#define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /!< MCO is divided by 8 /
mbed_official	114:fe4fe5cfc3a3	2041
mbed_official	114:fe4fe5cfc3a3	2042	#define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2043	#define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /!< MCO is divided by 2 /
mbed_official	114:fe4fe5cfc3a3	2044	#define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /!< MCO is divided by 4 /
mbed_official	114:fe4fe5cfc3a3	2045	#define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /!< MCO is divided by 8 /
mbed_official	114:fe4fe5cfc3a3	2046	#define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /!< MCO is divided by 16 /
mbed_official	114:fe4fe5cfc3a3	2047
mbed_official	114:fe4fe5cfc3a3	2048	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	2049	#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /!< MCO prescaler /
mbed_official	114:fe4fe5cfc3a3	2050	#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2051	#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2052	#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2053	#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2054	#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO is divided by 1 /
mbed_official	114:fe4fe5cfc3a3	2055
mbed_official	114:fe4fe5cfc3a3	2056	/!<*************** Bit definition for RCC_CIER register ******************/
mbed_official	114:fe4fe5cfc3a3	2057	#define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /!< LSI Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2058	#define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /!< LSE Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2059	#define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /!< HSI Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2060	#define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /!< HSE Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2061	#define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /!< PLL Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2062	#define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /!< MSI Ready Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2063	#define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /!< LSE CSS Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2064
mbed_official	114:fe4fe5cfc3a3	2065	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2066	#define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
mbed_official	114:fe4fe5cfc3a3	2067
mbed_official	114:fe4fe5cfc3a3	2068	/!<*************** Bit definition for RCC_CIFR register ******************/
mbed_official	114:fe4fe5cfc3a3	2069	#define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /!< LSI Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2070	#define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /!< LSE Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2071	#define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /!< HSI Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2072	#define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /!< HSE Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2073	#define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /!< PLL Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2074	#define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /!< MSI Ready Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2075	#define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /!< LSE Clock Security System Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2076	#define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /!< HSE Clock Security System Interrupt flag /
mbed_official	114:fe4fe5cfc3a3	2077
mbed_official	114:fe4fe5cfc3a3	2078	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2079	#define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
mbed_official	114:fe4fe5cfc3a3	2080	#define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
mbed_official	114:fe4fe5cfc3a3	2081
mbed_official	114:fe4fe5cfc3a3	2082	/!<*************** Bit definition for RCC_CICR register ******************/
mbed_official	114:fe4fe5cfc3a3	2083	#define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /!< LSI Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2084	#define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /!< LSE Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2085	#define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /!< HSI Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2086	#define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /!< HSE Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2087	#define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /!< PLL Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2088	#define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /!< MSI Ready Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2089	#define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /!< LSE Clock Security System Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2090	#define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /!< HSE Clock Security System Interrupt Clear /
mbed_official	114:fe4fe5cfc3a3	2091
mbed_official	114:fe4fe5cfc3a3	2092	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2093	#define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
mbed_official	114:fe4fe5cfc3a3	2094	#define RCC_CICR_CSSC RCC_CICR_CSSHSEC
mbed_official	114:fe4fe5cfc3a3	2095	/*************** Bit definition for RCC_IOPRSTR register ****************/
mbed_official	114:fe4fe5cfc3a3	2096	#define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /!< GPIO port A reset /
mbed_official	114:fe4fe5cfc3a3	2097	#define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /!< GPIO port B reset /
mbed_official	114:fe4fe5cfc3a3	2098	#define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /!< GPIO port C reset /
mbed_official	114:fe4fe5cfc3a3	2099	#define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /!< GPIO port H reset /
mbed_official	114:fe4fe5cfc3a3	2100
mbed_official	114:fe4fe5cfc3a3	2101	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2102	#define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /!< GPIO port A reset /
mbed_official	114:fe4fe5cfc3a3	2103	#define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /!< GPIO port B reset /
mbed_official	114:fe4fe5cfc3a3	2104	#define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /!< GPIO port C reset /
mbed_official	114:fe4fe5cfc3a3	2105	#define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /!< GPIO port H reset /
mbed_official	114:fe4fe5cfc3a3	2106
mbed_official	114:fe4fe5cfc3a3	2107
mbed_official	114:fe4fe5cfc3a3	2108	/**************** Bit definition for RCC_AHBRST register ****************/
mbed_official	114:fe4fe5cfc3a3	2109	#define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /!< DMA1 reset /
mbed_official	114:fe4fe5cfc3a3	2110	#define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /!< Memory interface reset reset /
mbed_official	114:fe4fe5cfc3a3	2111	#define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /!< CRC reset /
mbed_official	114:fe4fe5cfc3a3	2112
mbed_official	114:fe4fe5cfc3a3	2113	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2114	#define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /!< DMA1 reset /
mbed_official	114:fe4fe5cfc3a3	2115
mbed_official	114:fe4fe5cfc3a3	2116	/*************** Bit definition for RCC_APB2RSTR register ***************/
mbed_official	114:fe4fe5cfc3a3	2117	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /!< SYSCFG clock reset /
mbed_official	114:fe4fe5cfc3a3	2118	#define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /!< TIM21 clock reset /
mbed_official	114:fe4fe5cfc3a3	2119	#define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /!< TIM22 clock reset /
mbed_official	114:fe4fe5cfc3a3	2120	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /!< ADC1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2121	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /!< SPI1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2122	#define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /!< DBGMCU clock reset /
mbed_official	114:fe4fe5cfc3a3	2123
mbed_official	114:fe4fe5cfc3a3	2124	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2125	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /!< ADC1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2126	#define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /!< DBGMCU clock reset /
mbed_official	114:fe4fe5cfc3a3	2127
mbed_official	114:fe4fe5cfc3a3	2128	/*************** Bit definition for RCC_APB1RSTR register ***************/
mbed_official	114:fe4fe5cfc3a3	2129	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /!< Timer 2 clock reset /
mbed_official	114:fe4fe5cfc3a3	2130	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /!< Window Watchdog clock reset /
mbed_official	114:fe4fe5cfc3a3	2131	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /!< USART 2 clock reset /
mbed_official	114:fe4fe5cfc3a3	2132	#define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /!< LPUART1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2133	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /!< I2C 1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2134	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /!< PWR clock reset /
mbed_official	114:fe4fe5cfc3a3	2135	#define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /!< LPTIM1 clock reset /
mbed_official	114:fe4fe5cfc3a3	2136
mbed_official	114:fe4fe5cfc3a3	2137	/*************** Bit definition for RCC_IOPENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2138	#define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /!< GPIO port A clock enable /
mbed_official	114:fe4fe5cfc3a3	2139	#define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /!< GPIO port B clock enable /
mbed_official	114:fe4fe5cfc3a3	2140	#define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /!< GPIO port C clock enable /
mbed_official	114:fe4fe5cfc3a3	2141	#define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /!< GPIO port H clock enable /
mbed_official	114:fe4fe5cfc3a3	2142
mbed_official	114:fe4fe5cfc3a3	2143	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2144	#define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /!< GPIO port A clock enable /
mbed_official	114:fe4fe5cfc3a3	2145	#define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /!< GPIO port B clock enable /
mbed_official	114:fe4fe5cfc3a3	2146	#define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /!< GPIO port C clock enable /
mbed_official	114:fe4fe5cfc3a3	2147	#define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /!< GPIO port H clock enable /
mbed_official	114:fe4fe5cfc3a3	2148
mbed_official	114:fe4fe5cfc3a3	2149	/*************** Bit definition for RCC_AHBENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2150	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /!< DMA1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2151	#define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /!< NVM interface clock enable bit /
mbed_official	114:fe4fe5cfc3a3	2152	#define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /!< CRC clock enable /
mbed_official	114:fe4fe5cfc3a3	2153
mbed_official	114:fe4fe5cfc3a3	2154	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2155	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2156
mbed_official	114:fe4fe5cfc3a3	2157	/*************** Bit definition for RCC_APB2ENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2158	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /!< SYSCFG clock enable /
mbed_official	114:fe4fe5cfc3a3	2159	#define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /!< TIM21 clock enable /
mbed_official	114:fe4fe5cfc3a3	2160	#define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /!< TIM22 clock enable /
mbed_official	114:fe4fe5cfc3a3	2161	#define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /!< MiFare Firewall clock enable /
mbed_official	114:fe4fe5cfc3a3	2162	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /!< ADC1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2163	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /!< SPI1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2164	#define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /!< DBGMCU clock enable /
mbed_official	114:fe4fe5cfc3a3	2165
mbed_official	114:fe4fe5cfc3a3	2166	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2167
mbed_official	114:fe4fe5cfc3a3	2168	#define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /!< MiFare Firewall clock enable /
mbed_official	114:fe4fe5cfc3a3	2169	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2170	#define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /!< DBGMCU clock enable /
mbed_official	114:fe4fe5cfc3a3	2171
mbed_official	114:fe4fe5cfc3a3	2172	/*************** Bit definition for RCC_APB1ENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2173	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /!< Timer 2 clock enable /
mbed_official	114:fe4fe5cfc3a3	2174	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /!< Window Watchdog clock enable /
mbed_official	114:fe4fe5cfc3a3	2175	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /!< USART2 clock enable /
mbed_official	114:fe4fe5cfc3a3	2176	#define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /!< LPUART1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2177	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /!< I2C1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2178	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /!< PWR clock enable /
mbed_official	114:fe4fe5cfc3a3	2179	#define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /!< LPTIM1 clock enable /
mbed_official	114:fe4fe5cfc3a3	2180
mbed_official	114:fe4fe5cfc3a3	2181	/**************** Bit definition for RCC_IOPSMENR register **************/
mbed_official	114:fe4fe5cfc3a3	2182	#define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /!< GPIO port A clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2183	#define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /!< GPIO port B clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2184	#define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /!< GPIO port C clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2185	#define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /!< GPIO port H clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2186
mbed_official	114:fe4fe5cfc3a3	2187	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2188	#define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /!< GPIO port A clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2189	#define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /!< GPIO port B clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2190	#define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /!< GPIO port C clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2191	#define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /!< GPIO port H clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2192
mbed_official	114:fe4fe5cfc3a3	2193	/*************** Bit definition for RCC_AHBSMENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2194	#define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /!< DMA1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2195	#define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /!< NVM interface clock enable during sleep mode /
mbed_official	114:fe4fe5cfc3a3	2196	#define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /!< SRAM clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2197	#define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /!< CRC clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2198
mbed_official	114:fe4fe5cfc3a3	2199	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2200	#define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /!< DMA1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2201
mbed_official	114:fe4fe5cfc3a3	2202	/*************** Bit definition for RCC_APB2SMENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2203	#define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /!< SYSCFG clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2204	#define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /!< TIM21 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2205	#define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /!< TIM22 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2206	#define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /!< ADC1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2207	#define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /!< SPI1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2208	#define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /!< DBGMCU clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2209
mbed_official	114:fe4fe5cfc3a3	2210	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2211	#define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /!< ADC1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2212	#define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /!< DBGMCU clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2213
mbed_official	114:fe4fe5cfc3a3	2214	/*************** Bit definition for RCC_APB1SMENR register ****************/
mbed_official	114:fe4fe5cfc3a3	2215	#define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /!< Timer 2 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2216	#define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /!< Window Watchdog clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2217	#define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /!< USART2 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2218	#define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /!< LPUART1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2219	#define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /!< I2C1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2220	#define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /!< PWR clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2221	#define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /!< LPTIM1 clock enabled in sleep mode /
mbed_official	114:fe4fe5cfc3a3	2222
mbed_official	114:fe4fe5cfc3a3	2223	/!< USART2 Clock source selection /
mbed_official	114:fe4fe5cfc3a3	2224	#define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /!< USART2SEL[1:0] bits /
mbed_official	114:fe4fe5cfc3a3	2225	#define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2226	#define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2227
mbed_official	114:fe4fe5cfc3a3	2228	/!< LPUART1 Clock source selection /
mbed_official	114:fe4fe5cfc3a3	2229	#define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /!< LPUART1SEL[1:0] bits /
mbed_official	114:fe4fe5cfc3a3	2230	#define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2231	#define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2232
mbed_official	114:fe4fe5cfc3a3	2233	/!< I2C1 Clock source selection /
mbed_official	114:fe4fe5cfc3a3	2234	#define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /!< I2C1SEL [1:0] bits /
mbed_official	114:fe4fe5cfc3a3	2235	#define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2236	#define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2237
mbed_official	114:fe4fe5cfc3a3	2238
mbed_official	114:fe4fe5cfc3a3	2239	/!< LPTIM1 Clock source selection /
mbed_official	114:fe4fe5cfc3a3	2240	#define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /!< LPTIM1SEL [1:0] bits /
mbed_official	114:fe4fe5cfc3a3	2241	#define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2242	#define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2243
mbed_official	114:fe4fe5cfc3a3	2244	/***************** Bit definition for RCC_CSR register *****************/
mbed_official	114:fe4fe5cfc3a3	2245	#define RCC_CSR_LSION ((uint32_t)0x00000001U) /!< Internal Low Speed oscillator enable /
mbed_official	114:fe4fe5cfc3a3	2246	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /!< Internal Low Speed oscillator Ready /
mbed_official	114:fe4fe5cfc3a3	2247
mbed_official	114:fe4fe5cfc3a3	2248	#define RCC_CSR_LSEON ((uint32_t)0x00000100U) /!< External Low Speed oscillator enable /
mbed_official	114:fe4fe5cfc3a3	2249	#define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /!< External Low Speed oscillator Ready /
mbed_official	114:fe4fe5cfc3a3	2250	#define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /!< External Low Speed oscillator Bypass /
mbed_official	114:fe4fe5cfc3a3	2251
mbed_official	114:fe4fe5cfc3a3	2252	#define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
mbed_official	114:fe4fe5cfc3a3	2253	#define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2254	#define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2255
mbed_official	114:fe4fe5cfc3a3	2256	#define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /!< External Low Speed oscillator CSS Enable /
mbed_official	114:fe4fe5cfc3a3	2257	#define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /!< External Low Speed oscillator CSS Detected /
mbed_official	114:fe4fe5cfc3a3	2258
mbed_official	114:fe4fe5cfc3a3	2259	/!< RTC congiguration /
mbed_official	114:fe4fe5cfc3a3	2260	#define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /!< RTCSEL[1:0] bits (RTC clock source selection) /
mbed_official	114:fe4fe5cfc3a3	2261	#define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2262	#define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2263
mbed_official	114:fe4fe5cfc3a3	2264	#define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /!< No clock /
mbed_official	114:fe4fe5cfc3a3	2265	#define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /!< LSE oscillator clock used as RTC clock /
mbed_official	114:fe4fe5cfc3a3	2266	#define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /!< LSI oscillator clock used as RTC clock /
mbed_official	114:fe4fe5cfc3a3	2267	#define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /!< HSE oscillator clock used as RTC clock /
mbed_official	114:fe4fe5cfc3a3	2268
mbed_official	114:fe4fe5cfc3a3	2269	#define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /!< RTC clock enable /
mbed_official	114:fe4fe5cfc3a3	2270	#define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /!< RTC software reset /
mbed_official	114:fe4fe5cfc3a3	2271
mbed_official	114:fe4fe5cfc3a3	2272	#define RCC_CSR_RMVF ((uint32_t)0x00800000U) /!< Remove reset flag /
mbed_official	114:fe4fe5cfc3a3	2273	#define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /!< Mifare Firewall reset flag /
mbed_official	114:fe4fe5cfc3a3	2274	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /!< OBL reset flag /
mbed_official	114:fe4fe5cfc3a3	2275	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /!< PIN reset flag /
mbed_official	114:fe4fe5cfc3a3	2276	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /!< POR/PDR reset flag /
mbed_official	114:fe4fe5cfc3a3	2277	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /!< Software Reset flag /
mbed_official	114:fe4fe5cfc3a3	2278	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /!< Independent Watchdog reset flag /
mbed_official	114:fe4fe5cfc3a3	2279	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /!< Window watchdog reset flag /
mbed_official	114:fe4fe5cfc3a3	2280	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /!< Low-Power reset flag /
mbed_official	114:fe4fe5cfc3a3	2281
mbed_official	114:fe4fe5cfc3a3	2282	/* Reference defines */
mbed_official	114:fe4fe5cfc3a3	2283	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
mbed_official	114:fe4fe5cfc3a3	2284
mbed_official	114:fe4fe5cfc3a3	2285
mbed_official	114:fe4fe5cfc3a3	2286	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2287	/* */
mbed_official	114:fe4fe5cfc3a3	2288	/* Real-Time Clock (RTC) */
mbed_official	114:fe4fe5cfc3a3	2289	/* */
mbed_official	114:fe4fe5cfc3a3	2290	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2291	/****************** Bits definition for RTC_TR register *****************/
mbed_official	114:fe4fe5cfc3a3	2292	#define RTC_TR_PM ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2293	#define RTC_TR_HT ((uint32_t)0x00300000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2294	#define RTC_TR_HT_0 ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2295	#define RTC_TR_HT_1 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2296	#define RTC_TR_HU ((uint32_t)0x000F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2297	#define RTC_TR_HU_0 ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2298	#define RTC_TR_HU_1 ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2299	#define RTC_TR_HU_2 ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2300	#define RTC_TR_HU_3 ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2301	#define RTC_TR_MNT ((uint32_t)0x00007000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2302	#define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2303	#define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2304	#define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2305	#define RTC_TR_MNU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2306	#define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2307	#define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2308	#define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2309	#define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2310	#define RTC_TR_ST ((uint32_t)0x00000070U) /!< /
mbed_official	114:fe4fe5cfc3a3	2311	#define RTC_TR_ST_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2312	#define RTC_TR_ST_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2313	#define RTC_TR_ST_2 ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2314	#define RTC_TR_SU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2315	#define RTC_TR_SU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2316	#define RTC_TR_SU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2317	#define RTC_TR_SU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2318	#define RTC_TR_SU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2319
mbed_official	114:fe4fe5cfc3a3	2320	/****************** Bits definition for RTC_DR register *****************/
mbed_official	114:fe4fe5cfc3a3	2321	#define RTC_DR_YT ((uint32_t)0x00F00000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2322	#define RTC_DR_YT_0 ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2323	#define RTC_DR_YT_1 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2324	#define RTC_DR_YT_2 ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2325	#define RTC_DR_YT_3 ((uint32_t)0x00800000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2326	#define RTC_DR_YU ((uint32_t)0x000F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2327	#define RTC_DR_YU_0 ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2328	#define RTC_DR_YU_1 ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2329	#define RTC_DR_YU_2 ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2330	#define RTC_DR_YU_3 ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2331	#define RTC_DR_WDU ((uint32_t)0x0000E000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2332	#define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2333	#define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2334	#define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2335	#define RTC_DR_MT ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2336	#define RTC_DR_MU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2337	#define RTC_DR_MU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2338	#define RTC_DR_MU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2339	#define RTC_DR_MU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2340	#define RTC_DR_MU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2341	#define RTC_DR_DT ((uint32_t)0x00000030U) /!< /
mbed_official	114:fe4fe5cfc3a3	2342	#define RTC_DR_DT_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2343	#define RTC_DR_DT_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2344	#define RTC_DR_DU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2345	#define RTC_DR_DU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2346	#define RTC_DR_DU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2347	#define RTC_DR_DU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2348	#define RTC_DR_DU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2349
mbed_official	114:fe4fe5cfc3a3	2350	/****************** Bits definition for RTC_CR register *****************/
mbed_official	114:fe4fe5cfc3a3	2351	#define RTC_CR_COE ((uint32_t)0x00800000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2352	#define RTC_CR_OSEL ((uint32_t)0x00600000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2353	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2354	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2355	#define RTC_CR_POL ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2356	#define RTC_CR_COSEL ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2357	#define RTC_CR_BCK ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2358	#define RTC_CR_SUB1H ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2359	#define RTC_CR_ADD1H ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2360	#define RTC_CR_TSIE ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2361	#define RTC_CR_WUTIE ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2362	#define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2363	#define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2364	#define RTC_CR_TSE ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2365	#define RTC_CR_WUTE ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2366	#define RTC_CR_ALRBE ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2367	#define RTC_CR_ALRAE ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2368	#define RTC_CR_FMT ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2369	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2370	#define RTC_CR_REFCKON ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2371	#define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2372	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /!< /
mbed_official	114:fe4fe5cfc3a3	2373	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2374	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2375	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2376
mbed_official	114:fe4fe5cfc3a3	2377	/****************** Bits definition for RTC_ISR register ****************/
mbed_official	114:fe4fe5cfc3a3	2378	#define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2379	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2380	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2381	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2382	#define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2383	#define RTC_ISR_TSF ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2384	#define RTC_ISR_WUTF ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2385	#define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2386	#define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2387	#define RTC_ISR_INIT ((uint32_t)0x00000080U) /!< /
mbed_official	114:fe4fe5cfc3a3	2388	#define RTC_ISR_INITF ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2389	#define RTC_ISR_RSF ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2390	#define RTC_ISR_INITS ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2391	#define RTC_ISR_SHPF ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2392	#define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2393	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2394	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2395
mbed_official	114:fe4fe5cfc3a3	2396	/****************** Bits definition for RTC_PRER register ***************/
mbed_official	114:fe4fe5cfc3a3	2397	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2398	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2399
mbed_official	114:fe4fe5cfc3a3	2400	/****************** Bits definition for RTC_WUTR register ***************/
mbed_official	114:fe4fe5cfc3a3	2401	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
mbed_official	114:fe4fe5cfc3a3	2402
mbed_official	114:fe4fe5cfc3a3	2403	/****************** Bits definition for RTC_ALRMAR register *************/
mbed_official	114:fe4fe5cfc3a3	2404	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2405	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2406	#define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2407	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2408	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2409	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2410	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2411	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2412	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2413	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2414	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2415	#define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2416	#define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2417	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2418	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2419	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2420	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2421	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2422	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2423	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2424	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2425	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2426	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2427	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2428	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2429	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2430	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2431	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2432	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2433	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2434	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /!< /
mbed_official	114:fe4fe5cfc3a3	2435	#define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /!< /
mbed_official	114:fe4fe5cfc3a3	2436	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2437	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2438	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2439	#define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2440	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2441	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2442	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2443	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2444
mbed_official	114:fe4fe5cfc3a3	2445	/****************** Bits definition for RTC_ALRMBR register *************/
mbed_official	114:fe4fe5cfc3a3	2446	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2447	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2448	#define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2449	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2450	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2451	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2452	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2453	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2454	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2455	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2456	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2457	#define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2458	#define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2459	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2460	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2461	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2462	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2463	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2464	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2465	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2466	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2467	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2468	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2469	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2470	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2471	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2472	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2473	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2474	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2475	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2476	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /!< /
mbed_official	114:fe4fe5cfc3a3	2477	#define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /!< /
mbed_official	114:fe4fe5cfc3a3	2478	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2479	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2480	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2481	#define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2482	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2483	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2484	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2485	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2486
mbed_official	114:fe4fe5cfc3a3	2487	/****************** Bits definition for RTC_WPR register ****************/
mbed_official	114:fe4fe5cfc3a3	2488	#define RTC_WPR_KEY ((uint32_t)0x000000FFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2489
mbed_official	114:fe4fe5cfc3a3	2490	/****************** Bits definition for RTC_SSR register ****************/
mbed_official	114:fe4fe5cfc3a3	2491	#define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2492
mbed_official	114:fe4fe5cfc3a3	2493	/****************** Bits definition for RTC_SHIFTR register *************/
mbed_official	114:fe4fe5cfc3a3	2494	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2495	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2496
mbed_official	114:fe4fe5cfc3a3	2497	/****************** Bits definition for RTC_TSTR register ***************/
mbed_official	114:fe4fe5cfc3a3	2498	#define RTC_TSTR_PM ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2499	#define RTC_TSTR_HT ((uint32_t)0x00300000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2500	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2501	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2502	#define RTC_TSTR_HU ((uint32_t)0x000F0000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2503	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2504	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2505	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2506	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2507	#define RTC_TSTR_MNT ((uint32_t)0x00007000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2508	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2509	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2510	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2511	#define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2512	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2513	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2514	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2515	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2516	#define RTC_TSTR_ST ((uint32_t)0x00000070U) /!< /
mbed_official	114:fe4fe5cfc3a3	2517	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2518	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2519	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2520	#define RTC_TSTR_SU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2521	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2522	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2523	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2524	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2525
mbed_official	114:fe4fe5cfc3a3	2526	/****************** Bits definition for RTC_TSDR register ***************/
mbed_official	114:fe4fe5cfc3a3	2527	#define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2528	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2529	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2530	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2531	#define RTC_TSDR_MT ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2532	#define RTC_TSDR_MU ((uint32_t)0x00000F00U) /!< /
mbed_official	114:fe4fe5cfc3a3	2533	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2534	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2535	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2536	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2537	#define RTC_TSDR_DT ((uint32_t)0x00000030U) /!< /
mbed_official	114:fe4fe5cfc3a3	2538	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2539	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2540	#define RTC_TSDR_DU ((uint32_t)0x0000000FU) /!< /
mbed_official	114:fe4fe5cfc3a3	2541	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2542	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2543	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2544	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2545
mbed_official	114:fe4fe5cfc3a3	2546	/****************** Bits definition for RTC_TSSSR register **************/
mbed_official	114:fe4fe5cfc3a3	2547	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
mbed_official	114:fe4fe5cfc3a3	2548
mbed_official	114:fe4fe5cfc3a3	2549	/****************** Bits definition for RTC_CALR register ***************/
mbed_official	114:fe4fe5cfc3a3	2550	#define RTC_CALR_CALP ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2551	#define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2552	#define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2553	#define RTC_CALR_CALM ((uint32_t)0x000001FFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2554	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2555	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2556	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2557	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2558	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2559	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2560	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2561	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /!< /
mbed_official	114:fe4fe5cfc3a3	2562	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2563
mbed_official	114:fe4fe5cfc3a3	2564	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	2565	#define RTC_CAL_CALP RTC_CALR_CALP
mbed_official	114:fe4fe5cfc3a3	2566	#define RTC_CAL_CALW8 RTC_CALR_CALW8
mbed_official	114:fe4fe5cfc3a3	2567	#define RTC_CAL_CALW16 RTC_CALR_CALW16
mbed_official	114:fe4fe5cfc3a3	2568	#define RTC_CAL_CALM RTC_CALR_CALM
mbed_official	114:fe4fe5cfc3a3	2569	#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
mbed_official	114:fe4fe5cfc3a3	2570	#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
mbed_official	114:fe4fe5cfc3a3	2571	#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
mbed_official	114:fe4fe5cfc3a3	2572	#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
mbed_official	114:fe4fe5cfc3a3	2573	#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
mbed_official	114:fe4fe5cfc3a3	2574	#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
mbed_official	114:fe4fe5cfc3a3	2575	#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
mbed_official	114:fe4fe5cfc3a3	2576	#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
mbed_official	114:fe4fe5cfc3a3	2577	#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
mbed_official	114:fe4fe5cfc3a3	2578
mbed_official	114:fe4fe5cfc3a3	2579	/****************** Bits definition for RTC_TAMPCR register **************/
mbed_official	114:fe4fe5cfc3a3	2580	#define RTC_TAMPCR_TAMP3MF ((uint32_t)0x01000000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2581	#define RTC_TAMPCR_TAMP3NOERASE ((uint32_t)0x00800000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2582	#define RTC_TAMPCR_TAMP3IE ((uint32_t)0x00400000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2583	#define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2584	#define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2585	#define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2586	#define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2587	#define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2588	#define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2589	#define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2590	#define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2591	#define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2592	#define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2593	#define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2594	#define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /!< /
mbed_official	114:fe4fe5cfc3a3	2595	#define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /!< /
mbed_official	114:fe4fe5cfc3a3	2596	#define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /!< /
mbed_official	114:fe4fe5cfc3a3	2597	#define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /!< /
mbed_official	114:fe4fe5cfc3a3	2598	#define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /!< /
mbed_official	114:fe4fe5cfc3a3	2599	#define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /!< /
mbed_official	114:fe4fe5cfc3a3	2600	#define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /!< /
mbed_official	114:fe4fe5cfc3a3	2601	#define RTC_TAMPCR_TAMP3TRG ((uint32_t)0x00000040U) /!< /
mbed_official	114:fe4fe5cfc3a3	2602	#define RTC_TAMPCR_TAMP3E ((uint32_t)0x00000020U) /!< /
mbed_official	114:fe4fe5cfc3a3	2603	#define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /!< /
mbed_official	114:fe4fe5cfc3a3	2604	#define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /!< /
mbed_official	114:fe4fe5cfc3a3	2605	#define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /!< /
mbed_official	114:fe4fe5cfc3a3	2606	#define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2607	#define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2608
mbed_official	114:fe4fe5cfc3a3	2609	/****************** Bits definition for RTC_ALRMASSR register ***********/
mbed_official	114:fe4fe5cfc3a3	2610	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
mbed_official	114:fe4fe5cfc3a3	2611	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	2612	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	2613	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	2614	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	2615	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
mbed_official	114:fe4fe5cfc3a3	2616
mbed_official	114:fe4fe5cfc3a3	2617	/****************** Bits definition for RTC_ALRMBSSR register ***********/
mbed_official	114:fe4fe5cfc3a3	2618	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
mbed_official	114:fe4fe5cfc3a3	2619	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
mbed_official	114:fe4fe5cfc3a3	2620	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
mbed_official	114:fe4fe5cfc3a3	2621	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
mbed_official	114:fe4fe5cfc3a3	2622	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
mbed_official	114:fe4fe5cfc3a3	2623	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
mbed_official	114:fe4fe5cfc3a3	2624
mbed_official	114:fe4fe5cfc3a3	2625	/****************** Bits definition for RTC_OR register **************/
mbed_official	114:fe4fe5cfc3a3	2626	#define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /!< /
mbed_official	114:fe4fe5cfc3a3	2627	#define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /!< /
mbed_official	114:fe4fe5cfc3a3	2628
mbed_official	114:fe4fe5cfc3a3	2629	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	2630	#define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
mbed_official	114:fe4fe5cfc3a3	2631
mbed_official	114:fe4fe5cfc3a3	2632	/****************** Bits definition for RTC_BKP0R register **************/
mbed_official	114:fe4fe5cfc3a3	2633	#define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2634
mbed_official	114:fe4fe5cfc3a3	2635	/****************** Bits definition for RTC_BKP1R register **************/
mbed_official	114:fe4fe5cfc3a3	2636	#define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2637
mbed_official	114:fe4fe5cfc3a3	2638	/****************** Bits definition for RTC_BKP2R register **************/
mbed_official	114:fe4fe5cfc3a3	2639	#define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2640
mbed_official	114:fe4fe5cfc3a3	2641	/****************** Bits definition for RTC_BKP3R register **************/
mbed_official	114:fe4fe5cfc3a3	2642	#define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2643
mbed_official	114:fe4fe5cfc3a3	2644	/****************** Bits definition for RTC_BKP4R register **************/
mbed_official	114:fe4fe5cfc3a3	2645	#define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /!< /
mbed_official	114:fe4fe5cfc3a3	2646
mbed_official	114:fe4fe5cfc3a3	2647	/****************** Number of backup registers ****************************/
mbed_official	114:fe4fe5cfc3a3	2648	#define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /!< /
mbed_official	114:fe4fe5cfc3a3	2649
mbed_official	114:fe4fe5cfc3a3	2650	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2651	/* */
mbed_official	114:fe4fe5cfc3a3	2652	/* Serial Peripheral Interface (SPI) */
mbed_official	114:fe4fe5cfc3a3	2653	/* */
mbed_official	114:fe4fe5cfc3a3	2654	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2655	/***************** Bit definition for SPI_CR1 register ******************/
mbed_official	114:fe4fe5cfc3a3	2656	#define SPI_CR1_CPHA ((uint32_t)0x00000001U) /!< Clock Phase /
mbed_official	114:fe4fe5cfc3a3	2657	#define SPI_CR1_CPOL ((uint32_t)0x00000002U) /!< Clock Polarity /
mbed_official	114:fe4fe5cfc3a3	2658	#define SPI_CR1_MSTR ((uint32_t)0x00000004U) /!< Master Selection /
mbed_official	114:fe4fe5cfc3a3	2659	#define SPI_CR1_BR ((uint32_t)0x00000038U) /!< BR[2:0] bits (Baud Rate Control) /
mbed_official	114:fe4fe5cfc3a3	2660	#define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2661	#define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2662	#define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2663	#define SPI_CR1_SPE ((uint32_t)0x00000040U) /!< SPI Enable /
mbed_official	114:fe4fe5cfc3a3	2664	#define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /!< Frame Format /
mbed_official	114:fe4fe5cfc3a3	2665	#define SPI_CR1_SSI ((uint32_t)0x00000100U) /!< Internal slave select /
mbed_official	114:fe4fe5cfc3a3	2666	#define SPI_CR1_SSM ((uint32_t)0x00000200U) /!< Software slave management /
mbed_official	114:fe4fe5cfc3a3	2667	#define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /!< Receive only /
mbed_official	114:fe4fe5cfc3a3	2668	#define SPI_CR1_DFF ((uint32_t)0x00000800U) /!< Data Frame Format /
mbed_official	114:fe4fe5cfc3a3	2669	#define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /!< Transmit CRC next /
mbed_official	114:fe4fe5cfc3a3	2670	#define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /!< Hardware CRC calculation enable /
mbed_official	114:fe4fe5cfc3a3	2671	#define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /!< Output enable in bidirectional mode /
mbed_official	114:fe4fe5cfc3a3	2672	#define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /!< Bidirectional data mode enable /
mbed_official	114:fe4fe5cfc3a3	2673
mbed_official	114:fe4fe5cfc3a3	2674	/***************** Bit definition for SPI_CR2 register ******************/
mbed_official	114:fe4fe5cfc3a3	2675	#define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /!< Rx Buffer DMA Enable /
mbed_official	114:fe4fe5cfc3a3	2676	#define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /!< Tx Buffer DMA Enable /
mbed_official	114:fe4fe5cfc3a3	2677	#define SPI_CR2_SSOE ((uint32_t)0x00000004U) /!< SS Output Enable /
mbed_official	114:fe4fe5cfc3a3	2678	#define SPI_CR2_FRF ((uint32_t)0x00000010U) /!< Frame Format Enable /
mbed_official	114:fe4fe5cfc3a3	2679	#define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /!< Error Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2680	#define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /!< RX buffer Not Empty Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2681	#define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /!< Tx buffer Empty Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	2682
mbed_official	114:fe4fe5cfc3a3	2683	/****************** Bit definition for SPI_SR register ******************/
mbed_official	114:fe4fe5cfc3a3	2684	#define SPI_SR_RXNE ((uint32_t)0x00000001U) /!< Receive buffer Not Empty /
mbed_official	114:fe4fe5cfc3a3	2685	#define SPI_SR_TXE ((uint32_t)0x00000002U) /!< Transmit buffer Empty /
mbed_official	114:fe4fe5cfc3a3	2686	#define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /!< Channel side /
mbed_official	114:fe4fe5cfc3a3	2687	#define SPI_SR_UDR ((uint32_t)0x00000008U) /!< Underrun flag /
mbed_official	114:fe4fe5cfc3a3	2688	#define SPI_SR_CRCERR ((uint32_t)0x00000010U) /!< CRC Error flag /
mbed_official	114:fe4fe5cfc3a3	2689	#define SPI_SR_MODF ((uint32_t)0x00000020U) /!< Mode fault /
mbed_official	114:fe4fe5cfc3a3	2690	#define SPI_SR_OVR ((uint32_t)0x00000040U) /!< Overrun flag /
mbed_official	114:fe4fe5cfc3a3	2691	#define SPI_SR_BSY ((uint32_t)0x00000080U) /!< Busy flag /
mbed_official	114:fe4fe5cfc3a3	2692	#define SPI_SR_FRE ((uint32_t)0x00000100U) /!< TI frame format error /
mbed_official	114:fe4fe5cfc3a3	2693
mbed_official	114:fe4fe5cfc3a3	2694	/****************** Bit definition for SPI_DR register ******************/
mbed_official	114:fe4fe5cfc3a3	2695	#define SPI_DR_DR ((uint32_t)0x0000FFFFU) /!< Data Register /
mbed_official	114:fe4fe5cfc3a3	2696
mbed_official	114:fe4fe5cfc3a3	2697	/***************** Bit definition for SPI_CRCPR register ****************/
mbed_official	114:fe4fe5cfc3a3	2698	#define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /!< CRC polynomial register /
mbed_official	114:fe4fe5cfc3a3	2699
mbed_official	114:fe4fe5cfc3a3	2700	/**************** Bit definition for SPI_RXCRCR register ****************/
mbed_official	114:fe4fe5cfc3a3	2701	#define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /!< Rx CRC Register /
mbed_official	114:fe4fe5cfc3a3	2702
mbed_official	114:fe4fe5cfc3a3	2703	/**************** Bit definition for SPI_TXCRCR register ****************/
mbed_official	114:fe4fe5cfc3a3	2704	#define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /!< Tx CRC Register /
mbed_official	114:fe4fe5cfc3a3	2705
mbed_official	114:fe4fe5cfc3a3	2706	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2707	/* */
mbed_official	114:fe4fe5cfc3a3	2708	/* System Configuration (SYSCFG) */
mbed_official	114:fe4fe5cfc3a3	2709	/* */
mbed_official	114:fe4fe5cfc3a3	2710	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2711	/*************** Bit definition for SYSCFG_CFGR1 register **************/
mbed_official	114:fe4fe5cfc3a3	2712	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /!< SYSCFG_Memory Remap Config /
mbed_official	114:fe4fe5cfc3a3	2713	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /!< SYSCFG_Memory Remap Config Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2714	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /!< SYSCFG_Memory Remap Config Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2715	#define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /!< SYSCFG_Boot mode Config /
mbed_official	114:fe4fe5cfc3a3	2716	#define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /!< SYSCFG_Boot mode Config Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2717	#define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /!< SYSCFG_Boot mode Config Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2718
mbed_official	114:fe4fe5cfc3a3	2719	/*************** Bit definition for SYSCFG_CFGR2 register **************/
mbed_official	114:fe4fe5cfc3a3	2720	#define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /!< Firewall disable bit /
mbed_official	114:fe4fe5cfc3a3	2721	#define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /!< I2C PB6 Fast mode plus /
mbed_official	114:fe4fe5cfc3a3	2722	#define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /!< I2C PB7 Fast mode plus /
mbed_official	114:fe4fe5cfc3a3	2723	#define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /!< I2C PB8 Fast mode plus /
mbed_official	114:fe4fe5cfc3a3	2724	#define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /!< I2C PB9 Fast mode plus /
mbed_official	114:fe4fe5cfc3a3	2725	#define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /!< I2C1 Fast mode plus /
mbed_official	114:fe4fe5cfc3a3	2726
mbed_official	114:fe4fe5cfc3a3	2727	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
mbed_official	114:fe4fe5cfc3a3	2728	#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /!< EXTI 0 configuration /
mbed_official	114:fe4fe5cfc3a3	2729	#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /!< EXTI 1 configuration /
mbed_official	114:fe4fe5cfc3a3	2730	#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /!< EXTI 2 configuration /
mbed_official	114:fe4fe5cfc3a3	2731	#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /!< EXTI 3 configuration /
mbed_official	114:fe4fe5cfc3a3	2732
mbed_official	114:fe4fe5cfc3a3	2733	/**
mbed_official	114:fe4fe5cfc3a3	2734	* @brief EXTI0 configuration
mbed_official	114:fe4fe5cfc3a3	2735	*/
mbed_official	114:fe4fe5cfc3a3	2736	#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /!< PA[0] pin /
mbed_official	114:fe4fe5cfc3a3	2737	#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /!< PB[0] pin /
mbed_official	114:fe4fe5cfc3a3	2738	#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /!< PC[0] pin /
mbed_official	114:fe4fe5cfc3a3	2739	#define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /!< PH[0] pin /
mbed_official	114:fe4fe5cfc3a3	2740
mbed_official	114:fe4fe5cfc3a3	2741	/**
mbed_official	114:fe4fe5cfc3a3	2742	* @brief EXTI1 configuration
mbed_official	114:fe4fe5cfc3a3	2743	*/
mbed_official	114:fe4fe5cfc3a3	2744	#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /!< PA[1] pin /
mbed_official	114:fe4fe5cfc3a3	2745	#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /!< PB[1] pin /
mbed_official	114:fe4fe5cfc3a3	2746	#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /!< PC[1] pin /
mbed_official	114:fe4fe5cfc3a3	2747	#define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /!< PH[1] pin /
mbed_official	114:fe4fe5cfc3a3	2748
mbed_official	114:fe4fe5cfc3a3	2749	/**
mbed_official	114:fe4fe5cfc3a3	2750	* @brief EXTI2 configuration
mbed_official	114:fe4fe5cfc3a3	2751	*/
mbed_official	114:fe4fe5cfc3a3	2752	#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /!< PA[2] pin /
mbed_official	114:fe4fe5cfc3a3	2753	#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /!< PB[2] pin /
mbed_official	114:fe4fe5cfc3a3	2754	#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /!< PC[2] pin /
mbed_official	114:fe4fe5cfc3a3	2755	#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /!< PD[2] pin /
mbed_official	114:fe4fe5cfc3a3	2756
mbed_official	114:fe4fe5cfc3a3	2757	/**
mbed_official	114:fe4fe5cfc3a3	2758	* @brief EXTI3 configuration
mbed_official	114:fe4fe5cfc3a3	2759	*/
mbed_official	114:fe4fe5cfc3a3	2760	#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /!< PA[3] pin /
mbed_official	114:fe4fe5cfc3a3	2761	#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /!< PB[3] pin /
mbed_official	114:fe4fe5cfc3a3	2762	#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /!< PC[3] pin /
mbed_official	114:fe4fe5cfc3a3	2763
mbed_official	114:fe4fe5cfc3a3	2764	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official	114:fe4fe5cfc3a3	2765	#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /!< EXTI 4 configuration /
mbed_official	114:fe4fe5cfc3a3	2766	#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /!< EXTI 5 configuration /
mbed_official	114:fe4fe5cfc3a3	2767	#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /!< EXTI 6 configuration /
mbed_official	114:fe4fe5cfc3a3	2768	#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /!< EXTI 7 configuration /
mbed_official	114:fe4fe5cfc3a3	2769
mbed_official	114:fe4fe5cfc3a3	2770	/**
mbed_official	114:fe4fe5cfc3a3	2771	* @brief EXTI4 configuration
mbed_official	114:fe4fe5cfc3a3	2772	*/
mbed_official	114:fe4fe5cfc3a3	2773	#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /!< PA[4] pin /
mbed_official	114:fe4fe5cfc3a3	2774	#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /!< PB[4] pin /
mbed_official	114:fe4fe5cfc3a3	2775	#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /!< PC[4] pin /
mbed_official	114:fe4fe5cfc3a3	2776
mbed_official	114:fe4fe5cfc3a3	2777	/**
mbed_official	114:fe4fe5cfc3a3	2778	* @brief EXTI5 configuration
mbed_official	114:fe4fe5cfc3a3	2779	*/
mbed_official	114:fe4fe5cfc3a3	2780	#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /!< PA[5] pin /
mbed_official	114:fe4fe5cfc3a3	2781	#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /!< PB[5] pin /
mbed_official	114:fe4fe5cfc3a3	2782	#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /!< PC[5] pin /
mbed_official	114:fe4fe5cfc3a3	2783
mbed_official	114:fe4fe5cfc3a3	2784	/**
mbed_official	114:fe4fe5cfc3a3	2785	* @brief EXTI6 configuration
mbed_official	114:fe4fe5cfc3a3	2786	*/
mbed_official	114:fe4fe5cfc3a3	2787	#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /!< PA[6] pin /
mbed_official	114:fe4fe5cfc3a3	2788	#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /!< PB[6] pin /
mbed_official	114:fe4fe5cfc3a3	2789	#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /!< PC[6] pin /
mbed_official	114:fe4fe5cfc3a3	2790
mbed_official	114:fe4fe5cfc3a3	2791	/**
mbed_official	114:fe4fe5cfc3a3	2792	* @brief EXTI7 configuration
mbed_official	114:fe4fe5cfc3a3	2793	*/
mbed_official	114:fe4fe5cfc3a3	2794	#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /!< PA[7] pin /
mbed_official	114:fe4fe5cfc3a3	2795	#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /!< PB[7] pin /
mbed_official	114:fe4fe5cfc3a3	2796	#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /!< PC[7] pin /
mbed_official	114:fe4fe5cfc3a3	2797
mbed_official	114:fe4fe5cfc3a3	2798	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official	114:fe4fe5cfc3a3	2799	#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /!< EXTI 8 configuration /
mbed_official	114:fe4fe5cfc3a3	2800	#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /!< EXTI 9 configuration /
mbed_official	114:fe4fe5cfc3a3	2801	#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /!< EXTI 10 configuration /
mbed_official	114:fe4fe5cfc3a3	2802	#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /!< EXTI 11 configuration /
mbed_official	114:fe4fe5cfc3a3	2803
mbed_official	114:fe4fe5cfc3a3	2804	/**
mbed_official	114:fe4fe5cfc3a3	2805	* @brief EXTI8 configuration
mbed_official	114:fe4fe5cfc3a3	2806	*/
mbed_official	114:fe4fe5cfc3a3	2807	#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /!< PA[8] pin /
mbed_official	114:fe4fe5cfc3a3	2808	#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /!< PB[8] pin /
mbed_official	114:fe4fe5cfc3a3	2809	#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /!< PC[8] pin /
mbed_official	114:fe4fe5cfc3a3	2810
mbed_official	114:fe4fe5cfc3a3	2811	/**
mbed_official	114:fe4fe5cfc3a3	2812	* @brief EXTI9 configuration
mbed_official	114:fe4fe5cfc3a3	2813	*/
mbed_official	114:fe4fe5cfc3a3	2814	#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /!< PA[9] pin /
mbed_official	114:fe4fe5cfc3a3	2815	#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /!< PB[9] pin /
mbed_official	114:fe4fe5cfc3a3	2816	#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /!< PC[9] pin /
mbed_official	114:fe4fe5cfc3a3	2817
mbed_official	114:fe4fe5cfc3a3	2818	/**
mbed_official	114:fe4fe5cfc3a3	2819	* @brief EXTI10 configuration
mbed_official	114:fe4fe5cfc3a3	2820	*/
mbed_official	114:fe4fe5cfc3a3	2821	#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /!< PA[10] pin /
mbed_official	114:fe4fe5cfc3a3	2822	#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /!< PB[10] pin /
mbed_official	114:fe4fe5cfc3a3	2823	#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /!< PC[10] pin /
mbed_official	114:fe4fe5cfc3a3	2824
mbed_official	114:fe4fe5cfc3a3	2825	/**
mbed_official	114:fe4fe5cfc3a3	2826	* @brief EXTI11 configuration
mbed_official	114:fe4fe5cfc3a3	2827	*/
mbed_official	114:fe4fe5cfc3a3	2828	#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /!< PA[11] pin /
mbed_official	114:fe4fe5cfc3a3	2829	#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /!< PB[11] pin /
mbed_official	114:fe4fe5cfc3a3	2830	#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /!< PC[11] pin /
mbed_official	114:fe4fe5cfc3a3	2831
mbed_official	114:fe4fe5cfc3a3	2832	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
mbed_official	114:fe4fe5cfc3a3	2833	#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /!< EXTI 12 configuration /
mbed_official	114:fe4fe5cfc3a3	2834	#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /!< EXTI 13 configuration /
mbed_official	114:fe4fe5cfc3a3	2835	#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /!< EXTI 14 configuration /
mbed_official	114:fe4fe5cfc3a3	2836	#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /!< EXTI 15 configuration /
mbed_official	114:fe4fe5cfc3a3	2837
mbed_official	114:fe4fe5cfc3a3	2838	/**
mbed_official	114:fe4fe5cfc3a3	2839	* @brief EXTI12 configuration
mbed_official	114:fe4fe5cfc3a3	2840	*/
mbed_official	114:fe4fe5cfc3a3	2841	#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /!< PA[12] pin /
mbed_official	114:fe4fe5cfc3a3	2842	#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /!< PB[12] pin /
mbed_official	114:fe4fe5cfc3a3	2843	#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /!< PC[12] pin /
mbed_official	114:fe4fe5cfc3a3	2844
mbed_official	114:fe4fe5cfc3a3	2845	/**
mbed_official	114:fe4fe5cfc3a3	2846	* @brief EXTI13 configuration
mbed_official	114:fe4fe5cfc3a3	2847	*/
mbed_official	114:fe4fe5cfc3a3	2848	#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /!< PA[13] pin /
mbed_official	114:fe4fe5cfc3a3	2849	#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /!< PB[13] pin /
mbed_official	114:fe4fe5cfc3a3	2850	#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /!< PC[13] pin /
mbed_official	114:fe4fe5cfc3a3	2851
mbed_official	114:fe4fe5cfc3a3	2852	/**
mbed_official	114:fe4fe5cfc3a3	2853	* @brief EXTI14 configuration
mbed_official	114:fe4fe5cfc3a3	2854	*/
mbed_official	114:fe4fe5cfc3a3	2855	#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /!< PA[14] pin /
mbed_official	114:fe4fe5cfc3a3	2856	#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /!< PB[14] pin /
mbed_official	114:fe4fe5cfc3a3	2857	#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /!< PC[14] pin /
mbed_official	114:fe4fe5cfc3a3	2858
mbed_official	114:fe4fe5cfc3a3	2859	/**
mbed_official	114:fe4fe5cfc3a3	2860	* @brief EXTI15 configuration
mbed_official	114:fe4fe5cfc3a3	2861	*/
mbed_official	114:fe4fe5cfc3a3	2862	#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /!< PA[15] pin /
mbed_official	114:fe4fe5cfc3a3	2863	#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /!< PB[15] pin /
mbed_official	114:fe4fe5cfc3a3	2864	#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /!< PC[15] pin /
mbed_official	114:fe4fe5cfc3a3	2865
mbed_official	114:fe4fe5cfc3a3	2866
mbed_official	114:fe4fe5cfc3a3	2867	/*************** Bit definition for SYSCFG_CFGR3 register **************/
mbed_official	114:fe4fe5cfc3a3	2868	#define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /!< Vref Enable bit/
mbed_official	114:fe4fe5cfc3a3	2869	#define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /!< Verf_ADC connection bit /
mbed_official	114:fe4fe5cfc3a3	2870	#define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2871	#define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2872	#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /!< VREFINT reference for ADC enable bit /
mbed_official	114:fe4fe5cfc3a3	2873	#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /!< Sensor reference for ADC enable bit /
mbed_official	114:fe4fe5cfc3a3	2874	#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /!< VREFINT reference for comparator 2 enable bit /
mbed_official	114:fe4fe5cfc3a3	2875	#define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /!< Sensor for ADC ready flag /
mbed_official	114:fe4fe5cfc3a3	2876	#define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /!< VREFINT for ADC ready flag /
mbed_official	114:fe4fe5cfc3a3	2877	#define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /!< VREFINT for comparator ready flag /
mbed_official	114:fe4fe5cfc3a3	2878	#define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /!< VREFINT ready flag /
mbed_official	114:fe4fe5cfc3a3	2879	#define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /!< CFGR3 lock bit /
mbed_official	114:fe4fe5cfc3a3	2880
mbed_official	114:fe4fe5cfc3a3	2881	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	2882
mbed_official	114:fe4fe5cfc3a3	2883	#define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
mbed_official	114:fe4fe5cfc3a3	2884	#define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
mbed_official	114:fe4fe5cfc3a3	2885	#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
mbed_official	114:fe4fe5cfc3a3	2886	#define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
mbed_official	114:fe4fe5cfc3a3	2887
mbed_official	114:fe4fe5cfc3a3	2888	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2889	/* */
mbed_official	114:fe4fe5cfc3a3	2890	/* Timers (TIM) */
mbed_official	114:fe4fe5cfc3a3	2891	/* */
mbed_official	114:fe4fe5cfc3a3	2892	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	2893	/*
mbed_official	114:fe4fe5cfc3a3	2894	* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official	114:fe4fe5cfc3a3	2895	*/
mbed_official	114:fe4fe5cfc3a3	2896	#if defined (STM32L071xx) \|\| defined (STM32L072xx) \|\| defined (STM32L073xx) \
mbed_official	114:fe4fe5cfc3a3	2897	\|\| defined (STM32L081xx) \|\| defined (STM32L082xx) \|\| defined (STM32L083xx)
mbed_official	114:fe4fe5cfc3a3	2898	#define TIM_TIM2_REMAP_HSI_SUPPORT /!<Support remap HSI on TIM2 /
mbed_official	114:fe4fe5cfc3a3	2899	#define TIM_TIM2_REMAP_HSI48_SUPPORT /!<Support remap HSI48 on TIM2 /
mbed_official	114:fe4fe5cfc3a3	2900	#else
mbed_official	114:fe4fe5cfc3a3	2901	#define TIM_TIM2_REMAP_HSI_SUPPORT /!<Support remap HSI on TIM2 /
mbed_official	114:fe4fe5cfc3a3	2902	#endif
mbed_official	114:fe4fe5cfc3a3	2903
mbed_official	114:fe4fe5cfc3a3	2904	/***************** Bit definition for TIM_CR1 register ******************/
mbed_official	114:fe4fe5cfc3a3	2905	#define TIM_CR1_CEN ((uint32_t)0x00000001U) /!<Counter enable /
mbed_official	114:fe4fe5cfc3a3	2906	#define TIM_CR1_UDIS ((uint32_t)0x00000002U) /!<Update disable /
mbed_official	114:fe4fe5cfc3a3	2907	#define TIM_CR1_URS ((uint32_t)0x00000004U) /!<Update request source /
mbed_official	114:fe4fe5cfc3a3	2908	#define TIM_CR1_OPM ((uint32_t)0x00000008U) /!<One pulse mode /
mbed_official	114:fe4fe5cfc3a3	2909	#define TIM_CR1_DIR ((uint32_t)0x00000010U) /!<Direction /
mbed_official	114:fe4fe5cfc3a3	2910
mbed_official	114:fe4fe5cfc3a3	2911	#define TIM_CR1_CMS ((uint32_t)0x00000060U) /!<CMS[1:0] bits (Center-aligned mode selection) /
mbed_official	114:fe4fe5cfc3a3	2912	#define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2913	#define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2914
mbed_official	114:fe4fe5cfc3a3	2915	#define TIM_CR1_ARPE ((uint32_t)0x00000080U) /!<Auto-reload preload enable /
mbed_official	114:fe4fe5cfc3a3	2916
mbed_official	114:fe4fe5cfc3a3	2917	#define TIM_CR1_CKD ((uint32_t)0x00000300U) /!<CKD[1:0] bits (clock division) /
mbed_official	114:fe4fe5cfc3a3	2918	#define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2919	#define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2920
mbed_official	114:fe4fe5cfc3a3	2921	/***************** Bit definition for TIM_CR2 register ******************/
mbed_official	114:fe4fe5cfc3a3	2922	#define TIM_CR2_CCDS ((uint32_t)0x00000008U) /!<Capture/Compare DMA Selection /
mbed_official	114:fe4fe5cfc3a3	2923
mbed_official	114:fe4fe5cfc3a3	2924	#define TIM_CR2_MMS ((uint32_t)0x00000070U) /!<MMS[2:0] bits (Master Mode Selection) /
mbed_official	114:fe4fe5cfc3a3	2925	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2926	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2927	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2928
mbed_official	114:fe4fe5cfc3a3	2929	#define TIM_CR2_TI1S ((uint32_t)0x00000080U) /!<TI1 Selection /
mbed_official	114:fe4fe5cfc3a3	2930
mbed_official	114:fe4fe5cfc3a3	2931	/***************** Bit definition for TIM_SMCR register *****************/
mbed_official	114:fe4fe5cfc3a3	2932	#define TIM_SMCR_SMS ((uint32_t)0x00000007U) /!<SMS[2:0] bits (Slave mode selection) /
mbed_official	114:fe4fe5cfc3a3	2933	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2934	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2935	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2936
mbed_official	114:fe4fe5cfc3a3	2937	#define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /!< OCREF clear selection /
mbed_official	114:fe4fe5cfc3a3	2938
mbed_official	114:fe4fe5cfc3a3	2939	#define TIM_SMCR_TS ((uint32_t)0x00000070U) /!<TS[2:0] bits (Trigger selection) /
mbed_official	114:fe4fe5cfc3a3	2940	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2941	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2942	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2943
mbed_official	114:fe4fe5cfc3a3	2944	#define TIM_SMCR_MSM ((uint32_t)0x00000080U) /!<Master/slave mode /
mbed_official	114:fe4fe5cfc3a3	2945
mbed_official	114:fe4fe5cfc3a3	2946	#define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /!<ETF[3:0] bits (External trigger filter) /
mbed_official	114:fe4fe5cfc3a3	2947	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2948	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2949	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	2950	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	2951
mbed_official	114:fe4fe5cfc3a3	2952	#define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /!<ETPS[1:0] bits (External trigger prescaler) /
mbed_official	114:fe4fe5cfc3a3	2953	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2954	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2955
mbed_official	114:fe4fe5cfc3a3	2956	#define TIM_SMCR_ECE ((uint32_t)0x00004000U) /!<External clock enable /
mbed_official	114:fe4fe5cfc3a3	2957	#define TIM_SMCR_ETP ((uint32_t)0x00008000U) /!<External trigger polarity /
mbed_official	114:fe4fe5cfc3a3	2958
mbed_official	114:fe4fe5cfc3a3	2959	/***************** Bit definition for TIM_DIER register *****************/
mbed_official	114:fe4fe5cfc3a3	2960	#define TIM_DIER_UIE ((uint32_t)0x00000001U) /!<Update interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2961	#define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /!<Capture/Compare 1 interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2962	#define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /!<Capture/Compare 2 interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2963	#define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /!<Capture/Compare 3 interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2964	#define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /!<Capture/Compare 4 interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2965	#define TIM_DIER_TIE ((uint32_t)0x00000040U) /!<Trigger interrupt enable /
mbed_official	114:fe4fe5cfc3a3	2966	#define TIM_DIER_UDE ((uint32_t)0x00000100U) /!<Update DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2967	#define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /!<Capture/Compare 1 DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2968	#define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /!<Capture/Compare 2 DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2969	#define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /!<Capture/Compare 3 DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2970	#define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /!<Capture/Compare 4 DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2971	#define TIM_DIER_TDE ((uint32_t)0x00004000U) /!<Trigger DMA request enable /
mbed_official	114:fe4fe5cfc3a3	2972
mbed_official	114:fe4fe5cfc3a3	2973	/****************** Bit definition for TIM_SR register ******************/
mbed_official	114:fe4fe5cfc3a3	2974	#define TIM_SR_UIF ((uint32_t)0x00000001U) /!<Update interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2975	#define TIM_SR_CC1IF ((uint32_t)0x00000002U) /!<Capture/Compare 1 interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2976	#define TIM_SR_CC2IF ((uint32_t)0x00000004U) /!<Capture/Compare 2 interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2977	#define TIM_SR_CC3IF ((uint32_t)0x00000008U) /!<Capture/Compare 3 interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2978	#define TIM_SR_CC4IF ((uint32_t)0x00000010U) /!<Capture/Compare 4 interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2979	#define TIM_SR_TIF ((uint32_t)0x00000040U) /!<Trigger interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	2980	#define TIM_SR_CC1OF ((uint32_t)0x00000200U) /!<Capture/Compare 1 Overcapture Flag /
mbed_official	114:fe4fe5cfc3a3	2981	#define TIM_SR_CC2OF ((uint32_t)0x00000400U) /!<Capture/Compare 2 Overcapture Flag /
mbed_official	114:fe4fe5cfc3a3	2982	#define TIM_SR_CC3OF ((uint32_t)0x00000800U) /!<Capture/Compare 3 Overcapture Flag /
mbed_official	114:fe4fe5cfc3a3	2983	#define TIM_SR_CC4OF ((uint32_t)0x00001000U) /!<Capture/Compare 4 Overcapture Flag /
mbed_official	114:fe4fe5cfc3a3	2984
mbed_official	114:fe4fe5cfc3a3	2985	/***************** Bit definition for TIM_EGR register ******************/
mbed_official	114:fe4fe5cfc3a3	2986	#define TIM_EGR_UG ((uint32_t)0x00000001U) /!<Update Generation /
mbed_official	114:fe4fe5cfc3a3	2987	#define TIM_EGR_CC1G ((uint32_t)0x00000002U) /!<Capture/Compare 1 Generation /
mbed_official	114:fe4fe5cfc3a3	2988	#define TIM_EGR_CC2G ((uint32_t)0x00000004U) /!<Capture/Compare 2 Generation /
mbed_official	114:fe4fe5cfc3a3	2989	#define TIM_EGR_CC3G ((uint32_t)0x00000008U) /!<Capture/Compare 3 Generation /
mbed_official	114:fe4fe5cfc3a3	2990	#define TIM_EGR_CC4G ((uint32_t)0x00000010U) /!<Capture/Compare 4 Generation /
mbed_official	114:fe4fe5cfc3a3	2991	#define TIM_EGR_TG ((uint32_t)0x00000040U) /!<Trigger Generation /
mbed_official	114:fe4fe5cfc3a3	2992
mbed_official	114:fe4fe5cfc3a3	2993	/**************** Bit definition for TIM_CCMR1 register *****************/
mbed_official	114:fe4fe5cfc3a3	2994	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
mbed_official	114:fe4fe5cfc3a3	2995	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	2996	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	2997
mbed_official	114:fe4fe5cfc3a3	2998	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /!<Output Compare 1 Fast enable /
mbed_official	114:fe4fe5cfc3a3	2999	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /!<Output Compare 1 Preload enable /
mbed_official	114:fe4fe5cfc3a3	3000
mbed_official	114:fe4fe5cfc3a3	3001	#define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
mbed_official	114:fe4fe5cfc3a3	3002	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3003	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3004	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3005
mbed_official	114:fe4fe5cfc3a3	3006	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /!<Output Compare 1Clear Enable /
mbed_official	114:fe4fe5cfc3a3	3007
mbed_official	114:fe4fe5cfc3a3	3008	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
mbed_official	114:fe4fe5cfc3a3	3009	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3010	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3011
mbed_official	114:fe4fe5cfc3a3	3012	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /!<Output Compare 2 Fast enable /
mbed_official	114:fe4fe5cfc3a3	3013	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /!<Output Compare 2 Preload enable /
mbed_official	114:fe4fe5cfc3a3	3014
mbed_official	114:fe4fe5cfc3a3	3015	#define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
mbed_official	114:fe4fe5cfc3a3	3016	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3017	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3018	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3019
mbed_official	114:fe4fe5cfc3a3	3020	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /!<Output Compare 2 Clear Enable /
mbed_official	114:fe4fe5cfc3a3	3021
mbed_official	114:fe4fe5cfc3a3	3022	/----------------------------------------------------------------------------/
mbed_official	114:fe4fe5cfc3a3	3023
mbed_official	114:fe4fe5cfc3a3	3024	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
mbed_official	114:fe4fe5cfc3a3	3025	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3026	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3027
mbed_official	114:fe4fe5cfc3a3	3028	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
mbed_official	114:fe4fe5cfc3a3	3029	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3030	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3031	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3032	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3033
mbed_official	114:fe4fe5cfc3a3	3034	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
mbed_official	114:fe4fe5cfc3a3	3035	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3036	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3037
mbed_official	114:fe4fe5cfc3a3	3038	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
mbed_official	114:fe4fe5cfc3a3	3039	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3040	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3041	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3042	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3043
mbed_official	114:fe4fe5cfc3a3	3044	/**************** Bit definition for TIM_CCMR2 register *****************/
mbed_official	114:fe4fe5cfc3a3	3045	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
mbed_official	114:fe4fe5cfc3a3	3046	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3047	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3048
mbed_official	114:fe4fe5cfc3a3	3049	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /!<Output Compare 3 Fast enable /
mbed_official	114:fe4fe5cfc3a3	3050	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /!<Output Compare 3 Preload enable /
mbed_official	114:fe4fe5cfc3a3	3051
mbed_official	114:fe4fe5cfc3a3	3052	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
mbed_official	114:fe4fe5cfc3a3	3053	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3054	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3055	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3056
mbed_official	114:fe4fe5cfc3a3	3057	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /!<Output Compare 3 Clear Enable /
mbed_official	114:fe4fe5cfc3a3	3058
mbed_official	114:fe4fe5cfc3a3	3059	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
mbed_official	114:fe4fe5cfc3a3	3060	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3061	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3062
mbed_official	114:fe4fe5cfc3a3	3063	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /!<Output Compare 4 Fast enable /
mbed_official	114:fe4fe5cfc3a3	3064	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /!<Output Compare 4 Preload enable /
mbed_official	114:fe4fe5cfc3a3	3065
mbed_official	114:fe4fe5cfc3a3	3066	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
mbed_official	114:fe4fe5cfc3a3	3067	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3068	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3069	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3070
mbed_official	114:fe4fe5cfc3a3	3071	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /!<Output Compare 4 Clear Enable /
mbed_official	114:fe4fe5cfc3a3	3072
mbed_official	114:fe4fe5cfc3a3	3073	/----------------------------------------------------------------------------/
mbed_official	114:fe4fe5cfc3a3	3074
mbed_official	114:fe4fe5cfc3a3	3075	#define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
mbed_official	114:fe4fe5cfc3a3	3076	#define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3077	#define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3078
mbed_official	114:fe4fe5cfc3a3	3079	#define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
mbed_official	114:fe4fe5cfc3a3	3080	#define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3081	#define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3082	#define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3083	#define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3084
mbed_official	114:fe4fe5cfc3a3	3085	#define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
mbed_official	114:fe4fe5cfc3a3	3086	#define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3087	#define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3088
mbed_official	114:fe4fe5cfc3a3	3089	#define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
mbed_official	114:fe4fe5cfc3a3	3090	#define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3091	#define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3092	#define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3093	#define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3094
mbed_official	114:fe4fe5cfc3a3	3095	/***************** Bit definition for TIM_CCER register *****************/
mbed_official	114:fe4fe5cfc3a3	3096	#define TIM_CCER_CC1E ((uint32_t)0x00000001U) /!<Capture/Compare 1 output enable /
mbed_official	114:fe4fe5cfc3a3	3097	#define TIM_CCER_CC1P ((uint32_t)0x00000002U) /!<Capture/Compare 1 output Polarity /
mbed_official	114:fe4fe5cfc3a3	3098	#define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /!<Capture/Compare 1 Complementary output Polarity /
mbed_official	114:fe4fe5cfc3a3	3099	#define TIM_CCER_CC2E ((uint32_t)0x00000010U) /!<Capture/Compare 2 output enable /
mbed_official	114:fe4fe5cfc3a3	3100	#define TIM_CCER_CC2P ((uint32_t)0x00000020U) /!<Capture/Compare 2 output Polarity /
mbed_official	114:fe4fe5cfc3a3	3101	#define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /!<Capture/Compare 2 Complementary output Polarity /
mbed_official	114:fe4fe5cfc3a3	3102	#define TIM_CCER_CC3E ((uint32_t)0x00000100U) /!<Capture/Compare 3 output enable /
mbed_official	114:fe4fe5cfc3a3	3103	#define TIM_CCER_CC3P ((uint32_t)0x00000200U) /!<Capture/Compare 3 output Polarity /
mbed_official	114:fe4fe5cfc3a3	3104	#define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /!<Capture/Compare 3 Complementary output Polarity /
mbed_official	114:fe4fe5cfc3a3	3105	#define TIM_CCER_CC4E ((uint32_t)0x00001000U) /!<Capture/Compare 4 output enable /
mbed_official	114:fe4fe5cfc3a3	3106	#define TIM_CCER_CC4P ((uint32_t)0x00002000U) /!<Capture/Compare 4 output Polarity /
mbed_official	114:fe4fe5cfc3a3	3107	#define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /!<Capture/Compare 4 Complementary output Polarity /
mbed_official	114:fe4fe5cfc3a3	3108
mbed_official	114:fe4fe5cfc3a3	3109	/***************** Bit definition for TIM_CNT register ******************/
mbed_official	114:fe4fe5cfc3a3	3110	#define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /!<Counter Value /
mbed_official	114:fe4fe5cfc3a3	3111
mbed_official	114:fe4fe5cfc3a3	3112	/***************** Bit definition for TIM_PSC register ******************/
mbed_official	114:fe4fe5cfc3a3	3113	#define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /!<Prescaler Value /
mbed_official	114:fe4fe5cfc3a3	3114
mbed_official	114:fe4fe5cfc3a3	3115	/***************** Bit definition for TIM_ARR register ******************/
mbed_official	114:fe4fe5cfc3a3	3116	#define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /!<actual auto-reload Value /
mbed_official	114:fe4fe5cfc3a3	3117
mbed_official	114:fe4fe5cfc3a3	3118	/***************** Bit definition for TIM_CCR1 register *****************/
mbed_official	114:fe4fe5cfc3a3	3119	#define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 1 Value /
mbed_official	114:fe4fe5cfc3a3	3120
mbed_official	114:fe4fe5cfc3a3	3121	/***************** Bit definition for TIM_CCR2 register *****************/
mbed_official	114:fe4fe5cfc3a3	3122	#define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 2 Value /
mbed_official	114:fe4fe5cfc3a3	3123
mbed_official	114:fe4fe5cfc3a3	3124	/***************** Bit definition for TIM_CCR3 register *****************/
mbed_official	114:fe4fe5cfc3a3	3125	#define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 3 Value /
mbed_official	114:fe4fe5cfc3a3	3126
mbed_official	114:fe4fe5cfc3a3	3127	/***************** Bit definition for TIM_CCR4 register *****************/
mbed_official	114:fe4fe5cfc3a3	3128	#define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /!<Capture/Compare 4 Value /
mbed_official	114:fe4fe5cfc3a3	3129
mbed_official	114:fe4fe5cfc3a3	3130	/***************** Bit definition for TIM_DCR register ******************/
mbed_official	114:fe4fe5cfc3a3	3131	#define TIM_DCR_DBA ((uint32_t)0x0000001FU) /!<DBA[4:0] bits (DMA Base Address) /
mbed_official	114:fe4fe5cfc3a3	3132	#define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3133	#define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3134	#define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3135	#define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3136	#define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /!<Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3137
mbed_official	114:fe4fe5cfc3a3	3138	#define TIM_DCR_DBL ((uint32_t)0x00001F00U) /!<DBL[4:0] bits (DMA Burst Length) /
mbed_official	114:fe4fe5cfc3a3	3139	#define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3140	#define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3141	#define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3142	#define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /!<Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3143	#define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /!<Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3144
mbed_official	114:fe4fe5cfc3a3	3145	/***************** Bit definition for TIM_DMAR register *****************/
mbed_official	114:fe4fe5cfc3a3	3146	#define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /!<DMA register for burst accesses /
mbed_official	114:fe4fe5cfc3a3	3147
mbed_official	114:fe4fe5cfc3a3	3148	/***************** Bit definition for TIM_OR register *******************/
mbed_official	114:fe4fe5cfc3a3	3149	#define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /!<ETR_RMP[1:0] bits (TIM2 ETR remap) /
mbed_official	114:fe4fe5cfc3a3	3150	#define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3151	#define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3152	#define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3153	#define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) /
mbed_official	114:fe4fe5cfc3a3	3154	#define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3155	#define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3156
mbed_official	114:fe4fe5cfc3a3	3157	#define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /!<ETR_RMP[1:0] bits (TIM21 ETR remap) /
mbed_official	114:fe4fe5cfc3a3	3158	#define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3159	#define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3160	#define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) /
mbed_official	114:fe4fe5cfc3a3	3161	#define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3162	#define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3163	#define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /!<Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3164	#define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /!<TI2_RMP bit (TIM21 Input 2 remap) /
mbed_official	114:fe4fe5cfc3a3	3165
mbed_official	114:fe4fe5cfc3a3	3166	#define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /!<ETR_RMP[1:0] bits (TIM22 ETR remap) /
mbed_official	114:fe4fe5cfc3a3	3167	#define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3168	#define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3169	#define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) /
mbed_official	114:fe4fe5cfc3a3	3170	#define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /!<Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3171	#define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /!<Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3172
mbed_official	114:fe4fe5cfc3a3	3173
mbed_official	114:fe4fe5cfc3a3	3174	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3175	/* */
mbed_official	114:fe4fe5cfc3a3	3176	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official	114:fe4fe5cfc3a3	3177	/* */
mbed_official	114:fe4fe5cfc3a3	3178	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3179
mbed_official	114:fe4fe5cfc3a3	3180	/*
mbed_official	114:fe4fe5cfc3a3	3181	* @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
mbed_official	114:fe4fe5cfc3a3	3182	*/
mbed_official	114:fe4fe5cfc3a3	3183	/* Note: No specific macro feature on this device */
mbed_official	114:fe4fe5cfc3a3	3184
mbed_official	114:fe4fe5cfc3a3	3185	/**************** Bit definition for USART_CR1 register *****************/
mbed_official	114:fe4fe5cfc3a3	3186	#define USART_CR1_UE ((uint32_t)0x00000001U) /!< USART Enable /
mbed_official	114:fe4fe5cfc3a3	3187	#define USART_CR1_UESM ((uint32_t)0x00000002U) /!< USART Enable in STOP Mode /
mbed_official	114:fe4fe5cfc3a3	3188	#define USART_CR1_RE ((uint32_t)0x00000004U) /!< Receiver Enable /
mbed_official	114:fe4fe5cfc3a3	3189	#define USART_CR1_TE ((uint32_t)0x00000008U) /!< Transmitter Enable /
mbed_official	114:fe4fe5cfc3a3	3190	#define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /!< IDLE Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3191	#define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /!< RXNE Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3192	#define USART_CR1_TCIE ((uint32_t)0x00000040U) /!< Transmission Complete Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3193	#define USART_CR1_TXEIE ((uint32_t)0x00000080U) /!< TXE Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3194	#define USART_CR1_PEIE ((uint32_t)0x00000100U) /!< PE Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3195	#define USART_CR1_PS ((uint32_t)0x00000200U) /!< Parity Selection /
mbed_official	114:fe4fe5cfc3a3	3196	#define USART_CR1_PCE ((uint32_t)0x00000400U) /!< Parity Control Enable /
mbed_official	114:fe4fe5cfc3a3	3197	#define USART_CR1_WAKE ((uint32_t)0x00000800U) /!< Receiver Wakeup method /
mbed_official	114:fe4fe5cfc3a3	3198	#define USART_CR1_M ((uint32_t)0x10001000U) /!< Word length /
mbed_official	114:fe4fe5cfc3a3	3199	#define USART_CR1_M0 ((uint32_t)0x00001000U) /!< Word length - Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3200	#define USART_CR1_MME ((uint32_t)0x00002000U) /!< Mute Mode Enable /
mbed_official	114:fe4fe5cfc3a3	3201	#define USART_CR1_CMIE ((uint32_t)0x00004000U) /!< Character match interrupt enable /
mbed_official	114:fe4fe5cfc3a3	3202	#define USART_CR1_OVER8 ((uint32_t)0x00008000U) /!< Oversampling by 8-bit or 16-bit mode /
mbed_official	114:fe4fe5cfc3a3	3203	#define USART_CR1_DEDT ((uint32_t)0x001F0000U) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
mbed_official	114:fe4fe5cfc3a3	3204	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3205	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3206	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3207	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3208	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3209	#define USART_CR1_DEAT ((uint32_t)0x03E00000U) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
mbed_official	114:fe4fe5cfc3a3	3210	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3211	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3212	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3213	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3214	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3215	#define USART_CR1_RTOIE ((uint32_t)0x04000000U) /!< Receive Time Out interrupt enable /
mbed_official	114:fe4fe5cfc3a3	3216	#define USART_CR1_EOBIE ((uint32_t)0x08000000U) /!< End of Block interrupt enable /
mbed_official	114:fe4fe5cfc3a3	3217	#define USART_CR1_M1 ((uint32_t)0x10000000U) /!< Word length - Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3218	/**************** Bit definition for USART_CR2 register *****************/
mbed_official	114:fe4fe5cfc3a3	3219	#define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /!< 7-bit or 4-bit Address Detection /
mbed_official	114:fe4fe5cfc3a3	3220	#define USART_CR2_LBDL ((uint32_t)0x00000020U) /!< LIN Break Detection Length /
mbed_official	114:fe4fe5cfc3a3	3221	#define USART_CR2_LBDIE ((uint32_t)0x00000040U) /!< LIN Break Detection Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3222	#define USART_CR2_LBCL ((uint32_t)0x00000100U) /!< Last Bit Clock pulse /
mbed_official	114:fe4fe5cfc3a3	3223	#define USART_CR2_CPHA ((uint32_t)0x00000200U) /!< Clock Phase /
mbed_official	114:fe4fe5cfc3a3	3224	#define USART_CR2_CPOL ((uint32_t)0x00000400U) /!< Clock Polarity /
mbed_official	114:fe4fe5cfc3a3	3225	#define USART_CR2_CLKEN ((uint32_t)0x00000800U) /!< Clock Enable /
mbed_official	114:fe4fe5cfc3a3	3226	#define USART_CR2_STOP ((uint32_t)0x00003000U) /!< STOP[1:0] bits (STOP bits) /
mbed_official	114:fe4fe5cfc3a3	3227	#define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3228	#define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3229	#define USART_CR2_LINEN ((uint32_t)0x00004000U) /!< LIN mode enable /
mbed_official	114:fe4fe5cfc3a3	3230	#define USART_CR2_SWAP ((uint32_t)0x00008000U) /!< SWAP TX/RX pins /
mbed_official	114:fe4fe5cfc3a3	3231	#define USART_CR2_RXINV ((uint32_t)0x00010000U) /!< RX pin active level inversion /
mbed_official	114:fe4fe5cfc3a3	3232	#define USART_CR2_TXINV ((uint32_t)0x00020000U) /!< TX pin active level inversion /
mbed_official	114:fe4fe5cfc3a3	3233	#define USART_CR2_DATAINV ((uint32_t)0x00040000U) /!< Binary data inversion /
mbed_official	114:fe4fe5cfc3a3	3234	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /!< Most Significant Bit First /
mbed_official	114:fe4fe5cfc3a3	3235	#define USART_CR2_ABREN ((uint32_t)0x00100000U) /!< Auto Baud-Rate Enable/
mbed_official	114:fe4fe5cfc3a3	3236	#define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
mbed_official	114:fe4fe5cfc3a3	3237	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3238	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3239	#define USART_CR2_RTOEN ((uint32_t)0x00800000U) /!< Receiver Time-Out enable /
mbed_official	114:fe4fe5cfc3a3	3240	#define USART_CR2_ADD ((uint32_t)0xFF000000U) /!< Address of the USART node /
mbed_official	114:fe4fe5cfc3a3	3241
mbed_official	114:fe4fe5cfc3a3	3242	/**************** Bit definition for USART_CR3 register *****************/
mbed_official	114:fe4fe5cfc3a3	3243	#define USART_CR3_EIE ((uint32_t)0x00000001U) /!< Error Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3244	#define USART_CR3_IREN ((uint32_t)0x00000002U) /!< IrDA mode Enable /
mbed_official	114:fe4fe5cfc3a3	3245	#define USART_CR3_IRLP ((uint32_t)0x00000004U) /!< IrDA Low-Power /
mbed_official	114:fe4fe5cfc3a3	3246	#define USART_CR3_HDSEL ((uint32_t)0x00000008U) /!< Half-Duplex Selection /
mbed_official	114:fe4fe5cfc3a3	3247	#define USART_CR3_NACK ((uint32_t)0x00000010U) /!< SmartCard NACK enable /
mbed_official	114:fe4fe5cfc3a3	3248	#define USART_CR3_SCEN ((uint32_t)0x00000020U) /!< SmartCard mode enable /
mbed_official	114:fe4fe5cfc3a3	3249	#define USART_CR3_DMAR ((uint32_t)0x00000040U) /!< DMA Enable Receiver /
mbed_official	114:fe4fe5cfc3a3	3250	#define USART_CR3_DMAT ((uint32_t)0x00000080U) /!< DMA Enable Transmitter /
mbed_official	114:fe4fe5cfc3a3	3251	#define USART_CR3_RTSE ((uint32_t)0x00000100U) /!< RTS Enable /
mbed_official	114:fe4fe5cfc3a3	3252	#define USART_CR3_CTSE ((uint32_t)0x00000200U) /!< CTS Enable /
mbed_official	114:fe4fe5cfc3a3	3253	#define USART_CR3_CTSIE ((uint32_t)0x00000400U) /!< CTS Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3254	#define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /!< One sample bit method enable /
mbed_official	114:fe4fe5cfc3a3	3255	#define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /!< Overrun Disable /
mbed_official	114:fe4fe5cfc3a3	3256	#define USART_CR3_DDRE ((uint32_t)0x00002000U) /!< DMA Disable on Reception Error /
mbed_official	114:fe4fe5cfc3a3	3257	#define USART_CR3_DEM ((uint32_t)0x00004000U) /!< Driver Enable Mode /
mbed_official	114:fe4fe5cfc3a3	3258	#define USART_CR3_DEP ((uint32_t)0x00008000U) /!< Driver Enable Polarity Selection /
mbed_official	114:fe4fe5cfc3a3	3259	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
mbed_official	114:fe4fe5cfc3a3	3260	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3261	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3262	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3263	#define USART_CR3_WUS ((uint32_t)0x00300000U) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
mbed_official	114:fe4fe5cfc3a3	3264	#define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3265	#define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3266	#define USART_CR3_WUFIE ((uint32_t)0x00400000U) /!< Wake Up Interrupt Enable /
mbed_official	114:fe4fe5cfc3a3	3267	#define USART_CR3_UCESM ((uint32_t)0x00800000U) /!< Clock Enable in Stop mode /
mbed_official	114:fe4fe5cfc3a3	3268
mbed_official	114:fe4fe5cfc3a3	3269	/**************** Bit definition for USART_BRR register *****************/
mbed_official	114:fe4fe5cfc3a3	3270	#define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /!< Fraction of USARTDIV /
mbed_official	114:fe4fe5cfc3a3	3271	#define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /!< Mantissa of USARTDIV /
mbed_official	114:fe4fe5cfc3a3	3272
mbed_official	114:fe4fe5cfc3a3	3273	/**************** Bit definition for USART_GTPR register ****************/
mbed_official	114:fe4fe5cfc3a3	3274	#define USART_GTPR_PSC ((uint32_t)0x000000FFU) /!< PSC[7:0] bits (Prescaler value) /
mbed_official	114:fe4fe5cfc3a3	3275	#define USART_GTPR_GT ((uint32_t)0x0000FF00U) /!< GT[7:0] bits (Guard time value) /
mbed_official	114:fe4fe5cfc3a3	3276
mbed_official	114:fe4fe5cfc3a3	3277
mbed_official	114:fe4fe5cfc3a3	3278	/***************** Bit definition for USART_RTOR register ***************/
mbed_official	114:fe4fe5cfc3a3	3279	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /!< Receiver Time Out Value /
mbed_official	114:fe4fe5cfc3a3	3280	#define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /!< Block Length /
mbed_official	114:fe4fe5cfc3a3	3281
mbed_official	114:fe4fe5cfc3a3	3282	/***************** Bit definition for USART_RQR register ****************/
mbed_official	114:fe4fe5cfc3a3	3283	#define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /!< Auto-Baud Rate Request /
mbed_official	114:fe4fe5cfc3a3	3284	#define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /!< Send Break Request /
mbed_official	114:fe4fe5cfc3a3	3285	#define USART_RQR_MMRQ ((uint32_t)0x00000004U) /!< Mute Mode Request /
mbed_official	114:fe4fe5cfc3a3	3286	#define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /!< Receive Data flush Request /
mbed_official	114:fe4fe5cfc3a3	3287	#define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /!< Transmit data flush Request /
mbed_official	114:fe4fe5cfc3a3	3288
mbed_official	114:fe4fe5cfc3a3	3289	/***************** Bit definition for USART_ISR register ****************/
mbed_official	114:fe4fe5cfc3a3	3290	#define USART_ISR_PE ((uint32_t)0x00000001U) /!< Parity Error /
mbed_official	114:fe4fe5cfc3a3	3291	#define USART_ISR_FE ((uint32_t)0x00000002U) /!< Framing Error /
mbed_official	114:fe4fe5cfc3a3	3292	#define USART_ISR_NE ((uint32_t)0x00000004U) /!< Noise detected Flag /
mbed_official	114:fe4fe5cfc3a3	3293	#define USART_ISR_ORE ((uint32_t)0x00000008U) /!< OverRun Error /
mbed_official	114:fe4fe5cfc3a3	3294	#define USART_ISR_IDLE ((uint32_t)0x00000010U) /!< IDLE line detected /
mbed_official	114:fe4fe5cfc3a3	3295	#define USART_ISR_RXNE ((uint32_t)0x00000020U) /!< Read Data Register Not Empty /
mbed_official	114:fe4fe5cfc3a3	3296	#define USART_ISR_TC ((uint32_t)0x00000040U) /!< Transmission Complete /
mbed_official	114:fe4fe5cfc3a3	3297	#define USART_ISR_TXE ((uint32_t)0x00000080U) /!< Transmit Data Register Empty /
mbed_official	114:fe4fe5cfc3a3	3298	#define USART_ISR_LBDF ((uint32_t)0x00000100U) /!< LIN Break Detection Flag /
mbed_official	114:fe4fe5cfc3a3	3299	#define USART_ISR_CTSIF ((uint32_t)0x00000200U) /!< CTS interrupt flag /
mbed_official	114:fe4fe5cfc3a3	3300	#define USART_ISR_CTS ((uint32_t)0x00000400U) /!< CTS flag /
mbed_official	114:fe4fe5cfc3a3	3301	#define USART_ISR_RTOF ((uint32_t)0x00000800U) /!< Receiver Time Out /
mbed_official	114:fe4fe5cfc3a3	3302	#define USART_ISR_EOBF ((uint32_t)0x00001000U) /!< End Of Block Flag /
mbed_official	114:fe4fe5cfc3a3	3303	#define USART_ISR_ABRE ((uint32_t)0x00004000U) /!< Auto-Baud Rate Error /
mbed_official	114:fe4fe5cfc3a3	3304	#define USART_ISR_ABRF ((uint32_t)0x00008000U) /!< Auto-Baud Rate Flag /
mbed_official	114:fe4fe5cfc3a3	3305	#define USART_ISR_BUSY ((uint32_t)0x00010000U) /!< Busy Flag /
mbed_official	114:fe4fe5cfc3a3	3306	#define USART_ISR_CMF ((uint32_t)0x00020000U) /!< Character Match Flag /
mbed_official	114:fe4fe5cfc3a3	3307	#define USART_ISR_SBKF ((uint32_t)0x00040000U) /!< Send Break Flag /
mbed_official	114:fe4fe5cfc3a3	3308	#define USART_ISR_RWU ((uint32_t)0x00080000U) /!< Receive Wake Up from mute mode Flag /
mbed_official	114:fe4fe5cfc3a3	3309	#define USART_ISR_WUF ((uint32_t)0x00100000U) /!< Wake Up from stop mode Flag /
mbed_official	114:fe4fe5cfc3a3	3310	#define USART_ISR_TEACK ((uint32_t)0x00200000U) /!< Transmit Enable Acknowledge Flag /
mbed_official	114:fe4fe5cfc3a3	3311	#define USART_ISR_REACK ((uint32_t)0x00400000U) /!< Receive Enable Acknowledge Flag /
mbed_official	114:fe4fe5cfc3a3	3312
mbed_official	114:fe4fe5cfc3a3	3313	/***************** Bit definition for USART_ICR register ****************/
mbed_official	114:fe4fe5cfc3a3	3314	#define USART_ICR_PECF ((uint32_t)0x00000001U) /!< Parity Error Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3315	#define USART_ICR_FECF ((uint32_t)0x00000002U) /!< Framing Error Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3316	#define USART_ICR_NCF ((uint32_t)0x00000004U) /!< Noise detected Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3317	#define USART_ICR_ORECF ((uint32_t)0x00000008U) /!< OverRun Error Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3318	#define USART_ICR_IDLECF ((uint32_t)0x00000010U) /!< IDLE line detected Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3319	#define USART_ICR_TCCF ((uint32_t)0x00000040U) /!< Transmission Complete Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3320	#define USART_ICR_LBDCF ((uint32_t)0x00000100U) /!< LIN Break Detection Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3321	#define USART_ICR_CTSCF ((uint32_t)0x00000200U) /!< CTS Interrupt Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3322	#define USART_ICR_RTOCF ((uint32_t)0x00000800U) /!< Receiver Time Out Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3323	#define USART_ICR_EOBCF ((uint32_t)0x00001000U) /!< End Of Block Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3324	#define USART_ICR_CMCF ((uint32_t)0x00020000U) /!< Character Match Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3325	#define USART_ICR_WUCF ((uint32_t)0x00100000U) /!< Wake Up from stop mode Clear Flag /
mbed_official	114:fe4fe5cfc3a3	3326
mbed_official	114:fe4fe5cfc3a3	3327	/***************** Bit definition for USART_RDR register ****************/
mbed_official	114:fe4fe5cfc3a3	3328	#define USART_RDR_RDR ((uint32_t)0x000001FFU) /!< RDR[8:0] bits (Receive Data value) /
mbed_official	114:fe4fe5cfc3a3	3329
mbed_official	114:fe4fe5cfc3a3	3330	/***************** Bit definition for USART_TDR register ****************/
mbed_official	114:fe4fe5cfc3a3	3331	#define USART_TDR_TDR ((uint32_t)0x000001FFU) /!< TDR[8:0] bits (Transmit Data value) /
mbed_official	114:fe4fe5cfc3a3	3332
mbed_official	114:fe4fe5cfc3a3	3333	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3334	/* */
mbed_official	114:fe4fe5cfc3a3	3335	/* Window WATCHDOG (WWDG) */
mbed_official	114:fe4fe5cfc3a3	3336	/* */
mbed_official	114:fe4fe5cfc3a3	3337	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3338
mbed_official	114:fe4fe5cfc3a3	3339	/***************** Bit definition for WWDG_CR register ******************/
mbed_official	114:fe4fe5cfc3a3	3340	#define WWDG_CR_T ((uint32_t)0x0000007FU) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
mbed_official	114:fe4fe5cfc3a3	3341	#define WWDG_CR_T_0 ((uint32_t)0x00000001U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3342	#define WWDG_CR_T_1 ((uint32_t)0x00000002U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3343	#define WWDG_CR_T_2 ((uint32_t)0x00000004U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3344	#define WWDG_CR_T_3 ((uint32_t)0x00000008U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3345	#define WWDG_CR_T_4 ((uint32_t)0x00000010U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3346	#define WWDG_CR_T_5 ((uint32_t)0x00000020U) /!< Bit 5 /
mbed_official	114:fe4fe5cfc3a3	3347	#define WWDG_CR_T_6 ((uint32_t)0x00000040U) /!< Bit 6 /
mbed_official	114:fe4fe5cfc3a3	3348
mbed_official	114:fe4fe5cfc3a3	3349	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	3350	#define WWDG_CR_T0 WWDG_CR_T_0
mbed_official	114:fe4fe5cfc3a3	3351	#define WWDG_CR_T1 WWDG_CR_T_1
mbed_official	114:fe4fe5cfc3a3	3352	#define WWDG_CR_T2 WWDG_CR_T_2
mbed_official	114:fe4fe5cfc3a3	3353	#define WWDG_CR_T3 WWDG_CR_T_3
mbed_official	114:fe4fe5cfc3a3	3354	#define WWDG_CR_T4 WWDG_CR_T_4
mbed_official	114:fe4fe5cfc3a3	3355	#define WWDG_CR_T5 WWDG_CR_T_5
mbed_official	114:fe4fe5cfc3a3	3356	#define WWDG_CR_T6 WWDG_CR_T_6
mbed_official	114:fe4fe5cfc3a3	3357
mbed_official	114:fe4fe5cfc3a3	3358	#define WWDG_CR_WDGA ((uint32_t)0x00000080U) /!< Activation bit /
mbed_official	114:fe4fe5cfc3a3	3359
mbed_official	114:fe4fe5cfc3a3	3360	/***************** Bit definition for WWDG_CFR register *****************/
mbed_official	114:fe4fe5cfc3a3	3361	#define WWDG_CFR_W ((uint32_t)0x0000007FU) /!< W[6:0] bits (7-bit window value) /
mbed_official	114:fe4fe5cfc3a3	3362	#define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3363	#define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3364	#define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /!< Bit 2 /
mbed_official	114:fe4fe5cfc3a3	3365	#define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /!< Bit 3 /
mbed_official	114:fe4fe5cfc3a3	3366	#define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /!< Bit 4 /
mbed_official	114:fe4fe5cfc3a3	3367	#define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /!< Bit 5 /
mbed_official	114:fe4fe5cfc3a3	3368	#define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /!< Bit 6 /
mbed_official	114:fe4fe5cfc3a3	3369
mbed_official	114:fe4fe5cfc3a3	3370	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	3371	#define WWDG_CFR_W0 WWDG_CFR_W_0
mbed_official	114:fe4fe5cfc3a3	3372	#define WWDG_CFR_W1 WWDG_CFR_W_1
mbed_official	114:fe4fe5cfc3a3	3373	#define WWDG_CFR_W2 WWDG_CFR_W_2
mbed_official	114:fe4fe5cfc3a3	3374	#define WWDG_CFR_W3 WWDG_CFR_W_3
mbed_official	114:fe4fe5cfc3a3	3375	#define WWDG_CFR_W4 WWDG_CFR_W_4
mbed_official	114:fe4fe5cfc3a3	3376	#define WWDG_CFR_W5 WWDG_CFR_W_5
mbed_official	114:fe4fe5cfc3a3	3377	#define WWDG_CFR_W6 WWDG_CFR_W_6
mbed_official	114:fe4fe5cfc3a3	3378
mbed_official	114:fe4fe5cfc3a3	3379	#define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /!< WDGTB[1:0] bits (Timer Base) /
mbed_official	114:fe4fe5cfc3a3	3380	#define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /!< Bit 0 /
mbed_official	114:fe4fe5cfc3a3	3381	#define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /!< Bit 1 /
mbed_official	114:fe4fe5cfc3a3	3382
mbed_official	114:fe4fe5cfc3a3	3383	/* Legacy defines */
mbed_official	114:fe4fe5cfc3a3	3384	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
mbed_official	114:fe4fe5cfc3a3	3385	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
mbed_official	114:fe4fe5cfc3a3	3386
mbed_official	114:fe4fe5cfc3a3	3387	#define WWDG_CFR_EWI ((uint32_t)0x00000200U) /!< Early Wakeup Interrupt /
mbed_official	114:fe4fe5cfc3a3	3388
mbed_official	114:fe4fe5cfc3a3	3389	/***************** Bit definition for WWDG_SR register ******************/
mbed_official	114:fe4fe5cfc3a3	3390	#define WWDG_SR_EWIF ((uint32_t)0x00000001U) /!< Early Wakeup Interrupt Flag /
mbed_official	114:fe4fe5cfc3a3	3391
mbed_official	114:fe4fe5cfc3a3	3392	/**
mbed_official	114:fe4fe5cfc3a3	3393	* @}
mbed_official	114:fe4fe5cfc3a3	3394	*/
mbed_official	114:fe4fe5cfc3a3	3395
mbed_official	114:fe4fe5cfc3a3	3396	/**
mbed_official	114:fe4fe5cfc3a3	3397	* @}
mbed_official	114:fe4fe5cfc3a3	3398	*/
mbed_official	114:fe4fe5cfc3a3	3399
mbed_official	114:fe4fe5cfc3a3	3400	/** @addtogroup Exported_macros
mbed_official	114:fe4fe5cfc3a3	3401	* @{
mbed_official	114:fe4fe5cfc3a3	3402	*/
mbed_official	114:fe4fe5cfc3a3	3403
mbed_official	114:fe4fe5cfc3a3	3404	/***************************** ADC Instances ******************************/
mbed_official	114:fe4fe5cfc3a3	3405	#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official	114:fe4fe5cfc3a3	3406
mbed_official	114:fe4fe5cfc3a3	3407	/***************************** COMP Instances *****************************/
mbed_official	114:fe4fe5cfc3a3	3408	#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) \|\| \
mbed_official	114:fe4fe5cfc3a3	3409	((INSTANCE) == COMP2))
mbed_official	114:fe4fe5cfc3a3	3410
mbed_official	114:fe4fe5cfc3a3	3411	#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
mbed_official	114:fe4fe5cfc3a3	3412
mbed_official	114:fe4fe5cfc3a3	3413	/***************************** CRC Instances ******************************/
mbed_official	114:fe4fe5cfc3a3	3414	#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official	114:fe4fe5cfc3a3	3415
mbed_official	114:fe4fe5cfc3a3	3416	/***************************** DMA Instances *******************************/
mbed_official	114:fe4fe5cfc3a3	3417	#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) \|\| \
mbed_official	114:fe4fe5cfc3a3	3418	((INSTANCE) == DMA1_Stream1) \|\| \
mbed_official	114:fe4fe5cfc3a3	3419	((INSTANCE) == DMA1_Stream2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3420	((INSTANCE) == DMA1_Stream3) \|\| \
mbed_official	114:fe4fe5cfc3a3	3421	((INSTANCE) == DMA1_Stream4) \|\| \
mbed_official	114:fe4fe5cfc3a3	3422	((INSTANCE) == DMA1_Stream5) \|\| \
mbed_official	114:fe4fe5cfc3a3	3423	((INSTANCE) == DMA1_Stream6) \|\| \
mbed_official	114:fe4fe5cfc3a3	3424	((INSTANCE) == DMA1_Stream7))
mbed_official	114:fe4fe5cfc3a3	3425
mbed_official	114:fe4fe5cfc3a3	3426	/***************************** GPIO Instances *****************************/
mbed_official	114:fe4fe5cfc3a3	3427	#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	114:fe4fe5cfc3a3	3428	((INSTANCE) == GPIOB) \|\| \
mbed_official	114:fe4fe5cfc3a3	3429	((INSTANCE) == GPIOC) \|\| \
mbed_official	114:fe4fe5cfc3a3	3430	((INSTANCE) == GPIOH))
mbed_official	114:fe4fe5cfc3a3	3431
mbed_official	114:fe4fe5cfc3a3	3432	#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) \|\| \
mbed_official	114:fe4fe5cfc3a3	3433	((INSTANCE) == GPIOB) \|\| \
mbed_official	114:fe4fe5cfc3a3	3434	((INSTANCE) == GPIOC))
mbed_official	114:fe4fe5cfc3a3	3435
mbed_official	114:fe4fe5cfc3a3	3436	/****************************** I2C Instances *****************************/
mbed_official	114:fe4fe5cfc3a3	3437	#define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	114:fe4fe5cfc3a3	3438
mbed_official	114:fe4fe5cfc3a3	3439
mbed_official	114:fe4fe5cfc3a3	3440
mbed_official	114:fe4fe5cfc3a3	3441	/**************************** RTC Instances *******************************/
mbed_official	114:fe4fe5cfc3a3	3442	#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official	114:fe4fe5cfc3a3	3443
mbed_official	114:fe4fe5cfc3a3	3444	/****************************** SMBUS Instances ***************************/
mbed_official	114:fe4fe5cfc3a3	3445	#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official	114:fe4fe5cfc3a3	3446
mbed_official	114:fe4fe5cfc3a3	3447	/****************************** SPI Instances *****************************/
mbed_official	114:fe4fe5cfc3a3	3448	#define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
mbed_official	114:fe4fe5cfc3a3	3449
mbed_official	114:fe4fe5cfc3a3	3450	/**************** LPTIM Instances : All supported instances ***************/
mbed_official	114:fe4fe5cfc3a3	3451	#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
mbed_official	114:fe4fe5cfc3a3	3452
mbed_official	114:fe4fe5cfc3a3	3453	/**************** TIM Instances : All supported instances *****************/
mbed_official	114:fe4fe5cfc3a3	3454	#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3455	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3456	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3457
mbed_official	114:fe4fe5cfc3a3	3458	/**************** TIM Instances : supporting counting mode selection ******/
mbed_official	114:fe4fe5cfc3a3	3459	#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3460	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3461	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3462
mbed_official	114:fe4fe5cfc3a3	3463	/**************** TIM Instances : supporting clock division ***************/
mbed_official	114:fe4fe5cfc3a3	3464	#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3465	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3466	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3467
mbed_official	114:fe4fe5cfc3a3	3468	/**** TIM Instances : supporting external clock mode 1 for ETRF input *****/
mbed_official	114:fe4fe5cfc3a3	3469	#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3470	((INSTANCE) == TIM21))
mbed_official	114:fe4fe5cfc3a3	3471
mbed_official	114:fe4fe5cfc3a3	3472	/**** TIM Instances : supporting external clock mode 2 for ETRF input *****/
mbed_official	114:fe4fe5cfc3a3	3473
mbed_official	114:fe4fe5cfc3a3	3474	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official	114:fe4fe5cfc3a3	3475	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3476	((INSTANCE) == TIM21))
mbed_official	114:fe4fe5cfc3a3	3477
mbed_official	114:fe4fe5cfc3a3	3478	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
mbed_official	114:fe4fe5cfc3a3	3479	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3480	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3481	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3482
mbed_official	114:fe4fe5cfc3a3	3483	/*********** TIM Instances : at least 1 capture/compare channel ***********/
mbed_official	114:fe4fe5cfc3a3	3484	#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3485	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3486	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3487
mbed_official	114:fe4fe5cfc3a3	3488	/********** TIM Instances : at least 2 capture/compare channels ***********/
mbed_official	114:fe4fe5cfc3a3	3489	#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3490	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3491	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3492
mbed_official	114:fe4fe5cfc3a3	3493	/********** TIM Instances : at least 3 capture/compare channels ***********/
mbed_official	114:fe4fe5cfc3a3	3494	#define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3495
mbed_official	114:fe4fe5cfc3a3	3496	/********** TIM Instances : at least 4 capture/compare channels ***********/
mbed_official	114:fe4fe5cfc3a3	3497	#define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3498
mbed_official	114:fe4fe5cfc3a3	3499	/****************** TIM Instances : Advanced-control timers ***************/
mbed_official	114:fe4fe5cfc3a3	3500
mbed_official	114:fe4fe5cfc3a3	3501	/***************** TIM Instances : Timer input XOR function ***************/
mbed_official	114:fe4fe5cfc3a3	3502	#define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3503
mbed_official	114:fe4fe5cfc3a3	3504	/**************** TIM Instances : DMA requests generation (UDE) ***********/
mbed_official	114:fe4fe5cfc3a3	3505	#define IS_TIM_DMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3506
mbed_official	114:fe4fe5cfc3a3	3507	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
mbed_official	114:fe4fe5cfc3a3	3508	#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3509
mbed_official	114:fe4fe5cfc3a3	3510	/********** TIM Instances : DMA requests generation (COMDE) ***************/
mbed_official	114:fe4fe5cfc3a3	3511	#define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3512
mbed_official	114:fe4fe5cfc3a3	3513	/****************** TIM Instances : DMA burst feature *********************/
mbed_official	114:fe4fe5cfc3a3	3514	#define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3515
mbed_official	114:fe4fe5cfc3a3	3516	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
mbed_official	114:fe4fe5cfc3a3	3517	#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3518	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3519	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3520
mbed_official	114:fe4fe5cfc3a3	3521	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
mbed_official	114:fe4fe5cfc3a3	3522	#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3523	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3524	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3525
mbed_official	114:fe4fe5cfc3a3	3526	/******************** TIM Instances : 32 bit Counter **********************/
mbed_official	114:fe4fe5cfc3a3	3527
mbed_official	114:fe4fe5cfc3a3	3528	/*************** TIM Instances : external trigger input availabe **********/
mbed_official	114:fe4fe5cfc3a3	3529	#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3530	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3531	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3532
mbed_official	114:fe4fe5cfc3a3	3533	/**************** TIM Instances : remapping capability ********************/
mbed_official	114:fe4fe5cfc3a3	3534	#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3535	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3536	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3537
mbed_official	114:fe4fe5cfc3a3	3538	/**************** TIM Instances : supporting encoder interface ************/
mbed_official	114:fe4fe5cfc3a3	3539	#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3540	((INSTANCE) == TIM21) \|\| \
mbed_official	114:fe4fe5cfc3a3	3541	((INSTANCE) == TIM22))
mbed_official	114:fe4fe5cfc3a3	3542
mbed_official	114:fe4fe5cfc3a3	3543	/***************** TIM Instances : output(s) OCXEC register ***************/
mbed_official	114:fe4fe5cfc3a3	3544	#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
mbed_official	114:fe4fe5cfc3a3	3545
mbed_official	114:fe4fe5cfc3a3	3546	/***************** TIM Instances : output(s) available ********************/
mbed_official	114:fe4fe5cfc3a3	3547	#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official	114:fe4fe5cfc3a3	3548	((((INSTANCE) == TIM2) && \
mbed_official	114:fe4fe5cfc3a3	3549	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	114:fe4fe5cfc3a3	3550	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3551	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	114:fe4fe5cfc3a3	3552	((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official	114:fe4fe5cfc3a3	3553	\|\| \
mbed_official	114:fe4fe5cfc3a3	3554	(((INSTANCE) == TIM21) && \
mbed_official	114:fe4fe5cfc3a3	3555	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	114:fe4fe5cfc3a3	3556	((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official	114:fe4fe5cfc3a3	3557	\|\| \
mbed_official	114:fe4fe5cfc3a3	3558	(((INSTANCE) == TIM22) && \
mbed_official	114:fe4fe5cfc3a3	3559	(((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	114:fe4fe5cfc3a3	3560	((CHANNEL) == TIM_CHANNEL_2))))
mbed_official	114:fe4fe5cfc3a3	3561
mbed_official	114:fe4fe5cfc3a3	3562	/****************** UART Instances : Asynchronous mode ********************/
mbed_official	114:fe4fe5cfc3a3	3563	#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3564	((INSTANCE) == LPUART1))
mbed_official	114:fe4fe5cfc3a3	3565
mbed_official	114:fe4fe5cfc3a3	3566	/****************** USART Instances : Synchronous mode ********************/
mbed_official	114:fe4fe5cfc3a3	3567	#define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official	114:fe4fe5cfc3a3	3568
mbed_official	114:fe4fe5cfc3a3	3569	/**************** USART Instances : Auto Baud Rate detection **************/
mbed_official	114:fe4fe5cfc3a3	3570
mbed_official	114:fe4fe5cfc3a3	3571	#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official	114:fe4fe5cfc3a3	3572
mbed_official	114:fe4fe5cfc3a3	3573	/****************** UART Instances : Half-Duplex mode ********************/
mbed_official	114:fe4fe5cfc3a3	3574	#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3575	((INSTANCE) == LPUART1))
mbed_official	114:fe4fe5cfc3a3	3576
mbed_official	114:fe4fe5cfc3a3	3577	/****************** UART Instances : LIN mode ********************/
mbed_official	114:fe4fe5cfc3a3	3578	#define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official	114:fe4fe5cfc3a3	3579
mbed_official	114:fe4fe5cfc3a3	3580	/****************** UART Instances : Wake-up from Stop mode ********************/
mbed_official	114:fe4fe5cfc3a3	3581	#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3582	((INSTANCE) == LPUART1))
mbed_official	114:fe4fe5cfc3a3	3583	/**************** UART Instances : Hardware Flow control ******************/
mbed_official	114:fe4fe5cfc3a3	3584	#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART2) \|\| \
mbed_official	114:fe4fe5cfc3a3	3585	((INSTANCE) == LPUART1))
mbed_official	114:fe4fe5cfc3a3	3586
mbed_official	114:fe4fe5cfc3a3	3587	/******************* UART Instances : Smard card mode *********************/
mbed_official	114:fe4fe5cfc3a3	3588	#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official	114:fe4fe5cfc3a3	3589
mbed_official	114:fe4fe5cfc3a3	3590	/********************* UART Instances : IRDA mode *************************/
mbed_official	114:fe4fe5cfc3a3	3591	#define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART2)
mbed_official	114:fe4fe5cfc3a3	3592
mbed_official	114:fe4fe5cfc3a3	3593	/**************************** IWDG Instances ******************************/
mbed_official	114:fe4fe5cfc3a3	3594	#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official	114:fe4fe5cfc3a3	3595
mbed_official	114:fe4fe5cfc3a3	3596	/**************************** WWDG Instances ******************************/
mbed_official	114:fe4fe5cfc3a3	3597	#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official	114:fe4fe5cfc3a3	3598
mbed_official	114:fe4fe5cfc3a3	3599	/**
mbed_official	114:fe4fe5cfc3a3	3600	* @}
mbed_official	114:fe4fe5cfc3a3	3601	*/
mbed_official	114:fe4fe5cfc3a3	3602
mbed_official	114:fe4fe5cfc3a3	3603	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3604	/* For a painless codes migration between the STM32L0xx device product */
mbed_official	114:fe4fe5cfc3a3	3605	/* lines, the aliases defined below are put in place to overcome the */
mbed_official	114:fe4fe5cfc3a3	3606	/* differences in the interrupt handlers and IRQn definitions. */
mbed_official	114:fe4fe5cfc3a3	3607	/* No need to update developed interrupt code when moving across */
mbed_official	114:fe4fe5cfc3a3	3608	/* product lines within the same STM32L0 Family */
mbed_official	114:fe4fe5cfc3a3	3609	/******************************************************************************/
mbed_official	114:fe4fe5cfc3a3	3610
mbed_official	114:fe4fe5cfc3a3	3611	/* Aliases for __IRQn */
mbed_official	114:fe4fe5cfc3a3	3612
mbed_official	114:fe4fe5cfc3a3	3613	#define RNG_LPUART1_IRQn LPUART1_IRQn
mbed_official	114:fe4fe5cfc3a3	3614	#define AES_LPUART1_IRQn LPUART1_IRQn
mbed_official	114:fe4fe5cfc3a3	3615	#define AES_RNG_LPUART1_IRQn LPUART1_IRQn
mbed_official	114:fe4fe5cfc3a3	3616	#define RCC_CRS_IRQn RCC_IRQn
mbed_official	114:fe4fe5cfc3a3	3617
mbed_official	114:fe4fe5cfc3a3	3618	/* Aliases for __IRQHandler */
mbed_official	114:fe4fe5cfc3a3	3619	#define RNG_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official	114:fe4fe5cfc3a3	3620	#define AES_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official	114:fe4fe5cfc3a3	3621	#define AES_RNG_LPUART1_IRQHandler LPUART1_IRQHandler
mbed_official	114:fe4fe5cfc3a3	3622	#define TIM6_DAC_IRQHandler TIM6_IRQHandler
mbed_official	114:fe4fe5cfc3a3	3623	#define RCC_CRS_IRQHandler RCC_IRQHandler
mbed_official	114:fe4fe5cfc3a3	3624
mbed_official	114:fe4fe5cfc3a3	3625	/**
mbed_official	114:fe4fe5cfc3a3	3626	* @}
mbed_official	114:fe4fe5cfc3a3	3627	*/
mbed_official	114:fe4fe5cfc3a3	3628
mbed_official	114:fe4fe5cfc3a3	3629	/**
mbed_official	114:fe4fe5cfc3a3	3630	* @}
mbed_official	114:fe4fe5cfc3a3	3631	*/
mbed_official	114:fe4fe5cfc3a3	3632
mbed_official	114:fe4fe5cfc3a3	3633	#ifdef __cplusplus
mbed_official	114:fe4fe5cfc3a3	3634	}
mbed_official	114:fe4fe5cfc3a3	3635	#endif /* __cplusplus */
mbed_official	114:fe4fe5cfc3a3	3636
mbed_official	114:fe4fe5cfc3a3	3637	#endif /* __STM32L031xx_H */
mbed_official	114:fe4fe5cfc3a3	3638
mbed_official	114:fe4fe5cfc3a3	3639
mbed_official	114:fe4fe5cfc3a3	3640
mbed_official	114:fe4fe5cfc3a3	3641	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/